Hydraulisch betätigbare Fahrzeugbremse

Die Erfindung betrifft eine Fahrzeugbremse und ein Verfahren zum Betätigen einer derartigen Fahrzeugbremse. Die erfindungsgemäße Fahrzeugbremse ist ausgeführt mit einem Gehäuse (12; 12a), einem in dem Gehäuse (12; 12a) aufgenommenen Bremskolben (14; 14a), der mit einem Bremsbelag (18; 18a) gekoppelt ist, und einer Blockiereinrichtung zum Arretieren des Bremskolbens (14; 14a) innerhalb des Gehäuses (12; 12a), wobei der Bremskolben (14; 14a) mit dem Gehäuse (12; 12a) eine erste Fluidkammer (24; 24a) begrenzt, die mit Hydraulikfluid beschickbar ist, so dass der Bremskolben (14; 14a) zum Betätigen der Fahrzeugbremse (10; 10a) hydraulisch innerhalb des Gehäuses (12; 12a) entlang einer Kolbenlängsachse (A) verlagerbar ist, wobei die Blockiereinrichtung ein Blockierelement (54; 54a) aufweist, das zum Arretieren des Bremskolbens (14; 14a) innerhalb des Gehäuses (12; 12a) verlagerbar ist. Zur einfachen vollhydraulischen Realisierung einer Feststellbremsfunktion ist erfindungsgemäß vorgesehen, dass ...

Semiconductor integrated circuit and system lsi

Method and apparatus for parameter adjustment, testing, and configuration

A method and apparatus for parameter adjustment, testing and configuration pertaining to the testing of devices is disclosed. The method and apparatus allows tuning the interaction of components in a system for best performance, modifying the operation of components in a system, and monitoring changes in parameters which may predict degradation or failure. The method and apparatus may operate at the device, interface or system level. Through serial data chains, systems may be made to perform under selected or imposed operating conditions to allow configuration, testing, measuring or monitoring.

Methods and apparatus that selectively use or bypass a remote pin electronics block to test at least one device under test

SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THE SAME

METHOD FOR TESTING AN INTEGRATED CIRCUIT

TEST MODE CONTROL CIRCUIT FOR RECONFIGURING A DEVICE PIN OF AN INTEGRATED CIRCUIT CHIP

A test mode control circuit for reconfiguring a device pin of an integrated circuit chip which is initially configured in a test mode includes an input register for applying trim/configuring data to one or more components on an integrated circuit chip; a device pin; an output register for receiving output data from an integrated circuit on an integrated circuit chip which integrated circuit has had one or more of its elements trimmed/reconfigured; an I/O logic circuit for controlling the device pin to operate as a test pin to selectively deliver the trim/configuring data to the input register and receive output data form the output register; a programmable ray including a plurality of logic state elements for permanently mapping a selected set of the trim/configuring data from the input register, the programmable array including a test bit; and a switching system for applying the trim/configuring data to the one or more components on the integrated circuit when the test bit is in a first ...

Parallel scan paths with stimulus and header data circuitry

Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.

OPTIMIZED JTAG INTERFACE

METHOD FOR REALIZING PINS TIME SHARE MULTIPLEXING AND A SYSTEM-ON-A-CHIP

A method for using pins in different mode during different time is provided. The method is able to make at least one pin of a SOC be used in a first interface mode or a second interface mode during different time; wherein the SOC comprises a first interface circuit, a first pin, a second interface circuit, and a second pin; the first interface circuit comprises a first bidirectional PAD unit, a first signal interface unit of the first interface mode and a interface unit of the second interface mode; the second interface circuit comprises a second bidirectional PAD unit, a second signal interface unit of the first interface mode. The method comprises: selecting the output of the first signal interface unit or the output of the interface unit of the second interface mode to be connected with the first pin through the first bidirectional PAD unit during different time.

Verfahren zum Testen eines integrierten Schaltkreises

Es werden ein Verfahren zum Testen eines integrierten Schaltkreises (100) und ein integrierter Schaltkreis (100) vorgestellt. Der integrierte Schaltkreis (100) weist eine interne Teststruktur, auf die über einen internen Testzugangsanschluss (106) zugegriffen werden kann, und einen Steuerbus (110), der über Steueranschlüsse (108) nach außen geführt ist, auf, wobei zwischen einem Fahrbetrieb und einem Testbetrieb umgeschaltet werden kann, so dass im Testbetrieb über die Steueranschlüsse (108) und den Steuerbus (110) ein Zugriff auf den Testzugangsanschluss (106) und damit ein Testen des integrierten Schaltkreises (100) erfolgt.

Reconfiguring debug circuitry

LATCH CIRCUIT INCLUDING A DATA RETENTION LATCH

A latch circuit (2) is described including a function path latch (4, 6), which may be in the form of a standard flip-flop, together with a data retention latch (12, 14). The reset signal preset and the scan enable signal SE are used to control these latches to perform reset, scan, save and restore functions. The save and restore functions serve to save a data value dv from the functional path latch (4, 6) into the data retention latch (12, 14) and restore this value such that the functional path latch can be powered down without a loss of data. © KIPO & WIPO 2007 ...

Bypassing an encoded latch on a chip during a test-pattern scan

Aspects include techniques for bypassing an encoded latch on a chip during a test-pattern scan and using on-chip circuitry to generate a desired encoded pattern, which is inserted into a scan-bypassed latch, to test the on-chip circuitry for defects. A computer-implemented method may include applying a global control bit to the chip; initializing a scan of the chip while bypassing the encoded latch; and applying an extra scan clock to initiate the encoded latch after completing the scan, wherein the encoded latch is updated with check bits generated by the on-chip circuitry.

Semiconductor device and evaluation circuit for the same

An evaluation circuit includes an evaluation pad and a first inverter circuit connected to a first measurement point and a second measurement point to be jointed to first and second power sources, respectively. The first inverter circuit is initialized by an initialization signal from the evaluation pad. The first inverter circuit selectively outputs electric potentials of the first and the second measurement points to the evaluation pad. The circuit further includes a second inverter circuit which has an input connected to the evaluation pad and an output connected to the first inverter circuit. The first and the second inverter circuits are connected in the form of a loop. According to the present invention, the number of evaluation pads can be reduced.

Mixed-signal core design for concurrent testing of mixed-signal, analog, and digital components

A mixed-signal core disclosed herein is designed for efficient concurrent testing analog, mixed-signal, and digital components. One tester may test all components and, thereby, reduce test time without losing full test coverage. An analog module includes all the analog and mixed-signal components of the mixed-signal core, while a first digital module includes digital components required for functional/parametric verification of the mixed-signal components within the analog module. A first virtual boundary connects the analog and the first digital modules to gate the signal transfer during testing. A second digital module includes the remaining digital components of the mixed-signal core, whereby a second virtual boundary separates it from the first digital module. This type of partitioning enables the mixed-signal core to have three modes of operation, wherein the first mode of operation provides digital interface characterization testing of the first and second digital module and analog ...

Programmable test compression architecture input/output shift register coupled to SCI/SCO/PCO

The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.

SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS

Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.

PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGISTER COUPLED TO SCI/SCO/PCO

The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.

Test interface circuit and semiconductor integrated circuit device including the same

In a test interface circuit arranged between an embedded memory and a test data input/output (I/O) terminal, a first-in first-out circuit for successively storing test data is arranged for controlling a latency of data read from the embedded memory. The test interface circuit for the embedded memory can reduce the number of test data I/O terminals, and can increase the executable test patterns.

REDUCED SIGNALING INTERFACE METHOD & APPARATUS

This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

SELF-REPAIRABLE SEMICONDUCTOR AND ITS METHOD

PROBLEM TO BE SOLVED: To provide a self-repairable semiconductor equipped with multi function units. SOLUTION: The self-repairable semiconductor is equipped with multi function units which perform the same function and have an auxiliary function unit. The semiconductor is equipped with one or more perfect or partial spare function units, when a defect of the auxiliary function unit which is accumulated to form the semiconductor is detected, its auxiliary function unit is changed so as to be replaced with an auxiliary function unit in a perfect or partial spare function unit. The reconfiguration is realized by a switching device related to the auxiliary function unit. The defective function unit or auxiliary function unit may be periodically detected in operation and/or may be detected manually while a power source is connected after assembling. COPYRIGHT: (C)2005,JPO&NCIPI ...

Verfahren zum Testen einer zu testenden Schaltungseinheit mit Auskopplung von Verifikationssignalen und Testvorrichtung zur Durchführung des Verfahrens

Die Erfindung schafft eine Testvorrichtung zum Testen einer zu testenden Schaltungseinheit (101) mit einer Sockeleinheit (102) zum Aufnehmen der zu testenden Schaltungseinheit (101) und zur Kontaktierung von Kontaktierungseinheiten (103) der zu testenden Schaltungseinheit (101), einem Testsystem (201) zur Erzeugung von Solldaten (203), die der zu testenden Schaltungseinheit (101) zugeführt werden, und zur Analyse von aus der zu testenden Schaltungseinheit (101) in Abhängigkeit von den dieser zugeführten Solldaten (203) ausgegebenen Istdaten (204) und einem aus mehreren Leitungen bestehenden Testerkanal (202) zur elektrischen Verbindung des Testsystems (201) mit in der Sockeleinheit (102) angebrachten Anschlussstiften (104) zum Anschließen der zu testenden Schaltungseinheit (101) und zur Kommunikation von Solldaten (203) und Istdaten (204) zwischen dem Testsystem (201) und der zu testenden Schaltungseinheit (101). Eine Signalauskopplungseinheit (401) dient einer Auskopplung von Verifikationssignalen ...

Diagnostic mode switching

Reconfiguring debug circuitry

A method of reconfiguring a current debug configuration of a debug unit connected to a peripheral circuit on an integrated circuit chip comprises the debug unit collecting 601 debug data of the peripheral circuit and outputting 602 the debug data in a message stream. The debug unit receives a debug reconfiguration command 603 and in response transmits an indication of the current debug configuration 606, before reconfiguring 607 the debug configuration to a new debug configuration in accordance with the debug reconfiguration command. The debug unit then transmits an indication of the new debug configuration 609. The indication of the current debug configuration 606 and the indication of the new debug configuration 609 are transmitted adjacent to the debug data 604, 610 in the message stream. The method is used for reconfiguring a debug unit associated with e.g. a processor in a system on chip (SoC) integrated circuit.

STRUCTURED INTEGRATION CIRCUIT ELEMENT

Test mode control circuit for reconfiguring a device pin of an integrated circuit chip

SEMICONDUCTOR INTEGRATED CIRCUIT WITH FUNCTIONSL MODES

LOW COST TEST FOR IC'S OR ELECTRICAL MODULES USING STANDARD RECONFIGURABLE LOGIC DEVICES

Low cost test for Integrated Circuits or electrical modules using a reconfigurable logic device is described. In one embodiment, the invention includes configuring a reconfigurable logic device to comply with input standards of a device under test, applying test signals to the device under test, detecting output results of the device under test, and analyzing the detected output results.

Enhanced boundary-scan method and apparatus providing tester channel reduction

An integrated circuit or other electronic circuitry is tested by arranging device pins into multiple-pin groups, and permitting the device pins of the group to share a single tester channel of a piece of test equipment. More particularly, a group comprising a plurality of device pins of the electronic circuitry is designated, and assigned to one of a plurality of tester channels in the test equipment. A test may then be performed on the electronic circuitry, via the assigned tester channel, utilizing at least a subset of the device pins in the designated multiple-pin group. Advantageously, the invention allows high pin count integrated circuits to be tested using inexpensive test equipment platforms.

SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS

Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.

Test card for multiple functions testing

The present invention provides a test card for multiple functions testing. The test card includes a host of media devices, all of which reside on a single printed circuit board; and a selection device which selects each one of the host of media devices for testing. The test card can test all SD, MMC, MS (Pro), SMC devices and functions in one time in a bench without inserting and removing the media devices, thus accelerates the production line test speed.

PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGISTER COUPLED TO SCI/SCO/PCO

The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.

TESTING A BOARD ASSEMBLY USING TEST CARDS

A testing arrangement is provided which comprises: a board assembly comprising (i) a first connector configured to receive a first component while the board assembly is to operate in a regular mode of operation and (ii) a second connector configured to receive a second component while the board assembly is to operate in the regular mode of operation; a first test card configured to be attached to the first connector while the board assembly is to operate in a test mode of operation; and a second test card configured to be attached to the second connector while the board assembly is to operate in the test mode of operation, wherein while the board assembly is to operate in the test mode of operation, the first test card is configured to communicate with the second test card to facilitate testing of the board assembly.

REDUCED SIGNALING INTERFACE METHOD & APPARATUS

This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

遠隔ピンエレクトロニクスブロックの使用又は回避を選択的に行い、少なくとも1つの被試験デバイスを試験する方法及び装置

... 一実施形態では、少なくとも1つの被試験デバイス(DUT)を試験する装置は、試験装置の入力/出力(I/O)ノード、DUTのI/Oノード、遠隔ピンエレクトロニクスブロック、バイパス回路、及び制御システムを含む。遠隔ピンエレクトロニクスブロックは試験機能を提供し、試験装置のI/OノードとDUTのI/Oノードとの間に連結される。試験装置のI/OノードとDUTのI/Oノードとの間にバイパス回路を連結し、試験装置のI/OノードとDUTのI/Oノードとの間に信号バイパス経路を提供する。信号バイパス経路は遠隔ピンエレクトロニクスブロックの提供する試験機能を回避する。バイパス回路を有効及び無効にするよう制御システムを構成する。これに関連した装置及びその他の関連した装置を使用して1つ以上のDUTを試験する方法も開示する。 【選択図】図1 ...

Method and apparatus for test time reduction

TEST CIRCUIT AND A METHOD OF CONTROLLING THE SAME, CAPABLE OF REDUCING THE NUMBER OF A TESTER INPUT/OUTPUT PIN IN READING

PURPOSE: A test circuit and a method of controlling the same are provided to reduce a test time by increasing the number of a semiconductor integrated circuit which is connected serially. CONSTITUTION: A clock control signal generator(100) outputs a first and a second clock control signal(DMU_CT, DML_CT) according to an upper data masking signal, a lower data masking signal, a read enable signal, and a test mode signal. A DLL clock signal generation unit(200) outputs an upper data clock signal and a lower data clock signal in response to the first clock and a second clock signal. A data strobe signal generation unit(300) generates an upper data strobe signal and a lower data strobe signal in response to the upper and lower data clock signal. © KIPO 2009 ...

ELECTRONIC DEVICE HAVING AN INTERFACE SUPPORTED TESTING MODE

A system is provided for testing a first integrated circuit chip associated with at least a second integrated circuit chip in a semiconductor device, wherein at least some external terminals for the semiconductor device are to be shared by the first and second integrated circuit chips, and wherein the first integrated circuit chip is designed for normal operation and a test mode. The system includes a plurality of multiplexer circuits. Each multiplexer circuit is operable to receive a respective signal from the second integrated circuit chip when the first integrated circuit chip is in normal operation. Each multiplexer circuit is further operable to receive a respective signal from either the second integrated circuit chip or an associated external terminal when the first integrated circuit chip is in test mode. An external terminal of the semiconductor device operable to receive a signal for causing the first integrated circuit chip to transition between normal operation and the test ...

DUAL MODE TEST ACCESS PORT METHOD AND APPARATUS

Connection circuitry couples scan test port (STP) circuitry to test access port (TAP) circuitry. The connection circuitry has inputs connected to scan circuitry control output leads from the TAP circuitry, a select input lead, and a clock input lead. The connection circuitry has outputs connected to a scan enable (SE) input lead, a capture select (CS) input lead, and the scan clock (CK) input lead of the STP circuitry. The connection circuitry includes a multiplexer having a control input connected with a clock select lead from the TAP circuitry, an input connected with a functional clock lead, an input connected with the clock input lead, an input connected with a Clock-DR lead from the TAP circuitry, an OFF lead, and an output connected with the scan clock input lead.

Data processing device, signal processing device, and interface device

In a data processing device, a processor processes data based on a stored program and a buffer manager accesses the data. The data processing device includes a program memory which stores program codes, the program codes being loaded into the program memory and executed by the processor when processing the data. A shared memory stores one of the program codes and the data. A control unit selectively connects one of the processor and the buffer manager to the shared memory based on a select pattern, wherein the shared memory functions to store the program codes when the select pattern is set in a first condition, and the shared memory functions to store the data when the select pattern is set in a second condition.

APPARATUS, METHOD, AND STORAGE MEDIUM

Provided is an apparatus including a generating section that generates an altered test candidate obtained by adding an alteration shortening an execution time of a test to a target test for testing a device under test; a test processing section that causes a test apparatus to perform the altered test candidate on the device under test; and a comparing section that compares an altered test result of the device under test resulting from the altered test candidate to a target test result of the device under test resulting from the target test; and a judging section that judges whether the target test can be replaced by the altered test candidate, based on the comparison result of the comparing section.

TEST APPARATUS AND TEST METHOD TO A MEMORY DEVICE

A test system is disclosed. The test system includes a tester, a first voltage stabilization circuit, and a device under test (DUT). The tester generates a first operational voltage and a control signal. The first voltage stabilization circuit transmits a second operational voltage, associated with the first operational voltage, to a socket board. The DUT operates with the second operational voltage received through the socket board. The first voltage stabilization circuit is further configured to control, according to the control signal, the second operational voltage to have a first voltage level when the DUT is operating.

INTEGRATED CIRCUIT WITH SCAN CHAIN AND CHIP TESTING METHOD

Halbleiterbauelement, Testsystem und ODT-Testverfahren

Halbleiterbauelement mit- einer Abschlussimpedanzsteuerschaltung (1200), die konfiguriert ist, in Reaktion auf einen Testmodusbefehl (CMD) ein Abschlussimpedanzsteuersignal (ICONPi, ICONNi) zu erzeugen,- einer On-Die-Termination(ODT)-Schaltung (1100), die mit einer Mehrzahl von Anschlüssen gekoppelt ist und konfiguriert ist, eine Mehrzahl von Abschlussimpedanzen (ODT01 bis ODT0m) zu erzeugen, und- einer Grenzpfadabtastschaltung (1300), die miteinander kaskadiert verschaltete Grenzpfadabtastregister (1310, 1320, 1330) umfasst, wobei die Grenzflächenabtastregister jeweils die Abschlussimpedanzen speichern, um die Abschlussimpedanzen durch einen Schiebevorgang sequentiell auszugeben,- wobei die Abschlussimpedanzen sequentiell über einen einzigen Pin ausgegeben werden.

Integrated circuit using signal interface for communicating a diagnostic signal within a multi-bit value of a functional signal

An integrated circuit 1700 includes a functional circuit 1720, which processes a functional signal comprising at least one multi-bit value, and a diagnostic circuit 1722, which processes a diagnostic signal. The integrated circuit additionally comprises a signal interface controller 1730 to control selective communication of the diagnostic signal and the functional signal across a signal interface, where at least one bit of the multi-bit value contained within the functional signal is replaced by data of the diagnostic signal. The replaced bit may be a low-order bit of the value, and the signal interface controller may additionally perform timedivision multiplexing. This reduces the number of interface connections required on the integrated circuit, minimising system complexity and reducing material requirements.

Reconfiguring debug circuitry

INTEGRATED CIRCUIT TESTER ON A SILICON WAFER AND INTEGRATED CIRCUIT.

A system for verifying operations of system LSI

The multiplexing processor multiplexes internal signals of the system LSI to be verified, at a clock rate higher than that of the internal bus lines, so as to make a multiplexed internal signal to be output. Thus, internal signals on target bus lines can be taken out of the system LSI using a small number of signal lines. Therefore, without considerably increasing the number of output terminals of the system LSI, the internal signals can be taken out through the necessary smallest number of additional output terminals. This can realize an easy verifying process for the whole operation of the system LSI without the need of a complicated design of the system LSI and an increase in cost of the system LSI.

REDUCED PIN COUNT SCAN CHAIN IMPLEMENTATION

The synchronous logic device with reduced pin count scan chain includes: more than two flip/flops (SDC0, SDC1, SDC2) coupled to form a shift register for receiving a scan data input signal (ScanDataIn); a combinational logic circuit (20) for receiving device inputs, generating flip/flop inputs for the more than two flip/flops, and generating an output signal; a first multiplexer (MUX10) for providing a clock signal to the more than two flip/flops during a test mode; a second multiplexer (MUX12) for selecting between a test mode output from the shift register and the output signal from the combinational logic circuit (20), and for providing a scan data output signal (ScanDataOut). In one embodiment, the scan data input signal and the scan data output signal share an input/output pin.

CORE CIRCUIT TEST ARCHITECTURE

An integrated circuit includes combinational logic with flip-flops, parallel scan paths with a scan input for receiving test stimulus data to be applied to the combinational logic, combinational connections with the combinational logic for applying stimulus data to the combinational logic and receiving response data from the combinational logic, a scan output for transmitting test response data obtained from the combinational logic, and control inputs having an enable input and a select input for operating the parallel scan paths, each scan path includes flip-flops of the combinational logic that, in a test mode, are connected in series, compare circuitry indicates the result of a comparison of the received test response data and the expected data at a fail flag output, and one of the scan paths includes a scan cell having an input coupled to the fail flag output.

Scheme for masking output of scan chains in test circuit

Operating a scan chain of a test circuit of an integrated circuit to have either a single fanout or multiple fanout to a compressor. The test circuit receives a fanout control signal for configuring the fanout of the scan chain. If the fanout control signal indicates configuring of the scan chain with a single fanout, the output of the scan chain is sent to one input of a compressor. If the fanout control signal indicates configuring of the scan chain with multiple fanout, the output of the scan chain is sent to multiple inputs of the compressor.

DDR circuitry data and control buses connected to test circuitry

A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The reduced device test interface is achieved using a double data rate (DDR) signaling technique between the tester and the device. The DDR test interface allows the tester to interface to test circuits within the device, such as IEEE 1500 and/or IEEE 1149.1 test circuits, to provide high test data bandwidth to the test circuits using a minimum of test interface signals. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. Additional features and embodiments ...

System for verifying operations of system LSI

A multiplexing processor multiplexes internal signals of a system LSI to be verified at a clock rate higher than that of the internal bus lines of the system LSI so as to create a multiplexed internal signal to be output. Thus, internal signals on target bus lines can be taken out of the system LSI using a small number of signal lines. Therefore, without considerably increasing the number of output terminals of the system LSI, the internal signals can be taken out through the smallest number of additional output terminals. This results in an easy verifying process for the entire operation of the system LSI without the need for a complicated design of the system LSI or an increase in cost of the system LSI.

Compacting circuit responses

Circuit responses to a stimulus may be compacted, decreasing the number of pin outs, without increasing the circuit element length, using a compactor. In accordance with one embodiment of the present invention, errors may be detected in scan chains used for integrated circuit testing. The number of outputs applied to output pins or other connectors may be substantially decreased, resulting in cost savings.

Semiconductor device protecting built-in transistor from the voltage applied at test mode

A semiconductor device comprises a high-voltage detector for generating a test mode signal and a detection signal when a test mode setting signal is inputted from an input terminal for inputting, as a first input signal, any one of a normal signal and the test mode setting signal having a higher voltage than the normal signal, an input circuit for generating a normal mode signal in accordance with the normal signal, and a protection circuit for reducing an electric field between an input side and a low-voltage power supply side of the input circuit in accordance with the detection signal, the electric field being generated by inputting the test mode setting signal thereto.

Semiconductor integrated circuit device

An input/output pin for test corresponding to a test circuit of the digital section is used in common as the input/output pin for usual operation of the analog section, the selection switches are respectively provided between the relevant analog pin and analog circuit and on a signal line up to the test circuit of the digital section from the relevant analog pin and the switches are provided at both end portions of the signal line between the test circuit of digital section and the input/output pin for common use in order to fix the voltage of the signal line to the predetermined voltage such as the ground voltage during the usual operation.

OPTIMIZED JTAG INTERFACE

An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations.

Integrierter Baustein zum vereinfachten parallelen Testen, Testboard zum Testen von mehreren integrierten Bausteinen sowie Testsystem und Testereinheit

Die Erfindung betrifft einen integrierten Baustein, umfassend: - einen Nutzschaltkreis; - eine Testschaltung zum Durchführen eines Tests des Nutzschaltkreises und zum Bereitstellen eines Fehlerdatums; - ein Registerelement zum Speichern des Fehlerdatums und zum Ausgeben des Fehlerdatums an einem Fehlerdatenausgang des integrierten Bausteins abhängig von einem Ausgabesignal, wobei das Registerelement weiterhin mit einem Dateneingang des integrierten Bausteins verbunden ist, um abhängig von dem Ausgabesignal ein an dem Dateneingang anliegendes Datum zu übernehmen.

SYSTMEME AND PROCESS Of EVALUATION the SPEED Of a CIRCUIT

Un procédé et un système destinés à évaluer la vitesse d'un circuit 20 sont proposés. Selon un mode de réalisation, le procédé comprend la détermination 605, pendant une première phase opérationnelle 602 d'un premier cycle opérationnel 601, de la vitesse de propagation d'un premier signal 228 dans un premier chemin de propagation de signal 24 et simultanément l'empêchement 605 de tous les signaux de se propager dans un deuxième chemin de propagation de signal 25 sensiblement parallèle au premier chemin de propagation de signal 24. Le procédé comprend en outre la détermination 606, pendant une deuxième phase opérationnelle 603 alternant avec la première phase opérationnelle 602, de la vitesse de propagation d'un deuxième signal 229 dans le deuxième chemin de propagation de signal 25 et, simultanément, l'empêchement 606 de tous les signaux de se propager dans le premier chemin de propagation de signal 24.

CIRCUIT AND MEHTOD FOR DIAGNOSING POWER SWITCH USING OR GATE CIRCUIT, BMS INCLUDING CIRCUIT FOR DIAGNOSING POWER SWITCH USING OR GATE CIRCUIT

Test Circuit and Method of Controlling the Same

Ultra low pin count interface for die testing

An apparatus, a method and a system to test a device. An input/output (I/O) block communicates with an external tester to receive test data and to send test result using first and second communication modes. A logic block parses the test data. A memory stores microcode from the parsed test data. The microcode contains a test program to test a circuit. A controller executes the test program.

OPTIMIZED JTAG INTERFACE

An optimized JTAG interface is used to access JTAG Tap Domains (104) within an integrated circuit (300). The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations.

Method and apparatus for fast PLL initialization

A method and apparatus for fast PLL initialization have been disclosed where control of a VCO is based on a selected control signal which is based upon either a comparison signal or a prespecified signal.

Method and apparatus for test time reduction using fractional data packing

An embodiment provides a circuit for testing an integrated circuit. The circuit includes an input converter that receives N scan inputs and generates M pseudo scan inputs, where M and N are integers. A scan compression architecture is coupled to the input converter and generates P pseudo scan outputs in response to the M pseudo scan inputs. An output converter is coupled to the scan compression architecture and generates Q scan outputs in response to the P pseudo scan outputs, wherein P and Q are integers. The input converter receives the N scan inputs at a first frequency and generates the M pseudo scan inputs at a second frequency and the output converter receives the P pseudo scan outputs at the second frequency and generates the Q scan outputs at the first frequency.

DEBUGGING METHOD EXECUTED VIA SCAN CHAIN FOR SCAN TEST AND RELATED CIRCUITRY SYSTEM

A circuit debugging method includes: utilizing a debugging circuit to determine an operating status of a specific circuit to generate a result; utilizing a register located in a scan chain path to store the result, wherein the scan chain path is arranged for a scan test; and utilizing an output pad located in the scan chain path to output the result, wherein the result is arranged to be indicative of the operating status of the specific circuit.

REDUCED SIGNALING INTERFACE METHOD & APPARATUS

This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

Reducing power consumption by estimating load and reducing clock speed

In a data processing device, a processor (34) processes data based on a stored program and a buffer manager (32) accesses the data. The data processing device includes a program memory (35) which stores program codes, the program codes being loaded into the program memory (35) and executed by the processor (34) when processing the data. A shared memory (101) stores one of the program codes and the data. A control unit (103) selectively connects one of the processor (34) and the buffer manager (32) to the shared memory (101 based on a select pattern, wherein the shared memory functions to store the program codes when the select pattern is set in a first condition, and the shared memory functions to store the data when the select pattern is set in a second condition.

Diagnostic interface switching with shared external connections

A data processing device, such as an integrated circuit, has two diagnostic modes. In the first mode, a first diagnostic unit 2 within the device communicates with an external test apparatus 20. In the second mode, a second diagnostic 4 unit within the device communicates with an external test apparatus. The diagnostic units communicate with the test apparatus using data connections 8, 10, 12, 14, 16. Some of the data connections 14, 16 are shared between the units. A watcher unit 6 monitors one or more of the connections. If a predetermined signal is detected on the monitored connection, the watcher unit changes the diagnostic mode. The pattern used to switch from the first mode to the second mode may be different to the one used to switch back. One of the diagnostic units may use all of the connections and the other may use only some of them.

测试电路、集成电路及其测试方法

... 本发明提供一种测试电路、集成电路及其测试方法，所述测试电路包括选择器SEL1和选择器SEL2，所述选择器SEL1在其第一输入端，接收来自宏块MB1的信号M1OUT，在其第二输入端，接收宏块MB2用的测试输入信号TIN1和TIN2；所述选择器SEL2，在其第一输入端，接收来自SEL1的信号SQ，在其第二输入端接收来自MB2的信号M2OUT。在对MB1进行测试的第一测试模式中，SEL1向SEL2的第一输入端输出来自MB1的信号M1OUT；SEL2向MB1输出来自SEL1的信号SQ。在对MB2进行测试的第二测试模式中，SEL1向MB2输出MB2用的测试输入信号TIN1和TIN2；SEL2将来自MB2的信号M2OUT作为MB2用的测试输出信号TOUT输出。 ...

SEMICONDUCTOR TEST DEVICE AND SEMICONDUCTOR TEST METHOD

Provided are a semiconductor test device and a semiconductor test method capable of applying a different test mode command for each semiconductor chip without using the additional pin of semiconductor test equipment. A semiconductor test device for a reception side according to the present invention includes a DQ signal receiving part for receiving a first DQ signal through a first DQ pin; a test mode register set signal processing part for receiving a test mode register set signal and outputting a test mode register set pulse signal in response to the first DQ signal; and a test mode command generation part for generating a test mode command corresponding to an input address in response to the test mode register set pulse signal. COPYRIGHT KIPO 2018 (110) DQ signal receiving part (120) MRS decoder (130) TMRS signal processing part (140) Test mode command generation part ...

LOW COST TEST FOR IC'S OR ELECTRICAL MODULES USING STANDARD RECONFIGURABLE LOGIC DEVICES

Low cost test for Integrated Circuits or electrical modules using a reconfigurable logic device is described. In one embodiment, the invention includes configuring a reconfigurable logic device to comply with input standards of a device under test, applying test signals to the device under test, detecting output results of the device under test, and analyzing the detected output results.

DOUBLE DATA RATE TEST INTERFACE AND ARCHITECTURE

A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The reduced device test interface is achieved using a double data rate (DDR) signaling technique between the tester and the device. The DDR test interface allows the tester to interface to test circuits within the device, such as IEEE 1500 and/or IEEE 1149.1 test circuits, to provide high test data bandwidth to the test circuits using a minimum of test interface signals. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. Additional features and embodiments ...

SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS

Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.

TDI, SC, and SE gating circuitry with count complete input

The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to be reused when the device is placed in a JTAG daisy-chain arrangement with other devices, such as in a customers system using the device. Additional embodiments are also provided and described in the disclosure.

Tap, decoder providing SC and SE to scan path circuits

The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.

Programmable scan compression

An implementation of a system disclosed herein includes a decompressor logic with the capability to vary a level of decompression of a scanning input signal based on value of compression program bits and a compressor logic to generate a scanning output signal, the compressor logic including a plurality of XOR logics, wherein the output of the plurality of XOR logics is selected based on the compression program bits.

Hardware enablement using an interface

A hardware enablement apparatus includes a processor, and a communications interface configured for writing license data to one or more data registers and for using the license data to selectively enable, under control of the processor, hardware features associated with the data registers, at least one of the data registers being implemented in non-volatile memory.

Low cost test for IC's or electrical modules using standard reconfigurable logic devices

Low cost test for Integrated Circuits or electrical modules using a reconfigurable logic device is described. In one embodiment, the invention includes configuring a reconfigurable logic device to comply with input standards of a device under test, applying test signals to the device under test, detecting output results of the device under test, and analyzing the detected output results.

System und Verfahren zum Auswerten der Geschwindigkeit einer Schaltung

Es wrden ein Verfahren und ein System zum Auswerten der Geschwindigkeit einer Schaltung geliefert. Gemäß einem Ausführungsbeispiel umfaßt das Verfahren ein Bestimmen, während einer ersten Betriebsphase eines ersten Betriebszyklus, der Ausbreitungsgeschwindigkeit eines ersten Signals in einem ersten Signalausbreitungspfad und ein gleichzeitiges Hindern aller Signale daran, sich in einem zweiten Signalausbreitungspfad, der zu dem ersten Signalausbreitungspfad im wesentlichen parallel ist, auszubreiten. Das Verfahren umfaßt ferner ein Bestimmen, während einer zweiten Betriebsphase, die sich mit der ersten Betriebsphase abwechselt, der Ausbreitungsgeschwindigkeit eines zweiten Signals in dem zweiten Signalausbreitungspfad und ein gleichzeitiges Hindern aller Signale daran, sich in dem ersten Signalausbreitungspfad auszubereiten.

Communication of a diagnostic signal and a functional signal by an integrated circuit

Communication of a diagnostic signal and a functional signal by an integrated circuit

INTEGRATED CIRCUIT TESTER ON A SILICON WAFER AND INTEGRATED CIRCUIT.

L'invention concerne un testeur de circuits intégrés sur une galette de silicium, caractérisé en ce que le testeur comporte une connexion entrée sortie pour tester un circuit intégré et en ce que le testeur comporte : - des moyens (E71) de transfert au circuit intégré d'une trame de données par la connexion entrée sortie, la trame de données comportant une référence de temps pour les données comprises dans la trame de données, un champ de validation de la référence de temps et un champ de données comprenant au moins une commande de test du circuit intégré, - des moyens (E74) de réception, par la connexion entrée sortie, d'une trame de données, les données de la trame de données reçue ayant une durée multiple de la référence de temps.

ULTRA LOW PIN COUNT INTERFACE FOR DIE TESTING

An apparatus, a method and a system to test a device. An input/output (I/O) block communicates with an external tester to receive test data and to send test result using first and second communication modes. A logic block parses the test data. A memory stores microcode from the parsed test data. The microcode contains a test program to test a circuit. A controller executes the test program.

REDUCED PIN COUNT SCAN CHAIN IMPLEMENTATION

A synchronous logic device with reduced pin count scan chain includes more than two flip/flops (SDCO, SDC1, SDC2) coupled to form a shift register for receiving a scan data input signal (ScanDataln), a combinational logic circuit (20) for receiving device inputs, generating flip/flop inputs for the more than two flip/flops, and generating an output signal, a first multiplexer (MUX10) for providing a clock signal to the more than two flip/flops during a test mode, a second multiplexer (MUX12) for selecting between a test mode output from the shift register and the output signal from the combinational logic circuit (20), and for providing a scan data output signal (ScanDataOut).

Design-for-test circuit for low pin count devices

A design-for-test (DFT) circuit for an integrated circuit (IC) for enabling accurate quiescent current testing. The IC includes a voltage supply pin, a ground pin and an internal voltage regulator coupled between the voltage supply and ground pins for providing an internal output voltage. The DFT circuit includes a voltage storage device which couples to the voltage regulator to temporarily maintain the internal output voltage when the voltage regulator is disabled. The mode control circuit detects a quiescent current test mode, disables the voltage regulator and decouples the voltage regulator from the voltage storage device when the quiescent current test mode is detected. The DFT circuit may include an enable circuit which generates a freeze signal when the quiescent current test mode is detected, and at least one switch which decouples the voltage regulator from the voltage storage node. The DFT circuit is particularly useful for low pin-count ICs.

Circuit test interface and test method thereof

A circuit test interface and a test method are disclosed. The circuit test interface may include a test voltage input pad, a test voltage output pad, and a plurality of input buffers. Each of the plurality of input buffers may have a first input terminal, a second input terminal, and an output terminal. The first input terminal of each respective input buffer may be coupled to one of a plurality of through-silicon vias (TSVs). The circuit test interface may further include a plurality of switch units. Each of the plurality of switch units may have a first terminal and a second terminal. The circuit test interface may further include a scan chain, coupled to both the output terminal of each of the plurality of input buffers and to the test voltage output pad.

Increase data transfer throughput by enabling dynamic JTAG test mode entry and sharing of all JTAG pins

An integrated circuit with functional circuitry and testing circuitry, the testing circuitry having a state machine operable in a plurality of different states. The integrated circuit also has a pin for receiving a signal, wherein the state machine is operable to transition between states in response to a change in level of the signal. Circuitry couples the signal of the pin, in a first level, to the state machine in a first time period for causing the state machine to enter a predetermined state, and circuitry maintains the signal in the first level to the state machine in a second time period for maintaining the state machine in the predetermined state. Also during the second time period, circuitry couples data received at the pin to a destination circuit other than the state machine, wherein the destination circuit is operable to perform plural successive scan tests using data from the pin without a power on reset of the functional circuitry.

Semiconductor device protecting built-in transistor from the voltage applied at test mode

A semiconductor device comprises a high-voltage detector for generating a test mode signal and a detection signal when a test mode setting signal is inputted from an input terminal for inputting, as a first input signal, any one of a normal signal and the test mode setting signal having a higher voltage than the normal signal, an input circuit for generating a normal mode signal in accordance with the normal signal, and a protection circuit for reducing an electric field between an input side and a low-voltage power supply side of the input circuit in accordance with the detection signal, the electric field being generated by inputting the test mode setting signal thereto.

Panel Testing Device

Disclosed is a panel testing device. The panel testing device includes: a supporter and a plurality of test pins disposed on the supporter, wherein the plurality of test pins are in one-to-one correspondence with a plurality of signal pins on the tested panel, any one of the test pins satisfies d≤D≤d+L; wherein D is a width of the test pin, d is a width of the signal pin corresponding to the test pin, L is a minimum pitch between two adjacent signal pins.

TAP addressable circuit with bi-directional TMS and second signal lead

This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

Communication of a diagnostic signal and a functional signal by an integrated circuit

Testing method and program product used therein

Disclosed is a testing method that tests multiple devices to be tested which are connected to a test module, and that includes: (a) a step wherein, of the combinations of the multiple devices to be tested, the combinations of devices to be tested that are theoretically capable of being measured simultaneously, are determined based at least on the connection relationships between the test module and the multiple devices to be tested; and (b) a step wherein, from the combinations determined in the step (a), the combinations of devices to be tested which actually are measured simultaneously are selected in order, and the multiple devices to be tested are tested.

Self-reparable semiconductor and system thereof

Transitioning POLL IN to set MRST and CE high states

An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations.

Reconfiguring monitoring circuitry

A method of reconfiguring a current debug configuration of a debug unit connected to a peripheral circuit on an integrated circuit chip. The method comprises the debug unit collecting debug data of the peripheral circuit and outputting the debug data in a message stream. The debug unit receives a debug reconfiguration command. The debug unit transmits an indication of the current debug configuration, then reconfigures the current debug configuration to a new debug configuration in accordance with the debug reconfiguration command, then transmits an indication of the new debug configuration. The indication of the current debug configuration and the indication of the new debug configuration are transmitted adjacent to the debug data in the message stream.

METHODS AND APPARATUS THAT SELECTIVELY USE OR BYPASS A REMOTE PIN ELECTRONICS BLOCK TO TEST AT LEAST ONE DEVICE UNDER TEST

METHOD FOR REALIZING PINS TIME SHARE MULTIPLEXING AND A SYSTEM-ON-A-CHIP

A method for realizing pin time-share multiplexing which can utilize at least one pin of a system-on-a-chip (SOC) for time-share multiplexing as a first interface mode or a second interface mode, said SOC including a first interface circuit, a first pin, a second interface circuit and a second pin. The first interface circuit includes the first bidirectional solder-pad unit, the first signal interface unit of the first interface mode and the interface unit of said second interface mode. The second interface circuit includes the second bidirectional solder-pad unit and the second signal interface unit of the first interface mode. The method includes: time-share selecting the output port of the first signal interface unit or the output port of the interface unit of the second interface mode to connect with the first pin via the first bidirectional solder-pad unit.

Programmable circuits for correcting scan-test circuitry defects in integrated circuit designs

In certain embodiments, an integrated circuit has scan-test circuitry that performs scan testing on circuitry under scan test (CUST) within the IC, where the scan-test circuitry is susceptible to a defect. In order to enable the defect to be corrected after it occurs, the scan-test circuitry includes a set of programmable circuitry connected to provide a signal to other circuitry (e.g., a scan chain) within the scan-test circuitry, where the set of programmable circuitry includes one or more configurable memory cells connected to control the programming of the set of programmable circuitry. The memory cell(s) can be configured to program the set of programmable circuitry to enable the scan testing to be performed without modification. The memory cell(s) can also be configured to program the set of programmable circuitry to modify the scan testing to correct the defect in the scan-test circuitry.

Scan test method and apparatus

The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device using the falling edge of a test/scan clock. The signals are provided on device leads that are also used to provide signals to scan test architectures using the rising edge of the test/scan clock. According to the disclosure, device test leads serve to input different test signals on the rising and falling edge of the test/scan clock which reduces the number of interconnects between a tester and the device under test.

Time difference measurement apparatus

A time difference measurement apparatus for measuring a time difference between transmission delay times of signals transmitted on two signal lines, includes: a selector for outputting one of the signals transmitted on the signal lines in accordance with a selection signal; a switch for outputting the selection signal in accordance with an output signal of the selector, the output signal being delayed for a predetermined time; a feedback loop for connecting the output of the selector to the input ends of the two signal lines; and a controller for calculating a time difference between transmission delay times of the signals transmitted on the two signal lines on the basis of self-oscillation cycles of signals transmitted through the feedback loop, the self-oscillation cycles changing in accordance with a logical value of the selection signal.

Electronic circuit, circuit apparatus, test system, control method of the electronic circuit

An electronic circuit includes: a first power line capable of supplying power; a second power line capable of supplying power independently from the first power line; a main circuit connected to the second power line; a detector that detects the supply of power from the first power line or the second power line; and a controller connected to the first power line and the second power line, wherein the controller controls a voltage or a current supplied from the first power line and supplies the voltage or the current to the main circuit when the detector detects supply of power from the first power line.

Method and apparatus for device access port selection

The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved using only the dedicated TDI, TMS, TCK, and TDO signal terminals of the device. The selecting and accessing of device access ports can be achieved when a single device is connected to the controller, when multiple devices are placed in a daisy-chain arrangement and connected to the controller, or when multiple devices are placed in a addressable parallel arrangement and connected to the controller. Additional embodiments are also provided and described in the disclosure.

Apparatus and system for implementing variable speed scan testing

In an embodiment of the invention, variable test clock circuitry is provided within an integrated circuit desired to be tested. The variable test clock frequency implements a test clock control register that receives serial test data from a device tester and is configured to serially pass the received test data to scan test chains within the integrated circuit. The test clock control register stores test clock information. The test clock information is provided to a test clock generator where the test clock generator then produces test clock signals at a predetermined frequency. The test clock signal is then provided as a test clock frequency for the scan test chains within the integrated circuit. Methods are also disclosed for operating the variable test clock frequency.

Dual mode test access port method and apparatus

Connection circuitry couples scan test port (STP) circuitry to test access port (TAP) circuitry. The connection circuitry has inputs connected to scan circuitry control output leads from the TAP circuitry, a select input lead, and a clock input lead. The connection circuitry has outputs connected to a scan enable (SE) input lead, a capture select (CS) input lead, and the scan clock (CK) input lead of the STP circuitry. The connection circuitry includes a multiplexer having a control input connected with a clock select lead from the TAP circuitry, an input connected with a functional clock lead, an input connected with the clock input lead, an input connected with a Clock-DR lead from the TAP circuitry, an OFF lead, and an output connected with the scan clock input lead.

Methods and Systems for Production Testing of DCO Capacitors

Systems provide for a test system for capacitors in a digitally controllable oscillator (DCO). The system includes: capacitor toggling logic configured to switch on and off a selected one of the capacitors at a modulation frequency; a tone generator configured to generate a tone; a mixer configured to receive the tone and an output carrier signal from the DCO while the capacitor toggling logic is switching the selected one of the capacitors on and off and to output an intermediate frequency signal having FM sidebands based on the modulation frequency and relative capacitor size; and an evaluation circuit configured to evaluate a frequency deviation associated with the selected one of the capacitors based on at least one of the FM sidebands.

Test apparatus

A test apparatus tests a DUT formed on a wafer. A power supply compensation circuit includes source and a sink switches each controlled according to a control signal. When the source or sink switch is turned on, a compensation pulse current is generated, and the compensation pulse current is injected into a power supply terminal of the DUT via a path that differs from that of a main power supply, or is drawn from the power supply current that flows from the main power supply to the DUT via a path that differs from that of the power supply terminal of the DUT. Of components forming the power supply compensation circuit, including the source and sink switches, a part is formed on the wafer. Pads are formed on the wafer in order to apply a signal to such a part of the power supply compensation circuit formed on the wafer.

Integrated circuit having a scan chain and testing method for a chip

An IC having a scan chain and a testing method for a chip, comprising a first interface group, a second interface group and a scan data selector. The first interface group and the second interface group each comprise at least two input/output (I/O) interfaces which can be packaged as external pins of the IC. The I/O interfaces of the first interface group are connected to input terminals of the scan data selector in one-to-one correspondence, and an output terminal of the scan data selector is connected to a scan data input terminal of the scan chain. A scan data output terminal of the scan chain is connected to the I/O interfaces of the second interface group.

Serial i/o using jtag tck and tms signals

The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus. According to the present disclosure, the TAP's TMS terminal is used as a clock signal and the TCK terminal is used as a bidirectional data signal to allow serial communication to occur between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC.

Device and method for examining usb port of test apparatus

A device and method for examining a USB port of a test apparatus are characterized in that before a functional test is performed, with the test apparatus, on an electronic product equipped with a USB interface, the device including a USB connector, a connecting unit, and an alerting unit is connected to the USB port of the test apparatus so as to examine the power supply status of the USB port of the test apparatus. Accordingly, the electronic product equipped with the USB interface is efficiently protected against damage which might otherwise arise from unstable power supply to or an error in the USB port of the test apparatus during the ensuing functional test.

Ieee 1149.1 and p1500 test interfaces combined circuits and processes

In a first embodiment a TAP of IEEE standard 1149.1 is allowed to commandeer control from a WSP of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface. One approach provides for the TAP to maintain access and control of the TAP instruction register, but provides for a selected data register to be accessed and controlled by either the TAP+ATC or by the discrete CaptureDR, UpdateDR, TransferDR, ShiftDR, and ClockDR WSP data register control signals.

Memory channel having deskew separate from redrive

A memory module may have a redrive circuit having a plurality of redrive paths, a memory device, and a deskew circuit. The deskew circuit may be separate from the plurality of redrive paths. The deskew circuit may be coupled between the plurality of redrive paths and the memory device to selectively deskew data received in the redrive circuit.

Selectable jtag or trace access with data store and output

An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

Test Generator For Low Power Built-In Self-Test

Aspects of the invention relate to low power BIST-based testing. A low power test generator may comprise a pseudo-random pattern generator unit, a toggle control unit configured to generate toggle control data based on bit sequence data generated by the pseudo-random pattern generator unit, and a hold register unit configured to generate low power test pattern data by replacing, based on the toggle control data received from the toggle control unit, data from some or all of outputs of the pseudo-random pattern generator unit with constant values during various time periods. The low power test generator may further comprise a phase shifter configured to combine bits of the low power test pattern data for driving scan chains.

Optimized jtag interface

An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations.

Method and apparatus for testing integrated circuits

Aspects of the disclosure provide a testing method. The method includes supplying a power supply from a voltage regulator to a device under test (DUT). The DUT includes an adaptive voltage scaling module configured to generate a feedback signal in response to the power supply. Further, the method includes receiving the feedback signal from the DUT to the voltage regulator to regulate the power supply based on the feedback signal from the DUT, and determining whether the DUT meets a specified performance requirement while the voltage regulator regulates the power supply provided to the DUT based on the feedback signal received from the DUT.

Clock domain check method, clock domain check program, and recording medium

To reduce pseudo errors. A stationary signal is propagated through the circuit to be checked. A combination is extracted in which different asynchronous transfers occur between a transmitting side register and a receiving side register. From the extracted combination of asynchronous transfers, a circuit to be checked is extracted, and a synchronization circuit of a plurality of signals is excluded from the circuit to be checked. A stationary signal is propagated through the circuit to be checked, for each combination among all combinations of logic values “1” and “0” of the stationary signal. It is checked whether or not there exists one asynchronous transmitting side register to which signal change can logically reach, in the combination of logic values of the stationary signal propagated. Based on the result, it is determined whether or not the circuit is appropriate as a synchronization circuit for a single-signal transfer, thereby reducing pseudo errors.

Aging degradation diagnosis circuit and aging degradation diagnosis method for semiconductor integrated circuit

Provided is an aging degradation diagnosis circuit, including: a first delay circuit including a gate array for allowing aging degradation to progress, the first delay circuit being configured to delay an input signal and output a first output signal; a second delay circuit including a gate array having the same number of stages as the first delay circuit, the second delay circuit being configured to delay an input signal and output a second output signal; and an arbitrary delay unit, which is capable of varying a delay period in the second delay circuit by a predetermined amount. A delay comparison unit outputs comparison information obtained by relatively comparing delays between the first output signal and the second output signal. An adjustment unit uses the comparison information, to thereby readjust the delay period in the second delay circuit.

Selectable jtag or trace access with data store and output

An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

Method for testing an integrated circuit

A method for testing an integrated circuit and an integrated circuit. The integrated circuit has an internal testing structure which may be accessed via an internal test access port and a control bus which is conducted to the outside via control ports, it being possible to switch over between a running mode and a test mode so that, in the test mode, the test access port is accessed via the control ports and the control bus, thus testing the integrated circuit.

Automatic generation of valid at-speed structural test (asst) test groups

A method and system is provided for automatically generating valid at speed structural test (ASST) test groups. The method includes loading a netlist for an integrated circuit into a processor. The method further includes determining a plurality of clock domain crossings between a plurality of clock domains within the integrated circuit. The method further includes generating a first test group. The method further includes adding a first clock domain of the plurality of clock domains to the first test group. The method further includes adding a second clock domain of the plurality of clock domains to the first test group when the second clock domain does not have a clock domain crossing into the first clock domain.

IEEE1588 PROTOCOL NEGATIVE TESTING METHOD

The present invention relates to an IEEE1588 protocol negative testing method, comprises steps of: connecting a IEEE1588 tester and a slave clock DUT to establish a real-time closed-loop feedback mechanism; taking the IEEE1588 tester as a master clock, and establishing a stable time synchronization with the slave clock DUT; obtaining the timing offset or path delay of the slave clock DUT before disturbance; assembling an abnormal message in a frame and sending it to the slave clock DUT; calculating the timing offset or path delay increment after disturbance of the abnormal message; determining whether there is a sudden change in the timing offset or path delay of the slave clock DUT, wherein if there is no sudden change, the test passes; otherwise the test fails. This testing method uses the field of correction field (correction Field) in the IEEE1588 message to “magnify” the response of the slave clock DUT to the abnormal message stimulus, and realizes a real-time closed-loop detection to efficiently verify whether the message processing logic of the slave clock DUT follows the IEEE1588 protocol. 1. An IEEE1588 protocol negative testing method , characterized in that , the method comprises the following steps:(1) connecting a IEEE1588 tester and a slave clock DUT to establish a real-time closed-loop feedback mechanism;(2) taking the IEEE1588 tester as a master clock, and establishing a stable time synchronization with the slave clock DUT;(3) obtaining the timing offset or path delay of the slave clock DUT before disturbance through a real-time closed-loop feedback mechanism by the IEEE1588 tester;(4) assembling an abnormal message in a frame by the IEEE1588 tester, and sending it to the slave clock DUT;(5) obtaining the timing offset or path delay of the slave clock DUT after disturbance of the abnormal message through the real-time closed-loop feedback mechanism by the IEEE1588 tester;(6) calculating the timing offset increment or path delay increment after ...

Apparatus for monitoring operating parameters of integrated circuits and integrated circuit with operating parameter monitoring

A device for monitoring operating parameters of integrated circuits. A signal is generated at least at one output of a comparison element by comparing switching states of input signals at the at least two inputs of the comparison element, which signal indicates that the at least one operating parameter has fallen below or has exceeded a predefined threshold. The two input signals are generated by at least two operating parameter-dependent devices, and the switching behavior thereof is subject to a time delay depending on the current value of the at least one operating parameter. A predefined time delay has a value such that when the predefined threshold of the operating parameter is exceeded, one of the input signals changes its switching state at the times predefined for the comparison element by the clock signal on the basis of the time delay.

OSCILLATION CIRCUIT, INTEGRATED CIRCUIT, AND ABNORMALITY DETECTION METHOD

There is provided an oscillation circuit including: a main oscillation circuit that outputs a specific main clock to an internal circuit; a sub oscillation circuit that outputs a sub clock having a different frequency to the frequency of the main oscillation circuit; a first abnormality detection section that detects an abnormality according to a number of main clock cycles output from the main oscillation circuit within a predetermined period corresponding to sub clock outputs from the sub oscillation circuit; and a second abnormality detection section that detects an abnormality according to a frequency divided clock of the main clock output from the main oscillation circuit that has been frequency-divided and the sub clock output from the sub oscillation circuit. 1. An oscillation circuit comprising:a main oscillation circuit that outputs a specific main clock to an internal circuit;a sub oscillation circuit that outputs a sub clock having a different frequency to the frequency of the main oscillation circuit;a first abnormality detection section that detects an abnormality according to a number of main clock cycles output from the main oscillation circuit within a predetermined period corresponding to sub clock outputs from the sub oscillation circuit; anda second abnormality detection section that detects an abnormality according to a frequency divided clock of the main clock output from the main oscillation circuit that has been frequency-divided and the sub clock output from the sub oscillation circuit.2. The oscillation circuit of claim 1 , wherein the first abnormality detection section detects as an abnormality each of an abnormality in the oscillation frequency of the main oscillation circuit claim 1 , an abnormality in the oscillation frequency of the sub oscillation circuit claim 1 , and an oscillation cessation of the sub oscillation circuit.3. The oscillation circuit of claim 1 , wherein the second abnormality detection section detects an oscillation ...

Cycle accurate and cycle reproducible memory for an fpga based hardware accelerator

A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.

On-chip integrated circuit power measurement cell

A power measurement cell, or group of power measurement cells, for the calculation of the power consumption of one or more electrical signals, as well as monitoring electrical signals in an integrated circuit, are disclosed. Further, super cells for the automation of specialized functions associated with the calculation of power consumption of one or more electrical signals are also disclosed. Methods associated with the use of the one or more power measurement cells and for the use of super cells for the calculation of the power consumption of one or more electrical signals are also described.

ON-CHIP SENSOR FOR MEASURING DYNAMIC POWER SUPPLY NOISE OF THE SEMICONDUCTOR CHIP

An on-chip sensor measures dynamic power supply noise, such as voltage droop, on a semiconductor chip. In-situ logic is employed, which is sensitive to noise present on the power supply of functional logic of the chip. Exemplary functional logic includes a microprocessor, adder, and/or other functional logic of the chip. The in-situ logic performs some operation, and the amount of time required for performing that operation (i.e., the operational delay) is sensitive to noise present on the power supply. Thus, by evaluating the operational delay of the in-situ logic, the amount of noise present on the power supply can be measured. 1. An integrated circuit comprising:functional logic that performs operations with reference to a reference clock signal;an in-situ probe that receives a delayed clock signal, said delayed clock signal delayed by an amount of time relative to the reference clock signal, and said in-situ probe performs an operation to generate an output signal, wherein the in-situ probe shares a power supply with said functional logic;a pulse generator that receives the delayed clock signal and the output signal of the in-situ probe, and said pulse generator generates a pulse signal that corresponds to operational delay of the in-situ probe in generating the output signal; anda sensor that receives the pulse signal and evaluates width of the pulse signal for determining a corresponding dynamic power supply noise fluctuation that was experienced by the functional logic during performance of the operation of the in-situ probe.2. The integrated circuit of wherein the in-situ probe comprises stacked inverters.3. The integrated circuit of wherein the operation performed by the in-situ probe is to invert the delayed clock4. The integrated circuit of wherein the sensor comprises:a D flip-flop that receives a reference signal as its D signal and that receives the pulse signal as the flip-flop's clock signal.5. The integrated circuit of wherein when the reference ...

Scan response reuse method and apparatus

The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and applied as stimulus data input to the scan inputs of the circuit under test. Also the disclosure described a novel method and apparatus for allowing the response data output from the scan outputs of a circuit under test to be formatted and used as expected data to compare against the response data output from the circuit under test. Additional embodiments are also provided and described in the disclosure.

Scan topology discovery in target systems

Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values.

Test compression in a jtag daisy-chain environment

The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to be reused when the device is placed in a JTAG daisy-chain arrangement with other devices, such as in a customers system using the device. Additional embodiments are also provided and described in the disclosure.

Delay fault testing for chip i/o

An integrated circuit (IC) chip is provided. The IC chip includes a signal output via which an outgoing signal is transmitted, and a signal input via which an incoming data signal is received. Also included on the IC ship is a pass circuit to couple the signal output to the signal input during testing of the IC chip. Furthermore, a delay circuit produces a first timing signal and a second timing signal during testing of the IC chip. The second timing signal is delayed from the first timing signal according to a test parameter. The first timing signal triggers transmission of a test signal via the signal output, and the second timing signal triggers sampling of the received test signal via the signal input.

Adapting scan-bist architectures for low power operation

A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known art. The changes between the known art Scan-BIST architecture and the low power Scan-BIST architecture involve modification of the known scan path into scan path 502, to insert scan paths A 506, B 508 and C 510, and the insertion of an adaptor circuit 504 in the control path 114 between controller 110 and scan path 502.

Integrated circuit and test system thereof

An integrated circuit includes an input unit, a core processor and M output buffers, where M is a natural number greater than 1. The input unit has an output control pin, and receives an output control signal. The core processor is coupled to the input unit, and receives the output control signal to provide M output control signals. The M output buffers are coupled to the core processor, and are time-division multiplexing and enabled in response to the M output control signals, respectively, to output M output signals in M operation periods, respectively.

Minimizing the amount of time stamp information reported with instrumentation data

This invention is time stamping subsystem of an electronic apparatus. A time stamp generator generates a multibit time stamp value including a predetermined number of least significant bits overlapping a predetermined number of most significant bits. Each client receives the least significant bits. Each client associates captured data with a corresponding set of the least significant bits in a message. A central scheduling unit associates most significant bits of the time stamp value with the least significant bits of the message. This associating compares overlap bits of the most significant bits and least significant bits. The most significant bits are decremented until the overlap bits are equal.

System and method for sharing a communications link between multiple communications protocols

A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols.

TEST SYSTEM AND TEST METHOD THEREOF

An embodiment of a test system is provided. The system includes an electronic device to be tested and a network connection device. The electronic device to be tested includes a central processing unit (CPU) and a first universal serial bus (USB) interface. The network connection device includes a LAN module coupled to a remote server via a LAN port, and a second USB interface. When the second USB interface of the network connection device is coupled to the first USB interface of the electronic device to be tested, the CPU of the electronic device to be tested obtains a specific program from the remote server via the LAN port and the LAN module of the network connection device according to a preboot execution environment (PXE) code from the network connection device. 1. A test system , comprising: a central processing unit (CPU); and', 'a first universal serial bus (USB) interface; and, 'an electronic device to be tested, comprising a LAN module coupled to a remote server via a LAN port; and', 'a second USB interface,, 'a network connection device, comprisingwherein when the second USB interface of the network connection device is coupled to the first USB interface of the electronic device to be tested, the CPU of the electronic device to be tested obtains a specific program from the remote server via the LAN port and the LAN module of the network connection device according to a preboot execution environment (PXE) code from the network connection device.2. The test system as claimed in claim 1 , wherein the CPU of me electronic device to be tested performs a test operation or a preload operation according to the specific program.3. The test system as claimed in claim 1 , wherein the network connection device further comprises:a storage module, storing the PXE code, wherein the PXE code comprises a PXE ROM code or a PXE unified extensible firmware interface (UEFI) driver.4. The test system as claimed in claim 1 , wherein when a power on self test (POST) is performed ...

Product reliability estimation

Methods and systems for systems and methods for product reliability estimation are provided. A method implemented in a computer infrastructure includes separating products into different process window segments. The method also includes calculating a product reliability estimation for each process window segment. The method further includes calculating a system product reliability estimation. At least one of the separating, calculating the product reliability estimation, and calculating the system product reliability estimation is performed using a processor.

Methods and structure for on-chip clock jitter testing and analysis

Methods and structure for on-chip self-test of clock jitter for an application clock signal generated within an integrated circuit (IC). Features and aspects hereof provide for acquisition of samples of an application clock signal within the IC and counting the number of samples having a predetermined value. The count is compared to acceptable limits range values to generate a pass/fail signal of the IC use by external automated. A sample clock is generated based on the reference clock used by a Phase Locked Loop (PLL) circuit. An incremental delay is added to the sample clock pulse such that the sequence of samples “walk” through an application clock pulse waveform to sense clock jitter at various points of the waveform based on the counts. Acceptable limits range for the count at each sampled point, the incremental delay, and the number of samples at each delayed value may be user programmed

Test apparatus

A judgment unit judges the pass/fail of DUTs. A power supply circuit has changeable characteristics, and supplies a power supply signal to the DUTs. A condition setting unit performs a pilot test before a main test for the DUTs, and acquires a test condition to be used in the main test. The condition setting unit executes: (a) measuring a first device characteristic value for each of multiple pilot samples sampled from among the DUTs while emulating a power supply characteristic close to what is used in a user environment in which the DUT is actually used; (b) measuring a predetermined second device characteristic value for each of the multiple pilot sample devices while emulating a power supply characteristic close to what is used in a tester environment in which the main test is performed; and (c) determining the test condition based on the first and second device characteristic values.

Adapting scan architectures for low power operation

Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

INTEGRATED CIRCUIT AND ELECTRONIC APPARATUS INCLUDING INTEGRATED CIRCUIT

An integrated circuit and an electronic apparatus including the same. The electronic apparatus includes a scan input processing circuit, a selection circuit and a scanning circuit. The scan input processing unit is configured to output one of a scan input and a first logical value in response to a scan enable signal. The selection unit is configured to select one of an output of the scan input processing unit or a data input in response to the scan enable signal. The scan element comprises a flip-flop configured to store an output of the selection unit. 2. The electronic apparatus of claim 1 , wherein the scan input processing circuit comprises a NAND gate configured to receive the scan enable signal and an inverted scan input as inputs.3. The electronic apparatus of claim 2 , wherein the selection circuit comprises an OR-AND-INVERT (OAI) gate configured to receive an output of the NAND gate claim 2 , the scan enable signal claim 2 , and the data input.5. The electronic apparatus of claim 3 , wherein claim 3 , in a scan mode claim 3 , the NAND gate outputs the scan input claim 3 , andthe OAI gate outputs the inverted scan input.6. (canceled)7. The electronic apparatus of claim 6 , wherein a voltage at the second node is applied to the flip-flop.8. The electronic apparatus of claim 3 , wherein the flip-flop comprises a D flip-flop.916.-. (canceled)1716. The electronic apparatus of claim claim 3 , wherein the scan input processing circuit comprises a NAND gate.18. The electronic apparatus of claim 17 , wherein the NAND gate outputs the logic value in a normal mode and outputs the scan input in a scan mode.1916. The electronic apparatus of claim claim 17 , wherein the scan input processing circuit comprises a NOR gate.20. (canceled)2116. The electronic apparatus of claim claim 17 , wherein the selection circuit comprises an OR-AND-INVERT (OAI) gate.2216. The electronic apparatus of claim claim 17 , wherein the flip-flop comprises a D flip-flop.2316. The electronic ...

SELF-TEST CIRCUIT IN INTEGRATED CIRCUIT, AND DATA PROCESSING CIRCUIT

A self-test circuit is driven by a multiphase clock signal which includes N number of clock signals in same cycle having phases from first to N-th phases each phase-shifted by 1/N of the cycle. The self-test circuit includes a data selecting circuit, a serialization circuit, and a logical test circuit. The data selecting circuit switches input data that are input as M-bit wide parallel data to the self-test circuit, between normal data and test data for logical test. The serialization circuit performs serial conversion of the input data in N-parallel manner and outputs bits in N-parallel manner, as a single serial output signal at timing corresponding to each phase. In synchronization with timing corresponding to each phase, the logical test circuit imports the serial output signal as N-parallel bit strings each having length equal to M/N number of bits and performs a bit logical test for M number of bits. 1. A self-test circuit in an integrated circuit driven by a multiphase clock signal which includes N number of clock signals in same cycle having phases from a first phase to an N-th phase that are each phase-shifted by 1/N of the cycle , the self-test circuit comprising:a data selecting circuit configured to switch input data between normal data and test data for logical test, the input data being input as N-bit wide parallel data to the self-test circuit;a serialization circuit configured to perform serial conversion of the input data in N-parallel manner and outputs bits in N-parallel manner, as a single serial output signal at timing corresponding to each phase from the first phase to the N-th phase; anda logical test circuit configured to, in synchronization with timing corresponding to each phase from the first phase to the N-th phase, import the serial output signal as N-parallel bit strings each having length equal to M/N number of bits and perform a bit logical test for N number of bits.2. The self-test circuit in the integrated circuit according to claim ...

INTEGRATED CIRCUIT CHIP AND A METHOD FOR TESTING THE SAME

An integrated circuit chip includes at least two integrated circuits, at least three scan chains, and a multiplexor circuitry. Each integrated circuit includes an integrated circuit input port and an integrated circuit output port. The scan chains and the integrated circuits are coupled by default with a series chain having integrated circuits and scan chains alternating each other. The series chain starts with an initial scan chain and ends with the end scan chain. Each scan chain except the initial one includes a first scan chain input port coupled by default with the integrated circuit output port of the respective adjacent integrated circuit. Each scan chain except the end one includes a first scan chain output port coupled by default with the integrated circuit input port of the respective adjacent integrated circuit. 1. A chip comprising at least two integrated circuits , at least three scan chains , and a multiplexor circuitry , each integrated circuit comprising an input port and an output port , the scan chains and the integrated circuits are coupled in a series chain with the integrated circuits and the scan chains alternating each other , the series chain beginning with an initial scan chain and ending with an end scan chain , wherein each scan chain comprises a first scan chain input port and a first scan chain output port , the first scan chain input port of each scan chain , except the initial scan chain , is coupled with the output port of a preceding integrated circuit in the series chain , the first scan chain output port of each scan chain , except the end scan chain , is coupled with the input port of a successive integrated circuit in the series chain , the multiplexor circuitry comprising:using a computer, bypassing a first portion of the series chain beginning with a first bypassed scan chain and ending with a last bypassed integrated circuit wherein the output port of the integrated circuit preceding the first bypassed scan chain is coupled ...

INTEGRATED CIRCUIT TESTING

Systems and methods of testing integrated circuits are disclosed. A system may include a data compression component to compress data received from an integrated circuit under test at a first clock frequency, to generate compressed data. The system may also include a data output component, operatively coupled to the data compression component, to convey the compressed data to automated testing equipment at a second clock frequency. 1. A system comprising:a data compression component to compress data received from an integrated circuit under test at a first clock frequency, to generate compressed data; anda data output component, operatively coupled to the data compression component, to convey the compressed data to automated testing equipment at a second clock frequency.2. The system of claim 1 , wherein the second clock frequency is different than the first clock frequency.3. The system of claim 2 , wherein the second clock frequency is a lower frequency than the first clock frequency.4. The system of claim 1 , wherein the data compression component is to compare the received data to an expected data result and to communicate an output to the automated testing equipment.5. The system of claim 4 , wherein the data output component is included in a test module claim 4 , the test module being one of a plurality of test modules included in a test array to test a plurality of integrated circuits.6. The system of claim 5 , wherein the test array comprises a memory to store the expected data result claim 5 , and wherein the memory being shared by the plurality of test modules.7. The system of claim 1 , wherein the data compression component is to compress the data received from the integrated circuit responsive to whether an address of the data is even or odd.8. The system of claim 1 , wherein the data compression component is to compress the data received from the integrated circuit responsive to an invert odd or even bit mode.9. The system of claim 1 , wherein the data ...

Scan topology discovery in target systems

Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values.

DUBUGGING A SEMICONDUCTOR DEVICE

Devices and techniques are disclosed herein for debugging a device implemented on a die using non-test pins. An instruction to enable a debugging mode of operation is received with a memory device implemented at least in part on a die. In response to receiving the instruction, functionality of a first non-test pin of the die is modified to enable debugging data to be transmitted to a debugging component external to the die over the first non-test pin of the die. A debugging clock signal is established using a signal received at a second non-test pin of the die. Information including the debugging data is exchanged between the die and the debugging component using the first and second non-test pins of the die. 1. A method comprising:receiving with a memory device, implemented at least in part on a die, an instruction to enable a debugging mode of operation; and modifying functionality of a first non-test pin of the die to enable debugging data to be transmitted to a debugging component external to the die over the first non-test pin of the die;', 'establishing a debugging clock signal using a signal received at a second non-test pin of the die; and', 'exchanging information including the debugging data between the die and the debugging component using the first and second non-test pins of the die., 'in response to receiving the instruction2. The method of claim 1 , wherein receiving the instruction comprises receiving a command including the instruction over a data bus of the die during a normal operating mode of the die.3. The method of claim 1 , wherein the first non-test pin comprises a reset pin of the die claim 1 , and wherein the second non-test pin comprises a reference clock pin of the die.4. The method of claim 1 , wherein the die is placed on a circuit board claim 1 , wherein the die includes debugging pins that are not coupled to the circuit board claim 1 , and wherein the information is exchanged with the debugging component using the first and second non ...

APPARATUSES INVOLVING CALIBRATION OF INPUT OFFSET VOLTAGE AND SIGNAL DELAY OF CIRCUITS AND METHODS THEREOF

An example apparatus includes a circuit and calibration circuitry. The circuit has complementary input ports to receive input signals including a monotonously rising and/or falling wave reference signal and a voltage-test signal to test at least one direct current (DC) voltage associated with the circuit by comparing the input signals using a first polarity and second polarity associated with the circuit to produce a first output signal and a second output signal. During operation, the circuit manifests an input voltage offset and a signal delay with each comparison of the input signals. The calibration circuitry processes the first and second output signals and, in response, calibrates or sets an adjustment for at least one signal path associated with the circuit in order to account for the input offset voltage and signal delay during normal operation of the circuit. 1. An apparatus comprising: a first polarity associated with the circuit to produce a first output signal, and', 'a second polarity associated with the circuit to produce a second output signal, wherein during operation, the circuit manifests an input voltage offset and a signal delay with each comparison of the input signals; and, 'a circuit having complementary input ports to receive input signals including a monotonously rising and/or falling wave reference signal and a voltage-test signal to test at least one direct current (DC) voltage associated with the circuit by comparing the input signals using'}calibration circuitry to process the first and second output signals and, in response, calibrate or set an adjustment for at least one signal path associated with the circuit in order to account for the input offset voltage and signal delay during normal operation of the circuit.2. The apparatus of claim 1 , wherein the circuit includes matrix circuitry configured and arranged to couple the voltage-test signal to a first of the complementary input ports for the first polarity of the circuit and couple ...

HIGH-SPEED INTERFACE APPARATUS AND DESKEW METHOD THEREOF

A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode. 1. A high-speed data transmitter comprising:a first buffer connected to a first channel;a second buffer connected to a second channel; anda third buffer connected to a third channel, toggle the first channel from a first voltage level to a second voltage level different from the first voltage level over a predetermined interval;', 'maintain the second channel at the first or second voltage level during the predetermined interval; and', 'start a skew calibration mode based on the first channel and at least one of the second or third channel., 'wherein the high-speed data transmitter is configured to2. The high-speed data transmitter of claim 1 , wherein the predetermined interval is a period of transmitting a deskew synchronous code.3. The high-speed data transmitter of claim 2 , wherein the deskew synchronous code includes serial data “11111111”.4. The high-speed data transmitter of claim 1 , further configured to transmit normal data in a Mobile Industry Processor Interface (MIPI) standard.5. The high-speed data transmitter of claim 4 , wherein the normal data includes display data or image data.6. The high-speed data transmitter of claim 1 , configured to transmit normal data after the predetermined interval.7. The high-speed data transmitter of claim 1 , further comprising a clock generator configured to generate a clock signal.8. The high-speed data transmitter of claim 1 , wherein at least one of the first to third channels includes differential data lines.9. The ...

CLOCK JITTER AND POWER SUPPLY NOISE ANALYSIS

Disclosed are a method, system, and/or apparatus to perform clock jitter and power supply noise analysis. In one embodiment, a method may include receiving a first signal, which may be a clock signal, then generating a second signal based on the first signal. The method may further include delaying the second signal by a base delay and/or a series of fine delays. The method may also include taking measurements of the delayed second signal and comparing those measurements to theoretical measurements of the second signal that would occur if the first signal were noise-free. The method may further include determining, based on the measurements and the comparison thereof, whether noise is present, whether the noise is high frequency or low frequency noise, and whether the noise is due to clock jitter and/or power supply deviations. 1. A method comprising:receiving a first signal by a noise analyzer;generating, through the noise analyzer, a second signal based on the first signal;temporally displacing, through a base delay element, the second signal by a base delay time; andcomparing, through a comparator, an actual measurement of the temporally displaced second signal to a theoretical measurement of a third theoretical signal, wherein the third theoretical signal is a version of the second signal which would be generated from a first signal if the first signal were free from high frequency noise and low frequency noise.2. The method of claim 1 , further comprising:temporally displacing, through at least one fine delay element, the second signal by a fine delay time.3. The method of claim 2 , further comprising:comparing, through the comparator, a fine measurement taken of the temporally displaced second signal to a theoretical fine measurement taken of the third theoretical signal, wherein the fine measurement and the theoretical fine measurement temporally correspond to the temporal displacement provided by the at least one fine delay.4. The method of claim 1 , wherein ...

Adapting scan architectures for low power operation

Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

INTEGRATED CIRCUIT DEVICE AND METHOD THEREFOR

An integrated circuit device comprising at least one self-test component arranged to execute self-testing within at least one self-test structure during a self-test execution phase of the IC device, and at least one clock control component arranged to provide at least one clock signal to the at least one self-test component at least during the self-test execution phase of the IC device. The at least one clock control component is further arranged to receive at least one indication of at least one power dissipation parameter for at least a part of the IC device, and modulate the at least one clock signal provided to the at least one self-test component based at least partly on the received at least one power dissipation parameter for at least a part of the IC device. 1. An integrated circuit , IC , device comprising at least one self-test component arranged to execute self-testing within at least one self-test structure during a self-test execution phase of the IC device , and at least one clock control component arranged to provide at least one clock signal to the at least one self-test component at least during the self-test execution phase of the IC device; wherein the at least one clock control component is further arranged to:receive at least one indication of at least one power dissipation parameter for at least a part of the IC device; andmodulate the at least one clock signal provided to the at least one self-test component based at least partly on the received at least one power dissipation parameter for at least a part of the IC device.2. The IC device of claim 1 , wherein the at least one indication of at least one power dissipation parameter comprises at least one static power dissipation parameter value.3. The IC device of claim 2 , wherein the at least one static power dissipation parameter value is/are configured within at least one register accessible by the at least one clock control component.4. The IC device of claim 3 , wherein the at least one ...

SCAN TEST MULTIPLEXING

System and method for performing scan test on multiple IC devices by site-multiplexing. Multiple test sites of an ATE are coupled to multiple DUTs through a multiplexer. A scan test includes a scan-in/out phase and consecutive launch/capture cycles. Each site performs scan in/out in parallel on the corresponding DUT. In each launch/capture cycle, a respective site drives/captures data from a DUT while the remaining sites are inactive. The multiplexer allows the active site to borrow test channels assigned to other test sites such that all the test data of a DUT can be driven /captured in the launch capture cycle despite the test channel limitation of the active test site. As the tester channels receive interleaved data of the multiple sites, each strobe edge of a receive channel is assigned to a particular test site and used to quickly identify a failure site without post-processing test data. 1. A system for testing devices under test (DUTs) , said system comprising:a first test site comprising a first plurality of channels operable to be allocated between first and second DUTs during parallel data capture;a second test site comprising a second plurality of channels operable to be allocated between said first and second DUTs during parallel data capture;a multiplexer operable to selectively couple input/output (I/O) pins of said first DUT or I/O pins of said second DUT to said first and second plurality of channels; and a) said first and second test sites performing scan operations in parallel wherein said first test site performs scan operations with respect to said first DUT and wherein said second test site performs scan operations with respect to said second DUT;', 'b) said first and second test sites performing scan capture of said first DUT while said second DUT is placed on hold and while further said multiplexer couples said first and second plurality of channels to said I/O pins of said first DUT; and', 'c) said first and second test sites performing scan ...

Semiconductor apparatus

A semiconductor apparatus includes a test entry control block configured to generate a plurality of trigger signals and a reset signal according to a test setting command and addresses; and a test entry signal generation block configured to enable a test entry signal when the plurality of trigger signals are sequentially enabled.

Stuck-at fault detection on the clock tree buffers of a clock source

A first clock signal and second clock signal are generated by first and second clock circuits, respectively. A multiplexer selects between the first clock signal and second clock signal to produce a scan clock signal. A non-scan flip flop clocks a data input through to a data output in response to the second clock signal. A scan chain includes a scan flip flop configured to capture the data output from the non-scan flip flop in response to the scan clock signal. The logic state of the captured data in the scan flip flop of the scan chain is indicative of whether the second clock circuit has a stuck-at fault condition (for example, with respect to any one or more included buffer circuits).

Clock jitter measurement circuit and semiconductor device including the same

A circuit for measuring clock jitter includes: an internal signal generator configured to generate an internal clock signal and a single pulse signal, respectively synchronized with an input clock signal; a plurality of delay units being connected in series with each other and configured to generate respective delayed clock signals; a plurality of latch circuits configured to latch the single pulse signal in synchronization with the respective delayed clock signals, and output sampling signals; and a count sub-circuit configured to output a count value resulting from counting a number of active sampling signals of the sampling signals.

Optimized jtag interface

An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations.

POWER CIRCUIT AND TESTING DEVICE

A power circuit and a testing device are provided. A first voltage output circuit of the power circuit provides normal working voltage to electronic device, and a second voltage output circuit provides aging voltage to electronic device. The aging voltage is greater than the normal working voltage, and a controller stores a preset failure rate curve of an electronic device and controls switching of output voltages of the first voltage output circuit and the second voltage output circuit according to the preset failure rate curve. 1. A power circuit , applied to an electronic device , wherein the power circuit comprises:a first voltage output circuit, configured to provide a normal operating voltage to the electronic device;a second voltage output circuit, configured to provide an aging voltage to the electronic device, the aging voltage being greater than the normal operating voltage;a controller, configured to store a preset failure rate curve of the electronic device; anda switch control circuit, configured to switch on/off based on control of the controller according to the preset failure rate curve of the electronic device, to control the first voltage output circuit or the second voltage output circuit to provide a voltage to the electronic device.2. The power circuit according to claim 1 , wherein the switch control circuit comprises a first input terminal claim 1 , a second input terminal claim 1 , a controlled terminal claim 1 , and an output terminal claim 1 , an output terminal of the first voltage output circuit is connected with the first input terminal of the switch control circuit claim 1 , an output terminal of the second voltage output circuit is connected with the second input terminal of the switch control circuit claim 1 , the controlled terminal of the switch control circuit is connected with an output terminal of the controller claim 1 , and the output terminal of the switch control circuit is connected with an input terminal of the electronic ...

AUTO-CALIBRATION CIRCUIT FOR PULSE GENERATING CIRCUIT USED IN RESONATING CIRCUITS

Disclosed is an auto-calibration circuit and method to generate the precise pulses that are required for energy savings achieved by using wide-band resonating cells for digital circuits. The calibration circuit performs a calibration technique by programming the number of PMOS devices and NMOS devices in parallel to an inverter, and these numbers are dynamically changed based on a target reference voltage that is defined by a resistance ratio or any PVT-independent reference voltages could also be set as a target voltage level. 1206206. An auto-calibration circuit () for calibrating a circuit fabricated on Metal-Oxide Semiconductors (MOS) technology providing required calibration to improve the performance of the circuit , wherein said auto-calibration circuit () comprises:{'b': 302', '312', '314, 'an inverter block () that comprises a P-type Metal Oxide Semiconductor (PMOS) () and a N-type Metal Oxide Semiconductor (NMOS) ();'}{'b': 304', '304', '304', '304, 'sub': n', 'p, 'one or more gated inverters (A-N) that obtain first inputs Band Bfrom Digital Memory Counters of the circuit, wherein the one or more gated inverters (A-N) comprises a plurality of PMOS and a plurality of NMOS;'}{'b': 306', '304', '304', '302', '304', '304, 'a first comparator () that is connected with the one or more gated inverters (A-N) that obtains a second input from at least one of the inverter block () or the one or more gated inverters (A-N);'}{'b': 320', '316', '318', '316', '318', '318', '318', '306, 'a NMOS gate () that is connected with a capacitor () and an XOR gate () to charge the capacitor () using a XOR signal (n1x) from the XOR gate (), wherein the XOR gate () generates the XOR signal when the XOR gate () is connected with the first comparator ();'}{'b': 308', '310', '316, 'a second comparator () that obtains input from at least one of a voltage divider () or a capacitor ();'}{'b': 308', '318', '304', '304, 'a PMOS counter that increases the count values when output values of ...

HIGHLY EFFICIENT DOUBLE-SAMPLING ARCHITECTURES

Aggressive technology scaling impacts parametric yield, life span, and reliability of circuits fabricated in advanced nanometric nodes. These issues may become showstoppers when scaling deeper to the sub-10nm domain. To mitigate them various approaches have been proposed including increasing guard-bands, fault-tolerant design, and canary circuits. Each of them is subject to several of the following drawbacks; large area, power, or performance penalty; false positives; false negatives; and in sufficient coverage of the failures encountered in the deep nanometric domain. The invention presents a highly efficient double-sampling architecture, which allow mitigating all these failures at low area and performance penalties, and also enable significant power reduction. 2. The circuit protected against timing errors and parasitic disturbances of claim 1 , wherein: said fourth sampling element is driven by the opposite edge of the same clock signal as said first and second sampling elements delayed by a second predetermined delay claim 1 , say second predetermined delay is equal to said first predetermined delay minus the duration of the high level of said clock signal.3. A circuit protected against timing errors and parasitic disturbances claim 1 , the circuit comprising:a combinatory logic circuit having at least one input and one output;at least a first sampling element having its output connected to said at least one input and activated by the rising edge of a clock signal;at least a second sampling element having its input connected to said at least one output and activated by the rising edge of said clock signal;at least a third sampling element having its input connected to the input of said at least first sampling element and activated by the falling edge of said clock signal;at least a fourth sampling element having its input connected to the input of said at least second sampling element and activated by the falling edge of said clock signal;a comparator circuit ...

Programmable scan shift testing

The disclosed technology facilitates programmable scan shift testing for a scan chain including at least a first segment of scan-flops connected in series with a second segment of scan-flops. The scan chain includes at least a first multiplexor positioned between the first segment and the second segment that is configured to selectively supply scan input from a test controller to the second segment while preventing the second segment from receiving an output of the first segment.

APPARATUS AND METHOD FOR PROVIDING A SUPPLY VOLTAGE TO A DEVICE UNDER TEST USING A CAPACITOR

An apparatus for providing a supply voltage to a device under test includes a controlled source configured to provide a voltage in dependence on one or more control signals; a switchable resistor circuited between the output of the controlled source and a DUT port, having first and second resistances in first and second switch states, respectively, the second resistance being smaller than the first resistance; a regulator configured to provide a control signal to the controlled source, to regulate a voltage to be provided to the DUT in dependence on information about a desired voltage; a capacitor circuited in parallel to the switchable resistor at least during switching of the switchable resistor and configured to slow a voltage change across the switchable resistor which is caused by changing a switch state of the switchable resistor; the apparatus being configured to change a switch state of the switchable resistor while a voltage is provided to the DUT via the switchable resistor. 1. An apparatus for testing , the apparatus comprising: a controlled source configured to provide a voltage at an output based on one or more control signals;', 'a switchable resistor coupled between the output of the controlled source and a device under test, the switchable resistor having a first resistance in a first switch state and a second resistance in a second switch state, wherein the second resistance is smaller than the first resistance;', 'a regulator configured to provide a first control signal to the controlled source, wherein the regulator is further configured to regulate a voltage provided to the device under test based on an information about a desired voltage; and', 'a capacitor coupled in parallel with the switchable resistor during switching of the switchable resistor and configured to slow a voltage change across the switchable resistor, wherein the voltage change is responsive to changing a switch state of the switchable resistor,', 'wherein the circuit is ...

Hybrid automated testing equipment for testing of optical-electrical devices

A hybrid optical-electrical automated testing equipment (ATE) system can implement an optical test assembly that includes an electrical interface and an optical interface with an optical-electrical device under test. The optical assembly can include a socket on which the device is placed by the ATE system to connect electrical and optical connections. The optical connections can couple light through the socket and the optical assembly to one or more testing devices to perform efficient testing of optical devices, such as high-speed optical transceivers.

Optical interconnections for hybrid testing using automated testing equipment

A hybrid optical-electrical automated testing equipment (ATE) system can implement a workpress assembly that can interface with a device under test (DUT) and a load board that holds the DUT during testing, analysis, and calibration. A test hand can actuate to position the DUT on a socket and align one or more alignment features. The workpress assembly can include two optical interfaces that are optically coupled such that light can be provided to a side of the DUT that is facing away from the load board, thereby enabling the ATE system to perform simultaneous optical and electrical testing of the DUT.

REGISTER CIRCUIT WITH DETECTION OF DATA EVENTS, AND METHOD FOR DETECTING DATA EVENTS IN A REGISTER CIRCUIT

A monitor circuit () for monitoring changes in an input digital value of a register circuit comprises a data input () configured to receive a copy of the input digital value of said register circuit, and one or more triggering signal inputs () configured to receive one or more triggering signals. One or more triggering edges thereof define an allowable time limit before which a digital value must appear at a data input of said register circuit to become properly stored in said register circuit. The monitor circuit comprises a data event (DE) output (), so that said monitor circuit is configured to produce a DE signal at said DE output () in response to a digital value at said data input () changing within a time window defined by said one or more triggering signals. 121-. (canceled)22. A monitor circuit for monitoring changes in an input digital value of a register circuit , the monitor circuit comprising:a data input configured to receive a copy of the in-put digital value of said register circuit, andone or more triggering signal inputs configured to receive one or more triggering signals, one or more triggering edges of which define an allowable time limit before which a digital value must appear at a data input of said register circuit to become properly stored in said register circuit, anda data event output, referred to below as DE output;wherein said monitor circuit is configured to produce a data event signal, referred to below as DE signal, at said DE output in response to a digital value at said data input changing within a time window defined by said one or more triggering signals.23. A monitor circuit according to claim 22 , comprising a timing event observation output claim 22 , referred to below as TEO output claim 22 , so that said monitor circuit is configured to produce a timing event observation signal claim 22 , referred to below as TEO signal claim 22 , at said TEO out-put in response to a digital value at said data input changing later than said ...

INTERLEAVED TESTING OF DIGITAL AND ANALOG SUBSYSTEMS WITH ON-CHIP TESTING INTERFACE

The disclosure provides a method and apparatus of interleaved on-chip testing. The method merges a test setup for analog components with a test setup for digital components and then interleaves the execution of the digital components with the analog components. This provides concurrency via a unified mode of operation. The apparatus includes a system-on-chip test access port (SoC TAP) in communication with a memory test access port (MTAP). A built-in self-test (BIST) controller communicates with the MTAP, a physical layer, and a memory. A multiplexer is in communication with the memory and a phase locked loop (PLL) through an AND gate. 1. A method of interleaved on-chip testing , comprising:merging a test setup for analog components and digital components; andinterleaving execution of the digital components and the analog components with the test setup to achieve concurrency via a unified mode of operation.2. The method of claim 1 , in which the interleaving execution comprises performing a memory write operation while waiting for a phase locked loop (PLL) to lock.3. The method of claim 2 , further comprising performing a lock detect and clock check while waiting for data initiation from a transmitter.4. The method of claim 3 , further comprising performing a memory read and a memory status check concurrently with checking for data at a receiver.5. The method of claim 4 , further comprising performing the memory status check after checking for data at the receiver.6. The method of claim 2 , further comprising inputting a write done signal to a multiplexer in response to receiving a read done signal.7. The method of claim 6 , further comprising toggling the multiplexer in response to receiving a phase locked loop signal.8. An apparatus for interleaved on-chip testing claim 6 , comprising:a system-on-chip test access port (SoC TAP) in communication with a memory test access port (MTAP);a built-in self-test (BIST) controller in communication with the MTAP, a physical ...

MULTI-BIT FLIP-FLOPS AND SCAN CHAIN CIRCUITS

A multi-bit flip-flop includes a plurality of multi-bit flip-flop blocks that share a clock signal. Each of the multi-bit flip-flop blocks includes a single inverter and a plurality of flip-flops. The single inverter generates an inverted clock signal by inverting the clock signal. Each of the flip-flops includes a master latch part and a slave latch part and operates the master latch part and the slave latch part based on the clock signal and the inverted clock signal. Here, the flip-flops are triggered at rising edges of the clock signal. Thus, the multi-bit flip-flop operating as a master-slave flip-flop may minimize (or, reduce) power consumption occurring in a clock path through which the clock signal is transmitted. 120-. (canceled)21. A device comprising: a plurality of flip-flops, each of the plurality of flip-flops including a master latch and a slave latch, and', each of the plurality of flip-flops operates using the clock signal and the inverted clock signal,', 'each master latch included in the plurality of multi-bit flip-flop blocks directly receives the clock signal, and', 'each slave latch included in the plurality of multi-bit flip-flop blocks directly receives the clock signal., 'a single inverter configured to receive a clock signal and to generate an inverted clock signal, wherein'}], 'a plurality of multi-bit flip-flop blocks, each of the plurality of multi-bit flip-flop block including,'}22. The device of claim 21 , whereineach master latch included in the plurality of multi-bit flip-flop blocks directly receives the inverted clock signal, andeach slave latch included in the plurality of multi-bit flip-flop blocks directly receives the inverted clock signal.23. The device of claim 21 , whereineach master latch included in the plurality of multi-bit flip-flop blocks directly receives the clock signal that does not pass through the single inverter, andeach slave latch included in the plurality of multi-bit flip-flop blocks directly receives the ...

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals. 1. An integrated circuit die , comprising: (i) a bidirectional data input/output path for a test mode select signal, a test data in signal, and a test data out signal;', '(ii) a clock input lead, and', '(iii) a linking module interface that includes a test mode select output lead, a test data in output lead, a test data out input lead, and a test clock output lead;, '(a) channel circuitry having a channel interface that includes(b) a scan TAP domain connected to combinational logic and having a TAP interface that includes a test mode select input, a test data input, a test clock input, and a test data output; and(c) a BIST TAP domain connected to the combinational logic and having a TAP interface that includes a test mode select input, a test data input, a test clock input, and a test data output; and(d) TAP linking module circuitry having a first interface connected to the linking module interface of the channel circuitry, a second interface connected to the TAP interface of the scan TAP domain, and a third interface connected to the TAP interface of the BIST TAP domain.2. The die of in which the first interface of the TAP linking module includes a test mode select input lead connected to the test mode select output lead claim 1 , a test data in input lead connected to the test data in output lead claim 1 , a test data out output lead connected to the test data out input lead claim 1 , and a test clock input lead connected to the test clock ...

ADAPTING SCAN-BIST ARCHITECTURES FOR LOW POWER OPERATION

A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator , compactor , and controller remain the same as in the known art. The changes between the known art Scan-BIST architecture and the low power Scan-BIST architecture involve modification of the known scan path into scan path , to insert scan paths A , B and C , and the insertion of an adaptor circuit in the control path between controller and scan path 1. An integrated circuit comprising:(a) logic circuitry including a primary input path, a primary output path, stimulus bus leads, and response bus leads; (i) a scan input lead;', '(ii) a scan output lead;', '(iii) a control leads that include a scan enable lead, and a scan clock lead;', (A) first multiplexer circuitry having a response input connected with one response bus lead, a scan in input, a scan enable input and an output;', '(B) hold state multiplexer circuitry having an input coupled with the output of the first multiplexer circuitry, a stimulus input, a control input, and an output; and', '(C) flip-flop circuitry having an input connected with the output of the hold state multiplexer circuitry, a scan clock input, and an output connected with one stimulus bus lead, the stimulus input of the hold state multiplexer circuitry, and a scan out lead;', '(D) the scan cells being serially connected with the scan out lead of one scan cell being connected with the scan in input of the multiplexer circuitry of another scan cell; and', '(E) the scan cells being organized into selectable separate scan paths with the scan in input of the first scan cell of each selectable separate scan path being connected with the scan input lead; and, '(iv) scan cells, each scan cell including, '(v) output buffers, one for each selectable separate scan path, each output buffer having an input connected with the scan out lead of the last scan cell of that selectable separate scan path, a control input, and an output connected with the scan output lead ...

Apparatus and method to debug a voltage regulator

Described is an apparatus which comprises: a first voltage regulator (VR) having a reference input node; and a first multiplexer to provide a reference voltage to the reference input node and operable to select one of at least two different reference voltages as the reference voltage.

Device for detecting margin of circuit operating at certain speed

Disclosed is a device for detecting the margin of a circuit operating at an operating speed. The device includes: a signal generating circuit generating an input signal including predetermined data; a first adjustable delay circuit delaying the input signal by a first delay amount and thereby generating a delayed input signal; a circuit under test performing a predetermined operation based on a predetermined operation timing and thereby generating a to-be-tested signal according to the delayed input signal; a second adjustable delay circuit delaying the to-be-tested signal by a second delay amount and thereby generating a delayed to-be-tested signal; a comparison circuit comparing the data included in the delayed to-be-tested signal with the predetermined data based on the predetermined operation timing and thereby generating a comparison result; and a calibration circuit determining whether the circuit under test passes a speed test according to the comparison result. 1. A device for detecting a margin of a circuit operating at a circuit operating speed , the device comprising:a signal generating circuit configured to generate an input signal including predetermined data at a beginning of a detection process;a first adjustable delay circuit coupled to the signal generating circuit, and configured to delay the input signal by a first delay amount to generate a delayed input signal;a circuit under test (CUT) coupled to the first adjustable delay circuit, and configured to perform a predetermined operation after the beginning of the detection process to generate a to-be-tested signal according to the delayed input signal, wherein the predetermined operation is based on a predetermined operation timing;a second adjustable delay circuit coupled to the CUT, and configured to delay the to-be-tested signal by a second delay amount in the detection process to generate a delayed to-be-tested signal;a comparison circuit coupled to the second adjustable delay circuit, and ...

FLIP FLOP OF A DIGITAL ELECTRONIC CHIP

A flip flop includes a data input, a clock input, a test chain input, a test chain output, a monitoring circuit, and an alert transmission circuit. The monitoring circuit is adapted to generate an alert if the time between arrival of a data bit and a clock edge is less than a threshold. The alert transmission circuit is adapted to apply during a monitoring phase an alert level to the test chain output in the event of an alert generated by the monitoring circuit, and to apply the alert level to the test chain output when an alert level is received at the test chain input. 1. A flip flop circuit comprising:a data input and a clock input;a test chain input and a test chain output;a monitoring circuit configured to generate an alert if a time between arrival of a data bit and a clock edge of a clock signal is less than a threshold; andan alert transmission circuit configured to transmit, during a monitoring phase, an alert level to the test chain output in response to the monitoring circuit issuing the alert, and to apply the alert level to the test chain output in response to the alert level being on the test chain input.2. The flip flop circuit of claim 1 , wherein the alert transmission circuit is configured to maintain the alert level at the test chain output until an arrival of a reset signal at the alert transmission circuit.3. The flip flop circuit of claim 2 , wherein the alert transmission circuit comprises:an OR gate having an input configured to receive the alert and another input coupled to the test chain input; andan asynchronous latch having an input coupled to an output of the OR gate and an output coupled to the test chain output.4. The flip flop circuit of claim 2 , further comprising a control circuit configured to apply a monitoring control signal at a first level to begin the monitoring phase claim 2 , the reset signal corresponding to a second level of the monitoring control signal.5. The flip flop circuit of claim 1 , wherein the monitoring circuit ...

OSCILLATOR, ELECTRONIC DEVICE, AND VEHICLE

An oscillator includes a resonator, a circuit device that is electrically coupled to the resonator and generates a clock signal, and an output terminal that is electrically coupled to the circuit device and outputs the clock signal. The circuit device includes an abnormality detection circuit, and when an abnormal state is detected by the abnormality detection circuit, the circuit device changes a signal characteristic of the clock signal. 1. An oscillator comprising:a resonator;a circuit device that is electrically coupled to the resonator and generates a clock signal; andan output terminal that is electrically coupled to the circuit device and outputs the clock signal, whereinthe circuit device includes an abnormality detection circuit, and the circuit device changes a signal characteristic of the clock signal when an abnormal state is detected by the abnormality detection circuit.2. The oscillator according to claim 1 , whereinwhen the abnormal state is detected, the circuit device changes a duty of the clock signal.3. The oscillator according to claim 2 , wherein an oscillation circuit that causes the resonator to oscillate to generate an oscillation signal,', 'an output circuit that outputs the clock signal based on the oscillation signal, and', 'a reference voltage generation circuit that generates a reference voltage, the output circuit includes a comparator that compares a voltage level of the oscillation signal and the reference voltage to each other, and the duty of the clock signal is changed by changing a voltage level of the reference voltage based on an abnormality detection signal from the abnormality detection circuit., 'the circuit device includes'}4. The oscillator according to claim 1 , whereinwhen the abnormal state is detected, the circuit device changes an amplitude of the clock signal.5. The oscillator according to claim 4 , wherein an oscillation circuit that causes the resonator to oscillate to generate an oscillation signal,', 'an output ...

Method for calibrating channel delay skew of automatic test equipment

The present invention relates to a method for calibrating a channel delay skew of automatic test equipment (ATE), the method comprising: providing multiple calibration reference devices, wherein the calibration reference devices have a second plurality of delay paths each having a predetermined path delay value and coupling a pair of pins of one of the calibration reference devices together, wherein each pin is coupled to at most one delay path; coupling each of the calibration reference devices with the ATE, respectively, wherein the test probe of each of the first plurality of test channels is coupled with a pin of one of the calibration reference devices; testing the calibration reference devices to obtain multiple delay measurements from one or more transmitting channels of the first plurality of test channels to one or more receiving channels of the first plurality of test channels using the ATE; and calculating based on the delay measurements.

APPARATUS FOR DESIGN FOR TESTABILITY OF MULTIPORT REGISTER ARRAYS

In an aspect of the disclosure, a method and an apparatus are provided. The apparatus is a register array including first and second flip-flop latch arrays. The first flip-flop latch array includes a first set of master latches, a first set of slave latches coupled to the first set of master latches, and a first address port. The second flip-flop latch array includes a second set of master latches, a second set of slave latches coupled to the second set of master latches, and a second address port. The register array includes an address counter, coupled to the first flip-flop latch array and the second flip-flop latch array. The address counter is shared by the first flip-flop latch array and the second flip-flop latch array and configured to address, in parallel in a test mode, the first flip-flop latch array through the first address port and the second flip-flop latch array through the second address port. 1. A register array comprising: a first set of master latches;', 'a first set of slave latches coupled to the first set of master latches; and', 'a first address port configured to select a subset of the first set of slave latches to function with the first set of master latches;, 'a first flip-flop latch array including a second set of master latches;', 'a second set of slave latches coupled to the second set of master latches; and', 'a second address port configured to select a subset of the second set of slave latches to function with the second set of master latches, the second address port being different than the first address port; and', 'an address counter, coupled to the first flip-flop latch array and the second flip-flop latch array, the address counter shared by the first flip-flop latch array and the second flip-flop latch array and configurable to address, in parallel in a test mode, the first flip-flop latch array through the first address port and the second flip-flop latch array through the second address port., 'a second flip-flop latch array ...

SEMICONDUCTOR DEVICE

A semiconductor device in which the area of a circuit that is unnecessary during normal operation is small. The semiconductor device includes a first circuit and a second circuit. The first circuit includes a third circuit storing at least one pair of first data including a history of a branch instruction and a first address corresponding to the branch instruction; a fourth circuit comparing a second address of an instruction and the first address; and a fifth circuit selecting the first data of one pair among the at least one pair in accordance with a comparison result. The second circuit includes a plurality of sixth circuits having a function of generating a signal for testing operation of the first circuit in accordance with second data, and a function of storing the at least one pair together with the second circuit after the operation is tested. 1. (canceled)2. An electronic device comprising:a first circuit comprising a first memory; anda second circuit comprising a second memory and a logic array,wherein the first memory is configured to store first data corresponding to a history of a first branch instruction of the first circuit,wherein the second memory is configured to store second data for controlling electrical continuity between circuits in the logic array and an output signal with respect to an input signal of the circuits in the logic array to generate a signal for testing an operating state of the first circuit in a test for the operating state of the first circuit, and third data corresponding to a history of a second branch instruction of the first circuit in normal operation after the test, andwherein the electronic device is at least one of a display device, a personal computer, an image reproducing device, a mobile phone, game machine, a portable information appliance, an e-book reader, a video camera, a digital still camera, a goggle-type display, a head mounted display, an navigation system, an audio reproducing device, a copier, a facsimile ...

TUNING A TESTING APPARATUS FOR MEASURING SKEW

Embodiments herein discuss tuning a testing apparatus to better match the input response of a target system in which a cable will be used. For example, conductors in the cable may have a different skew depending on the system in which they are used. The testing apparatus may be tuned using frequency information regarding the type of signals that will be driven on the cable when installed in the target system. In one embodiment, the testing apparatus uses the frequency information to configure a programmable clock source that can be used to shape a reference clock and control a driver to match the signals in the target system. Using the clock source to modify the reference clock results in the driver outputting a testing signal that better reflects the actual signals that will be transmitted on the cable in the target system. 1. A method comprising:configuring a programmable clock source in a testing apparatus by selecting a configuration of the clock source from a plurality of pre-defined configurations of the clock source, wherein each configuration of the clock source corresponds to a respective frequency response different from frequency responses of other configurations of the clock source, and wherein each of the respective frequency responses represents output power of the clock source relative to frequency;processing a reference clock signal using the configured clock source to generate a modified clock signal;driving a testing signal based on the modified clock signal onto a plurality of conductors; andmeasuring skew associated with the conductors in response to driving the testing signal.2. The method of claim 1 , further comprising:receiving frequency information associated with a target computing system in which the conductors are configured to be used.3. The method of claim 3 , wherein the clock source is configured based on a similarity between the frequency information associated with the target computing system and the frequency response of a ...

ON-THE-FLY TEST AND DEBUG LOGIC FOR ATPG FAILURES OF DESIGNS USING ON-CHIP CLOCKING

A system disclosed herein includes an on-chip clock controller (OCC) circuit receiving a test pattern and responsively generating output clock pulses in response to the test pattern. An OCC test circuit is coupled to the OCC circuit and configured to detect data corresponding to output clock pulses generated by the OCC controller circuit and generate corresponding OCC test outputs. A test output logic circuit is configured to receive the OCC test outputs from the OCC test circuit. A debug controller is operable to configure the test output logic circuit to output the OCC test outputs. 1. A system , comprising:an on-chip clock controller (OCC) circuit receiving a test pattern and responsively generating output clock pulses in response to the test pattern;an OCC test circuit coupled to the OCC circuit and configured to detect data corresponding to output clock pulses generated by the OCC controller circuit and generate corresponding OCC test outputs;a test output logic circuit configured to receive the OCC test outputs from the OCC test circuit; anda debug controller operable to configure the test output logic circuit to output the OCC test outputs.2. The system of claim 1 , wherein the OCC test outputs are based upon the output clock pulses; and wherein the debug controller is operable to configure the test output logic circuit to output the data corresponding to the output clock pulses to one or more output pins.3. The system of claim 1 , further comprising an IR drop test circuit configured to capture second outputs of a plurality of IR hotspot flip-flops located in a design under test (DUT) and provide the second outputs to the test output logic circuit.4. The system of claim 3 , wherein the OCC test outputs are based upon the output clock pulses; and wherein the debug controller is operable to switch configurations of the test output logic circuit from generating the OCC test outputs based on the output clock pulses of the OCC test circuit to generating the OCC ...

PERFORMANCE, THERMAL AND POWER MANAGEMENT SYSTEM ASSOCIATED WITH AN INTEGRATED CIRCUIT AND RELATED METHOD

The performance, thermal and power management system is configured to perform DVFS calibration, temperature compensation adjustment, aging calibration, and DC offset calibration in an IC. The initial voltage supplied to the IC maybe set to an initial value which takes chip-to-chip process variations into account and then dynamically adjusted according to temperature variations, DC offset and/or aging effects. Therefore, the performance, thermal and power management system may achieve optimized thermal and power performance of the IC. 1. A performance , thermal and power (PTP) management system associated with an integrated circuit (IC) , comprising:a performance circuit with adjustable configurations for simulating operations of the IC when receiving a supply voltage having a level set to a predetermined value for a given application use;a sensing module configured to measure a characteristic of the performance circuit;a memory for storing characterization data associated with the IC and the performance circuit, wherein the characterization data includes crossover voltages of the performance circuit in a plurality of configurations; and set the performance circuit in a specific configuration according to the characterization data; and', 'adjust the level of the supply voltage according to the characteristic of the performance circuit., 'a PTP controller configured to2. The PTP management system of claim 1 , wherein:the performance circuit includes a first PTP detector and a second PTP detector having an identical circuitry; power on the first PTP detector during a booting sequence of the IC and power off the first PTP detector after the booting sequence of the IC ends; and', 'power on the second PTP detector according to a system clock based on which the IC operates; and, 'the PTP controller is further configured tothe sensing module is further configured to measure a non-aged performance based on the first PTP detector and measure an aged performance based on the ...

Wafer scale testing using a 2 signal jtag interface

Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuity, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.

METHOD AND DEVICE FOR MONITORING THE RELIABILITY OF AN ELECTRONIC SYSTEM

The invention relates to a method as well as an apparatus configured for its execution for monitoring the reliability of an electronic system, in particular an electronic system comprising one or more electronic components. The method comprises: repeatedly measuring, at different measurement times and according to a predetermined transmission quality measure, a transmission quality of signals transmitted to or from the electronic system over a wired electrical signal transmission path; (ii) comparing, for each of the measurement times, the associated measured transmission quality with a respective associated transmission quality reference value previously determined according to the transmission quality measure; and (iii) determining a value of a reliability indicator associated with the respective measurement time in dependence on the result of the associated comparison In this regard, the transmission quality measure is defined as a measure of the extent of a subrange of a one- or multi-dimensional operating parameter range of the electronic system in which, according to a predetermined reliability criterion, the electronic system operates reliably. 1200100100ab. A method () for monitoring the reliability of an electronic system (; ) , comprising:{'b': 225', '1, 'repeatedly measuring (), at different measurement times (t) and according to a predetermined transmission quality measure, a transmission quality (V) of signals transmitted to or from the electronic system over a wired electrical signal transmission path (L);'}{'b': '245', 'comparing (), for each of the measurement times, the associated measured transmission quality (V) with a respective associated transmission quality reference value (R) previously determined according to the transmission quality measure; and'}{'b': 255', '260, 'determining (, ) a value of a reliability indicator (Z) associated with the respective measurement time in dependence on the result of the associated comparison;'}wherein the ...

ADDRESSABLE TEST ACCESS PORT METHOD AND APPARATUS

The disclosure describes a novel method and apparatus for making device TAPs addressable to allow device TAPs to be accessed in a parallel arrangement without the need for having a unique TMS signal for each device TAP in the arrangement. According to the disclosure, device TAPs are addressed by inputting an address on the TDI input of devices on the falling edge of TCK. An address circuit within the device is associated with the device's TAP and responds to the address input to either enable or disable access of the device's TAP. 1. A device including:(1) a data input terminal, a clock input terminal, a mode input terminal, and a data output terminal;(2) a first circuit having an enable input lead, a first data input lead coupled to the data input terminal, a first mode input lead coupled to the mode input terminal, a first clock input lead coupled to the clock input terminal, and a data output lead coupled to the data output terminal; and(3) a second circuit having an enable output lead coupled to the enable input lead of the first circuit, a second data input lead coupled to the data input terminal, a second mode input lead coupled to the mode input terminal, and a second clock input lead coupled to the clock input terminal.2. The device of claim 1 , wherein:the second circuit enables or disables operation of the first circuit by a logic state on the enable output lead.3. The device of claim 2 , wherein:in response to a first logic state from the enable output lead of the second circuit, the first circuit inputs a first data from the data input terminal on a rising edge of the clock input terminal and outputs a second data to the data output terminal on a falling edge of the clock input terminal.4. The device of claim 2 , wherein:in response to a second logic state from the enable output lead of the second circuit, the first circuit is disabled from inputting a first data from the data input terminal on a rising edge of the clock input terminal and outputting a ...

Measuring delay between signal edges of different signals using an undersampling clock

A system may measure a first sample, of a first signal, using an undersampling signal. The system may measure a second sample, of a second signal, using the undersampling signal. The undersampling signal may have a frequency that is based on a frequency of the first signal or a frequency of the second signal. The system may detect, based on measuring the first sample, a first edge of the first signal. The system may detect, based on measuring the second sample, a second edge of the second signal. The system may determine a delay, associated with the first signal and the second signal, based on detecting the first edge, based on detecting the second edge, based on a first cycle time of the undersampling signal, and based on a second cycle time of the first signal or the second signal.

Measuring power consumption of ciruit component operating in ultra-low power mode

By powering an electronic component operating in an ultra-low power mode from a pre-charged measuring capacitor and measuring the time to discharge the capacitor to a trip voltage level, measurement data can be obtained. In some implementations, the capacitance of the capacitor can be obtained by adding a known current to the unknown current drawn from the capacitor and calculating the capacitance using a mathematical formula.

HARDWARE-BASED LOCAL-STATE RETENTION FAULT DETECTION

Apparatuses of a scan controller include memory and circuitry, where the circuitry is configured to respond to a first signal by sending a second signal to isolate state retention elements from non-state retention elements in a scan chain of power gating circuitry and cycling through the scan chain while obtaining state retention data from the state retention elements during each cycle. The circuitry may be further configured to determine a first error detection code from the state retention data and store the error detection code in the memory. The circuitry may be configured to determine a second error detection code in response to another signal and compare the first error detection code with the second error detection code. The circuitry may be configured to send a signal indicating that the state retention data is corrupted if the first error detection code does not match the second error detection code. 1. An apparatus of a scan controller , the apparatus comprising: in response to a first signal, send a second signal to isolate state retention elements from non-state retention elements in a scan chain of power gating circuitry;', 'cycle through the scan chain obtaining state retention data from the state retention elements;', 'determine an error detection code based on the state retention data;', 'store the error detection code in the memory; and', 'send a third signal, the third signal indicating that the error detection code has been determined., 'memory and circuitry coupled to the memory, the circuitry configured to2. The apparatus of claim 1 , wherein the circuitry is further configured to:send a fourth signal to rejoin the state retention elements and the non-state retention together in the scan chain.3. The apparatus of claim 1 , wherein the error detection code is a first error detection code claim 1 , and wherein the circuitry is further configured to:in response to a fourth signal, send a fifth signal to isolate state retention elements from non- ...

Design-For-Test for Asynchronous Circuit Elements

Various examples of a circuit and a technique for testing the circuit are disclosed herein. In an example, the circuit includes a data input coupled to a scan multiplexer and a path select multiplexer. The circuit further includes a scan-in input coupled to the scan multiplexer and to receive a value of a scan pattern. The circuit further includes a scan latch to store the value that has an input coupled to the scan multiplexer and an output coupled to the path select multiplexer. The scan multiplexer selects a first signal from the data input and the scan-in input and provides the first signal to the input of the scan latch. The path select multiplexer selects a second signal from the data input and the output of the scan latch and provides the second signal to a data output of the circuit.

Pessimism in static timing analysis

The disclosure relates to a method, computer program product or data processing system for performing graph-based static timing analysis, GBA, of an integrated circuit design having a set of timing paths. The method comprises identifying a subset of the set of timing paths and performing path-based analysis, PBA, of the subset of timing paths to determine at least one PBA timing parameter for each timing path of the subset of timing paths. The method further comprises determining at least one optimized GBA timing parameter for at least one timing path of the subset of timing paths by minimizing a function that is based on a difference between the at least one optimized GBA timing parameter and the at least one PBA timing parameter of the at least one timing path.

Electronic anti-tamper device

This invention relates to an anti-tamper assembly for a circuit board comprising one or more electronic components, the assembly comprising: a container having side walls, a first, closed end and a second, opposing, open end, the container being configured to be mounted on said circuit board at said open end, over at least one of said electrical components, to form, in use, a sealed cavity around said at least one of said electrical components; a source of radioactive particles mounted within said container; an image sensor for capturing image frames within said sealed cavity, in use, wherein said image sensor comprises a detector region defining an array of pixels; and a processor for receiving said captured image frames, monitoring said image frames for changes in the statistical distribution of active pixels and, in the event that statistical distribution of active pixels indicates the presence of a feature in an image frame, generating a tamper alert.

Method and device for detecting a deterioration state of a load bearing capacity in a suspension member arrangement for an elevator

A deterioration state of load bearing capacity in an elevator suspension member having a plurality of electrically conductive cords is detected by: providing a multi-phase alternating current circuitry including electrically conductive legs; applying at least one phase of a multi-phase alternating current to at least one of the cords electrically connected to one of the legs; applying at least another phase of the current to at least another cord and at least one resistor electrically connected to at least another leg; measuring an electric indicator current being at least one of a net sum of all phases of the current and an electric bypass current through a neutral wire being connected in parallel to the circuitry, wherein a peak current in each phase is shifted by a phase angle with respect to a peak current in another phase; and determining the deterioration state based on the measured indicator electric current.

JTAG BUS COMMUNICATION METHOD AND APPARATUS

The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state. 1. Communication circuitry comprising:(a) interface leads including a data input lead, a mode select lead, a clock lead, and a data output lead;(b) access port circuitry coupled to the interface leads and including controller circuitry connected to the mode select lead and the clock lead and having control outputs, an instruction register connected to the data input lead and the control outputs, and a data register connected to the data input lead and the control outputs; and(c) serial communication circuitry separate from the access port circuitry, the serial communication circuitry being connected to the mode select lead and to the control outputs to output data to the mode select lead.2. The communication circuitry of including an integrated circuit containing the interface leads claim 1 , the access port circuitry claim 1 , and the serial communication circuitry.3. The communication circuitry of in which the access port circuitry includes multiplexer circuitry coupling the instruction register and the data register to the data output lead claim 1 , and having a control input connected with the control outputs.4. The communication circuitry of in which the instruction register has bus leads for updating and outputting data to other circuits and for capturing data from other circuits.5. The communication circuitry of in which the data register ...

Scan Speed Optimization of Input and Output Paths

Disclosed herein is a scan optimizer system and method designed to generate optimal ATE input/output timing with small margin but yielding stable results. Therefore the scan test time is greatly improved. 1. A scan optimizer system comprising:multiple parallel scan chains; anda provider for providing an optimal combination of timing of said multiple parallel scan chains and scan frequency of said multiple parallel scan chains to maximize throughput;wherein said multiple parallel scan chains comprise an input path and an output path;wherein said provider for providing an optimal combination of timing of said multiple parallel scan chains and scan frequency of said multiple parallel scan chains to maximize throughput comprises a modifier for modifying timing of said input path and said output path; andwherein said provider for providing an optimal combination of timing of said multiple parallel scan chains and scan frequency of said multiple parallel scan chains to maximize throughput is configured to increase an optimal scan frequency by modifying the timing offsets of each individual scan chain to reduce the timing skew between the multiple parallel scan chains, to enable TDO strobe to occur at viable times for all multiple parallel scan chains, and to optimize the data edge positions for the input path.2. The scan optimizer system of claim 1 , wherein said modifier for modifying timing of said input path and said output path comprises a provider for providing a time delay to at least one of said input path and said output path.3. The scan optimizer system of claim 2 , wherein said provider for providing a time delay to at least one of said input path and said output path comprises at least one timing vernier in at least one of said input path and said output path.4. The scan optimizer system of comprising a timing vernier in said input path configured to control TDI input data edge during shift in to position the input data edge near center of a passing range of ...

Functional Testing of an Integrated Circuit Chip

A method of functionality testing system circuitry on an integrated circuit chip, the system circuitry comprising a plurality of sub-circuits and the integrated circuit chip further comprising debugging circuitry, the debugging circuitry comprising variability circuitry. The method comprises: at the system circuitry, performing a function by the sub-circuits performing concurrent actions; at the variability circuitry, altering relative timing of the concurrent actions so as to increase the likelihood of one or more errors in the system circuitry's performance of the function; and at the debugging circuitry, recording one or more errors in the system circuitry's performance of the function. 1. An integrated circuit chip comprising:system circuitry configured to perform a function, the system circuitry comprising a plurality of sub-circuits configured to perform the function by performing concurrent actions;debugging circuitry configured to detect one or more errors in the system circuitry's performance of the function, the debugging circuitry comprising variability circuitry; ["at the variability circuitry, altering relative timing of the concurrent actions so as to increase the likelihood of one or more errors in the system circuitry's performance of the function, wherein the relative timing of the concurrent actions is altered by applying an error to one or more of the concurrent actions; and", 'recording one or more errors., 'wherein the debugging circuitry is configured to functionally test the system circuitry by2. An integrated circuit chip as claimed in claim 1 , wherein the variability circuitry is configured to apply the error where the error is detectable by the system circuitry.3. An integrated circuit chip as claimed in claim 2 , wherein the system circuitry is configured to respond to detecting the error by implementing an accommodating procedure.4. An integrated circuit chip as claimed in claim 3 , wherein the system circuitry is configured to implement ...

HIGH SENSITIVITY DIGITAL VOLTAGE DROOP MONITOR FOR INTEGRATED CIRCUITS

Implementations of the present disclosure involve a system and/or method for measuring on-die voltage levels of an integrated circuit through a digital sampling circuit. In particular, the system and/or method utilize a delay line based analog-to-digital sampling circuit that produces a voltage reading over time, such as at every high frequency clock cycle. In one embodiment, the digital sampling circuit or digital voltage monitor circuit includes a coarse delay component or circuit that further delays the propagation of a clock signal through the delay line. The coarse delay circuit may be programmed to delay the propagation of the signal through the delay line in such a manner as to allow for multiple edges of a clock or test signal to travel simultaneously down the delay line and increase the sensitivity of the circuit. Additional sensitivity of the digital voltage monitor circuit may also be obtained through selection of the types of components that comprise the circuit and a clock jitter monitor circuit configured with a constant supply voltage. 1. A digital voltage monitor circuit of an integrated circuit , the digital voltage monitor circuit comprising: a delay chain comprising a plurality of inverters powered by a supply voltage of the integrated circuit, wherein a speed of propagation of a signal through each of the plurality of inverters is dependent at least on the supply voltage of the integrated circuit; and', 'a plurality of flip-flops each connected to a corresponding inverter in the delay chain, the plurality of flip-flops configured to sample the delay chain on a positive edge of a sample clock signal;', 'wherein the delay chain is configured to propagate a system clock signal for the integrated circuit through the plurality of inverters and the plurality of flip-flops is configured to output an N-bit output value corresponding to a power supply voltage measurement of the integrated circuit, wherein N is an integer larger than zero; and, 'a voltage ...

SEMICONDUCTOR POWER AND PERFORMANCE OPTIMIZATION

Embodiments are directed to a method and system for testing and optimizing integrated circuit devices. Latches within an integrated circuit device that fail to operate properly are found using observed data from a test. Thereafter, a directed graph of the layout of the integrated circuit is used to find clock controllers that feed into the latches. The clock controllers that are the most likely to be at issue are ranked, then testing can be performed to confirm that a critical path can be found. The critical path can be excluded from further power optimization to maintain the performance of the integrated circuit device. Other embodiments are also disclosed. 1. A computer-implemented method comprising:examining, by a processor, fail data of an integrated circuit device to determine which latches of the integrated circuit device are underperforming;analyzing, by the processor, a directed graph of the integrated circuit device to find clock controllers that feed into the latches that are underperforming;creating, using the processor, a test plan to test the clock controllers; andperforming, using the processor, the test plan to find the clock controllers that are in a critical path.2. The computer-implemented method of further comprising:testing a proposed solution to the clock controllers in the critical path; andwriting the proposed solution to a vital product data (VPD).3. The computer-implemented method of wherein claim 2 , the proposed solution is a timing correction to the clock controllers in the critical path.4. The computer-implemented method of wherein claim 2 , the VPD comprises a set of operating parameters applied to the integrated circuit device prior to operation.5. The computer-implemented method of claim 1 , wherein the test plan to test the clock controllers tests the clock controllers in order of a likelihood of the clock controller being part of the critical path.6. The computer-implemented method of further comprising:using a performance screen ...

LOGIC BUILT-IN SELF-TEST (LBIST) WITH PIPELINE SCAN ENABLE LAUNCH ON SHIFT (LOS) FLIP-FLOP CIRCUIT

A logic built-in self-test (LBIST) circuit implements a pipeline scan enable launch on shift (LOS) feature. A first scan chain flip-flop has a scan enable input configured to receive a first scan enable signal. A logic circuit has a first input coupled to a data output of the first scan chain flip-flop and a second input coupled to receive the first scan enable signal. A second scan chain flip-flop has a scan input coupled to a scan output of the first scan chain flip-flop. A scan enable input of the second scan chain flip-flop is coupled to receive a second scan enable signal generated at an output of the logic circuit. The first and second scan chain flip-flops are clocked by a same clock signal. 1. A circuit , comprising:a first flip-flop having a data input, a scan input, a data output and a scan output, said first flip-flop clocked by a clock signal and having a scan enable input configured to receive a first scan enable signal;a logic circuit having a first input coupled to the data output of the first flip-flop and a second input coupled to receive the first scan enable signal; anda second flip-flop having a data input, a scan input, a data output and a scan output, said scan input of the second flip-flop coupled to the scan output of the first flop-flop, said second flip-flop clocked by the clock signal and having a scan enable input configured to receive a second scan enable signal generated at an output of the logic circuit.2. The circuit of claim 1 , wherein the logic circuit is a logic OR gate having a first input connected to the data output of the first flip-flop and a second input connected to receive the first scan enable signal and an output connected to the scan enable input of the second flip-flop.3. The circuit of claim 1 , further comprising a combinatorial logic circuit having an output coupled to the data input of the second flip-flop.4. The circuit of claim 1 , further comprising a combinatorial logic circuit having an input coupled to the ...

GATING TAP REGISTER CONTROL BUS AND AUXILIARY/WRAPPER TEST BUS

In a first embodiment a TAP of IEEE standard 1149.1 is allowed to commandeer control from a WSP of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface. 1. An integrated circuit comprising:(a) a TDI lead, a TDO lead, a TMS lead, and a TCK lead;(b) a test access port controller having inputs connected to the TMS and TCK leads and having a CaptureDR output, a ShiftDR output, and an UpdateDR output;(c) instruction register circuitry having a Mode-2 output and an ATC enable output, the instruction register circuitry including a first gate with a gated CaptureDR input and a Capture-2 output, a second gate having a ShiftDR input coupled to the ShiftDR output and a Shift-2 output, and a third gate with a gated UpdateDR input and an Update-2 output;(d) data register circuitry having a TDI input connected to the TDI lead, a TDO output selectively coupled to the TDO lead, a Mode-2 input coupled to the Mode-2 output, a Clock-2 input coupled to the TCK lead, a Shift-2 input coupled to the Shift-2 output, and an Update-2 input coupled to the Update-2 output; and(e) ATC gating circuitry having an ATC enable input connected to the ATC enable output, a CaptureDR input coupled to the CaptureDR output, a Capture input, and a gated CaptureDR output coupled to the gated CaptureDR input.2. The integrated circuit of in which the Capture input is part of an auxiliary test control bus of leads that includes a Clock lead claim 1 , a Shift lead claim 1 , an Update lead claim 1 , a Transfer lead claim 1 , a Reset lead claim 1 , a Select lead claim 1 , a WSI lead claim 1 , and a WSO lead.3. The ...

OPTO ELECTRICAL TEST MEASUREMENT SYSTEM FOR INTEGRATED PHOTONIC DEVICES AND CIRCUITS

An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data. 1. An integrated circuit including a testing circuit , said testing circuit comprising an optical test circuit having:an optical input configured to receive an optical test signal;a test channel configured to receive said optical test signal and produce an optical test output signal in response to processing of the optical test signal through at least one optical device under test circuit, said test channel further including a photodetector coupled to receive said optical test output signal and generate an electrical signal; andan electrical output for outputting said electrical signal.2. The integrated circuit of claim 1 , wherein the test channel comprises a plurality of series coupled optical device under test circuits.3. The integrated circuit of claim 1 , wherein the test channel comprises a further photodetector coupled to receive optical test signal and generate a further electrical signal claim 1 , the optical test circuit further including a further electrical output for outputting said further electrical signal.4. The integrated circuit of claim 1 , wherein the test channel comprises a further photodetector coupled to receive the optical test output signal and generate a further electrical signal claim 1 , the ...

SYSTEMS AND/OR METHODS FOR ANOMALY DETECTION AND CHARACTERIZATION IN INTEGRATED CIRCUITS

Systems, methods, and computer readable medium described herein relate to techniques for characterizing and/or anomaly detection in integrated circuits such as, but not limited to, field programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). In one example aspect of certain example embodiments, a fully digital technique relies on the pulse width of signals propagated through a path under test. In another example aspect, the re-configurability of the integrated circuit is leveraged to combine the pulse propagation technique with a delay characterization technique to yield better detection of certain type of Trojans and the like. Another example aspect provides for running the test through reconfigurable path segments in order to isolate and identify anomalous circuit elements. Yet another example aspect provides for performing the characterization and anomaly detection without requiring golden references and the like. 1. A system for characterizing and/or testing a circuit , comprising:a pulse generator incorporated in the circuit and coupled to at least one active signal path in the circuit at a signal input thereof, the pulse generator being configured to generate a sequence of pulses of varying pulse widths for propagation through the at least one active signal path; anda pulse detector incorporated in the circuit and coupled to a signal output of the at least one active signal path and configured to detect respective pulses in the sequence of pulses propagated through the at least one active signal path.2. The system of claim 1 , wherein the pulse generator is configured to generate the pulses by logically combining two clock signals generated by existing clock generation circuitry within the circuit being characterized and/or tested.3. The system of claim 1 , wherein the pulse generator is configured to generate the pulses by ANDing two clock signals from clocks of the circuit.4. The system of claim 3 , wherein the two clocks are ...

System, Apparatus And Method For Functional Testing Of One Or More Fabrics Of A Processor

In one embodiment, an apparatus includes at least one fabric to interface with a plurality of intellectual property (IP) blocks of the apparatus, the at least one fabric including at least one status storage, and a fabric bridge controller coupled to the at least one fabric. The fabric bridge controller may be configured to initiate a functional safety test of the at least one fabric in response to a fabric test signal received during functional operation of the apparatus, receive a result of the functional safety test via the at least one status storage, and send to a destination location a test report based on the result. Other embodiments are described and claimed. 1. An apparatus comprising:at least one fabric to interface with a plurality of intellectual property (IP) blocks of the apparatus, the at least one fabric including at least one status storage; anda fabric bridge controller coupled to the at least one fabric, the fabric bridge controller to initiate a functional safety test of the at least one fabric in response to a fabric test signal received during functional operation of the apparatus, receive a result of the functional safety test via the at least one status storage, and send to a destination location a test report based on the result.2. The apparatus of claim 1 , further comprising a first sideband router coupled to the at least one fabric and the fabric bridge controller claim 1 , wherein the first sideband router is to receive the result of the functional safety test and send to the fabric bridge controller the result of the functional safety test.3. The apparatus of claim 1 , wherein the fabric bridge controller comprises a pseudo-random number generator to generate one or more test patterns based on a seed value claim 1 , wherein the fabric bridge controller is to send the one or more test patterns to the at least one fabric.4. The apparatus of claim 3 , wherein the fabric bridge controller is to send a first transaction to the at least one ...

SCAN TEST METHOD AND APPARATUS

The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device using the falling edge of a test/scan clock. The signals are provided on device leads that are also used to provide signals to scan test architectures using the rising edge of the test/scan clock. According to the disclosure, device test leads serve to input different test signals on the rising and falling edge of the test/scan clock which reduces the number of interconnects between a tester and the device under test. 1. A device comprising:(a) a scan data input;(b) a test clock input;(c) a test mode select input;(d) test access port circuitry having an input coupled to the test clock input, an input coupled to the test mode select input, a scan clock output, and a control output;(e) a scan register having an input coupled to the scan data input, an input coupled to the scan clock output, a gated scan enable input, and a scan output;(f) an inverter having an input coupled to the test clock input and an inverted test clock output;(g) an expected data flip flop having an input coupled to the scan data input. an input coupled to the inverted test clock output, and an expected data output;(h) a second flip flop having an input coupled to the test mode select input, an input coupled to the inverted test clock output, and a data output;(i) gate circuitry having an input coupled to the data output of the second flip flop, an input coupled to the control output, and a gated scan enable output coupled to the gated scan enable input; and(j) compare circuitry having a first input coupled to the scan output of the scan register and a second input coupled to the expected data output.2. The device of including combinational logic having parallel stimulus inputs and parallel response outputs and in which the scan register includes parallel stimulus outputs coupled to the parallel stimulus inputs and parallel response inputs ...