IC device authentication using energy characterization

Systems, methods, and apparatuses are described for verifying the authenticity of an integrated circuit device. An integrated test apparatus may use quiescent current and/or conducted electromagnetic interference readings to determine if a device under test matches the characteristics of an authenticated device. Deviations from the characteristics of the authenticated device may be indicative of a counterfeit device.

Method And Apparatus For Transferring Hidden Signals In A Boundary Scan Test Interface

An apparatus, which comprises a state detector, and a method for transferring hidden signals in a boundary scan test interface is disclosed. The invalid state transition loop, fig. 4, in the state transition diagram of the boundary scan test interface is used to transfer hidden signals without inputting signals though the standard input / output pins. An input, TMS, of the state transition diagram of the boundary scan test interface is initially monitored and an output of a first data is generated when a first predetermined input stream conforming to the invalid state transition loop is detected. An output of a second data is then generated when a second predetermined input stream is detected. The second predetermined input stream is different from the first one and also conforms to the invalid state transition loop. The boundary scan test interface may be a JTAG interface, IEEE 1149.1 interface or IEEE 1149.4 interface, and the state transition diagram may be in a test access port (TAP ...

Detection of pulse width tampering of signals

Method and apparatus for transferring hidden signals in a boundary scan test interface

Method And Apparatus For Accessing Hidden Data In A Boundary Scan Test Interface

An apparatus and method for accessing hidden data in a boundary scan test interface is disclosed. The apparatus comprises a state detector, a shift register, a hidden register 37 and a comparison device. The invalid state transition loop, fig. 4, in the state transition diagram of the boundary scan test interface is used to transfer hidden signals without inputting signals through the standard input / output pins. An input, TMS, of the state transition diagram of the boundary scan test interface is initially monitored and an output of a first data is generated when a first predetermined input stream conforming to the invalid state transition loop is detected. An output of a second data is then generated when a second predetermined input stream is detected. The second predetermined input stream is different from the first one and also conforms to the invalid state transition loop. A combination of the first and second output data is stored in the shift register. An input key included in ...

Robust secure testing of integrated circuits

A method includes configuring a first set of blocks of a plurality of blocks of an IC chip as secure data blocks, and configuring a second set of blocks of the plurality of blocks as non-secure data blocks. The method further includes receiving a test mode entry request in the IC chip. In response to the IC chip receiving the test mode entry request, carrying out a data-initialization operation on the plurality of blocks independently of whether any blocks of the plurality of blocks are configured as the secure data blocks or the non-secure data blocks. An IC chip data output is disabled during the data-initialization operation.

JTAG lockout with dual function communication channels

A Joint Test Action Group (JTAG) communication lockout processor is disclosed. The processor is configured to generate a unlock sequence based on an operational mode change of an operably connected programmable device, and save the unlock sequence to one or more memory registers. The processor can also receive an execution of the unlock sequence via a dual function JTAG communication bus, determine, via an unlock logic, whether the execution of the unlock sequence is valid, and responsive to determining that the execution of the unlock sequence is valid, allow or disallow the JTAG communication with an embedded processor.

Conditional access chip, built-in self-test circuit and test method thereof

ELECTRONIC SYSTEM, SYSTEM DIAGNOSTIC CIRCUIT AND OPERATION METHOD THEREOF

Electronic system, system diagnostic circuit and operation method thereof

An electronic system, a system diagnostic circuit, and an operation method thereof are provided. The system diagnostic circuit includes a data register circuit, an instruction register circuit, a diagnostic controller circuit, a control register circuit, and a detect circuit. The diagnostic controller circuit determines to transmit test data to the instruction register circuit or the data register circuit according to an operating state. The detect circuit update the control register circuit when the first test data transmitted to the data register circuit meets a predefined pattern.

디스에이블된 센시티브 모드를 갖는 전자 디바이스를 제작하는 방법, 및 그러한 전자 디바이스를 변환하여 그것의 센시티브 모드를 재활성화시키기 위한 방법

... 방법은, 새로운 센시티브 사용을 위해, 제1 식별자에 연관되고, 제작 이후에 디스에이블된 센시티브 모드를 갖는 보안 전자 디바이스(CH)를 변환하도록 의도된다. 본 방법은 다음 단계들, (i) 미리 결정된 보안키 및 제1 식별자가 공급된 미리 결정된 함수를 이용하여 제1 식별자의 암호를 외부적으로 연산하는 단계, (ii) 외부적으로 연산된 제1 식별자의 암호를 나타내는 활성 패턴(AS)을 형성하기 위해 전자 디바이스(CH)의 액세스 가능한 금속 층(ML)을 변환하는 단계, (iii) 활성 패턴을 나타내는 값을 전자 디바이스(CH)에 입력하는 단계, (iv) 보안키 및 이러한 값을 미리 결정된 함수의 역함수에 공급하여 변환된 전자 디바이스(CH)로 제2 식별자를 연산하고, 제2 식별자가 제1 식별자와 동일한 경우에 센시티브 모드로의 복귀를 트리거하는 단계를 포함한다.

Using Embedded Time-Varying Code Generator to Provide Secure Access to Embedded Content in an On Chip Access Architecture

A network of storage units has a data path, which is at least a portion of the network. The network also has a dynamic time-varying or cycle-varying code generation unit and a code comparator unit that together make up an unlock signal generation unit; and a gateway storage unit. If the gateway storage unit does not store an unlock signal or the unlock signal generation unit does not generate and transmit an unlock signal, the gateway storage unit does not insert a data path segment in the data path. If the unlock signal generation unit is operated such that it generates an unlock signal, and it transmits that unlock signal to a gateway storage unit, and the gateway storage unit stores the unlock signal value, then the gateway storage unit inserts a data path segment into the data path.

Detection of pulse width tampering of signals

A sensor system can include a sensor having a charge storage device controllably connected to a voltage source under control of a signal under test; and a readout circuit coupled to the charge storage device to determine whether the pulse width of the signal under test has changed greater than a threshold amount according to a voltage at the charge storage device. In some cases, the determination of whether the pulse width of the signal under test has changed can include determining whether the voltage satisfies a condition with respect to a comparison voltage. In some cases, the determination of whether the pulse width of the signal under test has changed can be based on a propagation delay through a delay chain, where the propagation delay is dependent on the voltage.

Method and apparatus for accessing hidden data in a boundary scan test interface

RECONFIGURABLE JTAG ARCHITECTURE FOR IMPLEMENTATION OF PROGRAMMABLE HARDWARE SECURITY FEATURES IN DIGITAL DESIGNS

A reconfigurable JTAG includes, in part, a core logic, a boundary scan chain cell, one or more reconfigurable blocks (RBs), and a reconfigurable block (RB) programming module. The RBs may include, in part, one or more reconfigurable boundary scan chain blocks (RBB) adapted to couple the boundary scan chain cell to the core logic and to input/output (I/O) ports of the reconfigurable JTAG. The RBs may also include, in part, one or more additional reconfigurable logic (ARL) blocks to provide enhanced logic for locking operations. The RB programmable module may communicate with a memory storing data for configuring the RBBs and ARLs. The RB programming module may configure the RBBs and ARLs based at least in part on the data stored in the memory to disable access to the I/O ports of the JTAG. The RB programming module may configure the RBBs to encrypt the I/O ports in accordance with a cipher algorithm. The RB programming module may also configure the RBBs and ARLs to compare a counter's count to a predefined time and lock the I/O ports after an expiration of the predefined time.

Verfahren und Vorrichtung zur Übertragung versteckter Signale in einer BoundaryScan Testschnittstelle

Eine Vorrichtung und ein Verfahren zur Übertragung versteckter Signale in einer Boundary Scan Testschnittstelle wird offenbart, die eine Ungültiger-Zustandsübergang-Schleife in einer Boundary Scan Testschnittstelle definiert und anfänglich eine Eingabe des Zustandsübergangsdiagramms der Boundary Scan Testschnittstelle überwacht, so dass eine Ausgabe von ersten Daten erzeugt wird, wenn ein erster vorbestimmter Eingabestrom entdeckt wird, der mit der Ungültiger-Zustandsübergang-Schleife konform geht, und dann eine Ausgabe von zweiten Daten erzeugt wird, wenn ein zweiter vorbestimmter Eingabestrom entdeckt wird, wobei der zweite vorbestimmte Eingabestrom vom ersten verschieden ist und auch mit der Ungültiger-Zustandsübergang-Schleife konform geht.

Method and apparatus for transferring hidden signals in a boundary scan test interface

Method and apparatus for accessing hidden data in a boundary scan test interface

SECURE SCAN

Programmable circuits for correcting scan-test circuitry defects in integrated circuit designs

In certain embodiments, an integrated circuit has scan-test circuitry that performs scan testing on circuitry under scan test (CUST) within the IC, where the scan-test circuitry is susceptible to a defect. In order to enable the defect to be corrected after it occurs, the scan-test circuitry includes a set of programmable circuitry connected to provide a signal to other circuitry (e.g., a scan chain) within the scan-test circuitry, where the set of programmable circuitry includes one or more configurable memory cells connected to control the programming of the set of programmable circuitry. The memory cell(s) can be configured to program the set of programmable circuitry to enable the scan testing to be performed without modification. The memory cell(s) can also be configured to program the set of programmable circuitry to modify the scan testing to correct the defect in the scan-test circuitry.

SYSTEM ON CHIP AND SECURE DEBUGGING METHOD

A system on chip (SoC) is provided. The system on chip includes a multiprocessor that includes multiple processors, a debugging controller that includes a debug port and retention logic configured to store an authentication result of a secure joint test action group system, and a power management unit configured to manage power supplied to the multiprocessor and the debugging controller. The power management unit changes the debug port and the retention logic into an alive power domain in response to a debugging request signal.

PROCESSOR SWITCHABLE BETWEEN TEST AND DEBUG MODES

A processor includes a TCU TAP for access of a TCU for running functional tests and a DAP TAP for access of a debugger. A TAP selection module selects reversibly TAP access by default through the TCU TAP when the processor is a bare die, or by default through the DAP TAP when the processor is packaged, the selection of TAP access being reversible by the TCU. The processor also includes a fuse for irreversibly disabling the selection by the TAP selection module of the TAP access by default through the TCU TAP. Functional tests on bare dies are run with a TCU probing the dies through the TCU TAP by default. Packaged engineering samples can be supplied for debugging with the DAP TAP selected by default, but access possible for the TCU through the TCU TAP.

DYNAMIC SECRET KEY SECURITY SYSTEM FOR TEST CIRCUIT AND METHOD OF THE SAME

A dynamic secret key security system for test circuit and a method of the same are disclosed. The security architecture includes a scan chain set, a dynamic key generator, a secret key checking logic, a fake response generator, and a controller. Scan chains of the scan chain set receive a test vector while the dynamic key generator produces different secret keys according to the test vector received. The secret key checking logic is used for comparing the test vector with the secret key so as to know whether they are the same. Thus whether the test vector being input is legal can be learned. Thereby the present dynamic secret key generation technique provides higher security level. Moreover, the secret key will not be stored in the memory in advance so that attackers cannot get the secret key through attacks on the memory.

Method and apparatus for switchably selecting an integrated circuit operating mode

A method and circuit for preventing external access to secure data of an integrated circuit while supporting DFT is disclosed. In accordance with the method the integrated circuit is automatically placed into the test mode at integrated circuit power-up from a power-down state. At power up, secure data is other than present within a secure data-path of the integrated circuit. Access is provided to the secure data path via a second data path coupled with the first secure data-path. Via the access path, data other than secure data is provided to the integrated circuit, the data for performing test functions of the integrated circuit operating in the test mode. Once data other than secure data is provided to first secure data path, the test mode is terminated and access via other than the secure ports is disabled. The test mode is only re-entered by powering down the integrated circuit and re-initialising it.

Device and method for detecting points of failures

Devices, methods, and computer program products for detecting Points Of Failures in an integrated circuit (IC) are provided. The integrated circuit device is described by a structural description ( 2 ) comprising a plurality of elements, the elements representing cells and wires interconnecting the cells, the structural description further comprising portions representing a set of sensitive functional blocks ( 16 ), each sensitive functional block comprising one or more inputs, at least one sensitive output, and a set of elements interconnected such that the value of the sensitive output is a Boolean function of the input values of the sensitive functional block. The detection device ( 100 ) comprises: a selection unit ( 101 ) configured to iteratively select a n-tuple of elements in at least the portions of the netlist corresponding to said sensitive functional blocks, a testing unit ( 104 ) configured to test each selected n-tuple of elements, the testing unit being configured to: modify said selected n-tuple of elements from an initial state to a testing state; determine if the derivative of the Boolean function associated with each sensitive functional block is equal to zero. The detection device ( 100 ) is configured to detect that said n-tuple represents a Point Of Failure of order n in the integrated circuit (IC) device if the derivative of the Boolean function associated with said sensitive functional block is equal to zero.

IC Device Authentication Using Energy Characterization

Systems, methods, and apparatuses are described for verifying the authenticity of an integrated circuit device. An integrated test apparatus may use quiescent current and/or conducted electromagnetic interference readings to determine if a device under test matches the characteristics of an authenticated device. Deviations from the characteristics of the authenticated device may be indicative of a counterfeit device.

Ein-Chip-System und sicheres Debugging-Verfahren

Ein Ein-Chip-System (100, 200, 300, 400) ist vorgesehen. Das Ein-Chip-System (100, 200, 300, 400) weist einen Multiprozessor (110, 210, 310, 410), welcher mehrere Prozessoren (111, 112, 211–21N, 311–31N, 411–41N) aufweist, einen Debugging-Controller, welcher einen Debug-Anschluss (231, 331, 431) und eine Retentionslogik (336, 436) aufweist, welche konfiguriert ist, um ein Authentifizierungsergebnis eines sicheren Joint Test Action Group(JTAG)-Systems (232, 332, 432) zu speichern, und eine Leistungsverwaltungseinheit (120, 220, 320, 420) auf, welche konfiguriert ist, um Leistung, welche dem Multiprozessor (110, 210, 310, 410) und dem Debugging-Controller zugeführt wird, zu verwalten. Die Leistungsverwaltungseinheit (120, 220, 320, 420) ändert den Debug-Anschluss (231, 331, 431) und die Retentionslogik (336, 436) in eine spannungsführende Leistungsdomäne in Antwort auf ein Debugging-Anforderungssignal.

INTEGRATED CIRCUIT WITH SECURE SCAN ENABLE

An integrated circuit senses attempts to access security-related data stored in registers connectable into a scan chain when the attempt includes locally and selectively asserting a scan-enable signal at a corresponding branch of the scan-enable tree when the integrated circuit is in a secure functional mode. When such an attempt is detected, the integrated circuit (i) generates a security warning that causes a reset of the security-related data and/or (ii) engages a bypass switch to disconnect the scan chain from the respective output terminal to preclude the security-related data from being shifted out of the IC via the scan chain.

TEST CIRCUIT USING CLOCK GATING SCHEME TO HOLD CAPTURE PROCEDURE AND BYPASS MODE, AND INTEGRATED CIRCUIT INCLUDING THE SAME

Disclosed is a test circuit for testing an integrated circuit core or an external circuit of the integrated circuit core. The test circuit may not only transmit a cell function input to a cell function output using only one multiplexer in a bypass mode, may but also use a clock gating scheme capable of blocking a clock signal from transmitting to a scan flip-flop to hold a capture procedure.

Verfahren und Vorrichtung zur Übertragung versteckter Signale in einer Boundary Scan Testschnittstelle

Vorrichtung zur Übertragung versteckter Signale unter Verwendung einer Boundary Scan Testschnittstelle, wobei die Boundary Scan Testschnittstelle mit einem vorbestimmten Zustandsübergangsdiagramm arbeitet, um auf der Grundlage einer Eingabe Zustandsübergänge durchzuführen, worin mindestens eine Ungültiger-Zustandsübergang-Schleife in dem vorbestimmten Zustandsübergangsdiagramm vorgesehen ist und, die Vorrichtung umfasst: einen Zustandsdetektor (51), zur Überwachung der Eingabe, um erste Daten auszugeben, wenn ein erster vorbestimmter Eingabestrom entdeckt wird, und dann zweite Daten auszugeben, wenn ein zweiter vorbestimmter Eingabestrom entdeckt wird, worin der erste und der zweite vorbestimmte Eingabestrom unterschiedlichen Eingabeströmen der Ungültiger-Zustandsübergang-Schleife entsprechen.

Electronic system, system diagnostic circuit and operation method thereof

Device having secure JTAG and debugging method for the same

A method of debugging a device which includes a plurality of processors is provided. The method includes verifying a request to initiate authentication that is provided to the device to a user; performing a challenge-response authentication operation between the user and the device in response to the request to initiate authentication being a request from a non-malicious user; activating or deactivating an access to a Joint Test Action Group (JTAG) port of each of the processors, based on access control information from the user; and permitting a debugging operation via an access that is activated.

System on chip and secure debugging method

本揭露提供一種系統晶片(SOC)。所述系統晶片包括： 多處理器，包括多個處理器；偵錯控制器，包括偵錯埠及用以儲存安全聯合測試工作群組系統的認證結果的保持邏輯；以及電力管理單元，用以管理被供應至所述多處理器及所述偵錯控制器的電力。所述電力管理單元因應於偵錯請求訊號而將所述偵錯埠及所述保持邏輯改變至活動電力域。

Circuit with design-for-test element

Various examples of a circuit and a technique for testing the circuit are disclosed herein. In an example, the circuit includes a data input coupled to a scan multiplexer and a path select multiplexer. The circuit further includes a scan-in input coupled to the scan multiplexer and to receive a value of a scan pattern. The circuit further includes a scan latch to store the value that has an input coupled to the scan multiplexer and an output coupled to the path select multiplexer. The scan multiplexer selects a first signal from the data input and the scan-in input and provides the first signal to the input of the scan latch. The path select multiplexer selects a second signal from the data input and the output of the scan latch and provides the second signal to a data output of the circuit.

Using embedded time-varying code generator to provide secure access to embedded content in an on chip access architecture

A network of storage units has a data path, which is at least a portion of the network. The network also has a dynamic time-varying or cycle-varying code generation unit and a code comparator unit that together make up an unlock signal generation unit; and a gateway storage unit. If the gateway storage unit does not store an unlock signal or the unlock signal generation unit does not generate and transmit an unlock signal, the gateway storage unit does not insert a data path segment in the data path. If the unlock signal generation unit is operated such that it generates an unlock signal, and it transmits that unlock signal to a gateway storage unit, and the gateway storage unit stores the unlock signal value, then the gateway storage unit inserts a data path segment into the data path.

ENABLING SECURED DEBUG OF AN INTEGRATED CIRCUIT

Secured debug of an integrated circuit having a test operation mode and a secure mission operation mode. The integrated circuit has a processing unit, a test interface through which the test operation mode is controllable, an on-chip memory which is accessible in the test operation mode and in the secure mission operation mode, and one or more protected resources inaccessible in the test operation mode. The processing unit is configured, in the test operation mode, to receive an authenticated object through the test interface, and store the received authenticated object in the on-chip memory. The processing unit is moreover configured, upon reset into the secure mission operation mode, to execute a boot procedure to determine that the authenticated object is available in the on-chip memory, authenticate the authenticated object, and—upon successful authentication—render the more protected resources accessible to a debug host external to the integrated circuit.

JTAG LOCKOUT WITH DUAL FUNCTION COMMUNICATION CHANNELS

A Joint Test Action Group (JTAG) communication lockout processor is disclosed. The processor is configured to generate a unlock sequence based on an operational mode change of an operably connected programmable device, and save the unlock sequence to one or more memory registers. The processor can also receive an execution of the unlock sequence via a dual function JTAG communication bus, determine, via an unlock logic, whether the execution of the unlock sequence is valid, and responsive to determining that the execution of the unlock sequence is valid, allow or disallow the JTAG communication with an embedded processor.

System and apparatus for trusted and secure test ports of integrated circuit devices

A trusted boot device secures JTAG scan chains of integrated circuit components on a circuit card assembly without necessarily modifying the integrated circuit components. Component JTAG port I/O scan chain signal pins are independently routed to FPGA fabric on the trusted boot device. The trusted boot device monitors the JTAG paths and triggers a security event if unauthorized activity is detected on a JTAG path. JTAG paths on the secure trusted boot device are latch disabled by default and upon detection of a security event. JTAG paths are only enabled for a predefined length of time. To prevent JTAG access when protected data is exposed, a watchdog timer latch disables the JTAG paths when the predefined time has expired and may trigger a security event if activity is detected after the time has expired. A power cycle is then used to re-enable authenticated JTAG enable requests.

Secure low pin count scan

A contactless smartcard type integrated circuit needing only two pins for performing a standard ATPG test is disclosed. A scan test may be performed using one pin for the clock and the other pin for the input and input of the scan test data. Additionally, security is enhanced by using an embedded signature generator to avoid observation of the data shifted out.

Secure device state apparatus and method and lifecycle management

A semiconductor chip device include device state fuses that may be used to configure various device states and corresponding security levels for the semiconductor chip as it transitions from wafer manufacturing to provisioned device. The device states and security levels prevent the semiconductor chip from being accessed and exploited, for example, during manufacturing testing. A secure boot flow process for a semiconductor chip over its lifecycle is also disclosed. The secure boot flow may start at the wafer manufacturing stage and continue on through the insertion of keys and firmware.

Integrated circuit with secure scan enable

An integrated circuit senses attempts to access security-related data stored in registers connectable into a scan chain when the attempt includes locally and selectively asserting a scan-enable signal at a corresponding branch of the scan-enable tree when the integrated circuit is in a secure functional mode. When such an attempt is detected, the integrated circuit (i) generates a security warning that causes a reset of the security-related data and/or (ii) engages a bypass switch to disconnect the scan chain from the respective output terminal to preclude the security-related data from being shifted out of the IC via the scan chain.

The safe low pins scanning

Robust secure testing of integrated circuits

A method includes configuring a first set of blocks of a plurality of blocks of an IC chip as secure data blocks, and configuring a second set of blocks of the plurality of blocks as non-secure data blocks. The method further includes receiving a test mode entry request in the IC chip. In response to the IC chip receiving the test mode entry request, carrying out a data-initialization operation on the plurality of blocks independently of whether any blocks of the plurality of blocks are configured as the secure data blocks or the non-secure data blocks. An IC chip data output is disabled during the data-initialization operation.

Protecting chip settings using secured scan chains

Some embodiments include a method for processing a scan chain in an integrated circuit. The method can include: receiving, in the integrated circuit, the scan chain, wherein the scan chain includes a secret key pattern; separating the secret key pattern from the scan chain; comparing the secret key pattern to a reference key pattern; determining, based on the comparing the secret key pattern to the reference key pattern, that the secret key pattern does not match the reference key pattern; and generating a signal indicating that the secret key pattern does not match the reference key pattern.

Method and apparatus for accessing hidden data in a boundary scan test interface

An apparatus and method for accessing hidden data in a boundary scan test interface is disclosed, which defines an invalid state transition loop in a boundary scan test interface and initially monitors an input of state transition diagram of the boundary scan test interface so that an output of a first data is generated when a first predetermined input stream conforming to the invalid state transition loop is detected and next an output of a second data is generated when a second predetermined input stream conforming to the invalid state transition loop is detected, wherein when an input key included in a combination of the first and the second data is matched with a predetermined write key, a specific write data is loaded into a hidden register.

Semiconductor LSI circuit with scan circuit, scan circuit system, scanning test system and method

A semiconductor LSI circuit provided with a scan circuit includes: to-be-tested combinational logic circuits; scan circuits adjacent to and disposed alternately with the combinational logic circuits; scan elements, which form the scan circuits; a first selector inserted in a first scan circuit scan and connects a first group of scan elements and a second group of scan elements; a second selector inserted in a second scan circuits and connects a third group of scan elements and a fourth group of scan elements; a first route provided in the first group of scan elements and extending from a scanning output terminal of a scan element; and a second route provided in a third group of scan elements and extending from the scanning output terminal of a scan element. The first selector selects either the first route or the second route.

Protecting information processing system secrets from debug attacks

Embodiments of an invention for protecting information processing system secrets from debug attacks are disclosed. In one embodiment, a processor includes storage, a debug unit, and a test access port. The debug unit is to receive a policy from a debug aggregator. The policy is based on a value of a first fuse and has a production mode corresponding to a production value of the first fuse and a debug mode corresponding to a debug value of the fuse. The test access port is to provide access to the storage using a debug command in the debug mode and to prevent access to the storage using the debug command in the production mode.

Circuit for securing scan chain data

PROTECTION OF THE CONTENTS OF A FUSE MEMORY

METHOD FOR PRODUCING AN ELECTRONIC DEVICE WITH A DISABLED SENSITIVE MODE, AND METHOD FOR TRANSFORMING SUCH AN ELECTRONIC DEVICE TO RE-ACTIVATE ITS SENSITIVE MODE

Design-for-test for asynchronous circuit elements

Various examples of a circuit and a technique for testing the circuit are disclosed herein. In an example, the circuit includes a data input coupled to a scan multiplexer and a path select multiplexer. The circuit further includes a scan-in input coupled to the scan multiplexer and to receive a value of a scan pattern. The circuit further includes a scan latch to store the value that has an input coupled to the scan multiplexer and an output coupled to the path select multiplexer. The scan multiplexer selects a first signal from the data input and the scan-in input and provides the first signal to the input of the scan latch. The path select multiplexer selects a second signal from the data input and the output of the scan latch and provides the second signal to a data output of the circuit.

Secure device state apparatus and method and lifecycle management

A semiconductor chip device include device state fuses that may be used to configure various device states and corresponding security levels for the semiconductor chip as it transitions from wafer manufacturing to provisioned device. The device states and security levels prevent the semiconductor chip from being accessed and exploited, for example, during manufacturing testing. A secure boot flow process for a semiconductor chip over its lifecycle is also disclosed. The secure boot flow may start at the wafer manufacturing stage and continue on through the insertion of keys and firmware.

Semiconductor device

A semiconductor device, comprising: a user circuit having a plurality of flip-flops; and a connection path which, while in test mode, connects the plurality of flip-flops and forms a scan chain, wherein the connection path has a logic operation circuit which performs a logic operation on a non-inverted output value of any flip-flop among the plurality of flip-flops and outputs the result, or, an inverted value connection path which outputs to a following-stage flip-flop an inverted output value of any flip-flop among the plurality of flip-flops.

INTRUSION DETECTION FOR INTEGRATED CIRCUITS

Certain aspects of the disclosure are directed to methods and apparatuses of intrusion detection for integrated circuits. An example apparatus can include a wired communications bus configured and arranged to carry data and a plurality of integrated circuits. The plurality of integrated circuits can include a first integrated circuit configured and arranged to operate in a scan mode during which the first integrated circuit performs a scan test to detect one or more faults in circuitry of the plurality of integrated circuits. The plurality of integrated circuits can further include a second integrated circuit configured and arranged to operate in a mission mode and supervise data traffic by monitoring communications including data patterns and accesses on the wired communications bus. In response to identifying a suspected illegitimate access, the second integrated circuit can perform a security action to mitigate a suspect illegitimate action in the plurality of integrated circuits.

Method and system for blocking data in scan registers from being shifted out of a device

Aspects of a method and system for blocking data in scan registers from being shifted out of a device may comprise preventing data intrusion in an integrated circuit by generating a device reset signal prior to entering scan mode. The method may further comprise detecting an attempt to enter said scan mode. The device reset signal may also be an internal reset signal. A subsequent device reset signal may be generated after entering scan mode. The subsequent device reset signal may be an internal pulse signal. The method may further comprise clearing stored data in an integrated circuit after generating a subsequent device reset signal.

PROTECTION OF THE CONTENTS OF A FUSE MEMORY

La présente description concerne un procédé dans lequel un état d'un circuit intégré entre un premier état (CLOSED), autorisant un accès pour lecture d'une première zone (202) d'une mémoire non volatile de type fusible (110) à une unité de traitement (112), et un deuxième état (OPEN), interdisant l'accès pour lecture de ladite mémoire à l'unité de traitement (112), est conditionné par une vérification, par une machine à états finis (108), d'un premier mot de type fusible (WORD1) de ladite mémoire, représentant un nombre de transitions vers ledit premier état, et d'un deuxième mot de type fusible (WORD2) de ladite mémoire, représentant un nombre de transitions vers ledit deuxième état.

Securing access to integrated circuit scan mode and data

Embodiments relate to providing security of scan mode access and data in an integrated circuit. In embodiments, one or both of two layers of security are provided. A first layer includes requiring a complex initialization sequence to be performed in order to access scan mode. A second layer includes scrambling the scan data before it is output from the circuit under test, which prevents unauthorized persons from extracting useful information from the output scan data. Further embodiments relate to methodologies for utilizing these protection layers after manufacture of the integrated circuit and incorporating these protection layers in an integrated circuit design flow.

JTAG LOCKOUT FOR EMBEDDED PROCESSORS IN PROGRAMMABLE DEVICES

A Joint Test Action Group (JTAG) communication lockout processor is disclosed. The processor is configured to generate a multi-channel unlock sequence based on an operational mode change of an operably connected programmable device, and save the unlock sequence to one or more memory registers. The processor can also receive an execution of the multi-channel unlock sequence via two or more unlock channels, determine, via an unlock logic, whether the execution of the multi-channel unlock sequence is valid, and responsive to determining that the execution of the multi-channel unlock sequence is valid, allow or disallow the JTAG communication with an embedded processor.

DETECTION OF PULSE WIDTH TAMPERING OF SIGNALS

A sensor system can include a sensor having a charge storage device controllably connected to a voltage source under control of a signal under test; and a readout circuit coupled to the charge storage device to determine whether the pulse width of the signal under test has changed greater than a threshold amount according to a voltage at the charge storage device. In some cases, the determination of whether the pulse width of the signal under test has changed can include determining whether the voltage satisfies a condition with respect to a comparison voltage. In some cases, the determination of whether the pulse width of the signal under test has changed can be based on a propagation delay through a delay chain, where the propagation delay is dependent on the voltage.

System on chip and secure debugging method

本揭露提供一種系統晶片（SOC）。所述系統晶片包括：多處理器，包括多個處理器；偵錯控制器，包括偵錯埠及用以儲存安全聯合測試工作群組系統的認證結果的保持邏輯；以及電力管理單元，用以管理被供應至所述多處理器及所述偵錯控制器的電力。所述電力管理單元因應於偵錯請求訊號而將所述偵錯埠及所述保持邏輯改變至活動電力域。

ELECTRONIC SYSTEM, SYSTEM DIAGNOSTIC CIRCUIT AND OPERATION METHOD THEREOF

An electronic system, a system diagnostic circuit, and an operation method thereof are provided. The system diagnostic circuit includes a data register circuit, an instruction register circuit, a diagnostic controller circuit, a control register circuit, and a detect circuit. The diagnostic controller circuit determines to transmit test data to the instruction register circuit or the data register circuit according to an operating state. The detect circuit update the control register circuit when the first test data transmitted to the data register circuit meets a predefined pattern.

Protecting hidden content in integrated circuits

An integrated circuit has a first scan cell segment, a second scan cell segment connected to one or more hidden content, and a scan cell circuit connected to the first scan cell segment and the second scan cell segment. The scan cell circuit alternatively provides access to the first scan cell segment and the second scan cell segment based on a state of the scan cell circuit.

METHODS FOR DETECTING SYSTEM-LEVEL TROJANS AND AN INTEGRATED CIRCUIT DEVICE WITH SYSTEM-LEVEL TROJAN DETECTION

Embodiments of a method, an IC device, and a circuit board are disclosed. In an embodiment, the method involves at an IC device of the system, monitoring activity on a bus interface of the IC device, wherein the bus interface is connected to a bus on the system that communicatively couples the IC device to at least one other IC device on the system, applying machine learning to data corresponding to the monitored activity to generate an activity profile, monitoring subsequent activity on the bus interface of the IC device, comparing data corresponding to the to subsequently monitored activity to the machine learning generated activity profile to determine if a system-level Trojan is detected, and generating a notification when it is determined from the comparison that a system-level Trojan has been detected.

Verfahren und Vorrichtung zum Zugriff auf versteckte Daten in einer Boundary Scan Testschnittstelle

Eine Vorrichtung und ein Verfahren zum Zugriff auf versteckte Daten in einer Boundary Scan Testschnittstelle wird offenbart, das eine Ungültiger-Zustandsübergang-Schleife in einer Boundary Scan Testschnittstelle definiert und anfangs eine Eingabe des Zustandsübergangsdiagramms der Boundary Scan Testschnittstelle überwacht, so dass eine Eingabe erster Daten erzeugt wird, wenn ein erster vorbestimmter Eingabestrom entdeckt wird, der konform geht mit der Ungültiger-Zustandsübergang-Schleife, und als nächstes eine Ausgabe zweiter Daten erzeugt wird, wenn ein zweiter vorbestimmter Eingabestrom entdeckt wird, der konform geht mit der Ungültiger-Zustandsübergang-Schleife, worin, wenn ein Eingabeschlüssel, der in einer Kombination der ersten und der zweiten Daten enthalten ist, mit einem vorbestimmten Schreibschlüssel abgeglichen wird, spezifische Schreibdaten in ein verstecktes Register geladen werden.

JTAG LOCKOUT FOR EMBEDDED PROCESSORS IN PROGRAMMABLE DEVICES

Protecting chip settings using secured scan chains

Some embodiments include a method for processing a scan chain in an integrated circuit, the method comprising receiving, in the integrated circuit, the scan chain, wherein the scan chain includes a secret key pattern; separating the secret key pattern from the scan chain; storing the scan chain in a first plurality of latches; storing the secret key pattern in a second plurality of latches; comparing the secret key pattern to a reference key pattern, the reference key pattern stored in a third plurality of latches; determining, based on the comparing the secret key pattern to the reference key pattern, that the secret key pattern does not match the reference key pattern; and generating a signal indicating that the secret key pattern does not match the reference key pattern.

Protecting hidden content in integrated circuits

Various integrated circuits protect hidden content e.g., embedded instruments, keys, data, etc.) using scan cell circuit(s). For example, a first scan cell circuit is connected to the hidden content, and a second scan cell circuit is connected to the first scan cell circuit forming all or part of a serial data path. The first scan cell circuit provides access to the hidden content whenever the first scan cell circuit is in a first specified state and prevents access whenever the first scan cell circuit is in a different state. The first scan cell circuit does not interrupt the serial data path when the first scan cell circuit is in the different state. The second scan cell circuit changes an operational characteristic of the first scan cell circuit whenever the second scan cell circuit is in a second specified state. In some cases, the second scan cell circuit can be eliminated.

Circuit for securing scan chain data

Methods, devices and circuits are provided for protecting secure data from being read during a scan chain output. A plurality of scan flip-flops is coupled in a scan chain, and an input circuit is configured to shift input data to the scan flip-flops. A protection circuit is coupled to the scan flip-flops, and the protection circuit configured to detect scan-in of data from the input circuit to a designated one of the scan flip-flops. Scan-out of data from the designated scan flip-flop is enabled in response to detection of a scan-in of data from the input circuit to the designated scan flip-flop. Scan-out of data from the designated scan flip-flop is prevented in response to no detection of scan-in of data from the input circuit to the designated scan flip-flop.

Design-For-Test for Asynchronous Circuit Elements

Various examples of a circuit and a technique for testing the circuit are disclosed herein. In an example, the circuit includes a data input coupled to a scan multiplexer and a path select multiplexer. The circuit further includes a scan-in input coupled to the scan multiplexer and to receive a value of a scan pattern. The circuit further includes a scan latch to store the value that has an input coupled to the scan multiplexer and an output coupled to the path select multiplexer. The scan multiplexer selects a first signal from the data input and the scan-in input and provides the first signal to the input of the scan latch. The path select multiplexer selects a second signal from the data input and the output of the scan latch and provides the second signal to a data output of the circuit.

Secure Device State Apparatus and Method and Lifecycle Management

A semiconductor chip device include device state fuses that may be used to configure various device states and corresponding security levels for the semiconductor chip as it transitions from wafer manufacturing to provisioned device. The device states and security levels prevent the semiconductor chip from being accessed and exploited, for example, during manufacturing testing. A secure boot flow process for a semiconductor chip over its lifecycle is also disclosed. The secure boot flow may start at the wafer manufacturing stage and continue on through the insertion of keys and firmware. 1. A method of provisioning a semiconductor chip device , the method comprising:determining that the semiconductor chip device is ready for provisioning based on a bit pattern stored in device fuses within the semiconductor chip device;writing boot processing code to non-volatile memory of the semiconductor chip device;verifying an authenticity of the boot processing code;creating a device initialization key using a certificate;disabling the certificate;deriving a plurality of provisioning keys using the device initialization key and the boot processing code;proving identity by providing a device ID and one of the provisioning keys;decrypting provisioning data using another of the provisioning keys; andverifying that the provisioning data is valid.2. The method of claim 1 , wherein the non-volatile memory is flash memory.3. The method of claim 1 , wherein the device initialization key is stored in a firmware readable register.4. The method of claim 1 , wherein the provisioning data includes application-specific flash firmware; andwherein the method further comprises allowing, by the boot processing code, storage of the application-specific flash firmware in the non-volatile memory.5. The method of claim 1 , wherein the certificate is disabled by permanently burning a plurality of the device fuses.6. The method of claim 1 , wherein the certificate is contained within the boot ...

Non-Intrusive Monitoring

A technique for detecting unauthorized manipulation of a circuit. In one embodiment, a test data channel of a boundary scan system of a circuit is monitored while the circuit is in operation. By monitoring the test data channel, a monitoring module determines the presence of a signal on the test data channel. During operation, activity on this channel may represent a potential unauthorized manipulation attempt. An alarm condition may therefore be created if a signal is detected.

半導体装置

Circuit with design test elements

Electronic system, system diagnostic circuit and operation method thereof

An electronic system, a system diagnostic circuit and an operation method thereof are provided. The system diagnostic circuit includes a data register circuit, an instruction register circuit, a diagnostic controller circuit, a control register circuit, and a detect circuit. The diagnostic controller circuit determines to transmit test data of a diagnosis host to the instruction register circuit or the data register circuit according to the operating state. The detect circuit updates the control register circuit when the first test data transmitted to the data register circuit meets a predefined pattern.

SEMICONDUCTOR DEVICE

A semiconductor device, comprising: a user circuit having a plurality of flip-flops; and a connection path which, while in test mode, connects the plurality of flip-flops and forms a scan chain, wherein the connection path has a logic operation circuit which performs a logic operation on a non-inverted output value of any flip-flop among the plurality of flip-flops and outputs the result, or, an inverted value connection path which outputs to a following-stage flip-flop an inverted output value of any flip-flop among the plurality of flip-flops.

Verfahren und Vorrichtung zum Zugriff auf versteckte Daten in einer Boundary Scan Testschnittstelle

Vorrichtung zum Zugriff auf versteckte Daten unter Verwendung einer Boundary Scan Testschnittstelle, wobei die Boundary Scan Testschnittstelle mit einem vorbestimmten Zustandsübergangsdiagramm arbeitet, um Zustandsübergänge auf der Grundlage einer Eingabe durchzuführen, worin mindestens eine Ungültiger-Zustandsübergang-Schleife in dem vorbestimmten Zustands-Übergangs-Diagramm vorgesehen ist und die Vorrichtung umfasst: einen Zustandsdetektor (51) zur Überwachung der Eingabe, um erste Daten auszugeben, wenn ein erster vorbestimmter Eingabestrom entdeckt wurde, und dann zweite Daten auszugeben, wenn ein zweiter vorbestimmter Eingabestrom entdeckt wurde, worin der erste und der zweite vorbestimmte Eingabestrom unterschiedlichen Eingabeströmen der Ungültiger-Zustandsübergang-Schleife entsprechen; ein Schieberegister (52) zur Speicherung einer Kombination der ersten und der zweiten Daten, worin ein Teil der Kombination als Eingabeschlüssel dient; ein verstecktes Register (37) zur Datenspeicherung ...

The security device state apparatus and method and life-cycle management

Conditional access chip, built-in self-test circuit and test method thereof

一種內建於一條件式存取晶片的自我測試電路，該條件式存取晶片利用複數邏輯單元解密一影音資料，該自我測試電路包含：一儲存單元，用來儲存一測試資料及一比對資料；以及一控制單元，耦接該些邏輯單元，用來：控制該些邏輯單元接收一時脈以進行一測試；自該儲存單元讀取該測試資料；將該測試資料依據該時脈輸入該些邏輯單元所組成之一掃描鏈；以及比對該掃描鏈之一輸出資料與該比對資料以得到一測試結果。

Secure design-for-test scan chains

A method of securing a design-for-test scan chain within a programmable integrated circuit device (IC) can include placing the programmable IC in an operational mode and responsive to a request to access a scan chain within the programmable IC, selectively enabling a secure mode within the programmable IC according to a configuration state of the programmable IC. Enabling secure mode within the programmable IC can provide access to the scan chain. Responsive to enabling the secure mode, the programmable IC can remain in the secure mode and be prevented from re-entering the operational mode until the programmable IC is power cycled.

A PROVISIONING CONTROL APPARATUS FOR PROVISIONING AN ELECTRONIC COMPONENT FOR ELECTRONIC EQUIPMENT

The invention relates to a provisioning control apparatus (140) configured to be coupled to a provisioning apparatus (160), wherein the provisioning apparatus (160) is electrically connectable with a plurality of pins of an electronic component (170) for provisioning the electronic component (170) with security sensitive provisioning data (150). The provisioning control apparatus (140) comprises a communication interface (143) configured to provide the security sensitive provisioning data (150) via the provisioning apparatus (160) to the electronic component (170). The communication interface (143) is further configured to trigger a lockdown of the electronic component (170). The communication interface (143) is further configured to determine via the provisioning apparatus (160) one or more states of the plurality of pins of the electronic component (170) for determining a state of the electronic component (170), after the electronic component (170) has been locked down.

Secure device state apparatus and method and lifecycle management

IC device authentication using energy characterization

Systems, methods, and apparatuses are described for verifying the authenticity of an integrated circuit device. An integrated test apparatus may use quiescent current and/or conducted electromagnetic interference readings to determine if a device under test matches the characteristics of an authenticated device. Deviations from the characteristics of the authenticated device may be indicative of a counterfeit device.

Method and system for blocking data in scan registers from being shifted out of a device

Aspects of a method and system for blocking data in scan registers from being shifted out of a device may comprise preventing data intrusion in an integrated circuit by generating a device reset signal prior to entering scan mode. The method may further comprise detecting an attempt to enter said scan mode. The device reset signal may also be an internal reset signal. A subsequent device reset signal may be generated after entering scan mode. The subsequent device reset signal may be an internal pulse signal. The method may further comprise clearing stored data in an integrated circuit after generating a subsequent device reset signal.

Method for producing an electronic device with a disabled sensitive mode, and method for transforming such an electronic device to re-activate its sensitive mode

A method is intended for transforming a secure electronic device, associated to a first identifier and having a sensitive mode disabled after production, for a new sensitive use. This method comprises the steps of: (i) externally computing a cipher of the first identifier with a predetermined function fed with this first identifier and a predetermined secret key; (ii) transforming an accessible metal layer of the electronic device to form an activation pattern representing this externally computed cipher of the first identifier; (iii) getting a value representative of this activation pattern into the electronic device; and (iv) computing a second identifier with this transformed electronic device by feeding a reverse function of the predetermined function with this value and this secret key, to trigger a comeback to the sensitive mode if this second identifier is equal to the first identifier.

SYSTEM AND METHOD TO PROVIDE SAFETY PARTITION FOR AUTOMOTIVE SYSTEM-ON-A-CHIP

An automotive control system includes a safety processor and a system-on-a-chip. The SoC includes a primary processor, a safety monitor, first and second GPIO banks, and a debug interface. The safety monitor is configured to detect a fault condition of the primary processor and to provide an indication of the fault condition to the safety processor. The first GPIO bank is coupled to the primary processor to provide input/output operations to a non-critical function of an automobile, while the second GPIO bank is coupled for a critical function of the automobile. The debug interface is coupled to the second GPIO bank to form a scan chain with input and output registers of the second GPIO bank, and is coupled to the safety processor to receive control information for the scan chain to provide input/output operations to the critical function of the automobile when the safety monitor provides the indication.

Using embedded time-varying code generator to provide secure access to embedded content in an on-chip access architecture

A network of storage units has a data path, which is at least a portion of the network. The network also has a dynamic time-varying or cycle-varying code generation unit and a code comparator unit that together make up an unlock signal generation unit; and a gateway storage unit. If the gateway storage unit does not store an unlock signal or the unlock signal generation unit does not generate and transmit an unlock signal, the gateway storage unit does not insert a data path segment in the data path. If the unlock signal generation unit is operated such that it generates an unlock signal, and it transmits that unlock signal to a gateway storage unit, and the gateway storage unit stores the unlock signal value, then the gateway storage unit inserts a data path segment into the data path.

DEVICE AND METHOD FOR DETECTING POINTS OF FAILURES

The detection device (100) is configured to detect that said n-tuple represents a Point Of Failure of order n in the integrated circuit (IC) device if the derivative of the Boolean function associated with said sensitive functional block is equal to zero.

Method and apparatus for accessing hidden data in a boundary scan test interface

An apparatus and method for accessing hidden data in a boundary scan test interface is disclosed, which defines an invalid state transition loop in a boundary scan test interface and initially monitors an input of state transition diagram of the boundary scan test interface so that an output of a first data is generated when a first predetermined input stream conforming to the invalid state transition loop is detected and next an output of a second data is generated when a second predetermined input stream conforming to the invalid state transition loop is detected, wherein when an input key included in a combination of the first and the second data is matched with a predetermined write key, a specific write data is loaded into a hidden register.

Using Embedded Time-Varying Code Generator to Provide Secure Access to Embedded Content in an On Chip Access Architecture

A network of storage units has a data path, which is at least a portion of the network. The network also has a dynamic time-varying or cycle-varying code generation unit and a code comparator unit that together make up an unlock signal generation unit; and a gateway storage unit. If the gateway storage unit does not store an unlock signal or the unlock signal generation unit does not generate and transmit an unlock signal, the gateway storage unit does not insert a data path segment in the data path. If the unlock signal generation unit is operated such that it generates an unlock signal, and it transmits that unlock signal to a gateway storage unit, and the gateway storage unit stores the unlock signal value, then the gateway storage unit inserts a data path segment into the data path.

DEVICE AND METHOD FOR DETECTING POINTS OF FAILURES

Processor switchable between test and debug modes

A processor includes a TCU TAP for access of a TCU for running functional tests and a DAP TAP for access of a debugger. A TAP selection module selects reversibly TAP access by default through the TCU TAP when the processor is a bare die, or by default through the DAP TAP when the processor is packaged, the selection of TAP access being reversible by the TCU. The processor also includes a fuse for irreversibly disabling the selection by the TAP selection module of the TAP access by default through the TCU TAP. Functional tests on bare dies are run with a TCU probing the dies through the TCU TAP by default. Packaged engineering samples can be supplied for debugging with the DAP TAP selected by default, but access possible for the TCU through the TCU TAP.

Methods and apparatus for testing an IC

In a first aspect, a first method is provided for testing an integrated circuit (IC). The first method includes the steps of (1) employing one of a plurality of input lines to receive a test signal for a processor; (2) employing one of a plurality of output lines to send a test result from the processor; and (3) if the test result is unsuccessful, performing at least one of employing a remaining one of the plurality of input lines to receive the test signal for the processor and employing a remaining one of the plurality of output lines to send the test result from the processor. Numerous other aspects are provided.

Non-intrusive monitoring

A technique for detecting unauthorized manipulation of a circuit. In one embodiment, a test data channel of a boundary scan system of a circuit is monitored while the circuit is in operation. By monitoring the test data channel, a monitoring module determines the presence of a signal on the test data channel. During operation, activity on this channel may represent a potential unauthorized manipulation attempt. An alarm condition may therefore be created if a signal is detected.

JTAG debugging device and JTAG debugging method

Design-for-test for asynchronous circuit elements

Various examples of a circuit and a technique for testing the circuit are disclosed herein. In an example, the circuit includes a data input coupled to a scan multiplexer and a path select multiplexer. The circuit further includes a scan-in input coupled to the scan multiplexer and to receive a value of a scan pattern. The circuit further includes a scan latch to store the value that has an input coupled to the scan multiplexer and an output coupled to the path select multiplexer. The scan multiplexer selects a first signal from the data input and the scan-in input and provides the first signal to the input of the scan latch. The path select multiplexer selects a second signal from the data input and the output of the scan latch and provides the second signal to a data output of the circuit.

METHODS AND APPARATUS FOR TESTING AN IC USING A PLURALITY OF I/O LINES

In a first aspect, a first method is provided for testing an integrated circuit (IC). The first method includes the steps of (1) employing one of a plurality of input lines to receive a test signal for a processor; (2) employing one of a plurality of output lines to send a test result from the processor; and (3) if the test result is unsuccessful, performing at least one of employing a remaining one of the plurality of input lines to receive the test signal for the processor and employing a remaining one of the plurality of output lines to send the test result from the processor. Numerous other aspects are provided.

METHOD FOR PRODUCING AN ELECTRONIC DEVICE WITH A DISABLED SENSITIVE MODE, AND METHOD FOR TRANSFORMING SUCH AN ELECTRONIC DEVICE TO RE-ACTIVATE ITS SENSITIVE MODE

A method is intended for transforming a secure electronic device, associated to a first identifier and having a sensitive mode disabled after production, for a new sensitive use. This method comprises the steps of: (i) externally computing a cipher of the first identifier with a predetermined function fed with this first identifier and a predetermined secret key; (ii) transforming an accessible metal layer of the electronic device to form an activation pattern representing this externally computed cipher of the first identifier; (iii) getting a value representative of this activation pattern into the electronic device; and (iv) computing a second identifier with this transformed electronic device by feeding a reverse function of the predetermined function with this value and this secret key, to trigger a comeback to the sensitive mode if this second identifier is equal to the first identifier.

Device and method for accessing hidden data in boundary scan test interface

Secure device state apparatus and method and lifecycle management

A semiconductor chip device include device state fuses that may be used to configure various device states and corresponding security levels for the semiconductor chip as it transitions from wafer manufacturing to provisioned device. The device states and security levels prevent the semiconductor chip from being accessed and exploited, for example, during manufacturing testing. A secure boot flow process for a semiconductor chip over its lifecycle is also disclosed. The secure boot flow may start at the wafer manufacturing stage and continue on through the insertion of keys and firmware.

Circuit for Securing Scan Chain Data

Methods, devices and circuits are provided for protecting secure data from being read during a scan chain output. A plurality of scan flip-flops is coupled in a scan chain, and an input circuit is configured to shift input data to the scan flip-flops. A protection circuit is coupled to the scan flip-flops, and the protection circuit configured to detect scan-in of data from the input circuit to a designated one of the scan flip-flops. Scan-out of data from the designated scan flip-flop is enabled in response to detection of a scan-in of data from the input circuit to the designated scan flip-flop. Scan-out of data from the designated scan flip-flop is prevented in response to no detection of scan-in of data from the input circuit to the designated scan flip-flop.

Design-For-Test for Asynchronous Circuit Elements

Various examples of a circuit and a technique for testing the circuit are disclosed herein. In an example, the circuit includes a data input coupled to a scan multiplexer and a path select multiplexer. The circuit further includes a scan-in input coupled to the scan multiplexer and to receive a value of a scan pattern. The circuit further includes a scan latch to store the value that has an input coupled to the scan multiplexer and an output coupled to the path select multiplexer. The scan multiplexer selects a first signal from the data input and the scan-in input and provides the first signal to the input of the scan latch. The path select multiplexer selects a second signal from the data input and the output of the scan latch and provides the second signal to a data output of the circuit.

Protecting Information Processing System Secrets From Debug Attacks

Embodiments of an invention for protecting information processing system secrets from debug attacks are disclosed. In one embodiment, a processor includes storage, a debug unit, and a test access port. The debug unit is to receive a policy from a debug aggregator. The policy is based on a value of a first fuse and has a production mode corresponding to a production value of the first fuse and a debug mode corresponding to a debug value of the fuse. The test access port is to provide access to the storage using a debug command in the debug mode and to prevent access to the storage using the debug command in the production mode.

System and apparatus for trusted and secure test ports of integrated circuit devices

A trusted boot device secures JTAG scan chains of integrated circuit components on a circuit card assembly without necessarily modifying the integrated circuit components. Component JTAG port I/O scan chain signal pins are independently routed to FPGA fabric on the trusted boot device. The trusted boot device monitors the JTAG paths and triggers a security event if unauthorized activity is detected on a JTAG path. JTAG paths on the secure trusted boot device are latch disabled by default and upon detection of a security event. JTAG paths are only enabled for a predefined length of time. To prevent JTAG access when protected data is exposed, a watchdog timer latch disables the JTAG paths when the predefined time has expired and may trigger a security event if activity is detected after the time has expired. A power cycle is then used to re-enable authenticated JTAG enable requests.

Device having secure jtag and debugging method for the same

A method of debugging a device which includes a plurality of processors is provided. The method includes verifying a request to initiate authentication that is provided to the device to a user; performing a challenge-response authentication operation between the user and the device in response to the request to initiate authentication being a request from a non-malicious user; activating or deactivating an access to a Joint Test Action Group (JTAG) port of each of the processors, based on access control information from the user; and permitting a debugging operation via an access that is activated.

IC Device Authentication Using Energy Characterization

Systems, methods, and apparatuses are described for verifying the authenticity of an integrated circuit device. An integrated test apparatus may use quiescent current and/or conducted electromagnetic interference readings to determine if a device under test matches the characteristics of an authenticated device. Deviations from the characteristics of the authenticated device may be indicative of a counterfeit device.

Programmable Circuits for Correcting Scan-Test Circuitry Defects in Integrated Circuit Designs

In certain embodiments, an integrated circuit has scan-test circuitry that performs scan testing on circuitry under scan test (OUST) within the IC, where the scan-test circuitry is susceptible to a defect. In order to enable the defect to be corrected after it occurs, the scan-test circuitry includes a set of programmable circuitry connected to provide a signal to other circuitry (e.g., a scan chain) within the scan-test circuitry, where the set of programmable circuitry includes one or more configurable memory cells connected to control the programming of the set of programmable circuitry. The memory cell(s) can be configured to program the set of programmable circuitry to enable the scan testing to be performed without modification. The memory cell(s) can also be configured to program the set of programmable circuitry to modify the scan testing to correct the defect in the scan-test circuitry.

Device and method for detecting points of failures

집적 회로(IC)에서 POF를 검출하기 위한 장치, 방법 및 컴퓨터 프로그램 제품이 제공된다. 집적 회로 장치는 다수의 요소를 포함하는 구조적 설명(2)에 의해 기술되며, 상기 요소는 셀들 및 셀들을 상호 연결하는 와이어를 나타내고, 구조적 설명은 민감한 기능 블록(16)의 세트를 나타내는 부분을 더 포함하고, 각각의 민감한 기능적 블럭은 하나 이상의 입력, 적어도 하나의 민감한 출력, 및 상기 민감한 출력의 값이 상기 민감한 기능 블록의 입력값의 불리언 함수가 되도록 상호 연결되는 요소들의 세트를 포함한다. 상기 검출 장치(100)는, - 상기 민감한 기능 블록들에 대응하는 상기 네트리스트의 적어도 일부분에서 n-튜플을 반복적으로 선택하도록 구성된 선택 유닛(101), 및 - 선택된 요소의 각각의 n-튜플을 테스트하도록 구성된 테스트 유닛(104)을 포함하되, 상기 테스트 유닛은, 상기 선택된 요소의 n-튜플을 초기 상태에서 테스트 상태로 수정하고; 각 민감한 기능 블록과 관련된 불리언 함수의 미분이 0인지 여부를 결정하도록 구성된다. 상기 검출 장치(100)는 상기 민감한 기능 블록과 관련된 불리언 함수의 미분이 0인 경우에 상기 n-튜플이 집적 회로(IC) 장치에서 차수 n의 POF를 나타내는 것을 검출하도록 구성된다.

Method for producing an electronic device with a disabled sensitive mode, and method for transforming such an electronic device to re-activate its sensitive mode

A method is intended for transforming a secure electronic device (CH), associated to a first identifier and having a sensitive mode disabled after production, for a new sensitive use. This method comprises the steps of: (i) externally computing a cipher of the first identifier with a predetermined function fed with this first identifier and a predetermined secret key, (ii) transforming an accessible metal layer (ML) of the electronic device (CH) to form an activation pattern (AS) representing this externally computed cipher of the first identifier, (iii) getting a value representative of this activation pattern into the electronic device (CH), (iv) computing a second identifier with this transformed electronic device (CH) by feeding a reverse function of the predetermined function with this value and this secret key, to trigger a comeback to the sensitive mode if this second identifier is equal to the first identifier.

Security device state apparatus and method

本发明涉及安全器件状态设备和方法以及生命周期管理。本发明公开了一种半导体芯片器件，其包括器件状态熔丝，当所述器件状态熔丝从晶片制造转换至供应器件时，所述器件状态熔丝可以用于为所述半导体芯片配置各种器件状态和对应的安全级别。所述器件状态和安全级别防止例如在制造测试期间访问和利用所述半导体芯片。还公开了半导体芯片在其生命周期内的安全引导流程进程。所述安全引导流程可以开始于所述晶片制造阶段并且通过插入密钥和固件而继续。

Device and method for detecting points of failures

집적 회로(IC)에서 POF를 검출하기 위한 장치, 방법 및 컴퓨터 프로그램 제품이 제공된다. 집적 회로 장치는 다수의 요소를 포함하는 구조적 설명(2)에 의해 기술되며, 상기 요소는 셀들 및 셀들을 상호 연결하는 와이어를 나타내고, 구조적 설명은 민감한 기능 블록(16)의 세트를 나타내는 부분을 더 포함하고, 각각의 민감한 기능적 블럭은 하나 이상의 입력, 적어도 하나의 민감한 출력, 및 상기 민감한 출력의 값이 상기 민감한 기능 블록의 입력값의 불리언 함수가 되도록 상호 연결되는 요소들의 세트를 포함한다. 상기 검출 장치(100)는, - 상기 민감한 기능 블록들에 대응하는 상기 네트리스트의 적어도 일부분에서 n-튜플을 반복적으로 선택하도록 구성된 선택 유닛(101), 및 - 선택된 요소의 각각의 n-튜플을 테스트하도록 구성된 테스트 유닛(104)을 포함하되, 상기 테스트 유닛은, 상기 선택된 요소의 n-튜플을 초기 상태에서 테스트 상태로 수정하고; 각 민감한 기능 블록과 관련된 불리언 함수의 미분이 0인지 여부를 결정하도록 구성된다. 상기 검출 장치(100)는 상기 민감한 기능 블록과 관련된 불리언 함수의 미분이 0인 경우에 상기 n-튜플이 집적 회로(IC) 장치에서 차수 n의 POF를 나타내는 것을 검출하도록 구성된다. An apparatus, method and computer program product for detecting a POF in an integrated circuit (IC) are provided. An integrated circuit device is described by a structural description (2) comprising a number of elements, the elements representing cells and wires interconnecting the cells, the structural description further indicating a portion representing a set of sensitive functional blocks 16. Each sensitive functional block comprises one or more inputs, at least one sensitive output, and a set of elements interconnected such that the value of the sensitive output is a Boolean function of the input value of the sensitive functional block. The detection device 100, A selection unit 101 configured to repeatedly select n-tuples in at least a portion of the netlist corresponding to the sensitive functional blocks, and A test unit 104 configured to test each n-tuple of the selected element, wherein the test unit comprises: Modify the n-tuple of the selected element from an initial state to a test state; And determine whether the derivative of the Boolean function associated with each sensitive function block is zero. The detection device 100 is configured to detect that the n-tuple represents a POF of order n in an integrated circuit (IC) device when the derivative of the Boolean function associated with the sensitive functional block is ...

Circuit for securing scan chain data

Methods, devices and circuits are provided for protecting secure data from being read during a scan chain output. A plurality of scan flip-flops is coupled in a scan chain, and an input circuit is configured to shift input data to the scan flip-flops. A protection circuit is coupled to the scan flip-flops, and the protection circuit configured to detect scan-in of data from the input circuit to a designated one of the scan flip-flops. Scan-out of data from the designated scan flip-flop is enabled in response to detection of a scan-in of data from the input circuit to the designated scan flip-flop. Scan-out of data from the designated scan flip-flop is prevented in response to no detection of scan-in of data from the input circuit to the designated scan flip-flop.

Secure scan

According to the invention, a circuit that is capable of automated scan testing is disclosed. Included in the circuit are a cryptographic engine, a digital circuit, an input pin, and an output pin. The cryptographic engine capable of performing at least one of encryption and decryption of one or more digital signals. The digital circuit includes combinatorial logic and a number of memory cells. The memory cells have scan inputs connected serially in a scan chain. The input pin and output pin are coupled to the scan chain. At least one of the input pin and the output pin carries at least some cipher text data of the scan chain.

Methods and apparatus for using scan operations to protect secure assets

Methods and apparatus are described to protect secure assets using scan operations. One example apparatus includes logic circuitry including a scan chain (212) that includes data storage elements (232, 234, 236) and design logic (216) coupled to the scan chain. The example apparatus also includes data storage (202) to store secure data. The design logic is coupled to the data storage. The example apparatus also includes a security controller (240) to transition the apparatus out of a secure mode of operation. The transition includes the security controller to cause the scan chain to serially shift secure scan data from an input of the scan chain into each data storage element of the data storage elements of the scan chain.

Secure scan

According to the invention, a circuit that is capable of automated scan testing is disclosed. Included in the circuit are a cryptographic engine, a digital circuit, an input pin, and an output pin. The cryptographic engine capable of performing at least one of encryption and decryption of one or more digital signals. The digital circuit includes combinatorial logic and a number of memory cells. The memory cells have scan inputs connected serially in a scan chain. The input pin and output pin are coupled to the scan chain. At least one of the input pin and the output pin carries at least some cipher text data of the scan chain.

Enabling secured debug of an integrated circuit

Electronic system, system diagnostic circuitry and its operating method

本发明提供一种电子系统、系统诊断电路与其操作方法。系统诊断电路包括数据寄存器电路、指令寄存器电路、诊断控制器电路、控制寄存器电路以及检测电路。诊断控制器电路依据操作状态来决定将诊断主机的测试数据传输至指令寄存器电路或数据寄存器电路。当经传输至数据寄存器电路的第一测试数据符合预设样式时，检测电路更新控制寄存器电路。在符合联合测试工作群组标准或IEEE 1149.1标准的规范下，本发明的系统诊断电路可以依据诊断主机的指令而弹性控制对电子系统的诊断操作。

Methods for detecting system-level trojans and an integrated circuit device with system-level trojan detection

Embodiments of a method, an IC device, and a circuit board are disclosed. In an embodiment, the method involves at an IC device of the system, monitoring activity on a bus interface of the IC device, wherein the bus interface is connected to a bus on the system that communicatively couples the IC device to at least one other IC device on the system, applying machine learning to data corresponding to the monitored activity to generate an activity profile, monitoring subsequent activity on the bus interface of the IC device, comparing data corresponding to the to subsequently monitored activity to the machine learning generated activity profile to determine if a system-level Trojan is detected, and generating a notification when it is determined from the comparison that a system-level Trojan has been detected.

A kind of Key-insulated security sweep chain circuit

本发明涉及一种密钥隔离安全扫描链电路，属于集成电路技术领域，包括安全扫描链电路、密钥隔离器电路和控制器电路；所述控制器电路通过所述密钥隔离器电路连接所述安全扫描链电路；所述安全扫描链电路包括相连的若干个普通扫描寄存器和安全扫描寄存器，该电路可以针对加密芯片的密钥提供安全有效地保护，使芯片无法被黑客攻击。安全扫描链电路中扫描寄存器包括普通扫描寄存器（SFF）和安全扫描寄存器（SSFF）。安全扫描寄存器由一个普通扫描寄存器、一个异或逻辑门和一个反向器组成。密钥隔离器电路将扫描链电路与密钥生成电路隔离，控制器电路使能密钥隔离器电路加载密钥。本电路在有效保证密钥安全的同时，对故障覆盖率的影响较小，并且面积消耗较小。

Electronic system, system diagnostic circuit and operation method thereof

Method and system for blocking data in scan registers from being shifted out of a device

Aspects of a method and system for blocking data in scan registers from being shifted out of a device may comprise preventing data intrusion in an integrated circuit by generating a device reset signal prior to entering scan mode. The method may further comprise detecting an attempt to enter said scan mode. The device reset signal may also be an internal reset signal. A subsequent device reset signal may be generated after entering scan mode. The subsequent device reset signal may be an internal pulse signal. The method may further comprise clearing stored data in an integrated circuit after generating a subsequent device reset signal.

Methods and apparatus for using scan operations to protect secure assets

Methods and apparatus are described to protect secure assets using scan operations. One example apparatus includes logic circuitry including a scan chain (212) that includes data storage elements (232, 234, 236) and design logic (216) coupled to the scan chain. The example apparatus also includes data storage (202) to store secure data. The design logic is coupled to the data storage. The example apparatus also includes a security controller (240) to transition the apparatus out of a secure mode of operation. The transition includes the security controller to cause the scan chain to serially shift secure scan data from an input of the scan chain into each data storage element of the data storage elements of the scan chain.

測試電路及包括其的積體電路

本發明揭露一種用於測試積體電路核心或積體電路核心的外部電路的測試電路。測試電路不僅可在旁路模式中僅採用一個多工器將單元功能輸入傳輸至單元功能輸出，而且可採用能夠阻止時鐘信號傳輸至掃描正反器的時鐘門控方案來保持擷取程序。

보안 디버깅 회로를 갖는 디바이스 및 그것에 대한 디버깅 방법

본 발명에 따른 복수의 프로세서들을 갖는 디바이스에 대한 디버깅 방법은: 상기 디바이스로 입력된 사용자의 요청을 검증하는 단계; 상기 요청이 합법적인 사용자의 요청이라면, 상기 사용자와 상기 디바이스 사이에서 챌린지-리스판스 인증 동작을 수행하는 단계; 상기 사용자로부터 전송된 접근 제어 정보를 근거로 하여 상기 복수의 프로세서들 각각의 JTAG에 대한 접근을 활성 혹은 비활성시키는 단계; 및 상기 활성화된 적어도 하나의 접근을 통하여 디버깅을 수행하는 단계를 포함한다.

Dynamic scan obfuscation for integrated circuit protections

An integrated circuit (IC) protection circuit can include a reconfigurable block that receives a seed value from a tamper-proof memory and generates a dynamic key; an authentication block that receives the dynamic key from the reconfigurable block and taint bits from a scan chain to generate an authentication signature; and an encryptor that encrypts a test pattern response on the scan chain if a mismatch is found between the authentication signature and a test pattern embedded signature.

Invisible scan architecture for secure testing of digital designs

Various embodiments of the present disclosure provide a scan-based architecture for register-transfer-level (RTL) or gate-level designs that improves the security of scan chain-based design-for-testability (DFT) structures. In various embodiments, the scan-based architecture includes invisible scan chains that are hidden in such a way that an attacker cannot easily identify or locate the invisible scan chains for exploitation and revealing internal secure information of the design. The invisible scan chains are dynamically configurable into a scan chain with select flip-flops, such that scan paths of the invisible scan chains may be different between different designs, chips, or testing operations. Various embodiments further employ key-based obfuscation by combining a scan control finite state machine with existing state machines within a design, which improves design security against unauthorized use and increases confidentiality. Specific sequences of key patterns cause the design to transition into a test mode or a normal mode.

具有受保护的jtag接口的fpga芯片

本公开涉及一种具有受保护的JTAG接口的FPGA芯片。一个方面提供了一种被安装在印刷电路板(PCB)上的FPGA芯片。所述FPGA芯片可以包括：联合测试动作组(JTAG)接口，包括多个输入/输出引脚和启用引脚；以及控制逻辑块，被耦合至所述JTAG接口的所述启用引脚。所述控制逻辑块可以从片外控制单元接收控制信号，并且基于接收到的所述控制信号来控制所述启用引脚的逻辑值，从而便于所述片外控制单元锁定或解锁所述JTAG接口。所述FPGA芯片还可以包括检测逻辑块，以检测对所述FPGA芯片的未授权访问。所述检测逻辑的输入被耦合至所述启用引脚，并且耦合所述检测逻辑块的所述输入和所述启用引脚的导电迹线位于所述PCB的内层上。

FPGA chip with protected JTAG interface

One aspect provides an FPGA chip mounted on a printed circuit board (PCB). The FPGA chip can include a joint test action group (JTAG) interface comprising a number of input/output pins and an enablement pin, and a control logic block coupled to the enablement pin of the JTAG interface. The control logic block can receive a control signal from an off-chip control unit and control a logical value of the enablement pin based on the received control signal, thereby facilitating the off-chip control unit to lock or unlock the JTAG interface. The FPGA chip can further include a detection logic block to detect an unauthorized access to the FPGA chip. An input to the detection logic is coupled to the enablement pin, and a conductive trace coupling the input of the detection logic block and the enablement pin is situated on an inner layer of the PCB.

熔丝型存储器内容的保护

本公开的实施例涉及熔丝型存储器内容的保护。本公开涉及一种方法，其中集成电路在允许处理器对熔丝型非易失性存储器的第一区域的读取访问的第一状态(例如，封闭)和禁止处理器对存储器的读取访问的第二状态(例如，开封)之间的状态由有限状态机调节为对存储器的第一熔丝字的值和存储器的第二熔丝字的值的验证，所述第一熔丝字表示到第一状态的转变的数目，所述第二熔丝字表示到第二状态的转变的数目。

Providing configurable security for intellectual property circuits of a processor

In one embodiment, a method includes: receiving, in a replica circuit associated with a first intellectual property (IP) circuit of a system on chip (SoC), a security policy; receiving, in the replica circuit, a test data register access message to identify an access to a first test data register of the first IP circuit; and preventing the access to the first test data register based at least in part on the security policy. Other embodiments are described and claimed.

Semiconductor integrated circuit, a method for testing the semiconductor integrated circuit, and a semiconductor system

A semiconductor integrated circuit to receive a test scan input, a test clock, and a test mode signal and output a secure scan output signal, the integrated circuit including: a secure key circuit to generate delay input signals, which are differently delayed from the test scan input, and to generate an input key signal by capturing the delay input signals in response to the test clock; a key comparator to generate a verification result indicating whether an input key of the input key signal is identical with a preset reference key; a chip to generate a scan output signal based on the test scan input; a scan output remapper to obfuscate the scan output signal according to the verification result and to output the obfuscated scan output signal as the secure scan output signal; and a secure scan controller to control the secure key circuit, key comparator, chip, and remapper.

Test Point-Enhanced Hardware Security

Various aspects of the disclosed technology relate to techniques of using control test points to enhance hardware security. The design-for-security circuitry reuses control test points, a part of design-for-test circuitry. The design-for-security circuitry comprises: identity verification circuitry; scrambler circuitry coupled; and test point circuitry. The test point circuitry comprises scan cells and logic gates The identify verification circuitry outputs an identity verification result to the scrambler circuitry to enable/disable control test points of the test point circuitry through the logic gates, and the scrambler circuitry outputs logic bits for loading the scan cells to activate/inactivate the control test points through the logic gates.

System on chip for performing scan test and method of designing the same

A system on chip includes a one-time programmable (OTP) memory configured to store secure data, an OTP controller including at least one shadow register configured to read the secure data from the OTP memory and to store the secure data, a power management unit configured to receive an operation mode signal from an external device and to output test mode information indicating whether an operation mode is a test mode according to the operation mode signal and a test valid signal corresponding to the secure data, and a test circuit configured to receive the test mode information from the power management unit, to receive test data from the external device, and to output a scan mode signal and a test mode signal according to the test data and a test deactivation signal, wherein the test deactivation signal corresponds to development state data indicating a chip development state in the secure data.

Protection of proprietary embedded instruments

A network of storage units has a data path which is at least a portion of the network. The network also has a key storage unit and a gateway storage unit. If the key storage unit stores a key value, the key storage unit transmits a key signal to the gateway storage unit. If the gateway storage unit does not store a gateway value or the key signal is not transmitted to the gateway storage unit, the gateway storage unit does not insert a data path segment in the data path. If the gateway storage unit stores a gateway value and the key signal is transmitted to the gateway storage unit, the gateway storage unit inserts the data path segment.

Secured scan access for a device including a scan chain

A device includes a scan chain including a plurality of storage elements and an output buffer; a shadow shift register having a shadow shift input coupled to a scan output of one of the storage elements of the scan chain; a signature register; and a comparator having a first input, a second input, and an output. The comparator first input is to receive a value of the shadow shift register, and the comparator second input is to receive a value of the signature register. The output buffer has a control input coupled to the comparator output, and the output buffer provides a high-impedance output responsive to the value of the shadow shift register being unequal to the value of the signature register.

Protecting information processing system secrets from debug attacks

Embodiments of an invention for protecting information processing system secrets from debug attacks are disclosed. In one embodiment, a processor includes storage, a debug unit, and a test access port. The debug unit is to receive a policy from a debug aggregator. The policy is based on a value of a first fuse and has a production mode corresponding to a production value of the first fuse and a debug mode corresponding to a debug value of the fuse. The test access port is to provide access to the storage using a debug command in the debug mode and to prevent access to the storage using the debug command in the production mode.

System on chip for performing scan test and method of designing the same

A system on chip includes a one-time programmable (OTP) memory configured to store secure data, an OTP controller including at least one shadow register configured to read the secure data from the OTP memory and to store the secure data, a power management unit configured to receive an operation mode signal from an external device and to output test mode information indicating whether an operation mode is a test mode according to the operation mode signal and a test valid signal corresponding to the secure data, and a test circuit configured to receive the test mode information from the power management unit, to receive test data from the external device, and to output a scan mode signal and a test mode signal according to the test data and a test deactivation signal, wherein the test deactivation signal corresponds to development state data indicating a chip development state in the secure data.

具有电源毛刺检测和电源毛刺自测试功能的芯片

示出了芯片内的电源毛刺检测和电源毛刺自测试。在芯片中，处理器具有电源端、毛刺检测器和自测试电路。电源端用于接收电源。毛刺检测器耦接到处理器的电源端，用于检测电源毛刺。自测试电路包括毛刺产生器和毛刺控制器，毛刺控制器控制毛刺产生器在芯片内产生自测试毛刺信号，以对所述毛刺检测器进行测试。本申请的自测试毛刺信号由芯片自身产生，不需要额外的测试垫测试毛刺检测器。

Chip with power-glitch detection and power-glitch self-testing

Power-glitch detection and power-glitch self-testing within a chip is shown. In a chip, a processor has a power terminal, a glitch detector, and a self-testing circuit. The power terminal is configured to receive power. The glitch detector is coupled to the power terminal of the processor for power-glitch detection. The self-testing circuit has a glitch generator and a glitch controller. The glitch controller controls the glitch generator to generate a self-testing glitch signal within the chip to test the glitch detector.

スキャンテスト回路、スキャンテスト方法およびスキャンテスト回路の設計方法

【課題】オーバヘッドの増加を抑え、高秘匿性要求回路の秘匿性を守りながらテストを行うことができるスキャンテスト回路およびスキャンテスト回路の設計方法を提供する。【解決手段】スキャンテスト回路は、複数のサブスキャンチェーンによって構成されるスキャンチェーンと、入力分配回路と、出力圧縮回路とを備える。バイパス回路によって、圧縮スキャンモードの場合に、内部回路に含まれる複数のスキャンセル回路のうち、高秘匿性要求回路のスキャンセル回路を接続して複数のサブスキャンチェーンが構成され、非圧縮スキャンモードの場合に、高秘匿性要求回路のスキャンセル回路をバイパスして複数のサブスキャンチェーンが構成される。【選択図】 図１

Side-channel signature based pcb authentication using jtag architecture and a challenge-response mechanism

The present disclosure describes exemplary methods and systems that are applicable for hardware authentication, counterfeit detection, and in-field tamper detection in both printed circuit board and/or integrated circuit levels by utilizing random variations in boundary-scan path delay and/or current in the industry-standard JTAG-based design-for-test structure to generate unique device identifiers.

Invisible scan architecture for secure testing of digital designs

Various embodiments of the present disclosure provide a scan-based architecture for register-transfer-level (RTL) or gate-level designs that improves the security of scan chain-based design-for-testability (DFT) structures. In various embodiments, the scan-based architecture includes invisible scan chains that are hidden in such a way that an attacker cannot easily identify or locate the invisible scan chains for exploitation and revealing internal secure information of the design. The invisible scan chains are dynamically configurable into a scan chain with select flip-flops, such that scan paths of the invisible scan chains may be different between different designs, chips, or testing operations. Various embodiments further employ key-based obfuscation by combining a scan control finite state machine with existing state machines within a design, which improves design security against unauthorized use and increases confidentiality. Specific sequences of key patterns cause the design to transition into a test mode or a normal mode.

Method and apparatus for switchably selecting an integrated circuit operating mode

A method and circuit for preventing external access to secure data of an integrated circuit while supporting DFT is disclosed. In accordance with the method the integrated circuit is automatically placed into the test mode at integrated circuit power-up from a power-down state. At power up, secure data is other than present within a secure data-path of the integrated circuit. Access is provided to the secure data path via a second data path coupled with the first secure data-path. Via the access path, data other than secure data is provided to the integrated circuit, the data for performing test functions of the integrated circuit operating in the test mode. Once data other than secure data is provided to first secure data path, the test mode is terminated and access via other than the secure ports is disabled. The test mode is only re-entered by powering down the integrated circuit and re-initialising it.

Secured scan access for a device including a scan chain

A device includes a scan chain including a plurality of storage elements and an output buffer; a shadow shift register having a shadow shift input coupled to a scan output of one of the storage elements of the scan chain; a signature register; and a comparator having a first input, a second input, and an output. The comparator first input is to receive a value of the shadow shift register, and the comparator second input is to receive a value of the signature register. The output buffer has a control input coupled to the comparator output, and the output buffer provides a high-impedance output responsive to the value of the shadow shift register being unequal to the value of the signature register.

Fpga-chip mit geschützter jtagschnittstelle

Ein Aspekt sieht einen FPGA-Chip vor, der auf einer gedruckten Schaltung (PCB) montiert ist. Der FPGA-Chip kann eine JTAG-Schnittstelle (Joint Test Action Group) umfassen, die eine Anzahl von Eingangs-/Ausgangsstiften und einen Freigabe-Stift umfasst, sowie einen Steuerlogikblock, der mit dem Freigabe-Stift der JTAG-Schnittstelle verbunden ist. Der Steuerlogikblock kann ein Steuersignal von einer Off-Chip-Steuereinheit empfangen und einen logischen Wert des Freigabepins auf der Grundlage des empfangenen Steuersignals steuern, wodurch die Off-Chip-Steuereinheit das Sperren oder Entsperren der JTAG-Schnittstelle erleichtert. Der FPGA-Chip kann ferner einen Erkennungslogikblock enthalten, um einen unbefugten Zugriff auf den FPGA-Chip zu erkennen. Ein Eingang der Erkennungslogik ist mit dem Freigabepin gekoppelt, und eine Leiterbahn, die den Eingang des Erkennungslogikblocks und den Freigabepin koppelt, befindet sich auf einer inneren Schicht der Leiterplatte.

Fpga-chip mit geschützter jtag-schnittstelle

Multi-Partition, Multi-Domain System-on-Chip JTAG Debug Control Architecture and Method

A method and apparatus are disclosed for a multi-processor SoC which includes an execution domain processor for running an execution domain which hosts n partitions by accessing, for each partition, one or more SoC resources; a control point processor that generates control data with n JTAG debug enable signals corresponding to the n partitions for controlling access to the SoC resources by identifying at least a first SoC resource that each partition is allowed to access; and an access control circuit connected between the execution domain and the SoC resources and configured to provide, in response to the control data, a dynamic runtime isolation barrier which allows access by the JTAG debugging tool to only a specified partition running on the execution domain which has a JTAG debug enable signal set to a first active value and prevents access to the other n-1 partitions running on the execution domain, and for the partition under debug (debug signal set to a first active value), the dynamic runtime isolation barrier can be configured to block debugger access to selected memory regions accessible by the partition under debug.

Protection du contenu d'une mémoire fusible

Protection du contenu d'une mémoire fusible La présente description concerne un procédé dans lequel un état d’un circuit intégré entre un premier état (CLOSED), autorisant un accès pour lecture d’une première zone d’une mémoire non volatile de type fusible à une unité de traitement, et un deuxième état (OPEN), interdisant l’accès pour lecture de ladite mémoire à l’unité de traitement, est conditionné par une vérification, par une machine à états finis, d’un premier mot de type fusible de ladite mémoire, représentant un nombre de transitions vers ledit premier état, et d’un deuxième mot de type fusible de ladite mémoire, représentant un nombre de transitions vers ledit deuxième état. Figure pour l'abrégé : Fig. 3

半導體積體電路以及測試半導體積體電路的方法

一種用於接收測試掃描輸入、測試時脈及測試模式訊號且輸出安全掃描輸出訊號的半導體積體電路，積體電路包括：安全金鑰電路，生成自測試掃描輸入不同地延遲的延遲輸入訊號，且藉由因應於測試時脈捕捉延遲輸入訊號來生成輸入金鑰訊號；金鑰比較器，生成指示輸入金鑰訊號的輸入金鑰與預設參考金鑰是否相同的驗證結果；晶片，基於測試掃描輸入生成掃描輸出訊號；掃描輸出重映射器，根據驗證結果混淆掃描輸出訊號且輸出經混淆的掃描輸出訊號作為安全掃描輸出訊號；以及安全掃描控制器，用於控制安全金鑰電路、金鑰比較器、晶片及重映射器。

Apparatus and method of authenticating Joint Test Action Group (JTAG)

In an apparatus including a joint test action group (JTAG) authentication device, and a JTAG authentication method using the apparatus, the apparatus includes a joint test action group (JTAG) authentication device, the apparatus comprising a JTAG access circuit that determines whether to access a JTAG-compliant device according to a predetermined protocol that governs the JTAG-compliant device and the apparatus, wherein the JTAG access circuit at least one of inactivates at least one of inner bus lines and inner units and activates the at least one of the inner bus lines and the inner units according to whether the JTAG-compliant device is accessed.

具有電源毛刺檢測和電源毛刺自測試功能的晶片

示出了晶片內的電源毛刺檢測和電源毛刺自測試。在晶片中，處理器具有電源端、毛刺檢測器和自測試電路。電源端用於接收電源。毛刺檢測器耦接到處理器的電源端，用於檢測電源毛刺。自測試電路包括毛刺產生器和毛刺控制器，毛刺控制器控制毛刺產生器在晶片內產生自測試毛刺信號，以對所述毛刺檢測器進行測試。本申請的自測試毛刺信號由晶片自身產生，不需要額外的測試墊測試毛刺檢測器。

Chip with power-glitch detection and power-glitch self-testing

Power-glitch detection and power-glitch self-testing within a chip is shown. In a chip, a processor has a power terminal, a glitch detector, and a self-testing circuit. The power terminal is configured to receive power. The glitch detector is coupled to the power terminal of the processor for power-glitch detection. The self-testing circuit has a glitch generator and a glitch controller. The glitch controller controls the glitch generator to generate a self-testing glitch signal within the chip to test the glitch detector.

Scan flip-flop, scan chain circuit including the same, and control method of the scan flip-flop

A scan flip-flop configured to generate physically unclonable function (PUF) data according to the present disclosure includes a multiplexer configured to provide an internal signal through an input switch, a first latch circuit configured to latch the internal signal, wherein the first latch circuit comprises a first inverter, a second inverter, a first switch connected in parallel with the first inverter, and a second switch connected in series with the second inverter. Additionally, a second latch circuit configured to latch an output of the first latch circuit and output a latched value, wherein the second latch circuit comprises a third inverter, a fourth inverter, an output inverter connected in series with the third inverter, and a fourth switch connected in series with the fourth inverter. A third switch is configured to switch between the first latch circuit and the second latch circuit.

Method and Apparatus for Digital Only Secure Test Mode Entry

A fully digital integrated circuit apparatus ( 200 ) and method ( 300 ) are provided for generating a test mode enable signal with a digital non-resettable state retention storage circuit ( 210 ) connected to store an authentication control pattern for authorizing test mode access to a secure circuit, a digital safety interlock gate circuit ( 220 ) connected to store a safety interlock gate setting that may be accessed independently from a test mode enable signal, and combinatorial logic circuitry ( 205 ) for generating the test mode enable signal only when the interlock safety gate setting is set to a first value and the digital non-resettable state retention storage circuit stores the authentication control code.

Secured scan access for a device including a scan chain

A device includes a scan chain including a plurality of storage elements and an output buffer; a shadow shift register having a shadow shift input coupled to a scan output of one of the storage elements of the scan chain; a signature register; and a comparator having a first input, a second input, and an output. The comparator first input is to receive a value of the shadow shift register, and the comparator second input is to receive a value of the signature register. The output buffer has a control input coupled to the comparator output, and the output buffer provides a high-impedance output responsive to the value of the shadow shift register being unequal to the value of the signature register.

基于改进的线性反馈移位寄存器的安全测试电路

本发明属于集成电路硬件安全技术领域，公开了基于改进的线性反馈移位寄存器的安全测试电路，通过控制模块控制改进的线性反馈移位寄存器的状态，利用种子信号产生模块提供改进的线性反馈移位寄存器所需要的种子信号，改进的线性反馈移位寄存器模块输出难以预测的序列作为内部测试密钥提供给安全扫描链；安全扫描链的结构是动态的，输出经过混淆的数据，攻击者难以得到真正的扫描数据；通过明文限制模块对扫描链输出进行限制，进一步增强加密电路的安全性，防止差分密码攻击。本发明所述电路可以保护加密芯片免受基于扫描链的攻击，并且面积开销相对较小，且不会增加测试时间，在不影响芯片正常功能的同时又能够实现芯片安全测试的目的。

基于改进的线性反馈移位寄存器的安全测试电路

本发明属于集成电路硬件安全技术领域，公开了基于改进的线性反馈移位寄存器的安全测试电路，通过控制模块控制改进的线性反馈移位寄存器的状态，利用种子信号产生模块提供改进的线性反馈移位寄存器所需要的种子信号，改进的线性反馈移位寄存器模块输出难以预测的序列作为内部测试密钥提供给安全扫描链；安全扫描链的结构是动态的，输出经过混淆的数据，攻击者难以得到真正的扫描数据；通过明文限制模块对扫描链输出进行限制，进一步增强加密电路的安全性，防止差分密码攻击。本发明所述电路可以保护加密芯片免受基于扫描链的攻击，并且面积开销相对较小，且不会增加测试时间，在不影响芯片正常功能的同时又能够实现芯片安全测试的目的。

Secure joint test action group (jtag)

A port protection network provided with a joint test action group (JTAG) core and method of use. The port protection network includes an agent device operatively connected with a streaming bus and a test access port (TAP) of the JTAG core. The port protection network also includes a master device operatively connected with the streaming bus and the TAP of the JTAG core. In the port protection network, the agent device is configured to selectively restrict access to the master device through the JTAG core.

Detection of pulse width tampering of signals

Detection of pulse width tampering of signals

A sensor system can include a sensor having a charge storage device controllably connected to a voltage source under control of a signal under test; and a readout circuit coupled to the charge storage device to determine whether the pulse width of the signal under test has changed greater than a threshold amount according to a voltage at the charge storage device. In some cases, the determination of whether the pulse width of the signal under test has changed can include determining whether the voltage satisfies a condition with respect to a comparison voltage. In some cases, the determination of whether the pulse width of the signal under test has changed can be based on a propagation delay through a delay chain, where the propagation delay is dependent on the voltage.

IC device authentication using energy characterization

Systems, methods, and apparatuses are described for verifying the authenticity of an integrated circuit device. An integrated test apparatus may use quiescent current and/or conducted electromagnetic interference readings to determine if a device under test matches the characteristics of an authenticated device. Deviations from the characteristics of the authenticated device may be indicative of a counterfeit device.

IC device authentication using energy characterization

Systems, methods, and apparatuses are described for verifying the authenticity of an integrated circuit device. An integrated test apparatus may use quiescent current and/or conducted electromagnetic interference readings to determine if a device under test matches the characteristics of an authenticated device. Deviations from the characteristics of the authenticated device may be indicative of a counterfeit device.

Ic device authentication using energy characterization

Systems, methods, and apparatuses are described for verifying the authenticity of an integrated circuit device. An integrated test apparatus may use quiescent current and/or conducted electromagnetic interference readings to determine if a device under test matches the characteristics of an authenticated device. Deviations from the characteristics of the authenticated device may be indicative of a counterfeit device.

能够进行安全扫描的集成电路

本公开涉及能够进行安全扫描的集成电路。在集成电路处于安全功能模式中时并且当访问存储在可连接到扫描链中的寄存器中与安全相关的数据的企图包括局部且选择性地在扫描使能树的相应分支处将扫描使能信号设为有效时，集成电路感测该企图。当检测到这个企图时，集成电路(i)产生导致与安全相关的数据的复位的安全警告，和/或(ii)接合旁路开关以将扫描链与相应的输出端子断开，从而阻止将与安全相关的数据经由扫描链移出IC。

片上系统和安全调试方法

提供一种片上系统和安全调试方法。所述片上系统包括：多处理器，包括多个处理器；调试控制器，包括调试端口和被配置为存储安全联合测试行动组系统的认证结果的保留逻辑；电力管理单元，被配置为管理供应给多处理器和调试控制器的电力。电力管理单元响应于调试请求信号将调试端口和保留逻辑改变到活动电力域。

片上系统和安全调试方法

提供一种片上系统和安全调试方法。所述片上系统包括：多处理器，包括多个处理器；调试控制器，包括调试端口和被配置为存储安全联合测试行动组系统的认证结果的保留逻辑；电力管理单元，被配置为管理供应给多处理器和调试控制器的电力。电力管理单元响应于调试请求信号将调试端口和保留逻辑改变到活动电力域。

Device and method for transmitting hidden signal in boundary scan testing interface

Techniques for infield testing of cryptographic circuitry

Examples include techniques for infield testing of cryptographic circuitry located on a die. The infield testing to include providing a pass or fail status of an infield test scan of the cryptographic circuitry based on comparing an output generated by the cryptographic circuitry during a test run to a signature. The output generated by the cryptographic circuitry is in response to an input generated by a linear-feedback shift register during the test run.

Intrusion detection for integrated circuits

Certain aspects of the disclosure are directed to methods and apparatuses of intrusion detection for integrated circuits. An example apparatus can include a wired communications bus configured and arranged to carry data and a plurality of integrated circuits. The plurality of integrated circuits can include a first integrated circuit configured and arranged to operate in a scan mode during which the first integrated circuit performs a scan test to detect one or more faults in circuitry of the plurality of integrated circuits. The plurality of integrated circuits can further include a second integrated circuit configured and arranged to operate in a mission mode and supervise data traffic by monitoring communications including data patterns and accesses on the wired communications bus. In response to identifying a suspected illegitimate access, the second integrated circuit can perform a security action to mitigate a suspect illegitimate action in the plurality of integrated circuits.

Scan chain security circuit and driving method thereof

A scan chain security circuit includes a scan chain including at least one flip-flop, a scan path obfuscator to obfuscate a path of a pattern sequence input to at least one first flip-flop grouped at an input side of the scan chain, in response to a first control signal, a scan path normalizer to normalize the path of the pattern sequence input to at least one second flip-flop grouped at an outside of the scan chain, in response to a second control signal, at least one dummy flip-flop interposed between the at least one first flip-flop and the at least one second flip-flop to receive a test key included in the pattern sequence, and a scan data obfuscator to damage and obfuscate an output pattern sequence output from the at least one second flip-flop, depending on whether a security key stored in a memory of a chip to be inspected is matched with the test key.