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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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30-05-2019 дата публикации

Видеоинтерфейс транспортного средства

Номер: RU0000189705U1
Автор: Виталий Вячеславович Пархоменко
Принадлежит: Общество с ограниченной ответственностью "Киберкар Мотор Рус"

Полезная модель относится к устройствам для передачи информации, ее визуализации на приборной панели транспортного средства в форме видеосигнала, а также для подключения к штатным системам транспортного средства устройств, установка которых изначально не предусмотрена конфигурацией автомобиля.Устройство включает в себя установленную в корпус одну или несколько печатных плат с размещенными на них устройством ввода информации (1), модулем беспроводного подключения Wi-Fi и Bluetooth (2), модулем громкой связи (3), модулем связи 3G/4G/GSM (4), модулем приема и обработки данных геолокации (5), модулем подключения периферийных устройств по USB (6), модулем подключения SD-карт (7), модулем управления устройствами через инфракрасный порт (8), модулем коммутации и преобразования видеосигнала (9), модулем взаимодействия с дополнительными устройствами (10), модулем подключения к шине данных (11), модулем подключения сенсорного управления (12), модулем обработки видеосигнала форматов RGB\Digital RGB\LVDS (13), модулем установки навигационной системы (13а), модулем обработки видеосигнала формата CVBS и стерео-аудиосигнала (14), модулем обработки видеосигнала формата HDMI (15), модулем программирования и обновления программного обеспечения (16), модулем коммутации и преобразования аудиосигнала с выводом для подключения динамика (17), центральным модулем управления (18). РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 189 705 U1 (51) МПК B60R 25/00 (2013.01) G06F 3/00 (2006.01) G06F 13/12 (2006.01) G06F 13/38 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (52) СПК B60R 25/00 (2019.02); G06F 3/00 (2019.02); G06F 13/12 (2019.02); G06F 13/38 (2019.02) (21)(22) Заявка: 2018130956, 27.08.2018 (24) Дата начала отсчета срока действия патента: (73) Патентообладатель(и): Общество с ограниченной ответственностью "Киберкар Мотор Рус" (RU) Дата регистрации: 30.05.2019 102737614 A, 17.10.2012. JP 2006222611 A, 24.08.2006. US 9563582 B2, 07.02.2017 ...

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Номер записи: 1
06-09-2019 дата публикации

Универсальный модульный IoT-контроллер для системы глобального мониторинга и управления энергопотреблением

Номер: RU0000192192U1
Автор: Алексей Владимирович Кычкин, Сергей Викторович Грибанов
Принадлежит: Общество с ограниченной ответственностью "ИНСАЙТ - Менеджмент"

Полезная модель относится к обработке цифровых данных с помощью электрических устройств, представляющих собой соединение запоминающих устройств, устройств ввода-вывода, устройств центрального процессора, устройств передачи информации или других сигналов между этими устройствами, и предназначенных для использования в системах глобального мониторинга и управления энергоресурсами на основе IoT-технологии. Технический результат заключается в реализации указанного назначения: расширение арсенала контроллеров путем создания универсального модульного IoT-контроллера, характеризующегося возможностью контроля энергоданных, управления потреблением энергоресурсов как в автономном режиме, так и, преимущественно, в рамках центра глобального управления потреблением энергоресурсов на базе технологии IoT-управления. Контроллер содержит встроенные в общий корпус модуль ввода-вывода 1, являющийся одновременно кросс-платой, стационарно установленный на кросс-плате системный модуль 2, а также установленный на кросс-плате разъем, предназначенный для установки на кросс-плате модуля связи 3. При этом модуль ввода-вывода 1, системный модуль 2 и модуль связи 3 (если установлен) электрически связаны между собой через кросс-плату, так что модуль ввода-вывода 1 и модуль связи 3 (если установлен) работают под непосредственным управлением системного модуля 2. Модуль ввода-вывода 1 выполнен с возможностью измерений параметров, связанных с энергопотреблением (энергоданных), и управления объектами энергопотребления. Системный модуль 2 содержит центральный процессор 15, с которым соединены два блока оперативной памяти 16, блок постоянной памяти 17, SD карта памяти 18, разъем программатора 19, разъем USB 20 через диодную защиту 21, разъем Ethernet 22 через LAN адаптер 23, блок светодиодных индикаторов 24, а также дополнительную цепь электропитания, включающую дополнительный стабилизатор 25, соединенный с выходом стабилизатора 11, аккумуляторную батарею 26, контроллер 27 заряда аккумуляторной батареи ...

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Номер записи: 2
05-01-2012 дата публикации

Dual In Line Memory Module with Multiple Memory Interfaces

Номер: US20120005400A1
Автор: William Hinson Winderweedle
Принадлежит: Texas Instruments Inc

A memory module such as a DIMM includes two separate memories with corresponding data, address and control interfaces. Each separate memory core includes plural memory banks for corresponding portions of the data interface. The separate interfaces include separate byte strobes and control signals. The two memories may be separately powered or share power connection. The two memories may be disposed on a single semiconductor integrated circuit or separate semiconductor integrated circuit. The two memories may be connected to two external memory interfaces of a single data processor or to separate data processors.

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Номер записи: 3
26-01-2012 дата публикации

Accessory attachment protocol and responsive actions

Номер: US20120023185A1
Автор: Lawrence Bolton, Nitin Ganatra, Paul Holden, Shyam Toprani
Принадлежит: Apple Inc

Embodiments of the present invention provide various communication techniques for communication between a mobile computing device and an accessory. An accessory protocol that is generic to the mobile computing device can be used for some communication. An application executing at the mobile computing device can communicate with the accessory using an application communication protocol. In some embodiments, the application communication protocol can be different from the accessory communication protocol. In other embodiments the application protocol may only be recognized by the application and the accessory. In some embodiments, messages conforming to an application protocol can be communicated between the application and the accessory by packaging the messages inside a message conforming to the accessory communication protocol.

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Номер записи: 4
02-02-2012 дата публикации

Modifying commands

Номер: US20120030452A1
Автор: Mehdi Asnaashari
Принадлежит: Micron Technology Inc

The present disclosure includes methods, devices, modules, and systems for modifying commands. One device embodiment includes a memory controller including a channel, wherein the channel includes a command queue configured to hold commands, and circuitry configured to modify at least a number of commands in the queue and execute the modified commands.

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Номер записи: 5
09-02-2012 дата публикации

Optical memory expansion

Номер: US20120033978A1
Автор: Michael Renne Ty Tan, Terrel Morris
Принадлежит: Hewlett Packard Development Co LP

Various embodiments of the present invention are directed to optical-based methods and expansion memory systems for disaggregating memory of computer systems. In one aspect, an expansion memory system comprises a first optical/electronic interface in electrical communication with a processor, a memory expansion board configured with memory, and a second optical/electronic interface attached to the memory expansion board. The first interface converts optical signals into electronic signals that are sent to the processor and converts electronic signals produced by the processor into optical signals. The second interface converts optical signals into electronic signals that are sent to the memory and converts electronic signals produced by the memory into optical signals. The optical signals are exchanged between the first and second interfaces. Embodiments also include methods for sending and receiving data in an expansion memory system.

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Номер записи: 6
16-02-2012 дата публикации

Apparatus and methods for real-time routing of received commands in a split-path architecture storage controller

Номер: US20120042101A1
Автор: Dante Cinco, Howard Young, Thomas P. Anderson
Принадлежит: LSI Corp

Apparatus and methods for real-time routing of received frames in a split-path architecture storage controller. In one exemplary embodiment, a split-path storage controller comprises a soft-path I/O processor for processing of any received frames and comprises a fast-path I/O processor for efficient processing of common read and write command. A content parsing circuit of the storage controller parses each frame substantially concurrent with reception of the frame and selects an I/O processor for processing of an initial frame and subsequent related frames. Received frames are then routed concurrently as they are received for processing by the selected I/O processor of the multiple I/O processors of the split-path storage controller.

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Номер записи: 7
16-02-2012 дата публикации

Bus bandwidth monitoring device and bus bandwidth monitoring method

Номер: US20120042111A1
Автор: Akira Ueno, Keisuke Nakazono, Tomonori Yonemoto
Принадлежит: Olympus Corp

A bus bandwidth monitoring device may include a buffer unit that is connected to a common bus, the buffer unit storing data that has been input via the common bus, a processing unit that performs predetermined processing based on the data stored in the buffer unit, and a detection unit that detects a bandwidth of the data of the common bus based on a state of storage of the data that is input to the buffer unit through the common bus.

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Номер записи: 8
16-02-2012 дата публикации

Memory systems and memory modules

Номер: US20120042204A1
Автор: Michael John Sebastian Smith, Suresh Natarajan Rajan
Принадлежит: Google LLC

One embodiment of the present invention sets forth a memory module that includes at least one memory chip, and an intelligent chip coupled to the at least one memory chip and a memory controller, where the intelligent chip is configured to implement at least a part of a RAS feature. The disclosed architecture allows one or more RAS features to be implemented locally to the memory module using one or more intelligent register chips, one or more intelligent buffer chips, or some combination thereof. Such an approach not only increases the effectiveness of certain RAS features that were available in prior art systems, but also enables the implementation of certain RAS features that were not available in prior art systems.

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Номер записи: 9
23-02-2012 дата публикации

Multiplexing application and debug channels on a single usb connection

Номер: US20120047295A1
Автор: Chi Kwok Wong
Принадлежит: Individual

A computer system for software development and debugging for an embedded system includes a Universal Serial Bus (USB), a host computer comprising a USB driver interfaced with the USB, wherein the USB driver can multiplex application data and debug data to and from the USB, and an embedded system comprising a USB module interfaced with the USB. The USB module can multiplex the application data and the debug data to and from the host computer via the USB.

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Номер записи: 10
01-03-2012 дата публикации

Sampling phase correcting host controller, semiconductor device and method

Номер: US20120049919A1
Автор: Masayoshi Murayama, Noriyo Fujii
Принадлежит: Toshiba Corp

One embodiment provides a host controller which performs a phase shift correction of a sampling clock when sampling a signal received, includes a phase shift judging section which judges whether or not it is necessary to shift a phase of the sampling clock, and up/down counts a counter in accordance with a shift direction when judging that it is necessary to shift the phase, a limit value storage section which stores a variance range limit value of the phase shift, and a shift limit judging section which judges whether or not a value of the counter exceeds the limit value of the phase shift, notifies a host device of an error when judging that the counter value exceeds the limit value, and shifts the phase of the sampling clock in accordance with the counter value of the counter when judging that the counter value does not exceed the limit value.

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Номер записи: 11
01-03-2012 дата публикации

Dynamic routing of audio among multiple audio devices

Номер: US20120053715A1
Автор: Chris Ryan, Christopher McKillop, Gregory Christie, Hooman Borghei, Justin Edward Santamaria, Nitin Ganatra
Принадлежит: Individual

A routing screen is presented on an electronic device by a user interface application in response to receiving a notification that an external audio device is connected to the electronic device. The routing screen displays representations of an internal audio device and the external audio device. In one aspect, the representations are buttons. In another aspect, the representations are entries in a list. If a user selects one of representations, the user interface application causes the audio signals to be routed to the audio device represented by the selection. An application control screen having a set of objects that represent functions for an audio application may also be displayed. One of the objects on the application control screen is modified in response status changes in the external audio device. A user may select this object to access the routing screen when the external audio device is connected.

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Номер записи: 12
01-03-2012 дата публикации

Methods and apparatus for improved serial advanced technology attachment performance

Номер: US20120054403A1
Автор: Brian A. Day
Принадлежит: LSI Corp

Methods and apparatus for improved performance in communications with a SATA target device. Features and aspects hereof provide for continuing DMA transfers from a storage controller (e.g., a SATA host or a SAS/STP initiator) to a SATA target device without regard to receipt of DMA ACTIVATE Frame Information Structures (FIS). Logic to implement these features may be provided by bridge logic within an enhanced SAS expander coupled with an enhanced SAS/STP initiator or may be provided by suitable logic in an enhanced SATA host coupled directly with an enhanced SATA target device. By continuing DMA transfer of data from the initiator/host to the SATA target device without regard to receipt of a DMA ACTIVATE FIS, more of the available bandwidth of the SAS/SATA communication link may be utilized. Other standard features of the SAS/SATA protocols provide for flow control to prevent overrun of the SATA target device's buffers.

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Номер записи: 13
01-03-2012 дата публикации

Load Balancing Scheme In Multiple Channel DRAM Systems

Номер: US20120054423A1
Автор: Feng Wang, Jonghae Kim, Matthew Michael Nowak, Shiqun Gu
Принадлежит: Qualcomm Inc

A load balancing in a multiple DRAM system comprises interleaving memory data across two or more memory channels. Access to the memory channels is controlled by memory controllers. Bus masters are coupled to the memory controllers via an interconnect system and memory requests are transmitted from the bus masters to the memory controller. If congestion is detected in a memory channel, congestion signals are generated and transmitted to the bus masters. Memory requests are accordingly withdrawn or rerouted to less congested memory channels based on the congestion signals.

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Номер записи: 14
01-03-2012 дата публикации

Method and apparatus for fuzzy stride prefetch

Номер: US20120054449A1
Автор: Shiliang Hu, Youfeng Wu
Принадлежит: Intel Corp

In one embodiment, the present invention includes a prefetching engine to detect when data access strides in a memory fall into a range, to compute a predicted next stride, to selectively prefetch a cache line using the predicted next stride, and to dynamically control prefetching. Other embodiments are also described and claimed.

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Номер записи: 15
08-03-2012 дата публикации

System and method for a hierarchical buffer system for a shared data bus

Номер: US20120059958A1
Автор: Gary A. Van Huben, Steven J. Hnatko
Принадлежит: International Business Machines Corp

The present invention provides a system and method for controlling data entries in a hierarchical buffer system. The system includes an integrated circuit device comprising: a memory core, a shared data bus, and a plurality of 1st tier buffers that receive data from the memory. The system further includes a 2nd tier transfer buffer that delivers the data onto the shared data bus with pre-determined timing. The present invention can also be viewed as providing methods for controlling moving data entries in a hierarchical buffer system. The method includes managing the buffers to allow data to flow from a plurality of 1st tier buffers through a 2nd tier transfer buffer, and delivering the data onto a shared data bus with pre-determined timing.

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Номер записи: 16
08-03-2012 дата публикации

Precision synchronisation architecture for superspeed universal serial bus devices

Номер: US20120059965A1
Автор: Peter Graham Foster
Принадлежит: CHRONOLOGIC PTY LTD

A method of providing a synchronisation channel to a SuperSpeed USB device is provided. The method including a SuperSpeed communication channel connection to the SuperSpeed USB device with a USB cable that has USB 2.0 D+ and D− data signalling lines disabled or disconnected at an upstream connection point; multiplexing synchronization information onto the D+/D− data signalling lines at the upstream connection point; and demultiplexing the synchronization information from the D+/D− signalling lines at a downstream connection point of the cable; whereby the synchronisation channel is maintained across the D+/D− data signalling lines.

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Номер записи: 17
08-03-2012 дата публикации

Electronic device, controller for accessing a plurality of chips via at least one bus, and method for accessing a plurality of chips via at least one bus

Номер: US20120059977A1
Автор: Hai-Feng Chuang
Принадлежит: Jmicron Tech Corp

An electronic device includes a plurality of chips, at least a bus and a controller, where the plurality of chips include a first chip and a second chip, the bus includes a plurality of data lines, the controller couples to the plurality of chips via the bus, and the controller is utilized for accessing the plurality of chips. The controller determines an allocation for data transmission of external data according to information about which chip the external data will be written to, where the allocation for data transmission is an arrangement of a plurality of bits of the external data transmitted on the plurality of data lines, and a first allocation for data transmission corresponding to the first chip is different from a second allocation for data transmission corresponding to the second chip.

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Номер записи: 18
15-03-2012 дата публикации

Synchronous network of superspeed and non-superspeed usb devices

Номер: US20120066418A1
Автор: Peter Graham Foster
Принадлежит: CHRONOLOGIC PTY LTD

A method of synchronising the operation of a plurality of SuperSpeed USB devices and a plurality of non-SuperSpeed USB devices is provided. The method includes establishing a SuperSpeed synchronisation channel for each of the plurality of SuperSpeed USB devices; establishing a non-SuperSpeed synchronisation channel for each of the plurality of non-SuperSpeed USB devices; synchronising a respective local clock of each of the plurality of SuperSpeed USB devices; synchronising a respective local clock of each of the plurality of non-SuperSpeed USB devices; and synchronising the SuperSpeed and non-SuperSpeed synchronisation channels so that the SuperSpeed and non-SuperSpeed devices can operate in synchrony.

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Номер записи: 19
15-03-2012 дата публикации

Multi-device docking with a displayport compatible cable

Номер: US20120066425A1
Автор: Henry Zeng, Ji Park
Принадлежит: Integrated Device Technology Inc

A docking system utilizing a single DisplayPort cable connection to a computer system is provided. In one embodiment, the docking system includes a single DisplayPort (“DP”) input, a management layer module coupled to receive video inputs from the single DP input and to provide video data to at least one video monitor output, and a USB layer module coupled to receive an AUX channel from the single DP input and to couple the AUX channel with a USB hub.

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Номер записи: 20
15-03-2012 дата публикации

Memory Architecture with Policy Based Data Storage

Номер: US20120066473A1
Автор: Robert B. Tremaine, Robert W. Wisniewski
Принадлежит: International Business Machines Corp

A computing system and methods for memory management are presented. A memory or an I/O controller receives a write request where the data two be written is associated with an address. Hint information may be associated with the address and may relate to memory characteristics such as an historical, O/S direction, data priority, job priority, job importance, job category, memory type, I/O sender ID, latency, power, write cost, or read cost components. The memory controller may interrogate the hint information to determine where (e.g., what memory type or class) to store the associated data. Data is therefore efficiently stored within the system. The hint information may also be used to track post-write information and may be interrogated to determine if a data migration should occur and to which new memory type or class the data should be moved.

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Номер записи: 21
15-03-2012 дата публикации

Compound universal serial bus architecture providing precision synchronisation to an external timebase

Номер: US20120066537A1
Автор: Peter Graham Foster
Принадлежит: CHRONOLOGIC PTY LTD

A method of synchronising a compound Super Speed USB device, comprising: providing data communication between a host computing device and the compound Super Speed USB device across the Super Speed USB communication channel; establishing a Super Speed USB communication channel to a Super Speed USB function of the compound USB device; establishing a non-Super Speed synchronisation channel to a non-Super Speed USB function of the compound USB device; and synchronising a local clock of the compound USB device to a periodic data structure within a data stream in the non-Super Speed synchronisation channel so that the local clock can enable synchronous operation of the compound USB device with one or more comparable USB devices.

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Номер записи: 22
22-03-2012 дата публикации

Method of uniform distribution for increasing display rate

Номер: US20120069030A1
Автор: SONG Shang
Принадлежит: ZHONGQING DIGITAL EQUIPMENT CO Ltd

A method of uniform distribution for increasing a display rate. For data to be displayed, dividing a complete effective output enable (OE) time that is greater than one serial shift cycle into several unit serial shift cycles and uniformly distributing the effective OE time for display. The method implements the uniform distribution of the display time to the maximum extent by using an OE signal under the condition that the whole display time remains unchanged, thereby increasing effective output number of the uniform distribution, uniformly maintaining a display effect and steadily improving a refresh rate effect, so as to effectively increase a display quality and avoid a significant loss of brightness.

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Номер записи: 23
22-03-2012 дата публикации

Reordering in the Memory Controller

Номер: US20120072679A1
Автор: Hao Chen, Sukalpa Biswas
Принадлежит: Apple Inc

In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.

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Номер записи: 24
29-03-2012 дата публикации

Transaction reordering arrangement

Номер: US20120079154A1
Автор: Daniele Mangano, Ignazio Antonino Urzi
Принадлежит: STMicroelectronics Grenoble 2 SAS, STMICROELECTRONICS SRL

An embodiment of a transaction reordering arrangement is provided. The transaction reordering arrangement includes a queue into which respective responses to requests are writable and a controller configured to control a position in said queue to which said respective responses to said requests are written. The position is controlled such that the responses are read out of said queue in an order which corresponds to an order in which the requests are issued.

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Номер записи: 25
29-03-2012 дата публикации

Cache with Multiple Access Pipelines

Номер: US20120079204A1
Автор: Abhijeet Ashok Chachad, Jonathan (Son) Hung Tran, Raguram Damodaran, Sanjive Agarwala, Timothy David Anderson
Принадлежит: Texas Instruments Inc

Parallel pipelines are used to access a shared memory. The shared memory is accessed via a first pipeline by a processor to access cached data from the shared memory. The shared memory is accessed via a second pipeline by a memory access unit to access the shared memory. A first set of tags is maintained for use by the first pipeline to control access to the cache memory, while a second set of tags is maintained for use by the second pipeline to access the shared memory. Arbitrating for access to the cache memory for a transaction request in the first pipeline and for a transaction request in the second pipeline is performed after each pipeline has checked its respective set of tags.

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Номер записи: 26
29-03-2012 дата публикации

Module Interrogation

Номер: US20120079508A1
Автор: Ashwin S. Needamangala, John R. Ashmun, Kantcho I. Bogdev, Mariyan D. Fransazov, Ying Deng
Принадлежит: Microsoft Corp

Module interrogation techniques are described in which modules configured to rely upon one or more operating system features are interrogated to determine which features are used and by which modules. A module is loaded that is configured to interact with a plurality of features provided by an operating system. Using one or more redirection techniques, calls made by the module to access features of the operating system are redirected to alternate functionality. Based on the redirection, data is generated to indicate the features of the operating system that are used by the module. The techniques may be performed for each of a plurality of modules to populate a database that relates features of the operating system to the plurality of modules.

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Номер записи: 27
05-04-2012 дата публикации

Demand based usb proxy for data stores in service processor complex

Номер: US20120084552A1
Автор: Mallik Bulusu, Michael A. Rothman, Palsamy Sakthikumar, Robert C. Swanson, Vincent J. Zimmer
Принадлежит: Intel Corp

A method, apparatus, system, and computer program product for secure server system management. A payload containing system software and/or firmware updates is distributed in an on-demand, secure I/O operation. The I/O operation is performed via a secured communication channel inaccessible by the server operating system to an emulated USB drive. The secure communication channel can be established for the I/O operation only after authenticating the recipient of the payload, and the payload can be protected from access by a potentially-infected server operating system. Furthermore, the payload can be delivered on demand rather than relying on a BIOS update schedule, and the payload can be delivered at speeds of a write operation to a USB drive.

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Номер записи: 28
26-04-2012 дата публикации

Auto Start Method and System of Universal Serial Bus Data Card

Номер: US20120102238A1
Автор: Zhigang Wei
Принадлежит: ZTE Corp

An auto start method and system for Universal Serial Bus (USB) data card. The method includes: when a terminal detects a data card is inserted, judging that the terminal does not install a driver of the data card, and using the default configuration mode to configure the data card and reading the content of the data card to install the driver; otherwise, using the driver of the data card to load the data card. After the PC finishes installing the related driver and software, the data card can directly start by the normal configuration when it is inserted again, therefore, the method can improve the auto start speed of the data card. Which kind of configuration is used to start the data card depends on the static configuration value in the registry, therefore, the performance of the method is reliable.

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Номер записи: 29
26-04-2012 дата публикации

Disabling outbound drivers for a last memory buffer on a memory channel

Номер: US20120102256A1
Автор: Dennis W. Brzezinski, Pete D. Vogt, Warren R. Morrow
Принадлежит: Individual

Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.

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Номер записи: 30
26-04-2012 дата публикации

Solid State Drive Architecture

Номер: US20120102263A1
Автор: Ajoy Aswadhati
Принадлежит: FASTOR SYSTEMS Inc

Embodiments of apparatuses, methods and systems of solid state drive are disclosed. One embodiment of a solid state drive includes a non-blocking fabric, wherein the non-blocking fabric comprises a plurality of ports, wherein a subset of the plurality of ports are each connected to a flash controller that is connected to at least one array of flash memory. Further, this embodiment includes a flash scheduler for scheduling data traffic through the non-blocking fabric, wherein the data traffic comprises a plurality of data packets, wherein the flash scheduler extracts flash fabric header information from each of the data packets and schedules the data traffic through the non-blocking fabric based on the extracted flash fabric header information. The scheduled data traffic provides transfer of data packets through the non-blocking fabric from at least one array of flash memory to at least one other array of flash memory.

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Номер записи: 31
26-04-2012 дата публикации

Transmission device, transmission method, and non-transitory computer-readable storage medium

Номер: US20120102293A1
Автор: Kenji Shirase, Shogo OGAMI, Tatsuhiko Negishi
Принадлежит: Fujitsu Ltd

A transmission device includes a plurality of memory units storing requests for processing information stored in a memory. Moreover, when a request from a first device is received, the transmission device analyzes the received request to specify an address range including a memory address storing data to be subjected to the requested processing. The transmission device stores requests in different memory units for each address range. Moreover, the transmission device determines for each memory unit whether the stored requests are being executed by a second device. The transmission device transmits a request which is stored in a memory unit and which is determined to be not being executed, to the second device.

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Номер записи: 32
03-05-2012 дата публикации

Data signal mirroring

Номер: US20120109896A1
Автор: Michael M. Abraham, Peter Feeley
Принадлежит: Micron Technology Inc

Methods, devices, and systems for data signal mirroring are described. One or more methods include receiving a particular data pattern on a number of data inputs/outputs of a memory component, and responsive to determining that a mirrored version of the particular data pattern is received by the memory component, configuring the number of data inputs/outputs to be mirrored.

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Номер записи: 33
10-05-2012 дата публикации

Wireless tramsmission of media from a media player

Номер: US20120115414A1
Автор: Anthony M. Fadell, John Benjamin Filson, Stephen Paul Zadesky
Принадлежит: Apple Inc

Wireless transmission of media from a media player is provided. A handheld media player includes a storage medium for storing a plurality of media items, a user interface for selecting one or more of the media items, a playback device for playing a selected media item for a user of the handheld media player, and a wireless transmitter configured to wirelessly transmit the selected media item to one or more media devices. The wireless transmitter can be configured to wirelessly transmit the selected media item while the playback device plays the selected media item for the user of the handheld media player.

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Номер записи: 34
10-05-2012 дата публикации

Providing indirect data addressing for a control block at a channel subsystem of an i/o processing system

Номер: US20120117275A1
Автор: Catherine C. Huang, Dale F. Riedy, Daniel F. Casper, Gustav E. Sittmann, John R. Flanagan, Matthew J. Kalos, Ugochukwu C. Njoku
Принадлежит: International Business Machines Corp

An computer program product, apparatus, and method for facilitating input/output (I/O) processing for an I/O operation at a host computer system configured for communication with a control unit. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes the host computer system obtaining a transport command word (TCW) for an I/O operation. The TCW specifies a location of one or more I/O commands and a flag set to indicate that the location is an indirect address. The host computer system extracts the location of the one or more I/O commands and the flag from the TCW, gathers the one or more I/O commands responsive to the location specified by the TCW and the flag, and then forwards the one or more I/O commands to the control unit for execution.

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Номер записи: 35
10-05-2012 дата публикации

Providing fault-tolerant spread spectrum clock signals in a system

Номер: US20120117415A1
Автор: Mark A. Shaw, Rangaswamy Arumugham, Stuart Haden
Принадлежит: Hewlett Packard Development Co LP

To provide fault-tolerant, spread spectrum clock signals, a plurality of processing modules having respective spread spectrum control circuits are provided. Clock signals of redundant clock sources are provided to the plurality of processing modules. Failover control logic selects a corresponding one of the clock signals from the redundant clock sources for use in each of the processing modules. Frequency spreading is applied to the corresponding selected clock signal in each of at least some of the plurality of processing module.

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Номер записи: 36
10-05-2012 дата публикации

Memory card

Номер: US20120117430A1
Автор: Kui-Hyun RO, Sung-Eun YUN, Young-Jae Jung, Yun-Bo Yang
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A memory card includes a memory cell, a connector, a controller, and firmware. The memory cell can switch between a plurality of states. The connector can be connected to an external device and exchange signals including commands and data with the external device. The controller exchanges signals with the connector, analyzes a received signal, and accesses the memory cell to record, retrieve or modify data based on the analysis result. The firmware is located within the controller, controls the operation of the controller, and can be set to a test mode or a user mode. When the firmware receives a test command from the external device and the firmware is set to the test mode, the firmware performs a defect test on the memory cell and transmits the result of the defect test to the external device through the connector.

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Номер записи: 37
10-05-2012 дата публикации

Detection circuit, detection method thereof, and memory system including the detection circuit

Номер: US20120117645A1
Автор: Ji Myung Na, Jung Hyun Kim, Seong Il Park
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A detection circuit, including a sensing circuit configured to sense whether there is an external attack and generate second data from first data, a data conversion circuit configured to convert the first data to third data, and a comparator configured to compare the second data with the third data.

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Номер записи: 38
17-05-2012 дата публикации

Hybrid storage device and electronic system using the same

Номер: US20120124266A1
Автор: Byung-Hoon Chung, Jae-won You, Kyu-yeol Park, Tae-yung Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A hybrid storage device is provided. The hybrid storage device includes a first storage part that comprises an interface device based on a first standard, a second storage part that comprises an interface device based on a second standard, and a connector for interface devices that is shared by the first storage part and the second storage part and comprises a plurality of pins.

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Номер записи: 39
24-05-2012 дата публикации

Duty cycle independent real time dynamic programming implementation for hybrid systems controls optimization

Номер: US20120130695A1
Автор: Chinmaya B. Patil, Vasilios Tsourapas
Принадлежит: Eaton Corp

Predicted environment conditions are received for time steps within a prediction horizon N. Information is accessed regarding expected system responses generated by a system model, each expected system response related to a different combination of control parameters and starting environment conditions applied to the model. An optimal response is designated for each combination of starting environment conditions for each time step from time step N- 1 to the current time step based in part on the expected system response and the predicted environment conditions, each optimal response in a time step based at least in part on an optimal response determined for a later time step. For the current time step, for starting environment conditions substantially similar to the current environment conditions, the combination of control parameters that results in the system response designated as the optimal response is determined from the expected system responses and is applied to the system.

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Номер записи: 40
24-05-2012 дата публикации

Method and system for protecting against multiple failures in a raid system

Номер: US20120131383A1
Автор: Choon-Seng Tan, Greg J. Pellegrino, Ryan A. Callison, William C. Galloway
Принадлежит: Pivot3 Inc

Embodiments of methods of protecting RAID systems from multiple failures and such protected RAID systems are disclosed. More particularly, in certain embodiments of a distributed RAID system each data bank has a set of associated storage media and executes a similar distributed RAID application. The distributed RAID applications on each of the data banks coordinate among themselves to distribute and control data flow associated with implementing a level of RAID in conjunction with data stored on the associated storage media of the data banks. Furthermore, one or more levels of RAID may be implemented within one or more of the data banks comprising the distributed RAID system.

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Номер записи: 41
31-05-2012 дата публикации

Memory Modules and Devices Supporting Configurable Core Organizations

Номер: US20120134084A1
Автор: Craig E. Hampel, Donald C. Stark, Ely K. Tsern, Frederick A. Ware, Richard E. Perego
Принадлежит: RAMBUS INC

Described are memory apparatus organized in memory subsections and including configurable routing to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey width selection information to configurable memory apparatus and support point-to-point data interfaces for multiple width configurations.

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Номер записи: 42
31-05-2012 дата публикации

Computer device and method for recognizing a removable storage device

Номер: US20120137023A1
Автор: Yan-Yan Zhan
Принадлежит: Hon Hai Precision Industry Co Ltd, Hongfujin Precision Industry Shenzhen Co Ltd

A system and a method for recognizing removable devices of a computer device, and displaying a dialog box to prompt whether a removable storage device needs to be renamed and if so to receive input data accordingly from a user, if a USB port has been newly connected to the removable storage device. The recognition method further includes acquiring a unique port number of the USB port actually connected to the removable storage device, and acquiring a device name of a system disk name of the removable storage device originally allocated by the computer device, if the removable storage device needs to be renamed. The recognition method further may utilize the unique port number of the USB port as the new device name of the removable storage device in renaming it.

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Номер записи: 43
31-05-2012 дата публикации

Computing device and serial communication method of the computing device

Номер: US20120137035A1
Автор: Ji-Zhi Yin, Jian Peng
Принадлежит: Hon Hai Precision Industry Co Ltd, Hongfujin Precision Industry Shenzhen Co Ltd

A serial communication method is applied in a computing device to communicate serially with any external serial device. The computing device includes a baseboard management controller (BMC) and an operating system (OS). The BMC includes at least one physical serial port. The method generates a virtual serial port for the OS by emulating serial port functionality of the physical serial port. When the BMC is initializing the physical serial port and a serial device is connected to the physical serial port, an interrupt handler is activated to handle an interrupt triggered to the BMC by the serial device. The interrupt handler is deactivated when the physical serial port has been initialized by the BMC.

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Номер записи: 44
07-06-2012 дата публикации

Data download method and terminal

Номер: US20120142332A1
Автор: Fei Li
Принадлежит: ZTE Corp

The present invention provides a data downloading method and a terminal, wherein the data downloading method includes: a communication processor receiving an open channel request from a universal integrated circuit card, and sending a connection request message to an application processor according to the open channel request; the communication processor sending a connection success message to the universal integrated circuit card, so as to instruct the universal integrated circuit card to download data The present invention not only enables a process of downloading an application over the air to the UICC by using the BIP (bearer independent protocol) protocol to be completed in a single processor, but also supports the process to be completed in multiple processors.

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Номер записи: 45
14-06-2012 дата публикации

Device action service

Номер: US20120151100A1
Автор: Allison O'Mahony, Francisco Jose Garcia-Ascanio, Graeme Andrew Kyle Roche, Rachel Karin Popkin
Принадлежит: Microsoft Corp

A user may operate many devices, each of which may provide a set of actions, such as installing firmware or software or viewing the contents of the device. However, in order to perform these actions, the user may have to interact with each device using a different user interface, resulting in an inconsistent user experience. Instead, a device action service may allow a user to identify his or her devices, may identify the actions available for each device (e.g., by interacting with a device source of each device, such as a manufacturer); and upon the request of the user, may present a list of the user's devices and the actions available for each device. The actions may comprise hyperlinks to various portions of the website of the device source (e.g., a driver page and a service registration page), or controls invoking the requested action upon the device.

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Номер записи: 46
14-06-2012 дата публикации

Method for operating flash memories on a bus

Номер: US20120151122A1
Автор: Ming-Hung Hsieh
Принадлежит: Individual

Enable a read command of a first flash memory. After the read command of the first flash memory is enabled, a ready/busy signal of the first flash memory enters a busy waiting time, and a read command of a second flash memory starts to be enabled. Start to read data of the first flash memory when the busy waiting time is over. Enable the read command of the first flash memory again upon completion of reading the data of the first flash memory. Start to read data of the second flash memory after the read command of the first flash memory is enabled again. And enable the read command of the second flash memory again upon completion of reading the data of the second flash.

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Номер записи: 47
14-06-2012 дата публикации

Providing frame start indication in a memory system having indeterminate read data latency

Номер: US20120151172A1
Автор: Kevin C. Gower, Paul W. Coteus, Robert B. Tremaine, Warren E. Maule
Принадлежит: International Business Corp

A method for providing frame start indication that includes receiving a data transfer via a channel in a memory system. The receiving is in response to a request, and at an indeterminate time relative to the request. It is determined whether the data transfer includes a frame start indicator. The data transfer and “n” subsequent data transfers are captured in response to determining that the data transfer includes a frame start indicator. The data transfer and the “n” subsequent data transfers make up a data frame, where “n” is greater than zero.

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Номер записи: 48
21-06-2012 дата публикации

Memory system and data transfer method

Номер: US20120159016A1
Автор: Hirokazu Morita
Принадлежит: Toshiba Corp

According to the embodiment, a memory system includes a first memory which includes a memory cell array and a read buffer, a second memory, a command queue, a command sorting unit, and a data transfer unit. The command sorting unit dequeues commands excluding a later-arrived command whose access range overlaps with an access range of an earlier-arrived command from the command queue. The data transfer unit performs a data preparing process of transferring data that is specified by dequeued read command and is read out from the memory cell array to the read buffer, a first data transfer of outputting the data stored in the read buffer, and a second data transfer of storing data that is specified by dequeued write command in the second memory. The data transfer unit is capable of performing the data preparing process and the second data transfer in parallel.

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Номер записи: 49
21-06-2012 дата публикации

Semiconductor device

Номер: US20120159020A1
Автор: Daijiro Harada, Takashi Utsumi
Принадлежит: Renesas Electronics Corp

There is a need to cause a delay to occur less frequently than the related art during processing of an input signal in need of relatively fast processing. In a semiconductor device, a conversion portion includes first channels and second channels and A/D converts a signal input to a selected channel. A signal input to the first channel requires faster processing than a signal input to the second channel. The conversion portion receives a scan conversion instruction from a central processing unit, sequentially selects the input channels in a specified selection order, and successively performs A/D conversion. In this case, the conversion portion notifies a peripheral circuit of completion of A/D conversion after completion of A/D conversion on signals input to the first channels and before completion of A/D conversion on input signals input to all input channels.

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Номер записи: 50
21-06-2012 дата публикации

Storage topology manager

Номер: US20120159021A1
Автор: Alan Warwick, Andrea D'amato, Sai Sudhir Anantha Padmanaban
Принадлежит: Microsoft Corp

Defining a storage topology of a distributed computing system including a set of machine nodes. A method includes dynamically receiving from a number of nodes in the distributed computing system information about storage devices. Each node sends information about storage devices connected to that particular node. The information is sent dynamically from each node as conditions related to storage change and as a result of conditions related to storage changing. From the received information, the method includes dynamically constructing a storage topology representation of the distributed computed system.

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Номер записи: 51
21-06-2012 дата публикации

Memory Module With Reduced Access Granularity

Номер: US20120159061A1
Автор: Craig E. Hampel, Frederick A. Ware
Принадлежит: RAMBUS INC

A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

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Номер записи: 52
28-06-2012 дата публикации

Methods and tools to debug complex multi-core, multi-socket qpi based system

Номер: US20120166882A1
Автор: Binata Bhattacharyya, Jayakrishna Guddeti, Keshavan K. Tiruvallur
Принадлежит: Intel Corp

Methods and apparatus relating to debugging complex multi-core and/or multi-socket systems are described. In one embodiment, a debug controller detects an event corresponding to a failure in a computing system and transmits data corresponding to the event to one of the other debug controllers in the system. Other embodiments are also disclosed and claimed.

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Номер записи: 53
05-07-2012 дата публикации

Memory controller for strobe-based memory systems

Номер: US20120170389A1
Автор: Benedict Lau, Jade M. Kizer, Sivakumar Doraiswamy
Принадлежит: RAMBUS INC

A memory controller for strobe-based memory systems is disclosed. The memory controller comprises a circuit to generate a control signal having a predetermined timing relationship with respect to a first clock signal, a circuit to receive the control signal, and a receiver to sample the read data in response to the qualified read strobe signal. The receiving circuit comprises an input to receive an external read strobe signal transmitted by a semiconductor memory device, circuitry to synchronize the control signal and the received read strobe signal to have a common timing relationship with respect to each other, and circuitry to gate the read strobe signal based on the synchronized control signal.

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Номер записи: 54
05-07-2012 дата публикации

Peripheral device detection with short-range communication

Номер: US20120171951A1
Автор: Maarten 't Hooft
Принадлежит: Google LLC

In general, embodiments of the present disclosure are directed to techniques for configuring a mobile device according to detection of one or more peripheral devices in an environment using short-range wireless communication. In one example, a method includes, receiving, by a computing device that communicates with a peripheral device using short-range wireless communication, a unique identifier of the peripheral device. If the computing device recognizes the unique identifier of the peripheral device, the computing device may determine a configuration operation based on the unique identifier that changes a current operating state of at least one application executing on the computing device to a different operating state. If the computing device does not recognize the unique identifier of the peripheral device, the computing device may send a lookup request to a network resource external to the computing device that requests data specifying the configuration operation for the computing device.

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Номер записи: 55
05-07-2012 дата публикации

System Timeout Reset Based on Media Detection

Номер: US20120173890A1
Автор: Ansuman Tapan Satpathy, Haitang Wang, Michael A. Root
Принадлежит: MOTOROLA MOBILITY LLC

In embodiments of system timeout reset based on media detection, an electronic device includes an interface connection that couples the electronic device to a peripheral. A power manager application is implemented to timeout the interface connection if user interaction with the electronic device is not detected for a timeout duration. A media data monitor is implemented to detect audio data in an audio channel of the interface connection, and initiate a reset of the timeout duration responsive to the audio data being detected. Video can continue to be rendered by the peripheral if the audio data is detected to initiate the reset of the timeout duration.

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Номер записи: 56
05-07-2012 дата публикации

System and method for accelerating input/output access operation on a virtual machine

Номер: US20120174102A1
Автор: Benny Koren, Dror Goldenberg, Michael Kagan, Michael Tsirkin
Принадлежит: MELLANOX TECHNOLOGIES LTD

A system and method for accelerating input/output (IO) access operation on a virtual machine, The method comprises providing a smart IO device that includes an unrestricted command queue (CQ) and a plurality of restricted CQs and allowing a guest domain to directly configure and control IO resources through a respective restricted CQ, the IO resources allocated to the guest domain. In preferred embodiments, the allocation of IO resources to each guest domain is performed by a privileged virtual switching element. In some embodiments, the smart IO device is a HCA and the privileged virtual switching element is a Hypervisor.

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Номер записи: 57
12-07-2012 дата публикации

Column address strobe write latency (cwl) calibration in a memory system

Номер: US20120176850A1
Автор: Lydia M. Do, William M. Zevin
Принадлежит: International Business Machines Corp

Column address strobe write latency (CWL) calibration including a method for calibrating a memory system. The method includes entering a test mode at a memory device and measuring a CWL at the memory device. A difference between the measured CWL and a programmed CWL is calculated. The calculated difference is transmitted to a memory controller that uses the calculated difference for adjusting a timing delay to match the measured CWL.

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Номер записи: 58
19-07-2012 дата публикации

Memory System with Multi-Level Status Signaling and Method for Operating the Same

Номер: US20120182780A1
Автор: Steven Cheng
Принадлежит: SanDisk Technologies LLC

A memory system includes a status circuit having a common status node electrically connected to a respective status pad of each of a plurality of memory chips. The memory system also includes a plurality of resistors disposed within the status circuit to define a voltage divider network for generating different voltage levels at the common status node. Each of the different voltage levels indicates a particular operational state combination of the plurality of memory chips. Also, each of the plurality of memory chips is either in a first operational state or a second operational state. Additionally, the different voltage levels are distributed within a voltage range extending from a power supply voltage level to a reference ground voltage level.

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Номер записи: 59
19-07-2012 дата публикации

Wireless network connection system and method

Номер: US20120185606A1
Автор: Iulian Mocanu
Принадлежит: Sierra Wireless Inc

The present invention provides a device, system, method and computer-program product for transferring information between a host computer and a wireless network. The device and system comprise an operatively linked mass storage module and modem module. The mass storage module is configured to transfer information with a host computer. The modem module is configured to transfer information with one or more wireless networks. Communication between the host computer and the mass storage module is at least in part using file system input/output protocols. One or more virtual drivers are provided on the host computer to enable communication with the modem module without installation of modem specific drivers.

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Номер записи: 60
19-07-2012 дата публикации

Apparatus and methods for serial interfaces

Номер: US20120185623A1
Автор: Florinel G. Balteanu, James Henry Ross
Принадлежит: Skyworks Solutions Inc

Apparatus and methods for serial interfaces are provided. In one embodiment, an integrated circuit operable to communicate over a serial interface is provided. The integrated circuit includes analog circuitry, registers for controlling the operation of the analog circuitry, and a distributed slave device including a primary block and a secondary block. The registers are accessible over the serial interface using a shared register address space. Additionally, the primary block is electrically connected to the serial interface and to a first portion of the registers and the secondary block is electrically connected to the primary block and to a second portion of the registers.

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Номер записи: 61
19-07-2012 дата публикации

System And Method For Consolidated Information Handling System Component Drivers

Номер: US20120185878A1
Автор: Christian Garvin, Troy Tiritilli
Принадлежит: Individual

An information handling system which includes plural processing components operable to process information wherein at least one processing component has plural region-specific modes of operation, a driver package associated with the at least one processing component wherein the driver package has plural region-specific drivers, and an encrypted key stored on a processing component wherein the encrypted key designates one of the plural region-specific drivers to manage the processing component.

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Номер записи: 62
26-07-2012 дата публикации

Integrated circuit with staggered signal output

Номер: US20120188835A1
Автор: Benedict C. Lau, Bret Stott, Ian P. Shaeffer
Принадлежит: RAMBUS INC

A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

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Номер записи: 63
26-07-2012 дата публикации

Method for extracting ibis simulation model

Номер: US20120191437A1
Автор: Koji Matsuo, Sadahiro Nonoyama, Shinji Itano, Tadaaki YOSHIMURA, Yoji Nishio, Yoshiyuki YAGAMI
Принадлежит: Elpida Memory Inc

A method for extracting an accurate IBIS simulation model of a semiconductor device including a plurality of semiconductor chips comprises: extracting an AC characteristics model of a first output buffer in an IBIS simulation model by treating first and second output buffers of first and second semiconductor chips connected to a single external connection terminal as a transistor model and executing a transistor-level circuit simulation; calculating an output capacitance model of the first output buffer as an IBIS simulation model by adding output capacitances of the first and second output buffers as a transistor-level circuit simulation model; and synthesizing an IBIS simulation model of the first output buffer viewed from the external connection terminal by using the AC characteristics model and the output capacitance model.

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Номер записи: 64
26-07-2012 дата публикации

Expandable asymmetric-channel memory system

Номер: US20120191921A1
Автор: Arun Vaidyanath, Ian Shaeffer, Sanku Mukherjee
Принадлежит: RAMBUS INC

An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.

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Номер записи: 65
26-07-2012 дата публикации

Memory management method

Номер: US20120191939A1
Автор: Donald R. DeSota, Joseph H. Robichaux, Rajendra D. Panda, Robert H. Bell, JR., Steven P. Hartman, Venkat R. Indukuru
Принадлежит: International Business Machines Corp

According to one aspect of the present disclosure a method and technique for managing memory access is disclosed. The method includes setting a memory databus utilization threshold for each of a plurality of processors of a data processing system to maintain memory databus utilization of the data processing system at or below a system threshold. The method also includes monitoring memory databus utilization for the plurality of processors and, in response to determining that memory databus utilization for at least one of the processors is below its threshold, reallocating at least a portion of unused databus utilization from the at least one processor to at least one of the other processors.

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Номер записи: 66
02-08-2012 дата публикации

Interface card

Номер: US20120194529A1
Автор: Yu-Lin Liu
Принадлежит: Micro Star International Co Ltd

An interface card comprising a graphic unit, an outputting interface, an inputting interface, an assigning processor and a card body is disclosed. The inputting interface is used for receiving a PCIE inputting signal. When the inputting interface is electrically connected to a CPU via a connector, the PCIE inputting signal is inputted to the assigning processor via an inputting interface. The assigning processor assigns a PCIE outputting signal to a graphic unit according to the PCIE inputting signal, and further assigns another PCIE outputting signal to another graphic unit according to the PCIE inputting signal when the outputting interface is externally connected to another graphic unit. The card body is used for placing the graphic unit, the outputting interface, the assigning processor and the inputting interface.

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Номер записи: 67
02-08-2012 дата публикации

Apparatus and method for providing application auto-install function in digital device

Номер: US20120198099A1
Автор: Eun-Young Song, Gyu-tae Park, Joon-Hwan Kwon
Принадлежит: SAMSUNG ELECTRONICS CO LTD

An apparatus and method install an application in a digital device. An apparatus for providing a connection program to a desired peripheral device in a digital device includes a communication unit for receiving system information from a peripheral device and transmitting a connection program list, a program detecting unit for analyzing the received system information and creating the connection program list executable in the peripheral device, and a control unit for transmitting the created connection program list to the peripheral device.

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Номер записи: 68
02-08-2012 дата публикации

Memory Attribute Sharing Between Differing Cache Levels of Multilevel Cache

Номер: US20120198166A1
Автор: Joseph Raymond Michael Zbiciak, Naveen Bhoria, Raguram Damodaran
Принадлежит: Texas Instruments Inc

The level one memory controller maintains a local copy of the cacheability bit of each memory attribute register. The level two memory controller is the initiator of all configuration read/write requests from the CPU. Whenever a configuration write is made to a memory attribute register, the level one memory controller updates its local copy of the memory attribute register.

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Номер записи: 69
02-08-2012 дата публикации

System and Method for Facilitating Data Transfer Between a First Clock Domain and a Second Clock Domain

Номер: US20120198267A1
Автор: Alexander Raykhman, Philip Crary, Srinjoy Das
Принадлежит: Qualcomm Atheros Inc

System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.

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Номер записи: 70
09-08-2012 дата публикации

Autonomous, Scalable, Digital System For Emulation of Wired-Or Hardware Connection

Номер: US20120203537A1
Автор: Daniel J. Barus
Принадлежит: International Business Machines Corp

A method and device for preserving the wired-OR nature of the clock signal connection between two devices without a direct analog connection between the lines and in an infinitely scalable fashion. The method includes detecting a logic state at a first connector and a second connector and driving an appropriate connector of the device to an active state in response to determining that a connector is driving an active state. The device includes first and second connectors for communicating logic states and driving active states in response to detected logic states.

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Номер записи: 71
09-08-2012 дата публикации

Transfer of Uncompressed Multimedia Contents or Data Communications

Номер: US20120203937A1
Автор: Ning Zhu, Soumendra Mohanty
Принадлежит: Individual

A system and corresponding method for transferring data via an interface assembly. The data may be transferred between a USB port of a first device and a media port of a second device. Uncompressed high definition media data may be received from the USB port. The received uncompressed high definition media data may be supplied to a media connector in accordance with a first media standard, such that the supplied data can be transmitted in accordance with the first media standard via the media connector to the media port of the second device. The uncompressed high definition media data may include multimedia data and side-band communication data. A single signal may be encoded and decoded in accordance with a protocol that enables the single signal to communicate all side-band communication to and from the source device via a single pin of a USB connector.

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Номер записи: 72
09-08-2012 дата публикации

Livelock prevention mechanism in a ring shaped interconnect utilizing round robin sampling

Номер: US20120203946A1
Автор: Amit Golander, Eric F. Robinson, Nadav Levison, Omer Heymann
Принадлежит: International Business Machines Corp

A novel and useful cost effective mechanism for detecting the livelock/starvation of transactions in a ring shaped interconnect that utilizes minimal logic resources. Rather than monitor all transactions concurrently in the ring, the mechanism monitors only a single transaction in the ring. A sampling point is located at a point in the ring which contains a set of N latches. If the monitored transaction is not being starved, it is released and the detection logic moves on the next candidate transaction in round robin fashion. If the monitored transaction passes the sampling point a threshold number of times, it is deemed to be starved and a starvation prevention handling procedure is activated. By traversing the entire ring a single transaction at a time, all starving transactions will eventually be detected with an upper limit on the detection time of O(N 2 ).

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Номер записи: 73
09-08-2012 дата публикации

Memory System with Calibrated Data Communication

Номер: US20120204054A1
Автор: Benedict Chung-Kwong Lau, Bruno W. Garlepp, Donald C. Stark, Jared Levan Zerbe, Jun Kim, Kevin S. Donnelly, Leung Yu, Mark A. Horowitz, Roxanne Vu, Stefanos Sidiropoulos, Tsyr-Chyang Ho
Принадлежит: RAMBUS INC

An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

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Номер записи: 74
30-08-2012 дата публикации

Opportunistic block transmission with time constraints

Номер: US20120221792A1
Автор: Arthur S. Hitomi, Jeffrey De Vries
Принадлежит: Endeavors Technology Inc

A technique for determining a data window size allows a set of predicted blocks to be transmitted along with requested blocks. A stream enabled application executing in a virtual execution environment may use the blocks when needed.

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Номер записи: 75
30-08-2012 дата публикации

Semiconductor memory device and method of controlling the same

Номер: US20120221918A1
Автор: Hironori Uchikawa, Shinichi Kanno
Принадлежит: Hironori Uchikawa, Shinichi Kanno

A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

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Номер записи: 76
06-09-2012 дата публикации

Logical address translation

Номер: US20120226887A1
Автор: Martin L. Culley, Troy A. Manning, Troy D. Larsen
Принадлежит: Micron Technology Inc

The present disclosure includes methods for logical address translation, methods for operating memory systems, and memory systems. One such method includes receiving a command associated with a LA, wherein the LA is in a particular range of LAs and translating the LA to a physical location in memory using an offset corresponding to a number of physical locations skipped when writing data associated with a range of LAs other than the particular range.

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Номер записи: 77
06-09-2012 дата публикации

Method, apparatus, and system for speculative execution event counter checkpointing and restoring

Номер: US20120227045A1
Автор: Konrad K. Lai, Laura A. Knauth, Martin G. Dixon, Peggy J. Irelan, Ravi Rajwar
Принадлежит: Intel Corp

An apparatus, method, and system are described herein for providing programmable control of performance/event counters. An event counter is programmable to track different events, as well as to be checkpointed when speculative code regions are encountered. So when a speculative code region is aborted, the event counter is able to be restored to it pre-speculation value. Moreover, the difference between a cumulative event count of committed and uncommitted execution and the committed execution, represents an event count/contribution for uncommitted execution. From information on the uncommitted execution, hardware/software may be tuned to enhance future execution to avoid wasted execution cycles.

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Номер записи: 78
13-09-2012 дата публикации

Host device suspending communication link to client device based on client device notification

Номер: US20120233361A1
Автор: Anand Dalal, Haining Zhang, Mitchell D. Adler
Принадлежит: Apple Inc

A communication link between a host device and a client device can be suspended based on a suspend request or notification provided by the client device. The suspend request can be transmitted by a client device to a host device if the client device determines that suspension is appropriate, and can be sent in response to receiving a polling request from the host device. After receiving a suspend request, the host device can initiate an operation to suspend the communication link between the devices.

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Номер записи: 79
20-09-2012 дата публикации

Hybrid system architecture for random access memory

Номер: US20120239856A1
Автор: Byungcheol Cho
Принадлежит: Taejin Infotech Co Ltd

Embodiments of the present invention provide a hybrid system architecture random access memory (RAM) such as Phase-Change RAM (PRAM), Magnetoresistive RAM (MRAM) and/or Ferroelectric RAM (FRAM). Specifically, embodiments of this invention provide a hybrid RAID controller coupled to a system control board. Coupled to the hybrid RAID controller are a DDR RAID controller, a RAM RAID controller, and a HDD/Flash RAID controller. A DDR RAID control block is coupled to the DDR RAID controller and includes (among other things) a set of DDR memory disks. Further, a RAM control block is coupled to the RAM RAID controller and includes a set of RAM SSDs. Still yet, a HDD RAID control block is coupled to the HDD/Flash RAID controller and includes a set of HDD/Flash SSD Units.

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Номер записи: 80
20-09-2012 дата публикации

Synchronous data processing system and method

Номер: US20120239961A1
Автор: PRABHJOT Singh, Prakash Makwana
Принадлежит: FREESCALE SEMICONDUCTOR INC

A synchronous data processing system includes a memory module to store data and a memory controller coupled to the memory module. The memory controller includes a clock inverter to receive an input clock signal and to transmit an inverted clock signal to the memory module. The inverted clock signal incurs a first propagation delay prior to reaching the memory module as a memory clock signal. A write data buffer is coupled to the memory module. The write data buffer transmits data to the memory module in response to the input clock signal. An asynchronous first-in-first-out (ASYNC FIFO) buffer is coupled to the memory module. The ASYNC FIFO buffer reads data from the memory module in response to a feedback signal generated by feeding back the memory clock signal to the ASYNC FIFO buffer.

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Номер записи: 81
27-09-2012 дата публикации

Signal receiving circuit, memory controller, processor, computer, and phase control method

Номер: US20120242385A1
Автор: Noriyuki Tokuhiro
Принадлежит: Fujitsu Ltd

A signal receiving circuit includes a phase detection unit and a delay control unit. The phase detection unit detects a phase difference between a received signal and a clock signal. The delay control unit receives the phase difference, delays a phase of the received signal in a range not exceeding a delay amount determined by using a predetermined phase difference as a unit, and changes, when the phase difference exceeds the predetermined phase difference, a delay amount of the received signal by using the predetermined phase difference as a unit.

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Номер записи: 82
27-09-2012 дата публикации

HID over Simple Peripheral Buses

Номер: US20120246377A1
Автор: Arvind R. AIYAR, David Abzarian, Firdosh K. Bhesania, Randall E. Aull
Принадлежит: Individual

In embodiments of HID over simple peripheral buses, a peripheral sensor receives inputs from a peripheral device, and the peripheral sensor implements an HID SPB interface to interface the peripheral device with a computing system via a simple peripheral bus (SPB) in an HID data format. The peripheral sensor can also receive extensibility data for a proprietary function of the peripheral device, and communicate the inputs from the peripheral device and the extensibility data via the simple peripheral bus in the computing system. Alternatively or in addition, a peripheral sensor can generate sensor data and the HID SPB interface interfaces the peripheral sensor with the computing system via the simple peripheral bus. The peripheral sensor can then communicate the sensor data as well as extensibility data for a proprietary function of the peripheral sensor via the simple peripheral bus in the HID data format to the computing system.

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Номер записи: 83
27-09-2012 дата публикации

Memory system with interleaved addressing method

Номер: US20120246395A1
Автор: Eun Chu Oh, Hong Rak Son, Kyoung Lae Cho
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Disclosed is a memory system which includes a nonvolatile memory device including a memory cell array having a plurality of word lines including a first set of word lines storing first data having a high bit error rate, and a second set of word lines storing second data having low bit error rate less than the high bit error rate, and a memory controller that during a program operation maps logical addresses for a portion of the first data and a portion of the second data onto a selected word line selected from the plurality of word lines.

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Номер записи: 84
27-09-2012 дата публикации

Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines

Номер: US20120246450A1
Автор: Mohammad Abdallah
Принадлежит: Soft Machines Inc

A system for executing instructions using a plurality of register file segments for a processor. The system includes a global front end scheduler for receiving an incoming instruction sequence, wherein the global front end scheduler partitions the incoming instruction sequence into a plurality of code blocks of instructions and generates a plurality of inheritance vectors describing interdependencies between instructions of the code blocks. The system further includes a plurality of virtual cores of the processor coupled to receive code blocks allocated by the global front end scheduler, wherein each virtual core comprises a respective subset of resources of a plurality of partitionable engines, wherein the code blocks are executed by using the partitionable engines in accordance with a virtual core mode and in accordance with the respective inheritance vectors. A plurality register file segments are coupled to the partitionable engines for providing data storage.

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Номер записи: 85
04-10-2012 дата публикации

Circuit providing load isolation and noise reduction

Номер: US20120250386A1
Автор: Chi-She Chen, Hyun Lee, Jayesh R. Bhakta, Jeffrey C. Solomon, Mario Jesus Martinez
Принадлежит: Netlist Inc

Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports.

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Номер записи: 86
11-10-2012 дата публикации

Electronic device with card interface

Номер: US20120260001A1
Автор: Akihisa Fujimoto, Hiroyuki Sakamoto, Kosei Okamoto, Masao Suga
Принадлежит: Toshiba Corp

When initializing a card-shaped device inserted in a card interface, operation mode acquiring means incorporated in an electronic device acquires operation mode information, stored in a register file incorporated in the card-shaped device, by a predetermined procedure using a predetermined pin. Operation mode setting means incorporated in the electronic device executes signal assignment on a plurality of data pins peculiar to an operation mode indicated by the acquired operation mode information, thereby switching a data transfer width, and allowing the card-shaped device to operate in the operation mode.

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Номер записи: 87
11-10-2012 дата публикации

Memory buffer for buffer-on-board applications

Номер: US20120260137A1
Автор: Stuart Allen Berke
Принадлежит: Dell Products LP

Disclosed in a method of optimizing a voltage reference signal. The method includes: assigning a first value to the voltage reference signal; executing a test pattern while using the voltage reference signal having the first value; observing whether a failure occurs in response to the executing and thereafter recording a pass/fail result; incrementing the voltage reference signal by a second value; repeating the executing, the observing, and the incrementing a plurality of times until the voltage reference signal exceeds a third value; and determining an optimized value for the voltage reference signal based on the pass/fail results obtained through the repeating the executing, the observing, and the incrementing the plurality of times.

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Номер записи: 88
18-10-2012 дата публикации

Microcomputer, system including the same, and data transfer device

Номер: US20120263429A1
Автор: Hideo Inoue, Yuji Shimoyama
Принадлежит: Renesas Electronics Corp

A microcomputer is provided, which can load data of different areas in parallel and transfer the loaded data to a storage circuit. The microcomputer includes a CPU to control a DRIs each of which loads image data of a prescribed area out of image data inputted from a camera and transfers the image data to a memory blocks, and the DRIs each of which transfers image data of respectively different area out of the image data inputted from the camera to the memory blocks. Therefore, it becomes possible to load image data of different areas in parallel and to transfer the loaded image data to the memory blocks.

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Номер записи: 89
01-11-2012 дата публикации

Reconfigurable memory module and method

Номер: US20120278524A1
Автор: Joseph M. Jeddeloh, Terry R. Lee
Принадлежит: Round Rock Research LLC

A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes.

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Номер записи: 90
08-11-2012 дата публикации

Zone group manager virtual phy

Номер: US20120284435A1
Автор: Balaji Natrajan, Michael G. Myrah, Sohail Hameed
Принадлежит: Hewlett Packard Development Co LP

A switch is provided. The switch includes an expander configured to couple a server to a set of storage drive bays. The switch also includes a zone manager coupled to the expander and configured to maintain a zoning configuration corresponding to the set of storage drive bays. The zone manager is coupled to the expander through a virtual PHY.

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Номер записи: 91
08-11-2012 дата публикации

Memory system and bad block management method

Номер: US20120284469A1
Автор: Dong-young Seo
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Disclosed is a bad block management method of a memory system that includes virtual blocks having a plurality of units and at least one reserved block. The bad block management method includes mapping the virtual blocks and the at least one reserved block onto one physical block in the plurality of physical blocks, determining that a first virtual block in the virtual blocks includes a bad virtual block unit, and replacing the bad virtual block unit in the first virtual block with a first reserved block unit selected from the reserved block units.

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Номер записи: 92
15-11-2012 дата публикации

Managing Bandwidth Allocation in a Processing Node Using Distributed Arbitration

Номер: US20120290756A1
Автор: Abhijeet Ashok Chachad, David Quintin Bell, Dheera Balasubramanian, Raguram Damodaran, Roger Kyle Castille
Принадлежит: Texas Instruments Inc

Management of access to shared resources within a system comprising a plurality of requesters and a plurality of target resources is provided. A separate arbitration point is associated with each target resource. An access priority value is assigned to each requester. An arbitration contest is performed for access to a first target resource by requests from two or more of the requesters using a first arbitration point associated with the first target resource to determine a winning requester. The request from the winning requester is forwarded to a second target resource. A second arbitration contest is performed for access to the second target resource by the forwarded request from the winning requester and requests from one or more of the plurality of requesters using a second arbitration point associated with the second target resource.

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Номер записи: 93
15-11-2012 дата публикации

System and method for maintaining cache coherency across a serial interface bus using a snoop request and complete message

Номер: US20120290796A1
Автор: Brian Keith Langendorf, David B. Glasco, Jonah M. Alben, Michael Brian Cox
Принадлежит: Individual

Techniques are disclosed for maintaining cache coherency across a serial interface bus such as a Peripheral Component Interconnect Express (PCIe) bus. The techniques include generating a snoop request (SNP) to determine whether first data stored in a local memory is coherent relative to second data stored in a data cache, the snoop request including destination information that identifies the data cache on the serial interface bus and causing the snoop request to be transmitted over the serial interface bus to a second processor. The techniques further include extracting a cache line address from the snoop request, determining whether the second data is coherent, generating a complete message (CPL) indicating that the first data is coherent with the second data, and causing the complete message to be transmitted over the bus to the first processor. The snoop request and complete messages may be vendor defined messages.

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Номер записи: 94
15-11-2012 дата публикации

Communication between internal and external processors

Номер: US20120290814A1
Автор: Robert Walker
Принадлежит: Micron Technology Inc

Systems, methods of operating a memory device, and methods of arbitrating access to a memory array in a memory device having an internal processor are provided. In one or more embodiments, conflicts in accessing the memory array are reduced by interfacing an external processor, such as a memory controller, with the internal processor, which could be an embedded ALU, through a control interface. The external processor can control access to the memory array, and the internal processor can send signals to the external processor to request access to the memory array. The signals may also request a particular bank in the memory array. In different embodiments, the external processor and the internal processor communicate via the control interface or a standard memory interface to grant access to the memory array, or to a particular bank in the memory array, for example.

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Номер записи: 95
29-11-2012 дата публикации

Heat management in an above motherboard interposer with peripheral circuits

Номер: US20120300392A1
Автор: Frederick G. Weiss, Morgan Johnson
Принадлежит: Morgan Johnson, Weiss Frederick G

A computing device has a circuit substrate having a socket, a main processor inserted into the socket, an interposer substrate inserted between the socket and the main processor, the circuit substrate, the socket and the interposer substrate being electrically connected, at least one peripheral circuit on the interposer substrate, and a heat sink thermally coupled to the peripheral circuit.

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Номер записи: 96
29-11-2012 дата публикации

Memory system and refresh control method thereof

Номер: US20120300569A1
Автор: Geun Hee Cho
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A memory system and a refresh control method thereof are provided. The memory system includes a semiconductor memory device including a plurality of memory cells and a memory controller configured to generate a special command for searching for refresh information stored in the semiconductor memory device and to control a refresh operation of the semiconductor memory device. The semiconductor memory device is configured to output the refresh information to the memory controller in response to the special command generated by the memory controller.

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Номер записи: 97
29-11-2012 дата публикации

Computational fluid dynamics modeling of a bounded domain

Номер: US20120303339A1
Автор: Ethan E. Cruz
Принадлежит: International Business Machines Corp

A method for hybrid computational fluid dynamics (CFD) approach for modeling a bounded domain, such as a data center, is disclosed. The CFD modeling approach divides the bounded domain into one or more viscous regions and one or more inviscid regions, and then performs a viscous domain solve for the viscous region(s) using a computational fluid dynamics model with turbulence equations (i.e., a turbulence model), and performs inviscid domain solve for the inviscid region(s) using a set of inviscid equations (or potential flow equations). After solving for the different regions, results of the viscous domain solve and the inviscid domain solve are provided as a model of the bounded domain.

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Номер записи: 98
29-11-2012 дата публикации

Transmission control device, memory control device, and plc including the transmission control device

Номер: US20120303915A1
Автор: Eitarou Hioki
Принадлежит: Mitsubishi Electric Corp

A transmission control device in the present invention includes: a data storage memory in which data are written; a plurality of data copy memories into which the data written in the data storage memory are copied; an unread copy-memory selection unit that selects one of the data copy memories for which reading of data is not performed from among the data copy memories; a memory copy unit that copies the data written in the data storage memory into a data copy memory selected by the unread copy-memory selection unit; a read copy-memory selection unit that selects a data copy memory into which the memory copy unit copies data from among the data copy memories; and a data output unit that reads data from a data copy memory selected by the read copy-memory selection unit and outputs the read data to a transmission unit.

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Номер записи: 99
13-12-2012 дата публикации

Asynchronous/synchronous interface

Номер: US20120314517A1
Автор: Chih Liang Chen, Dean K. Nobunaga, June Lee
Принадлежит: Micron Technology Inc

The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.

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Номер записи: 100