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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 71660. Отображено 100.
05-01-2012 дата публикации

Communication circuit of inter-integrated circuit device

Номер: US20120005385A1
Автор: Ming-Yuan Hsu
Принадлежит: Hon Hai Precision Industry Co Ltd

A communication circuit of an Inter-Integrated Circuit (I2C) includes a master device, a switch circuit, first and second groups of slave devices. Each slave device includes a data signal pin and a clock signal pin, which are connected to the switch circuit. The master device includes a data signal pin, a clock signal pin, and a general purpose input output (GPIO) pin, which are connected to the switch circuit. The GPIO pin of the master device outputs a control signal to the switch circuit, to allow communication between the first group of slave devices and the master device or communication between the second group of slave devices and the master device.

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Номер записи: 1
21-03-2022 дата публикации

Устройство коммуникационное для кластерной цифровой подстанции

Номер: RU0000209720U1
Автор: Андрей Александрович Кузьмин, Андрей Владиславович Климов, Илья Викторович Лукьянов, Сергей Александрович Перегудов
Принадлежит: Акционерное общество "Русатом Автоматизированные Системы Управления" (АО "РАСУ")

Полезная модель относится к области кластерных цифровых электрических подстанций (ЦПС).Техническим результатом является обеспечение подключения устройства кластерной ЦПС к независимым сегментам станционной и технологической шин коммуникационной сети (Ethernet) ЦПС, в каждом из которых дополнительно обеспечивается коммуникационное резервирование с применением «бесшовного» резервирования в соответствии с IEC 62432-3, в частности резервирования по протоколу PRP ("Parallel Redundancy Protocol"). Устройство коммуникационное (1) включает в себя четыре интерфейса (2-5) подключения к внешней коммуникационной сети Ethernet ЦПС, процессор (8); коммутатор (9), связанный с процессором (8), включающий в себя также, по меньшей мере, один внешний коммуникационный порт (12) для связи с соответствующим интеллектуальным электронным устройством (IED) (13) кластерной ЦПС. Устройство (1) дополнительно содержит два коммуникационных шлюза (10 и 11), связанных с процессором (8). При этом первый коммуникационный шлюз (10) также связан с первым (2) и вторым (3) интерфейсами подключения к внешней коммуникационной сети Ethernet ЦПС (6, 7), а второй коммуникационный шлюз (11) также связан с третьим (4) и четвертым (5) интерфейсами подключения к внешней коммуникационной сети Ethernet ЦПС (6, 7). При этом интерфейсы (2) и (3) устройства (1) предназначены для подключения к резервированному по протоколу PRP (IEC 62439-3) сегменту (6.1 - подсеть "A" (PRP), 7.1 - подсеть "В" (PRP)) станционной шины коммуникационной сети ЦПС, а интерфейсы (4) и (5) - к резервированному по протоколу PRP (IEC 62439-3) сегменту (6.2 - подсеть "A" (PRP), 7.2 - подсеть "В" (PRP)) технологической шины коммуникационной сети ЦПС. При этом первый коммуникационный шлюз (10) выполнен с возможностью обеспечения коммуникационного сопряжения с резервированным сегментом станционной шины (6.1, 7.1) внешней коммуникационной сети ЦПС с обеспечением двусторонней передачи данных в прямом и обратном ...

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Номер записи: 2
12-01-2012 дата публикации

Low power, low pin count interface for an rfid transponder

Номер: US20120007720A1
Автор: Mark R. Whitaker
Принадлежит: Ramtron International Corp

A serial interface includes a select node, a clock node, a first bidirectional data port, a second bidirectional data port, and shift register circuitry coupled to both data ports such that a leading edge and a falling edge of a clock signal associated with the clock node are used to shift or transfer data.

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Номер записи: 3
19-01-2012 дата публикации

Portable Storage Device With Retractable Connector

Номер: US20120015534A1
Автор: Jose Luis Pluchino, Robert Edward Wavra
Принадлежит: Individual

A thumb drive includes a retractable USB connector sized to translate between an extended position beyond a housing and a retracted position into the housing. An actuator, such as a dial or a lever, is sized to actuate the USB connector to move the USB connector between the extended position and the retracted position. The USB connector is sized to translate to the extended position when the actuator is moved in one direction. The USB connector is sized to translate to the retracted position when the actuator is moved in an opposite direction.

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Номер записи: 4
19-01-2012 дата публикации

Data transfer circuit and data transfer method

Номер: US20120017017A1
Автор: Masaru Nishiyashiki
Принадлежит: Fujitsu Ltd

A port A request queue is configured with a port AQ 0 to a port AQn for each of request types Q 0 to Qn connected with a requester resource busy flag controller Q 0 to a requester resource busy flag controller Qn, respectively. A port A resource checking unit of a port X arbiter unit gives instructions to the requester resource busy flag controller of the port AQ 0 to turn a busy flag on when it is determined that a data request from the port AQ 0 has difficulty in being output to a port X inter-port arbiter unit due to resources being busy as a result of referring to a resource information unit of a port X resource managing unit. The port AQ 0 inhibits output of a data request as long as the busy flag is on.

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Номер записи: 5
19-01-2012 дата публикации

Isolation-free in-circuit programming system

Номер: US20120017051A1
Автор: Chong-Yung Tsao
Принадлежит: Dediprog Technology Co Ltd

Disclosed is an isolation-free in-circuit programming system including an in-circuit programmer and an application board connected to the in-circuit programmer through a peripheral interface bus and having a bus controller and a memory, wherein the bus controller is connected to the memory through a system bus, in which the in-circuit programmer includes a leakage current discharging circuit connected to the bus controller for detouring a leakage current flowing from the memory or the in-circuit programmer to the bus controller to flow therethrough. The in-circuit programmer also includes an input level shifter for receiving data signals from the memory and adjusting the high-level input voltage of the in-circuit programmer to decode any weak high-level output voltage from the memory, thereby allowing the high-level output voltage of the memory to be higher than the high-level input voltage of the in-circuit programmer.

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Номер записи: 6
02-02-2012 дата публикации

Information handling system remote input/output connection system

Номер: US20120030455A1
Автор: Douglas Evan Messick, Jason Alan Shepherd, Robyn Reed McLaughlin
Принадлежит: Dell Products LP

An information handling system (IHS) remote input/output (I/O) connection system includes an enclosure having a power button, a communication bus connection point, and an audio connection point. A cable dongle extends from the enclosure. The cable dongle has a first end and a second end. The cable dongle also includes a connection from the power button on the enclosure on the first end to a communication connection point plug on the second end, which mates with a connection point plug on a remote I/O device card that enables a parallel (ACPI) S5-capable power button from the IHS to exist on the enclosure. The cable dongle further includes a communication cable coupled to the communication bus connection point on the first end and having a communication connection point plug on the second end. In addition, the cable dongle includes an audio cable coupled to the audio connection point on the first end and having an audio connection point plug on the second end.

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Номер записи: 7
09-02-2012 дата публикации

Optical memory expansion

Номер: US20120033978A1
Автор: Michael Renne Ty Tan, Terrel Morris
Принадлежит: Hewlett Packard Development Co LP

Various embodiments of the present invention are directed to optical-based methods and expansion memory systems for disaggregating memory of computer systems. In one aspect, an expansion memory system comprises a first optical/electronic interface in electrical communication with a processor, a memory expansion board configured with memory, and a second optical/electronic interface attached to the memory expansion board. The first interface converts optical signals into electronic signals that are sent to the processor and converts electronic signals produced by the processor into optical signals. The second interface converts optical signals into electronic signals that are sent to the memory and converts electronic signals produced by the memory into optical signals. The optical signals are exchanged between the first and second interfaces. Embodiments also include methods for sending and receiving data in an expansion memory system.

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Номер записи: 8
16-02-2012 дата публикации

Adjustable finite impulse response transmitter

Номер: US20120042104A1
Автор: Charles Wang, Karen Tucker
Принадлежит: Advanced Micro Devices Inc

Apparatus and methods are provided for generating output signals representative of bits of serial data. A transmitter comprises a plurality of delay elements, driver circuitry, and bypass logic coupled between the plurality of delay elements and the driver circuitry. The plurality of delay elements delay serialized data, resulting in delayed serialized data, and the driver circuitry generates an output signal representative of a first bit of the delayed serialized data. The bypass logic is configured to selectively bypass one or more delay elements of the plurality of delay elements to provide the first bit of the delayed serialized data to the driver circuitry.

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Номер записи: 9
23-02-2012 дата публикации

Card type peripheral apparatus and host apparatus

Номер: US20120047290A1
Автор: Junko Nagata, Kenichi Nakanishi, Kenichi Satori, Naohiro Adachi, Noriyuki Hosoe, Tamaki Konno
Принадлежит: Sony Corp

A card type peripheral apparatus connected to a host apparatus for communication therewith according to a specific protocol. The card type peripheral apparatus includes a plurality of configuration registers configured to be accessible by the host apparatus and to be set with diverse set information. At least one of the plurality of configuration registers is a special register configured to be set with data arbitrarily selected and fixedly established by a vendor that either fabricates or markets the card type peripheral apparatus. The special register is set with protocol identification information for discriminating the specific protocol.

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Номер записи: 10
01-03-2012 дата публикации

Method for finding starting bit of reference frames for an alternating-parity reference channel

Номер: US20120054388A1
Автор: Howard RIDEOUT
Принадлежит: Avalon Microelectronics Inc

The present invention discloses a method for locating the reference frames of the reference lane on the transmitting data bus. The present invention addresses this object by disclosing a method whereby the relationship between the size of the reference frame transmitted over the reference lane and the width of the data bus is such that the reference frame is bit-shifted automatically until it is aligned with the data bus.

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Номер записи: 11
08-03-2012 дата публикации

Method for Assigning Addresses to Nodes of a Bus System, and Installation

Номер: US20120059959A1
Автор: Olaf Simon
Принадлежит: SEW Eurodrive GmbH and Co KG

A method for assigning addresses to nodes of a bus system, and installation, bus nodes being furnished with an identical delivery address, where (i) an assigning entity, particularly a central computer, start-up computer or bus node sends information to the delivery address via the bus system, (ii) the information includes a first address, (iii) an action is performed whose effect is detected by a first bus node, (iv) the first bus node accepts the first address, (v) the first bus node sends a response to the assigning entity, (vi) steps (i) through (v) are repeated, each time with a further address for a further bus node.

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Номер записи: 12
08-03-2012 дата публикации

Precision synchronisation architecture for superspeed universal serial bus devices

Номер: US20120059965A1
Автор: Peter Graham Foster
Принадлежит: CHRONOLOGIC PTY LTD

A method of providing a synchronisation channel to a SuperSpeed USB device is provided. The method including a SuperSpeed communication channel connection to the SuperSpeed USB device with a USB cable that has USB 2.0 D+ and D− data signalling lines disabled or disconnected at an upstream connection point; multiplexing synchronization information onto the D+/D− data signalling lines at the upstream connection point; and demultiplexing the synchronization information from the D+/D− signalling lines at a downstream connection point of the cable; whereby the synchronisation channel is maintained across the D+/D− data signalling lines.

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Номер записи: 13
08-03-2012 дата публикации

Non-invasive direct-mapping usb switching device

Номер: US20120059969A1
Автор: Cheng-Sheng Chou, Chien-Fa Lin
Принадлежит: June On Technology Co Ltd

A non-invasive direct-mapping USB switching device includes a main-controlled microprocessing module connected to a high-impedance module, and the high-impedance module is provided for detecting and monitoring a functional instruction code of a USB device transmitted from a data transmission module, such that a USB connecting module can be used for transmitting the USB data and functional instruction code to detect and monitor the data transmission module when the USB device is connected to the USB switching device. If the data transmitted from the data transmission module is not the required functional code, the non-required functional code (such as the USB data) will be passed, so that the USB device can be connected and communicated with a plurality of computer devices through another USB connecting module and a switching module to achieve a plug-and-play function.

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Номер записи: 14
15-03-2012 дата публикации

Synchronous network of superspeed and non-superspeed usb devices

Номер: US20120066418A1
Автор: Peter Graham Foster
Принадлежит: CHRONOLOGIC PTY LTD

A method of synchronising the operation of a plurality of SuperSpeed USB devices and a plurality of non-SuperSpeed USB devices is provided. The method includes establishing a SuperSpeed synchronisation channel for each of the plurality of SuperSpeed USB devices; establishing a non-SuperSpeed synchronisation channel for each of the plurality of non-SuperSpeed USB devices; synchronising a respective local clock of each of the plurality of SuperSpeed USB devices; synchronising a respective local clock of each of the plurality of non-SuperSpeed USB devices; and synchronising the SuperSpeed and non-SuperSpeed synchronisation channels so that the SuperSpeed and non-SuperSpeed devices can operate in synchrony.

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Номер записи: 15
15-03-2012 дата публикации

Method and system for transferring high-speed data within a portable device

Номер: US20120066422A1
Автор: Morgan Monks
Принадлежит: Standard Microsystems LLC

A system for high-speed data transfer within a portable device, such as, cell phone or a set-top box, which includes a memory medium and a processor. The system includes a first port for coupling to the processor, and a second port for coupling to the memory medium. Further, the system includes an embedded Universal Serial Bus (USB) host configured for receiving data transfer commands from the processor, and transferring data at high speed between a USB device on the processor and the memory medium. Moreover, a data path is provided between the embedded USB host and the first port.

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Номер записи: 16
15-03-2012 дата публикации

Inter-integrated circuit bus multicasting

Номер: US20120066423A1
Автор: Boon Siang Choo, Chee How Lee, Tzye Perng POH
Принадлежит: Hewlett Packard Development Co LP

A master node selects a plurality of slave nodes that share a common slave address to receive a data communication. The master node multicasts the data communication to the plurality of selected slave nodes via an inter-integrated circuit bus having a serial data line and a serial clock line.

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Номер записи: 17
15-03-2012 дата публикации

Multi-device docking with a displayport compatible cable

Номер: US20120066425A1
Автор: Henry Zeng, Ji Park
Принадлежит: Integrated Device Technology Inc

A docking system utilizing a single DisplayPort cable connection to a computer system is provided. In one embodiment, the docking system includes a single DisplayPort (“DP”) input, a management layer module coupled to receive video inputs from the single DP input and to provide video data to at least one video monitor output, and a USB layer module coupled to receive an AUX channel from the single DP input and to couple the AUX channel with a USB hub.

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Номер записи: 18
15-03-2012 дата публикации

Use of pci express for cpu-to-cpu communication

Номер: US20120066430A1
Автор: Braden Michael Cooper, Stephen Dale Cooper
Принадлежит: Individual

CPUs that generate PCIe auxiliary signals and changing clock signals nevertheless communicate with each other using PCIe owing to PCIe switch assemblies that are disposed in the communication paths to isolate and terminate the auxiliary signals from reaching other CPUs and to isolate changing clock signals, communicating with each other using a fixed clock derived from one of the changing clock signals. Also, the CPUs directly access the memories of CPUs to which they wish to write data so that data is directly written from one CPU memory to another without store-and-forward operations being needed in the network.

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Номер записи: 19
15-03-2012 дата публикации

Compound universal serial bus architecture providing precision synchronisation to an external timebase

Номер: US20120066537A1
Автор: Peter Graham Foster
Принадлежит: CHRONOLOGIC PTY LTD

A method of synchronising a compound Super Speed USB device, comprising: providing data communication between a host computing device and the compound Super Speed USB device across the Super Speed USB communication channel; establishing a Super Speed USB communication channel to a Super Speed USB function of the compound USB device; establishing a non-Super Speed synchronisation channel to a non-Super Speed USB function of the compound USB device; and synchronising a local clock of the compound USB device to a periodic data structure within a data stream in the non-Super Speed synchronisation channel so that the local clock can enable synchronous operation of the compound USB device with one or more comparable USB devices.

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Номер записи: 20
22-03-2012 дата публикации

Semiconductor integrated circuit

Номер: US20120068539A1
Автор: Masayoshi SHIOTANI
Принадлежит: Panasonic Corp

A constantly power-ON domain and a standby-time power OFF domain are included on the same chip, and the constantly power-ON domain includes: a shutoff control circuit shutting off a signal inputted and outputted between the constantly power-ON domain and the standby-time power OFF domain when the first power source is ON and the second power source is OFF; and a shutoff control circuit outputting a first control signal indicating that shutoff of an emergent shutoff control circuit unit is to be enabled or disabled, the standby-time power OFF domain includes the emergent shutoff control circuit unit shutting off, based on the first control signal from the shutoff control circuit, the signal inputted between the emergent shutoff control circuit unit and the constantly power-ON domain.

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Номер записи: 21
22-03-2012 дата публикации

Implementing lane shuffle for fault-tolerant communication links

Номер: US20120069729A1
Автор: Ibrahim Abdel-Rahman Ouda, John David Irish, Kerry Christopher Imming, Ryan Abel Heckendorf
Принадлежит: International Business Machines Corp

A method and circuit for implementing lane shuffle for fault-tolerant communication links, and a design structure on which the subject circuit resides are provided. Shuffle hardware logic steers a set of virtual data lanes onto a set of physical optical lanes, steering around all lanes that are detected as bad during link initialization training. A mask status register is loaded with a mask of lane fail information during link training, which flags the bad lanes, if any. The shuffle hardware logic uses a shift template, where each position in the starting template is a value representing the corresponding lane position. The shift template is cascaded through a set of shifters controlled by the fail mask.

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Номер записи: 22
29-03-2012 дата публикации

Root hub virtual transaction translator

Номер: US20120079145A1
Автор: Alejandro Lenero Beracoechea, Jennifer C. Wang, Nai-chih Chang
Принадлежит: Intel Corp

Systems and methods of operating root hub host controllers provide for determining, at a protocol engine having a dedicated port, a speed of a device in response to a coupling of the device to the dedicated port. Data transfer can occur at a second speed between software interface logic of the host controller and the protocol engine, and at the first speed between the protocol engine and the device via the dedicated port, wherein the second speed is greater than the first speed. In addition, data may be transferred in unicast transactions in which no split tokens are exchanged.

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Номер записи: 23
29-03-2012 дата публикации

Transaction reordering arrangement

Номер: US20120079154A1
Автор: Daniele Mangano, Ignazio Antonino Urzi
Принадлежит: STMicroelectronics Grenoble 2 SAS, STMICROELECTRONICS SRL

An embodiment of a transaction reordering arrangement is provided. The transaction reordering arrangement includes a queue into which respective responses to requests are writable and a controller configured to control a position in said queue to which said respective responses to said requests are written. The position is controlled such that the responses are read out of said queue in an order which corresponds to an order in which the requests are issued.

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Номер записи: 24
12-04-2012 дата публикации

Method of adjusting transfer speed after initialization of SATA interface

Номер: US20120089755A1
Автор: Hsieh-Huan Yen, Huei-Chiang Shiu, Teng-Chuan Hsieh
Принадлежит: Individual

In a method of adjusting transfer speed after initialization of a SATA interface, a SATA link device transmits a first predetermined primitive to a SATA link partner for requesting to change a first transfer speed of the SATA link device from a first speed to a second speed, the SATA link partner replies to the SATA link device with a second predetermined primitive according to the first predetermined primitive, and the SATA link device and the SATA link partner respectively adjust the first transfer speed of the SATA link device and a second transfer speed of the SATA link partner according to the second predetermined primitive.

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Номер записи: 25
19-04-2012 дата публикации

Cooperative Writes over the Address Channel of a Bus

Номер: US20120096201A1
Автор: Richard Gerard Hofmann, Terence J. Lohman
Принадлежит: Qualcomm Inc

A method of communicating over a bus is disclosed. The bus includes a write address channel, a write channel, and a read address channel. The method includes sending an address from a sending device to a receiving device via the write address channel. The method further includes concurrently sending a portion of a payload to the receiving device via the write channel and another portion of the payload to the receiving device via the read address channel. When sending multiple sequential portions of the payload via the bus concurrently, the sending device is configured to give data ordering preference to the write channel over the read address channel by sending a first sequential portion of the multiple sequential portions via the write channel and sending a subsequent sequential portion of the multiple sequential portions via the read address channel.

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Номер записи: 26
26-04-2012 дата публикации

Allocation of an Operating Address to a Bus-Compatible Operating Device for Luminous Means

Номер: US20120102235A1
Автор: Andre Mitterbacher, Markus Kuenzli, Patrick Zueger, Reinhard Boeckle, Reto Sprenger, Roger Kistler
Принадлежит: Tridonic GmbH and Co KG

The invention relates to a method for allocating an operating address to an operating device for luminous means, in which the operating address is transmitted to the operating device in digitally coded form via an interface which is configured to connect a light sensor. The operating address is allocated by a user using a handheld device to transmit optical digital signals to a light sensor or infrared sensor which is connected to the interface.

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Номер записи: 27
26-04-2012 дата публикации

Disabling outbound drivers for a last memory buffer on a memory channel

Номер: US20120102256A1
Автор: Dennis W. Brzezinski, Pete D. Vogt, Warren R. Morrow
Принадлежит: Individual

Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.

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Номер записи: 28
26-04-2012 дата публикации

Solid State Drive Architecture

Номер: US20120102263A1
Автор: Ajoy Aswadhati
Принадлежит: FASTOR SYSTEMS Inc

Embodiments of apparatuses, methods and systems of solid state drive are disclosed. One embodiment of a solid state drive includes a non-blocking fabric, wherein the non-blocking fabric comprises a plurality of ports, wherein a subset of the plurality of ports are each connected to a flash controller that is connected to at least one array of flash memory. Further, this embodiment includes a flash scheduler for scheduling data traffic through the non-blocking fabric, wherein the data traffic comprises a plurality of data packets, wherein the flash scheduler extracts flash fabric header information from each of the data packets and schedules the data traffic through the non-blocking fabric based on the extracted flash fabric header information. The scheduled data traffic provides transfer of data packets through the non-blocking fabric from at least one array of flash memory to at least one other array of flash memory.

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Номер записи: 29
26-04-2012 дата публикации

Virtual function boot in single-root and multi-root i/o virtualization environments

Номер: US20120102491A1
Автор: Parag R. Maharana
Принадлежит: LSI Corp

A method for virtual function boot in a system including a single-root I/O virtualization (SR-IOV) enabled server includes loading a PF driver of the PF of a storage adapter onto the server utilizing the virtual machine manager of the server; creating a plurality of virtual functions utilizing the PF driver, detecting each of the virtual functions on an interconnection bus, maintaining a boot list associated with the plurality of virtual functions, querying the storage adapter for the boot list utilizing a VMBIOS associated with the plurality of VMs, presenting the detected boot list to a VM boot manager of the VMM, and booting each of the plurality of virtual machines utilizing each of the virtual functions, wherein each VF of the plurality of VFs is assigned to a VM of the plurality of VMs via an interconnect passthrough between the VMM and the plurality of VMs.

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Номер записи: 30
03-05-2012 дата публикации

Medical Data Collection Apparatus

Номер: US20120110228A1
Автор: Anna McNamara, Charles Gropper, Erich Vlach
Принадлежит: Cardionet LLC

A physiological data collection device obtains physiological data from a subject interface on a subject. The physiological data collection device includes a data connector such as a USB connector for connecting directly to a computer. When the physiological data collection device is connected to the computer, the physiological data is uploaded to a remote data processing center for computer-based analysis and review by a medical professional. A report can be provided to the subject based on the analysis and review. When the subject interface is physically connected to the physiological data collection device, the data connector is prevented from being connected to an external device such as the computer.

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Номер записи: 31
10-05-2012 дата публикации

Usb connector device for an antenna

Номер: US20120112984A1
Автор: Cheng-Si Wang
Принадлежит: Trans Electric Co Ltd

A USB connector device for an antenna has a first cable, a receiver, a second cable and a USB connector. The first cable has an end connected to the receiver. The second cable has two ends respectively connected to the receiver and the USB connector. Because the receiver and the USB connector are combined in a series-connection way, the series-connection design can compact the structure of the USB connector device for an antenna in accordance with the present invention and reduce redundant cables, and it occupies a single one USB slot of the computer only. The USB connector device is very useful and convenient in use.

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Номер записи: 32
17-05-2012 дата публикации

Segmented transmission signal circuit

Номер: US20120119854A1
Автор: Chih-Chuan Huang
Принадлежит: Raydium Semiconductor Corp

A segmented transmission signal circuit is provided with a parallel bus of data transmission. The bus includes a plurality of sections, each section transmits a corresponding parallel data of multiple bits, and the parallel data corresponding to different sections are in different bit orders.

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Номер записи: 33
17-05-2012 дата публикации

Active business client

Номер: US20120124133A1
Автор: Joerg Beringer
Принадлежит: Individual

Methods and apparatuses enable generation of and consumption of business context data. A server generates business context data that describes a resource, a view, and actionable context data related to a business scenario. The business context data is not specific to any particular UI capability of the client device, and may include tittle or no UI information. The server transmits the business context data to a client device that has an active client. The active client identifies one or more UI capabilities of the client device and generates a UI component based on the business scenario and the UI capabilities. The UI component enables functionality in the client device related to execution of the actionable context data. In one embodiment, the active client enables predictive deployment of services on the client device based on an understanding of the business scenario.

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Номер записи: 34
17-05-2012 дата публикации

Conversion of a single-wire bus communication protocol

Номер: US20120124258A1
Автор: Francois Tailliet
Принадлежит: STMICROELECTRONICS ROUSSET SAS

A method of transmission-reception over a serial bus placed, when idle, in a first state at a first voltage, including: a transmit circuit capable of coding a transmission according to a first protocol in which the respective states of the bits are conditioned by time periods of fixed levels, indifferently in the first state or in a second state at a second voltage smaller than the first one; a receive circuit capable of interpreting a communication according to the first protocol; and a protocol converter, interposed between the bus and the transmit and receive circuits, to convert the signals to be transmitted to a second protocol in which the respective states of the bits are conditioned by respective time periods of fixed levels in the first state, and to convert the received signals from the second protocol to the first protocol.

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Номер записи: 35
17-05-2012 дата публикации

Hybrid storage device and electronic system using the same

Номер: US20120124266A1
Автор: Byung-Hoon Chung, Jae-won You, Kyu-yeol Park, Tae-yung Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A hybrid storage device is provided. The hybrid storage device includes a first storage part that comprises an interface device based on a first standard, a second storage part that comprises an interface device based on a second standard, and a connector for interface devices that is shared by the first storage part and the second storage part and comprises a plurality of pins.

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Номер записи: 36
17-05-2012 дата публикации

Serial i/o using jtag tck and tms signals

Номер: US20120124438A1
Автор: Lee D. Whetsel
Принадлежит: Texas Instruments Inc

The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus. According to the present disclosure, the TAP's TMS terminal is used as a clock signal and the TCK terminal is used as a bidirectional data signal to allow serial communication to occur between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC.

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Номер записи: 37
24-05-2012 дата публикации

Determining addresses of electrical components arranged in a daisy chain

Номер: US20120131231A1
Автор: Gerardo Monreal
Принадлежит: Allegro Microsystems LLC

In one aspect, a system includes electrical components arranged in a daisy chain that include a first electrical component disposed at a first end of the daisy chain and a second electrical component disposed at an opposite end of the daisy chain than the first end. Each of the first and second electrical components includes an input port, an output port and a common port. The input port of the first electrical component is coupled to one of a supply voltage port or ground and the common ports of the first and second electrical components are coupled to the other one of the supply voltage or the ground. An address of the second electrical component is determined before addresses of the other of the electrical components are determined, and the addresses determine a position of an electrical component with respect to the other of the electrical components.

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Номер записи: 38
24-05-2012 дата публикации

Configuring an input/output adapter

Номер: US20120131232A1
Автор: John R. Oberly, III, Sean T. Brownlow
Принадлежит: International Business Machines Corp

A computer-implemented method includes initializing a driver associated with an input/output adapter in response to receiving an initialize driver request from a client application. The input/output adapter may be initialized to enable adapter capabilities of the input/output adapter to be determined. The computer-implemented method also includes determining the adapter capabilities of the input/output adapter and determining slot capabilities of a slot associated with the input/output adapter. The computer-implemented method further includes setting configurable capabilities of the input/output adapter based on the adapter capabilities and the slot capabilities.

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Номер записи: 39
31-05-2012 дата публикации

Computer chassis system and hard disk status display method thereof

Номер: US20120133520A1
Автор: Chen-Pin Lee, Huang-Ching Wang, Po-Chung CHANG
Принадлежит: Inventec Corp

A computer system displays and controls the hard disk condition. The computer system includes a host bus adapter which detects the status of the hard disk, and the status light gives light to display the hard disk status. The baseboard management controller and the host bus adapters are set on the motherboards, in which the baseboard management controller monitors and records the status of the hard disk. The microcontroller is set on the hard disk backplane for decoding the message from the host bus adapter in order to control the displaying of the status light.

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Номер записи: 40
31-05-2012 дата публикации

Memory Modules and Devices Supporting Configurable Core Organizations

Номер: US20120134084A1
Автор: Craig E. Hampel, Donald C. Stark, Ely K. Tsern, Frederick A. Ware, Richard E. Perego
Принадлежит: RAMBUS INC

Described are memory apparatus organized in memory subsections and including configurable routing to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey width selection information to configurable memory apparatus and support point-to-point data interfaces for multiple width configurations.

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Номер записи: 41
31-05-2012 дата публикации

Communication system, master node, and slave node

Номер: US20120137034A1
Автор: Naoji Kaneko
Принадлежит: Denso Corp

In a node communicably coupled to alternative nodes through a bus, a transmitting unit receives first designation information from an alternative node. When the first designation information designates the node, the transmitting unit successively transmits, on the bus, the first designation information and data. When a request of an active communication occurs in the node, a request unit determines whether to receive a former part of the first identification information indicative of start timing of an active communication mode on the bus. When determining to receive the former part of the first identification information, the request unit transmits, on the bus, collision information at a timing that allows the collision information to collide with a latter part of the first identification information, resulting in rewrite of the first identification information based on bus arbitration, and transmits second designation information meeting the request of the active communication.

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Номер записи: 42
07-06-2012 дата публикации

Apparatuses, systems, and methods for facilitating optical communication between electronic devices

Номер: US20120141132A1
Автор: Richard C. Walker
Принадлежит: CORNING OPTICAL COMMUNICATIONS LLC

Active optical cable assemblies, and systems, methods, and adapter modules and integrated circuits for facilitating communication between a host and a client device over a fiber optic cable are disclosed. In one embodiment, an active optical cable assembly includes a fiber optic cable having at least one optical fiber, a host active circuit, a client active circuit, a host connector, and a client connector. Upon a connection between the host active circuit and a host device, the client termination switch closes to couple the client termination impedance to the ground reference potential. Upon a connection between the client active circuit and a client device, the host termination switch closes to the couple the host termination impedance to the ground reference potential. In another embodiment, a method includes enabling a host termination impedance upon a connection of an active optical cable to a client device.

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Номер записи: 43
07-06-2012 дата публикации

Baseboard management controller and method for sharing serial port

Номер: US20120144180A1
Автор: Chiang-Chung Tang
Принадлежит: Hon Hai Precision Industry Co Ltd

A baseboard management controller (BMC) connects with a COM serial port. The BMC includes an input queue and an output queue. If a basic input output system (BIOS) of the BMC has been initialized, the COM serial port is used by the BIOS. When a processor of the BMC sends a control command to a sharing system of the BMC, the input queue and the output queue are converted to time division multiplex (TDM) queues. The COM serial port may be used by the BIOS or by the BMC according to an ID flag of each element of the TDM queues.

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Номер записи: 44
14-06-2012 дата публикации

Method for operating flash memories on a bus

Номер: US20120151122A1
Автор: Ming-Hung Hsieh
Принадлежит: Individual

Enable a read command of a first flash memory. After the read command of the first flash memory is enabled, a ready/busy signal of the first flash memory enters a busy waiting time, and a read command of a second flash memory starts to be enabled. Start to read data of the first flash memory when the busy waiting time is over. Enable the read command of the first flash memory again upon completion of reading the data of the first flash memory. Start to read data of the second flash memory after the read command of the first flash memory is enabled again. And enable the read command of the second flash memory again upon completion of reading the data of the second flash.

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Номер записи: 45
14-06-2012 дата публикации

Power-Saving Device for Universal Serial Bus Modem Apparatus and Method Thereof

Номер: US20120151239A1
Автор: Wei Wang
Принадлежит: ZTE Corp

A power-saving apparatus for universal serial bus (USB) modem equipment is disclosed in the present invention, which includes: a personal computer and USB Modem equipment. Accordingly, a power-saving method for USB Modem equipment is provided in the present invention, which includes: regularly detecting whether selective suspending is allowed, if not allowed, processing a received request from an application program, and if allowed, transmitting an instruction for entering the selective suspending state to the USB Modem equipment; after receiving the instruction for entering the selective suspending state, the USB Modem equipment entering the selective suspending state. Thus, the present invention can realize that the USB Modem equipment enters the power-saving state in the idle period and resumes the work state when receiving a service request.

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Номер записи: 46
21-06-2012 дата публикации

Semiconductor device

Номер: US20120159020A1
Автор: Daijiro Harada, Takashi Utsumi
Принадлежит: Renesas Electronics Corp

There is a need to cause a delay to occur less frequently than the related art during processing of an input signal in need of relatively fast processing. In a semiconductor device, a conversion portion includes first channels and second channels and A/D converts a signal input to a selected channel. A signal input to the first channel requires faster processing than a signal input to the second channel. The conversion portion receives a scan conversion instruction from a central processing unit, sequentially selects the input channels in a specified selection order, and successively performs A/D conversion. In this case, the conversion portion notifies a peripheral circuit of completion of A/D conversion after completion of A/D conversion on signals input to the first channels and before completion of A/D conversion on input signals input to all input channels.

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Номер записи: 47
21-06-2012 дата публикации

Memory Module With Reduced Access Granularity

Номер: US20120159061A1
Автор: Craig E. Hampel, Frederick A. Ware
Принадлежит: RAMBUS INC

A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

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Номер записи: 48
21-06-2012 дата публикации

Ieee 1149.1 and p1500 test interfaces combined circuits and processes

Номер: US20120159275A1
Автор: Lee D. Whetsel
Принадлежит: Texas Instruments Inc

In a first embodiment a TAP of IEEE standard 1149.1 is allowed to commandeer control from a WSP of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface. One approach provides for the TAP to maintain access and control of the TAP instruction register, but provides for a selected data register to be accessed and controlled by either the TAP+ATC or by the discrete CaptureDR, UpdateDR, TransferDR, ShiftDR, and ClockDR WSP data register control signals.

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Номер записи: 49
28-06-2012 дата публикации

Multi-root sharing of single-root input/output virtualization

Номер: US20120166690A1
Автор: Jack Regula
Принадлежит: PLX Technology Inc

In a first embodiment of the present invention, a method for multi-root sharing of a plurality of single root input/output virtualization (SR-IOV) endpoints is provided, the method comprising: CSR redirection to a management processor which either acts as a proxy to execute the CSR request on behalf of the host or filters it and performs an alternate action, downstream routing of memory mapped I/O request packets through the switch in the host's address space and address translation with VF BAR granularity, upstream routing of requests originated by I/O devices by table lookup indexed by Requester ID, and requester ID translation using a fixed local-global RID offset.

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Номер записи: 50
28-06-2012 дата публикации

Communications architecture for providing data communication, synchronization and fault detection between isolated modules

Номер: US20120166695A1
Автор: Brian VENUS, Nicholas D. Benavides
Принадлежит: CONVERTEAM TECHNOLOGY LTD

An electronic system includes a master module having a first control unit having one or more first serial interfaces and being programmed to output a first data signal and a first clock signal through the one or more first serial interfaces, and a slave module having a second control unit, the second control unit having a second serial interface. The slave module receives the first clock signal through the second serial interface, and the second control unit is programmed to monitor the slave module for a fault condition and output a second clock signal through the second serial interface which is (i) the same as the first clock signal if a fault condition on the slave module is not detected, and (ii) a modified clock signal having a predetermined format through the second serial interface if a fault condition on the slave module is detected.

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Номер записи: 51
05-07-2012 дата публикации

Memory controller for strobe-based memory systems

Номер: US20120170389A1
Автор: Benedict Lau, Jade M. Kizer, Sivakumar Doraiswamy
Принадлежит: RAMBUS INC

A memory controller for strobe-based memory systems is disclosed. The memory controller comprises a circuit to generate a control signal having a predetermined timing relationship with respect to a first clock signal, a circuit to receive the control signal, and a receiver to sample the read data in response to the qualified read strobe signal. The receiving circuit comprises an input to receive an external read strobe signal transmitted by a semiconductor memory device, circuitry to synchronize the control signal and the received read strobe signal to have a common timing relationship with respect to each other, and circuitry to gate the read strobe signal based on the synchronized control signal.

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Номер записи: 52
12-07-2012 дата публикации

Protocol translation method and bridge device for switched telecommunication and computing platforms

Номер: US20120177035A1
Автор: Barton W. Stuck, Ching-Tai Hu, Viswa Nath Sharma, William Chu, Yi-chang Chou
Принадлежит: Psimast Inc

A computing and communication architecture utilizes a serial protocol based switched fabric among circuit cards housed in packaging arrangement. In one embodiment, each circuit card connected to the serial protocol based switched fabric in the packaging arrangement is provided with a protocol processor that enables all of the circuit cards to efficiently provide packet-based serial self-clocked communications at line speed. As a result, it is not necessary to arrange the circuit cards in a hierarchical manner in order to address the problems of switch blocking and related traffic congestion issues that would otherwise limit the implementation of the serial protocol based backplane arrangement for housing circuit cards.

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Номер записи: 53
12-07-2012 дата публикации

Electrical Circuit For Transmitting Signals Between Two Masters And One Or More Slaves

Номер: US20120179848A1
Автор: Volker Frese
Принадлежит: ROBERT BOSCH GMBH

An electrical circuit for transmitting signals between two masters and one or more slaves is described. The two masters and the slave or slaves are connected to one another via a bus system. At least one master data signal can be generated by each of the two masters, which signal can be received by the slave or slaves. A three-state gate is present at each of the outputs of the two masters at which the respective master data signal is present. The three-state gates are effective either as closed or as open switches. The three-state gates are activated in such a way that the three-state gate associated with the one of the two masters acts as a closed switch, and the three-state gate associated with the other of the two masters acts as an open switch.

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Номер записи: 54
19-07-2012 дата публикации

Apparatus and methods for serial interfaces

Номер: US20120185623A1
Автор: Florinel G. Balteanu, James Henry Ross
Принадлежит: Skyworks Solutions Inc

Apparatus and methods for serial interfaces are provided. In one embodiment, an integrated circuit operable to communicate over a serial interface is provided. The integrated circuit includes analog circuitry, registers for controlling the operation of the analog circuitry, and a distributed slave device including a primary block and a secondary block. The registers are accessible over the serial interface using a shared register address space. Additionally, the primary block is electrically connected to the serial interface and to a first portion of the registers and the secondary block is electrically connected to the primary block and to a second portion of the registers.

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Номер записи: 55
19-07-2012 дата публикации

Operation method for a computer system

Номер: US20120185631A1
Автор: Hua-Chih Yang, Liang-Chun Lin
Принадлежит: Prolific Technology Inc

A device receives a standard command. The device judges whether an address field and/or a data length field and/or a data field of the standard command includes at least one of a vendor command, a vendor data and a checkword. The device judges whether the address field and/or a data length field and/or the data field of the standard command matches a vendor predetermined pattern. If matched, the device performs a vendor operation based on the vendor command and/or the vendor data of the standard command.

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Номер записи: 56
19-07-2012 дата публикации

Computer architectures using shared storage

Номер: US20120185725A1
Автор: David D. Bettger, Dennis L. Kuehn, Kevin A. Stone, Marc A. Peters
Принадлежит: Boeing Co

A method includes providing a persistent common view of a virtual shared storage system. The virtual shared storage system includes a first shared storage system and a second shared storage system, and the persistent common view includes information associated with data and instructions stored at the first shared storage system and the second shared storage system. The method includes automatically updating the persistent common view to include third information associated with other data and other instructions stored at a third shared storage system in response to adding the third shared storage system to the virtual shared storage system.

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Номер записи: 57
26-07-2012 дата публикации

Expandable asymmetric-channel memory system

Номер: US20120191921A1
Автор: Arun Vaidyanath, Ian Shaeffer, Sanku Mukherjee
Принадлежит: RAMBUS INC

An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.

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Номер записи: 58
02-08-2012 дата публикации

Embedded system development platform

Номер: US20120198103A1
Автор: Chih-Chieh Han, David Alexander Butler, Shahram Izadi, Stephen E. Hodges
Принадлежит: Microsoft Corp

A modular development platform is described which enables creation of reliable, compact, physically robust and power efficient embedded device prototypes. The platform consists of a base module which holds a processor and one or more peripheral modules each having an interface element. The base module and the peripheral modules may be electrically and/or physically connected together. The base module communicates with peripheral modules using packets of data with an addressing portion which identifies the peripheral module that is the intended recipient of the data packet.

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Номер записи: 59
02-08-2012 дата публикации

System and Method for Facilitating Data Transfer Between a First Clock Domain and a Second Clock Domain

Номер: US20120198267A1
Автор: Alexander Raykhman, Philip Crary, Srinjoy Das
Принадлежит: Qualcomm Atheros Inc

System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.

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Номер записи: 60
09-08-2012 дата публикации

Transfer of Uncompressed Multimedia Contents or Data Communications

Номер: US20120203937A1
Автор: Ning Zhu, Soumendra Mohanty
Принадлежит: Individual

A system and corresponding method for transferring data via an interface assembly. The data may be transferred between a USB port of a first device and a media port of a second device. Uncompressed high definition media data may be received from the USB port. The received uncompressed high definition media data may be supplied to a media connector in accordance with a first media standard, such that the supplied data can be transmitted in accordance with the first media standard via the media connector to the media port of the second device. The uncompressed high definition media data may include multimedia data and side-band communication data. A single signal may be encoded and decoded in accordance with a protocol that enables the single signal to communicate all side-band communication to and from the source device via a single pin of a USB connector.

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Номер записи: 61
09-08-2012 дата публикации

Memory System with Calibrated Data Communication

Номер: US20120204054A1
Автор: Benedict Chung-Kwong Lau, Bruno W. Garlepp, Donald C. Stark, Jared Levan Zerbe, Jun Kim, Kevin S. Donnelly, Leung Yu, Mark A. Horowitz, Roxanne Vu, Stefanos Sidiropoulos, Tsyr-Chyang Ho
Принадлежит: RAMBUS INC

An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

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Номер записи: 62
16-08-2012 дата публикации

Method and apparatus for plug and play, networkable iso 18000-7 connectivity

Номер: US20120207141A1
Автор: John Peter Norair
Принадлежит: Blackbird Technology Holdings Inc

A device may comprise a Universal Serial Bus (USB) interface and a wireless interface operable to communicate in accordance with the ISO 18000-7 standard. The device may be operable to receive a command via the USB interface and transmit the command via the wireless interface. The device may be operable to receive data via the wireless interface and transmit the data via the USB interface. A form factor of the USB device may be such that it can be plugged directly into a USB port without any external cabling between the USB device and said USB port.

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Номер записи: 63
23-08-2012 дата публикации

Usb interface device and circuit board thereof

Номер: US20120214322A1
Автор: Chun-Wei Lee, Jeffrey Shue Jen Lu, Ping-Kun Lin
Принадлежит: Hon Hai Precision Industry Co Ltd

An exemplary USB interface device includes a circuit board and a USB socket mounted on the circuit board. The USB socket includes a connecting port, a plurality of electrical pins and fixing pins extending from a side of the USB socket. The circuit board defines first and second inserting hole groups. The USB socket can be selectively inserted into the first or second inserting hole group according to the type of USB socket. When the electrical pins and the fixing pins of the USB socket are inserted into and fixed on the first inserting hole group of the circuit board, the second inserting hole group is standing idle. When the electrical pins and the fixing pins of the USB socket are inserted into and fixed on the second inserting hole group of the circuit board, the first inserting hole group is standing idle.

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Номер записи: 64
23-08-2012 дата публикации

Supporting global input/output interconnect features on ports of a midpoint device

Номер: US20120215948A1
Автор: Jeffrey Michael Dodson
Принадлежит: PLX Technology Inc

In a first embodiment of the present invention, a method for operating a midpoint device utilizing an Input/Output (I/O) interconnect is provided, wherein the midpoint device contains a plurality of ports, the method comprising: receiving a request to initiate a session between a device on a first port of the midpoint device and a device on a second port of the midpoint device; retrieving information regarding whether the first port supports a feature, and information regarding whether the second port supports the feature; and when the first port supports the feature and the second port does not support the feature, permitting the session to be initiated, such that communications between the first device and the second device are performed partially using the feature, independently of support of the feature on other ports.

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Номер записи: 65
30-08-2012 дата публикации

Method for the operation of a data bus, and data bus system

Номер: US20120218601A1
Автор: Arno Best, Herbert Gibisch, Hermann Andresen, Robert Heimbach, Thomas Kreppold
Принадлежит: Individual

For operation of a data bus to which multiple bus participants each with a respective serial number are connected, a new bus participant is connected. A request bus message is generated by the new bus participant containing a preliminary participant identification number. The request bus message is arbitrated in the data bus by means of the identification number. A final participant identification number is assigned for the new bus participant having fewer digits than the serial number of the new participant. The final participant identification number is used for further bus messages by the new bus participant. During an initialization bus messages are used with an identifier in which a complete serial number is entered as the identifier. After the initialization a different type of bus message is used that has a shorter identifier.

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Номер записи: 66
30-08-2012 дата публикации

Integrated circuit

Номер: US20120218840A1
Автор: Jinyeong MOON
Принадлежит: Hynix Semiconductor Inc

An integrated circuit includes a plurality of data lines on which data aligned by a plurality of pulse signals are loaded, a plurality of transfer lines, a data transfer unit configured to transfer the data of the plurality of data lines to the plurality of transfer lines in response to a correlation signal, a data output unit configured to output the data of the transfer line corresponding to a transmission signal activated among a plurality of transmission signals, a correlation signal generation unit configured to generate the correlation signal using a latency value and a logic value of one of the plurality of transmission signals when a command is inputted to the correlation signal generation unit, and a pulse signal generation unit configured to sequentially activate the plurality of pulse signals when the command is inputted.

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Номер записи: 67
30-08-2012 дата публикации

Semiconductor memory device and method of controlling the same

Номер: US20120221918A1
Автор: Hironori Uchikawa, Shinichi Kanno
Принадлежит: Hironori Uchikawa, Shinichi Kanno

A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

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Номер записи: 68
06-09-2012 дата публикации

Method, apparatus, and system for speculative execution event counter checkpointing and restoring

Номер: US20120227045A1
Автор: Konrad K. Lai, Laura A. Knauth, Martin G. Dixon, Peggy J. Irelan, Ravi Rajwar
Принадлежит: Intel Corp

An apparatus, method, and system are described herein for providing programmable control of performance/event counters. An event counter is programmable to track different events, as well as to be checkpointed when speculative code regions are encountered. So when a speculative code region is aborted, the event counter is able to be restored to it pre-speculation value. Moreover, the difference between a cumulative event count of committed and uncommitted execution and the committed execution, represents an event count/contribution for uncommitted execution. From information on the uncommitted execution, hardware/software may be tuned to enhance future execution to avoid wasted execution cycles.

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Номер записи: 69
20-09-2012 дата публикации

Memory system with independently adjustable core and interface data rates

Номер: US20120239898A1
Автор: Frederick A. Ware
Принадлежит: Individual

An integrated circuit device is disclosed including core circuitry and interface circuitry. The core circuitry outputs in parallel a set of data bits, while the interface circuitry couples to the core circuitry. The interface circuitry receives in parallel a first number of data bits among the set of data bits from the core circuitry and outputs in parallel a second number of data bits. The ratio of the first number to the second number is a non-power-of-2 value.

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Номер записи: 70
27-09-2012 дата публикации

Configurable health-care equipment apparatus

Номер: US20120246375A1
Автор: Ian K. Edwards, Jon R. Salvati, Raymond A. Lia, Robert J. Wood, Robert L. Vivenzio, Scott A. Martin, Thaddeus J. Wawro
Принадлежит: Welch Allyn Inc

An apparatus, system and method for providing health-care equipment in a plurality of customizable configurations. A configuration includes a selection and arrangement of health-care equipment modules that each provide specialized support for the provision of health care, including the measurement of physiological parameters. Various types of configurations include those adapted to be mounted upon a desk top or a wall surface, or adapted for wheel mounting or hand-carriable mobile configurations.

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Номер записи: 71
27-09-2012 дата публикации

HID over Simple Peripheral Buses

Номер: US20120246377A1
Автор: Arvind R. AIYAR, David Abzarian, Firdosh K. Bhesania, Randall E. Aull
Принадлежит: Individual

In embodiments of HID over simple peripheral buses, a peripheral sensor receives inputs from a peripheral device, and the peripheral sensor implements an HID SPB interface to interface the peripheral device with a computing system via a simple peripheral bus (SPB) in an HID data format. The peripheral sensor can also receive extensibility data for a proprietary function of the peripheral device, and communicate the inputs from the peripheral device and the extensibility data via the simple peripheral bus in the computing system. Alternatively or in addition, a peripheral sensor can generate sensor data and the HID SPB interface interfaces the peripheral sensor with the computing system via the simple peripheral bus. The peripheral sensor can then communicate the sensor data as well as extensibility data for a proprietary function of the peripheral sensor via the simple peripheral bus in the HID data format to the computing system.

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Номер записи: 72
04-10-2012 дата публикации

Circuit providing load isolation and noise reduction

Номер: US20120250386A1
Автор: Chi-She Chen, Hyun Lee, Jayesh R. Bhakta, Jeffrey C. Solomon, Mario Jesus Martinez
Принадлежит: Netlist Inc

Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports.

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Номер записи: 73
11-10-2012 дата публикации

Electronic device with card interface

Номер: US20120260001A1
Автор: Akihisa Fujimoto, Hiroyuki Sakamoto, Kosei Okamoto, Masao Suga
Принадлежит: Toshiba Corp

When initializing a card-shaped device inserted in a card interface, operation mode acquiring means incorporated in an electronic device acquires operation mode information, stored in a register file incorporated in the card-shaped device, by a predetermined procedure using a predetermined pin. Operation mode setting means incorporated in the electronic device executes signal assignment on a plurality of data pins peculiar to an operation mode indicated by the acquired operation mode information, thereby switching a data transfer width, and allowing the card-shaped device to operate in the operation mode.

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Номер записи: 74
11-10-2012 дата публикации

Kvm switcher with ability to extend universal serial bus (usb) host interface via serial peripherial interface (spi)

Номер: US20120260018A1
Автор: Chun Tse LIN
Принадлежит: OCT Technology Co Ltd

A multi-computer (KVM) switcher with ability to extend universal serial bus (USB) host interface via serial peripheral interface (SPI), characterized in that SPI master device interface of master control unit can switch the capability of controlling plural SPI slave devices via serial peripheral interface (SPI), and through installing SPI slave device interfaces on plural universal serial bus (USB) host interface control units to be extended, the object of extending peripheral device with USB interface via SPI interface is achieved.

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Номер записи: 75
18-10-2012 дата публикации

Crosspoint switch with separate voltage sources for input and output ports

Номер: US20120262219A1
Автор: Merrick Brownlee, Poupak Khodabandeh
Принадлежит: Mindspeed Technologies LLC

A crosspoint switch device has a plurality of input ports each connected to a respective voltage source and a plurality of output ports each connected to a respective voltage source. A switch array selectively provides signal paths between the input ports and the output ports. The voltage sources are separate from one another.

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Номер записи: 76
18-10-2012 дата публикации

Microcomputer, system including the same, and data transfer device

Номер: US20120263429A1
Автор: Hideo Inoue, Yuji Shimoyama
Принадлежит: Renesas Electronics Corp

A microcomputer is provided, which can load data of different areas in parallel and transfer the loaded data to a storage circuit. The microcomputer includes a CPU to control a DRIs each of which loads image data of a prescribed area out of image data inputted from a camera and transfers the image data to a memory blocks, and the DRIs each of which transfers image data of respectively different area out of the image data inputted from the camera to the memory blocks. Therefore, it becomes possible to load image data of different areas in parallel and to transfer the loaded image data to the memory blocks.

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Номер записи: 77
18-10-2012 дата публикации

Server Input/Output Failover Device Serving Highly Available Virtual Devices

Номер: US20120265910A1
Автор: Luca Cafiero, Michael B. Galles
Принадлежит: Cisco Technology Inc

A failover input/output device and corresponding method are provided to manage failover events of input/output controller devices that operate in accordance with a computer expansion card standard, such as the Peripheral Component Interconnect Express (PCIe) standard. The failover input/output device connects to redundant first and second virtualized input/output controller devices each comprising multiple virtual network interfaces that are in an active or standby state at any given time, and to a computing device that hosts one or more processes. The failover input/output device broadcasts transactions in accordance with the computer expansion card standard initiated from the computing device to the first and second virtualized input/output controller devices. The failover input/output device receives signals associated with upstream transaction completions in accordance with the computer expansion card standard for both active and standby virtual network interfaces on the first and second virtualized input/output controller devices. The failover input/output device forwards signals associated with upstream transaction completions for active virtual network interfaces on the first and second virtualized input/output controller devices to the computing device.

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Номер записи: 78
25-10-2012 дата публикации

Semiconductor module includes semiconductor chip initialized by reset signal

Номер: US20120268173A1
Автор: Haruki Nagahashi, Masashi Kawamura, Susumu Hatano, Tadaaki YOSHIMURA, Takao Hirayama, Yoji Nishio
Принадлежит: Elpida Memory Inc

Disclosed herein is a device that includes a plurality of semiconductor chips mounted on a module substrate. Each of the semiconductor chips includes a reset terminal to which a reset signal is supplied, and an internal circuit that is initialized based on the reset signal. The module substrate includes a reset signal line connected commonly to the reset terminals of the semiconductor chips, and an anti-resonance element connected to the reset signal line.

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Номер записи: 79
25-10-2012 дата публикации

Sampling clock selection module of serial data stream

Номер: US20120269308A1
Автор: Chin-Chieh Chao, Hui Wen Miao, Ko-Yang Tso, Ren-Feng Huang
Принадлежит: Raydium Semiconductor Corp

A sampling clock selection module for a serial data stream is disclosed. The sampling clock selection module includes a multi-phase generation circuit, a sampling circuit, a comparison unit and a logic operation unit. The multi-phase generation circuit generates a plurality of non-overlapping clock phases derived from a reference clock signal. The phase selection circuit selects a sampling clock phase under a calibration mode. The sampling circuit performs sampling on the serial data stream a plurality of times to generate a plurality of sampled values in response to the sampling clock phase. The comparison unit compares the sampled values with the serial data stream so as to update a plurality of flag signals. The logic operation unit performs a logic operation on the flag signals so as to select a sampling clock phase under a normal operation mode from the clock phases.

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Номер записи: 80
25-10-2012 дата публикации

Interface

Номер: US20120272089A1
Автор: Gordon Richard Mcleod, John Laurence Pennock, Robert James Hatfield
Принадлежит: Wolfson Microelectronics plc

The present invention relates to methods and apparatus for data transfer. A data interface is described with at least a first data terminal for either outputting or receiving a data signal. In bi-directional embodiments there may be one terminal for receiving data and one terminal for outputting data. A bit clock terminal outputs or receives a bit clock signal; and a frame clock terminal for outputs or receives a frame clock signal. Interface control circuitry is configurable to associate data outputted or received in each frame with time slots (1-8) of a predetermined number of bits (x, y, z) wherein the control circuitry is adapted such that the frequency of the bit clock signal can be changed at any time so as to vary the number of time slots in a frame.

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Номер записи: 81
01-11-2012 дата публикации

Non-ported generic device (software managed generic device)

Номер: US20120278518A1
Автор: Hans Georg Gruber, Julio Arceo, Magesh Hariharan, Mark A. Landguth, Suren Mohan
Принадлежит: Qualcomm Inc

Techniques are disclosed for utilizing a non-ported generic device (NGD) or other non-ported hardware to couple processing device(s) to access components on a serial data bus without the need for integrated manager hardware. Using the NGD, a processing device(s) can utilize available unused bandwidth on the serial data bus to communicate with components coupled with the serial data bus, including a processing device having the manager hardware. Various alterations and embodiments are disclosed.

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Номер записи: 82
01-11-2012 дата публикации

Disk subsystem

Номер: US20120278523A1
Автор: Kazuhisa Aruga
Принадлежит: HITACHI LTD

A protocol controller disposed between switches in a fiber channel fabric switch circuit and disk drive units for converting a protocol to enable one-to-one connectivity established between controllers and disk drive units.

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Номер записи: 83
01-11-2012 дата публикации

Reconfigurable memory module and method

Номер: US20120278524A1
Автор: Joseph M. Jeddeloh, Terry R. Lee
Принадлежит: Round Rock Research LLC

A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes.

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Номер записи: 84
08-11-2012 дата публикации

Disc drive system

Номер: US20120281515A1
Автор: Matthias Loges
Принадлежит: Harman Becker Automotive Systems GmbH

A disc drive may provide data communications to a host using a universal serial bus (“USB”) interface. Activation of the USB interface may be triggered upon insertion of a disc into the disc drive. A connection unit may activate the USB interface by providing power to the USB interface when a disc switch detects that the disc has been inserted into the disc drive. The connection unit may deactivate the USB interface by no longer providing power to the USB interface when the disc switch detects that the disc has been ejected or no longer is in the disc drive.

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Номер записи: 85
08-11-2012 дата публикации

Zone group manager virtual phy

Номер: US20120284435A1
Автор: Balaji Natrajan, Michael G. Myrah, Sohail Hameed
Принадлежит: Hewlett Packard Development Co LP

A switch is provided. The switch includes an expander configured to couple a server to a set of storage drive bays. The switch also includes a zone manager coupled to the expander and configured to maintain a zoning configuration corresponding to the set of storage drive bays. The zone manager is coupled to the expander through a virtual PHY.

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Номер записи: 86
08-11-2012 дата публикации

Redundant Electrical Network Between Remote Electrical Systems and a Method of Operating Same

Номер: US20120284445A1
Автор: Geddielee Milton Parry
Принадлежит: SEAGRAVE FIRE APPARATUS LLC

A redundant electrical connection network may include a first electronic system having a first processor, a second, remote electric system having a second processor, a first communication link coupled between the first and second processors, and a second communication link coupled between the first and second processors. The second communication link may be separate and isolated from the first communication link, and the first and second processors may be configured to normally conduct data communications solely via one of the first and second communication links, and at least one of the first and second processors may be configured to monitor the one of the first and second communication links and re-route the data communications solely to the other of the first and second communication links upon detection of loss of the one of the first and second communication links.

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Номер записи: 87
08-11-2012 дата публикации

Constituting a control system with virtual and physical backplanes and modules as building blocks

Номер: US20120284447A1
Автор: Richard J. Grgic, Subbian Govindaraj
Принадлежит: Rockwell Automation Technologies Inc

A custom control system created based on combinations of software applications and hardware control and communication modules overlaid in a virtual backplane. The user can select the modules of interest and map them together without the loss of communications between the modules while the control system is configured and overlaid. The user can then archive the system design and implement the system with a greater level of confidence in the ability of the design to meet the requirements of the application while reducing the costs of the implementation.

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Номер записи: 88
15-11-2012 дата публикации

Data transfer apparatus and data transfer method

Номер: US20120290746A1
Автор: Akiyoshi Momoi, Chuma Nagao, Daisuke Shiraishi, Takeshi Hiraoka
Принадлежит: Canon Inc

A packet accompanying data valid information is transferred at high efficiency within an integrated circuit or between integrated circuits. A character indicating data enable information is provided and an identifier indicating a data enable character is assigned onto the packet. When the data enable information is valid in series, the data enable characters are eliminated from the packet to be transferred.

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Номер записи: 89
22-11-2012 дата публикации

Motherboard of computing device

Номер: US20120297132A1
Автор: Bo Tian, Guo-Yi Chen
Принадлежит: Hon Hai Precision Industry Co Ltd, Hongfujin Precision Industry Shenzhen Co Ltd

A motherboard of a computing device includes a dual inline memory module (DIMM), a processor socket, a platform controller hub (PCH), a switch, and a switch controller. The DIMM is connected to the processor socket or the PCH through the switch controller. The switch is connected to the switch controller, and generates a signal when the switch is operated. The switch controller controls the DIMM to connect either to the processor socket or to the PCH according to the signal, so that a solid state disk (SSD) or a memory that is connected to the DIMM can be supported appropriately by the motherboard.

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Номер записи: 90
29-11-2012 дата публикации

Heat management in an above motherboard interposer with peripheral circuits

Номер: US20120300392A1
Автор: Frederick G. Weiss, Morgan Johnson
Принадлежит: Morgan Johnson, Weiss Frederick G

A computing device has a circuit substrate having a socket, a main processor inserted into the socket, an interposer substrate inserted between the socket and the main processor, the circuit substrate, the socket and the interposer substrate being electrically connected, at least one peripheral circuit on the interposer substrate, and a heat sink thermally coupled to the peripheral circuit.

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Номер записи: 91
06-12-2012 дата публикации

Driving strength control apparatus, driving strength control method and terminal equipment

Номер: US20120306544A1
Автор: Yinong Liu
Принадлежит: SONY ERICSSON MOBILE COMMUNICATIONS AB

The embodiments of the present invention provide a driving strength control apparatus and method and terminal equipment. The control apparatus comprises: a signal receiving unit to receive a test signal transmitted by a peripheral device; a signal sampling unit to sample the test signal received by the signal receiving unit to obtain a plurality of rising edges and falling edges of the test signal; an interval measuring unit to measure the time interval between a rising edge and a falling edge, or between a rising edge and another rising edge, or between a falling edge and another falling edge; and a controlling unit to adjust the driving strength imposed on the peripheral device according to the time interval. With the embodiments of the present invention, the driving strengths imposed on the peripheral device may be made identical, preventing signal deviation and improving the quality of compatibility.

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Номер записи: 92
06-12-2012 дата публикации

Implementing device physical location identification in serial attached scsi (sas) fabric using resource path groups

Номер: US20120311222A1
Автор: Brian L. Bowles, Laurel Scaife, Robert E. Galbraith
Принадлежит: International Business Machines Corp

A method and controller for implementing device physical location identification in a Serial Attached SCSI (SAS) fabric using resource path groups, and a design structure on which the subject controller circuit resides are provided. The device physical location identification includes a Resource Path Group (RPG). Each RPG provides a unique persistent physical locator of a storage device in the system. Each RPG including at least two Resource Paths (RPs) and each RP has a fixed size identifying a type and a series of egress ports. A persistent RPG is stored within the device metadata on the storage device.

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Номер записи: 93
13-12-2012 дата публикации

Parallel communication device and communication method thereof

Номер: US20120317320A1
Автор: Tae Bum Park
Принадлежит: LSIS Co Ltd

Provided are a parallel communication device and a communication method thereof. The parallel communication device includes: a first receiving terminal receiving communication data transmitted through a master device; a first transmitting terminal transmitting the communication data received through the first receiving terminal to a slave device; a switch managing a communication line disposed between the first transmitting terminal and a plurality of slave devise; and a control unit confirming a first slave device to which the communication data are to be transmitted by using destination information in the communication data, and transmitting the received communication data to the confirmed first slave device.

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Номер записи: 94
13-12-2012 дата публикации

Processor bridging in heterogeneous computer system

Номер: US20120317321A1
Автор: Teng-Chang Chang
Принадлежит: INSTITUTE FOR INFORMATION INDUSTRY

A bridge logic device for a heterogeneous computer system that has at least one performance processor, a processor supporting logic supporting the at least one performance processor to execute tasks of the software, and a hypervisor processor consuming less power than the at least one performance processor is disclosed. The bridge logic device comprises a hypervisor operation logic that maintains status of the system under the at least one performance processor; a processor language translator logic that translates between processor languages of the at least one performance and the hypervisor processors; and a high-speed bus switch that has first, second and third ports for relaying data across any two of the three ports bidirectionally. The switch is connected to the at least one performance processor, the hypervisor processor via the processor language translator logic, and to the processor supporting logic respectively at the first, second, and third port.

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Номер записи: 95
20-12-2012 дата публикации

Apparatus and method for sharing i/o device

Номер: US20120324078A1
Автор: Junji Yamamoto, Ken Sugimoto, Kenichi Watanabe
Принадлежит: HITACHI LTD

In a server apparatus in which a plurality of physical servers and an I/O device are connected via an I/O switch, when the plurality of physical servers share one I/O device, a tag included in a request packet transmitted from a first physical server to the I/O device is translated into a value that is not used in the I/O device in the I/O switch and thereafter the request packet is transferred to the I/O device, and then a tag included in a response packet which responds to the request packet and which is transmitted from the I/O device to the first physical server is restored to the original tag, so that conflict of tags when a plurality of physical servers share one I/O device is avoided.

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Номер записи: 96
27-12-2012 дата публикации

Programmable mechanism for delayed synchronous data reception

Номер: US20120331325A1
Автор: Darius D. Gaskins, James R. Lundberg
Принадлежит: Via Technologies Inc

An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a Joint Test Action Group (JTAG) interface, a synchronous bus optimizer, and a delay-locked loop (DLL). The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to delay a data bit signal associated with a data group. The synchronous bus optimizer is configured to receive the control information, and is configured to develop a value on a ratio bus that indicates the amount. The DLL is coupled to the ratio bus, and is configured generate a delayed data bit signal, where the DLL adds the amount of delay to the data bit signal to generate the delayed data bit signal.

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Номер записи: 97
27-12-2012 дата публикации

Apparatus and method for advanced synchronous strobe transmission

Номер: US20120331326A1
Автор: Darius D. Gaskins, James R. Lundberg
Принадлежит: Via Technologies Inc

An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a resistor network, a core clocks generator, and a synchronous strobe driver. The resistor network is configured to provide a ratio signal that indicates an amount to advance a synchronous data strobe associated with a data group. The core clocks generator is coupled to the ratio signal, and is configured to advance a data strobe clock by the amount. The synchronous strobe driver is configured to receive the data strobe clock, and is configured to employ the data strobe clock to generate the synchronous data strobe, where the synchronous data strobe, when enabled, is advanced also by the amount.

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Номер записи: 98
03-01-2013 дата публикации

System and method for improving ecc enabled memory timing

Номер: US20130007320A1
Автор: Saya Goud Langadi
Принадлежит: Texas Instruments Inc

A pipeline communication system includes a master and a plurality of slaves configured to communicate with each other. Each of the plurality of slaves includes a memory, and is configured to generate a first ready signal and a second ready signal. The first ready signal is configured to be provided only to the master and the second ready signal is configured to be provided only to each of the plurality of slaves. The second ready signal is generated independent of the error check in each of the plurality of slaves.

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Номер записи: 99
10-01-2013 дата публикации

High Availability Device Level Ring Backplane

Номер: US20130010588A1
Автор: David S. Wehrle, Gerald R. Creech, Robert J. Kretschmann
Принадлежит: Rockwell Automation Technologies Inc

A modular, high-availability network for an industrial control system employs a plurality of base modules having backplane and using network ring topology. Base modules may include I/O base modules for communicating with industrial processes or machines, an adapter base module for communicating with a programmable logic controller (PLC) and/or a bus expansion base module for providing additional I/O base modules. Base modules may be arranged side-by-side, having a backplane in a bank. Another embodiment may include having plurality of banks. The network ring topology used by the base modules is normally opened by a ring supervisor at the ring supervisor location. Upon failure of the network, the ring supervisor reconnects the ring to provide an alternative transmission path around the failure point.

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Номер записи: 100