Steuerschaltung einer Flash-Speichervorrichtung unhtung

Ein Verfahren zum Betreiben einer Flash-Speichervorrichtung mit einem ersten Bereich und einem zweiten Bereich wird bereitgestellt, in welcher ein programmierter Zustand und ein gelöschter Zustand des ersten Bereiches gegensätzlich zu denjenigen des zweiten Bereiches sind. Das Verfahren weist folgende Verfahrensschritte auf: Empfangen eines Programmierbefehls; Invertieren der Programmierdaten, wenn der empfangene Programmierbefehl ein Befehl zur Programmierung des zweiten Bereiches ist; und Programmieren der invertierten Programmierdaten in den zweiten Bereich.

Method of using memory allocation to address hot and cold data

An apparatus, method and computer program for managing memory page updates within non-volatile memory

PROCEDURE FOR THE FLASH MEMORY ADMINISTRATION

MASS STORAGE ARCHITECTURE WITH FLASH MEMORY

Wear leveling in non-volatile storage systems

METHOD FOR ADDRESSING MEMORIES THAT CAN BE DELETED IN BLOCKS

WEAR MANAGEMENT FOR FLASH MEMORY DEVICES

A machine-implemented method for managing a flash storage system includes receiving a command for a data operation. The method includes determining a projected life value for each of a plurality of flash memory devices in the flash storage system, wherein the projected life value for at least one of the plurality of flash memory devices is higher than the projected life value for at least another one of the plurality of flash memory devices. The method also includes selecting a flash memory block on one of the plurality of flash memory devices for the data operation based on the respective projected life values for the plurality of flash memory devices.

Method for operating erasable and reprogrammable non-volatile memory system

DATA STORAGE DEVICE USING A NON-VOLATILE MEMORY UNIT TO EFFICIENTLY MANAGE DATA, A MEMORY SYSTEM AND A COMPUTER SYSTEM

PURPOSE: A data storage device, a memory system and a computer system are provided to improve the lifespan and writing performance of the data storage device using at least two or more heterogeneous non-volatile memories by distributively store user data and meta data. CONSTITUTION: A non-volatile memory system(1000) comprises a data storage device(100) and a controller(200). The controller is constructed so as to communicate with the outside through one of various interface protocols, and controls the data storage device. The data storage device comprises a memory cell array(130) consisting of flash memory cells. The memory cell array is divided into the first data storage region(110) and the second data storage region(120). The first and second data storage region consist of heterogeneous non-volatile memory cells having different properties. © KIPO 2009 ...

컨트롤러, 플래시 메모리 장치, 데이터 블록 안정성을 확인하는 방법, 그리고 플래시 메모리 장치에 데이터를 저장하는 방법

... 본 발명의 실시 예는 프로세서, 캐시, 및 통신 인터페이스를 포함하는 컨트롤러를 제공하며, 플래시 메모리 장치가 동일한 안정성 레벨을 가지는 데이터 블록들을 함께 저장하도록, 컨트롤러는 캐시로부터 제1 데이터 블록에 대한 정보를 판독하고, 제1 데이터 블록의 기준 카운트, 제1 데이터 블록이 플래시 메모리 장치에 저장되는 기간의 길이, 및 데이터 블록의 기준 카운트와 데이터 블록이 플래시 메모리 장치에 저장되는 기간의 길이와 안정성 레벨 사이의 매핑 관계에 따라 제1 데이터 블록의 안정성 레벨을 결정하고 - 안정성 레벨은 데이터 블록의 안정성을 나타내는 데 사용됨 -; 그리고 제1 데이터 블록의 논리 어드레스(logical address)와 제1 데이터 블록의 안정성 레벨을 통신 인터페이스를 통하여 플래시 메모리 장치로 전달하도록 구성된다.

Memory apparatuses for proactive corrective actions based on a probabilistic data structure, and methods of operating the same

Memory management device

Disclosed is a memory management device (1) that controls, corresponding to a write request and a readout request from a processor (6a), write and readout on and from main storage memory (2), which includes nonvolatile semiconductor memory (9) and volatile semiconductor memory (8). The memory control device (1) is provided with: a coloring information storage unit (17), which holds coloring information (14) generated based on the data characteristics of data to be written on the nonvolatile semiconductor memory (9) and/or the volatile semiconductor memory (8); and a write management unit (15), which refers to the coloring information (14) and determines a region in which the data to be written is to be written in the nonvolatile semiconductor memory (9) and the volatile semiconductor memory (8).

METHOD AND APPARATUS FOR PERFORMING WEAR LEVELING IN MEMORY

The embodiment of the solution provides a method for performing wear leveling in a memory. The method includes: dividing the lifecycle of the memory which includes more than one physical blocks into at least one sampling interval; for each sampling interval, getting the first physical block by taking statistics of the degree of the wear leveling of each physical block in the memory in the current sampling interval; getting the second physical block by taking statistics of the updating times of each logical address in the current sampling interval; exchanging the logical addresses and data of the first physical block and the second physical block. The embodiment of the solution also provides an apparatus corresponding the method.

MEMORY DEVICE PERFORMANCE ENHANCEMENT THROUGH PRE-ERASE MECHANISM

The specification and drawings present a new method, apparatus and software product for performance enhancement of a memory device (e.g., a memory card) using a pre-erase mechanism. The memory device can be, e.g., a memory card, a multimedia card or a secure digital card, etc. A new command or commands can be used to inform a memory device controller when the data in one particular sector, allocation unit or block can be deleted. Using that information the memory device controller then can be able to do some internal maintenance, e.g., by moving valid data from a fragmented erase block to another so that the fragmented erase block can be cleared and erased for future use as well as performing effective wear leveling maintenance and write performance optimization.

METHOD FOR FLASH-MEMORY MANAGEMENT

A SIM card including: (a) a first NVM for storing user data; and (b) a second NVM, separate from the first NVM, for storing management data related to the user data. Preferably, the first NVM is block-erasable and the second NVM is word-erasable. Preferably, the first NVM is a flash memory and the second NVM is an EEPROM. Preferably, the management data includes a mapping table for mapping virtual addresses, of the first NVM, to physical device addresses. Preferably, the user data and the management data are organized in a file system. Most preferably, the management data includes at least one file allocation table. Most preferably, the management data includes at least one files directory, wherein at least one files directory includes at least one item selected from the group consisting of: a file name, a file size, a file attribute, and a physical address of a file sector.

FLASH MEMORY MASS STORAGE ARCHITECTURE

A semiconductor mass storage system (100) and architecture can be substituted for a rotating hard disk. The system and architecture avoid an eras cycle each time information stored in the mass storage is changed. Erase cycles are avoided by programming an altered data file into an empty mass storage block (step 202-206) rather than over itself as hard disk would. Periodically, the mass storage will need to be cleaned up (step 204). Secondly, means are provied for evenly using all blocks in the mass storage (Fig. 7). These advantages are achieved through the use of several flags (200), a map to correlate a logical address of a block to a physical address of that block (308, 408) and a count register for each block. In particular, flags are provided for defective blocks (118), used blocks (112), old version of a block (104, 116), a count to determine the number of times a block has been erased and written and erase inhibit flag (200).

Garbage collection in solid state drives

In a solid state drive, a journal may be associated with a cluster block, such that the journal stores updates to an indirection mapping data structure for that cluster block. The journals may be stored on the cluster block. During garbage collection these spatially coupled journals can be retrieved and used to determine the data written to each media location within the cluster block. Logical and physical address information can be determined from the journal content, and used to compare against the current mapping in the indirection mapping data structure, to determine the validity of each media location. Since the journals are physical media aware, this comparison can occur without the consultation of a bad block tracking structure. When a physical media address is deemed to hold valid data it will be relocated as part of garbage collection processing.

Zoned Namespaces in Solid-State Drives

The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a media unit. The capacity of the media unit is divided into a plurality of zones. The controller is configured to make informed use of errors by update zone metadata to indicate one or more first logical block addresses were skipped and to indicate the next valid logical block address is available to store data. The controller is further configured to update zone metadata to recommend to the host device to reset one or more full zones, to recommend to the host device to transition one or more open zones to a full state, to alert the host device that one or more open zones have been transitioned to the full state, and to notify the host device of the writeable zone capacity of each of the plurality of zones. 1. A storage device , comprising:a media unit, wherein a capacity of the media unit is divided into a plurality of zones, and wherein the media unit comprises a plurality of dies, each of the plurality of dies comprising a plurality of erase blocks; and update zone metadata to recommend to a host device to reset one or more full zones of the plurality of zones;', 'update the zone metadata to recommend to the host device to transition one or more open zones of the plurality of zones to a full state;', 'transition the one or more open zones to the full state; and', 'update the zone metadata to alert the host device that the one or more open zones have been transitioned to the full state., 'a controller coupled to the media unit, the controller configured to2. The storage device of claim 1 , wherein the controller is configured to issue an event to inform the host device that the zone metadata has changed upon updating an attribute in the zone metadata of Reset Full Zone Anticipated claim 1 , Transition Zone to Full Recommendation claim 1 , or Controller Transitioned Full Zone.3. The storage device of claim 1 , wherein the zone metadata is ...

SYSTEM AND METHOD OF UPDATING METABLOCKS

A method includes, in a data storage device that includes a non-volatile memory having multiple memory dies, determining whether one or more metablocks are metablock update candidates based on relinking metrics corresponding to the one or more metablocks. Each memory die includes multiple blocks of storage elements and metablocks are formed through linking of blocks from the multiple memory dies. The method also includes comparing a number of the metablock update candidates to a relinking pool threshold. The method further includes, in response to the number of the metablock update candidates satisfying the relinking pool threshold, updating the linking of the blocks of the metablock update candidates to form updated metablocks. Linking of blocks may be updated by changing fields of a metablock data table, and blocks may be grouped based on block health values to extend an average useful life of the updated metablocks.

MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY

According to one embodiment, for each area having a first size, a number of accesses to the area is recorded in first information. In units of sub areas each having a second size smaller than the first size, access information for the sub area is recorded in the second information. In the first information, the number of accesses to an area to which a sub area in which duplicate accesses occur belongs is updated.

Mobile communication terminal

A mobile communication terminal comprises an information managing portion 1 , and a nonvolatile storing medium 2 attached to the information managing portion 1 , and the nonvolatile storing medium 2 has a plurality of memory areas for storing same information items in sequence. According to this configuration, when storing of the information items, e.g., the time information, etc., whose access frequency is high are updated by using the nonvolatile storing medium, the burden imposed on the nonvolatile storing medium can be reduced by using different areas. Thus, the information items having a high updating frequency, e.g., the time information, etc. can be stored in the nonvolatile storing medium whose lifetime is short and then employed.

Enhancing the lifetime and performance of flash-based storage

A storage management system decouples application write requests from write requests to a flash-based storage device. By placing a layer of software intelligence between application requests to write data and the storage device, the system can make more effective decisions about when and where to write data that reduce wear and increase performance of the storage device. An application has a set of performance characteristics and writes data with a frequency that is appropriate for the application, but not necessarily efficient for the hardware. By analyzing how data is being used by an application, the system can strategically place data in the storage device or even avoid using the storage device altogether for some operations to minimize wear. One technique for doing this is to create an in-memory cache that acts as a buffer between the application requests and the storage hardware.

UNALIGNED DATA COALESCING

The present disclosure includes methods and systems for coalescing unaligned data. One method includes receiving a first write command associated with a first unaligned portion of data, receiving a second write command associated with a second unaligned portion of data, and coalescing the first unaligned portion of data and the second unaligned portion of data, wherein coalescing includes writing the first unaligned portion of data and the second unaligned portion of data to a page in a memory device.

Optimizing Write and Wear Performance for a Memory

Determining and using the ideal size of memory to be transferred from high speed memory to a low speed memory may result in speedier saves to the low speed memory and a longer life for the low speed memory. 1. A method performed on a computing device , the method comprising:caching, by the computing device, data in a volatile random access memory, where the data being cached is designated to be stored in first disk-based memory; andbacking-up, by the computing device, a first preferred amount of the cached data to an additional memory that comprises flash-based memory or second disk-based memory.2. The method of where the first preferred amount corresponds to a preferred write size of the additional memory.3. The method of further comprising writing a second preferred amount of the cached data to the first disk-based memory.4. The method of where the second preferred amount corresponds to a preferred write size of the first disk-based memory.5. The method of further comprising writing claim 1 , in response to the first preferred amount of the data being cached in the volatile random access memory claim 1 , the first preferred amount of the cached data to the flash-based memory or the second disk-based memory.6. The method of where the writing is further in response to a period of low system activity.7. The method of further comprising determining that a portion of the cached data in the volatile random access memory has been replaced with newer cached data prior to the writing.8. A computing device comprising:at least one processor;volatile random access memory;first disk-based memory; and caching data in the volatile random access memory, where the data being cached is designated to be stored in the first disk-based memory; and', 'backing-up, by the computing device, a first preferred amount of the cached data to an additional memory that comprises flash-based memory or second disk-based memory., 'computer-executable instructions that, based on execution by the at ...

Controller for minimizing flushing operations for mapping table, memory system and operating method thereof

A memory system includes a memory device comprising a plurality of memory cells storing data, and configured to perform one or more of a write operation, read operation and erase operation on the plurality of memory cells; and a controller configured to control an operation of the memory device, wherein the controller is configured to: cache a logical block addressing (LBA) mapping table from the memory device when the memory system is powered on by driving power applied thereto; and transfer a direct memory access (DMA) setup to a host when the LBA mapping table is cached.

CONTROLLER, OPERATING METHOD OF THE CONTROLLER AND MEMORY SYSTEM

A memory system includes: a plurality of memory devices; a plurality of cores suitable for controlling the plurality of memory devices, respectively; and a controller including: a host interface layer for providing any one of the cores with a request of a host based on mapping between logical addresses and the cores, a remap manager for changing the mapping between the logical addresses and the cores in response to a trigger, a data swapper for swapping data between the plurality of memory devices based on the changed mapping, and a state manager for determining a state of the memory system depending on whether the data swapper is swapping the data or has completed swapping the data, and providing the remap manager with the trigger based on the state of the memory system and a difference in a degree of wear between the plurality of memory devices.

IMPLANTABLE MEDICAL DEVICE HAVING A SCHEME FOR MANAGING STORAGE OF DATA

The disclosure describes a scheme for managing the operations of a flash memory. The scheme enables the flash memory to be used in a write-once mode to allow non-volatile storage of small amounts of data that must be written repeatedly. Among other things, the scheme eliminates the need to erase sectors of the flash memory, thus eliminating the high current consumption associated with erasures, while enabling preservation of relevant data in those sectors. In the context of an implantable medical device, this scheme is used to store data that is needed after a reset of the device, such as MRI-related data that is/are dynamically adjusted by firmware, or program code updates.

Non-volatile memory data write management

An open block management apparatus, system, and method for non-volatile memory devices is disclosed herein, providing improved performance for namespace-based host applications. The namespace identifier is applied to determine the open blocks to which to direct data from storage commands. One benefit of the disclosed technique is fewer de-fragmentation operations and more efficient memory garbage collection. Another benefit is the ability to secure private allocations of physical memory without needing to assign a partition or implement hardware isolation.

Storage system using flash memories, wear-leveling method for the same system and wear-leveling program for the same system

A storage system (100) using flash memories includes a storage controller (SC) and plural flash memory modules (Pxx) as storage media. Each flash memory module includes at least one flash memory chip (MEM) and a memory controller (MC) for leveling erase counts of blocks belonging to the flash memory chip. The storage controller combines the plural flash memory modules into a first logical group, translates a first address used for accessing the flash memory modules belonging to the first logical group to a second address used for handling the first address in the storage controller, and combines the plural first logical groups into a second logical group.

FLASH MEMORY WITH REDUCED ERASING AND OVERWRITING

METHOD OF OPERATING STORAGE DEVICE, STORAGE DEVICE PERFORMING THE SAME AND STORAGE SYSTEM INCLUDING THE SAME

УПРАВЛЕНИЕ УДАЛЕНИЕМ В СИСТЕМАХ ПАМЯТИ

Изобретение относится к области управления данными в системе памяти. Технический результат заключается в повышении длительности срока службы и пригодности устройства. Способ для управления системой энергонезависимой памяти, в котором, в ответ на прием уведомления о том, что данные, сохраненные в области ячеек сохранения в системе энергонезависимой памяти, содержат данные, не предназначенные для использования, система сохраняет данные, не предназначенные для использования, помечая область как содержащую данные, не предназначенные для использования; и управляют временем, в течение которого область ячеек сохранения находится в состоянии удаления, выполняют задержку операции удаления данных, не предназначенных для использования, удаляют данные, не предназначенные для использования, в ответ на детектирование необходимости сохранять данные замещения в системе энергонезависимой памяти. 5 н. и 20 з.п. ф-лы, 9 ил.

СПОСОБ УПРАВЛЕНИЯ ТЕХНИЧЕСКИМ РЕСУРСОМ ЭНЕРГОНЕЗАВИСИМОЙ ПАМЯТИ

... 1. Способ управления техническим ресурсом системы хранения данных, содержащей набор секторов, обладающих собственным гарантированным техническим ресурсом (G), содержащий следующие этапы:- разбивают упомянутую систему хранения данных на ряд рабочих секторов и ряд резервных секторов, способных сформировать резерв технического ресурса, причем определенные рабочие сектора подлежат замещению резервными секторами в случае износа упомянутых рабочих секторов после определенного количества циклов программирования и/или стирания;- задают зону управления адресами для определения расположения резервных секторов, назначаемых на замещение изношенных рабочих секторов;- определяют, сектор за сектором, изношен ли текущий сектор физически и замещают данный рабочий сектор резервным сектором, только если текущий сектор признан физически изношенным;отличающийся тем, что для оценки износа сектора производят автоматическое считывание качества стирания точек памяти упомянутого сектора и сравнивают с пограничным ...

DATENSPEICHERSYSTEME UND VERFAHREN ZUM AUTONOMEN ANPASSEN DER LEISTUNG, KAPAZITÄT UND/ODER DER BETRIEBSANFORDERUNGEN EINES DATENSPEICHERSYSTEMS

Vorrichtung, Medien, Verfahren und Systeme für Datenspeichersysteme und Verfahren zum autonomen Anpassen der Leistung, Lebensdauer, Kapazität und/oder Betriebsanforderungen von Datenspeichersystemen. Ein Datenspeichersystem kann eine Steuerung und eine oder mehrere nichtflüchtige Speichervorrichtungen umfassen. Die Steuerung ist dazu eingerichtet, eine Kategorie für eine Arbeitslast von einer oder mehreren Operationen zu bestimmen, die vom Datenspeichersystem unter Verwendung eines maschinell gelernten Modells verarbeitet werden. Die Steuerung ist dazu eingerichtet, eine erwartete Beeinträchtigung der einen oder mehreren nichtflüchtigen Speichervorrichtungen zu bestimmen. Die Steuerung ist dazu eingerichtet, basierend auf der erwarteten Beeinträchtigung und einer tatsächlichen Nutzung von physischem Speicher des Datenspeichersystems durch ein Host-System eine Menge an physischem Speicher des dem Host-System zur Verfügung stehenden Datenspeichersystems einzustellen.

PROCEDURE FOR THE OPERATION OF A DATA MEMORY DEVICE USING PASSIVE MATRIX ADDRESSING

PROCEDURE AND EQUIPMENT FOR THE ADMINISTRATION OF THE NUMBER OF DELETIONS OF BLOCKS

WEAR LEVELING IN NON-VOLATILE STORAGE SYSTEMS

Flash memory architecture with separate storage of overhead and user data

Method and apparatus for using a one-time or few-time programmable memory with a host device designed for erasable/rewriteable memory

Garbage collection and data relocation for data storage system

Managing data in a data storage system including at least one Data Storage Device (DSD) and a host. An initial location is determined for data to be stored in the at least one DSD based on at least one attribute defined by the host. A source portion is identified from a plurality of source portions in the at least one DSD for a garbage collection operation based on the at least one attribute defined by the host. A destination portion is identified in the at least one DSD for storing data resulting from the garbage collection operation based on the at least one attribute defined by the host. Garbage collection of the data in the source portion is performed into the destination portion, and after completion of garbage collection, the source portion is designated as a new destination portion for a new garbage collection operation.

METHOD AND APPARATUS FOR USING A ONE-TIME OR FEW-TIME PROGRAMMABLE MEMORY WITH A HOST DEVICE DESIGNED FOR ERASABLE/REWRITEABLE MEMORY

MEMORY DEVICE PERFORMANCE ENHANCEMENT THROUGH PRE-ERASE MECHANISM

The specification and drawings present a new method, apparatus and software product for performance enhancement of a memory device (e.g., a memory card) using a pre-erase mechanism. The memory device can be, e.g., a memory card, a multimedia card or a secure digital card, etc. A new command or commands can be used to inform a memory device controller when the data in one particular sector, allocation unit or block can be deleted. Using that information the memory device controller then can be able to do some internal maintenance, e.g., by moving valid data from a fragmented erase block to another so that the fragmented erase block can be cleared and erased for future use as well as performing effective wear leveling maintenance and write performance optimization.

APPARATUS AND METHOD FOR PERFORMING GARBAGE COLLECTION BY PREDICTING REQUIRED TIME

Apparatus and method for managing non-volatile memory

METHOD AND A DEVICE FOR ADJUSTING A USER USABLE MEMORY CAPACITY AND A RESERVED MEMORY CAPACITY OF A FLASH EEPROM

PURPOSE: A method and a device for adjusting a memory capacity are provided to adjust a user usable memory capacity and a reserved memory capacity of the flash EEPROM according to a use state of the data storage device, thereby increasing lifetime of a flash EEPROM(Electronically Erasable Programmable ROM)-based storage device. CONSTITUTION: A flash EEPROM(40) includes a user usable memory region(41) for storing user data and a reserved memory region(43) having at least one reserved block(45). A processor(30) stores a series of instructions, and reconfigures mapping information of the flash EEPROM representing the user usable memory region and the reserved memory region based on an inputted parameter when the instructions are executed in response to a capacity adjusting command. The parameter is a user usable memory region value, a reserved memory region value, a ratio between the user and reserved memory region values, or the number of reserved blocks. The processor includes an FTL(Flash ...

비정렬 데이터 통합

... 본 발명은 비정렬 데이터를 통합하기 위한 방법들 및 시스템들을 포함한다. 하나의 방법은 데이터의 제 1 비정렬 부분과 연관된 제 1 기록 명령어를 수신하는 단계, 데이터의 제 2 비정렬 부분과 연관된 제 2 기록 명령어를 수신하는 단계; 및 상기 데이터의 제 1 비정렬 부분 및 상기 데이터의 제 2 비정렬 부분을 통합하는 단계를 포함하며, 상기 통합 단계는 상기 데이터의 제 1 비정렬 부분 및 상기 데이터의 제 2 비정렬 부분을 메모리 디바이스에서의 페이지에 기록하는 단계를 포함한다.

METHOD OF ACHIEVING WEAR LEVELING IN FLASH MEMORY USING RELATIVE GRADES

MEMORY SYSTEM AND OPERATING METHOD THEREOF

The present invention relates to a memory system capable of supporting a wear-leveling operation and an operating method thereof. The memory system includes: a nonvolatile memory device having K memory blocks; and a controller suitable for controlling an operation of the nonvolatile memory device. The controller may include: a counting management unit suitable for using K count codes capable of counting a preset range from a base value to a limit value in order to manage K counting values corresponding to predetermined operations of the K memory blocks, respectively, and adjusting the absolute values of the base value and the limit value using the count code in the form of a 1/N-chain depending on a distribution of the K counting values; and a wear-leveling operation unit suitable for performing a wear-leveling operation on the K memory blocks such that the K counting values are distributed in a section of values corresponding to 1/N of the preset range, the count code may be a J-based ...

STORAGE DEVICE USING BUFFER MEMORY IN READ RECLAIM OPERATION

TRACKING THE MOST FREQUENTLY ERASED BLOCKS IN NON-VOLATILE STORAGE SYSTEMS

Methods and apparatus for performing wear leveling in a non-volatile memory system are disclosed. According to one aspect of the present invention, a method for processing elements included in a non-volatile memory of a memory system includes obtaining erase counts associated with a plurality of erased elements. Each element included in the plurality of elements has an associated erase count that indicates a number of times the element has been erased. The method also includes grouping a number of erased elements included in the plurality of elements into a first set, and storing the erase counts associated with the first set in a memory component of the memory system. Grouping the number of elements into the first set typically includes selecting erased elements included in the plurality of elements which have the highest associated erase counts of the erase counts associated with the plurality of elements. © KIPO & WIPO 2007 ...

Solid-state disk and operation method of the same

Data storage device, memory system, and computing system using nonvolatile memory device

Provided is a data storage device including two or more data storage areas including may have two or more (heterogeneous) types of nonvolatile memory cells. At least one of the data storage areas includes a plurality of memory blocks that are sequentially selected, and metadata are stored in the currently selected memory block. The memory blocks can be sequentially used and metadata can be stored in a uniformly-distributed manner throughout the data storage device. Therefore, separate merging and wear-leveling operations are unnecessary. Thus, it is possible to improve the lifetime and writing performance of a data storage device having two or more heterogeneous nonvolatile memories.

Memory system

HYBRID MEMORY MANAGEMENT

Methods and apparatus for managing data storage in hybrid memory devices utilizing single level and multi level memory cells. Logical addresses can be distributed between single level and multilevel memory cells based on a frequency of write operations performed. Initial storage of data corresponding to a logical address in memory can be determined by various methods including initially writing all data to single level memory or initially writing all data to multilevel memory. Other methods permit a host to direct logical address writes to single level or multilevel memory cells based on anticipated usage.

APPARATUS INCLUDING MEMORY SYSTEM CONTROLLERS AND RELATED METHODS

Memory controllers can include a switch and non-volatile memory control circuitry including channel control circuits coupled to the switch. The channel control circuits can coupled to logical units including blocks. Volatile memory and memory management circuitry including local memory can be coupled to the switch. The memory management circuitry can be configured to store health and status information for each of the blocks in a block table in the volatile memory, store a candidate block table that identifies a candidate block for a particular operation based on criteria in the local memory, update the health and status information for a particular block in the block table, compare the updated health and status information for the particular block with the candidate block according to the criteria, and update the candidate block table to identify the particular block in response to the comparison indicating that the particular block better satisfies the criteria.

EXTENDING FLASH DRIVE LIFESPAN

In a computer-implemented method for filtering input/output operations of a flash drive, an input/output request directed toward a flash drive is received. It is determined whether the input/output request is associated with a high volume write operation. If the input/output request is associated with the high volume write operation, a flash drive input/output management action to perform is selected. If the input/output request is not associated with the high volume write operation, the input/output request is forwarded to the flash drive.

Array controller, solid state disk, and method for controlling solid state disk to write data

Application relates to storage technologies, and in particular, to writing data in a storage system having solid state disks. Embodiments of the application provide an array controller, including a communication interface and a processor. The processor receives information about a logical block from a solid state disk. The information about the logical block includes a size of the logical block and indication information of the logical block, and the logical block includes one or more physical blocks. The processor sends multiple write data requests to the solid state disk. Each write data request includes data, and each write data request instructs the solid state disk to write the data into the logical block indicated by the indication information of the logical block. A total size of data included in the multiple write data requests is equivalent to the size of the logical block.

Effective wear-leveling and concurrent reclamation method for embedded linear flash file systems

Reclamation of an Erase Unit of a flash memory is performed concurrently with a file operation on the flash memory by initiating a reclamation operation on the individually erasable portion of the memory, by suspending the reclamation operation for the file operation, by performing the file operation, and by resuming the reclamation operation.

Hybrid memory module and transaction-based memory interface

A hybrid module includes one or more memory modules, each of which includes one or more memory devices and a memory controller, one or more storage modules, each of which includes one or more storage devices and a storage controller. A host interface of the hybrid module includes a main controller and provides an interface with the memory controller and the storage controller. A transaction-based memory interface provides an interface between the main controller and a host memory controller.

Method for Enhancing Life Cycle of Memory

A hierarchical mechanism for preventing concentrated wear on single physical block or a specific set of physical blocks in the physical memory is proposed. The logical blocks mapping to the physical blocks in the physical memory are classified into two different levels for implicitly representing the modification times of the physical blocks. A modify count and a maximum modify count are further included for counting the modification times in a single process of the hierarchical mechanism and for limiting the modification times in single process, leading to the probabilities of all the physical blocks being modified in the physical memory being balanced. The breakdown of the physical memory caused by the breakdown of a specific set of physical blocks or single physical block is thus prevented.

Memory module and information processing system

A memory module includes: a first memory device that is volatile or non-volatile; a second memory device that is non-volatile; a third memory device that is non-volatile; and a controller that controls the first to third memory devices, wherein a capacity of the second memory device is larger than a capacity of the first memory device, and a capacity of the third memory device is larger than the capacity of the second memory device, a second upper limit value of the number of rewritings of the second memory device is larger than a third upper limit value of the number of rewritings of the third memory device, and a first upper limit value of the number of rewritings of the first memory device is larger than the second upper limit value of the number of rewritings of the second memory device, and the controller accesses the second memory device with reference to a first address translation table related to the second memory device stored in the first memory device, and accesses the third ...

Method and apparatus for using a one-time or few-time programmable memory with a host device designed for erasable/rewriteable memory

The embodiments described herein can be used to enable one-time or few-time programmable memories to work with existing consumer electronic devices (such as those that work with flash—an erasable, non-volatile memory) without requiring a firmware upgrade, thereby providing backwards compatibility while minimizing user impact. As such, these embodiments are a viable way to bridge one-time or few-time programmable memories with existing consumer electronic devices that have flash card slots. These embodiments also allow future consumer electronic devices to be designed without updating firmware to include a file system customized for a one-time or few-time programmable memory.

Proactive corrective actions in memory based on a probabilistic data structure

The present disclosure includes apparatuses and methods for proactive corrective actions in memory based on a probabilistic data structure. A number of embodiments include a memory, and circuitry configured to input information associated with a subset of data stored in the memory into a probabilistic data structure and proactively determine, at least partially using the probabilistic data structure, whether to take a corrective action on the subset of data stored in the memory.

System and method for data inversion in a storage resource

A method may comprise receiving a page of data to be stored on a storage resource. The method may also comprise determining, for each particular inversion mode of a plurality of inversion modes, the number of bits of the page of data to be inverted to store a representation of the page of data in accordance with the particular inversion mode. The method may additionally comprise determining a selected inversion mode from the plurality of inversion modes for the page of data, the selected inversion mode comprising the inversion mode for which the least number of physical bit transitions are required to store the representation of the page of data in accordance with the selected inversion mode. The method may further comprise storing the representation of the page of data in a data memory in accordance with the inversion mode.

SYSTEMS AND METHODS FOR ACCESSING NON-VOLATILE MEMORY AND WRITE ACCELERATION CACHE

Embodiment of a storage stack are disclosed whereby increased performance and other technical improvements are achieved by an application requesting access (e.g., asynchronously) to an address, returning a buffer, and the application issuing a buffer release when the operation is complete.

Flash memory mass storage architecture incorporating wear leveling technique without using cam cells

A semiconductor mass storage device can be substituted for a rotating hard disk. The device avoid an erase cycle each time information stored in the mass storage is changed. Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. Secondly, a circuit and method are provided for evenly using all blocks in the mass storage. These advantages are achieved through the use of several flags, a map to correlate a logical address of a block to a physical address of that block and a count register for each block. In particular, flags are provided for defective blocks, used blocks, old versions of a block, a count to determine the number of times a block has been erased and written and an erase inhibit flag. Reading is performed by providing the logical block address to the memory storage. The system sequentially compares the stored logical block addresses until ...

APPARATUS AND METHOD FOR PROCESSING DATA IN MEMORY SYSTEM

A memory system includes a memory device and a controller. The memory device includes plural blocks, each capable of storing data. The controller records operation information used for determining which blocks among the plural blocks a voluminous data is to be programmed. The voluminous data has a size that requires at least two blocks among the plural blocks. After performing a program operation of the voluminous data, the controller can resume the program operation based on the operation information after the program operation is halted.

UNALIGNED DATA COALESCING

The present disclosure includes methods and systems for coalescing unaligned data. One method includes receiving a first write command associated with a first unaligned portion of data, receiving a second write command associated with a second unaligned portion of data, and coalescing the first unaligned portion of data and the second unaligned portion of data, wherein coalescing includes writing the first unaligned portion of data and the second unaligned portion of data to a page in a memory device.

Memory controller and methods for enhancing write performance of a flash device

A memory controller and methods for managing efficient writing to a flash memory are presented. Fresh data is written to at least one block of the flash memory. During a space reclamation process, other data, previously written to the flash memory, is relocated to at least one other block of the flash memory, such that the fresh data and the relocated data always are maintained in separate blocks of the flash memory. During writing, an update frequency level is selected for the fresh data from among multiple update frequency levels and the fresh data is written to a block that is associated with the selected update frequency level. During space reclamation, a plurality of blocks, space of which is to be reclaimed, is selected and the valid pages thereof are copied to at least one destination block.

METHOD FOR CONTROLLING A MEMORY INTERFACE AND ASSOCIATED INTERFACE

NON-VOLATILE MEMORY SYSTEM WITH END OF LIFE CALCULATION

MEMORY DEVICE

PROBLEM TO BE SOLVED: To preliminarily prevent any accident to change data due to the accumulated influence of disturbance in a memory area which rewriting dose not generate is prevented beforehand. SOLUTION: A memory device comprises an erasable and writable nonvolatile memory (2) and a control circuit (5). The control circuit is made possible to perform the replacing processing of a memory area in a predetermined timing. The replacing processing is performed by writing the stored data of a first memory area, which has relatively a fewer number of times of rewrite, in a second memory area which is not used and replaces the first memory area with the second memory area, where the data has been written, as a working area. Thus, a memory area which has a fewer number of times of rewrite is used as an object to be replaced with another memory area so that it is possible to preliminarily prevent any accident to change illegal data due to the accumulated influence of disturbance in a memory ...

СПОСОБ УПРАВЛЕНИЯ ТЕХНИЧЕСКИМ РЕСУРСОМ ЭНЕРГОНЕЗАВИСИМОЙ ПАМЯТИ

Изобретение относится к вычислительной технике. Технический результат заключается в увеличении общего технического ресурса памяти. Способ управления техническим ресурсом системы хранения данных, в котором разбивают систему хранения данных на ряд рабочих секторов и ряд резервных секторов, способных сформировать резерв технического ресурса, причем определенные рабочие сектора подлежат замещению резервными секторами в случае износа упомянутых рабочих секторов после определенного количества циклов программирования и/или стирания; задают зону управления резервными секторами для определения расположения резервных секторов, назначаемых на замещение изношенных рабочих секторов; определяют, сектор за сектором, изношен ли текущий рабочий сектор физически и замещают данный рабочий сектор резервным сектором, только если текущий рабочий сектор признан физически изношенным; причем для оценки износа сектора производят автоматическое считывание качества стирания точек памяти упомянутого сектора и сравнивают ...

КОНТРОЛЛЕР МАССИВА, ТВЕРДОТЕЛЬНЫЙ ДИСК И СПОСОБ ДЛЯ УПРАВЛЕНИЯ ТВЕРДОТЕЛЬНЫМ ДИСКОМ ДЛЯ ЗАПИСИ ДАННЫХ

Изобретение относится к средствам управления твердотельным диском для записи данных. Технический результат заключается в повышении достоверности записи данных. Изобретения предоставляют контроллер массива, включающий в себя процессор и интерфейс связи, выполненный с возможностью осуществлять связь с твердотельным диском. Процессор осуществляет прием информации о логическом блоке, отправленной твердотельным диском, где информация о логическом блоке включает в себя размер логического блока и указывающую информацию логического блока, и логический блок включает в себя один или более блоков. Процессор дополнительно выполнен с возможностью отправки нескольких запросов записи данных в твердотельный диск, где каждый запрос записи данных переносит целевые данные, каждый запрос записи данных используется для предписания твердотельному диску записать целевые данные в соответствующий логический блок, при этом сумма длин целевых данных, переносимых в нескольких запросах записи данных, равна размеру ...

КОНТРОЛЛЕР МАССИВА, ТВЕРДОТЕЛЬНЫЙ ДИСК И СПОСОБ ДЛЯ УПРАВЛЕНИЯ ТВЕРДОТЕЛЬНЫМ ДИСКОМ ДЛЯ ЗАПИСИ ДАННЫХ

FLASH-SPEICHER MIT VERRINGERTER LÖSCHUNG UND ÜBERSCHREIBUNG

Reduktion der Schreibverstärkung in einem Objektspeicher

Ein Verfahren zum Verwalten eines Speichersystems mit einem oder mehreren Speichervorrichtungen umfasst das Empfangen einer Anforderung, in einer gestuften Datenstruktur auf ein Datenobjekt und ein oder mehrere Attribute des Datenobjektes zuzugreifen und die Zugriffsanforderung zu verarbeiten. Die Anforderung weist einen ersten Schlüsselwert für das Datenobjekt und jeweilige zweite Schlüsselwerte für das eine oder die mehreren Attribute des Datenobjektes auf. Modifizierte Schlüsselwerte für die Attribute des Datenobjektes werden in Übereinstimmung mit zumindest einem Anteil des ersten Schlüsselwertes erzeugt und verwendet, um auf Baumeinträge für die Datenobjektattribute in einem oder mehreren Blattknoten der gestuften Datenstruktur zuzugreifen. Auf einen Baumeintrag für das Datenobjekt wird auch von demselben Satz von einem oder mehreren Blattknoten zugegriffen.

Throttling accesses to flash based memory in a combined storage device

A storage system contains a controller 102, a flash memory 106 and another type of storage device, such as a hard disc drive 108. The flash memory has a life span based on the number of write/erase cycles for each block. The controller estimates the remaining lifespan of the flash memory. Based on the estimate, it determines which data should be written to the flash memory. A limit may be placed on the size of data transfer written to the flash memory. Data transfers over the limit are written to the other storage device without being written to the flash. A limit may be placed on the amount of data pre-fetched from the other storage device during read operations. A proportion of transfers to the system may be written directly to the other storage device and not to the flash memory.

Method of using memory allocation to address hot and cold data

Throttling accesses to flash based memory

PROCEDURE FOR THE STORE MANAGEMENT OF A FLASH OF MEMORY

PROCEDURES AND DEVICE FOR THE USE OF A ONCE OR SEVERAL TIMES OF PROGRAMMABLE MEMORY WITH A FOR LÖSCHUND RE+RECORDABLE MEMORY DEVELOPED HOST DEVICE

ARRAY CONTROLLER, SOLID STATE DISK, AND METHOD FOR CONTROLLING SOLID STATE DISK TO WRITE DATA

Embodiments of the present invention provide an array controller, including a communications interface and a processor. The communications interface is configured to communicate with a solid state disk. The processor is configured to receive information about a logical block sent by the solid state disk, where the information about the logical block includes a size of the logical block and indication information of the logical block, and the logical block includes one or more blocks. The processor is further configured to send multiple write data requests to the solid state disk, where each write data request carries target data, each write data request is used to instruct the solid state disk to write the target data into the logical block indicated by the indication information of the logical block, and a sum of lengths of the target data carried in the multiple write data requests is equal to the size of the logical block. The logical block may be filled after the solid state disk writes ...

ARRAY CONTROLLER, SOLID STATE DISK, AND METHOD FOR CONTROLLING SOLID STATE DISK TO WRITE DATA

Embodiments of the present invention provide an array controller, including a communications interface and a processor. The communications interface is configured to communicate with a solid state disk. The processor is configured to receive information about a logical block sent by the solid state disk, where the information about the logical block includes a size of the logical block and indication information of the logical block, and the logical block includes one or more blocks. The processor is further configured to send multiple write data requests to the solid state disk, where each write data request carries target data, each write data request is used to instruct the solid state disk to write the target data into the logical block indicated by the indication information of the logical block, and a sum of lengths of the target data carried in the multiple write data requests is equal to the size of the logical block. The logical block may be filled after the solid state disk writes ...

METHOD AND APPARATUS FOR MANAGING AN ERASE COUNT BLOCK

Methods and apparatus for managing erase counts in a non-volatile memory system. According to one aspect of the present invention, a method for initializing an erase count block in a system memory of a non-volatile memory system, the non-volatile memory system which includes a non-volatile memory involves allocating a plurality of pages within the system memory that are divided into a plurality of entries. Each entry of the plurality of entries has an associated block in the non-volatile memory. The method also includes identifying usable blocks which are suitable for use in accepting user data, and storing values in each entry which is associated with a usable block. Storing the values in each entry which is associated with a usable block substantially identifies the usable block as being usable. © KIPO & WIPO 2007 ...

MEMORY SYSTEM AND WEAR-LEVELING METHOD USING SAME

The present technology relates to a memory system and a method of operating the same. Provided are a non-volatile memory device and a memory controller for allocating first and second spaces of the non-volatile memory device to a system memory and a storage device, respectively. The memory controller divides the first and second spaces into regions of different sizes, and detects a hot or cold data region in each of the regions. COPYRIGHT KIPO 2018 (AA) Start (BB) End (S410) Define a region (S420) Select the region (S430) Number of operation = Maximum (S440) Detect a hot data region (S450) Number of operation = Minimum (S460) Detect a cold data region (S470) Swap data ...

Apparatus and Method of Wear Leveling for Storage Class Memory

MEMORY SYSTEM

A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest. COPYRIGHT KIPO & WIPO 2010 ...

OPTIMIZING WRITE AND WEAR PERFORMANCE FOR A MEMORY

메모리 시스템에서의 소거 관리

... 컴퓨터 프로세서 하드웨어는 비휘발성 메모리 시스템 내의 저장 셀들의 영역에 저장된 데이터가 유효하지 않은 데이터를 저장하고 있다는 통지를 수신한다. 통지에 응답하여, 컴퓨터 프로세서 하드웨어는 영역을 유효하지 않은 데이터를 저장하는 것으로서 표시한다. 컴퓨터 프로세서 하드웨어는 저장 셀들에 있는 유효하지 않은 데이터를 교체 데이터로 덮어쓰는 것과 연관되는 소거 체류 시간의 크기(즉, 하나 이상의 셀들이 소거된 상태로 설정되는 시간의 양)를 제어한다. 예를 들어, 각자의 저장 셀들을 재프로그램하기 위해, 데이터 관리자는 저장 셀들을 소거하고 이어서 저장 셀들을 교체 데이터로 프로그램해야만 한다. 데이터 관리 로직은 비휘발성 메모리 시스템의 수명을 향상시키기 위해 소거 체류 시간을 임계 시간 값 미만이 되도록 제어할 수 있다.

WEAR LEVELING OF MEMORY DEVICES

Memory management method, memory storage device and memory control circuit unit

Method for data storage

Re-initializing memory arrays

A system for re-initializing a memory array is described. The system includes a processor and a memory array communicatively coupled to the processor. The system also includes a memory manager. The memory manager includes an establish module to establish a reference state for the memory array. The reference state includes a number of target resistance values for the memory array. The memory manager includes a write module to write data to the memory array. The memory manager includes a re-initialize module to re-initialize the memory array to the established reference state.

Data protecting method, and memory controll and memory storage device using the same

A data protecting method applied to a rewritable non-volatile memory module including a plurality of physical blocks is provided. The method includes: when the rewritable non-volatile memory module is powered on, obtaining a power off period from the last power off to the current power on; and, if the power off period is larger than a time threshold, determining if the physical blocks matche a update condition according to block information; executing a update procedure to the physical blocks matching the update condition. The update procedure is configured to read data from a physical block, and rewrite the data to one of the physical blocks. Accordingly, it keeps the data in the physical blocks from being easily lost, and it increases the lifespan of the rewritable non-volatile memory module.

System, method, and computer program product for increasing spare space in memory to extend a lifetime of the memory

A system, method, and computer program product are provided for extending a lifetime of memory. In operation, spare space in memory is increased. Additionally, a lifetime of the memory is extended, as a result of increasing the spare space in the memory.

Method and apparatus for managing an erase count block

Methods and apparatus for managing erase counts in a non-volatile memory system. According to one aspect of the present invention, a method for initializing an erase count block in a system memory of a non-volatile memory system, the non-volatile memory system which includes a non-volatile memory involves allocating a plurality of pages within the system memory that are divided into a plurality of entries. Each entry of the plurality of entries has an associated block in the non-volatile memory. The method also includes identifying usable blocks which are suitable for use in accepting user data, and storing values in each entry which is associated with a usable block. Storing the values in each entry which is associated with a usable block substantially identifies the usable block as being usable.

Hybrid memory management

Methods and apparatus for managing data storage in hybrid memory devices utilizing single level and multi level memory cells. Logical addresses can be distributed between single level and multilevel memory cells based on a frequency of write operations performed. Initial storage of data corresponding to a logical address in memory can be determined by various methods including initially writing all data to single level memory or initially writing all data to multilevel memory. Other methods permit a host to direct logical address writes to single level or multilevel memory cells based on anticipated usage.

Apparatus, system, and method for managing lifetime of a storage device

An apparatus, system, and method are disclosed for managing lifetime for a data storage device. A target module determines a write bandwidth target for a data storage device. An audit module monitors write bandwidth of the data storage device relative to the write bandwidth target. A throttle module adjusts execution of one or more write operations on the data storage device in response to the write bandwidth of the data storage device failing to satisfy the write bandwidth target.

Storage apparatus and method of managing data storage area

To extend endurance and reduce bit cost, a storage apparatus includes a controller and a first storage device and a second storage device having a smaller erase count upper limit than the first storage device. Area conversion information includes correspondence of a first address of a data storage destination and a second address of a data storage area The controller selects an area corresponding to the first address, determines whether a rewrite frequency of the selected area is equal to or larger than a first threshold and, when the rewrite frequency is equal to or larger than the threshold, selects an area of the first storage device, and, when the rewrite frequency is smaller than the threshold, selects an area of the second storage device and maps the address of the selected area to the first address.

Memory controller and methods for enhancing write performance of a flash device

A memory controller and methods for managing efficient writing to a flash memory are presented. Fresh data is written to at least one block of the flash memory. During a space reclamation process, other data, previously written to the flash memory, is relocated to at least one other block of the flash memory, such that the fresh data and the relocated data always are maintained in separate blocks of the flash memory. During writing, an update frequency level is selected for the fresh data from among multiple update frequency levels and the fresh data is written to a block that is associated with the selected update frequency level. During space reclamation, a plurality of blocks, space of which is to be reclaimed, is selected and the valid pages thereof are copied to at least one destination block.

Optimized flash based cache memory

Embodiments of the invention relate to throttling accesses to a flash memory device. The flash memory device is part of a storage system that includes the flash memory device and a second memory device. The throttling is performed by logic that is external to the flash memory device and includes calculating a throttling factor responsive to an estimated remaining lifespan of the flash memory device. It is determined whether the throttling factor exceeds a threshold. Data is written to the flash memory device in response to determining that the throttling factor does not exceed the threshold. Data is written to the second memory device in response to determining that the throttling factor exceeds the threshold.

Apparatus including memory system controllers and related methods

Memory controllers can include a switch and non-volatile memory control circuitry including channel control circuits coupled to the switch. The channel control circuits can coupled to logical units including blocks. Volatile memory and memory management circuitry including local memory can be coupled to the switch. The memory management circuitry can be configured to store health and status information for each of the blocks in a block table in the volatile memory, store a candidate block table that identifies a candidate block for a particular operation based on criteria in the local memory, update the health and status information for a particular block in the block table, compare the updated health and status information for the particular block with the candidate block according to the criteria, and update the candidate block table to identify the particular block in response to the comparison indicating that the particular block better satisfies the criteria.

Limiting activity rates that impact life of a data storage media

A first cumulative data transfer over a first time window from an intermediary module to a data storage media is determined. The intermediary module is coupled between a host interface and the data storage media. An activity rate from the intermediary module to the data storage media is limited for one or more subsequent time windows if the first cumulative activity rate exceeds a threshold value that impacts life of the data storage media. The limitation of the activity rate is removed after the one or more subsequent time windows expire

System and method for data inversion in a storage resource

A method may comprise receiving a page of data to be stored on a storage resource. The method may also comprise determining, for each particular inversion mode of a plurality of inversion modes, the number of bits of the page of data to be inverted to store a representation of the page of data in accordance with the particular inversion mode. The method may additionally comprise determining a selected inversion mode from the plurality of inversion modes for the page of data, the selected inversion mode comprising the inversion mode for which the least number of physical bit transitions are required to store the representation of the page of data in accordance with the selected inversion mode. The method may further comprise storing the representation of the page of data in a data memory in accordance with the inversion mode.

Apparatus, system, and method for managing solid-state storage reliability

A storage controller may be configured to assess the reliability of a solid-state storage medium. The storage controller may be further configured to project, forecast, and/or estimate storage reliability at a future time. The projection may be based on a currently reliability metric of the storage and a reliability model. The portions or sections of the solid-state storage media may be retired in response the projected reliability metric failing to satisfy a reliability threshold. The reliability threshold may be based on data correction and/or reconstruction characteristics. The projected reliability metrics of a plurality of erase blocks of a storage division may be combined, and one or more of the erase blocks may be retired in response to determining that the combined reliability metric projection fails to satisfy the reliability threshold.

System and method for write-life extension of storage resources

An information handling system includes a processor and a storage resource communicatively coupled to the processor. The processor is configured to determine if available overprovisioned storage of the storage resource is less than a threshold overprovisioned storage capacity, establish a new stated capacity for the storage resource in response to a determination that the available overprovisioned storage of the storage resource is less than the threshold overprovisioned storage capacity, and communicate to the processor an indication of the new stated capacity.

Power-supply device and electronic device including the same

A power-supply device and an electronic device including the relate to technology for a data storage device. The electronic device includes a power-supply device and a controller. The power-supply device generates a sudden power loss (SPL) detection signal in a sudden power off (SPO) state by detecting a level of an external power, generates a charging sense signal indicative of a charging capacity of an auxiliary power-supply circuit, divides the charging capacity into a plurality of charging levels, detects a level of the charging capacity, and generates a charging sense signal indicating a charging level of the auxiliary power-supply circuit in response to the detected charging level. The controller stores flushing information in at least one non-volatile memory device when the SPL detection signal is activated, and variably adjust an amount of storage in the non-volatile memory device in response to the charging sense signal.

DATA CACHING FOR FERROELECTRIC MEMORY

Methods, systems, and devices for operating a memory device are described. One method includes caching data of a memory cell at a sense amplifier of a row buffer upon performing a first read of the memory cell; determining to perform at least a second read of the memory cell after performing the first read of the memory cell; and reading the data of the memory cell from the sense amplifier for at least the second read of the memory cell. 1. An apparatus , comprising:a first memory sub-bank and a second memory sub-bank, the first memory sub-bank and the second memory sub-bank each comprising a plurality of memory cells;a first row buffer coupled with the first memory sub-bank and comprising a plurality of sense components configured to cache data associated with the first memory sub-bank;a second row buffer coupled with the second memory sub-bank and comprising a second plurality of sense components configured to cache data associated with the second memory sub-bank; anda bank control circuit configured to cache the data associated with the first memory sub-bank in the first row buffer and cache the data associated with the second memory sub-bank in the second row buffer.2. The apparatus of claim 1 , further comprising:a column decoder coupled with the first memory sub-bank and the second memory sub-bank, the column decoder configured to receive from the bank control circuit a column address of at least one memory cell of the first memory sub-bank or the second memory sub-bank, wherein the bank control circuit is configured to cache the data in the first row buffer or in the second row buffer based at least in part on the column decoder receiving the column address.3. The apparatus of claim 1 , wherein the data cached in the first row buffer or the second row buffer is written to at least one memory cell of the first memory sub-bank or the second memory sub-bank.4. The apparatus of claim 1 , wherein the data cached in the first row buffer or the second row buffer is ...

ELECTRONIC DEVICE

An electronic device includes a semiconductor memory unit. The semiconductor memory unit includes a plurality of first lines extending in a first direction, a plurality of second lines extending in a second direction intersecting the first direction, and a plurality of variable resistance patterns that is positioned at intersections of the first lines and the second lines and disposed between the first lines and the second lines in a vertical direction. Each of the variable resistance patterns has an elongated shape in a plan view and a portion of each of the variable resistance patterns is disposed outside a region in which a corresponding first line and a corresponding second line overlap with each other. 1. An electronic device comprising a semiconductor memory unit , wherein the semiconductor memory unit comprises:a plurality of first lines extending in a first direction;a plurality of second lines extending in a second direction intersecting the first direction; anda plurality of variable resistance patterns positioned at intersections of the first lines and the second lines and disposed between the first lines and the second lines in a direction that is perpendicular to the first and second directions,wherein each of the variable resistance patterns has an elongated shape in a plan view and a portion of each of the variable resistance patterns extends outside a region in which a corresponding first line and a corresponding second line overlap with each other.2. The electronic device according to claim 1 , wherein a direction of a major axis of each of the variable resistance patterns intersects the first and second directions.3. The electronic device according to claim 2 , wherein claim 2 , when a third direction intersects the first and second directions and an angle between the third direction and the first direction is substantially the same as an angle between the third direction and the second direction claim 2 , the direction of the major axis is ...

Storage device capable of managing jobs without intervention of a processor

A storage device includes a nonvolatile memory and a controller. The controller includes a job manager circuit and a processor. The job manager circuit manages a first-type job associated with the nonvolatile memory, and the processor processes a second-type job associated with the nonvolatile memory. The job manager circuit manages the first-type job without intervention of the processor. The processor provides a management command to the job manager circuit in response to a notification received from the job manager circuit, such that the second-type job is processed.

Write broadcast operations associated with a memory device

Methods, systems, and devices related to write broadcast operations associated with a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may enable write broadcast operations. A write broadcast may occur from one or more signal development components or from one or more multiplexers to multiple locations of the memory array.

WEAR LEVELING IN A MEMORY SYSTEM

Embodiments are disclosed for replacing one or more pages of a memory to level wear on the memory. In one embodiment, a system includes a page fault handling function and a memory address mapping function. Upon receipt of a page fault, the page fault handling function maps an evicted virtual memory address to a stressed page and maps a stressed virtual memory address to a free page using the memory address mapping function. 1an operating system having a page fault handling function; anda memory address mapping memory function, wherein upon receipt of a page fault, the page fault handling function:maps an unmapped virtual memory address to a stressed page of a memory; and maps a stressed virtual memory address to a free page of the memory using the memory address mapping function, and wherein the stressed page is determined based on one or more durability parameters, the durability parameters including an error correction parameter representing a frequency of detected, corrected errors in each of the pages of memory.. A device comprising: This application is a continuation of U.S. patent application Ser. No. 14/370,013 filed Jun. 30, 2014, which is a U.S. National Phase filing under 35 U.S.C. 371 of International Application Number PCT/US2012/072219 filed Dec. 29, 2012, published as WO 2013/102163 on Jul. 4, 2013, and which claims the benefit of 61/582,142 filed on Dec. 30, 2011, the disclosures of which are incorporated herein in their entirety by reference.Memory devices used in different computing devices (e.g., computers, smart phones, etc.) include short-latency storage devices (e.g., random access memory (RAM)) and long-latency storage devices (e.g., hard disk drives). Latency relates to the cycle time of a processor accessing the memory device. Short-latency storage devices can be used to store frequently-used software applications or computer programs (such as operating system functions) and their associated temporary data structures. Further, short-latency ...

Hybrid drive caching in a backup system with ssd deletion management

Systems and methods can implement one or more intelligent caching algorithms that reduce wear on the SSD and/or to improve caching performance. Such algorithms can improve storage utilization and I/O efficiency by taking into account the write-wearing limitations of the SSD. Accordingly, the systems and methods can cache to the SSD while avoiding writing too frequently to the SSD to increase or attempt to increase the lifespan of the SSD. The systems and methods may, for instance, write data to the SSD once that data has been read from the hard disk or memory multiple times to avoid or attempt to avoid writing data that has been read only once. The systems and methods may also write large chunks of data to the SSD at once instead of a single unit of data at a time. Further, the systems and methods can write to the SSD in a circular fashion.

METHOD AND APPARATUS FOR MAPPING A LOGICAL ADDRESS BETWEEN MEMORIES OF A STORAGE DRIVE BASED ON WRITE FREQUENCY RANKINGS

A storage drive including a first and second memories and a controller. The second memory has a write cycle lifetime that is less than a write cycle lifetime of the first memory. Each of the first and second memories includes solid-state memory. The controller: determines a write frequency for a first logical address; and based on the write frequency, determines a write frequency ranking for the first logical address. The write frequency ranking is based on a weighted time-decay average of write counts or an average of elapsed times of write cycles. The controller also: determines whether the write frequency ranking is greater than a lowest write frequency ranking of logical addresses of the first memory; and if the write frequency ranking of the first logical address is greater, maps the logical address with the lowest write frequency ranking in the first memory to the second memory.

LIMITING ACCESS OPERATIONS IN A DATA STORAGE DEVICE

A hybrid data storage device disclosed herein includes a main data store, one or more data storage caches, and a data storage cache management sub-system. The hybrid data storage device is configured to limit write operations on the one or more data storage caches to less than an endurance value for the data storage cache. In one implementation, the data storage cache management sub-system limits or denies requests for promotion of data from the main data store to the one or more data storage caches. In another implementation, the data storage cache management sub-system limits garbage collection operations on the data storage cache. 1. A method comprising:dividing a remaining lifetime of a data storage cache into a series of time periods;receiving a write request from a storage controller to write one or more clusters to the data storage cache during a first time period in the series of time periods;determining a maximum number of write operations allowable on the data storage cache during the first time period; anddeclining the write request if allowing the write request would exceed the maximum number of write operations allowable on the data storage cache during the first time period.2. The method of claim 1 , further comprising allowing the write request if allowing the write request would not exceed the maximum number of write operations permitted on the storage cache during the first time period.3. The method of claim 1 , wherein the determining operation comprises dividing a number of remaining allowable write operations over the remaining lifetime of the storage cache by a number of periods remaining in the series of time periods.4. The method of claim 3 , wherein the number of remaining allowable write operations over the remaining lifetime of the storage cache is determined by the difference between an expected lifetime write operations endurance of the storage device minus a number of write operations already performed on the storage device over the life ...

Signal development caching in a memory device

Methods, systems, and devices related to signal development caching in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). In various examples, accessing the memory device may include accessing information from the signal development cache, or the memory array, or both, based on various mappings or operations of the memory device.

METHOD AND APPARATUS FOR TRANSFERRING BINARY IMAGE INTO MEMORY DEVICE

There is provided a method of transferring a binary image into a memory device having a memory controller for performing conversion between physical addresses and logical addresses of storage areas. The binary image is transferred into the memory device such that areas included in the binary image and having no valid data become free areas in storage areas of the memory device, the free areas to which physical addresses and logical addresses are not associated. 1. A method of transferring a binary image into a memory device having a memory controller for performing conversion between physical addresses and logical addresses of storage areas ,wherein the binary image is transferred into the memory device such that areas included in the binary image and having no valid data become free areas in storage areas of the memory device, the free areas to which physical addresses and logical addresses are not associated.2. The method according to claim 1 ,wherein the areas included in the binary image and having no valid data are determined, andwherein transferring of the binary image is performed, without writing the data of the areas determined as having no valid data, in the memory device.3. The method according to claim 1 , wherein transferring of the binary image is performed by generating image files of a plurality of areas of the binary image except for the areas having no valid data claim 1 , and writing the image files of the plurality of areas in corresponding storage areas of the memory device.4. The method according to claim 1 , wherein transferring of the binary image is performed by setting deletable dummy files in the areas included in the binary image and having no valid data claim 1 , and writing the binary image including the dummy files in the memory device claim 1 , and deleting the dummy files from the memory device.5. The method according to claim 1 , wherein transferring of the binary image is performed by generating a deletion-area designation file ...

CONTROLLING WEAR AMONG FLASH MEMORY DEVICES BASED ON REMAINING WARRANTY

A method includes identifying a product warranty for each of a plurality of flash memory devices within a system, wherein the product warranty includes a maximum number of writes and a maximum age, and tracking the number of writes made to each flash memory device and the age of each flash memory device. The method further includes determining, for each flash memory device, a number of pro rata writes remaining in the product warranty, which is determined as a number of writes remaining until the flash memory device reaches the maximum number of writes identified in the product warranty divided by an amount of time remaining until the flash memory reaches the maximum age identified in the product warranty. The method then causes data to be written to the flash memory device having the greatest number of pro rata writes remaining in the product warranty. 1. A method , comprising:identifying a product warranty for each of a plurality of flash memory devices within a system, wherein the product warranty includes a maximum number of writes and a maximum age;tracking the number of writes made to each flash memory device and the age of each flash memory device;determining, for each flash memory device, a number of pro rata writes remaining in the product warranty, wherein the number of pro rata writes remaining in the product warranty is determined as a number of writes remaining until the flash memory device reaches the maximum number of writes identified in the product warranty divided by an amount of time remaining until the flash memory reaches the maximum age identified in the product warranty; andcausing data to be written to the flash memory device having the greatest number of pro rata writes remaining in the product warranty.2. The method of claim 1 , further comprising:identifying one of the flash memory devices having the least amount of time remaining until the flash memory reaches the product age identified in the product warranty; andincreasing a rate of ...

METHODS AND SYSTEMS FOR USING PREDICTIVE CACHE STATISTICS IN A STORAGE SYSTEM

Method and systems for a storage system are provided. Simulated cache blocks of a cache system are tracked using cache metadata while performing a workload having a plurality of storage operations. The cache metadata is segmented, each segment corresponding to a cache size. Predictive statistics are determined for each cache size using a corresponding segment of the cache metadata. The predictive statistics are used to determine an amount of data that is written for each cache size within certain duration. The process then determines if each cache size provides an endurance level after executing a certain number of write operations, where the endurance level indicates a desired life-cycle for each cache size. 1. A machine implemented method , comprising:tracking simulated cache blocks of a cache system using cache metadata while performing a workload having a plurality of storage operations, where the cache metadata is segmented, each segment corresponding to a cache size;determining predictive statistics for each cache size using a corresponding segment of the cache metadata;using the predictive statistics to determine an amount of data that is written for each cache size within a certain duration; anddetermining an endurance level that each cache size provides after executing a certain number of write operations, where the endurance level indicates a desired life-cycle for each cache size.2. The method of claim 1 , wherein the cache metadata uses a segment identifier for tracking each segment of the cache metadata.3. The method of claim 1 , wherein a storage controller tracks the simulated cache blocks of the cache system using the cache metadata.4. The method of claim 3 , wherein the simulated cache blocks of the cache system are tracked using a least recently used cache tracking mechanism.5. The method of claim 3 , wherein the simulated cache blocks of the cache system are tracked using a most recently used cache tracking mechanism.6. The method of claim 1 , ...

Content-addressable memory for signal development caching in a memory device

Methods, systems, and devices related to content-addressable memory for signal development caching are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may also include storage, such as a content-addressable memory, configured to store a mapping between addresses of the signal development cache and addresses of the memory array. In various examples, accessing the memory device may include determining and storing a mapping between addresses of the signal development cache and addresses of the memory array, or determining whether to access the signal development cache or the memory array based on such a mapping.

ARRANGEMENTS FOR STORING MORE DATA IN FASTER MEMORY WHEN USING A HIERARCHICAL MEMORY STRUCTURE

Data employed in computations is processed so that during computations more of the data can be fit into or maintained in a smaller but higher speed memory than an original source of the data. More specifically, a sensitivity value is determined for various items of the data which reflect the number of bits in the data items that are not garbage bits, and only information in the data items that are indicated by the sensitivity value to not be garbage bits are necessarily effectively retained. At least the information that is not garbage bits and the corresponding associated sensitivity are packed together. The results of computations that are performed using the data items as at least one of the operands for the computation are associated with a sensitivity that is derived from the individual sensitivities of the operands used in the computation. 1. A system for reducing data movement from at least one sending memory component to at least one receiving memory component in a computer system , the former said system using information or knowledge about the structure of an algorithm , operations to be executed with the moved data , variables or subsets or groups of variables in an algorithm , or other forms of contextual information , for reducing the number of bits moved from the at least one sending memory component to the at least one receiving memory component.2. A method for reducing data movement from at least one sending memory component to at least one receiving memory component in a computer system , the method using information or knowledge about the structure of an algorithm , operations to be executed with the moved data , variables or subsets or groups of variables in an algorithm , or other forms of contextual information , for reducing the number of bits moved from the at least one sending memory component to the at least one receiving memory component. This application is a Continuation of co-pending U.S. patent application Ser. No. 15/249,627, now ...

CONTROLLER AND OPERATION METHOD THEREOF

A controller for controlling a memory device including memory dies includes: a processor suitable for checking whether or not any of the memory dies in the memory device is idle after transferring a write command to the memory device, and when there is an idle memory die, performing a garbage collection read operation of the idle memory die; and a garbage collection (GC) data region suitable for storing a valid data of a victim block, which is read through the garbage collection read operation; and wherein the processor transfers the valid data to the memory device based on an amount of valid data stored in the GC data region and controlling the memory device to perform a garbage collection write operation of programming the valid data in a target block. 1. A controller for controlling a memory device including memory dies , the controller comprising:a processor suitable for checking whether or not any of the memory dies in the memory device is idle after transferring a write command to the memory device, and when there is an idle memory die, performing a garbage collection read operation of the idle memory die; anda garbage collection (GC) data region suitable for storing valid data of a victim block, which is read through the garbage collection read operation; andwherein the processor transfers the valid data to the memory device based on an amount of valid data stored in the GC data region and controlling the memory device to perform a garbage collection write operation of programming the valid data in a target block.2. The controller of claim 1 , further comprising:a GC address region suitable for storing a valid data address corresponding to a region of a victim block of each of the memory dies that stores valid data,wherein the processor controls a garbage collection read operation with reference to the GC address region.3. The controller of claim 2 , wherein the processor decides the victim block claim 2 , among memory blocks claim 2 , based on the amount of ...

SCRUBBER DRIVEN WEAR LEVELING IN OUT OF PLACE MEDIA TRANSLATION

A process for wear-leveling in a memory subsystem where references to invalidated chunks and a write count for each of the invalidated chunks of a memory subsystem are received by a wear-leveling manager. The wear-leveling manager orders the received references to the invalidated chunks of the memory subsystem in a tracking structure based on the write count of each of the invalidated chunks, and provides a reference to at least one of the invalidated chunks based on the ordering from the tracking structure to a write scheduler to service a write request, wherein the memory subsystem is wear-leveled by biasing the order of the invalidated chunks to prioritize low write count chunks. 1. A method comprising:categorizing chunks of memory by codeword type, wherein codeword type indicates a sequence of partitions spanned by a codeword and each chunk includes one or more codewords of a same codeword type;organizing the categorized chunks into a cartridge, which is a set of chunks ordered by codeword type to avoid partition write collision between the chunks in the cartridge when the cartridge is utilized for a write;receiving a write request; andfulfilling the write request using the cartridge.2. The method of claim 1 , wherein categorizing chunks of memory includes determining a codeword type by converting a physical address of each chunk of memory to a starting partition and page offset.3. The method of claim 1 , wherein organizing the categorized chunks into a cartridge includes tracking an order of the chunks of memory in a queue.4. The method of claim 1 , further comprising:receiving references to invalidated chunks and a write count for each of the invalidated chunks of a memory subsystem; andordering the received references to the invalidated chunks of the memory subsystem in a tracking structure based on the write count of each of the invalidated chunks, wherein the chunks of memory are wear-leveled by biasing the order of the invalidated chunks to prioritize low ...

APPARATUS AND METHOD FOR PROGRAMMING NON-VOLATILE MEMORY USING A MULTI-CELL STORAGE CELL GROUP

Provided are an apparatus, method, and system for programming a multi-cell storage cell group. A non-volatile memory has storage cells. Each storage cell is programmed with information using a plurality of threshold voltage levels and each storage cell is programmed from bits from a plurality of pages. A memory controller is configured to program the storage cells and to organize the storage cells in the non-volatile memory into storage cell groups. Each storage cell group stores a number of bits of information and each of the storage cells in each of the storage cell groups is programmed with the plurality of threshold voltage levels. The memory controller selects bits from the pages to write for one storage cell group and determines at least one threshold voltage level to use for each of the storage cells in the storage cell group to program the selected bits in the storage cell group. 1. An apparatus , comprising:a non-volatile memory having storage cells, wherein each storage cell is programmed with information using a plurality of threshold voltage levels, and wherein each storage cell is programmed from bits from a plurality of pages; and organize the storage cells in the non-volatile memory into storage cell groups, wherein each storage cell group stores a number of bits of information, wherein each of the storage cells in each of the storage cell groups is programmed with the plurality of threshold voltage levels;', 'select bits from the pages to write for one storage cell group; and', 'determine at least one threshold voltage level to use for each of the storage cells in the storage cell group to program the selected bits in the storage cell group., 'a memory controller configured to program the storage cells and to2. The apparatus of claim 1 , wherein the selected bits from the pages to write comprises the number of bits of information stored in each storage cell group claim 1 , wherein all of the plurality of threshold voltage levels are used to program ...

Method of wear leveling for data storage device

A method of wear leveling for a data storage device is provided. The data storage device includes a non-volatile memory having a plurality of blocks. A portion of the blocks not having any valid data are defined as spare blocks, and the spare blocks are associated with a spare pool. The method includes the steps of: maintaining a management table recording a plurality of physical block numbers and a plurality of block statuses corresponding to the blocks; selecting a first spare block having a first smallest physical block number as a current temporary block; receiving a write command from a host; determining whether data in the write command shall be written into the current temporary block; if false, selecting a second spare block having a second smallest physical block number as a next temporary block; and writing the data into the next temporary block.

Apparatus and Method of Wear Leveling for Storage Class Memory

A method and apparatus of wear leveling control for storage class memory are disclosed. According to the present invention, whether current data to be written to a nonvolatile memory corresponds to a write cache hit is determined. If the current data to be written corresponds to the write cache hit, the current data are written to a write cache as well as to a designated location in the nonvolatile memory different from a destined location in the nonvolatile memory. If the current data to be written corresponds to a write cache miss, the current data are written to the destined location in the nonvolatile memory. If the current data to be written corresponds to the write cache miss and the write cache is not full, the current data is also written to the write cache. In another embodiment, the wear leveling control technique also includes address rotation process to achieve long-term wear leveling as well. 1. A method of wear leveling control for storage class memory based on nonvolatile memory using a write cache , the method comprising:dividing the nonvolatile memory into memory groups; andmapping an input group address corresponding to a logic address of one memory group in the nonvolatile memory to an output group address corresponding to a physical group address of one memory group in the nonvolatile memory, wherein the input group address belongs to a first set of N addresses and the output group address belongs to a second set of M addresses, M and N are positive integers and M>N, and wherein at least one input address is mapped to two different output addresses at two different time instances, wherein N memory groups are used as data groups and one or more memory groups are used as redundant groups, and M is equal to a sum of N and number of the redundant groups, and wherein the redundant groups are divided into one or more logging groups and a shadow group in unused memory space of the nonvolatile memory and the unused memory space of the nonvolatile memory ...

Semiconductor memory device and control method therefor

To prolong the lifetime of a semiconductor memory device without performing complicated control. A semiconductor memory device according to one embodiment is equipped with a bank A and a bank B operable complementarily to each other, and a bank selection circuit which selects either one of the banks A and B. The bank selection circuit alternately switches the bank to be selected, each time an erase command to instruct erasing of data in either one of the banks A and B is issued.

SAVING POSITION OF A WEAR LEVEL ROTATION

In one example in accordance with the present disclosure, a system may include a wear level handler to start a current rotation of a wear level algorithm through a plurality of cache line addresses in a region of memory and a location storer to store a rotation count of the rotation. The system may also include a data mover to move a cache line from the selected cache line address to a gap cache line address corresponding to the additional cache line address and a metadata setter to set a metadata of the gap cache line address to a value corresponding to the current rotation. The system may also include a current position determiner to determine, based on the value of at least one metadata and the rotation count, a current position of the current rotation after a power loss event. 1. A system comprising:a wear level handler to start a current rotation of a wear level algorithm through a plurality of cache line addresses in a region of memory;a location storer to store a rotation count corresponding to a cache line address belonging to the plurality;a data mover to move a cache line from the selected cache line address to a gap cache line address corresponding to the additional cache line address,a metadata setter to set a metadata of the gap cache line address to a value corresponding to the current rotation, wherein the first cache line address becomes the current gap cache line address after the data has been copied and the metadata has been set; anda current position determiner to determine, based on the value of at least one metadata and the rotation count, a current position of the current rotation after a power loss event.2. The system of claim 1 , wherein the wear level algorithm alternates between an even rotation and an odd rotation claim 1 , the even rotation characterized by a first value of the metadata and the odd rotation characterized by a second value of the metadata claim 1 , the system comprising: set the value of the metadata to the first value if ...

Codeword rotation for zone grouping of media codewords

Methods, systems, and devices for codeword rotation for zone grouping of media codewords are described. A value of a first pointer may be configured to correspond to a first memory address within a region of memory and a value of a second pointer may be configured to correspond to a second memory address within the region of memory. The method may include monitoring access commands for performing access operations within the region of memory, where the plurality of access command may be associated with requested addresses within the region of memory. The method may include updating the value of the second pointer bases on a quantity of the commands that are monitored satisfying a threshold and executing the plurality of commands on locations within the region of memory. The locations may be based on the requested address, the value of the first pointer, and the value of the second pointer.

Logical to physical table fragments

Logical to physical tables each including logical to physical address translations for first logical addresses can be stored. Logical to physical table fragments each including logical to physical address translations for second logical address can be stored. A first level index can be stored. The first level index can include a physical table address of a respective one of the logical to physical tables for each of the first logical addresses and a respective pointer to a second level index for each of the second logical addresses. The second level index can be stored and can include a physical fragment address of a respective logical to physical table fragment for each of the second logical addresses.

METHOD FOR ACCESSING FLASH MEMORY AND ASSOCIATED MEMORY CONTROLLER AND ELECTRONIC DEVICE

A method for accessing a flash memory includes: sending a write command and a set of corresponding data, wherein the data is for updating a part of contents of a first physical page, corresponding to a logical page, of a physical block in a flash memory; searching the physical block according to the write command for a second physical page that is allowed to be written; writing the data to the second physical page; and recording that the second physical page corresponds to the logical page. 1. A method for accessing a flash memory , comprising:sending a write command and a set of corresponding data, wherein the data is for updating a part of contents of a first physical page, corresponding to a logical page, of a physical block in a flash memory;searching the physical block according to the write command for a second physical page that is allowed to be written;writing the data to the second physical page; andrecording that the second page corresponds to the logical page.2. The method according to claim 1 , wherein the step of searching the physical block according to the write command for the second physical page that is allowed to be written comprises:searching the physical block for an empty physical page having a smallest physical page address to serve as the second physical page.3. The method according to claim 1 , wherein the step of writing the data to the second physical page comprises:reading contents that do not need to be updated in the first physical page, and jointly writing the read contents and the data to the second physical page.4. The method according to claim 1 , further comprising:when the physical block does not comprise the physical page that is allowed to be written, writing the data and at least a part of data read from the physical block to another physical page, and erasing contents of the physical block.5. The method according to claim 1 , further comprising:updating a logical-physical page mapping table to indicate that the logical page ...

METHOD AND APPARATUS FOR PROVIDING WEAR LEVELING

Exemplary embodiments provide wear spreading among die regions (i.e., one or more circuits) in an integrated circuit or among dies by using operating condition data in addition to or instead of environmental data such as temperature data, from each of a plurality of die regions. Control logic produces a cumulative amount of time each of the plurality of die regions has spent at an operating condition based on operating condition data wherein the operating condition data is based on at least one of the following operating characteristics: frequency of operation of the plurality of die regions, an operating voltage of the plurality of die regions, an activity level of the plurality of die regions, a timing margin of the plurality of die regions, and a number of detected faults of the plurality of die regions. The method and apparatus spreads wear among the plurality of same type of die regions by controlling task execution among the plurality of die regions using the die wear-out data. 1. A method for providing wear spreading among a plurality of die regions in an integrated circuit , the method comprising:producing, by control logic, die region wear-out data representing a cumulative amount of time each of the plurality of die regions has spent at an operating condition based on operating condition data from each of the plurality of die regions, wherein the operating condition data is based on at least one of the following operating characteristics: frequency of operation of the plurality of die regions, an operating voltage of the plurality of die regions, an activity level of the plurality of die regions, a timing margin of the plurality of die regions, and a number of detected faults of the plurality of die regions; andspreading, by the control logic, wear among the plurality of die regions by controlling task execution among the plurality of die regions using the die region wear-out data.2. The method of claim 1 , further comprising:storing, in persistent memory, ...

Writing an address conversion table for nonvolatile memory wear leveling

An apparatus configured to write, in a non-volatile memory, an address conversion table for wear leveling of the non-volatile memory includes a holding unit configured to hold a first address conversion table for wear leveling of a first block of the non-volatile memory, a second address conversion table for wear leveling of a second block other than the first block of the non-volatile memory, and a third address conversion table for wear leveling of a third block other than the first block of the non-volatile memory; and a writing unit configured to write, in the first block, a replication of the second address conversion table in addition to one replication of the first address conversion table and to write, in the third block, another replication of the first address conversion table in addition to a replication of the third address conversion table.

NON-VOLATILE MEMORY SYSTEM USING A PLURALITY OF MAPPING UNITS AND OPERATING METHOD THEREOF

A method of operating a non-volatile memory system, the method comprising: receiving an access request from a host; generating internal requests by processing the access request by a first central processing unit (CPU) according to a first mapping unit having a first size; and accessing a memory by processing the internal requests by a second CPU according to a second mapping unit having a second size; wherein the first size is different from the second size. 1. A method of operating a non-volatile memory system , the method comprising:receiving an access request from a host;generating internal requests by processing the access request by a first central processing unit (CPU) according to a first mapping unit having a first size; andaccessing a memory by processing the internal requests by a second CPU according to a second mapping unit having a second size;wherein the first size is different from the second size.2. The method of claim 1 , wherein:the second CPU is one of a plurality of second CPUs; andthe processing of the internal requests comprises processing the internal requests by the second CPUs according to the second mapping unit.3. The method of claim 2 , wherein:the first CPU is one of a plurality of first CPUs; andthe processing of the access request by the first CPUs according to the first mapping unit.4. The method of claim 1 , wherein:a data processing speed of the first CPU is faster than that of the second CPU.5. The method of claim 1 , wherein:the first CPU is one of at least one first CPU;the second CPU is one of at least one second CPU; andthe first size is larger than the second size when a number of the at least one first CPU is smaller than a number of the at least one of second CPU.6. The method of claim 1 , wherein the generating of the internal requests comprises:dividing the access request into a plurality of internal requests; andfor each of the internal requests, generating a first logical address corresponding to the internal request; ...

RRAM-BASED MONOTONIC COUNTER

A circuit includes a memory array having a plurality of memory cells; a control logic circuit, coupled to the memory array, and configured to use a first voltage signal to cause a first memory cell of the plurality of memory cells to transition from a first resistance state to a second resistance state; a counter circuit, coupled to the control logic circuit, and configured to increment a count by one in response to the first memory cell's transition from the first to the second resistance state; and an encryption circuit, coupled to the counter circuit, configured to generate an encrypted value using an updated count provided by the counter circuit. 1. A circuit , comprising:a memory array having a plurality of memory cells;a control logic circuit, coupled to the memory array, and configured to use a first voltage signal to cause a first memory cell of the plurality of memory cells to transition from a first resistance state to a second resistance state;a counter circuit, coupled to the control logic circuit, and configured to increment a count by one in response to the first memory cell's transition from the first to the second resistance state; andan encryption circuit, coupled to the counter circuit, configured to generate an encrypted value using an updated count provided by the counter circuit.2. The circuit of claim 1 , wherein the plurality of memory cells each comprises a resistive random access memory (RRAM) cell.3. The circuit of claim 1 , wherein the first memory cell presents a substantially lower resistance value when the first memory cell transitions from the first resistance state to the second resistance state.4. The circuit of claim 1 , wherein:the control logic circuit is further configured to use a second voltage signal to cause the first memory cell to transition from the second resistance state to a third resistance state;the counter circuit is further configured to again increment the count by one in response to the first memory cell's ...

Memory system with memory region read counts and a memory group read count and operating method thereof

A memory system includes a storage medium including a memory region group having a plurality of memory regions; a memory configured to store a plurality of region read counts respectively corresponding to the plurality of memory regions and a group read count corresponding to the memory region group; a count management circuit configured to, when a first memory region among the plurality of memory regions is read-accessed, based on a first region read count corresponding to the first memory region among the plurality of region read counts, increase the group read count and reduce remaining region read counts other than the first region read count among the plurality of region read counts; and a reliability management circuit configured to perform a reliability management operation for the memory region group, based on the group read count.

Smart dynamic wear balancing between memory pools

A memory system or flash card may include a dynamic system-level process for the management of blocks in the different memory pools. There may be spare blocks available to the pools that are over provisioned to the pool which increases the efficiency of data compaction and helps reduce the average hot count for that pool and compensate for the grown defects. The block wear and grown defects in each memory pool may be tracked so that remaining spare blocks can be re-allocated.

METHOD AND APPARATUS UTILIZING NON-UNIFORM HASH FUNCTIONS FOR PLACING RECORDS IN NON-UNIFORM ACCESS MEMORY

Method and apparatus for storing records in non-uniform access memory. In various embodiments, the placement of records is localized in one or more regions of the memory. This can be accomplished utilizing different ordered lists of hash functions to preferentially map records to different regions of the memory to achieve one or more performance characteristics or to account for differences in the underlying memory technologies. For example, one ordered list of hash functions may localize the data for more rapid access. Another list of hash functions may localize the data that is expected to have a relatively short lifetime. Localizing such data may significantly improve the erasure performance and/or memory lifetime, e.g., by concentrating the obsolete data elements in one location. Thus, the two or more lists of ordered hash functions may improve one or more of access latency, memory lifetime, and/or operation rate. 1. A method of storing index records in a non-uniform access memory , each record comprising a record key and wherein multiple hash functions are used to map records to logical buckets for translation to physical locations in the non-uniform access memory , the method comprising:applying a first ordered list of hash functions to a record key of a first type of record to preferentially map the first record type to a first region of the memory; andapplying a second ordered list of hash functions to a record key of a second type of record to preferentially map the second record type to a second region of the memory not limited to the first region.2. The method of claim 1 , including:maintaining a bucket translation table for mapping logical bucket identifiers to physical bucket locations of the memory, wherein the logical bucket identifiers are generated by the applying step and the table comprises a mapping of logical bucket identifier to physical bucket location where the associated record is stored in the memory.3. The method of claim 1 , wherein:the ...

DYNAMIC ANNEAL CHARACTERISTICS FOR ANNEALING NON-VOLATILE MEMORY

Apparatuses, systems, methods, and computer program products are disclosed for annealing non-volatile memory. A controller identifies one or more life cycle characteristics of a non-volatile storage element. The controller selects an anneal duration and an anneal temperature for annealing the non-volatile storage element. The anneal duration and the anneal temperature are based on the one or more life cycle characteristics. The controller anneals the non-volatile storage element using the selected anneal duration and anneal temperature. 1. An apparatus comprising: identify one or more life cycle characteristics of a non-volatile storage element;', 'select, based on the one or more life cycle characteristics, an anneal duration and an anneal temperature for annealing the non-volatile storage element; and', 'anneal the non-volatile storage element using the selected anneal duration and anneal temperature., 'a controller configured to,'}2. The apparatus of claim 1 , wherein selecting an anneal duration and an anneal temperature comprises determining whether to perform one of a partial anneal and a full anneal for the non-volatile storage element.3. The apparatus of claim 1 , wherein the controller is further configured to perform a garbage collection operation that moves valid data off of the non-volatile storage element in response to determining that a time remaining before annealing the non-volatile storage element satisfies a threshold claim 1 , the threshold based on a time to move remaining valid data off of the non-volatile storage element.4. The apparatus of claim 1 , wherein the controller is further configured to delay annealing the non-volatile storage element in response to determining that an endurance gain for annealing the non-volatile storage element does not exceed write amplification caused by moving valid data off of the non-volatile storage element.5. The apparatus of claim 1 , wherein the controller comprises a hardware controller for a storage ...

MEMORY SYSTEM AND METHOD FOR CONTROLLING NONVOLATILE MEMORY

According to one embodiment, when receiving a write request to designate a first block number and a first logical address from a host, a memory system determines a first location in a first block having the first block number, to which data from the host is to be written, and writes the data from the host to the first location of the first block. The memory system updates a first address translation table managing mapping between logical addresses and in-block physical addresses of the first block, and maps a first in-block physical address indicative of the first location to the first logical address. 1. A memory system connectable to a host , comprising:a nonvolatile memory including a plurality of blocks each including a plurality of pages; anda controller electrically connected to the nonvolatile memory, the controller being configured to, determine a first location in a first block corresponding to the first block number,', 'write data to the first location in the first block, the data being associated with the first logical address, and', 'update a first table such that a first in-block physical address corresponding to the first location is mapped to the first logical address, the first table mapping between logical addresses and in-block physical addresses of the first block but not mapping between the logical addresses and a physical address of the first block., 'in response to receiving a write request from the host, the write request designating a first block number and a first logical address,'}2. The memory system of claim 1 , wherein the controller is further configured to claim 1 , acquire the first in-block physical address by referring to the first table, and', 'read data associated with the first logical address from the nonvolatile memory, based on the first block number and the acquired first in-block physical address., 'in response to receiving a read request from the host, the read request designating the first block number and the first ...

Delaying Hot Block Garbage Collection with Adaptation

Memory systems may include a memory storage, and a controller suitable for measuring a write amplification (WA) value of a first, current window, comparing the WA value for the first window with a previous WA value for a previous window, and calculating and setting a value of a ratio threshold based on the comparison of the WA value for the current window threshold to the WA value of the previous window threshold. 1. A memory system , comprising:a memory storage, and measuring a write amplification (WA) value of a first, current window;', 'comparing the WA value for the first window with a previous WA value for a previous window; and', 'calculating and setting a value of a ratio threshold based on the comparison of the WA value for the current window threshold to the WA value of the previous window threshold., 'a controller suitable for2. The memory system of claim 1 , wherein the calculating includes selecting a direction of an adjustment to the value of the ratio threshold.3. The memory system of claim 1 , wherein the ratio threshold comprises a threshold against which a ratio of a number of valid pages in a second garbage collection (GC) candidate block to a number of valid pages in a first GC block candidate is compared.4. The memory system of claim 1 , wherein the calculating includes adjusting the value of the ratio threshold based on a predetermined proportionality constant.5. The memory system of claim 1 , wherein the first current window and the previous window are the most current windows.6. The memory system of claim 1 , wherein the controller is suitable for setting the value of the ratio threshold to be above a ratio threshold lower limit value to prevent the ratio threshold value from becoming too small.7. A method claim 1 , comprising:measuring, with a controller, a write amplification (WA) value of a first, current window;comparing, with the controller, the WA value for the first window with a previous WA value for a previous window; andcalculating ...

METHODS AND SYSTEMS FOR THROTTLING WRITES TO A CACHING DEVICE IN RESPONSE TO READ MISSES

A storage device includes a flash memory-based cache for a hard disk-based storage device and a controller that is configured to limit the rate of cache updates through a variety of mechanisms, including determinations that the data is not likely to be read back from the storage device within a time period that justifies its storage in the cache, compressing data prior to its storage in the cache, precluding storage of sequentially-accessed data in the cache, and/or throttling storage of data to the cache within predetermined write periods and/or according to user instruction. 1. A method for throttling cache updates in a storage system having a caching device and a storage device , the method comprising: (i) if a number of writes to the caching device for the write period is less than or equal to the threshold number of permitted writes, reading the requested data from the storage device and storing the requested data in the caching device; otherwise,', '(ii) if the number of writes to the caching device for the write period is greater than the threshold number of permitted writes for the write period, reading the requested data from the storage device without storing the requested data in the caching device., 'for each of a plurality of write periods of the storage system, each of the write periods having an associated threshold number of permitted writes to the caching device, receiving a request to read data that is stored on the storage system, and, upon determining that the requested data is stored on the storage device, but not on the caching device, then2. The method of claim 1 , wherein the threshold number of permitted writes corresponding to each of the write periods is a fixed value.3. The method of claim 1 , wherein the threshold number of permitted writes corresponding to each of the write periods is updated periodically.4. The method of claim 1 , wherein the threshold number of permitted writes corresponding to each of the write periods is determined ...

REDUCING WRITE AMPLIFICATION IN SOLID-STATE DRIVES BY SEPARATING ALLOCATION OF RELOCATE WRITES FROM USER WRITES

A computer program product, according to one embodiment, includes a computer readable storage medium having program instructions embodied therewith. The computer readable storage medium is not a transitory signal per se. Moreover, the program instructions are readable and/or executable by a processor to cause the processor to perform a method which includes: maintaining a first open logical erase block for user writes, and a second open logical erase block for relocate writes. A first data stream having the user writes is received, and transferred to the first open logical erase block. A second data stream having the relocate writes is also received, and transferred to the second open logical erase block. Furthermore, a third data stream is received, and is mixed with the first, second, and/or another data stream in response to determining that an open logical erase block is not available for assignment to the third data stream. 1. A computer program product comprising a computer readable storage medium having program instructions embodied therewith , wherein the computer readable storage medium is not a transitory signal per se , the program instructions readable and/or executable by a processor to cause the processor to perform a method comprising:maintaining, by the processor, a first open logical erase block for user writes;maintaining, by the processor, a second open logical erase block for relocate writes, wherein the first and second open logical erase blocks are different logical erase blocks;receiving, by the processor, a first data stream having the user writes;transferring, by the processor, the first data stream to the first open logical erase block;receiving, by the processor, a second data stream having the relocate writes;transferring, by the processor, the second data stream to the second open logical erase block;receiving, by the processor, a third data stream; andmixing, by the processor, the third data stream with the first data stream, the second ...

Multi-level wear leveling for non-volatile memory

A memory sub-system performs a first wear leveling operation among a plurality of individual data units of the memory component after a first interval and performs a second wear leveling operation among a first plurality of groups of data units of the memory component after a second interval, wherein a first group of the first plurality of groups comprises the plurality of individual data units. The memory sub-system further performs a third wear leveling operation among a second plurality of groups of data units of the memory component after a third interval, wherein a second group of the second plurality of groups comprises the first plurality of groups of data units.

Memory controller and operating method thereof

A memory controller controls operations of a memory device. The memory controller includes a group read count storage and a data distribution controller. The group read count storage divides logical block addresses corresponding to data stored in the memory device into a plurality of logical block address groups and stores respective read count values of the data corresponding to the logical block addresses according to the logical block address groups. The data distribution controller controls the memory device to distribute and store data corresponding to a target logical block address group selected among the plurality of logical block address groups in a plurality of memory blocks based on the read count values stored according to the logical block address groups.

Coherency of data in data relocation

At least one attribute defined by a host is used to identify data and/or a location for a destination portion for relocating data from a source portion to the destination portion. The data is relocated from the source portion to the destination portion in accordance with the identification of the data to be relocated and/or the location for the destination portion, and it is determined if a change was made to relevant data stored in the source portion while relocating the data from the source portion to the destination portion. If a change was made to relevant data stored in the source portion while relocating the data to the destination portion, the changed relevant data is relocated from the source portion to the destination portion.

MEMORY CONTROLLER SUPPORTING NONVOLATILE PHYSICAL MEMORY

A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory. 1. (canceled)2. A memory controller comprising:a first port to couple to nonvolatile memory having a plurality of erase units, each erase unit including nonvolatile access units, specified by respective nonvolatile-access-unit addresses, to store data over time, the data stored over time including eldest data;a second port to couple to a volatile memory having volatile access units, each volatile access unit specified by a respective volatile-access-unit address;a head register to store, as a head nonvolatile address, the nonvolatile-access-unit address of a next one of the nonvolatile access units to receive write data; anda tail register to store, as a tail nonvolatile address, the nonvolatile-access-unit address of one of the nonvolatile access units in the one of the erase units storing the eldest data;the memory controller to compare the head nonvolatile address with the tail nonvolatile address to initiate a garbage-collection process that erases the eldest data.3. The memory controller of claim 2 , wherein the head nonvolatile address and the tail nonvolatile address define between them a group of valid page entries and invalid page entries.4. The memory controller of claim 3 , wherein the group of valid page entries and invalid page entries are contiguous.5. The memory controller of claim 2 , wherein the memory controller wear levels the writes to the nonvolatile memory without a counter to track writes to the erase units.6. The memory controller of claim 2 , wherein the nonvolatile access units are pages of flash memory.7. The memory controller of claim 2 , the memory controller to maintain an address translation table mapping the volatile ...

System and method for providing a flash memory cache input/output throttling mechanism based upon temperature parameters for promoting improved flash life

Aspects of the disclosure pertain to a system and method for providing a flash memory cache input/output throttling mechanism based upon temperature parameters for promoting improved flash life. The mechanism restricts flash memory cache caching of inputs/outputs associated with Least Recently Used data and Most Recently Used data when a temperature of the flash memory is at or above a threshold temperature.

Garbage collection of a storage device

A method operable with the storage device includes determining a workload to the storage device based on host Input/Output (I/O) requests to the storage device. When the workload is above a threshold, a first portion of the storage device is selected for garbage collection based on the I/O requests. Otherwise, when the workload is below the threshold, a second different portion of the storage device is selected for garbage collection based on a storage ability of the second portion of the storage device.

EXPOSING AND MANAGING DISPARATE READ, WRITE, AND ERASE SIZES IN DATA STORAGE DEVICES

An improved interface for managing disparate read, write, and erase sizes and operations in data storage devices is provided. By improving an interface between a storage system driver layer and associated storage devices, performance of data storage is improved, including improving data storage speed and storage media endurance. Storage media management operations are made more efficient and consistent by providing improved types and sequences of commands sent from the driver layer to the device control layer such that data write operations are performed in a sequential manner as write commands are directed to portions of data as opposed to buffering individual portions of data followed by a large wholescale write/erase process for the buffered data. 1. A computer-implemented method of improving utilization of data storage media , comprising:translating a request to write data to a logical address on a data storage device to a sequentialized address on the data storage device; the write area size being smaller than the erase area size,', 'the read size being distinct from both the write area size and erase area size,', 'wherein the data to be written is not an integral multiple of the erase area size;, 'the data storage device having, for the sequentialized address, a write area size, an erase area size, and a read size,'}assigning a first write start address to align with a first erase area; andwriting a first portion of the data to the first write start address.2. The method of claim 1 , further comprising marking all sectors of a partially-written erase area as allocated and associated with the data.3. The method of claim 1 , further comprising claim 1 , upon receiving a command to delete the data claim 1 , sending an erase command for the entire erase area.4. The method of claim 1 , further comprising:if the first portion of the data is written to the end of a file, marking, in a file system metadata, all sectors of the erase area as allocated and associated ...

GARBAGE COLLECTION IN SSD DRIVES

A storage device, such as a NAND flash device, includes a controller that maintains a temperature for a plurality of data blocks, the temperature calculated according to a function that increases with a number of valid data objects in the block and recency with which the valid data objects have been accessed. Blocks with the lowest temperature are selected for garbage collection. Recency for a block is determined based on a number of valid data objects stored in the block that are referenced in a hot list of a LRU list. During garbage collection, data objects that are least recently used are invalidated to reduce write amplification. 1. A method comprising:executing, by a memory device controller, a plurality of read operations a plurality of blocks of memory, each block of the plurality of blocks of memory storing one or more data objects, each read operation referencing one of the data objects in one of the blocks of the plurality of memory;invalidating, by the memory device controller, a portion of the one or more data objects in the one or more blocks of memory in response to detecting the portion of the one or more data objects meeting an invalidation criteria;calculating, by the memory device controller, for each block of the plurality of blocks of memory, a recency metric that increases with a recency with which the one or more objects of the each block have been read;calculating, by the memory device controller, for each block of the plurality of blocks of memory, a validity metric that increases with a proportion of valid to invalid objects of the one or more objects of the each block;identifying, by the memory device controller, one or more lowest metric blocks from the plurality of blocks of memory, the one or more lowest metric blocks each having a combined recency metric and validity metric that is lower than a remainder of the plurality of blocks of memory not included in the lowest metric blocks; andperforming, by the memory device controller, garbage ...

Memory system and method of operating the same

A memory system includes a storage device including a plurality of dies in which data is stored, and a memory controller configured to control an operation of the storage device, wherein the dies store pieces of reliability grade information about the respective dies, and wherein the memory controller receives the pieces of reliability grade information from the dies, sets reference values for managing the dies depending on the received reliability grade information, and manages the respective dies based on the reference values.

AGGRESSIVE DATA DEDUPLICATION USING LAZY GARBAGE COLLECTION

A method for extending data lifetime for reference in deduplication is provided. The method includes determining that a quantity of user data has at least a threshold amount of data that is re-created in a storage system. The method includes protecting at least portions of the quantity of user data from erasure by garbage collection in the storage system during a predetermined time interval, wherein the protected at least portions are available for data deduplication of further user data in the storage system during the predetermined time interval. 1. A method , comprising:determining data received by a storage system has a threshold amount of data repeated in the storage system;protecting at least portions of the repeated data from deletion by garbage collection, during a predetermined time interval, the repeated data having a status as being unreferenced in the storage system; andperforming garbage collection except where deletion immunity prevents the deletion during the garbage collection.2. The method of claim 1 , further comprising:indicating in metadata that at least portions of recreated data associated with memory to be reclaimed are to have deletion immunity.3. The method of claim 1 , further comprising:forming a histogram, over one or more sampling windows of time, of data of the storage system, the histogram indicating amounts of the data of the storage system having hash function results matching hash function results of another portion of the data during the one or more sampling windows of time.4. The method of claim 1 , further comprising:setting an aging parameter for one of the at least portions of the repeated data to a first value, responsive to determining the one of the at least portions matches a fingerprint result of another portion of data during a sampling window of time, wherein the first value indicates to not delete during garbage collection.5. The method of claim 1 , further comprising:tracking file creation, file deletion, or frequency ...

SYSTEM AND METHOD FOR ADAPTIVE OPTIMIZATION FOR PERFORMANCE IN SOLID STATE DRIVES BASED ON SEGMENT ACCESS FREQUENCY

A method and information handling system and a solid state drive (SSD) memory device including NAND flash memory with an SSD controller to execute instructions of an SSD adaptive profiling engine for RAM cache optimization and configured to cache a partial FTL table in RAM including look-up addresses corresponding to LBA segments in the NAND flash memory having access counts reflecting SSD I/O operations. The method and system further configured to detect an outlier LBA segment having look-up addresses in the cached portion of the FTL table, wherein the outlier LBA segment has I/O access counts at a threshold level below the mean access counts of other LBA segments represented in the partial FTL look-up table and to evict the LBA segment look-up address of the outlier LBA segment from the cached portion of the FTL table pursuant. 1. An information handling system comprising:a solid state drive (SSD) memory device including NAND flash memory;an SSD controller executing instructions of an SSD adaptive profiling engine for RAM cache optimization;the SSD controller caching a partial FTL table in RAM including look-up addresses corresponding to LBA segments in the NAND flash memory having access counts reflecting SSD I/O operations;the SSD controller executing the adaptive profiling engine to detect an outlier LBA segment having look-up addresses in the cached portion of the partial FTL table, wherein the outlier LBA segment has I/O access counts at a threshold level below the mean access counts of other LBA segments represented in the partial FTL look-up table; andthe SSD controller evicting an LBA segment look-up addresses associated with the outlier LBA segment from the cached portion of the partial FTL table.2. The information handling system of further comprising:the SSD controller replacing the evicted look-up address of the outlier LBA segment with another LBA segment having access counts above a threshold level from the mean access counts of other LBA segments ...

MULTIPLE INDIRECTION GRANULARITIES FOR MASS STORAGE DEVICES

One embodiment provides a memory controller. The memory controller includes logical block address (LBA) section defining logic to define a plurality of LBA sections for a memory device circuitry, each section including a range of LB As, and each section including a unique indirection-unit (IU) granularity; wherein the IU granularity defines a physical region size of the memory device. The LBA section defining logic also to generate a plurality of logical-to-physical (L2P) tables to map a plurality of LBAs to physical locations of the memory device, each L2P table corresponding to an LBA section. The memory controller also includes LBA section notification logic to notify a file system of the plurality of LBA sections to enable the file system to issue a read and/or write command having an LBA based on an IU granularity associated with an LBA section. 1. A memory controller , comprising:logical block address (LBA) section defining logic to define a plurality of LBA sections for memory device circuitry, each section including a range of LBAs, and each section including a unique indirection-unit (IU) granularity; wherein the IU granularity defines a physical region size of the memory device, the LBA section defining logic also to generate a plurality of logical-to-physical (L2P) tables to map a plurality of LBAs to physical locations of the memory device, each L2P table corresponding to an LBA section; andLBA section notification logic to notify a file system of the plurality of LBA sections to enable the file system to issue a read and/or write command having an LBA based on an IU granularity associated with an LBA section.2. The memory controller of claim 1 , further comprising LBA to IU logic to determine an IU index number based on the LBA; and wherein each L2P table includes a range of IU index numbers corresponding to a range of LBAs; and wherein each IU index number points to a physical region of the memory device having region size of the IU granularity ...

MEMORY DEVICE AND NON-TRANSITORY COMPUTER READABLE RECORDING MEDIUM

According to one embodiment, a memory device includes a nonvolatile memory, address translation unit, generation unit, and reception unit. The nonvolatile memory includes erase unit areas. Each of the erase unit areas includes write unit areas. The address translation unit generates address translation information relating a logical address of write data written to the nonvolatile memory to a physical address indicative of a write position of the write data in the nonvolatile memory. The generation unit generates valid/invalid information indicating whether data written to the erase unit areas is valid data or invalid data. The reception unit receives deletion information including a logical address indicative of data to be deleted in the erase unit area. 1. A memory device , comprising:a nonvolatile memory; anda processor controlling the nonvolatile memory, whereinthe processorgenerates first information including a logical address indicative of valid data written to an area to be subjected to garbage collection in the nonvolatile memory,transmits the first information to a host device,receives second information including a logical address indicative of data to be deleted amongst the valid data in the area to be subjected to garbage collection from the host device, andperforms garbage collection of the valid data written to the area to be subjected to garbage collection excluding the data to be deleted.2. The memory device of claim 1 , whereinthe processor generates third information indicating whether data written to the nonvolatile memory is valid or invalid, and generates the first information based on the third information.3. The memory device of claim 2 , whereinthe processor generates fourth information relating a logical address of write data written to the nonvolatile memory to a physical address indicative of a write position of the write data in the nonvolatile memory, and generates the third information based on the fourth information.4. The memory ...

MEMORY CONTROLLER, NON-VOLATILE MEMORY SYSTEM, AND METHOD OPERATING SAME

Provided are a memory controller, a non-volatile memory system, and a method of operating the same. A method of operating a memory system includes selecting a plurality of source blocks to be garbage-collected, copying selected valid data from two or more source blocks among the plurality of source blocks into a destination block, storing changed mapping information in an update cache according to a result of the copying, and updating a mapping table by using the mapping information stored in the update cache. 1. A method of performing a garbage collection operation in a memory system including a memory controller including an update cache and a non-volatile memory device including a memory cell array including a storage region divided into blocks and a meta region storing mapping tables managing data stored in the storage region , the method comprising:storing mapping information in the update cache;determining whether to perform a sequential garbage collection operation or a simultaneous garbage collection operation;upon determining to perform the sequential garbage collection operation, collecting valid data from one source block among the blocks, and updating the mapping information stored in the update cache in response to the collecting of valid data from the one source block, elseupon determining to perform the simultaneous garbage collection operation, simultaneously collecting valid data from a plurality of source blocks from among the blocks, and updating the mapping information stored in the update cache in response to the collecting of valid data from the plurality of source blocks.2. The method of claim 1 , wherein the determining of whether to perform a sequential garbage collection operation or simultaneous garbage collection operation for the at least one of the blocks comprises; determining for at least one of the blocks whether data stored in the at least one of the blocks is random data claim 1 , and if the data stored in the at least one of the ...

Zoned Namespaces in Solid-State Drives

The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a media unit. The capacity of the media unit is divided into a plurality of zones. The controller is configured to make informed use of errors by update zone metadata to indicate one or more first logical block addresses were skipped and to indicate the next valid logical block address is available to store data. The controller is further configured to update zone metadata to recommend to the host device to reset one or more full zones, to recommend to the host device to transition one or more open zones to a full state, to alert the host device that one or more open zones have been transitioned to the full state, and to notify the host device of the writeable zone capacity of each of the plurality of zones. 1. A storage device , comprising:a media unit, wherein a capacity of the media unit is divided into a plurality of zones, and wherein the media unit comprises a plurality of dies, each of the plurality of dies comprising a plurality of erase blocks; and{'claim-text': ['determine a writeable zone capacity of each of the plurality of zones, the writeable zone capacity being equal to or less than a total zone storage capacity of each zone, wherein the writeable capacity of each zone is aligned with a capacity of one or more erase blocks; and', 'update zone metadata to notify a host device of the writeable zone capacity of each of the plurality of zones.'], '#text': 'a controller coupled to the media unit, the controller configured to:'}2. The storage device of claim 1 , wherein the controller updates a Writeable ZCAP attribute in the zone metadata to notify the host device of the writeable zone capacity.3. The storage device of claim 1 , wherein the writeable zone capacity of at least one zone is less than the total zone storage capacity of the at least one zone claim 1 , and wherein the at least one zone having a writeable zone capacity ...

Storage devices, data storage systems and methods of operating storage devices

A storage device includes a main storage including a plurality of nonvolatile memory devices, the main storage device configured to store data; and a storage controller configured to control the main storage. The storage controller is configured to, divide a plurality of memory blocks of the plurality of nonvolatile memory devices into a plurality of banks, assign each one of the plurality of banks into one of a) a plurality of sets and b) one free bank, each of the plurality of sets including at least one bank, perform data migration operation to transfer the data among the sets by using the one free bank in response to an input/output (I/O) request from an external host device while securing a specific I/O execution time, and control the data migration operation such that the I/O request is independent of the data migration operation.

Maintaining data consistency in a memory sub-system that uses hybrid wear leveling operations

A determination is made that a source group of data management units of a memory component satisfies a threshold wear condition. A wear leveling operation is performed by copying data from a first data management unit of the source group of data management units to a second data management unit of a destination group of data management units of the memory component. A logical address of the first data management unit is determined. Indicators in a mapping data structure are moved from entries associated with the first data management unit to another entries in the mapping data structure that are subsequent to the entries associated with the first data management unit. The indicators are used to access data requested by a host system at the source group of data management units or at the destination group of data management units.

PERFORMING HYBRID WEAR LEVELING OPERATIONS BASED ON A SUB-TOTAL WRITE COUNTER

Data is copied, to a first group of data blocks in a first plurality of groups of unmapped data blocks, from a second group of data blocks in a second plurality of groups of mapped data blocks. Upon copying data to the first group of data blocks from the second group of data blocks, the first group of data blocks is included in the second plurality of groups of mapped data blocks. Upon including the first group of data blocks in the second plurality of groups of mapped data blocks, a wear leveling operation is performed on the first group of data blocks, wherein performing the wear leveling operation comprises determining a base address of the first group of data blocks, the base address indicating a location at which the first group of data blocks begins. A request to access subsequent data at a logical address associated with a data block included in the first group of data blocks is received. A physical address based on the base address of the first group of data blocks and the logical address is determined. The subsequent data is accessed at the first group of data blocks based on the physical address. 1. A method comprising:copying, to a first group of data blocks in a first plurality of groups of unmapped data blocks, data from a second group of data blocks in a second plurality of groups of mapped data blocks;upon copying data to the first group of data blocks from the second group of data blocks, including the first group of data blocks in the second plurality of groups of mapped data blocks;upon including the first group of data blocks in the second plurality of groups of mapped data blocks, performing a wear leveling operation on the first group of data blocks, wherein performing the wear leveling operation comprises determining a base address of the first group of data blocks, the base address indicating a location at which the first group of data blocks begins;receiving a request to access subsequent data at a logical address associated with a data block ...

UNMAP STORAGE SPACE

A system that includes a storage drive and a controller communicatively coupled to the storage drive. The storage drive includes a first region of storage space that is mapped to a virtual volume and at least a second region of storage space reserved for over-provisioning operations. The controller is to unmap an operable portion of the first region of storage space in response to aging of the storage drive so that the unmapped portion can be used for over-provisioning operations. 1. A system comprising:a storage drive comprising a first region of storage space that is mapped to a virtual volume and at least a second region of storage space reserved for over-provisioning operations; anda controller communicatively coupled to the storage drive, the controller to unmap an operable portion of the first region of storage space in response to aging of the storage drive so that the unmapped portion can be used for over-provisioning operations.2. The system of claim 1 , the aging of the storage drive is characterized by a wear indicator computed by the storage drive.3. The system of claim 2 , wherein the controller obtains the wear indicator from the drive periodically and determines whether to unmap a portion of the first region of storage space based on the wear indicator4. The system of claim 2 , wherein the wear indicator is a life left percentage that indicates a percentage of the storage space still available in the second region for over-provisioning operations.5. The system of claim 1 , wherein the storage drive is a solid state drive comprising flash memory.6. A method comprising:sending data storage requests to a drive, the storage requests targeting a first region of storage space of the drive that is mapped to a virtual volume, the drive to perform over-provisioning operations using at least a second region of storage space that is not mapped to the virtual volume;obtaining a wear indicator from the drive; andunmapping an operable portion of the first region of ...

STORAGE DEVICE HAVING IMPROVED WRITE UNIFORMITY STABILITY

A machine readable storage medium containing program code that when processed by a processor causes a method to be performed a method is described. The method includes executing a wear leveling routine by servicing cold data from a first queue in a non volatile storage device to write the cold data. The method also includes executing a garbage collection routing by servicing valid data from a second queue in the non volatile storage device to write the valid data. The method also includes servicing host write data from a third queue in the non volatile storage device to write the host write data wherein the first queue remains fixed and is serviced at a constant rate so that a runtime size of the third queue is not substantially affected by the wear leveling routine. 1. A machine readable storage medium containing program code that when processed by a processor causes a method to be performed , the method comprising:executing a wear leveling routine by servicing cold data from a first queue in a non volatile storage device to write the cold data;executing a garbage collection routing by servicing valid data from a second queue in the non volatile storage device to write the valid data; and,servicing host write data from a third queue in the non volatile storage device to write the host write data wherein the first queue remains fixed and is serviced at a constant rate so that a runtime size of the third queue is not substantially affected by the wear leveling routine.2. The machine readable storage medium of wherein the non volatile storage device is a solid state disk (SSD) device.3. The machine readable storage medium of wherein the method further comprises changing a size of the second and third queues as a function of a write amplification determination.4. The machine readable storage medium of wherein the first claim 1 , second and third queues are implemented in memory local to the non volatile storage device.5. The machine readable storage medium of wherein ...

REDUCING WRITE AMPLIFICATION IN SOLID-STATE DRIVES BY SEPARATING ALLOCATION OF RELOCATE WRITES FROM USER WRITES

In one embodiment, a method includes maintaining a first open logical erase block for user writes, maintaining a second open logical erase block for relocate writes, wherein the first and second open logical erase blocks are different logical erase blocks, receiving a first data stream having the user writes, transferring the first data stream to the first open logical erase block, receiving a second data stream having the relocate writes, and transferring the second data stream to the second open logical erase block. Other systems, methods, and computer program products are described in additional embodiments. 1. A method , comprising:maintaining, by a processor, a first open logical erase block for user writes;maintaining, by the processor, a second open logical erase block for relocate writes, wherein the first and second open logical erase blocks are different logical erase blocks;receiving, by the processor, a first data stream having the user writes;transferring, by the processor, the first data stream to the first open logical erase block;receiving, by the processor, a second data stream having the relocate writes; andtransferring, by the processor, the second data stream to the second open logical erase block.2. The method of claim 1 , further comprising:assigning a first timeout value to the first open logical erase block; andassigning a second timeout value to the second open logical erase block.3. The method of claim 2 , further comprising:reassigning at least one of the open logical erase blocks to a different data stream when the timeout of the open logical erase block expires.4. The method of claim 2 , wherein the first and second timeout values are determined based on a logical erase block write interval.5. The method of claim 4 , wherein the first and second timeout values are between about two and about five times a length of the logical erase block write interval.6. The method of claim 1 , comprising:performing heat segregation on the data streams ...

PASS-THROUGH TAPE ACCESS IN A DISK STORAGE ENVIRONMENT

A command to write data to a virtual location is received at a disk storage system. The virtual location is mapped to a tape storage system. A record is generated including the data, the virtual location, and a sequence value. The sequence value indicates relative sequence when compared to other sequence values. The record is written to a record location on a tape cartridge loaded in a tape drive. Record metadata on the disk storage system is modified to indicate that the first record location contains the first record. The data on the record can be read from the tape cartridge. 1. A system comprising:a tape storage system comprising a set of tape cartridges; and receive a command to write data to a first virtual location, the first virtual location mapped to a tape storage system;', 'generate a first record comprising the data, the first virtual location, and a first sequence value, the first sequence value indicating relative sequence when compared to other sequence values;', 'write the first record to a first record location on a first tape cartridge loaded in a tape drive; and', 'modify record metadata on the disk storage system to indicate that the first record location contains the first record, the record metadata comprising a tape record table with record information for specific record locations., 'a disk storage system connected to the tape storage system, the disk storage system configured to2. The system of claim 1 , wherein the modifying the record metadata comprises:updating an entry in the tape record table associated with the first record location to include information on the first record.3. The system of claim 2 , wherein the disk storage system is further configured to:identify, in the record metadata, information regarding a previous record associated with the first virtual location, the previous record at a second record location; andmodify the record metadata to indicate that the second record location is free to be written to.4. The system of ...

TECHNOLOGIES FOR COMBINING LOGICAL-TO-PHYSICAL ADDRESS UPDATES

Technologies for combining logical-to-physical address updates include a data storage device. The data storage device includes a non-volatile memory to store data and a logical to physical (L2P) table indicative of logical addresses and associated physical addresses of the data. Additionally, the data storage device includes a volatile memory to store one or more bins. Each bin is indicative of a subset of entries in the L2P table. Further, the data storage device includes a controller to allocate a bin in the volatile memory, write a plurality of updates to a subset of entries of the L2P table to the bin, and write the bin to the L2P table in a single write operation. Other embodiments are also described and claimed. 1. A data storage device comprising:a non-volatile memory to store (i) a logical to physical (L2P) table indicative of logical addresses and associated physical addresses of data and (ii) data at the physical addresses;a volatile memory to store one or more bins, wherein each bin is indicative of a subset of entries in the L2P table; and allocate a bin in the volatile memory;', 'write a plurality of updates to a subset of entries of the L2P table to the bin; and', 'write the bin to the L2P table in a single write operation., 'a controller to2. The data storage device of claim 1 , wherein the non-volatile memory comprises a first memory device that includes write-in-place claim 1 , byte-addressable memory and a second memory device that includes a different type of non-volatile memory.3. The data storage device of claim 1 , wherein the L2P table is to be stored in a first non-volatile memory device and the data is to be stored at physical addresses in a second memory device that is different from the first memory device.4. The data storage device of claim 1 , wherein to allocate the bin in the volatile memory comprises to read a subset of the L2P table into the bin in the volatile memory.5. The data storage device of claim 1 , wherein to write a ...

APPLYING MULTIPLE HASH FUNCTIONS TO GENERATE MULTIPLE MASKED KEYS IN A SECURE SLICE IMPLEMENTATION

Methods and apparatus for efficiently storing and accessing secure data are disclosed. The method of storing includes encrypting data utilizing an encryption key to produce encrypted data, performing deterministic functions on the encrypted data to produce deterministic function values, masking the encryption key utilizing the deterministic function values to produce masked keys and combining the encrypted data and the masked keys to produce a secure package. The method of accessing includes de-combining a secure package to reproduce encrypted data and masked keys, selecting a deterministic function, performing the selected deterministic function on the reproduced encrypted data to reproduce a deterministic function value, de-masking a corresponding masked key utilizing the reproduced deterministic function value to reproduce an encryption key, and decrypting the reproduced encrypted data utilizing the reproduced encryption key to reproduce data. 1. A method for execution by one or more processing modules of one or more computing devices of a dispersed storage network (DSN) , the DSN including a plurality of storage units , the method comprising:encrypting data utilizing an encryption key to produce encrypted data;performing a plurality of deterministic functions on the encrypted data to produce a plurality of deterministic function values;masking the encryption key utilizing the plurality of deterministic function values to produce a plurality of masked keys;combining the encrypted data and the plurality of masked keys to produce a secure package; anddispersed storage error encoding the secure package.2. The method of claim 1 , wherein each of the plurality of deterministic function values includes a first number of bits that is substantially the same as a second number of bits of the encryption key.3. The method of claim 1 , wherein masking the encryption key utilizing the plurality of deterministic function values includes performing an exclusive OR function on ...

METHOD AND DEVICE FOR CLEARING PROCESS IN ELECTRONIC DEVICE

A method and a device for clearing a process in an electronic device are provided. The method includes calculating an amount of memory allocated for a preset time period when a memory application is requested, predicting an amount of memory to be allocated for a future setting time period based on the amount of the memory, and selecting and clearing at least one of present processes based on the amount of the memory to be allocated. Accordingly, sufficient memory can be obtained in a short period of time by recalling a plurality of processes. In this way, the electronic device can continuously allocate an abundance of memory. 1. A method of clearing a process , the method comprising:calculating an amount of memory allocated for a preset time period, when a memory application is requested;predicting an amount of memory to be allocated for a future setting time period based on the amount of the memory; andselecting and clearing at least one of present processes based on the amount of the memory to be allocated.2. The method of claim 1 , wherein the calculating of the amount of the memory allocated for the preset time period comprises:calculating an amount of memory first allocated for a recent setting time period;determining a presence or absence of at least one time period in the recent setting time period for which the memory is not allocated;predicting a time period for which the memory is allocated when there is not the at least one time period for which the memory is not allocated; andcalculating an amount of the memory allocated for the time period.3. The method of claim 2 , wherein the determining of the presence or absence of at least one time period in the recent setting time period for which the memory is not allocated comprises:configuring the time period in the recent setting time period for which the memory is not allocated as a present time period, and the recent setting time period as a present setting time period when there is the time period for which ...

MAINTAINING DATA CONSISTENCY IN A MEMORY SUB-SYSTEM THAT USES HYBRID WEAR LEVELING OPERATIONS

A processing device in a memory sub-system maintains a mapping data structure to track data movements from a plurality of data management units associated with a media management operation on a memory device. The processing device further uses a first indicator and a second indicator of a plurality of indicators to indicate which data of data management units of a source group of data management units have been copied to a destination group of data management units during the media management operation. Data located in data management units preceding the first indicator have been copied to data management units of the destination group of data management units. Data located in data management units associated with the first indicator and the second indicator or between the first indicator and the second indicator are either copied to data management units of the destination group of data management units or remain located in data management units of the source group of data management units. Data located in data management units subsequent to the second indicator remain located in data management units of the source group of data management units and have not been copied to the destination group of data management units. 1. A method comprising:maintaining a mapping data structure to track data movements from a plurality of data management units associated with a media management operation on a memory device; and data located in data management units preceding the first indicator have been copied to data management units of the destination group of data management units;', 'data located in data management units associated with the first indicator and the second indicator or between the first indicator and the second indicator are either copied to data management units of the destination group of data management units or remain located in data management units of the source group of data management units; and', 'data located in data management units subsequent to the ...

INTELLIGENT HYBRID DRIVE CACHING

Systems and methods can implement one or more intelligent caching algorithms that reduce wear on the SSD and/or to improve caching performance. Such algorithms can improve storage utilization and I/O efficiency by taking into account the write-wearing limitations of the SSD. Accordingly, the systems and methods can cache to the SSD while avoiding writing too frequently to the SSD to increase or attempt to increase the lifespan of the SSD. The systems and methods may, for instance, write data to the SSD once that data has been read from the hard disk or memory multiple times to avoid or attempt to avoid writing data that has been read only once. The systems and methods may also write large chunks of data to the SSD at once instead of a single unit of data at a time. Further, the systems and methods can write to the SSD in a circular fashion. 1. (canceled)2. A data storage system configured to perform data backup operations , comprising:a client computing device residing in a primary storage subsystem and having at least one software application installed thereon, the client computing device associated with and in networked communication with a storage system located in the primary storage subsystem, the storage system comprising a hard disk and a solid-state drive (SSD) operating as a cache for the hard disk, the storage system configured to store primary data generated by the software application;a storage manager implemented in a computing device and configured to instruct the client computing device to perform tasks associated with data backup operations in which the primary data is copied to one or more secondary storage devices residing in a secondary storage subsystem; receive a first request to read a first data element from the storage system, the first request relating to one of the data backup operations;', 'read the first data element from the hard disk;', 'receive a second request to read the first data element from the storage system, the first request ...

Intelligent hybrid drive caching

Systems and methods can implement one or more intelligent caching algorithms that reduce wear on the SSD and/or to improve caching performance. Such algorithms can improve storage utilization and I/O efficiency by taking into account the write-wearing limitations of the SSD. Accordingly, the systems and methods can cache to the SSD while avoiding writing too frequently to the SSD to increase or attempt to increase the lifespan of the SSD. The systems and methods may, for instance, write data to the SSD once that data has been read from the hard disk or memory multiple times to avoid or attempt to avoid writing data that has been read only once. The systems and methods may also write large chunks of data to the SSD at once instead of a single unit of data at a time. Further, the systems and methods can write to the SSD in a circular fashion.

SCRUBBER DRIVEN WEAR LEVELING IN OUT OF PLACE MEDIA TRANSLATION

A process for wear-leveling in a memory subsystem where references to invalidated chunks and a write count for each of the invalidated chunks of a memory subsystem are received by a wear-leveling manager. The wear-leveling manager orders the received references to the invalidated chunks of the memory subsystem in a tracking structure based on the write count of each of the invalidated chunks, and provides a reference to at least one of the invalidated chunks based on the ordering from the tracking structure to a write scheduler to service a write request, wherein the memory subsystem is wear-leveled by biasing the order of the invalidated chunks to prioritize low write count chunks. 1. A computer-implemented method comprising:receiving references to invalidated chunks and a write count for each of the invalidated chunks of a memory subsystem;ordering the received references to the invalidated chunks of the memory subsystem in a tracking structure based on the write count of each of the invalidated chunks; andproviding a reference to at least one of the invalidated chunks based on the ordering from the tracking structure to a write scheduler to service a write request, wherein the memory subsystem is wear-leveled by biasing the order of the invalidated chunks to prioritize low write count chunks.2. The computer-implemented method of claim 1 , wherein at least a portion of the invalidated chunks are invalidated when overwritten by the write scheduler.3. The computer-implemented method of claim 1 , wherein at least a portion of the invalidated chunks are invalidated by a scrubber function in response to the scrubber function identifying that the chunks have a low write count.4. The computer-implemented method of claim 1 , further comprising:determining a codeword type for each of the invalidated chunks, wherein the ordering is based on the codeword type to avoid a partition write collision.5. The computer-implemented method of claim 4 , wherein the invalidated chunks ...

Apparatus and Method of Wear Leveling for Storage Class Memory Using Address Cache

A method and apparatus of wear leveling control for storage class memory are disclosed. According to the present invention, where current data to be written to a nonvolatile memory corresponds to an address cache hit is determined. If the current data to be written corresponds to an address cache hit, the current data are written to a designated location in the nonvolatile memory different from a destined location in the nonvolatile memory. If the current data to be written corresponds to an address cache miss, the current data are written to the destined location in the nonvolatile memory. In another embodiment, the wear leveling control technique also includes address rotation process to achieve long-term wear leveling as well. 1. A method of wear leveling control for storage class memory based on nonvolatile memory using an address cache , the method comprising:determining whether current data to be written to a nonvolatile memory corresponds to an address cache hit, wherein the address cache hit indicates that address of the current data to be written to the nonvolatile memory is in the address cache;if the current data to be written corresponds to the address cache hit, writing the current data to a designated location in the nonvolatile memory different from a destined location in the nonvolatile memory; andif the current data to be written corresponds to an address cache miss, writing the current data to the destined location in the nonvolatile memory, wherein the address cache miss indicates that the address of the current data to be written to the nonvolatile memory is not in the address cache.2. The method of claim 1 , further comprising writing the address of the current data to the address cache also if the current data to be written corresponds to the address cache miss and the address cache is not full.3. The method of claim 1 , wherein claim 1 , when the current data is written to the designated location in the nonvolatile memory different from the ...

Apparatus and Method of Damage Recovery for Storage Class Memory

A method and apparatus of wear leveling control for storage class memory are disclosed. According to the present invention, whether current data to be written to a nonvolatile memory corresponds to a write cache hit is determined. If the current data to be written corresponds to the write cache hit, the current data are written to a write cache as well as to a designated location in the nonvolatile memory different from a destined location in the nonvolatile memory. If the current data to be written corresponds to a write cache miss, the current data are written to the destined location in the nonvolatile memory. If the current data to be written corresponds to the write cache miss and the write cache is not full, the current data is also written to the write cache. In another embodiment, the wear leveling control technique also includes address rotation process to achieve long-term wear leveling as well. 1. A method of damage recovery for storage class memory based on nonvolatile memory using a write cache , wherein input data is written to a selected write cache location as well as a selected nonvolatile memory location , the selected write cache location includes a timestamp , and contents in the selected nonvolatile memory location are flushed to a destined location in the nonvolatile memory if the timestamp indicates that the in the selected nonvolatile memory location are aged , the method comprising:dividing the nonvolatile memory into memory groups; andmapping N input group addresses corresponding to logic addresses of the memory groups to M output group addresses corresponding to physical group addresses of the memory groups using fixed mapping within a period T, wherein M and N are positive integers and M is greater than N, wherein N memory groups are used as data groups, and one or more memory groups are used as redundant groups, M is equal to a sum of N and number of the redundant groups, and wherein said mapping N input group addresses to M output group ...

Meta Data Arrangement for Wear Leveling of Storage Class Memory

A method and apparatus of wear leveling control for storage class memory are disclosed. According to the present invention, whether current data to be written to a nonvolatile memory corresponds to a write cache hit is determined. If the current data to be written corresponds to the write cache hit, the current data are written to a write cache as well as to a designated location in the nonvolatile memory different from a destined location in the nonvolatile memory. If the current data to be written corresponds to a write cache miss, the current data are written to the destined location in the nonvolatile memory. If the current data to be written corresponds to the write cache miss and the write cache is not full, the current data is also written to the write cache. In another embodiment, the wear leveling control technique also includes address rotation process to achieve long-term wear leveling as well. 1. A method of wear leveling control for storage class memory based on nonvolatile memory , the method comprising:configuring D nonvolatile-memory chips to store input data and E nonvolatile-memory chips to store extended data associated with the input data in the nonvolatile memory, wherein D and E are positive integers;dividing the nonvolatile memory into memory groups;mapping N input group addresses corresponding to logic addresses of the memory groups to M output group addresses corresponding to physical group addresses of the memory groups using fixed mapping within a period T, wherein M and N are positive integers and M is greater than N, wherein N memory groups are used as data groups, and one or more memory groups are used as redundant groups, M is equal to a sum of N and number of the redundant groups, and wherein said mapping N input group addresses to M output group addresses causes N data groups among M memory groups to store input data in a rotated fashion; andstoring Error Correction Code (ECC) check bytes and metadata associated with the data groups ...

Memory management method, memory control circuit unit and memory storage device

A memory management method, a memory control circuit unit and a memory storage device are provided. The method includes: performing a single-layer erasing operation on one of physical erasing units; performing a multi-layer erasing operation on another one of the physical erasing units; and performing a wear leveling operation based on the one and the another one of the physical erasing units, wherein the another one of the physical erasing units is performed the wear leveling operation first than the one of the physical erasing units.

Fine granularity translation layer for data storage devices

A Data Storage Device (DSD) includes a non-volatile memory configured to store data, and control circuitry configured to receive a memory access command from a host to access data in the non-volatile memory. A location is identified in the non-volatile memory for performing the memory access command using an Address Translation Layer (ATL) that has a finer logical-to-physical granularity than a logical-to-physical granularity of a logical block-based file system executed by the host or a granularity based on a memory Input/Output (IO) transaction size of a processor of the host. The non-volatile memory is accessed at the identified location to perform the memory access command.

STORAGE DEVICE AND COMPUTING SYSTEM

The present technology relates to an electronic device. More specifically, the present technology relates to a storage device and a computing system. A storage device according to an embodiment may include a memory device including a firmware block group configured to store main firmware data and sub firmware data, and a user block group configured to store write data, and a memory controller, in response to a booting request provided from a host, configured to count a number of previously generated power losses based on data stored in an open block in the user block group in a booted state based on the main firmware data, performs a rebooting operation using the sub firmware data when the number of power losses exceeds a reference number, and execute sub firmware to correct an error of data related to the power losses. 1. A storage device comprising:a memory device including a firmware block group configured to store main firmware data of main firmware for performing an operation according to an operation request provided from a host and sub firmware data of sub firmware for correcting an error of data related to power losses, and a user block group configured to store write data; and count a number of previously generated power losses based on data stored in an open block in the user block group in a booted state based on the main firmware data,', 'perform a rebooting operation using the sub firmware data when the number of power losses exceeds a reference number, and execute the sub firmware to correct the error of the data related to the power losses., 'a memory controller, in response to a booting request provided from the host, configured to2. The storage device of claim 1 , whereinthe open block includes a valid page that stores valid data, a stop page at which storage of data is stopped due to power loss, a dummy page that stores dummy data, and an erase page that is to store data, and a main firmware executor configured to control the memory device to store ...

PERFORMING HYBRID WEAR LEVELING OPERATIONS BASED ON A SUB-TOTAL WRITE COUNTER

Data is copied, from a second group of data blocks in a second plurality of groups of data blocks that are mapped, to a first group of data blocks in a first set of groups of data blocks that are not mapped to include the first group of data blocks in the second set of groups of data blocks that are mapped. A sub-total write counter associated with the first group of data blocks is reset. A value of the sub-total write counter indicates a number of write operations performed on the first group of data blocks since the first group of data blocks has been included in the second set of groups of data blocks. A wear leveling operation is performed on the first group of data blocks based on the sub-total write counter. 1. A method comprising:copying data, from a second group of data blocks in a second plurality of groups of data blocks that are mapped, to a first group of data blocks in a first plurality of groups of data blocks that are not mapped to include the first group of data blocks in the second plurality of groups of data blocks that are mapped;resetting a sub-total write counter associated with the first group of data blocks, wherein a value of the sub-total write counter indicates a number of write operations performed on the first group of data blocks since the group of data blocks has been included in the second plurality of groups of data blocks; andperforming, by a processing device, a wear leveling operation on the first group of data blocks based on the sub-total write counter.2. The method of claim 1 , wherein performing the wear leveling operation on the first group of data blocks based on the sub-total write counter further comprises determining that the first group of blocks satisfies a threshold wear condition when a value of the sub-total write counter exceeds a threshold write value.3. The method of claim 1 , further comprising:performing one or more writes to write data to the first group of data blocks; andincrementing the value of the sub-total ...

COMPUTING DEVICE AND METHOD FOR INFERRING A PREDICTED NUMBER OF PHYSICAL BLOCKS ERASED FROM A FLASH MEMORY

Computing device and method for inferring a predicted number of physical blocks erased from a flash memory. The computing device stores a predictive model generated by a neural network training engine. A processing unit of the computing device executes a neural network inference engine, using the predictive model for inferring the predicted number of physical blocks erased from the flash memory based on inputs. The inputs comprise a total number of physical blocks previously erased from the flash memory, an amount of data to be written on the flash memory, and optionally an operating temperature of the flash memory. In a particular aspect, the flash memory is comprised in the computing device, and an action may be taken for preserving a lifespan of the flash memory based at least on the predicted number of physical blocks erased from the flash memory. 1. A computing device , comprising: 'a predictive model comprising weights of a neural network, the predictive model being generated by a neural network training engine; and', 'memory for storing 'executing a neural network inference engine using the predictive model for inferring a predicted number of physical blocks to be erased from a flash memory during an execution of a write operation based on inputs, the inputs including a total number of physical blocks previously erased from the flash memory, an amount of data to be written on the flash memory by the write operation, and one or more characteristics of the flash memory.', 'a processing unit for2. The computing device of claim 1 , wherein the one or more characteristics of the flash memory comprises at least one of the following: a manufacturer of the flash memory claim 1 , a model of the flash memory claim 1 , a capacity of the flash memory claim 1 , a number of physical blocks comprised in the flash memory and a capacity of the physical blocks comprised in the flash memory.3. The computing device of claim 1 , wherein the inputs further comprise a temperature ...

MEMORY SYSTEM

A memory system includes a non-volatile memory, a buffer memory, and a controller. The controller is configured to write data corresponding to a write command received from a host in the buffer memory, and based on an indication from the host, do not write the data stored in the buffer memory into the non-volatile memory unless a non-volatilization event occurs, the non-volatilization event being one of a flush request from the host and a detection of a power shutdown. 1. A memory system comprising:a non-volatile memory;a buffer memory; and write data corresponding to a write command received from a host in the buffer memory; and', 'based on an indication from the host, do not write the data stored in the buffer memory into the non-volatile memory unless a non-volatilization event occurs, the non-volatilization event being one of a flush request from the host and a detection of a power shutdown., 'a controller configured to2. The memory system according to claim 1 , wherein the controller is further configured to manage mapping of logical addresses and physical addresses claim 1 , whereinwhen the data is stored in the buffer memory, the controller updates the mapping such that a first logical address corresponding to the data is mapped to a physical address of the buffer memory at which the data is stored, andafter the non-volatilization event occurs, the controller writes the data stored in the buffer memory into the non-volatile memory and updates the mapping such that the first logical address is mapped to a physical address of the non-volatile memory at which the data is stored.3. The memory system according to claim 1 , wherein the controller determines that the write command received from the host indicates that the data is to be kept in the buffer memory claim 1 , based on one of a first logical address designated by the write command claim 1 , information indicating that use of the non-volatile memory is to be suppressed claim 1 , and a command type.4. The ...

SENSOR BASED MEMORY ARRAY DATA SCRUBBING

According to one embodiment of the present invention, a computer-implemented method for dynamically altering a frequency at which data scrubbing is performed on a memory device is disclosed. The computer-implemented method includes monitoring at least one of a temperature and a magnetic field of the memory device. The computer-implemented method further includes, responsive to determining that at least one of the temperature and the magnetic field of the memory device reaches and/or exceeds a predetermined threshold, respectively, increasing the frequency at which data scrubbing is performed on the memory device. 1. A computer-implemented method for dynamically altering a frequency at which data scrubbing is performed on a memory device , comprising:monitoring at least one of a temperature and a magnetic field of the memory device; and 'increasing the frequency at which data scrubbing is performed on the memory device.', 'responsive to determining that at least one of the temperature and the magnetic field of the memory device reaches and/or exceeds a predetermined threshold, respectively2. The computer-implemented method of claim 1 , wherein the data scrubbing includes a read-only-operation for a memory area of the memory device if no bit errors are detected in the memory area.3. The computer-implemented method of claim 1 , wherein the data scrubbing includes a read-modify-write operation for a memory area of the memory device if one or more bit errors are detected in the memory area.4. The computer-implemented method of claim 1 , wherein a particular increase in the frequency at which data scrubbing is performed on the memory device is based on maintaining a desired chip error rate for the memory device.5. The computer-implemented method of claim 1 , further comprising: 'further increasing the frequency at which data scrubbing is performed on the memory device.', 'responsive to determining that both the temperature and the magnetic field of the memory device reach ...

DATA TRANSFER FOR WEAR-LEVELING

Methods, systems, and devices for data transfer for wear-leveling are described. Data may be stored in pages of banks and the banks may be grouped into bank clusters. A host device may address one bank of a bank cluster at a time. Data may be transferred from a bank to a buffer or a different bank cluster for wear-leveling purposes and this data transfer may take place opportunistically while a second bank, which may be in the same bank cluster, is being accessed based on an access command. 1. A method , comprising:receiving, at a memory device from a host device, an access command to access a first data set stored in a first bank of a first bank cluster of the memory device during an access period;accessing, during the access period, the first data set stored in the first bank of the first bank cluster based at least in part on receiving the access command from the host device;accessing, during the access period, a second data set stored in a second bank of the first bank cluster as part of a data migration operation based at least in part on accessing the first data set; andtransferring, during the access period, the second data set between the second bank of the first bank cluster and a different storage location based at least in part on accessing the second data set.2. The method of claim 1 , further comprising:determining that the data migration operation associated with the first bank cluster is waiting to be performed, wherein the second data set is accessed based at least in part on the determination.3. The method of claim 1 , further comprising:performing the data migration operation during at least a portion of the access period based at least in part on the host device accessing the first data set stored in the first bank of the first bank cluster; andperforming the data migration operation during at least a portion of a second access period based at least in part on the host device accessing a destination bank cluster for the second data set.4. The ...

MEMORY MODULE AND INFORMATION PROCESSING SYSTEM

A memory module includes: a first memory device that is volatile or non-volatile; a second memory device that is non-volatile; a third memory device that is non-volatile; and a controller that controls the first to third memory devices, wherein a capacity of the second memory device is larger than a capacity of the first memory device, and a capacity of the third memory device is larger than the capacity of the second memory device, a second upper limit value of the number of rewritings of the second memory device is larger than a third upper limit value of the number of rewritings of the third memory device, and a first upper limit value of the number of rewritings of the first memory device is larger than the second upper limit value of the number of rewritings of the second memory device, and the controller accesses the second memory device with reference to a first address translation table related to the second memory device stored in the first memory device, and accesses the third memory device with reference to a second address translation table related to the third memory device stored in the second memory device. 1. A memory module , comprising:a first memory device that is volatile or non-volatile;a second memory device that is non-volatile;a third memory device that is non-volatile; anda controller that controls the first to third memory devices,wherein a capacity of the second memory device is larger than a capacity of the first memory device, and a capacity of the third memory device is larger than the capacity of the second memory device,a second upper limit value of the number of rewritings of the second memory device is larger than a third upper limit value of the number of rewritings of the third memory device, and a first upper limit value of the number of rewritings of the first memory device is larger than the second upper limit value of the number of rewritings of the second memory device, andthe controller accesses the second memory device with ...

DATA STORAGE DEVICE AND METHOD FOR OPERATING NON-VOLATILE MEMORY

An efficient data storage device is disclosed, which uses a microprocessor and at least one volatile memory to operate a non-volatile memory. The microprocessor allocates the volatile memory to provide a cache area. According to an asynchronous event request (AER) issued by a host, the microprocessor uses the cache area to collect sections of write data requested by the host, programs the sections of write data collected in the cache area to the non-volatile memory together, and reports failed programming of the sections of write data to the host by AER completion information. 1. A data storage device , comprising:a non-volatile memory; anda controller operating the non-volatile memory, including a microprocessor and a volatile memory,wherein:the microprocessor allocates the volatile memory to provide a cache area;according to an asynchronous event request issued by a host, the microprocessor uses the cache area to collect sections of write data requested by the host, programs the sections of write data collected in the cache area to the non-volatile memory together, and reports failed programming of the sections of write data to the host by asynchronous event request completion information.2. The data storage device as claimed in claim 1 , wherein:each time the cache area is used to cache one section of write data, the microprocessor reports an acknowledgement message to the host and thereby the host issues the next section of write data in response to the acknowledgement message.3. The data storage device as claimed in claim 2 , wherein:when the number of the sections of write data collected in the cache area exceeds a predefined amount, the microprocessor notifies the host to issue a programming command; andaccording to the programming command, the microprocessor programs the sections of write data collected in the cache area to the non-volatile memory.4. The data storage device as claimed in claim 3 , wherein:when programming the sections of write data collected ...

RELOCATING DATA IN A MEMORY DEVICE

Methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others. 120.-. (canceled)21. A method for relocating data stored in a device comprising:first performing, using a memory controller module within a memory component, at least one lower level memory operation on the memory component,wherein the memory component comprises a plurality of memory locations, the plurality of memory locations comprising at least one memory location and at least one different memory location,wherein the at least one lower level memory operation comprises performing, on the at least one memory location, at least one of a read, a write, an erase, or a refresh operation;determining, using a memory manager module within the memory component, the memory manager module being independent of the memory controller module, to relocate data in the at least one memory location to the at least one different memory location based at least in part on a predetermined relocation criterion; andsecond performing, using the memory manager module and based at least in part on the determining, the second performing comprising at least one higher level memory operation on the memory component, ...

MEMORY SYSTEM AND CONTROL METHOD THEREOF

A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest. 1. (canceled)2. A memory system comprising:an interface configured to receive data;a nonvolatile memory including a plurality of blocks, each of the plurality of blocks being a unit for an erase operation; and copy first data from a first block to a second block, the number of erase operations performed on the second block being larger than the number of erase operations performed on the first block; and', 'when the copying is not performed, write second data to a third block, the second data being data that is received through the interface and has not been stored in the nonvolatile memory., 'a controller electrically connected to the nonvolatile memory and configured to3. The memory system according to claim 2 , whereinthe interface is configured to be connected with a host,the first data is valid data,the second block does not store valid data prior to the copying of the first data, andthe third block does not store valid data prior to the writing of the second data, whereinthe valid data is data stored in a block to which a logical address designated by the host is allocated.4. The memory system according to claim 2 , whereinthe interface is configured to be connected with a host, andthe controller is further configured to maintain an address conversion table to associate a logical address designated by the host with an identifier of each of the plurality of blocks, wherein,in the address conversion table,the identifier of the first block is associated with a logical address designated by the host prior to the copying of the first data,the identifier of the second block is not associated with a logical address designated by the ...

Optimized placement of data contained in a garbage collected storage system

A garbage collection process running on a computing device is configured to track the number of garbage collection cycles that storage fragments, called extents, are persisted in storage without being modified or deleted using a lifetime counter that is implemented using metadata. At each garbage collection cycle, the extents are sorted by lifetime values. Old extents (i.e., those existing at the start of the cycle) are bucketed together by lifetime values during garbage collection into new extents (i.e., those being created during the cycle). Thus, each of the new extents includes data having similar lifetime values. The lifetime value for the new extent equals the lowest lifetime value of the old source extent plus one additional increment on the counter. As extents are organized by garbage collection lifetime, placement on storage media can be optimized according to expected endurance requirements.

Memory location remapping and wear-levelling

In one example a system includes a memory, and at least one memory controller to: detect a failed first memory location of the memory, remap the failed first location of the memory to a spare second location of the memory based on a pointer stored at the failed first memory location, and wear-level the memory. To wear-level the memory, the memory controller may copy data from the spare second location of the memory to a third location of the memory, and keep the pointer in the failed first memory location.

Data merge method, memory storage device and memory control circuit unit

A data merge method for a rewritable non-volatile memory module including a plurality of physical units is provided according to an exemplary embodiment of the disclosure. The method includes: obtaining a first logical distance value between a first physical unit and a second physical unit among the physical units, and the first logical distance value reflects a logical dispersion degree between at least one first logical unit mapped by the first physical unit and at least one second logical unit mapped by the second physical unit; and performing a data merge operation according to the first logical distance value, so as to copy valid from a source node to a recycling node.

MANAGING PERSISTENT STORAGE WRITES IN ELECTRONIC SYSTEMS

The apparatus operable to communicate with a memory comprises a persistent write tracker component operable to track frequency of persistent writes to at least one memory location during a time window; a threshold-exceeded detector component responsive to the tracker component and operable to detect excessive persistent writes to the at least one memory location during the time window; and a selective throttle component operable in response to a threshold-exceeded outcome from the detector component to cause selective throttling of persistent writes to the at least one memory location. 1. An apparatus , operable to communicate with a memory , and comprising:a persistent write tracker component operable to track frequency of persistent writes to at least one memory location during a time window;a threshold-exceeded detector component responsive to the tracker component and operable to detect excessive persistent writes to the at least one memory location during the time window; anda selective throttle component operable in response to a threshold-exceeded outcome from the detector component to cause selective throttling of persistent writes to the at least one memory location.2. The apparatus as claimed in claim 1 , wherein the tracker component is operable to track at least one hot zone of persistent write commands.3. The apparatus as claimed in claim 1 , wherein the selective throttle component is operable to signal to at least one higher level in a hardware-firmware-software stack to detect a cause of the excessive persistent writes at a source of persistent write commands.4. The apparatus as claimed in claim 3 , wherein the at least one higher level in a hardware-firmware-software stack is operable to perform at least one of:disabling at least one source of persistent write commands, rate-limiting at least one source of persistent write commands, and performing a remedial action on at least one source of persistent write commands.5. The apparatus as claimed in ...

Operation method of storage device configured to support multi-stream

Disclosed is an operation method of a storage device supporting a multi-stream, which includes receiving an input/output request from an external host, generating a plurality of stream identifier candidates by performing machine learning on the input/output request based on a plurality of machine learning models that are based on different machine learning algorithms, generating a model ratio based on a characteristic of the input/output request, applying the model ratio to the plurality of stream identifier candidates to allocate a final stream identifier for the input/output request, and storing write data corresponding to the input/output request in a nonvolatile memory device of the storage device based on the final stream identifier.

METHOD AND SYSTEM FOR ENHANCING FLASH TRANSLATION LAYER MAPPING FLEXIBILITY FOR PERFORMANCE AND LIFESPAN IMPROVEMENTS

One embodiment facilitates a reduced write amplification. During operation, the system receives, by a computing device, a request to write data to a non-volatile memory. The system writes a first page of the data to a block of the non-volatile memory based on a first physical block address of a destination page of the block, wherein the destination page is a first available page of the block. The system maps, in a data structure by a flash translation layer module of the computing device, a first logical block address of the first page of the data to the first physical block address. 1. A computer-implemented method for facilitating a reduced write amplification , the method comprising:receiving, by a computing device, a request to write data to a non-volatile memory;writing a first page of the data to a block of the non-volatile memory based on a first physical block address of a destination page of the block, wherein the destination page is a first available page of the block; andmapping, in a data structure by a flash translation layer module of the computing device, a first logical block address of the first page of the data to the first physical block address.2. The method of claim 1 , wherein in response to determining that a search in the data structure for the first logical block address of the first page of the data returns the first physical block address claim 1 , the method further comprises:replacing the first physical block address with a new physical block address;marking as invalid the first physical block address; andwriting the first page of the data to the non-volatile memory based on the new physical block address.3. The method of claim 1 , wherein completing the request to write the data to the non-volatile memory comprises writing the data to one or more blocks of the non-volatile memory in a sequential manner by:distributing the data via a plurality of channels of the non-volatile memory; andwriting the data to a respective block of the non- ...