Method and system for controlling refresh in volatile memories

A memory system for controlling memory refresh is provided. An embodiment of the memory system includes a memory configured to operate in a self-refresh mode and an auto-refresh mode, the memory having a plurality of memory locations, and a memory controller configured to access a first one of the memory locations while a second one of the memory locations is being refreshed in the auto-refresh mode. Another embodiment of the memory system includes a memory that can communicate its self refresh address to the memory controller A further embodiment includes a memory controller that can communicate an auto-refresh address to a memory.

Memory apparatuses, computer systems and methods for ordering memory responses

Memory apparatuses that may be used for receiving commands and ordering memory responses are provided. One such memory apparatus includes response logic that is coupled to a plurality of memory units by a plurality of channels and may be configured to receiving a plurality of memory responses from the plurality of memory units. Ordering logic may be coupled to the response logic and be configured to cause the plurality of memory responses in the response logic to be provided in an order based, at least in part, on a system protocol. For example, the ordering logic may enforce bus protocol rules on the plurality of memory responses stored in the response logic to ensure that responses are provided from the memory apparatus in a correct order.

Cache architecture for comparing data

The present disclosure includes apparatuses and methods for a cache architecture. An example apparatus that includes a cache architecture according to the present disclosure can include an array of memory cells configured to store multiple cache entries per page of memory cells; and sense circuitry configured to determine whether cache data corresponding to a request from a cache controller is located at a location in the array corresponding to the request, and return a response to the cache controller indicating whether cache data is located at the location in the array corresponding to the request.

MEMORY HAVING INTERNAL PROCESSORS AND DATA COMMUNICATION METHODS IN MEMORY

Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s). 2. The memory claim 1 , as set forth in claim 1 , wherein the data is transferrable from a first bank in the memory array claim 1 , and wherein the results are transferrable to a second bank in the memory array.3. The memory claim 1 , as set forth in claim 1 , wherein the data is transferrable from a first buffer through a bus to a first bank in the memory array claim 1 , and wherein the results are transferrable to a second buffer via a bus to a second bank in the memory array.4. The memory claim 1 , as set forth in claim 1 , wherein the second internal processor is configured to execute at least part of an instruction to produce the data for the first internal processor claim 1 , and wherein the data is transferrable from the second internal processor to the first internal processor through a bus between a first buffer coupled to the first internal processor and a second buffer coupled to the second internal processor.5. The memory claim 1 , as set forth in claim 1 , wherein the results are transferrable to the ...

Memory having internal processors and data communication methods in memory

Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).

Method and system for minimizing impact of refresh operations on volatile memory performance

A memory system is provided. The system includes a volatile memory, a refresh counter configured to monitor a number of advanced refreshes performed in the volatile memory, and a controller configured to check the refresh counter to determine whether a regularly scheduled refresh can be skipped in response to detecting a request for the regularly scheduled refresh.

Devices and system providing reduced quantity of interconnections

Methods, devices and systems for reducing the quantity of external interconnections of a memory device are disclosed. Implementation of one such method, device and system includes inputting over an address bus a first portion of an address of a next row of memory cells to be activated. The first portion of the address of the next row of memory cells to be activated is embedded in a command related to the previously activated row of memory cells. The next row of memory cells is subsequently activated according to a concurrently received second portion of the address of the next row of memory cells also received over the address bus. The portioning of the address signals can reduce the width of the address bus and, therefore, the number of required respective external interconnections.

GOLF CLUB TRAINING HANDLE

A device for improving a golfer's swing, the device having a training handle for a golf club wherein the golf club has a longitudinal shaft having at its superior end a gripping area and at its inferior end a head, the training handle originating on or immediately inferior to the gripping area and extending perpendicularly from the longitudinal shaft, the handle being oriented such that it is parallel to the longitudinal axis of the golf club head. 1. A device for improving a golfer's swing , the device comprising:a training handle for a golf club wherein the golf club comprises a longitudinal shaft having at its superior end a gripping area and at its inferior end a head, the training handle originating on or immediately inferior to the gripping area and extending perpendicularly from the longitudinal shaft, the handle being oriented such that it is parallel to the longitudinal axis of the golf club head.2. The handle of wherein the handle is of sufficient length to enable gripping by a human hand.3. The handle of wherein the handle is of diameter similar to that of the gripping area.4. The handle of wherein the handle is permanently constructed to the golf club.5. The handle of wherein the handle is removably mounted to the golf club.6. The handle of further having at one end a mounting means for mounting the handle to the golf club shaft.7. The handle of wherein the mounting means is a cylindrical sleeve at one end of the handle claim 6 , wherein the sleeve further can be removably tightened on the golf club shaft.8. The handle of wherein the sleeve is removably tightened by at least one through hole claim 7 , at least one bolt traversing through the holes and at least one nut.9. The handle of wherein the handle further comprises an exterior gripping material.10. A method for improving a golfer's swing claim 1 , the method comprising:mounting a training handle on a golf club wherein the golf club comprises a longitudinal shaft having at its superior end a ...

DEVICES AND SYSTEM PROVIDING REDUCED QUANTITY OF INTERCONNECTIONS

Methods, devices and systems for reducing the quantity of external interconnections of a memory device are disclosed. Implementation of one such method, device and system includes inputting over an address bus a first portion of an address of a next row of memory cells to be activated. The first portion of the address of the next row of memory cells to be activated is embedded in a command related to the previously activated row of memory cells. The next row of memory cells is subsequently activated according to a concurrently received second portion of the address of the next row of memory cells also received over the address bus. The portioning of the address signals can reduce the width of the address bus and, therefore, the number of required respective external interconnections. 1. A memory device , comprising:at least two pages of memory cells; and receive a first portion of an address of a new page of memory cells in combination with a first command; and', 'receive a second portion of the address of the new page of memory cells in combination with a second command to activate the new page of memory cells with an address including the first portion and the second portion., 'a controller, an address bus, and a command bus configured to cooperatively2. The memory device of claim 1 , wherein the at least two pages of memory cells are addressable by a first number of address signals claim 1 , and wherein the address bus includes a second number of address signals claim 1 , which is less than the first number of address signals.3. The memory device of claim 1 , wherein the first command comprises a precharge command claim 1 , in response to which an open page of memory cells is at least partially closed.4. The memory device of claim 1 , wherein the first command comprises a refresh command to refresh at least one other page of memory cells.5. The memory device of claim 1 , further comprising a register to buffer the first portion of the address of the new page of ...

MEMORY APPARATUSES, COMPUTER SYSTEMS AND METHODS FOR ORDERING MEMORY RESPONSES

Memory apparatuses that may be used for receiving commands and ordering memory responses are provided. One such memory apparatus includes response logic that is coupled to a plurality of memory units by a plurality of channels and may be configured to receiving a plurality of memory responses from the plurality of memory units. Ordering logic may be coupled to the response logic and be configured to cause the plurality of memory responses in the response logic to be provided in an order based, at least in part, on a system protocol. For example, the ordering logic may enforce bus protocol rules on the plurality of memory responses stored in the response logic to ensure that responses are provided from the memory apparatus in a correct order. 1. A memory apparatus , comprising:response logic configured to receive a plurality of memory responses; andordering logic coupled to the response logic and configured to cause the plurality of memory responses to be ordered based, at least in part, on a protocol.2. The apparatus of claim 1 , wherein individual ones of the plurality of memory responses comprise a read identification bit and the ordering logic is further configured to cause the plurality of responses to be ordered based claim 1 , at least in part claim 1 , on the respective identification bits.3. The apparatus of claim 1 , further comprising:a queue coupled to the ordering logic, the ordering logic further configured to cause a plurality of commands in the queue to be ordered based, at least in part, on detecting at least one of a page hit and a hazard conflict.4. The apparatus of claim 3 , further comprising:a bank state machine coupled to the queue and configured to receive the plurality of commands from the queue, the bank state machine further configured to provide at least one of the plurality of commands to at least one of a plurality of memory units based, at least in part, on the at least one of a plurality of memory units having an available channel.5. ...

MEMORY, MEMORY CONTROLLERS, AND METHODS FOR DYNAMICALLY SWITCHING A DATA MASKING/DATA BUS INVERSION INPUT

Examples are described herein of dynamic switching of data masking and data bus inversion functionality of a memory input. Both dynamic switching and a static setting for the memory input may be supported in some examples described herein. Use of a command indicating a functionality of the memory input is described. 1. A memory comprising:a plurality of memory cells; masking logic configured to implement data masking; and', 'data bus inversion logic configured to implement data bus inversion; and, 'control logic coupled to an input, wherein the control logic includeswherein the control logic is configured to switch between implementing data masking and implementing data bus inversion during operation of the memory.2. The memory of claim 1 , wherein the memory cells comprise DRAM memory cells.3. The memory of claim 1 , wherein the control logic is configured to switch between implementing data masking and implementing data bus inversion at least in part by selectively coupling one of the masking logic or the data bus inversion logic to the input.4. The memory of claim 1 , wherein the control logic is configured to switch between implementing data masking and implementing data bus inversion responsive to receipt by the memory of a command including a bit indicative of either masking control or data bus inversion functionality.5. The memory of claim 4 , wherein the command comprises a NOP command.6. The memory of claim 4 , wherein the bit is included in a portion of the command associated with an address.7. The memory of claim 4 , further comprising a command decoder configured to receive the command and provide signals to the control logic responsive to the bit.8. The memory of claim 1 , wherein the input comprises a pin.9. The memory of claim 1 , wherein the control logic is configured to switch between the masking logic and the data bus inversion logic persistently.10. The memory of claim 1 , wherein the control logic is configured to switch back to a default ...

SYSTEMS, DEVICES, AND METHODS FOR DATA MIGRATION

Methods, systems, and devices for performing data migration operations using a memory system are described. The memory system may include a component, such as a controller, for facilitating a transfer of data between a first memory device that may implement a first memory technology (e.g., having a relatively fast access speed) and a second memory device that may implement a second memory technology (e.g., having a relatively large capacity). The component may receive an indication of the data migration operation from a host device and may initiate a transfer of data between the first and second memory devices. The controller may include one or more buffers to store data being transferred between the first and second memory devices. In some cases, the transfer of data between the first and second memory devices may occur within the memory system and without being transferred through the host device. 1. A method , comprising:generating a command to transfer a data set from a first memory location within a memory system to a second memory location within the memory system;dividing the command into a set of sub-commands, wherein each sub-command of the set of sub-commands corresponds to a respective portion of the data set; andtransmitting a first subset of the set of sub-commands to the memory system via one or more first channels and a second subset of the set of sub-commands to the memory system via one or more second channels different than the one or more first channels, the first subset of the set of sub-commands associated with data transfer between a first memory device and a second memory device of the memory system and the second subset of the set of sub-commands associated with data transfer between a third memory device and a fourth memory device of the memory system.2. The method of claim 1 , further comprising:determining a mapping between an address associated with a respective portion of the data set and a location within the memory system, wherein the ...

CACHE FILTER

The present disclosure includes apparatuses and methods related to a memory system including a filter. An example apparatus can include a filter to store a number flags, wherein each of the number of flags corresponds to a cache entry and each of the number of flags identifies a portion of the memory device where data of a corresponding cache entry is stored in the memory device. 1. An apparatus , comprising:a cache controller; and 'store a number flags, wherein each of the number of flags corresponds to a cache entry and each of the number of flags identifies a portion of the memory device where data of a corresponding cache entry is stored in the memory device.', 'a cache and a memory device coupled to the cache controller, wherein the cache controller includes a filter configured to2. The apparatus of claim 1 , wherein the memory device is a non-volatile memory device.3. The apparatus of claim 1 , wherein the cache is a DRAM memory device.4. The apparatus of claim 1 , wherein the cache is configured to store a portion of the data stored in the memory device.5. The apparatus of claim 1 , wherein the number of flags indicate a portion of the memory device where data corresponding to a request is located.6. The apparatus of claim 1 , wherein a setting of the number of flags indicate whether the cache is storing valid data corresponding to a request.7. The apparatus of claim 1 , wherein each of the number of flags identifies at least a partial location of data stored in the memory device of a corresponding cache entry.8. An apparatus claim 1 , comprising:a cache controller; anda cache and a memory device coupled to the cache controller, wherein the cache controller includes a filter, wherein the filter includes a number of flags that correspond to a number of cache entries in the cache and wherein the cache controller is configured to determine whether to search the cache for data corresponding to a request based on the number of flags.9. The apparatus of claim 8 , ...

MEDIA MANAGER CACHE EVICTION TIMER FOR READS AND WRITES DURING RESISTIVITY DRIFT

A method for caching memory requests while accounting for a phase change memory cell drift phenomenon is described. The method includes writing first user data to an address in phase change memory cells; setting a timer in a set of data structures to a first value in response to writing the first user data to the phase change memory cells, wherein the data structures are stored outside the phase change memory cells; determining whether the timer corresponding to the first user data has expired; and fulfilling a read request for the address from the set of data structures in response to determining that the timer has not expired. 1. A method for caching memory requests while accounting for a phase change memory cell drift phenomenon , the method comprising:writing first user data to an address in phase change memory cells;setting a timer in a set of data structures to a first value in response to writing the first user data to the phase change memory cells, wherein the set of data structures are stored outside the phase change memory cells;determining whether the timer, corresponding to the first user data has expired; andfulfilling a read request for the address from the set of data structures in response to determining that the timer has not expired.2. The method of claim 1 , further comprising:fulfilling the read request for the address from the phase change memory cells in response to determining that the timer has expired.3. The method of claim 1 , wherein the set of data structures comprise a content addressable memory (CAM) data structure that comprises a first set of entries and a cache data structure that comprises a second set of entries;wherein each entry in the first set of entries references a separate entry in the second set of entries;wherein an entry in the second set of entries comprises the first user data; andwherein an entry in the first set of entries comprises the address, a reference to the entry in the second set of entries, and the timer.4. ...

MEMORY APPARATUSES, COMPUTER SYSTEMS AND METHODS FOR ORDERING MEMORY RESPONSES

Memory apparatuses that may be used for receiving commands and ordering memory responses are provided. One such memory apparatus includes response logic that is coupled to a plurality of memory units by a plurality of channels and may be configured to receiving a plurality of memory responses from the plurality of memory units. Ordering logic may be coupled to the response logic and be configured to cause the plurality of memory responses in the response logic to be provided in an order based, at least in part, on a system protocol. For example, the ordering logic may enforce bus protocol rules on the plurality of memory responses stored in the response logic to ensure that responses are provided from the memory apparatus in a correct order. 1. An apparatus comprising:response logic configured to receive a plurality of read responses and a plurality of write responses; andordering logic coupled to the response logic and configured to cause the plurality of read responses and the plurality of write responses to be ordered,wherein an order of the plurality of write responses is independent of an order of the plurality of read responses.2. The apparatus of claim 1 , wherein the plurality of read responses corresponds to a first plurality of commands and wherein the plurality of write responses corresponds to a second plurality of commands.3. The apparatus of claim 1 , wherein the response logic is further configured to provide the plurality of read responses and the plurality of write responses to a system bus master responsive to the ordering logic causing the plurality of read responses and the plurality of write responses to be ordered.4. The apparatus of claim 1 , wherein the response logic is configured to receive the plurality of read responses and the plurality of write responses based on at least one memory unit of a plurality of memory units having an available logical channel.5. The apparatus of claim 1 , wherein the response logic is configured to store the ...

Command selection policy

Apparatuses and methods related to command selection policy for electronic memory or storage are described. Commands to a memory controller may be prioritized based on a type of command, a timing of when one command was received relative to another command, a timing of when one command is ready to be issued to a memory device, or some combination of such factors. For instance, a memory controller may employ a first-ready, first-come, first-served (FRFCFS) policy in which certain types of commands (e.g., read commands) are prioritized over other types of commands (e.g., write commands). The policy may employ exceptions to such an FRFCFS policy based on dependencies or relationships among or between commands. An example can include inserting a command into a priority queue based on a category corresponding to respective commands, and iterating through a plurality of priority queues in order of priority to select a command to issue.

MEDIA MANAGER CACHE WITH INTEGRATED DRIFT BUFFER

A method to cache memory requests while accounting for phase change memory cell drift is described. The method includes adding, in response to receiving a write memory request from a host system, an entry to a cache that includes user data of the write memory request, wherein the write memory request is directed to a set of phase change memory cells; adding, in response to receiving the write memory request, an entry in a first content-addressable memory (CAM), wherein the entry in the first CAM includes a reference to the entry in the cache that includes the user data of the write memory request; writing the user data of the write memory request to the set of phase change memory cells; and adding an entry to a second CAM, wherein the entry in the second CAM includes a reference to the entry in the cache that includes the user data. 1. A method to cache read and write memory requests while accounting for a phase change memory cell drift phenomenon , the method comprising:adding, in response to receiving a write memory request from a host system, an entry to a cache that includes user data of the write memory request, wherein the write memory request is directed to a set of phase change memory cells;adding, in response to receiving the write memory request, an entry in a first content-addressable memory (CAM), wherein the entry in the first CAM includes a reference to the entry in the cache that includes the user data of the write memory request;writing the user data of the write memory request to the set of phase change memory cells; andadding an entry to a second CAM, wherein the entry in the second CAM includes a reference to the entry in the cache that includes the user data of the write memory request.2. The method of claim 1 , further comprising:evicting the entry in the first CAM such that the entry in the cache is referenced by the second CAM but not referenced in the first CAM after the user data of the write memory request is written to the set of phase ...

MEMORY SEARCHING COMPONENT

An apparatus can include a memory device comprising a memory component and a memory controller that is coupled to the memory component. A memory searching component (MSC) is resident on the apparatus. The MSC can receive an external instruction indicative of performance of an operation to retrieve particular data from the memory component and issue, responsive to receipt of the instruction, a command to the memory controller to cause the memory controller to perform a read request invoking the memory component as part of performance of the operation in the absence of a further external instruction. 1. An apparatus , comprising:a memory device comprising a memory component and a memory controller coupled to the memory component; and receive an external instruction indicative of performance of an operation to retrieve particular data from the memory component; and', 'issue, responsive to receipt of the instruction, a command to the memory controller to cause the memory controller to perform a read request invoking the memory component as part of performance of the operation in the absence of a further external instruction., 'a memory searching component (MSC) resident on the apparatus and configured to2. The apparatus of claim 1 , wherein the MSC is configured to:determine whether the operation was successfully performed; andresponsive to the determination that the operation was successfully performed, transfer the retrieved particular data to circuitry external to the memory device.3. The apparatus of claim 1 , wherein the MSC is configured to:determine whether the operation was not successfully performed; andresponsive to the determination that the operation was not successfully performed, reperform the read request.4. The apparatus of claim 1 , wherein the MSC is configured to receive the signaling indicative of performance of the operation via an abstracted interface such that the operation is performed in a non-deterministic fashion.5. The apparatus of claim 1 , ...

CACHE LINE DATA

The present disclosure includes apparatuses and methods related to a memory system with cache line data. An example apparatus can store data in a number of cache lines in the cache, wherein each of the number of lines includes a number of chunks of data that are individually accessible. 1. An apparatus , comprising:a cache controller; and{'claim-text': [{'claim-text': 'each of the cache lines includes chunks of data that are individually accessible, wherein the chunks of data are portions of the data that are less than a total amount of the data in each of the cache lines;', '#text': 'store data in cache lines in the cache, wherein:'}, {'claim-text': [{'claim-text': 'the portion of the chunks of data is less than a total chunks of data on the first cache line of the cache lines;', '#text': 'read the portion of the chunks of data stored in the first cache line of the cache lines and return the portion of the chunks of data to the cache controller, wherein:'}, 'prioritize particular chunks of data that will remain in the cache lines, wherein a host identifies the chunks of data in the cache that will remain in the cache.'], '#text': 'in response to a request from the cache controller resulting in a hit, wherein the hit indicates the data requested by the cache controller is stored in the cache and the hit includes a portion of the chunks of data on a first cache line of the cache lines:'}], '#text': 'a cache and a memory device coupled to the cache controller, wherein the cache controller is configured to issue commands to cause the cache to:'}2. The apparatus of claim 1 , wherein dirty chunks of data of the first cache line are selected for writing back to the memory device claim 1 , wherein:the dirty chunks of data are the chunks of data that have been modified in the cache and not saved in the memory device; andthe selected dirty chunks of data include chunks of data of the portion of the chunks of data that were the hit and returned to the cache controller when ...

Cache line data

The present disclosure includes apparatuses and methods related to a memory system with cache line data. An example apparatus can store data in a number of cache lines in the cache, wherein each of the number of lines includes a number of chunks of data that are individually accessible.

CACHE BUFFER

The present disclosure includes apparatuses and methods related to a cache buffer. An example apparatus can store data associated with a request in one of a number of buffers and service a subsequent request for data associated with the request using the one of the number of buffers. The subsequent request can be serviced while the request is being serviced by the cache controller. 1. An apparatus , comprising:a cache controller; and 'store data associated with a request in one of the number of buffers and service a subsequent request for data associated with the request using the one of the number of buffers.', 'a cache and a memory device coupled to the cache controller, wherein the cache controller includes a number of buffers and wherein the cache controller configured to2. The apparatus of claim 1 , wherein the subsequent request is serviced while the request is being serviced.3. The apparatus of claim 1 , wherein the request evicts data from the cache.4. The apparatus of claim 1 , wherein the subsequent request reads data from the buffer.5. The apparatus of claim 1 , wherein data is kept in buffer until the request is serviced.6. The apparatus of claim 1 , wherein the data is located by searching the buffer.7. The apparatus of claim 1 , wherein cache line is not locked and the subsequent request does not wait for lock release before servicing the subsequent request.8. An apparatus claim 1 , comprising:a cache controller; and 'store data associated with a request in one of the number of buffers and service a first subsequent request for data associated with the first subsequent request using another one of the number of buffers and service a second subsequent request using the another one of the number of buffers.', 'a cache and a memory device coupled to the cache controller, wherein the cache controller includes a number of buffers and wherein the cache controller configured to9. The apparatus of claim 8 , wherein the one of the number of buffers is masked ...

CACHE IN A NON-VOLATILE MEMORY SUBSYSTEM

A first request to perform an operation at an address associated with a media is obtained. The operation is issued to a plurality of cache divisions, wherein each cache division comprises a cache controller and a cache memory. A location in another memory associated with the first request is updated, the location in the other memory including a plurality of indicators corresponding to a status of the operation with each of the plurality of cache divisions. Based on one or more responses from the cache division(s), a response to the first request is sent. 1. A method comprising:obtaining a first request to perform an operation at an address associated with a media;issuing the operation to a plurality of cache divisions, wherein each cache division comprises a cache controller and a cache memory;updating a location in another memory associated with the first request, the location in the other memory including a plurality of indicators corresponding to a status of the operation with each of the plurality of cache divisions; andsending a response to the first request.2. The method of claim 1 , wherein the response is sent prior to completing the operation with a first cache division in the plurality of cache divisions.3. The method of claim 1 , further comprising arbitrating for access to issue the operation to each of the cache controllers within the plurality of cache divisions.4. The method of claim 1 , further comprising writing to a selected location in a first cache division in the plurality of cache divisions when the plurality of indicators in the location in the other memory indicate that a check of each cache division resulted in a miss.5. The method of claim 4 , further comprising selecting claim 4 , based on a cache replacement policy claim 4 , the selected location.6. The method of claim 4 , wherein the writing comprises arbitrating for access to the first cache division.7. The method of claim 4 , wherein prior to writing to the selected location: ...

LOW LATENCY CACHE FOR NON-VOLATILE MEMORY IN A HYBRID DIMM

Systems and methods are disclosed including a first memory device, a second memory device coupled to the first memory device, where the second memory device has a lower access latency than the first memory device and acts as a cache for the first memory device. A processing device operatively coupled to the first and second memory devices can track access statistics of segments of data stored at the second memory device, the segments having a first granularity, and determine to update, based on the access statistics, a segment of data stored at the second memory device from the first granularity to a second granularity. The processing device can further retrieve additional data associated with the segment of data from the first memory device and store the additional data at the second memory device to form a new segment having the second granularity. 1. A system comprising:a first memory device;a second memory device coupled to the first memory device, wherein the second memory device has a lower access latency than the first memory device and is used as a cache for the first memory device; and tracking access statistics of segments of data stored at the second memory device, wherein the segments have a first granularity;', 'determining to update, based on the access statistics, a segment of data stored at the second memory device from the first granularity to a second granularity;', 'retrieving additional data associated with the segment of data from the first memory device; and', 'storing the additional data at the second memory device to form a new segment comprising the additional data and the segment of data, wherein the new segment has the second granularity., 'a processing device, operatively coupled to the first and second memory devices, to perform operations comprising2. The system of claim 1 , wherein the first memory device claim 1 , second memory device and the processing device are included within a hybrid dual in-line memory module claim 1 , and ...

MEMORY PROTOCOL

The present disclosure includes apparatuses and methods related to a memory protocol. An example apparatus can execute a read command that includes a first chunk of data and a second chunk of data by assigning a first read identification (RID) number to the first chunk of data and a second RID number to the second chunk of data, sending the first chunk of data and the first RID number to a host, and sending the second chunk of data and the second RID number to the host. The apparatus can be a non-volatile dual in-line memory module (NVDIMM) device.

CACHE OPERATIONS IN A HYBRID DUAL IN-LINE MEMORY MODULE

A system includes a first memory component of a first memory type, a second memory component of a second memory type with a higher access latency than the first memory component, and a third memory component of a third memory type with a higher access latency than the first and second memory components. The system further includes a processing device to identify a section of a data page stored in the first memory component, and access patterns associated with the data page and the section of the data page. The processing device determines to cache the data page at the second memory component based on the access patterns, copying the section of the data page stored in the first memory component to the second memory component. The processing device then copies additional sections of the data page stored at the third memory component to the second memory component. 1. A system comprising:a first memory component comprising a first memory type;a second memory component comprising a second memory type coupled to the first memory component, wherein the second memory type has a higher access latency than the first memory component;a third memory component of a third memory type coupled to the first memory component and the second memory component, wherein the third memory component has a higher access latency than the first and second memory components; and identifying a section of a data page stored in the first memory component;', 'identifying access patterns associated with the data page and the section of the data page;', 'determining to cache the data page at the second memory component based on the access patterns;', 'copying the section of the data page stored in the first memory component to the second memory component; and', 'copying one or more additional sections of the data page stored at the third memory component to the second memory component., 'a processing device, operatively coupled with the first memory component, the second memory component, and the ...

Data migration for memory operation

Apparatuses and methods for performing data migration operations are disclosed. An apparatus may include at least two interfaces, a first interface supporting data migration operations and a second interface supporting access operations associated with a host device. In some cases, the access operations may be a signal or protocol according to an industry standard or specification (e.g., a DRAM interface specification). The second interface may facilitate supporting industry standard applications, while the first interface supporting data migration operations may provide improved bandwidth for migrating data within the apparatus. The apparatus may include a buffer coupled with the interface and a bank cluster including two or more banks of memory cells. When a host device addresses a bank of the bank cluster, the apparatus may perform one or more data migration operations using the buffer and a different bank of the bank cluster.

Command selection policy

Apparatuses and methods related to command selection policy for electronic memory or storage are described. Commands to a memory controller may be prioritized based on a type of command, a timing of when one command was received relative to another command, a timing of when one command is ready to be issued to a memory device, or some combination of such factors. For instance, a memory controller may employ a first-ready, first-come, first-served (FRFCFS) policy in which certain types of commands (e.g., read commands) are prioritized over other types of commands (e.g., write commands). The policy may employ exceptions to such an FRFCFS policy based on dependencies or relationships among or between commands. An example can include inserting a command into a priority queue based on a category corresponding to respective commands, and iterating through a plurality of priority queues in order of priority to select a command to issue.

Command selection policy

Apparatuses and methods related to command selection policy for electronic memory or storage are described. Commands to a memory controller may be prioritized based on a type of command, a timing of when one command was received relative to another command, a timing of when one command is ready to be issued to a memory device, or some combination of such factors. For instance, a memory controller may employ a first-ready, first-come, first-served (FRFCFS) policy in which certain types of commands (e.g., read commands) are prioritized over other types of commands (e.g., write commands). The policy may employ exceptions to such an FRFCFS policy based on dependencies or relationships among or between commands. An example can include inserting a command into a priority queue based on a category corresponding to respective commands, and iterating through a plurality of priority queues in order of priority to select a command to issue.

DATA TRANSFER FOR WEAR-LEVELING

Methods, systems, and devices for data transfer for wear-leveling are described. Data may be stored in pages of banks and the banks may be grouped into bank clusters. A host device may address one bank of a bank cluster at a time. Data may be transferred from a bank to a buffer or a different bank cluster for wear-leveling purposes and this data transfer may take place opportunistically while a second bank, which may be in the same bank cluster, is being accessed based on an access command. 1. A method , comprising:receiving, at a memory device from a host device, an access command to access a first data set stored in a first bank of a first bank cluster of the memory device during an access period;accessing, during the access period, the first data set stored in the first bank of the first bank cluster based at least in part on receiving the access command from the host device;accessing, during the access period, a second data set stored in a second bank of the first bank cluster as part of a data migration operation based at least in part on accessing the first data set; andtransferring, during the access period, the second data set between the second bank of the first bank cluster and a different storage location based at least in part on accessing the second data set.2. The method of claim 1 , further comprising:determining that the data migration operation associated with the first bank cluster is waiting to be performed, wherein the second data set is accessed based at least in part on the determination.3. The method of claim 1 , further comprising:performing the data migration operation during at least a portion of the access period based at least in part on the host device accessing the first data set stored in the first bank of the first bank cluster; andperforming the data migration operation during at least a portion of a second access period based at least in part on the host device accessing a destination bank cluster for the second data set.4. The ...

DYNAMIC ACCESS GRANULARITY IN A CACHE MEDIA

A method comprising receiving a memory access request comprising an address of data to be accessed and determining an access granularity of the data to be accessed based on the address of the data to be accessed. The method further includes, in response to determining that the data to be accessed has a first access granularity, generating first cache line metadata associated with the first access granularity and in response to determining that the data to be accessed has a second access granularity, generating second cache line metadata associated with the second access granularity. The method further includes storing the first cache line metadata and the second cache line metadata in a single cache memory component. 1. A method comprising:receiving a memory access request comprising an address of data to be accessed;determining an access granularity of the data to be accessed based on the address of the data to be accessed;in response to determining that the data to be accessed has a first access granularity, generating first cache line metadata associated with the first access granularity;in response to determining that the data to be accessed has a second access granularity, generating second cache line metadata associated with the second access granularity; andstoring the first cache line metadata and the second cache line metadata in a single cache memory component.2. The method of claim 1 , wherein generating the cache line metadata associated with the first access granularity comprises:setting a mode bit of the first cache line metadata identifying the first access granularity; andsetting one or more bits of the first cache line metadata associated with the address and indicating a valid status and a dirty status of a first cache line.3. The method of claim 1 , wherein generating the cache line metadata associated with the second access granularity comprises:setting a mode bit of the second cache line metadata identifying the second access granularity; ...

MEMORY PROTOCOL

The present disclosure includes apparatuses and methods related to a memory protocol. An example apparatus can perform operations on a number of block buffers of the memory device based on commands received from a host using a block configuration register, wherein the operations can read data from the number of block buffers and write data to the number of block buffers on the memory device. 1. An apparatus , comprising:a memory device; and 'perform operations on the memory device based on a read command received from a host that includes a read increment value, wherein the read increment value indicates to the controller a value by which to increment a counter that is used to assign a memory device read identification number to the read command.', 'a controller coupled to the memory device configured to2. The apparatus of claim 1 , wherein the host also increments a host read identification number by the read increment value.3. The apparatus of claim 1 , wherein the read increment value allows the host to continue to send read commands to the apparatus when the apparatus has not completed execution of previously sent read commands.4. The apparatus of claim 1 , wherein the read increment value allows the apparatus to execute read commands in an order that in determined by the controller.5. The apparatus of claim 1 , wherein the controller is configured to assign the memory read identification number to the read command received by the memory device by incrementing a counter by 1 plus the read increment value included in the read command sent from the host.6. The apparatus of claim 1 , wherein the controller is configured to skip memory device read identification numbers that have not been executed by incrementing the counter according to the read increment value.7. The apparatus of claim 1 , wherein the controller is configured to send an indication to the host that the read command has been executed.8. An apparatus claim 1 , comprising: 'perform operations on the ...

NON-DETERMINISTIC MEMORY PROTOCOL

The present disclosure includes apparatuses and methods related to a non-deterministic memory protocol. An example apparatus can perform operations on the memory device based on commands received from a host according to a protocol, wherein the protocol includes non-deterministic timing of the operations. The memory device can be a non-volatile dual in-line memory module (NVDIMM) device. 1. A method , comprising:receiving, from a host via a command/address bus of a non-volatile dual inline memory module (NVDIMM), at least one read command and at least one write command;receiving, from the host via a data bus of the NVDIMM, data to be written to the NVDIMM; andtransmitting, to the host from a set of pins of the NVDIMM designated for write credit signaling, a write credit signal that is based at least in part on writing the data received from the host.2. The method of claim 1 , further comprising:transmitting, to the host via the data bus of the NVDIMM in a same data packet as the write credit signal, data that is responsive to the at least one read command.3. The method of claim 1 , wherein the write credit signal comprises write credit feedback that provides an indication to the host to increment a write credit counter at the host.4. The method of claim 1 , wherein the write credit signal comprises an indication that the at least one write command was executed.5. The method of claim 1 , further comprising:receiving the at least one write command at a write buffer of the NVDIMM, wherein the write credit signal comprises an indication of available space in the write buffer.6. The method of claim 5 , further comprising:transmitting the write credit signal in response to another command from the host.7. An apparatus claim 5 , comprising:a command/address bus configured to transmit read and write commands from a host to a volatile memory or a non-volatile memory, or both;a data bus configured to communicate data associated with a read or write command between the host ...

MEMORY PROTOCOL

The present disclosure includes apparatuses and methods related to a memory protocol. An example apparatus can perform operations on a number of block buffers of the memory device based on commands received from a host using a block configuration register, wherein the operations can read data from the number of block buffers and write data to the number of block buffers on the memory device. 1. An apparatus , comprising:a memory device; and 'perform commands on the memory device based a barrier command received from a host, wherein the barrier command indicates that commands previously received by the memory device are to be performed before commands received by the memory device subsequent to the barrier command.', 'a controller coupled to the memory device configured to2. The apparatus of claim 1 , wherein the barrier command is a write barrier command that indicates write commands previously received by the memory device are to be performed before write commands received by the memory device subsequent to the write barrier command.3. The apparatus of claim 1 , wherein the barrier command is a read barrier command that indicates read commands previously received by the memory device are to be performed before read commands received by the memory device subsequent to the read barrier command.4. The apparatus of claim 1 , wherein the barrier command programs a register on the controller.5. The apparatus of claim 1 , wherein the barrier command is indicated by a bit in a column command.6. The apparatus of claim 1 , wherein the barrier command indicates that commands previously received by the memory device are to be performed in the order in which the commands were received by the controller.7. A method for performing commands claim 1 , comprising:receiving a barrier command and a first number of commands at a memory device; andperforming commands received prior to the first number of commands before peforming the first number of command in response to receiving the ...

MEMORY PROTOCOL

The present disclosure includes apparatuses and methods related to a memory protocol. An example apparatus can execute a read command that includes a first chunk of data and a second chunk of data by assigning a first read identification (RID) number to the first chunk of data and a second RID number to the second chunk of data, sending the first chunk of data and the first RID number to a host, and sending the second chunk of data and the second RID number to the host. The apparatus can be a non-volatile dual in-line memory module (NVDIMM) device. 1. An apparatus , comprising:a memory device; and 'execute a read command that includes a first chunk of data and a second chunk of data by assigning a first read identification (RID) number to the first chunk of data and a second RID number to the second chunk of data, sending the first chunk of data and the first RID number to a host, and sending the second chunk of data and the second RID number to the host.', 'a controller coupled to the memory device configured to2. The apparatus of claim 1 , wherein the memory device is a non-volatile dual in-line memory module (NVDIMM) device.3. The apparatus of claim 1 , wherein the first chunk of data is sent to the host before the second chunk of data in response to the read command including an address of the first chuck of data.4. The apparatus of claim 1 , wherein the first chunk of data is sent to the host before the second chunk of data in response to the read command including an indication that the first chuck of data is to be sent before any other chunk of data associated with the read command.5. The apparatus of claim 1 , wherein the first chunk of data is sent to the host before the second chunk of data in response to the read command including a register address to locate a register that indicates an order in which chunks of data associated with the read command are to be returned.6. The apparatus of claim 1 , wherein the first chunk of data is sent to the host before ...

MEMORY HAVING INTERNAL PROCESSORS AND METHODS OF CONTROLLING MEMORY ACCESS

Memories having internal processors and methods of data communication within such memories are provided. One such memory may include a fetch unit configured to substantially control performing commands on a memory array based on the availability of banks to be accessed. The fetch unit may receive instructions including commands indicating whether data is to be read from or written to a bank, and the address of the data to be read from or written to the bank. The fetch unit may perform the commands based on the availability of the bank. In one embodiment, control logic communicates with the fetch unit when an activated bank is available. In another implementation, the fetch unit may wait for a bank to become available based on timers set to when a previous command in the activated bank has been performed. 1. A memory comprising:an internal processor configured to execute instructions;a memory array comprising one or more memory banks, wherein the memory array is configured to store information in the one or more memory banks and to provide the information to the internal processor; anda fetch unit configured to receive an instruction comprising an address in the memory array and a command to perform an operation at the address, and to substantially control access to the memory array by ensuring only one operation at a time is performed on a specific memory bank comprising the address, wherein the fetch unit is external to the internal processor.2. The memory of claim 1 , comprising a memory control device communicatively coupled to the fetch unit claim 1 , wherein the memory control device is configured to receive the command and the address in the memory array from the fetch unit and to decode the command and the address claim 1 , wherein the memory control is separate from the fetch unit.3. The memory of claim 1 , wherein the fetch unit is configured to perform the operation by reading data from the address or writing data to the address.4. The memory of claim 1 , ...

DEVICES AND SYSTEM PROVIDING REDUCED QUANTITY OF INTERCONNECTIONS

Methods, devices and systems for reducing the quantity of external interconnections of a memory device are disclosed. Implementation of one such method, device and system includes inputting over an address bus a first portion of an address of a next row of memory cells to be activated. The first portion of the address of the next row of memory cells to be activated is embedded in a command related to the previously activated row of memory cells. The next row of memory cells is subsequently activated according to a concurrently received second portion of the address of the next row of memory cells also received over the address bus. The portioning of the address signals can reduce the width of the address bus and, therefore, the number of required respective external interconnections.

ENHANCED DUPLICATE WRITE DATA TRACKING FOR CACHE MEMORY

Data is stored at a cache portion of a cache memory of a memory sub-system responsive to a request to perform a write operation to write the data. A duplicate copy of the data is stored at a write buffer portion of the cache memory. The cache memory is partitioned into the cache portion and the write buffer portion. An entry that maps a location of the duplicate copy of the data stored at the write buffer portion of the cache memory to a location of the data stored at the cache portion of the cache memory is recorded in a write buffer record. 1. A method , comprising:storing data at a cache portion of a cache memory of a memory sub-system responsive to a request to perform a write operation to write the data;storing a duplicate copy of the data at a write buffer portion of the cache memory, wherein the cache memory is partitioned into the cache portion and the write buffer portion; andrecording, in a write buffer record, an entry that maps a location of the duplicate copy of the data stored at the write buffer portion of the cache memory to a location of the data stored at the cache portion of the cache memory.2. The method of claim 1 , further comprising:performing a memory operation at the memory sub-system based at least in part on the write buffer record.3. The method of claim 2 , wherein performing the memory operation at the memory sub-system based at least in part on the write buffer record comprises:receiving a request to perform a read operation to read the data stored at a first sector of a first cache line of the cache portion of the cache memory;detecting an unrecoverable error at the first cache line;identifying the duplicate copy of the data stored at a second sector of a second cache line of the write buffer portion of the cache memory based on the entry of the write buffer record; andsending the duplicate copy of the data stored at the second sector of the second cache line responsive to the request to perform the read operation.4. The method of ...

SYSTEMS, DEVICES, TECHNIQUES, AND METHODS FOR DATA MIGRATION

Methods, systems, and devices for performing data migration operations using a memory system are described. The memory system may include a data migration component, such as a driver, for facilitating the transfer of data between a first memory device that may implement a first memory technology (e.g., having a relatively fast access speed) and a second memory device that may implement a second memory technology (e.g., having a relatively large capacity). The component may indicate the data migration operation to a second component (e.g., a controller) of the memory system. The second component may initiate the transfer of data between the first memory device and the second memory device based on the receiving the indication of the data migration operation. In some cases, the transfer of data between the first memory device and the second memory device may occur within the memory system without being transferred through a host device. 1. A method , comprising:receiving a first indication that data stored in a first memory device of a memory system is to be transferred to a second memory device as part of a data migration operation;generating, based at least in part on the data migration operation, one or more commands each comprising a request for a portion of the data to be migrated;transmitting, to the memory system, a first command containing the request for the portion of data to be migrated; andreceiving, from the memory system, a second indication of a completion of the first command.2. The method of claim 1 , further comprising:selecting a data size for channel interleaving from a plurality of data sizes; andidentifying a size of each portion of the data based at least in part on the data size for the channel interleaving, wherein the one or more commands are generated based at least in part on identifying the size of each portion of the data.3. The method of claim 1 , further comprising:transmitting, to the memory system, a second command containing a second ...

Systems, devices, and methods for data migration

Methods, systems, and devices for performing data migration operations using a memory system are described. The memory system may include a component, such as a controller, for facilitating a transfer of data between a first memory device that may implement a first memory technology (e.g., having a relatively fast access speed) and a second memory device that may implement a second memory technology (e.g., having a relatively large capacity). The component may receive an indication of the data migration operation from a host device and may initiate a transfer of data between the first and second memory devices. The controller may include one or more buffers to store data being transferred between the first and second memory devices. In some cases, the transfer of data between the first and second memory devices may occur within the memory system and without being transferred through the host device.

DATA MIGRATION FOR MEMORY OPERATION

Apparatuses and methods for performing data migration operations are disclosed. An apparatus may include at least two interfaces, a first interface supporting data migration operations and a second interface supporting access operations associated with a host device. In some cases, the access operations may be a signal or protocol according to an industry standard or specification (e.g., a DRAM interface specification). The second interface may facilitate supporting industry standard applications, while the first interface supporting data migration operations may provide improved bandwidth for migrating data within the apparatus. The apparatus may include a buffer coupled with the interface and a bank cluster including two or more banks of memory cells. When a host device addresses a bank of the bank cluster, the apparatus may perform one or more data migration operations using the buffer and a different bank of the bank cluster. 1. A method , comprising:receiving a command to transfer data between a first bank of a bank cluster and a different bank;determining that a host device addresses a second bank of the bank cluster during an access period; andtransferring, during the access period and based at least in part on the command, the data between the first bank and a buffer configured to store the data associated with the first bank as part of a data migration operation.2. The method of claim 1 , further comprising:transmitting, based at least in part on receiving the command to transfer the data, a status of the buffer indicating that the buffer includes the data to store in the first bank; andstoring the data in the first bank based at least in part on transmitting the status, wherein the data is transferred between the buffer and the first bank of the bank cluster based at least in part on storing the data in the first bank and receiving the command to transfer the data.3. The method of claim 2 , further comprising:receiving the data to store in the buffer in ...

DATA MIGRATION DYNAMIC RANDOM ACCESS MEMORY

Apparatuses and methods for performing data migration operations are disclosed. An apparatus may include at least two interfaces, a first interface supporting data migration operations and a second interface supporting access operations associated with a host device. In some cases, the access operations may be a signal or protocol according to an industry standard or specification (e.g., a DRAM interface specification). The second interface may facilitate supporting industry standard applications, while the first interface supporting data migration operations may provide improved bandwidth for migrating data within the apparatus. The apparatus may include a buffer coupled with the interface and a bank cluster including two or more banks of memory cells. When a host device addresses a bank of the bank cluster, the apparatus may perform one or more data migration operations using the buffer and a different bank of the bank cluster. 1. An apparatus , comprising:an interface configured to communicate with a controller as part of a data migration operation;a buffer coupled with the interface and configured to store data as part of the data migration operation; anda bank cluster comprising a first bank and a second bank and coupled with the buffer, the first bank configured to be accessed by a memory controller during an access period as part of an access operation, the second bank configured to transfer data with the buffer during the access period as part of the data migration operation concurrent with the first bank being accessed by the memory controller, wherein the buffer is configured to transmit, prior to the first bank being accessed, an indication that the buffer stores data to be written to a bank of the bank cluster or read from the buffer.2. The apparatus of claim 1 , further comprising:a second interface coupled with the bank cluster and configured to communicate commands or data with the memory controller as part of the data migration operation.3. The ...

Eviction of a cache line based on a modification of a sector of the cache line

An indication to perform an eviction operation on a cache line in a cache can be received. A determination can be made as to whether at least one sector of the cache line is associated with invalid data. In response to determining that at least one sector of the cache line is associated with invalid data, a read operation can be performed to retrieve valid data associated with the at least one sector. The at least one sector of the cache line that is associated with the invalid data can be modified based on the valid data. Furthermore, the eviction operation can be performed on the cache line with the modified at least one sector.

NON-DETERMINISTIC MEMORY PROTOCOL

The present disclosure includes apparatuses and methods related to a non-deterministic memory protocol. An example apparatus can perform operations on the memory device based on commands received from a host according to a protocol, wherein the protocol includes non-deterministic timing of the operations. The memory device can be a non-volatile dual in-line memory module (NVDIMM) device. 1. A method , comprising:transmitting to a host, utilizing a set of pins of a non-volatile dual inline memory module (NVDIMM) separate from a command/address bus across which read commands and write commands are received, a write credit identification (WID) signal identifying a write command of the write commands received from the host via the command/address bus; andtransmitting with the WID, via the set of pins, a write credit signal to the host, wherein the write credit signal is based at least in part on a non-deterministically timed writing of the write command.2. The method of claim 1 , including transmitting claim 1 , to the host via the data bus of the NVDIMM in a same data packet as the write credit signal claim 1 , data that is responsive to at least one of the read commands.3. The method of claim 2 , wherein the data that is responsive to at least one of the read commands includes a read ready command indicating data associated with the at least one of the read commands has been located and is ready to be sent to the host.4. The method of claim 3 , wherein the read ready command may be transmitted to the host prior to locating data associated with another read command that was received prior to the command the at least one of the read commands.5. The method of claim 2 , further comprising transmitting the data packet responsive to receiving a read send indicator from the host indicating that the host is ready to receive the data that is responsive to the at least one of the read commands.6. The method of claim 1 , further comprising receiving the write command at a write ...

MEMORY PROTOCOL WITH COMMAND PRIORITY

The present disclosure includes apparatuses and methods related to a memory protocol with command priority. An example apparatus can execute a command that includes a read identification (RID) number based on a priority assigned to the RID number in a register. The apparatus can be a non-volatile dual in-line memory module (NVDIMM) device. 1. An apparatus , comprising:a memory device; and 'execute a command that includes a read identification (RID) number based on a priority assigned to the RID number in a register.', 'a controller coupled to the memory device configured to2. The apparatus of claim 1 , wherein the memory device is a non-volatile dual in-line memory module (NVDIMM) device.3. The apparatus of claim 1 , wherein the priority assigned to the RID number is changed by reprogramming the register.4. The apparatus of claim 1 , wherein the command is executed before another command based on the priority assigned to the RID number.5. The apparatus of claim 4 , wherein the another command was sent to the memory device for execution prior to the command being sent to the memory device for execution.6. The apparatus of claim 1 , wherein the register includes a plurality of ranges of RID numbers and wherein each of the plurality of ranges of RID numbers are assigned priority information.7. The apparatus of claim 1 , wherein the controller determines when to execute the command based on the RID number and priority information in the register.8. An apparatus comprising:a memory device; and receive a first command having a first read identification (RID) number, a second command having a second RID number, and a third command having a third RID number; and', 'execute the first command, the second command, and the third command in an order based on priority information in a register., 'a controller coupled to the memory device configured to9. The apparatus of claim 8 , wherein the register is programmed to high priority for a first range of RIDs that includes the first ...

MEMORY MODULE INTERFACES

The present disclosure includes apparatuses and methods related to memory module interfaces. A memory module, which may include volatile memory or nonvolatile memory, or both, may be configured to communicate with a host device via one interface and to communicate with another memory module using a different interface. Memory modules may thus be added or removed from a system without impacting a PCB-based bus to the host, and memory modules may communicate with one another without accessing a bus to the host. The host interface may be configured according to one protocol or standard, and other interfaces between memory modules may be configured according to other protocols or standards. 1. An apparatus , comprising:a first memory module that comprises one or more types of memory media, including at least one non-volatile memory array;a first interface coupled to the non-volatile memory array and couplable to a host, the first interface configured to transfer data or commands, or both, between the first memory module and the host; anda second interface coupled to the non-volatile memory array and couplable to a second memory module, the second interface configured to transfer data or commands, or both, between the first memory module and the second memory module.2. The apparatus of claim 1 , wherein the memory module comprises a DRAM array coupled to the non-volatile memory array.3. The apparatus of claim 1 , wherein the non-volatile memory array comprises 3D XPoint memory.4. The apparatus of claim 1 , wherein the non-volatile memory array comprises NAND.5. The apparatus of claim 1 , wherein the first interface is couplable to the host via a first bus configured for NVDIMM-P.6. The apparatus of claim 6 , wherein the first bus is located on a PCB.7. The apparatus of claim 1 , wherein the second interface is couplable to the memory module via a second bus configured for NVDIMM-P and/or another interface and wherein the second bus is located off a PCB.8. A system claim ...

MEMORY MODULE CONTROLLER

Apparatuses and methods related to a memory module controller are disclosed. An example apparatus, such as a memory module, includes a first interface coupled to a host, a second interface coupled to another memory module. The memory module includes a controller configured to communicate with the host via the first interface and communicate with the other memory module via the second interface. In some examples, the first and second interfaces are configured according to different standards or protocols. The controller controls access to memory on the memory module. The controller may be configured to receive commands from a direct memory access (DMA) module. In some examples, the other memory module connected via the second interface includes a local controller and memory of a different type. In some examples, the memory modules include non-volatile or volatile memories, or both. 1. An apparatus , comprising:a plurality of memory devices;a controller coupled to and configured to control access operations to the plurality of memory devices;a first interface coupled to the controller and couplable to a host, the controller configured to communicate with the host via the first interface; and;a second interface coupled to the controller and couplable to a remote memory module, the controller configured to communicate with the remote memory module via the second interface, determine whether data associated with a command is located in the plurality of memory devices;', 'transfer the data from the plurality of memory devices to the host in response to determining that the data is located in the plurality of memory devices; and', 'transfer the command to the remote memory module in response to determining that the data is not located in the plurality of memory devices., 'wherein the controller is configured to2. The apparatus of claim 1 , wherein the apparatus is a dual in-line memory module claim 1 , the plurality of memory devices comprises dynamic random access memory ...

MODULE PROCESSING RESOURCE

The present disclosure includes apparatuses and methods related to a module processing resource. An example apparatus can include a first interface coupled to a host, and a second interface coupled to a memory module. The apparatus may be configured to process data between the host and the memory module via a processing resource. 1. An apparatus , comprising:a processing resource configured to process data transferred between a memory module and a host that comprises at least one of a central processing unit (CPU), graphics processing unit (GPU), or a general purpose GPU (GPGPU), or any combination thereofa first interface coupled to the processing resource and couplable to the host; anda second interface coupled to the processing resource and couplable to the memory module.2. The apparatus of claim 1 , wherein the processing resource is configured to reorder data from the host for storage on the memory module.3. The apparatus of claim 1 , wherein the processing resource is configured to filter the data read from the memory module to the host.4. The apparatus of claim 1 , wherein the first interface is couplable to the host via a first bus and wherein the first bus is located on a PCB.5. The apparatus of claim 1 , wherein the second interface is couplable to the memory module via a second bus and wherein the second bus is located off a PCB.6. The apparatus of claim 1 , wherein the first interface is configured for a first communication protocol and the second interface is a configured for a second communication protocol that is different from the first communication protocol.7. The apparatus of claim 6 , wherein the first interface is configured for at least one of NVDIMM-P claim 6 , NVDIMM-N claim 6 , DDR5 claim 6 , or DDR4 claim 6 , or any combination thereof.8. The apparatus of claim 6 , wherein the second interface is configured to write data to or read data from a 3D XPoint array.9. A system claim 6 , comprising:a first memory module with a first interface, a ...

MEMORY CONTROLLER

The present disclosure includes apparatuses and methods related to a memory controller, such as a host memory controller. An example apparatus can include a host memory controller coupled to a first memory device and a second memory device via a channel, wherein the host memory controller is configured to send a first number of commands to the first memory device using a first device select signal, and send a second number of commands to the second memory device using a second device select signal.

MEMORY PROTOCOL

The present disclosure includes apparatuses and methods related to a memory protocol. An example apparatus can execute a read command that includes a first chunk of data and a second chunk of data by assigning a first read identification (RID) number to the first chunk of data and a second RID number to the second chunk of data, sending the first chunk of data and the first RID number to a host, and sending the second chunk of data and the second RID number to the host. The apparatus can be a non-volatile dual in-line memory module (NVDIMM) device. 1. An apparatus , comprising:a memory device; and receive a read command;', 'execute the read command by sending data associated with the read command and a data packet that includes a read identification (RID) number., 'circuitry coupled to the memory device configured to2. The apparatus of claim 1 , wherein the circuitry is configured to execute the read command by sending a read ready signal in response to receiving the read command.3. The apparatus of claim 2 , wherein the read ready signal indicates the data associated with the command is ready to send.4. The apparatus of claim 1 , wherein the circuitry is configured to execute the read command by sending the data associated with the command and the data packet in response to receiving a send command.5. The apparatus of claim 1 , wherein the data packet include write credit information.6. The apparatus of claim 1 , wherein the data packet includes ECC information.7. The apparatus of claim 1 , wherein the data packet includes block identification information to indicate a number of chunks of data included in the data associated with the command.8. An apparatus claim 1 , comprising:a memory device; and receive a read command;', 'send a read ready command to indicate data associated with the read command is ready to send; and', 'send the data associated with the command and a data packet to the host., 'circuitry coupled to the memory device configured to9. The apparatus ...

MEMORY MODULE INTERFACES

The present disclosure includes apparatuses and methods related to memory module interfaces. A memory module, which may include volatile memory or nonvolatile memory, or both, may be configured to communicate with a host device via one interface and to communicate with another memory module using a different interface. Memory modules may thus be added or removed from a system without impacting a PCB-based bus to the host, and memory modules may communicate with one another without accessing a bus to the host. The host interface may be configured according to one protocol or standard, and other interfaces between memory modules may be configured according to other protocols or standards. 1. An apparatus , comprising:a first memory module coupled to a host via a first bus on a printed circuitry board (PCB) and comprising one or more types of memory media;a second memory module coupled to the first memory module via a second bus off the PCB; andan interface configured to transfer data, commands, or both, between the first memory module and the second memory module.2. The apparatus of claim 1 , wherein at least one of the one or more types of memory media comprises a non-volatile memory array.3. The apparatus of claim 1 , wherein the interface is configured to transfer data claim 1 , commands claim 1 , or both claim 1 , in response to receiving a read request claim 1 , a write request claim 1 , or both.4. The apparatus of claim 1 , further comprising a different interface configured to transfer data claim 1 , commands claim 1 , or both claim 1 , between the first memory module and the host in response to receiving a read request claim 1 , a write request claim 1 , or both.5. The apparatus of claim 1 , further comprising a different interface configured to transfer data claim 1 , commands claim 1 , or both claim 1 , between the second memory module and the host in response to receiving a read request claim 1 , a write request claim 1 , or both.6. The apparatus of claim 1 ...

Memory protocol with command priority

The present disclosure includes apparatuses and methods related to a memory protocol with command priority. An example apparatus can execute a command that includes a read identification (RID) number based on a priority assigned to the RID number in a register. The apparatus can be a non-volatile dual in-line memory module (NVDIMM) device.

TRANSACTION IDENTIFICATION

The present disclosure includes apparatuses and methods related to transaction identification. An example apparatus can determine a transaction identification (TID) associated with a command by comparing a host transaction identification (TID) record with a memory device transaction identification (TID) record. 1. A method , comprising:receiving a first command with a first transaction identification (TID);receiving a second command with a second transaction identification (TID);storing the first and second TIDs in a memory device; andproviding a memory device transaction identification (TID) record from the memory device for determining a corrupt transaction identification (TID), wherein the memory device TID record includes the first and second TIDs.2. The method of claim 1 , further comprising determining the corrupt TID using the memory device TID record.3. The method of claim 1 , further comprising providing a first output data including a first operation result based on the first command and a third transaction identification (TID).4. The method of claim 3 , wherein the third TID corresponds to the first TID.5. The method of claim 1 , further comprising providing a second output data including a second operation result based on the second command and a fourth transaction identification (TID).6. The method of claim 5 , wherein the fourth TID corresponds to the second TID.7. The method of claim 1 , further comprising storing the first and second TIDS in a buffer of the memory device.8. A method claim 1 , comprising:receiving a first command with a first transaction identification (TID);receiving a second command with a second transaction identification (TID);storing the first and second TIDs in a memory device;providing a first output data from the memory device, the first output data comprising a first operation result based on the first command and a third transaction identification (TID) accompanied with the first operation result, the third TID corresponding ...

Cache architecture for comparing data

The present disclosure includes apparatuses and methods for a cache architecture. An example apparatus that includes a cache architecture according to the present disclosure can include an array of memory cells configured to store multiple cache entries per page of memory cells; and sense circuitry configured to determine whether cache data corresponding to a request from a cache controller is located at a location in the array corresponding to the request, and return a response to the cache controller indicating whether cache data is located at the location in the array corresponding to the request.

EVICTION OF A CACHE LINE BASED ON A MODIFICATION OF A SECTOR OF THE CACHE LINE

An indication to perform an eviction operation on a cache line in a cache can be received. A determination can be made as to whether at least one sector of the cache line is associated with invalid data. In response to determining that at least one sector of the cache line is associated with invalid data, a read operation can be performed to retrieve valid data associated with the at least one sector. The at least one sector of the cache line that is associated with the invalid data can be modified based on the valid data. Furthermore, the eviction operation can be performed on the cache line with the modified at least one sector. 1. A method comprising:receiving an indication to perform an eviction operation on a cache line in a cache;determining whether at least one sector of a plurality of sectors of the cache line is associated with invalid data;in response to determining that at least one sector of the plurality of sectors of the cache line is associated with invalid data, performing, by a processing device, a read operation to retrieve valid data associated with the at least one sector;modifying the at least one sector of the cache line that is associated with the invalid data based on the valid data; andperforming the eviction operation on the cache line with the modified at least one sector.2. The method of claim 1 , wherein the performing of the eviction operation on the cache line with the modified at least one sector corresponds to writing data of the plurality of sectors of the modified cache line to one or more memory components.3. The method of claim 1 , wherein the read operation is performed at one or more memory components claim 1 , and wherein the eviction operation stores data of the cache line at the one or more memory components.4. The method of claim 1 , wherein performing the read operation to retrieve the valid data associated with the at least one sector comprises:determining that the valid data is stored in a second cache; andperforming the ...

Mobility Vehicle Enclosure

A mobility vehicle enclosure (MVE) that is secured to a rear location on an automobile, such as a car, truck or van, and encloses a mobility vehicle during storage or transportation. A first design of the MVE has a structure including an upper surface, a lower surface, a front side wall, a rear side wall and a left side wall. The structure is preferably rectangular shaped, although any shape can be used depending on the requirements of the application. The front side wall is secured to the structure by an upper securing device and at least one hinge that is attached at a lower edge of the front wall and a front edge of the lower surface. The hinge allows the front side wall to be lowered downward to ground level, thereby creating a ramp on which a mobility vehicle enters or exits the structure. A second design of the MVE is similar to the first, except the surfaces and side walls of the structure are all secured together by hinges. By using the hinges, the surfaces and side walls can be folded on top of each other, thereby creating a vertical stack that can be stored in a small space when the MVE is not in use. To assemble the second design, the surfaces and side walls are unfolded, and the final side wall is secured to the initial side wall. The number of side walls used is determined by the required shape of the structure. Both designs also have a MVE to automobile securing apparatus, which is based on a conventional trailer hitch, and a rear light assembly which provides rear light on the MVE when the MVE is in place blocking the automobile's rear lights. 1. A mobility vehicle enclosure (MVE) that is secured to a rear location on an automobile and encloses a mobility vehicle during storage or transportation , wherein said MVE is comprised of a structure including an upper surface , a lower surface , a front side wall , a rear side wall , a right side wall and a left side wall , wherein said front side wall is secured to said structure by an upper securing device ...

Memory protocol with programmable buffer and cache size

The present disclosure includes apparatuses and methods related to a memory protocol with programmable buffer and cache size. An example apparatus can program a resister to define a size of a buffer in memory, store data in the buffer in a first portion of the memory defined by the register, and store data in a cache in a second portion of the memory.

TRANSACTION IDENTIFICATION

The present disclosure includes apparatuses and methods related to transaction identification. An example apparatus can determine a transaction identification (TID) associated with a command by comparing a host transaction identification (TID) record with a memory device transaction identification (TID) record. 1. An apparatus , comprising:a memory device; and 'determine a transaction identification (TID) associated with a command by comparing a host transaction identification (TID) record with a memory device transaction identification (TID) record.', 'a host device coupled to the memory device, wherein the host device includes a host controller configured to2. The apparatus of claim 1 , wherein the host device is configured to send the determined TID to the memory device.3. The apparatus of claim 1 , wherein the host is configured to generate transaction identifications (TIDs) as identifiers.4. The apparatus of claim 1 , wherein the host is configured to determine a transmission error based on an error detection scheme used in a TID transmission.5. The apparatus of claim 1 , wherein the host determines the TID associated with the command by identifying a TID in the memory device TID record that is missing from the host TID record.6. The apparatus of claim 1 , wherein the memory device is a non-volatile dual in-line memory module (NVDIMM).7. An apparatus claim 1 , comprising:a memory device; and query the memory device with a status request in response to receiving a transmission error associated with a command;', 'receive a memory device transaction identification (TID) record from the memory device; and', 'determine a transaction identification (TID) associated with the command by comparing a host transaction identification (TID) record with the memory device TID record., 'a host device coupled to the memory device, wherein the host device includes a host controller configured to8. The apparatus of claim 7 , wherein the memory device is configured to send the ...

NON-DETERMINISTIC MEMORY PROTOCOL

The present disclosure includes apparatuses and methods related to a non-deterministic memory protocol. An example apparatus can perform operations on the memory device based on commands received from a host according to a protocol, wherein the protocol includes non-deterministic timing of the operations. The memory device can be a non-volatile dual in-line memory module (NVDIMM) device. 1. An apparatus , comprising:a memory device; and 'perform operations on the memory device based on commands received from a host according to a protocol, wherein the protocol includes non-deterministic timing of the operations.', 'a controller coupled to the memory device configured to2. The apparatus of claim 1 , wherein the memory device is a non-volatile dual in-line memory module (NVDIMM) device.3. The apparatus of claim 1 , wherein the protocol provides the host direct access to the memory device.4. The apparatus of claim 1 , wherein the protocol includes the memory device executing operations in an order that is different than an order in which the commands are received by the memory device.5. The apparatus of claim 1 , wherein the commands received from the host can include two or more commands that are sent without timing delays between the commands.6. The apparatus of claim 1 , wherein the controller can include a write buffer and a read buffer.7. An apparatus comprising:a memory device; and receive a first read command from a host;', 'send a first read ready signal to the host in response to the controller having data associated with the first read command ready to send to the host;', 'receive a first read send signal from the host in response to the host receiving the first read ready signal from the controller, wherein the host can send the first read send signal any time the host is ready to receive the data associated with the first read command; and', 'send the data associated with the first read command and a first read identification (RID) signal to the host on a ...

COMMAND SELECTION POLICY WITH READ PRIORITY

Apparatuses and methods related to command selection policy for electronic memory or storage are described. Commands to a memory controller may be prioritized based on a type of command, a timing of when one command was received relative to another command, a timing of when one command is ready to be issued to a memory device, or some combination of such factors. For instance, a memory controller may employ a first-ready, first-come, first-served (FRFCFS) policy in which certain types of commands (e.g., read commands) are prioritized over other types of commands (e.g., write commands). The policy may employ exceptions to such an FRFCFS policy based on dependencies or relationships among or between commands. An example can include inserting a command into a priority queue based on a category corresponding to respective commands, and iterating through a plurality of priority queues in order of priority to select a command to issue. 1. A method for command selection , comprising:receiving a read command to a memory controller, wherein the read command comprises an address for a bank and a channel of a memory device;inserting the read command into a queue of the memory controller;blocking a first number of write commands to the bank;issuing, to the memory device, an activation command associated with the read command;blocking a second number of write commands to the channel; andissuing the read command to the memory device.2. The method of claim 1 , further comprising blocking the second number of write commands after a predetermined duration of time.3. The method of claim 2 , wherein the predetermined duration of time comprises a difference between a row-to-column delay and a write-to-read delay.4. The method of claim 2 , wherein the predetermined duration of time is selected based on a read-after-write dependence associated with the read command.5. The method of claim 4 , further comprising selecting the predetermined duration of time to include a difference between a ...

COMMAND SELECTION POLICY WITH READ PRIORITY

Apparatuses and methods related to command selection policy for electronic memory or storage are described. Commands to a memory controller may be prioritized based on a type of command, a timing of when one command was received relative to another command, a timing of when one command is ready to be issued to a memory device, or some combination of such factors. For instance, a memory controller may employ a first-ready, first-come, first-served (FRFCFS) policy in which certain types of commands (e.g., read commands) are prioritized over other types of commands (e.g., write commands). The policy may employ exceptions to such an FRFCFS policy based on dependencies or relationships among or between commands. An example can include inserting a command into a priority queue based on a category corresponding to respective commands, and iterating through a plurality of priority queues in order of priority to select a command to issue. 120-. (canceled)21. An apparatus , comprising:a timer unit configured to generate timestamps for activation commands provided to a memory device in association with implementing a command selection policy; and responsive to receiving a read command, blocking a first number of write commands to a bank;', 'responsive to blocking the first number of write commands, issuing, to the memory device, an activation command associated with the read command, wherein the read command comprises an address of the bank and a channel of the memory device;', 'responsive to issuing the activation command, blocking a second number of write commands to the channel after an expiration of a predetermined duration of time that is based on memory device timing parameters; and', 'responsive to blocking the second number of write commands, issuing the read command to the memory device., 'command selection logic configured to implement the command selection policy by22. The apparatus of claim 21 , wherein the memory device timing parameters include a row-to-column ...

CACHE ARCHITECTURE

The present disclosure includes apparatuses and methods for a cache architecture. An example apparatus that includes a cache architecture according to the present disclosure can include an array of memory cells configured to store multiple cache entries per page of memory cells; and sense circuitry configured to determine whether cache data corresponding to a request from a cache controller is located at a location in the array corresponding to the request, and return a response to the cache controller indicating whether cache data is located at the location in the array corresponding to the request. 1. An apparatus , comprising:an array of memory cells configured to store multiple cache entries per page of memory cells; and determine whether cache data corresponding to a request from a cache controller is located at a location in the array corresponding to the request; and', 'return a response to the cache controller indicating whether cache data is located at the location in the array corresponding to the request., 'sense circuitry configured to2. The apparatus of claim 1 , wherein the apparatus is configured to return cache data corresponding to the request in response to a determination that the cache data is located at the location in the array corresponding to the request.3. The apparatus of claim 1 , wherein the apparatus is configured to write cache data corresponding to the request in the array of memory cells in response to a status of a validity indicator indicating that valid data is not at the location in the array corresponding to the request.4. The apparatus of claim 1 , wherein the apparatus is configured to evict dirty data from the array in response to a status of a validity indicator indicating that valid data is at the location in the array corresponding to the request.5. The apparatus of claim 4 , wherein the apparatus is configured to write cache data corresponding to the request at the location in the array subsequent to evicting dirty data ...

MEMORY PROTOCOL

The present disclosure includes apparatuses and methods related to a memory protocol. An example apparatus can perform operations on a number of block buffers of the memory device based on commands received from a host using a block configuration register, wherein the operations can read data from the number of block buffers and write data to the number of block buffers on the memory device. 1. An apparatus , comprising:a memory device; and 'perform operations on a number of block buffers of the memory device based on commands received from a host using a block configuration register, wherein the operations can read data from the number of block buffers and write data to the number of block buffers on the memory device.', 'a controller coupled to the memory device configured to2. The apparatus of claim 1 , wherein the block configuration register includes a block buffer address register that includes a start address claim 1 , an end address claim 1 , and status information for each of the number of block buffers.3. The apparatus of claim 1 , wherein the block configuration register includes a target address register that includes a target address for each of the number of block buffers.4. The apparatus of claim 1 , wherein the block configuration register includes a status register that includes status information for each of the number of block buffers.5. The apparatus of claim 1 , wherein the host sends commands to the controller to program the block configuration register setting a start address for each of the number of block buffers claim 1 , an end address for each of the number of block buffers claim 1 , and a corresponding target address in an array of memory cells on the memory device.6. The apparatus of claim 5 , wherein the host sends commands to the controller to write data to the number of block buffers.7. The apparatus of claim 6 , wherein the host sends commands to the controller to commit a portion of data from the number of block buffers to the ...

Cache architecture for comparing data

The present disclosure includes apparatuses and methods for a cache architecture. An example apparatus that includes a cache architecture according to the present disclosure can include an array of memory cells configured to store multiple cache entries per page of memory cells; and sense circuitry configured to determine whether cache data corresponding to a request from a cache controller is located at a location in the array corresponding to the request, and return a response to the cache controller indicating whether cache data is located at the location in the array corresponding to the request.

NON-DETERMINISTIC MEMORY PROTOCOL

The present disclosure includes apparatuses and methods related to a non-deterministic memory protocol. An example apparatus can perform operations on the memory device based on commands received from a host according to a protocol, wherein the protocol includes non-deterministic timing of the operations. The memory device can be a non-volatile dual in-line memory module (NVDIMM) device. 1. An apparatus , comprising:a memory device; and 'perform operations on the memory device based on commands received from a host according to a protocol, wherein the protocol includes non-deterministic timing of the operations.', 'a controller coupled to the memory device configured to2. The apparatus of claim 1 , wherein the memory device is a non-volatile dual in-line memory module (NVDIMM) device.3. The apparatus of claim 1 , wherein the protocol provides the host direct access to the memory device.4. The apparatus of claim 1 , wherein the protocol includes the memory device executing operations in an order that is different than an order in which the commands are received by the memory device.5. The apparatus of claim 1 , wherein the commands received from the host can include two or more commands that are sent without timing delays between the commands.6. The apparatus of claim 1 , wherein the controller can include a write buffer and a read buffer.7. An apparatus comprising:a memory device; and receive a first read command from a host;', 'send a first read ready signal to the host in response to the controller having data associated with the first read command ready to send to the host;', 'receive a first read send signal from the host in response to the host receiving the first read ready signal from the controller, wherein the host can send the first read send signal any time the host is ready to receive the data associated with the first read command; and', 'send the data associated with the first read command and a first read identification (RID) signal to the host on a ...

MEMORY CONTROLLER

The present disclosure includes apparatuses and methods related to a memory controller, such as a host memory controller. An example apparatus can include a host memory controller coupled to a first memory device and a second memory device via a channel, wherein the host memory controller is configured to send a first number of commands to the first memory device using a first device select signal, and send a second number of commands to the second memory device using a second device select signal. 1. An apparatus , comprising: send a first number of commands to the first memory device using a first device select signal; and', 'send a second number of commands to the second memory device using a second device select signal., 'a host memory controller coupled to a first memory device and a second memory device via a channel, wherein the host memory controller is configured to2. The apparatus of claim 1 , wherein the channel includes data lines and command lines that couple the host memory controller to the first memory device and the second memory device.3. The apparatus of claim 1 , wherein the channel includes a first device select line that couples the host memory controller to the first memory device.4. The apparatus of claim 1 , wherein the channel includes a second device select line that couples the host memory controller to the second memory device.5. The apparatus of claim 1 , wherein the first number of commands are sent to the first memory device on commands lines shared by the first memory device and the second memory device in response the host memory controller sending the first device select signal.6. The apparatus of claim 1 , wherein the second number of commands are sent to the second memory device on commands lines shared by the first memory device and the second memory device in response the host memory controller sending the second device select signal based on timing parameters associated with the second memory device.7. The apparatus of claim 6 ...

CACHE FILTER

The present disclosure includes apparatuses and methods related to a memory system including a filter. An example apparatus can include a filter to store a number flags, wherein each of the number of flags corresponds to a cache entry and each of the number of flags identifies a portion of the memory device where data of a corresponding cache entry is stored in the memory device. 1. An apparatus , comprising:a cache; and 'locate data, corresponding to a request for data, in the cache based on a number of bits of the request that correspond to a cache entry of a plurality of cache entries in the cache and identify a portion of the memory device where data corresponding to the request is located in the memory device.', 'a memory device coupled to the cache, wherein the cache is configured to2. The apparatus of claim 1 , wherein the memory device is a non-volatile memory device and the cache is a DRAM memory device.3. The apparatus of claim 1 , wherein the cache is configured to store a portion of the data that is stored in the memory device.4. The apparatus of claim 1 , wherein each of the number of bits indicate a particular portion of the memory device where data corresponding to the request is located.5. The apparatus of claim 1 , wherein the number of bits indicate whether the cache is storing valid data corresponding to the request.6. The apparatus of claim 1 , wherein the number of bits identify at least a partial location of data corresponding to the request in the memory device.7. The apparatus of claim 1 , wherein the cache is configured to locate data in the cache corresponding to the request in response to the number of bits indicating the data corresponding to the request is in the cache.8. The apparatus of claim 1 , wherein the cache controller is configured to locate data in the memory device corresponding to the request in response to the number of bits indicating the data corresponding to the request is not in the cache.9. An apparatus claim 1 , ...

DATA MIGRATION DYNAMIC RANDOM ACCESS MEMORY

Apparatuses and methods for performing data migration operations are disclosed. An apparatus may include at least two interfaces, a first interface supporting data migration operations and a second interface supporting access operations associated with a host device. In some cases, the access operations may be a signal or protocol according to an industry standard or specification (e.g., a DRAM interface specification). The second interface may facilitate supporting industry standard applications, while the first interface supporting data migration operations may provide improved bandwidth for migrating data within the apparatus. The apparatus may include a buffer coupled with the interface and a bank cluster including two or more banks of memory cells. When a host device addresses a bank of the bank cluster, the apparatus may perform one or more data migration operations using the buffer and a different bank of the bank cluster. 1. A method , comprising:transmitting an indication corresponding to a state of a buffer;accessing, after the indication is transmitted, a first bank of a bank cluster; andtransferring data, concurrent with accessing the first bank, between the buffer and a second bank of the bank cluster based at least in part on the indication.2. The method of claim 1 , further comprising:communicating a command or data with a controller as part of a data migration operation that comprises transferring the data between the buffer and the second bank.3. The method of claim 1 , further comprising:transmitting an indication that the buffer is available for performing one or more data migration operations based at least in part on completing a first data migration operation that comprises transferring the data between the buffer and the second bank.4. The method of claim 1 , wherein accessing the first bank of the bank cluster comprises:receiving an access command from a controller; andaccessing the first bank of the bank cluster during an access operation ...

Device for proportioning a lubricant

Dynamic access granularity in a cache media

A method comprising receiving a memory access request comprising an address of data to be accessed and determining an access granularity of the data to be accessed based on the address of the data to be accessed. The method further includes, in response to determining that the data to be accessed has a first access granularity, generating first cache line metadata associated with the first access granularity and in response to determining that the data to be accessed has a second access granularity, generating second cache line metadata associated with the second access granularity. The method further includes storing the first cache line metadata and the second cache line metadata in a single cache memory component.

APPARATUS FOR DOSING LUBRICANT.

EN UN APARATO PARA LA DOSIFICACION DE LUBRIFICANTES CON UN REGULADOR DE CORRIENTE DE DOS PASOS Y POR LO MENOS DOS ESTRANGULADORES (101, 113) CON ANCHO DE ABERTURA DIFERENTE, PUDIENDO CONECTARSE EN FILA EL QUE PRESENTA UNA ANCHURA DE ABERTURA MENOR (113) CON EL DE MAYOR ABERTURA (101). ESTE ULTIMO SE COLOCA EN LA CARCASA UNIDA AL REGULADOR DE DOS PASOS, CONECTANDO CON LA ABERTURA DE ENTRADA DEL REGULADOR, QUE A SU VEZ ESTA UNIDO A LA CONEXION DE APROVISIONAMIENTO. EL SEGUNDO ESTRANGULADOR (113) CUYA ABERTURA DE ENTRADA ESTA UNIDA CON ESTE ESPACIO (10), SE PUEDE REGULAR EN UNA POSICION DE EFECTIVIDAD Y OTRA SIN EFECTIVIDAD MEDIANTE UN ACCIONMIENTO DE AJUSTE. IN AN APPARATUS FOR THE DOSING OF LUBRICANTS WITH A TWO-STEP CURRENT REGULATOR AND AT LEAST TWO SQUEEZERS (101, 113) WITH A DIFFERENT OPENING WIDTH, MAY BE CONNECTED IN ROW, WHICH PRESENTS A LOWER OPENING WIDTH (113) OF GREATER OPENING (101). THE LAST ONE IS PLACED IN THE HOUSING ATTACHED TO THE TWO-STEP REGULATOR, CONNECTING WITH THE INLET OPENING OF THE REGULATOR, WHICH IN turn IS JOINED TO THE PROVISIONING CONNECTION. THE SECOND STRANGULATOR (113) WHOSE INLET OPENING IS LINKED WITH THIS SPACE (10), CAN BE REGULATED IN A POSITION OF EFFECTIVENESS AND ANOTHER WITHOUT EFFECTIVENESS THROUGH AN ADJUSTMENT OPERATION.

Data migration dynamic random access memory

Apparatuses and methods for performing data migration operations are disclosed. An apparatus may include at least two interfaces, a first interface supporting data migration operations and a second interface supporting access operations associated with a host device. In some cases, the access operations may be a signal or protocol according to an industry standard or specification (e.g., a DRAM interface specification). The second interface may facilitate supporting industry standard applications, while the first interface supporting data migration operations may provide improved bandwidth for migrating data within the apparatus. The apparatus may include a buffer coupled with the interface and a bank cluster including two or more banks of memory cells. When a host device addresses a bank of the bank cluster, the apparatus may perform one or more data migration operations using the buffer and a different bank of the bank cluster.

Command selection policy with read priority

Apparatuses and methods related to command selection policy for electronic memory or storage are described. Commands to a memory controller may be prioritized based on a type of command, a timing of when one command was received relative to another command, a timing of when one command is ready to be issued to a memory device, or some combination of such factors. For instance, a memory controller may employ a first-ready, first-come, first-served (FRFCFS) policy in which certain types of commands (e.g., read commands) are prioritized over other types of commands (e.g., write commands). The policy may employ exceptions to such an FRFCFS policy based on dependencies or relationships among or between commands. An example can include inserting a command into a priority queue based on a category corresponding to respective commands, and iterating through a plurality of priority queues in order of priority to select a command to issue.

Flow control system for lubrication devices

Data migration dynamic random access memory

Apparatuses and methods for performing data migration operations are disclosed. An apparatus may include at least two interfaces, a first interface supporting data migration operations and a second interface supporting access operations associated with a host device. In some cases, the access operations may be a signal or protocol according to an industry standard or specification (e.g., a DRAM interface specification). The second interface may facilitate supporting industry standard applications, while the first interface supporting data migration operations may provide improved bandwidth for migrating data within the apparatus. The apparatus may include a buffer coupled with the interface and a bank cluster including two or more banks of memory cells. When a host device addresses a bank of the bank cluster, the apparatus may perform one or more data migration operations using the buffer and a different bank of the bank cluster.

Method and electrical apparatus for destroying medical instruments

The invention provides an apparatus and method for destroying the metallic portion of an elongate medical instrument, such as a hypodermic needle or scalpel for example. One aspect of the invention relates to a method of destroying a metallic portion of a medical instrument having a longitudinal axis, a tip and shaft, the method comprising the steps of: locating the instrument in a position wherein the tip of the instrument electrically engages a contact surface of a first and second electrode, each electrode having the electrical contact surface disposed in opposition and separated by a gap, and each electrode in electrical contact with power source means for creating an electrical potential difference between the electrodes, the potential differencebeing sufficient to induce electrical resistance burning of the tip of the instrument when an electrical current is passed through the tip between the electrodes; and progressively advancing the instrument and the electrodes longitudinally relative to each other, whereby the burning of the tip of the instrument progressively consumes the shaft as the burning tip advances from the start position to a finish position continuously in electrical contact with each electrode. A device is also provided to carry out the method.

Command scheduling component for memory

A system includes a processing device that determines whether a memory bank is active and adds an activate command for a row of the memory bank accessed by an oldest command for the memory bank to a command scheduler in response to determining the memory bank is not active. The processing device determines whether the row of the memory bank has a corresponding row command in response to determining the memory bank is active. The processing device determines whether a close page mode is enabled or an open row timer has expired on the row and adds a precharge command to the command scheduler in response to determining the close page mode is enabled or the open row timer has expired. The processing device executes a command in the command scheduler based on a priority of commands included in the command scheduler.

Access tracking in memory

An access tracker configured to receive a request to access a page, determine whether a page identification (ID) associated with the page is in the access tracker, increment an access count of the page in response to determining the page ID is in the access tracker, sort a number of page IDs based on an access count of each page ID, and determine whether a different page is hot or cold in response to sorting the number of page IDs.

Memory having internal processors and data communication methods in memory

Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).

Cold data identification

A method comprising directing, via a memory manager, an address associated with data to be written to a cold memory map, receiving the data at a memory device, and writing the data to the memory device in response to the memory manager identifying the data as cold data in response to writing the address associated with the data to the cold memory map.

Microporous filter sheet

Memory protocol

The present disclosure includes apparatuses and methods related to a memory protocol. An example apparatus can perform operations on a number of block buffers of the memory device based on commands received from a host using a block configuration register, wherein the operations can read data from the number of block buffers and write data to the number of block buffers on the memory device.

Tlb access monitoring

An apparatus includes circuitry couplable to a host system and a memory device. The circuitry is configured to determine whether a page table maintained on the circuitry includes a physical address of the memory device corresponding to a virtual address associated with a TLB fill request from the host system. Responsive to determining that the page table includes the physical address, the circuitry provides signaling indicative of a completion to the TLB fill request to the host system, prefetch a page of data at the physical address from the memory device using the physical address from the page table, and provide signaling indicative of the page of data to the host system.

Cache architecture

The present disclosure includes apparatuses and methods for a cache architecture. An example apparatus that includes a cache architecture according to the present disclosure can include an array of memory cells configured to store multiple cache entries per page of memory cells; and sense circuitry configured to determine whether cache data corresponding to a request from a cache controller is located at a location in the array corresponding to the request, and return a response to the cache controller indicating whether cache data is located at the location in the array corresponding to the request.

Geraet zur schmierstoffdosierung.

Memory module interfaces

The present disclosure includes apparatuses and methods related to memory module interfaces. A memory module, which may include volatile memory or nonvolatile memory, or both, may be configured to communicate with a host device via one interface and to communicate with another memory module using a different interface. Memory modules may thus be added or removed from a system without impacting a PCB-based bus to the host, and memory modules may communicate with one another without accessing a bus to the host. The host interface may be configured according to one protocol or standard, and other interfaces between memory modules may be configured according to other protocols or standards.

Memory protocol with command priority

The present disclosure includes apparatuses and methods related to a memory protocol with command priority. An example apparatus can execute a command that includes a read identification (RID) number based on a priority assigned to the RID number in a register. The apparatus can be a non-volatile dual in-line memory module (NVDIMM) device.

Memory protocol with command priority

The present disclosure includes apparatuses and methods related to a memory protocol with command priority. An example apparatus can execute a command that includes a read identification (RID) number based on a priority assigned to the RID number in a register. The apparatus can be a non-volatile dual in-line memory module (NVDIMM) device.

Memory protocol with command priority

Outstanding transaction monitoring for memory sub-systems

A system includes a first controller configured to adjust a count of a number of first transactions and adjust a count of a number of second transactions. The count of the number of first transactions and the count of the number of second transactions are adjusted when a first transaction or second transaction is either received or executed by a second controller. The second controller is coupled to the first controller and is configured to limit the number of first transactions to a particular quantity of outstanding first transactions, limit the number of second transactions to a particular quantity of outstanding second transactions, and limit a number of total transactions to a particular quantity of outstanding total transactions.

Eviction of a cache line based on a modification of a sector of the cache line

An indication to perform an eviction operation on a cache line in a cache can be received. A determination can be made as to whether at least one sector of the cache line is associated with invalid data. In response to determining that at least one sector of the cache line is associated with invalid data, a read operation can be performed to retrieve valid data associated with the at least one sector. The at least one sector of the cache line that is associated with the invalid data can be modified based on the valid data. Furthermore, the eviction operation can be performed on the cache line with the modified at least one sector.

Dynamically sized redundant write buffer with sector-based tracking

Exemplary methods, apparatuses, and systems include detecting an operation to write dirty data to a cache. The cache is divided into a plurality of channels. In response to the operation, the dirty data is written to a first cache line in the cache, the first cache line being accessed via a first channel. Additionally, a redundant copy of the dirty data is written to a second cache line in the cache. The second cache line serves as a redundant write buffer and is accessed via a second channel, the first and second channels differing from one another. A metadata entry for the second cache line is updated to reference a location of the dirty data in the first cache line.

Command selection policy

Apparatuses and methods related to command selection policy for electronic memory or storage are described. Commands to a memory controller may be prioritized based on a type of command, a timing of when one command was received relative to another command, a timing of when one command is ready to be issued to a memory device, or some combination of such factors. For instance, a memory controller may employ a first-ready, first-come, first-served (FRFCFS) policy in which certain types of commands (e.g., read commands) are prioritized over other types of commands (e.g., write commands). The policy may employ exceptions to such an FRFCFS policy based on dependencies or relationships among or between commands. An example can include inserting a command into a priority queue based on a category corresponding to respective commands, and iterating through a plurality of priority queues in order of priority to select a command to issue.

Access tracking in memory

An access tracker configured to receive a request to access a page, determine whether a page identification (ID) associated with the page is in the access tracker, increment an access count of the page in response to determining the page ID is in the access tracker, sort a number of page IDs based on an access count of each page ID, and determine whether a different page is hot or cold in response to sorting the number of page IDs.

Memory module interfaces

The present disclosure includes apparatuses and methods related to memory module interfaces. A memory module, which may include volatile memory or nonvolatile memory, or both, may be configured to communicate with a host device via one interface and to communicate with another memory module using a different interface. Memory modules may thus be added or removed from a system without impacting a PCB-based bus to the host, and memory modules may communicate with one another without accessing a bus to the host. The host interface may be configured according to one protocol or standard, and other interfaces between memory modules may be configured according to other protocols or standards.

Cache line data

The present disclosure includes apparatuses and methods related to a memory system with cache line data. An example apparatus can store data in a number of cache lines in the cache, wherein each of the number of lines includes a number of chunks of data that are individually accessible.

Memory device security and row hammer mitigation

Systems, methods, and apparatus for memory device security and row hammer mitigation are described. A control mechanism may be implemented in a front-end and/or a back-end of a memory sub-system to refresh rows of the memory. A row activation command having a row address at control circuitry of a memory sub-system and incrementing a first count of a row counter corresponding to the row address stored in a content addressable memory (CAM) of the memory sub-system may be received. Control circuitry may determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); the second count may be incremented each time the CAM is full. A refresh command to the row address may be issued when a determination is made that the first count is greater than the RHT minus the second count.

Interleaved cache prefetching

A method includes receiving, at a direct memory access (DMA) controller of a memory device, a first command from a first cache controller coupled to the memory device to prefetch first data from the memory device and sending the prefetched first data, in response to receiving the first command, to a second cache controller coupled to the memory device. The method can further include receiving a second command from a second cache controller coupled to the memory device to prefetch second data from the memory device, and sending the prefetched second data, in response to receiving the second command, to a third cache controller coupled to the memory device.

Aliased row hammer detector

An energy-efficient and area-efficient, mitigation of errors in a memory media device that are caused by row hammer attacks and the like is described. The detection of errors is deterministically performed while maintaining, in an SRAM, a number of row access counters that is smaller than the total number of rows protected in the memory media device. The reduction of the number of required counters is achieved by aliasing a plurality of rows that are being protected to each counter. The mitigation may be implemented on a per-bank basis, per-channel basis or per-memory media device basis. The memory media device may be DRAM.

Memory sub-system address mapping

A method includes accessing a first memory component of a memory sub-system via a first interface, accessing a second memory component of the memory sub-system via a second interface, and transferring data between the first memory component and the second memory component via the first interface. The method further includes initially writing data in the first memory component via a first address window and accessing data in the second memory component via a second address window in response to caching the data in first memory component to the second memory component, wherein caching the data in the first memory component to the second component includes changing an address for the data from the first address window to the second address window.