SECURE CONTENT DISTRIBUTION

In an example, a method of securing content is described. The method may include instantiating a content server on a client device. The method may also include operating the content server to retrieve content identified by a Uniform Resource Identifier (URI). The method may also include serving the content from the content server to a content renderer on the client device. The content renderer may be configured to render the content at the client device and to prohibit saving the content in the clear on the client device. 1. A method of securing content , the method comprising:instantiating a content server on a client device;operating the content server to retrieve content identified by a Uniform Resource Identifier (URI); andserving the content from the content server to a content renderer on the client device, wherein the content renderer is configured to render the content at the client device and to prohibit saving the content in the clear on the client device.2. The method of claim 1 , wherein the content server is configured to prohibit serving the content to any client except the client device including the content renderer.3. The method of claim 1 , further comprising launching the content renderer claim 1 , wherein launching the content renderer includes:launching the content renderer as a thread separate from the content server; orloading a viewer library corresponding to the content renderer on the client device.4. The method of claim 1 , further comprising performing an authentication handshake between the content renderer and the content server prior to serving the content to the content renderer.5. The method of claim 4 , wherein performing an authentication handshake comprises at least one of:deriving a session token from a shared key established between the content server and the content renderer when the content server and the content renderer are two threads derived from the same process;authenticating the content renderer and content server using ...

CONTENT DISTRIBUTION AND AGGREGATION

In an example, a method for secure publication of content is described. The method may include encrypting content with a media key. The method may also include providing the encrypted content to a client device associated with a private key and a public key. The private key may be stored at the client device. The method may also include encrypting the media key with the public key. The method may also include providing the encrypted media key to the client device. 1. A method for secure publication of content , the method comprising:encrypting content with a media key;providing the encrypted content to a client device associated with a private key and a public key, wherein the private key is stored at the client device;encrypting the media key with the public key; andproviding the encrypted media key to the client device.2. The method of claim 1 , further comprising:prior to encrypting the content, transcoding the content into a plurality of formats, each format including a different version of the content, wherein the encrypted content includes an encrypted version of the content in a particular format;generating a first data stream including the encrypted content and a locator for the encrypted content;generating a second data stream including the media key and the locator of the content.3. The method of claim 2 , wherein the second data stream further includes one or more policies and each of the one or more policies controls consumption of the content by the client device.4. The method of claim 3 , wherein each of the one or more policies specifies at least one of:a consumption period having a predetermined length, starting when the content is first accessed on the client device;a consumption period starting at a first date and time and lasting until a second date and time;consumption of the content being contingent on other first content being previously accessed on the client device;consumption of the content being contingent on other second content not being ...

CACHE OPERATIONS IN A HYBRID DUAL IN-LINE MEMORY MODULE

A system includes a first memory device of a first memory type, a second memory device of a second memory type, and a third memory device of a third memory type. The system further includes a processing device to retrieve one or more sections of data from the first memory device comprising a first memory type, and retrieve one or more remaining sections of data from the second memory device comprising a second memory type, wherein the one or more remaining sections of data from the second memory device are associated with the one or more sections of data from the first memory device. The processing device is further to combine the one or more sections of data from the first memory device comprising the first memory type with the one or more remaining sections of each of data from the second memory device comprising the second memory type into a contiguous page, and copy the contiguous page to a third memory device comprising a third memory type. 1. A system comprising:a first memory device comprising a first memory type;a second memory device comprising a second memory type coupled to the first memory device;a third memory device comprising a third memory type coupled to the first memory device and the second memory device, wherein the third memory type has a higher access latency than the first memory device, and wherein the second memory device has a higher access latency than the first and third memory devices; and retrieving one or more sections of data from the first memory device comprising the first memory type;', 'retrieving one or more remaining sections of data from the second memory device comprising the second memory type, wherein the one or more remaining sections of data from the second memory device are associated with the one or more sections of data from the first memory device;', 'combining the one or more sections of data from the first memory device comprising the first memory type with the one or more remaining sections of each of data from the ...

Predictive Paging to Accelerate Memory Access

A computing system having memory components, including first memory and second memory. The computing system further includes a processing device, operatively coupled with the memory components, to: receive, in a prediction engine, usage history of pages in the second memory; train a prediction model based on the usage history; predict, by the prediction engine using the prediction model, likelihood of the pages being used in a subsequent period of time; and responsive to the likelihood predicted by the prediction engine, copy by a controller data in a page in the second memory to the first memory. 1. A computing system , comprising:a plurality of memory components having first memory and second memory; receive, in a prediction engine, usage history of pages in the second memory;', 'train a prediction model based on the usage history;', 'predict, by the prediction engine using the prediction model, likelihood of the pages being used in a subsequent period of time; and', 'responsive to the likelihood predicted by the prediction engine, copy by a controller data in a page in the second memory to the first memory., 'a processing device, operatively coupled with the plurality of memory components, to2. The computing system of claim 1 , further comprising a hypervisor generating information claim 1 , the prediction engine predicting the likelihood based on the information generated by the hyperviser.3. The computing system of claim 2 , further comprising a device driver receiving the information from the hypervisor and providing the information to the prediction engine; wherein the information comprises at least one of:a sequence of pages being used in a period of time;instances of requests to load pages from the second memory to the first memory;content attributes of the pages loaded from the second memory to the first memory;ownership attributes of the pages loaded from the second memory to the first memory;identifications of users of the pages loaded from the second ...

Cross point array memory in a non-volatile dual in-line memory module

A processing device determines a subset of a plurality of blocks from a volatile memory device of a memory sub-system, retrieves the subset of the plurality of blocks from the volatile memory device, and writes the subset of the plurality of blocks to a non-volatile cross point array memory device of the memory sub-system using a first type of write operation. The processing device further receives an indication of a power loss in the memory sub-system, and responsive to receiving the indication of the power loss, writes a remainder of the plurality of blocks to the non-volatile cross point array memory device using a second type of write operation.

Storing data based on a probability of a data graph

Data blocks of a memory sub-system that have been accessed by a host system can be determined. An access pattern associated with the data blocks by the host system can be determined. A spatial characteristic for each respective pair of the data blocks of the memory sub-system can be received. A data graph can be generated with nodes that are based on the access pattern associated with the data blocks of the memory sub-system and edge values between the nodes that are based on the spatial characteristic for each respective pair of the data blocks of the memory sub-system.

NVMe DIRECT VIRTUALIZATION WITH CONFIGURABLE STORAGE

A system controller, operatively coupled with one or more memory devices, is configured to provide a plurality of virtual memory controllers, wherein each of the plurality of virtual memory controllers is associated with a different portion of the one or more memory devices, and provide a plurality of physical functions, wherein each of the plurality of physical functions corresponds to a different one of the plurality of virtual memory controllers. The system controller further presents the plurality of physical functions to a host computing system over a peripheral component interconnect express (PCIe) interface, the host computing system to assign each of the plurality of physical functions to a different virtual machine running on the host computing system. 1. A memory system comprising:one or more memory devices; and provide a plurality of virtual memory controllers, wherein each of the plurality of virtual memory controllers is associated with a different portion of the one or more memory devices;', 'provide a plurality of physical functions, wherein each of the plurality of physical functions corresponds to a different one of the plurality of virtual memory controllers; and', 'present the plurality of physical functions to a host computing system over a peripheral component interconnect express (PCIe) interface, the host computing system to assign each of the plurality of physical functions to a different virtual machine running on the host computing system., 'a system controller, operatively coupled with the one or more memory devices, the system controller to2. The memory system of claim 1 , wherein the system controller further to:partition the one or more memory devices into a plurality of portions; andassociate each of the plurality of virtual memory controllers with one of the plurality of portions.3. The memory system of claim 1 , wherein each of the plurality of virtual memory controllers to receive and process memory access requests from an assigned ...

MEMORY TIERING USING PCIe CONNECTED FAR MEMORY

A processing device in a host system monitors a data temperature of a plurality of memory pages stored in a host-addressable region of a cache memory component operatively coupled with the host system. The processing device determines that a first memory page of the plurality of memory pages satisfies a first threshold criterion pertaining to the data temperature of the first memory page and sends a first migration command indicating the first memory page to a direct memory access (DMA) engine executing on a memory-mapped storage component operatively coupled with the cache memory component and with the memory-mapped storage component via a peripheral component interconnect express (PCIe) bus. The first migration command causes the DMA engine to initiate a first DMA transfer of the first memory page from the cache memory component to a host-addressable region of the memory-mapped storage component.

Providing bandwidth expansion for a memory sub-system including a sequencer separate from a controller

A processing device can determine a configuration parameter to be used in an error correction code (ECC) operation. The configuration parameter is based on a memory type of a memory component that is associated with a controller. Data can be received from a host system. The processing device can generate a code word for the data by using the ECC operation that is based on the configuration parameter. The code word can be sent to a sequencer that is external to the controller.

MEMORY SUB-SYSTEM INCLUDING AN IN PACKAGE SEQUENCER SEPARATE FROM A CONTROLLER

An instruction can be received at a sequencer from a controller. The sequencer can be in a package including the sequencer and one or more memory components. The sequencer is operatively coupled to a controller that is separate from the package. A processing device of the sequencer can perform an operation based on the instruction on at least one of the one or more memory components in the package. 1. A method comprising:receiving, from a controller, an instruction at a sequencer, wherein the sequencer is in a package comprising the sequencer and one or more memory components, and wherein the sequencer is operatively coupled to the controller that is separate from the package; andperforming, by a processing device of the sequencer, an operation based on the instruction on at least one of the one or more memory components in the package.2. The method of claim 1 , wherein the operation comprises one or more of:interfacing with the one or more memory components via a protocol;enforcing operation timing requirements for the one or more memory components; orreordering operations based on rules related to data coherency.3. The method of claim 1 , wherein the sequencer and the controller are operatively coupled via a serializer/deserializer (SerDes) interface.4. The method of claim 1 , wherein the one or more memory components comprise a first memory type claim 1 , and the sequencer is to interface with the first memory type via a protocol that is based on the first memory type.5. The method of claim 4 , further comprising:receiving a second instruction at a second sequencer, wherein the second sequencer is located in another package, and the second sequencer is operatively coupled to one or more second memory components within the another package and the second sequencer is operatively coupled to the controller.6. The method of claim 5 , wherein the one or more second memory components comprise a second memory type different than the first memory type claim 5 , and the ...

MEMORY SUB-SYSTEM INCLUDING AN IN-PACKAGE SEQUENCER TO PERFORM ERROR CORRECTION AND MEMORY TESTING OPERATIONS

A processing device of a sequencer component can receive data from a controller that is external to the sequencer component. The processing device of the sequencer component can perform an error correction operation on the data received from the controller that is external to the sequencer component to generate a code word associated with the data. The code word can be stored at a memory component coupled with the sequencer component. 1. A method comprising:receiving, by a processing device of a sequencer component, data from a controller that is external to the sequencer component;performing, by the processing device of the sequencer component, an error correction operation on the data received from the controller that is external to the sequencer component to generate a code word associated with the data; andstoring the code word at a memory component coupled with the sequencer component.2. The method of claim 1 , further comprising:receiving an indication of a memory type of the memory component, the memory type corresponding to a structure of the memory component, wherein performing the error correction operation to generate the code word is based on the memory type of the memory component.3. The method of claim 1 , further comprising:receiving an operation to read the data;in response to receiving the operation, retrieving the code word from the memory component; andperforming, by the processing device of the sequencer component, a decoding operation associated with the code word to generate the data.4. The method of claim 3 , further comprising:identifying that a portion of the data includes a first error that cannot be decoded by the decoding operation that is performed by the sequencer component, wherein decoding the data corrected at least a second error in the data; andperforming, by the processing device of sequencer component, a second error correction operation to decode the portion of the data to correct the first error.5. The method of claim 3 , ...

SCHEDULING OF READ OPERATIONS AND WRITE OPERATIONS BASED ON A DATA BUS MODE

A data bus is determined to be in a write mode. Whether a number of memory queues that identify at least one write operation satisfies a threshold criterion is determined. The memory queues include identifiers of one or more write operations and identifiers of one or more read operations. Responsive to determining that the number of memory queues satisfies the threshold criterion, a write operation from the memory queues is transmitted over the data bus. 1. A method , comprising:determining that a data bus is in a write mode;determining, by a processing device, whether a number of memory queues that identify at least one write operation satisfies a threshold criterion, wherein the memory queues comprise identifiers of one or more write operations and identifiers of one or more read operations; andresponsive to determining that the number of memory queues satisfies the threshold criterion, transmitting a write operation from the memory queues over the data bus.2. The method of claim 1 , further comprising:responsive to determining that the number of memory queues does not satisfy the threshold criterion, transmitting a read operation from the memory queues over the data bus.3. The method of claim 2 , further comprising:determining that a particular memory queue of the memory queues is available, wherein the particular memory queue is available when transmitting the read operation from the particular memory queue over the data bus satisfies a data bus protocol.4. The method of claim 2 , further comprising:responsive to determining that the number of memory queues does not satisfy the threshold criterion, changing a status of the data bus from the write mode to a read mode.5. The method of claim 1 , wherein the determining of whether the number of memory queues satisfies the threshold criterion is responsive to a write operation not being identified at an available memory queue.6. The method of claim 1 , wherein determining that the data bus is in the write mode is ...

CACHE OPERATIONS IN A HYBRID DUAL IN-LINE MEMORY MODULE

A system includes a first memory component of a first memory type, a second memory component of a second memory type with a higher access latency than the first memory component, and a third memory component of a third memory type with a higher access latency than the first and second memory components. The system further includes a processing device to identify a section of a data page stored in the first memory component, and access patterns associated with the data page and the section of the data page. The processing device determines to cache the data page at the second memory component based on the access patterns, copying the section of the data page stored in the first memory component to the second memory component. The processing device then copies additional sections of the data page stored at the third memory component to the second memory component. 1. A system comprising:a first memory component comprising a first memory type;a second memory component comprising a second memory type coupled to the first memory component, wherein the second memory type has a higher access latency than the first memory component;a third memory component of a third memory type coupled to the first memory component and the second memory component, wherein the third memory component has a higher access latency than the first and second memory components; and identifying a section of a data page stored in the first memory component;', 'identifying access patterns associated with the data page and the section of the data page;', 'determining to cache the data page at the second memory component based on the access patterns;', 'copying the section of the data page stored in the first memory component to the second memory component; and', 'copying one or more additional sections of the data page stored at the third memory component to the second memory component., 'a processing device, operatively coupled with the first memory component, the second memory component, and the ...

Scheduling of read operations and write operations based on a data bus mode

A data bus can be determined to be in a write mode based on a prior operation transmitted over the data bus being a write operation. In response to determining that the data bus is in the write mode, a number of partition queues of a plurality of partition queues that include at least one write operation can be identified. A determination as to whether the number of partition queues of the plurality of partition queues satisfies a threshold number can be made. In response to determining that the number of partition queues satisfies the threshold number, another write operation from the plurality of partition queues can be transmitted over the data bus.

SECURE CONTENT DISTRIBUTION

In an example, a method of securing content is described. The method may include instantiating a content server on a client device. The method may also include operating the content server to retrieve content identified by a Uniform Resource Identifier (URI). The method may also include serving the content from the content server to a content renderer on the client device. The content renderer may be configured to render the content at the client device and to prohibit saving the content in the clear on the client device. 1. A method of securing content , the method comprising:instantiating a content server on a client device;operating the content server to retrieve content identified by a Uniform Resource Identifier (URI); andserving the content from the content server to a content renderer on the client device, wherein the content renderer is configured to render the content at the client device and to prohibit saving the content in the clear on the client device.2. The method of claim 1 , wherein the content server is configured to prohibit serving the content to any client except the client device including the content renderer.3. The method of claim 1 , further comprising launching the content renderer claim 1 , wherein launching the content renderer includes:launching the content renderer as a thread separate from the content server; orloading a viewer library corresponding to the content renderer on the client device.4. The method of claim 1 , further comprising performing an authentication handshake between the content renderer and the content server prior to serving the content to the content renderer.5. The method of claim 4 , wherein performing an authentication handshake comprises at least one of:deriving a session token from a shared key established between the content server and the content renderer when the content server and the content renderer are two threads derived from the same process;authenticating the content renderer and content server using ...

MEMORY TIERING USING PCIe CONNECTED FAR MEMORY

A processing device in a host system monitors a data temperature of a plurality of memory pages stored in a host-addressable region of a cache memory component operatively coupled with the host system. The processing device determines that a first memory page of the plurality of memory pages satisfies a first threshold criterion pertaining to the data temperature of the first memory page and sends a first migration command indicating the first memory page to a direct memory access (DMA) engine executing on a memory-mapped storage component operatively coupled with the cache memory component and with the memory-mapped storage component via a peripheral component interconnect express (PCIe) bus. The first migration command causes the DMA engine to initiate a first DMA transfer of the first memory page from the cache memory component to a host-addressable region of the memory-mapped storage component.

Memory device data security based on content-addressable memory architecture

An access request is received. The access request comprises a physical page address corresponding to a primary memory block of a memory device, an input security key, and a logical page address corresponding to the physical page address. The input security key is provided as input to a (CAM) block that stores a plurality of security keys to verify that the input security key matches a stored security key. A location of the stored security key is checked to verify that it corresponds to the logical page address included in the access request based a predetermined mapping. Based on verifying that the stored security key corresponds to the logical page address included in the access request, the physical page address corresponding to the primary memory block is accessed.

MEMORY SUB-SYSTEM INCLUDING AN IN-PACKAGE SEQUENCER TO PERFORM ERROR CORRECTION AND MEMORY TESTING OPERATIONS

A sequencer component residing in a first package receives data from a controller residing in a second package that is different than the first package including the sequencer component. The sequencer component performs an error correction operation on the data received from the controller. The error correction operation encodes the data with additional data to generate a code word. The sequencer component stores the code word at a memory device. 1. A method comprising:receiving, by a sequencer component residing in a first package, data from a controller residing in a second package that is different than the first package including the sequencer component;performing, by the sequencer component, an error correction operation on the data received from the controller, wherein the error correction operation encodes the data with additional data to generate a code word; andstoring, by the sequencer component, the code word at a memory device.2. The method of claim 1 , further comprising:transmitting, by the sequencer component, a notification to the controller that indicates whether the sequencer component includes functionality to perform the error correction operation.3. The method of claim 1 , wherein the memory device resides in the first package with the sequencer component.4. The method of claim 1 , further comprising:receiving an indication of a memory type of the memory device, the memory type corresponding to a structure of the memory device, wherein performing the error correction operation is based on the memory type of the memory device.5. The method of claim 1 , further comprising:receiving an operation request to read the data;in response to receiving the operation request, retrieving the code word from the memory device; andperforming, by the sequencer component, a decoding operation using the code word to generate the data.6. The method of claim 5 , further comprising:identifying that a portion of the data includes a first error that cannot be decoded ...

CPU CACHE FLUSHING TO PERSISTENT MEMORY

A computing system having a power loss detector and memory components to store data associated with write commands received from a host system. The write commands are flushed from a protected write queue of the host system responsive to detecting an impending loss of power. The computing system further includes a processing device to receive the write commands over a memory interface. The processing device is further to, responsive to detecting the loss of power by the detector: disable the memory interface, and store the data associated with write commands that are received prior to disabling the memory interface. The data is stored in one or more of the memory components using power supplied by one or more capacitors. 1. A system comprising:a detector configured to detect an impending loss of power from a power supply; andat least one memory component configured to store first data associated with write commands received from a host system, wherein the write commands are sent by the host system responsive to a signal provided to the host system by a power supply monitor, and wherein the power supply monitor provides the signal responsive to detecting an impending loss of power from the power supply;wherein responsive to detecting, by the detector, the impending loss of power, the first data is stored in the at least one memory component.2. The system of claim 1 , wherein the write commands correspond to write operations committed to a memory controller by a processing device of the host system.3. The system of claim 2 , wherein the write operations are committed to the memory controller by software executing on the host system claim 2 , and the write commands are flushed by the software responsive to the signal provided to the host system by the power supply monitor.4. The system of claim 3 , wherein the write commands are flushed during an asynchronous memory refresh sequence.5. The system of claim 3 , wherein the write commands are flushed from a protected write ...

Remote Direct Memory Access in Multi-Tier Memory Systems

A memory system having memory components, a remote direct memory access (RDMA) network interface card (RNIC), and a host system, and configured to: allocate a page of virtual memory for an application; map the page of virtual memory to a page of physical memory in the memory components; instruct the RNIC to perform an RDMA operation; perform, during the RDMA operation, a data transfer between the page of physical memory in the plurality of memory components and a remote device that is connected via a computer network to the remote direct memory access network interface card; and at least for a duration of the data transfer, lock a mapping between the page of virtual memory and the page of physical memory in the memory components. 1. A computer system , comprising: allocate a page of virtual memory for an application running in the host system;', 'map the page of virtual memory to a page of physical memory in the plurality of memory components;', 'instruct, by the host system, the remote direct memory access network interface card to perform a remote direct memory access operation; wherein during the remote direct memory access operation, the remote direct memory access network interface card performs a data transfer between the page of physical memory in the plurality of memory components and a remote device that is connected via a computer network to the remote direct memory access network interface card; and', 'lock, at least for a duration of the data transfer, a mapping between the page of virtual memory and the page of physical memory in the plurality of memory components., 'a host system, operatively coupled to a plurality of memory components and a remote direct memory access network interface card, to at least2. The computer system of claim 1 , wherein the host system is further configured to unlock the mapping between the page of virtual memory and the plurality of memory components after the remote direct memory access operation.3. The computer system of ...

Predictive Data Orchestration in Multi-Tier Memory Systems

A computing system having memory components of different tiers. The computing system further includes a controller, operatively coupled between a processing device and the memory components, to: receive from the processing device first data access requests that cause first data movements across the tiers in the memory components; service the first data access requests after the first data movements; predict, by applying data usage information received from the processing device in a prediction model trained via machine learning, second data movements across the tiers in the memory components; and perform the second data movements before receiving second data access requests, where the second data movements reduce third data movements across the tiers caused by the second data access requests.

Memory Access Communications through Message Passing Interface Implemented in Memory Systems

A memory system having a plurality of memory components and a controller, operatively coupled to the plurality of memory components to: store data in the memory components; communicate with a host system via a bus; service the data to the host system via communications over the bus; communicate with a processing device that is separate from the host system using a message passing interface over the bus; and provide data access to the processing device through communications made using the message passing interface over the bus. 1. A memory system , comprising:a plurality of memory components; and store data in the memory components;', 'communicate with a host system via a bus;', 'service the data to the host system via communications over the bus;', 'communicate with a processing device that is separate from the host system using a message passing interface over the bus; and', 'provide data access to the processing device through communications made using the message passing interface over the bus., 'a controller, operatively coupled to the plurality of memory components, to at least2. The memory system of claim 1 , wherein the controller communicates with the processing device without involving the host system.3. The memory system of claim 2 , wherein the host system includes a central processing unit (CPU).4. The memory system of claim 3 , wherein the bus is a peripheral component interconnect express (PCIe) bus.5. The memory system of claim 3 , wherein the processing device is a graphics processing unit (GPU).6. The memory system of claim 3 , wherein the processing device is a controller of a storage device coupled to the bus.7. The memory system of claim 3 , wherein the processing device is a controller of a storage device coupled to the bus through a computer network.8. The memory system of claim 7 , wherein the bus is connected to the computer network via an InfiniBand (IB) interface.9. The memory system of claim 8 , wherein the memory system is a solid state ...

CPU Cache Flushing to Persistent Memory

A computing system having a power loss detector and memory components to store data associated with write commands received from a host system. The write commands are flushed from a protected write queue of the host system responsive to detecting an impending loss of power. The computing system further includes a processing device to receive the write commands over a memory interface. The processing device is further to, responsive to detecting the loss of power by the detector: disable the memory interface, and store the data associated with write commands that are received prior to disabling the memory interface. The data is stored in one or more of the memory components using power supplied by one or more capacitors. 1. A computing system , comprising:a detector to detect a loss of power provided from a power supply;at least one capacitor to provide power for storing data after the loss of power;a plurality of memory components to store data associated with write commands received from a host system, wherein write commands are flushed from a protected write queue of a memory controller of the host system responsive to a signal provided to the host system by a power supply monitor, and wherein the power supply monitor provides the signal responsive to detecting an impending loss of power from the power supply;a cache to receive, over a memory interface, write commands from the host system; and receive, by the cache over the memory interface, the write commands flushed from the protected write queue; and', disable the memory interface, and', 'store data corresponding to write commands flushed from the protected write queue that are received by the cache prior to disabling the memory interface, wherein the data is stored in at least one of the plurality of memory components using power supplied by the at least one capacitor., 'responsive to detecting, by the detector, the loss of power], 'a processing device, operatively coupled with the plurality of memory ...

Accelerate Data Access in Memory Systems via Data Stream Segregation

A computing system having memory components of different tiers. The computing system further includes a processing device, operatively coupled to the memory components, to: receive data access requests; generate a plurality of data access streams in accordance with the data access requests and access characteristics of the request; match characteristics of the data access streams with characteristics of the different tiers of the memory components; and direct the plurality of data access streams to the different tiers of the memory components based on matching the characteristics of the data access streams with the characteristics of the different tiers of the memory components. 1. A computing system , comprising:a plurality of memory components of different tiers; and receive data access requests;', 'generate a plurality of data access streams in accordance with the data access requests and access characteristics of the request;', 'match characteristics of the data access streams with characteristics of the different tiers of the memory components; and', 'direct the plurality of data access streams to the different tiers of the memory components based on matching the characteristics of the data access streams with the characteristics of the different tiers of the memory components., 'a processing device, operatively coupled to the plurality of memory components, to at least2. The computing system of claim 1 , wherein one of the different tiers comprises Dynamic Random-Access Memory (DRAM).3. The computing system of claim 1 , wherein one of the different tiers comprises cross point memory.4. The computing system of claim 1 , wherein one of the different tiers comprises Single Level Cell (SLC) flash memory.5. The computing system of claim 1 , wherein one of the different tiers comprises Triple Level Cell (TLC) flash memory or Quad-Level Cell (QLC) flash memory.6. The computing system of claim 1 , wherein the characteristics of the data access streams is based on ...

Memory Systems having Controllers Embedded in Packages of Integrated Circuit Memory

A computing system having a memory component with an embedded media controller. The memory component is encapsulated within an integrated circuit (IC) package. The embedded controller within the IC package is configured to: receive incoming packets, via a serial communication interface of the controller, from a serial connection outside of the IC package; convert the incoming packets into commands and addresses according to a predetermined serial communication protocol; operate memory units encapsulated within the IC package according to the commands and the addresses; convert results of at least a portion of the commands into outgoing packets; and transmit the outgoing packets via the serial communication interface to the serial connection outside of the IC package. 1. A memory component , comprising:at least one integrated circuit memory die having an integrated circuit configured as a plurality of memory units;an embedded controller comprising a serial communication interface; andan integrated circuit package that encapsulates the embedded controller and the at least one integrated circuit memory die; receive first packets, via the serial communication interface, from a serial connection outside of the integrated circuit package;', 'convert the first packets into commands and addresses according to a predetermined serial communication protocol;', 'operate the memory units according to the commands and the addresses;', 'convert results of at least a portion of the commands into second packets; and', 'transmit the second packets via the serial communication interface to the serial connection outside of the integrated circuit package., 'wherein the embedded controller, operatively coupled to the memory units in the at least one integrated circuit memory die, is configured to at least2. The memory component of claim 1 , wherein the at least one integrated circuit memory die includes multiple dies connected to the embedded controller in parallel.3. The memory ...

NVMe DIRECT VIRTUALIZATION WITH CONFIGURABLE STORAGE

A processing device, operatively coupled with one or more memory devices, is configured to provide a plurality of virtual memory controllers, partition one or more memory devices into a plurality of physical partitions, and associate each of the plurality of virtual memory controllers with one of the plurality of physical partitions. The processing device further provides a plurality of physical functions, wherein each of the plurality of physical functions corresponds to a different one of the plurality of virtual memory controllers, and presents the plurality of physical functions to a host computing system over a peripheral component interconnect express (PCIe) interface.

Remote Direct Memory Access in Multi-Tier Memory Systems

A memory system having memory components, a remote direct memory access (RDMA) network interface card (RNIC), and a host system, and configured to: allocate a page of virtual memory for an application; map the page of virtual memory to a page of physical memory in the memory components; instruct the RNIC to perform an RDMA operation; perform, during the RDMA operation, a data transfer between the page of physical memory in the plurality of memory components and a remote device that is connected via a computer network to the remote direct memory access network interface card; and at least for a duration of the data transfer, lock a mapping between the page of virtual memory and the page of physical memory in the memory components.

MEMORY ACCESS COMMUNICATIONS THROUGH MESSAGE PASSING INTERFACE IMPLEMENTED IN MEMORY SYSTEMS

A memory system having a plurality of memory components and a controller, operatively coupled to the plurality of memory components to: store data in the memory components; communicate with a host system via a bus; service the data to the host system via communications over the bus; communicate with a processing device that is separate from the host system using a message passing interface over the bus; and provide data access to the processing device through communications made using the message passing interface over the bus. 1. A memory system , comprising:a bus; anda peripheral device connected to the bus; implement a message passing interface;', 'instruct a controller of the storage device to communicate directly with the peripheral device over the bus using the message passing interface; and', 'provide data access to the peripheral device through communications made using the message passing interface over the bus., 'a storage device connected to the bus, the storage bus including a data orchestrator configured to2. The memory system of claim 1 , wherein the data orchestrator communicates with the peripheral device without involving a host system connected to the bus.3. The memory system of claim 2 , wherein the host system comprises a central processing unit (CPU).4. The memory system of claim 1 , wherein the bus comprises a peripheral component interconnect express (PCIe) bus.5. The memory system of claim 1 , wherein the peripheral device comprises a graphics processing unit (GPU).6. The memory system of claim 1 , wherein the peripheral device comprises a controller of a second storage device coupled to the bus.7. The memory system of claim 1 , wherein the peripheral device comprise a controller of a second storage device coupled to the bus through a computer network.8. The memory system of claim 7 , wherein the bus is connected to the computer network via an InfiniBand (IB) interface.9. The memory system of claim 1 , wherein the peripheral device comprises ...

Predictive Data Orchestration in Multi-Tier Memory Systems

A computing system having memory components of different tiers. The computing system further includes a controller, operatively coupled between a processing device and the memory components, to: receive from the processing device first data access requests that cause first data movements across the tiers in the memory components; service the first data access requests after the first data movements; predict, by applying data usage information received from the processing device in a prediction model trained via machine learning, second data movements across the tiers in the memory components; and perform the second data movements before receiving second data access requests, where the second data movements reduce third data movements across the tiers caused by the second data access requests.

CROSS POINT ARRAY MEMORY IN A NON-VOLATILE DUAL IN-LINE MEMORY MODULE

An indication of a power loss can be received at a cross point array memory dual in-line memory module (DIMM) operation component of a memory sub-system. The cross point array memory DIMM operation component includes a volatile memory component and a non-volatile cross point array memory component. In response to receiving the indication of the power loss, a type of write operation for the non-volatile cross point array memory component of the cross point array memory DIMM operation component is determined based on a characteristic of the memory sub-system. Data stored at the volatile memory component of the cross point array memory DIMM operation component is retrieved and written to the non-volatile cross point array memory component of the cross point array memory DIMM operation component by using the determined type of write operation.

Secure content distribution

In an example, a method of securing content is described. The method may include instantiating a content server on a client device. The method may also include operating the content server to retrieve content identified by a Uniform Resource Identifier (URI). The method may also include serving the content from the content server to a content renderer on the client device. The content renderer may be configured to render the content at the client device and to prohibit saving the content in the clear on the client device.

Memory access communications through message passing interface implemented in memory systems

A memory system having a plurality of memory components and a controller, operatively coupled to the plurality of memory components to: store data in the memory components; communicate with a host system via a bus; service the data to the host system via communications over the bus; communicate with a processing device that is separate from the host system using a message passing interface over the bus; and provide data access to the processing device through communications made using the message passing interface over the bus.

Memory access communications through message passing interface implemented in memory systems

A memory system having a plurality of memory components and a controller, operatively coupled to the plurality of memory components to: store data in the memory components; communicate with a host system via a bus; service the data to the host system via communications over the bus; communicate with a processing device that is separate from the host system using a message passing interface over the bus; and provide data access to the processing device through communications made using the message passing interface over the bus.

Remote direct memory access in multi-tier memory systems

A memory system having memory components, a remote direct memory access (RDMA) network interface card (RNIC), and a host system, and configured to: allocate a page of virtual memory for an application; map the page of virtual memory to a page of physical memory in the memory components; instruct the RNIC to perform an RDMA operation; perform, during the RDMA operation, a data transfer between the page of physical memory in the plurality of memory components and a remote device that is connected via a computer network to the remote direct memory access network interface card; and at least for a duration of the data transfer, lock a mapping between the page of virtual memory and the page of physical memory in the memory components.

Memory access communications through message passing interface implemented in memory systems

A memory system having a plurality of memory components and a controller, operatively coupled to the plurality of memory components to: store data in the memory components; communicate with a host system via a bus; service the data to the host system via communications over the bus; communicate with a processing device that is separate from the host system using a message passing interface over the bus; and provide data access to the processing device through communications made using the message passing interface over the bus.

Secure content distribution

In an example, a method of securing content is described. The method may include instantiating a content server on a client device. The method may also include operating the content server to retrieve content identified by a Uniform Resource Identifier (URI). The method may also include serving the content from the content server to a content renderer on the client device. The content renderer may be configured to render the content at the client device and to prohibit saving the content in the clear on the client device.

Zone based repeated runout error compensation

Compensation for repeated runout (RRO) error, such as in a data storage device servo circuit, is preferably carried out by obtaining a population distribution of RRO error values from at least selected ones of a subset of tracks. An RRO error compensation value is determined for each one of the subset of tracks when a variance characteristic of said population distribution meets a selected criterion. Preferably, a first track of a storage medium has a servo field at a first angular position on the medium, a repeated runout (RRO) error compensation field at a second angular position on the medium, and a user data field at a third angular position on the medium. An immediately adjacent second track preferably has a servo field at the first angular position and a user data field at the second angular position in lieu of an RRO error compensation field.

Memory access communications through message passing interface implemented in memory systems

Accelerate data access in memory systems via data stream segregation

Accelerate data access in memory systems via data stream segregation

A computing system having memory components of different tiers. The computing system further includes a processing device, operatively coupled to the memory components, to: receive data access requests; generate a plurality of data access streams in accordance with the data access requests and access characteristics of the request; match characteristics of the data access streams with characteristics of the different tiers of the memory components; and direct the plurality of data access streams to the different tiers of the memory components based on matching the characteristics of the data access streams with the characteristics of the different tiers of the memory components.

Scheduling of read operations and write operations based on a data bus mode

A data bus coupled to a plurality of memory devices is determined to be in a read mode. Responsive to determining that the data bus is in the read mode, a particular read operation identified in a particular memory queue of memory queues that include identifiers of one or more write operations and identifiers of one or more read operations is determined. The particular memory queue includes a highest number of read operations for a memory device of the memory devices. The particular read operation is transmitted from the particular memory queue over the data bus.

A memory sub-system including an in package sequencer separate from a controller

An instruction can be received at a sequencer from a controller. The sequencer can be in a package including the sequencer and one or more memory components. The sequencer is operatively coupled to a controller that is separate from the package. A processing device of the sequencer can perform an operation based on the instruction on at least one of the one or more memory components in the package.

Memory device data security based on content-addressable memory architecture

Predictive Data Orchestration in Multi-Tier Memory Systems

A computing system having memory components of different tiers. The computing system further includes a controller, operatively coupled between a processing device and the memory components, to: receive from the processing device first data access requests that cause first data movements across the tiers in the memory components; service the first data access requests after the first data movements; predict, by applying data usage information received from the processing device in a prediction model trained via machine learning, second data movements across the tiers in the memory components; and perform the second data movements before receiving second data access requests, where the second data movements reduce third data movements across the tiers caused by the second data access requests.

Predictive data orchestration in multi-tier memory systems

A computing system having memory components of different tiers. The computing system further includes a controller, operatively coupled between a processing device and the memory components, to: receive from the processing device first data access requests that cause first data movements across the tiers in the memory components; service the first data access requests after the first data movements; predict, by applying data usage information received from the processing device in a prediction model trained via machine learning, second data movements across the tiers in the memory components; and perform the second data movements before receiving second data access requests, where the second data movements reduce third data movements across the tiers caused by the second data access requests.

Predictive data orchestration in multi-tier memory systems

Predictive data orchestration in multi-tier memory systems

A computing system having memory components of different tiers. The computing system further includes a controller, operatively coupled between a processing device and the memory components, to: receive from the processing device first data access requests that cause first data movements across the tiers in the memory components; service the first data access requests after the first data movements; predict, by applying data usage information received from the processing device in a prediction model trained via machine learning, second data movements across the tiers in the memory components; and perform the second data movements before receiving second data access requests, where the second data movements reduce third data movements across the tiers caused by the second data access requests.

Scheduling of read operations and write operations based on a data bus mode

A data bus is determined to be in a write mode. Whether a number of memory queues that identify at least one write operation satisfies a threshold criterion is determined. The memory queues include identifiers of one or more write operations and identifiers of one or more read operations. Responsive to determining that the number of memory queues satisfies the threshold criterion, a write operation from the memory queues is transmitted over the data bus.

Cpu cache flushing to persistent memory

A computing system having a power loss detector and memory components to store data associated with write commands received from a host system. The write commands are flushed from a protected write queue of the host system responsive to detecting an impending loss of power. The computing system further includes a processing device to receive the write commands over a memory interface. The processing device is further to, responsive to detecting the loss of power by the detector: disable the memory interface, and store the data associated with write commands that are received prior to disabling the memory interface. The data is stored in one or more of the memory components using power supplied by one or more capacitors.

NVMe direct virtualization with configurable storage

A processing device, operatively coupled with one or more memory devices, is configured to provide a plurality of virtual memory controllers, partition one or more memory devices into a plurality of physical partitions, and associate each of the plurality of virtual memory controllers with one of the plurality of physical partitions. The processing device further provides a plurality of physical functions, wherein each of the plurality of physical functions corresponds to a different one of the plurality of virtual memory controllers, and presents the plurality of physical functions to a host computing system over a peripheral component interconnect express (PCIe) interface.

Memory sub-system including an in-package sequencer to perform error correction and memory testing operations

A sequencer component residing in a first package receives data from a controller residing in a second package that is different than the first package including the sequencer component. The sequencer component performs an error correction operation on the data received from the controller. The error correction operation encodes the data with additional data to generate a code word. The sequencer component stores the code word at a memory device.

Memory device data security based on content-addressable memory architecture

An access request is received. The access request comprises a physical page address corresponding to a primary memory block of a memory device, an input security key, and a logical page address corresponding to the physical page address. The input security key is provided as input to a (CAM) block that stores a plurality of security keys to verify that the input security key matches a stored security key. A location of the stored security key is checked to verify that it corresponds to the logical page address included in the access request based a predetermined mapping. Based on verifying that the stored security key corresponds to the logical page address included in the access request, the physical page address corresponding to the primary memory block is accessed.

Scheduling of read operations and write operations based on a data bus mode

Cross point array memory in a non-volatile dual in-line memory module

A memory sub-system including an in package sequencer separate from a controller

A memory sub-system including an in package sequencer separate from a controller

Memory device data security based on content-addressable memory architecture

An access request is received. The access request comprises a physical page address corresponding to a primary memory block of a memory device, an input security key, and a logical page address corresponding to the physical page address. The input security key is provided as input to a (CAM) block that stores a plurality of security keys to verify that the input security key matches a stored security key. A location of the stored security key is checked to verify that it corresponds to the logical page address included in the access request based a predetermined mapping. Based on verifying that the stored security key corresponds to the logical page address included in the access request, the physical page address corresponding to the primary memory block is accessed.

Remote direct memory access in multi-tier memory systems

A memory system having memory components, a remote direct memory access (RDMA) network interface card (RNIC), and a host system, and configured to: allocate a page of virtual memory for an application; map the page of virtual memory to a page of physical memory in the memory components; instruct the RNIC to perform an RDMA operation; perform, during the RDMA operation, a data transfer between the page of physical memory in the plurality of memory components and a remote device that is connected via a computer network to the remote direct memory access network interface card; and at least for a duration of the data transfer, lock a mapping between the page of virtual memory and the page of physical memory in the memory components.

Memory systems having controllers embedded in packages of integrated circuit memory

A computing system having a memory component with an embedded media controller. The memory component is encapsulated within an integrated circuit (IC) package. The embedded controller within the IC package is configured to: receive incoming packets, via a serial communication interface of the controller, from a serial connection outside of the IC package; convert the incoming packets into commands and addresses according to a predetermined serial communication protocol; operate memory units encapsulated within the IC package according to the commands and the addresses; convert results of at least a portion of the commands into outgoing packets; and transmit the outgoing packets via the serial communication interface to the serial connection outside of the IC package.

Providing bandwidth expansion for a memory sub-system including a sequencer separate from a controller

A processing device can determine a configuration parameter to be used in an error correction code (ECC) operation. The configuration parameter is based on a memory type of a memory component that is associated with a controller. Data can be received from a host system. The processing device can generate a code word for the data by using the ECC operation that is based on the configuration parameter. The code word can be sent to a sequencer that is external to the controller.

Predictive paging to accelerate memory access

Storing data based on a probability of a data graph

A graph can be generated based on an access pattern associated with blocks of a memory device that have been accessed by a host system, wherein the graph comprises nodes representing at least a subset of the blocks that have been accessed by the host system and edges that are based on the access pattern, wherein each edge is associated with a respective probability value between a respective pair of nodes. A number of edges having respective probability values that satisfy a probability value threshold criterion can be determined. It can be determined whether the number of edges satisfies a decayed edge value condition. In response to determining that the number of edges does not satisfy the decayed edge value condition, the graph can be removed.

Cpu cache flushing to persistent memory

A computing system having a power loss detector and memory components to store data associated with write commands received from a host system. The write commands are flushed from a protected write queue of the host system responsive to detecting an impending loss of power. The computing system further includes a processing device to receive the write commands over a memory interface. The processing device is further to, responsive to detecting the loss of power by the detector: disable the memory interface, and store the data associated with write commands that are received prior to disabling the memory interface. The data is stored in one or more of the memory components using power supplied by one or more capacitors.

Cpu cache flushing to persistent memory

NVMe DIRECT VIRTUALIZATION WITH CONFIGURABLE STORAGE

A system controller, operatively coupled with one or more memory devices, is configured to provide a plurality of virtual memory controllers, wherein each of the plurality of virtual memory controllers is associated with a different portion of the one or more memory devices, and provide a plurality of physical functions, wherein each of the plurality of physical functions corresponds to a different one of the plurality of virtual memory controllers. The system controller further presents the plurality of physical functions to a host computing system over a peripheral component interconnect express (PCIe) interface, the host computing system to assign each of the plurality of physical functions to a different virtual machine running on the host computing system.

Predictive paging to accelerate memory access

A computing system having memory components, including first memory and second memory. The computing system further includes a processing device, operatively coupled with the memory components, to: receive, in a prediction engine, usage history of pages in the second memory; train a prediction model based on the usage history; predict, by the prediction engine using the prediction model, likelihood of the pages being used in a subsequent period of time; and responsive to the likelihood predicted by the prediction engine, copy by a controller data in a page in the second memory to the first memory.

Memory systems having controllers embedded in packages of integrated circuit memory

Memory device data security based on content-addressable memory architecture

An access request is received. The access request comprises a physical page address corresponding to a primary memory block of a memory device, an input security key, and a logical page address corresponding to the physical page address. The input security key is provided as input to a (CAM) block that stores a plurality of security keys to verify that the input security key matches a stored security key. A location of the stored security key is checked to verify that it corresponds to the logical page address included in the access request based a predetermined mapping. Based on verifying that the stored security key corresponds to the logical page address included in the access request, the physical page address corresponding to the primary memory block is accessed.

Predictive paging to accelerate memory access

A computing system having memory components, including first memory and second memory. The computing system further includes a processing device, operatively coupled with the memory components, to: receive, in a prediction engine, usage history of pages in the second memory; train a prediction model based on the usage history; predict, by the prediction engine using the prediction model, likelihood of the pages being used in a subsequent period of time; and responsive to the likelihood predicted by the prediction engine, copy by a controller data in a page in the second memory to the first memory.

Predictive paging to accelerate memory access

A computing system having memory components, including first memory and second memory. The computing system further includes a processing device, operatively coupled with the memory components, to: receive, in a prediction engine, usage history of pages in the second memory; train a prediction model based on the usage history; predict, by the prediction engine using the prediction model, likelihood of the pages being used in a subsequent period of time; and responsive to the likelihood predicted by the prediction engine, copy by a controller data in a page in the second memory to the first memory.

Memory systems having controllers embedded in packages of integrated circuit memory

A computing system having a memory component with an embedded media controller. The memory component is encapsulated within an integrated circuit (IC) package. The embedded controller within the IC package is configured to: receive incoming packets, via a serial communication interface of the controller, from a serial connection outside of the IC package; convert the incoming packets into commands and addresses according to a predetermined serial communication protocol; operate memory units encapsulated within the IC package according to the commands and the addresses; convert results of at least a portion of the commands into outgoing packets; and transmit the outgoing packets via the serial communication interface to the serial connection outside of the IC package.

Scheduling of read operations and write operations based on a data bus mode

A data bus can be determined to be in a write mode based on a prior operation transmitted over the data bus being a write operation. In response to determining that the data bus is in the write mode, a number of partition queues of a plurality of partition queues that include at least one write operation can be identified. A determination as to whether the number of partition queues of the plurality of partition queues satisfies a threshold number can be made. In response to determining that the number of partition queues satisfies the threshold number, another write operation from the plurality of partition queues can be transmitted over the data bus.

Remote Direct Memory Access in Multi-Tier Memory Systems

A memory system having memory components, a remote direct memory access (RDMA) network interface card (RNIC), and a host system, and configured to: allocate a page of virtual memory for an application; map the page of virtual memory to a page of physical memory in the memory components; instruct the RNIC to perform an RDMA operation; perform, during the RDMA operation, a data transfer between the page of physical memory in the plurality of memory components and a remote device that is connected via a computer network to the remote direct memory access network interface card; and at least for a duration of the data transfer, lock a mapping between the page of virtual memory and the page of physical memory in the memory components.

CPU cache flushing to persistent memory

A computing system having a power loss detector and memory components to store data associated with write commands received from a host system. The write commands are flushed from a protected write queue of the host system responsive to detecting an impending loss of power. The computing system further includes a processing device to receive the write commands over a memory interface. The processing device is further to, responsive to detecting the loss of power by the detector: disable the memory interface, and store the data associated with write commands that are received prior to disabling the memory interface. The data is stored in one or more of the memory components using power supplied by one or more capacitors.

Memory systems having controllers embedded in packages of integrated circuit memory

A computing system having a memory component with an embedded media controller. The memory component is encapsulated within an integrated circuit (IC) package. The embedded controller within the IC package is configured to: receive incoming packets, via a serial communication interface of the controller, from a serial connection outside of the IC package; convert the incoming packets into commands and addresses according to a predetermined serial communication protocol; operate memory units encapsulated within the IC package according to the commands and the addresses; convert results of at least a portion of the commands into outgoing packets; and transmit the outgoing packets via the serial communication interface to the serial connection outside of the IC package.

Cross point array memory in a non-volatile dual in-line memory module

An indication of a power loss can be received at a cross point array memory dual in- line memory module (DIMM) operation component of a memory sub-system. The cross point array memoryDIMM operation component includes a volatile memory component and a non-volatile cross point array memory component. In response to receiving the indication of the power loss, a type of write operation for the non-volatile cross point array memory component of the cross point array memory DIMM operation component is determined based on a characteristic of the memory sub-system. Data stored at the volatile memory component of the cross point array memory DIMM operation component is retrieved and written to the non-volatile cross point array memory component of the cross point array memory DIMM operation component by using the determined type of write operation.

Memory systems having controllers embedded in packages of integrated circuit memory

A computing system having a memory component with an embedded media controller. The memory component is encapsulated within an integrated circuit (IC) package. The embedded controller within the IC package is configured to: receive incoming packets, via a serial communication interface of the controller, from a serial connection outside of the IC package; convert the incoming packets into commands and addresses according to a predetermined serial communication protocol; operate memory units encapsulated within the IC package according to the commands and the addresses; convert results of at least a portion of the commands into outgoing packets; and transmit the outgoing packets via the serial communication interface to the serial connection outside of the IC package.