Speichereinrichtung, die eine Menge von kommunizierten Daten abhängig von einer Aussetzhäufigkeit einer Operation drosselt

Eine Speichereinrichtung (1300) weist einen Speicher (1310, 1311, 1312, 1319) und einen Controller (1330) auf. Der Controller (1330) steuert den Speicher (1310, 1311, 1312, 1319) derart, dass in Antwort auf eine Anforderung für eine erste Leseoperation auf dem Speicher (1310, 1311, 1312, 1319), während eine erste Schreiboperation auf dem Speicher (1310, 1311, 1312, 1319) durchgeführt wird, die erste Schreiboperation ausgesetzt wird und die erste Leseoperation durchgeführt wird, die ausgesetzte erste Schreiboperation wieder aufgenommen wird, nachdem die erste Leseoperation vollendet ist, und eine zweite Schreiboperation nachfolgend auf die erste Schreiboperation auf dem Speicher (1310, 1311, 1312, 1319) durchgeführt wird, nachdem die wiederaufgenommene erste Schreiboperation vollendet ist. Der Controller (1330) drosselt eine Menge von Daten, welche zu der Speichervorrichtung (1310, 1311, 1312, 1319) für die zweite Schreiboperation oder für eine zweite Leseoperation nachfolgend auf die erste ...

Data processing system and method

Virtual memory metadata management

Scalable virtual memory metadata management comprising a plurality of pre-instantiated VM metadata containers representing the entire amount of real physical memory available to a computing system, with additional instantiated VM metadata containers created as needed. Individual and/or groups of VM metadata containers are assigned to metadata container groups, wherein each container group is controlled by an acquired lock assigned to the VM metadata container groups. Virtual memory metadata is managed using a "least used" technique. In response to allocation requests, the allocator scans the container groups/ VM containers and fulfills memory object metadata allocation to the least used VM metadata container of the least used container group, filling the individual VM metadata containers and/or the container groups at a nearly equal rate.

SYSTEMS AND METHODS FOR FACILITATING DATA ENCRYPTION AND DECRYPTION AND ERASING OF ASSOCIATED INFORMATION

Various techniques provide systems and methods for facilitating data encryption/ decryption and almost immediate erasure of associated information. In one example, a method includes receiving first data in a first memory. The method further includes receiving a first key in a second memory. The method further includes generating, by a logic circuit, second data based on the first data and the first key. The method further includes providing the second data for transmission. The method further includes erasing the first data and/or the first key in one-half clock cycle of generating the second data. Related methods and devices are also provided.

METHODS AND SYSTEMS FOR QUICK AND EFFICIENT DATA MANAGEMENT AND/OR PROCESSING

System(s) and method(s) are provided for data management and data processing. For example, various embodiments may include systems and methods relating to relatively larger groups of data being selected with comparable or better performing selection results (e.g. high data redundancy elimination and/or average chunk size). In various embodiments, the system(s) and method(s) may include, for example a data group, block, or chunk combining technique and/or a data group, block, or chunk splitting technique. Various embodiments may include a first standard or typical data grouping, blocking, or chunking technique and/or data group, block or chunk combining technique and/or a data group, block, or chunk splitting technique. Exemplary system(s) and method(s) may relate to data hashing and/or data elimination. Embodiments may include a look-ahead buffer and determine whether to emit small chunks or large chunks based on characteristics of underlying data and/or particular application of the invention ...

MANAGING OPERATIONS ON STORED DATA UNITS

A system for managing storage of data units includes a data storage system (106) configured to store multiple data blocks (202A-202C), at least some of the data blocks containing multiple data units, with at least a group of the data blocks being stored contiguously, thereby supporting a first read operation (340) that retrieves data units from at least two adjacent data blocks in the group. The system is configured to perform one or more operations with respect to data units, the operations including a delete operation (300) that replaces a first data block containing a data unit to be deleted with a second data block that does not contain the deleted data unit, with the second data block having the same size as the first data block.

MULTI-LAYERED STORAGE ADMINISTRATION FOR FLEXIBLE PLACEMENT OF DATA

A storage administrator may maintain location information in separate layers. A data storage system may identify the location of particular data by identifying the virtual location of data, such as the logical extent to which the data belongs. Object stores may maintain mappings of virtual locations to physical locations, such as mappings of extent identifiers to virtual storage objects and mappings of virtual storage objects to storage unit locations. When particular data is relocated to a new location, a storage administrator may update mappings used to translate virtual locations to physical locations, such as an extent-object mapping or an object-storage unit mapping. References to the virtual locations, such as references to logical extent identifiers, may not be updated in response to the relocation of data.

CACHING AND TIERING FOR CLOUD STORAGE

Various systems and methods for caching and tiering in cloud storage are described herein. A system for managing storage allocation comprises a storage device management system to maintain an access history of a plurality of storage blocks of solid state drives (SSDs) managed by the storage device management system; and automatically configure each of a plurality of storage blocks to operate in cache mode or tier mode, wherein a ratio of storage blocks operating in cache mode and storage blocks operating in tier mode is based on the access history.

MANAGING OPERATIONS ON STORED DATA UNITS

A system for managing storage of data units includes a data storage system (106) configured to store multiple data blocks (202A-202C), at least some of the data blocks containing multiple data units, with at least a group of the data blocks being stored contiguously, thereby supporting a first read operation (340) that retrieves data units from at least two adjacent data blocks in the group. The system is configured to perform one or more operations with respect to data units, the operations including a delete operation (300) that replaces a first data block containing a data unit to be deleted with a second data block that does not contain the deleted data unit, with the second data block having the same size as the first data block.

Système et méthode pour structurer et accéder aux données des tenants dans un environnement hiérarchique multiutilisateur.

L'invention concerne un système de stockage de données hiérarchique multiutilisateur (300), où des nœuds tenants (305, 306, 307) sont organisés en arbres et sous-arbres comprenant des partitions virtuelles et les données des tenants sur des partitions individuelles. Le système (300) est configuré pour permettre un accès parallèle évolutif par une pluralité de tenants-utilisateurs. L'invention concerne également une méthode pour traiter des demandes d'accès parallèles ainsi qu'une méthode de configuration d'un accès parallèle à des noeuds tenants.

Method and apparatus processing data

Embodiments of the present invention provide a method for processing data, which comprises: constructing a data window that slides along a data flow, wherein a length of the data window is a preset number of bytes; when the data window slides, determining whether a hash value corresponding to central position data of the data window is an extreme value; if yes, determining that a position is a first intermediate extreme value point, and the data window continuing to slide so as to determine subsequence intermediate extreme value points; if no, the data window continuing to slide so as to determine the first intermediate extreme value point; and extracting data between adjacent intermediate extreme value points to form valid data fragments and using data except for intermediate extreme value points as invalid data fragments. The embodiments of the present invention also provide an apparatus for processing the data. Adoption of the present invention can improve an effect of data deduplication ...

A method and system for determining an operational state of a large data storage system

For adaptive persistence of the system, method and interface

COMPUTING SYSTEM WITH DISTRIBUTED COMPUTABLE STORAGE GROUP AND OPERATING METHOD THEREOF

The present invention relates to a computing system having a distributed computable storage group. The computing system includes: a storage device to perform in-storage processing with formatted data based on application data from an application, and return an in-storage processing output to the application for continued execution. COPYRIGHT KIPO 2016 ...

볼륨 영역들의 중복성 제거

... 볼륨 영역들의 대략적인(coarse-grained) 중복성 제거를 수행하기 위한 시스템 및 방법. 저장 제어기는 제1 볼륨의 제1 영역이 제2 볼륨의 제2 영역과 동일하다는 것을 검출하며, 제1 볼륨은 제1 매체를 가리키고, 제2 볼륨은 제2 매체를 가리킨다. 동일 영역들의 검출에 응답하여, 저장 제어기는 제1 매체의 제1 범위가 제2 매체의 제2 범위의 기저가 된다는 지시를 저장한다. 또한, 동일 영역들의 검출에 응답하여, 제2 매체의 제2 범위와 관련된 맵핑들이 무효화된다.

COMPUTER SYSTEM HAVING MAIN MEMORY AND CONTROL METHOD THEREOF

CONCURRENT RESPONSE FOR DEVICE INFORMATION DURING AN INITALIZATION PROCESS FOR A STORAGE DEVICE

Methods operable on a storage controller and related structure are provided for responding to inquiry commands from a host for a storage device. A command requesting information about a storage device is received from a host. In response to the command, the storage controller determines that the storage device is not initialized, and begins an initialization process for the storage device. Information received from the storage device during the initialization process is stored for completing a response to the inquiry. A response to the inquiry is transmitted to the host based on the stored information to complete the inquiry without waiting for the storage device to complete the initialization.

SYSTEMS AND METHODS FOR COMPRESSION OF DATA FOR BLOCK MODE ACCESS STORAGE

Systems and methods for creating, reading, and writing compressed data for use with a block mode access storage. The compressed data are packed into plurality of compressed units and stored in a storage logical unit (LU). One or more corresponding compressed units may be read and/or updated with no need of restoring the entire storage logical unit while maintaining de-fragmented structure of the LU.

ONLINE MEASUREMENT OF POTENTIAL DEDUPLICATION EFFICIENCY

A computer-implemented method, according to one embodiment, includes: determining which of a plurality of fingerprints correspond to a copy of user data stored in one or more logical volumes at a storage location, and which of the plurality of fingerprints correspond to a pointer that points to a copy of user data stored in the one or more logical volumes at the storage location. A number of unique fingerprints is determined, and a number of the copies of user data stored in the one or more logical volumes is determined. The number of the copies of user data and the number of unique fingerprints are used to calculate an actual deduplication efficiency value. The number of the copies of user data and the number of unique fingerprints are used to calculate a potential deduplication efficiency value. The actual deduplication efficiency value is compared to the potential deduplication efficiency value.

Efficient management of reference blocks used in data deduplication

Various aspects for managing data blocks in a storage system are provided. For instance, a method may include storing, in a buffer memory, a plurality of comparison blocks, initiating a data deduplication process utilizing the plurality of comparison blocks, and performing garbage collection in conjunction with the data deduplication process. Garbage collection may include maintaining a hit count for comparison blocks of a passive set of comparison blocks in the buffer memory and deleting the passive set from the buffer memory when the hit count is decremented to a predetermined value. The hit count may be incremented and decremented based on utilization of a comparison block in the data deduplication process.

SYSTEM AND METHOD FOR CONTROLLING THE PERFORMANCE OF SERIAL ATTACHED SCSI (SAS) TARGET DEVICES

A system and method for controlling the performance of one or more target devices. A connection request for a target device of a plurality of target devices is received at a serial attached SCSI (SAS) Expander from an SAS initiator device, wherein a maximum performance availability value is associated with the target device. If the current performance availability value of the target device indicates that the target device does have availability to service the connection request, the connection request from the SAS initiator device is accepted and a connection is established between the SAS initiator device and the target device. Alternatively, if the current performance availability value of the target device indicates that the target device does not have availability to service the connection request, the connection request from the SAS initiator device is rejected and a connection is not established between the SAS initiator device and the target device. Traffic flow between the devices ...

Data storage space recovery system and method

A process of determining explicitly free data space in computer data storage systems with implicitly allocated data space through the use of information provided by a hosting computer system with knowledge of what space allocated is currently being used at the time of a query, is provided. In one embodiment, a File System ("FS") is asked to identify clusters no longer in use which is then mapped to physical disks as visible to an Operating System ("OS"). The physical disks are mapped to simulated/virtualized volumes presented by a storage subsystem. By using server information regarding the FS, for those pages that are no longer in use, point in time copy ("PITC") pages are marked for future PITC and will not be coalesced forward, thereby saving significant storage.

Write-optimized nested trees

A Bε-tree associated with a file system on a storage volume includes a hierarchy of nodes. Each node includes a buffer portion that can be characterized by a fixed maximum allowable size to store key-value pairs as messages in the buffer. Messages can be initially buffered in the root node of the Bε-tree, and flushed to descendent children from the root node. Messages stored in the buffers can be indexed using a B+-tree data structure. As the B+-tree data structure in a buffer grows (due to receiving flushed messages) and shrinks (due to messages being flushed), disk blocks can be allocated from the storage volume to increase the actual size of the buffer and deallocated from the buffer to reduce the actual size of the buffer.

DYNAMICALLY LIMITING VEHICLE OPERATION FOR BEST EFFORT ECONOMY

Vehicle operation (e.g., speed, acceleration) may be limited based on various conditions such as a current charge condition of an electrical energy storage devices (e.g., batteries, super- or ultracapacitors), history of such, conditions related to the vehicle (e.g., mileage, weight, size, drag coefficient), a driver or operator of the vehicle (e.g., history with respect to speed, acceleration, mileage) and/or environmental conditions (e.g., ambient temperature, terrain). A controller may control operation of one or more power converters to limit current and/or voltage supplied to a traction electric motor, accordingly.

Delaying deletion of a dataset

Delaying deletion of a dataset, including: associating an eradication timer with the dataset, wherein the eradication timer specifies an amount of time to delay a requested deletion of the dataset; determining that the amount of time to delay the requested deletion of the dataset should be modified; and modifying the eradication timer to specify a modified amount of time to delay the requested deletion of the dataset.

System for permanent file deletion

A system for permanent data deletion is provided. The file deletion system consists of a permanent deletion unit, an analysis module, a database of rules for forming deletion algorithm and an algorithm forming unit. A file to be deleted is passed into the system and the system permanently deletes the file. The system dynamically forms the deletion algorithm based on algorithm forming rules. The rules are selected from the database according to file parameters and user criteria. The file parameters are determined by the analysis module. A user has an access to algorithm forming rules and can edit the rules. Algorithm forming rules can be based on an arbitrary number of complex conditions.

Information processing system and method of controlling the same

An information processing system in which a plurality of information processing apparatuses are connected with each other, wherein each information processing apparatus includes a storage unit configured to store data according to each destination information processing apparatus, and a transmission control unit configured to transmit data to be transmitted in the same transmission direction and with the same number of hops collectively among the data stored in the storage unit.

USB-TO-SATA HIGH-SPEED BRIDGE

СИСТЕМА И СПОСОБ ПРОГНОЗИРОВАНИЯ ЭФФЕКТИВНОСТИ ПАМЯТИ

... 1. Реализуемый компьютером способ, содержащийзадание оптимального времени (t) выполнения для параллельной операции в памяти, производимой в системе на основе транзакционной памяти;ассоциирование вероятности (р) прекращения с оптимальным временем (t) выполнения на основе, по меньшей мере частично, кривой вероятностей, причем кривая вероятностей выведена эмпирически и основана на эффективности системы на основе транзакционной памяти; иопределение вероятного времени (T) выполнения для параллельной операции в памяти на основе, по меньшей мере частично, вероятности (р) прекращения.2. Реализуемый компьютером способ по п.1, дополнительно содержащий задание уровня (с) параллелизма для системы на основе транзакционной памяти.3. Реализуемый компьютером способ по п.2, дополнительно содержащийопределение времени (T) последовательного выполнения для параллельной операции в памяти на основе, по меньшей мере частично:оптимального времени (t) выполнения для параллельной операции в памяти, иуровня (с) параллелизма ...

Intelligentes System zur Bestimmung einer optimalen Partitionsgrösse in einer auf Bestellung fertigenden Umgebung

Ein intelligentes System zum Bestimmen einer optimalen Partitionsgröße auf einem Informationsverarbeitungssystem. Das System bietet Kunden eine verbesserte Kundenerfahrung durch Anbieten einer Partition, deren Größe nur so groß wie notwendig ist, entsprechend optionalen/gesperrten Prüfdaten, die für dieses System heruntergeladen werden.

STORAGE INSTRUCTION DELAY RECONCILIATION IN A CONCATENATED MEMORY TOPOLOGY

MANAGING OPERATIONS ON STORED DATA UNITS

Abstract: A system for managing storage of data units includes a data storage system (106) configured to store multiple data blocks (202A-202C), at least some of the data blocks containing multiple data units, with at least a group of the data blocks being stored contiguously, thereby supporting a first read operation (340) that retrieves data units from at least two adjacent data blocks in the group. The system is configured to perform one or more operations with respect to data units, the operations including a delete operation (300) that replaces a first data block containing a data unit to be deleted with a second data block that does not contain the deleted data unit, with the second data block having the same size as the first data block. WO 2014/137587 PCT/US2014/016858 (04 -'j C) co w ii 0) 0 0 *. LU 4 ( ) C) 0 N LUI - LU LU LU LU U)C U)( L- - -L o -j 0 -j d3 oC() w 0 C) LU LU LU 0: w w 0 0 0 0 0 0 0 *' 0 LU U LU LU LU LU LUJ C)' w/ CC) ...

STORAGE VOLUME CREATION METHOD AND APPARATUS, SERVER, AND STORAGE MEDIUM

Disclosed are a storage volume creation method and apparatus, a server, and a storage medium. The method comprises: obtaining the attribute information of a storage volume to be created, and the information of a joint storage pool used for creating the storage volume to be created; selecting a target sub storage pool in the joint storage pool corresponding to the information of the joint storage pool, wherein the joint storage pool comprises at least one sub storage pool; and according to the attribute information of the storage volume to be created, creating the storage volume in the target sub storage pool by means of a physical storage medium therein.

ARRANGING AND DESTAGING DATA TO HOLOGRAPHIC STORAGE

Data for storage by holographic data storage is arranged in an intermedia te data storage as data segments which are replicas of holographic storage s egments. Files of data are aggregated into the data segments, and a destagin g control determines the destaging of the data segments to the holographic d ata storage in accordance with a plurality of policies, such as whether a se gment is full, a time threshold has been reached, or whether a threshold num ber of segments are "open". The intermediate data storage may be arranged in to a number of partitions at least equal to the number of sources having inp ut to the data destaging system, the partitions comprising integral multiple s of the data segments.

Has a plurality of the inn of the use in the storage controller of the I/O request transfer area locking method and structure

Management by a protective device

서비스가능한 비휘발성 메모리 모듈들을 인에이블시키는 서버 플랫폼 아키텍처들을 위한 방법 및 장치

... 컴퓨터 시스템들에서 메모리 컴포넌트들의 서비싱을 용이하게 할 수 있는 서버 아키텍처들을 구현하는 시스템들 및 방법들이 개시된다. 시스템들 및 방법들은 시스템 메모리 및 대용량 스토리지, 뿐만 아니라 펌웨어 메모리를 위해 사용될 수 있는 비휘발성 메모리(NVM)를 포함하는 비휘발성 메모리/스토리지 모듈들을 사용한다. 각자의 NVM/스토리지 모듈들은 컴퓨터 시스템들의 전방 또는 후방-로딩 베이들에 수용될 수 있다. 시스템들 및 방법들은 단일, 듀얼, 또는 쿼드 소켓 프로세서들을 추가로 사용하며, 여기서 각각의 프로세서가 하나 이상의 메모리 및/또는 입력/출력(I/O) 채널들에 의해 전방 또는 후방-로딩 베이들에 배치된 NVM/스토리지 모듈들 중 적어도 일부에 통신가능하게 연결된다. 컴퓨터 시스템들의 전방 또는 후방-로딩 베이들에 수용될 수 있는 NVM/스토리지 모듈들을 사용함으로써, 시스템들 및 방법들은 종래의 서버 아키텍처들을 구현하는 컴퓨터 시스템들에서 지금까지 달성할 수 없었던 메모리 컴포넌트 서비스가능성을 제공한다.

METHOD AND SYSTEM FOR QUEUING TRANSFERS OF MULTIPLE NON-CONTIGUOUS ADDRESS RANGES WITH A SINGLE COMMAND

저장 시스템에서의 복사 수행

... 복사 오프로드 작업들을 수행하기 위한 시스템 및 방법. (제1 매체를 가리키는) 제1 볼륨으로부터 (제2 매체를 가리키는) 제2 볼륨으로의 복사 오프로드 작업이 요청될 때, 복사되는 데이터에 액세스하지 않고서 복사 오프로드 작업이 수행된다. 제3 매체가 생성되고, 제1 매체가 제3 매체의 기저 매체로서 기록된다. 제1 볼륨은 제3 매체를 다시 가리킨다. 또한, 제4 매체가 생성되고, 제2 볼륨이 제4 매체를 다시 가리키며, 제2 매체는 제4 매체의 목표 범위의 기저 매체로서 기록된다. 제4 매체의 모든 다른 범위들은 제2 매체를 그들의 기저 매체로서 갖는다.

Apparatus, method and article for providing vehicle diagnostic data

A network of collection, charging and distribution machines collects, charges and distributes portable electrical energy storage devices (e.g., batteries, supercapacitors or ultracapacitors). Vehicle diagnostic data of a vehicle using the portable electrical energy storage device is stored on a diagnostic data storage system of the portable electrical energy storage device during use of a respective portable electrical energy storage device by a respective vehicle. Once the user places the portable electrical energy storage device in the collection, charging and distribution machine, or comes within wireless communications range of a collection, charging and distribution machine, a connection is established between the collection, charging and distribution machine and the portable electrical energy storage device. The collection, charging and distribution machine then reads vehicle diagnostic data stored on the diagnostic data storage system of the portable electrical energy storage device ...

Thermal management of components in electric motor drive vehicles

Thermal management of various components such as electrical energy storage devices (e.g., batteries, super- or ultracapacitors), power converters and/or control circuits, in electrically powered vehicles may employ active temperature adjustment devices (e.g., Peltier devices), which may advantageously be powered using electrical energy generated by the traction electric motor during regenerative braking operation. Temperature adjustment may include cooling or heating one or more components. The adjustment may be based on a variety of factors or conditions, for instance sensed temperature, sensed current draw, sensed voltage, sensed rotational speed.

A portable electrical energy storage device collection,charging and distrbution machne, anoperating method thereof,and a non-transitorycomputer-readable medium for storing instructions

SNAPSHOTS IN A STORAGE SYSTEM

A system and method for creating and managing snapshots. Mediums are recorded and maintained, all of which are read-only except for the most recent mediums in use by a volume. Multiple volumes may be maintained, including a first volume which points to a first medium. When a snapshot of the first volume is taken, a second medium is created that points to the first medium. The first volume is also updated to point to the second medium. The first medium becomes the underlying medium of the second medium, and lookups are performed initially on the second medium and then on the first medium if the data is not located in the second medium.

ARRANGING AND DESTAGING DATA TO HOLOGRAPHIC STORAGE

Data for storage by holographic data storage is arranged in an intermediate data storage as data segments which are replicas of holographic storage segments. Files of data are aggregated into the data segments, and a destaging control determines the destaging of the data segments to the holographic data storage in accordance with a plurality of policies, such as whether a segment is full, a time threshold has been reached, or whether a threshold number of segments are "open". The intermediate data storage may be arranged into a number of partitions at least equal to the number of sources having input to the data destaging system, the partitions comprising integral multiples of the data segments.

MERGING DATA VOLUMES AND DERIVATIVE VERSIONS OF THE DATA VOLUMES

Disclosed are systems, methods, and software for performing version control. In a particular embodiment, a non-transitory computer readable medium is provided having stored therein program instructions that, when executed by a computer system, direct the computer system to perform a method of version control. The method includes executing a plurality of virtual machines from a plurality of derivative versions of an ancestor data volume, wherein the ancestor data volume and the plurality of derivative versions each comprise a plurality of files. The method further includes tracking modifications to the plurality of files in each of the plurality of derivative versions and merging the plurality of derivative versions with the ancestor data volume based on the modifications.

TECHNIQUES FOR PROVIDING I/O HINTS USING I/O FLAGS

Techniques for processing I/O operations may include: issuing, by a process of an application on a host, an I/O operation; determining, by a driver on the host, that the I/O operation is a read operation directed to a logical device used as a log to log writes performed by the application, wherein the read operation reads first data stored at one or more logical addresses of the logical device; storing, by the driver, an I/O flag in the I/O operation, wherein the I/O flag has a first flag value denoting an expected read frequency associated with the read operation; sending the I/O operation from the host to the data storage system; and performing first processing of the I/O operation on the data storage system, wherein said first processing includes using the first flag value in connection with caching the first data in a cache of the data storage system.

SYSTEM AND METHOD FOR LOGICAL DELETION OF STORED DATA OBJECTS

Systems and methods for providing object versioning in a storage system may support the logical deletion of stored objects. In response to a delete operation specifying both a user key and a version identifier, the storage system may permanently delete the specified version of an object having the specified key. In response to a delete operation specifying a user key, but not a version identifier, the storage system may create a delete marker object that does not contain object data, and may generate a new version identifier for the delete marker. The delete marker may be stored as the latest object version of the user key, and may be addressable in the storage system using a composite key comprising the user key and the new version identifier. Subsequent attempts to retrieve the user key without specifying a version identifier may return an error, although the object was not actually deleted.

Methods and systems for quick and efficient data management and/or processing

System(s) and method(s) are provided for data management and data processing. For example, various embodiments may include systems and methods relating to relatively larger groups of data being selected with comparable or better performing selection results (e.g., high data redundancy elimination and/or average chunk size). In various embodiments, the system(s) and method(s) may include, for example a data group, block, or chunk combining technique or/and a data group, block, or chunk splitting technique. Various embodiments may include a first standard or typical data grouping, blocking, or chunking technique and/or data group, block, or chunk combining technique or/and a data group, block, or chunk splitting technique. Exemplary system(s) and method(s) may relate to data hashing and/or data elimination. Embodiments may include a look-ahead buffer and determine whether to emit small chunks or large chunks based on characteristics of underlying data and/or particular application of the ...

DATA PROCESSING SYSTEM

A data processing system may include at least two memory systems including first and second memory systems to which a logical address and a command are applied in parallel from a host. The first memory system may store a plurality of first physical addresses for physically indicating a plurality of first pages included in a first non-volatile memory device as a first table, and determines whether to perform a preset operation corresponding to the applied command according to whether a physical address generated by performing a preset operation on the applied logical address exists in the first table, and the second memory system may store a plurality of second physical addresses for physically indicating a plurality of second pages included in a second non-volatile memory device as a second table, and determines whether to perform the preset operation corresponding to the applied command according to whether a physical address generated by performing the preset operation on the applied ...

Massively scalable object storage system

Several different embodiments of a massively scalable object storage system are described. The object storage system is particularly useful for storage in a cloud computing installation whereby shared servers provide resources, software, and data to computers and other devices on demand. In several embodiments, the object storage system includes a ring implementation used to associate object storage commands with particular physical servers such that certain guarantees of consistency, availability, and performance can be met. In other embodiments, the object storage system includes a synchronization protocol used to order operations across a distributed system. In a third set of embodiments, the object storage system includes a metadata management system. In a fourth set of embodiments, the object storage system uses a structured information synchronization system. Features from each set of embodiments can be used to improve the performance and scalability of a cloud computing object storage ...

EFFICIENT MEMORY DEDUPLICATION BY HYPERVISOR INITIALIZATION

Systems and methods for performing data deduplication of storage units. An example method may comprise: receiving a request to initialize a portion of a data storage; modifying a content of a storage unit to comprise an initialization value; updating, by a processing device, a content indicator to represent the initialization value of the storage unit; determining in view of the content indicator that a plurality of storage units comprise matching content; and updating the storage unit to comprise a reference to the matching content of one of the plurality of storage units that comprise the matching content.

Data accessing method using data protection with aid of parity check matrix having partial sequential information, and associated apparatus

A data accessing method using data protection with aid of a parity check matrix having partial sequential information, and associated apparatus such as memory device, memory controller, and decoding circuit thereof are provided. The data accessing method may include: in response to a read request, starting receiving protected data corresponding to the read request from predetermined storage space; generating the parity check matrix; performing syndrome calculation based on the parity check matrix according to a codeword to generate and output a syndrome for the codeword; performing error detection according to the syndrome to generate and output a decoding result signal, and performing error location decoding according to the syndrome to generate and output an error location; performing error correction of the codeword, to correct an error at the error location of the codeword; and performing further processing according to the one or more codewords obtained from the protected data.

Storage controller for handling data stream and method thereof

A storage controller for handling data stream having data integrity field (DIF) and method thereof. The storage controller comprises a host-side I/O controller for receiving a data stream from a host entity, a host-side I/O controller for connecting to a physical storage device, and, a central processing circuitry having at least one DIF I/O interface for handling DIF data so as to reduce the number of memory access to the main memory of the storage controller.

Memory command delay balancing in a daisy-chained memory topology

A methodology for a daisy-chained memory topology wherein, in addition to the prediction of the timing of receipt of a response from a memory module (DIMM), the memory controller can effectively predict when a command sent by it will be executed by the addressee DIMM. By programming DIMM-specific command delay in the DIMM's command delay unit, the command delay balancing methodology according to the present disclosure normalizes or synchronizes the execution of the command signal across all DIMMs in the memory channel. With such ability to predict command execution timing, the memory controller can efficiently control power profile of all the DRAM devices (or memory modules) on a daisy-chained memory channel. A separate DIMM-specific response delay unit in the DIMM may also be programmed to provide DIMM-specific delay compensation in the response path, further allowing the memory controller to accurately ascertain the timing of receipt of a response thereat, and, hence, to better manage ...

METHOD AND SYSTEM FOR MAINTAINING RELEASE CONSISTENCY IN SHARED MEMORY PROGRAMMING

A method and system for maintaining release consistency in shared memory programming on a computing device having multiple processing units includes, in response to a page fault, initiating a transfer, from one processing unit to another, of data associated with more than one but less than all of the pages of shared memory.

Storage management systems and methods

A hardware-based storage node manager enables processing devices to perform file access operations without invoking the file-data access functions of an operating system.

PHASENEINSTELLVORRICHTUNG UND VERFAHREN FÜR EIN SPEICHERBAUSTEIN-SIGNALISIERUNGSSYSTEM

Predicting backup data volumes, occupancy and cost of a backup system

Disclosed is a method that predicts the managed backup occupancy of a backup system. The method determines the current managed backup occupancy of the backup system, the expected occupancies of backups taken by the backup system per predetermined time period, the expected growth rate of a protected data volume of the backup system per time period, and are the data volumes of existing backups that are expected to expire within the next few time periods. The method then calculates a predicted managed backup occupancy after n time periods based on the above determined values. The above values may be the average of the real measured values over the previous time period, which may be a year. The predicted backup data volumes may be used in a cost comparison engine to work out the cost of backing up the predicted data on the existing system or on an alternative system.

Virtual memory metadata management

PHASE RIGGING DEVICE AND PROCEDURE FOR A MEMORY MODULE SIGNALING SYSTEM

Managing operations on stored data units

A system for managing storage of data units includes a data storage system (106) configured to store multiple data blocks (202A-202C), at least some of the data blocks containing multiple data units, and configured to store, for at least some of the data blocks, corresponding historical information (214) about prior removal of one or more data units from that data block, the removal affecting at least some addresses of data units in that data block. The system is configured to perform at least one operation that accesses at least a first data unit stored in a first data block according to address information interpreted based on any stored historical information corresponding to the first data block.

For collecting, charging and distribution such as a battery such as the electric power storage device of the apparatus, method and article

Caching and tiering for cloud storage

For processing message device and method

MEDIA CONTENT CACHING

A playback device includes tangible storage configured to receive transfer of media content from a remote communications device to the playback device while the remote communications device is operating in a high power mode. Interface logic is coupled to the tangible storage and configured to signal the remote communications device during the transfer to prepare the remote communications device to enter a low power mode after the transfer is complete. The remote communications device includes a content manager configured to transfer of media content from the remote communications device to a playback device while the remote communications device is operating in a high power mode. Power logic is coupled to the content manager and configured to prepare the remote communications device to enter a low power mode after the transfer is complete, responsive to receipt of a signal from the playback device during the transfer is complete.

서비스가능한 비휘발성 메모리 모듈들을 인에이블시키는 서버 플랫폼 아키텍처들을 위한 방법 및 장치

... 컴퓨터 시스템들에서 메모리 컴포넌트들의 서비싱을 용이하게 할 수 있는 서버 아키텍처들을 구현하는 시스템들 및 방법들이 개시된다. 시스템들 및 방법들은 시스템 메모리 및 대용량 스토리지, 뿐만 아니라 펌웨어 메모리를 위해 사용될 수 있는 비휘발성 메모리(NVM)를 포함하는 비휘발성 메모리/스토리지 모듈들을 사용한다. 각자의 NVM/스토리지 모듈들은 컴퓨터 시스템들의 전방 또는 후방-로딩 베이들에 수용될 수 있다. 시스템들 및 방법들은 단일, 듀얼, 또는 쿼드 소켓 프로세서들을 추가로 사용하며, 여기서 각각의 프로세서가 하나 이상의 메모리 및/또는 입력/출력(I/O) 채널들에 의해 전방 또는 후방-로딩 베이들에 배치된 NVM/스토리지 모듈들 중 적어도 일부에 통신가능하게 연결된다. 컴퓨터 시스템들의 전방 또는 후방-로딩 베이들에 수용될 수 있는 NVM/스토리지 모듈들을 사용함으로써, 시스템들 및 방법들은 종래의 서버 아키텍처들을 구현하는 컴퓨터 시스템들에서 지금까지 달성할 수 없었던 메모리 컴포넌트 서비스가능성을 제공한다.

Storage controller for handling data stream and method thereof

Apparatus, method and article for physical security of power storage devices in vehicles

Data processing system with out of order transfer

Various embodiments of the present inventions provide systems and methods for data processing with out of order transfer. For example, a data processing system is disclosed that includes a data processor operable to process input blocks of data and to yield corresponding processed output blocks of data, wherein the processed output blocks of data are output from the data processor in an order in which their processing is completed, and a scheduler operable to receive processing priority requests for the input blocks of data and to assign processing resources in the data processor according to the priority requests.

Storage system

A host I/F unit has a management table for managing an MPPK which is in-charge of the control of input/output processing for a storage area of an LDEV, and if a host computer transmits an input/output request for the LDEV, the host I/F unit transfers the input/output request to the MPPK which is in-charge of the input/output processing for the LDEV based on the management table, an MP of the MPPK performs the input/output processing based on the input/output request, and the MP of the MPPK also judges whether the MPPK that is in-charge of the input/output processing for the LDEV is to be changed, and sets the management table so that an MPPK which is different from the MPPK that is in-charge is to be in-charge of the input/output processing for the LDEV.

Independently configurable remapping for interconnect access requests

Access control request parameter remapping may be implemented that supports user-configurable and host-configurable processing stages. A request may be received and evaluated to determine user-configured remapping is applied, host-configured remapping is applied or both user and host remapping applied. For applied remapping, an unmasked portion of a parameter of the access request may be replaced with a corresponding portion of a remap parameter.

DATA ACCESS METHOD OF A MEMORY DEVICE

The invention provides a data access method of a memory device. In one embodiment, the memory device comprises a plurality of memories. First, a plurality of commands sequentially received from a host is stored in a command queue. A target command is then retrieved from the command queue. A target memory accessed by the target command is then determined Whether the target memory is in a busy state is then determined When the target memory is not in a busy state, access operations requested by the target command are then performed. When the target memory is in a busy state, a substitute command is selected from a plurality of subsequent commands stored in the command queue and access operations requested by the substitute command are performed, wherein the sequence of the subsequent commands in the command queue is subsequent to the target command. 1. A data access method of a memory device , wherein the memory device comprises a plurality of memories , comprising:storing a plurality of commands sequentially received from a host in a command queue;retrieving a target command from the command queue;determining a target memory accessed by the target command;determining whether the target memory is in a busy state;when the target memory is not in a busy state, performing access operations requested by the target command; andwhen the target memory is in a busy state, selecting a substitute command from a plurality of subsequent commands stored in the command queue and performing access operations requested by the substitute command, wherein the sequence of the subsequent commands in the command queue is subsequent to the target command,wherein selection of the substitute command comprises:selecting a candidate substitute command from the subsequent commands stored in the command queue;determining a logical address range accessed by the candidate substitute command;determining a plurality of reference address ranges accessed by a plurality of prior commands stored in the ...

COMPUTER SYSTEM BACKUP PERFORMANCE OPTIMIZATION THROUGH PERFORMANCE ANALYTICS

Embodiments in accordance with the present invention disclose a method, computer program product, and system for optimizing performance of a computer backup solution that includes at least two data movers. The automated method includes measuring data mover performance during operation of a backup cycle, and optimizing the performance of data movers by increasing or decreasing the number of threads operating concurrently in the data movers. The method further includes computation of performance rankings of the data movers and shifting workload among the data movers in accordance with their respective performance rankings, such that the computer backup solution converges toward an optimized configuration.

Increasing performance of write throughput using machine learning

Techniques for processing data may include: determining a first amount denoting an amount of write pending data stored in cache to be redirected through storage class memory (SCM) when destaging cached write pending data from the cache; performing first processing that destages write pending data from the cache, the first processing including: selecting, in accordance with the first amount, a first portion of write pending data that is destaged from the cache and stored in the SCM and a second portion of write pending data that is destaged directly from the cache and stored on one or more physical storage devices providing back-end non-volatile physical storage; and subsequent to storing the first portion of write pending data to the SCM, transferring the first portion of write pending data from the SCM to the one or more physical storage devices providing back-end non-volatile physical storage.

Systems, methods, and computer readable media for an adaptative block allocation mechanism

Systems, methods, and computer readable media for an adaptive block allocation mechanism are disclosed. According to one aspect, a method for allocating slices of storage in a storage medium based on scores is disclosed. The method occurs at a storage processor for controlling access to a storage medium divided into a plurality of logical slices of storage. The method includes determining one or more scores associated with one or more slices. Determining one or more scores includes combining plural dissimilar characteristics of the slice into a single value. The method further includes receiving a slice allocation request, and in response to the slice allocation request, selecting a slice for allocation using the scores.

Electronic storage module, method for assigning contacts of an electronic storage module, method for implementing an assignment

Provided are an electronic storage module, a method for assigning contacts of an electronic storage module and a method for implementing an assignment. Exemplary modules include chip cards such as SIM cards (Subscriber Identification Modules), in particular but not limited to cards that use six contacts. The electronic storage module has a plurality of contacts, including at least one reset contact and at least one first set of contacts forming a first communication interface between the electronic storage module and an electronic device including the electronic storage module. The set of contacts constitutes at least one second communication interface. The reset contact makes it possible to indicate which one of the first or second communication interfaces the first set of contacts uses at a given time.

Methods and systems for data cleanup using physical image of files on storage devices

Methods, systems, and computer program products are provided for optimizing selection of files for eviction from a first storage pool to free up a predetermined amount of space in the first storage pool. A method includes analyzing an effective space occupied by each file of a plurality of files in the first storage pool, identifying, from the plurality of files, one or more data blocks making up a file to free up the predetermined amount of space based on the analysis of the effective space of each file of the plurality of files, selecting one or more of the plurality of files as one or more candidate files for eviction, based on the identified one or more data blocks, and evicting the one or more candidate files for eviction from the first storage pool to a second storage pool.

DIMM SSD SOC DRAM BYTE LANE SKEWING

A Dual In-Line Memory Module (DIMM) Solid State Drive (SSD) System-on-a-Chip (SoC) ( 345 ) is disclosed. The DIMM SSD SoC ( 345 ) can interoperate with a host memory controller ( 335 ) as though it were a traditional Dynamic Random Access Memory (DRAM) DIMM ( 105, 130 ) with system interconnect skew and on-DIMM skew, even though the DIMM SSD SoC ( 345 ) does not have on-DIMM skew. The DIMM SSD SoC ( 345 ) can include variable delay elements ( 422, 424, 426, 428, 430, 432, 434, 436, 438 ) that can replicate the delay a traditional DRAM DIMM ( 105, 130 ) experiences and that the host memory controller ( 335 ) expects, or a superior delay that minimizes system signal integrity issues, thereby increasing maximum system speed.

APPARATUS, METHOD AND ARTICLE FOR REDISTRIBUTING POWER STORAGE DEVICES, SUCH AS BATTERIES, BETWEEN COLLECTION, CHARGING AND DISTRIBUTION MACHINES

A network of collection, charging and distribution machines collect, charge and distribute portable electrical energy storage devices. To charge, the machines employ electrical current from an external source. As demand at individual collection, charging and distribution machines increases or decreases relative to other collection, charging and distribution machines, a distribution management system initiates redistribution of portable electrical energy storage devices from one collection, charging and distribution machine to another collection, charging and distribution machine in an expeditious manner. Also, redeemable incentives are offered to users to return or exchange their portable electrical energy storage devices at selected collection, charging and distribution machines within the network to effect the redistribution.

RDMA DATA SENDING AND RECEIVING METHODS, ELECTRONIC DEVICE, AND READABLE STORAGE MEDIUM

A Remote Direct Memory Access (RDMA) data sending method is disclosed. The method is applicable to a sending end, with a data-transmission RDMA device disposed thereon. The method includes: the data-transmission RDMA device acquiring raw data; the data-transmission RDMA device compressing the raw data by using a preset compression method to obtain compressed data; and the data-transmission RDMA device encapsulating the compressed data into a data packet, and transmitting the data packet to a receiving end. The data packet may include a method tag corresponding to the preset compression method. In this method, the compression and transmission of the raw data are conducted by the data-transmission RDMA device on the hardware level.

Indirect user authentication

As disclosed herein a computer system, executed by a computer, includes receiving, from a user, a request for access to a shared system, wherein the request comprises a user identifier and a user password corresponding to the user, and determining privileges corresponding to the shared system using the user identifier. The computer system further includes requesting, from an identity manager, a shared identifier and a shared password corresponding to the shared system, receiving, from the identity manager, the shared identifier and the shared password, and using the shared identifier and the shared password to enable the user to use the shared system.

Use of Delete Notifications By File Systems And Applications To Release Storage Space

In accordance with one or more aspects, one or more portions of each of multiple files that have been freed are determined. One or more delete notifications are generated identifying the one or more portions of the multiple files. Each portion is identified as a range of data on a storage device, and each delete notification includes one or more ranges of data on the storage device. These generated delete notifications are then sent to a storage stack. Additionally, an application can determine that one or more ranges of data of a storage device are to be freed and send a delete notification, in the absence of a file system on the device, to the storage stack identifying the one or more ranges of data of the storage device that are to be freed.

Localized data block destaging

A system includes a memory and a processor coupled to the memory, where the processor is configured to perform various operations. The operations include receiving, in response to a first read input/output operation, a first location of a first data block. The operations also include executing the first read input/output operation at the first data block at the first location. The operations also include selecting a second location within a first search range for destaging a second data block based at least in part on the first location. The operations also include destaging the second data block at the second location upon a determination that a second read input/output operation is not currently executing or queued for execution.

АДМИНИСТРИРОВАНИЕ ЗАЩИЩЕННЫМИ УСТРОЙСТВАМИ

... 1. Реализуемый в компьютере способ, содержащий этапы, на которых:принимают запрос на разблокирование зашифрованного устройства, соединенного с системой, причем запрос принимают с помощью защищенного раздела системы по защищенному каналу связи, установленному между доверяемой удаленной консолью и защищенным разделом, а защищенный раздел изолирован от основной операционной системы в системе; иразблокируют с помощью защищенного раздела зашифрованное устройство в ответ на запрос без привлечения основной операционной системы.2. Способ по п.1, дополнительно содержащий этапы, на которых:принимают маркер от доверяемой удаленной консоли с помощью защищенного раздела;ииспользуют указанный маркер для разворачивания ключа, используемого для шифрования блоков зашифрованного устройства.3. Способ по п.2, дополнительно содержащий этап, на котором:получают указанный ключ из защищенной области хранения зашифрованного устройства, причем защищенная область хранения скрыта от основной операционной системы.4 ...

PORTABLE MEMORY DEVICE WITH REMOVABLE CAPS, WHICH, IF ATTACHED, DROVE THE ENTERPRISE OUT OF THE DEVICE

Intelligent system for determining optimum partition according to customize circumstance

An intelligent system for determining an optimal partition size on an information handling system. The system provides customers with an improved customer experience by offering a partition that is sized only as large as needed according to optional/locked/trial data downloaded for that system.

Data storage device control with power hazard mode

Management server, management method, and management program for virtual hard disk

Heterogeneous multi-processor system to the shared memory region in the dynamic address negotiations

AN INTELLIGENT SYSTEM FOR DETERMINING THE OPTIMAL SIZE OF A PARTITION IN MANUFACTURING UNENVIRONNEMENT ON COMMAND

La présente invention concerne un système intelligent pour déterminer une taille optimale de partition (220) sur un système de traitement d'informations (120). Le système procure une réaction améliorée des clients en offrant une partition qui est dimensionnée pour n'avoir que la taille nécessaire fonction des données facultatives, verrouillées ou d'essai téléchargées pour ce système.

SCALABLE ARCHITECTURE ENABLING LARGE MEMORY SYSTEM FOR IN-MEMORY COMPUTATIONS

Efficient file storage and retrieval system, method and apparatus

A system, method and apparatus for efficiently storing and retrieving files by a host processing system coupled to a mass data storage device. The host processing system issues file storage and retrieval commands that are mapped to a standard or vendor-specific command by storage device drivers in the host processing system. The storage device drivers issue a single file store or file retrieve command, and a file associated with the command is stored on the mass data storage device, or retrieved from the mass data storage device, based on the single standard or vendor-specific command.

Data management method and storage controller using the same

A data management method and a storage controller are provided. The method includes: receiving write sectors corresponding to a write command and transmitting the write sectors to a partial block buffer or a full block buffer; when the write sectors corresponding to a first block are transmitted to the partial block buffer, starting a timer corresponding to the first block; when the partial block buffer receives first write sectors corresponding to the first block and the first writes sectors and the write sectors corresponding to the first block in the partial block buffer form a full first block, the first block is transmitted to the full block buffer before or at the timer expired; and when the timer is expired and the full first block is not yet formed in the partial block buffer, performing a read-modify-write operation according to the write sectors corresponding to the first block.

DATA STORAGE SPACE RECOVERY SYSTEM AND METHOD

A process of determining explicitly free data space in computer data storage systems with implicitly allocated data space through the use of information provided by a hosting computer system with knowledge of what space allocated is currently being used at the time of a query, is provided. In one embodiment, a File System ("FS") is asked to identify clusters no longer in use which is then mapped to physical disks as visible to an Operating System ("OS"). The physical disks are mapped to simulated/virtualized volumes presented by a storage subsystem. By using server information regarding the FS, for those pages that are no longer in use, point in time copy ("PITC") pages are marked for future PITC and will not be coalesced forward, thereby saving significant storage.

SCHEDULING OF READ OPERATIONS AND WRITE OPERATIONS BASED ON A DATA BUS MODE

A data bus is determined to be in a write mode. Whether a number of memory queues that identify at least one write operation satisfies a threshold criterion is determined. The memory queues include identifiers of one or more write operations and identifiers of one or more read operations. Responsive to determining that the number of memory queues satisfies the threshold criterion, a write operation from the memory queues is transmitted over the data bus. 1. A method , comprising:determining that a data bus is in a write mode;determining, by a processing device, whether a number of memory queues that identify at least one write operation satisfies a threshold criterion, wherein the memory queues comprise identifiers of one or more write operations and identifiers of one or more read operations; andresponsive to determining that the number of memory queues satisfies the threshold criterion, transmitting a write operation from the memory queues over the data bus.2. The method of claim 1 , further comprising:responsive to determining that the number of memory queues does not satisfy the threshold criterion, transmitting a read operation from the memory queues over the data bus.3. The method of claim 2 , further comprising:determining that a particular memory queue of the memory queues is available, wherein the particular memory queue is available when transmitting the read operation from the particular memory queue over the data bus satisfies a data bus protocol.4. The method of claim 2 , further comprising:responsive to determining that the number of memory queues does not satisfy the threshold criterion, changing a status of the data bus from the write mode to a read mode.5. The method of claim 1 , wherein the determining of whether the number of memory queues satisfies the threshold criterion is responsive to a write operation not being identified at an available memory queue.6. The method of claim 1 , wherein determining that the data bus is in the write mode is ...

Method and system for rapid data-fragmentation analysis of a New Technology File System

A method and system for rapid data-fragmentation analysis of a New Technology File System (NTFS) is described. In one embodiment, the Master File Table (MFT) associated with a NTFS volume is analyzed to estimate the extent of data fragmentation on the NTFS volume, the analysis being performed substantially without using directory index information associated with the NTFS volume.

Memory device signaling system and method with independent timing calibration for parallel signal paths

A memory system includes a memory controller and a memory component coupled to each other. The memory controller includes an interface to receive a first signal and a second signal from the memory component, wherein the first signal comprises a first symbol and the second signal comprises a second symbol. A first circuit of the memory controller receives the first signal by sampling the first symbol using a first timing offset relative to a reference clock signal, and a second circuit of the memory controller receives the second signal by sampling the second symbol using a second timing offset relative to the reference clock signal. The first timing offset is independent of the second timing offset.

Virtual bucket multiple hash tables for efficient memory in-line deduplication application

A method of deduplicating memory in a memory module includes identifying a hash table array including hash tables each corresponding to a hash function, and each including physical buckets, each physical bucket including ways and being configured to store data, identifying a plurality of virtual buckets each including some of the physical buckets, and each sharing at least one of the physical buckets with another of the virtual buckets, hashing a block of data according to a corresponding one of the hash functions to produce a hash value, determining whether an intended physical bucket has available space for the block of data according to the hash value, and determining whether a near-location physical bucket has available space for the block of data when the intended physical bucket does not have available space, the near-location physical bucket being in a same one of the virtual buckets as the intended physical bucket.

METADATA SPACE EFFICIENT SNAPSHOT OPERATION IN PAGE STORAGE

A method includes accessing a first top level entry of a first table of the base volume, the first top level entry having at least a first bottom level entry. The method also includes receiving a first request for a metadata snapshot of the base volume, including the first bottom level entry. The method also includes generating a second top level entry of the first table, the second top level entry configured to point to the at least first bottom level entry of the first table, and the second top level entry configured to operate as a first snapshot of the first table including the at least first bottom level entry. 1. A method , comprising:accessing a first entry of a first table of a volume, the first entry having at least a second entry of a different level than the first entry;receiving a first request for a metadata snapshot of the volume, including the second entry; andgenerating a third entry of the first table, the third entry configured to point to the at least second entry of the first table, and the third entry configured to operate as a first snapshot of the first table including the at least level second entry.2. The method of claim 1 , further comprising:receiving a second request for a metadata snapshot of the volume, including a fourth entry;receiving an indication that the fourth entry has been modified; andin response to the receiving the second request and the indication, generating a fifth entry of the first table, the fifth entry configured to operate as a second snapshot of the first table including at least the fourth entry, wherein the fifth entry operates to copy to the fourth entry to be stored in association with the fifth entry, and wherein the fifth entry is configured to point to the copy of the fourth entry.3. The method of claim 2 , wherein the receiving the indication that the fourth entry has been modified is received after the third entry of the first table is generated claim 2 , and wherein the metadata snapshot comprises a state ...

Logical unit number management device, logical unit number management method, and program therefor

A logical unit number management device includes: an access processing unit that performs information processing with access objects by using logical unit numbers for identifying logical identification information; a logical unit number management table storage unit that stores a logical unit number management table storing a corresponding relationship between the logical identification information and the logical unit numbers; a logical unit number management table changing unit that changes the corresponding relationship based on an external change request; a change completion reporting unit that reports change completion to the access processing unit when the logical unit number management table has been changed in accordance with the change request; and an access control unit that controls an access to the access object indicated by the logical identification information corresponding to one of the logical unit numbers after a report of the change completion.

Managing read requests from multiple requestors

Techniques are disclosed for managing data requests from multiple requestors. According to one implementation, when a new data request is received, a determination is made as to whether a companion relationship should be established between the new data request and an existing data request. Such a companion relationship may be appropriate under certain conditions. If a companion relationship is established between the new data request and an existing data request, then when data is returned for one request, it is used to satisfy the other request as well. This helps to reduce the number of data accesses that need to be made to a data storage, which in turn enables system efficiency to be improved.

Parallel block allocation for declustered logical disks

In a method for allocating space on a logical disk, a computer receives an allocation request to allocate a number of requested logical disk extents. The computer selects one of a first group having an array of logical disk extents and a second group having an array of logical disk extents. The computer selects a group having a number of free logical disk extents that is greater than or equal to the number of requested logical disk extents. The logical disk extents in the array of the first group and in the array of the second group correspond to disk blocks on a logical disk. The logical disk spans one or more physical random access disks. The computer locks the selected group to prevent allocating a logical disk extent other than in response to the allocation request.

Electronic devices

A storage device ( 3 ), such as an SD card, that is coupled to a host device ( 2 ), such as a mobile phone, includes a computing environment ( 8 ). The computing environment ( 8 ) includes an application processing part ( 6 ), and a separate interface processing part ( 7 ). The application processing part ( 6 ) of the computing environment 8 is operable to execute one or more applications on the storage device ( 3 ). The interface processing part ( 7 ) of the computing environment 8 includes an interface processor that interfaces between a communications protocol used between the host device ( 2 ) and the storage device ( 3 ), and a communications protocol used by the application processor in the application processing part ( 6 ) of the storage device ( 3 ). The interface processor communicates with the application processor via interrupts and a shared memory ( 9 ).

Vector-Based Matching Circuit for Data Streams

Systems and methods are described relating to a matcher that inputs partial vectors at a rate of 1 per clock cycle and delivers complete vectors at the output with an indication per vector of its validity. The matcher can copy a maximum number of valid elements from an input queue to target vector in-order each clock cycle and eliminate copied elements from the input queue. The completely filled target vectors are paired with the complete data vectors and outputted as composite vectors. 1. A method of processing addresses for addressing a memory containing data to be reordered , the method comprising:storing a first at least partial address vector and first validity information indicating which elements of the first at least partial address vector are valid,receiving a sequence of address vectors comprising a second at least partial address vector and second validity information indicating which vector elements of the second at least partial address vector are valid,transferring a number of valid vector elements from the first and second at least partial address vectors to a target address vector while replacing the stored first at least partial address vector by storing any valid vector elements of the second at least partial address vector that have not been transferred, as the first at least partial address vector, andoutputting the target vector if all of the vector elements of the target vector are valid.2. The method of claim 1 , wherein all valid elements from the first at least partial address vector are transferred claim 1 , and at least some of the valid elements from the second at least partial address vector are transferred.3. The method of claim 1 , wherein one second at least partial address vector with its validity information indicating which vector elements of the second at least partial address vector are valid is received per clock cycle.4. The method of claim 3 , wherein the validity information of the first and second at least partial address ...

Storage apparatus and data management method

The present invention provides high-speed copying of a compressed data volume. The control unit of the storage apparatus divides the pool into a plurality of chunks comprising a plurality of pages storing data, compresses data which is written to the logical volume by the host and assigns one of the plurality of chunks to a compressed data logical volume which stores the compressed data, and, when the compressed data logical volume is copied, the control unit makes the page length of the chunk which is assigned to the compressed data logical volume which is the copy source the same as the page length of the chunk which is assigned to the compressed data logical volume which is the copy destination.

Apparatus, method and article for providing vehicle diagnostic data

A network of collection, charging and distribution machines collects, charges and distributes portable electrical energy storage devices (e.g., batteries, supercapacitors or ultracapacitors). Vehicle diagnostic data of a vehicle using the portable electrical energy storage device is stored on a diagnostic data storage system of the portable electrical energy storage device during use of a respective portable electrical energy storage device by a respective vehicle. Once the user places the portable electrical energy storage device in the collection, charging and distribution machine, or comes within wireless communications range of a collection, charging and distribution machine, a connection is established between the collection, charging and distribution machine and the portable electrical energy storage device. The collection, charging and distribution machine then reads vehicle diagnostic data stored on the diagnostic data storage system of the portable electrical energy storage device and provides information regarding the diagnostic data.

Accelerated deduplication

Mechanisms are provided for accelerated data deduplication. A data stream is received an input interface and maintained in memory. Chunk boundaries are detected and chunk fingerprints are calculated using a deduplication accelerator while a processor maintains a state machine. A deduplication dictionary is accessed using a chunk fingerprint to determine if the associated data chunk has previously been written to persistent memory. If the data chunk has previously been written, reference counts may be updated but the data chunk need not be stored again. Otherwise, datastore suitcases, filemaps, and the deduplication dictionary may be updated to reflect storage of the data chunk. Direct memory access (DMA) addresses are provided to directly transfer a chunk to an output interface as needed.

Memory Component with Pattern Register Circuitry to Provide Data Patterns for Calibration

A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration.

SYSTEM AND METHOD FOR PREDICTING BACKUP DATA VOLUMES

A method and system for predicting the managed backup occupancy of a backup system are disclosed. The method includes determining the variables m, xto x, r and zto z. Variable mis the current managed backup occupancy of the backup system, xto xare the expected occupancies of backups taken by the backup system per predetermined time period T with retention periods of 0-1 time periods T, 1-2 time periods T, 2-3 time periods T and so on up to n time periods T respectively, r is the expected growth rate of a protected data volume of the backup system per time period T, and zto zare the data volumes of existing backups that are expected to expire within each of the first to nth time periods T after the current time respectively. 1. A method for predicting the managed backup occupancy of a backup system , the method comprising:{'sub': 0', 'n', '1', 'n', '0', '1', 'n', '1', 'n', 'n', '0', '1', 'n', '1', 'n, 'b': '1', 'determining variables m, x to x, r and zto z, where mis the current managed backup occupancy of the backup system, xto xare the expected occupancies of backups taken by the backup system per predetermined time period T with retention periods of 0-1 time periods T, 1-2 time periods T, 2-3 time periods T and so on up to n time periods T respectively, r is the expected growth rate of a protected data volume of the backup system per time period T, and zto zare the data volumes of existing backups that are expected to expire within each of the first to nth time periods T after the current time respectively; and calculating a predicted managed backup occupancy mafter n time periods T from the current time based on the variables m, xto x, r and zto z.'}2. The method according to claim 1 , further comprising:{'sub': 1', 'n', '1', 'n', 'n', '1', 'n, 'measuring average values of xto xand r for the backup system over a predetermined past time period; and setting the values of xto xand r used to calculate the predicted managed backup occupancy mto the measured average ...

Systems, methods, and interfaces for adaptive cache persistence

A storage module may be configured to service I/O requests according to different persistence levels. The persistence level of an I/O request may relate to the storage resource(s) used to service the I/O request, the configuration of the storage resource(s), the storage mode of the resources, and so on. In some embodiments, a persistence level may relate to a cache mode of an I/O request. I/O requests pertaining to temporary or disposable data may be serviced using an ephemeral cache mode. An ephemeral cache mode may comprise storing I/O request data in cache storage without writing the data through (or back) to primary storage. Ephemeral cache data may be transferred between hosts in response to virtual machine migration.

METHODS AND SYSTEMS FOR DATA CLEANUP USING PHYSICAL IMAGE OF FILES ON STORAGE DEVICES

Methods, systems, and computer program products are provided for optimizing selection of files for eviction from a first storage pool to free up a predetermined amount of space in the first storage pool. A method includes analyzing an effective space occupied by each file of a plurality of files in the first storage pool, identifying, from the plurality of files, one or more data blocks making up a file to free up the predetermined amount of space based on the analysis of the effective space of each file of the plurality of files, selecting one or more of the plurality of files as one or more candidate files for eviction, based on the identified one or more data blocks, and evicting the one or more candidate files for eviction from the first storage pool to a second storage pool. 1. A method of optimizing selection of files for eviction from a first storage pool to free up a predetermined amount of space in the first storage pool , the method comprising:analyzing an effective space occupied by each file of a plurality of files in the first storage pool;identifying, from the plurality of files, one or more data blocks making up a file to free up the predetermined amount of space based on the analysis of the effective space of each file of the plurality of files;selecting one or more of the plurality of files as one or more candidate files for eviction, based on the identified one or more data blocks; andevicting the one or more candidate files for eviction from the first storage pool to a second storage pool.2. The method of claim 1 , wherein identifying includes:after the plurality of files have undergone a deduplication process, determining whether the one or more data blocks is pointed to by an other file other than an instant file of the plurality of files being examined; andchoosing the instant file, if the one or more data blocks is not pointed to by the other file and if the instant file occupies space equal to or greater than the predetermined amount of space ...

STORAGE SYSTEM

A host I/F unit has a management table for managing an MPPK which is in-charge of the control of input/output processing for a storage area of an LDEV, and if a host computer transmits an input/output request for the LDEV, the host I/F unit transfers the input/output request to the MPPK which is in-charge of the input/output processing for the LDEV based on the management table, an MP of the MPPK performs the input/output processing based on the input/output request, and the MP of the MPPK also judges whether the MPPK that is in-charge of the input/output processing for the LDEV is to be changed, and sets the management table so that an MPPK which is different from the MPPK that is in-charge is to be in-charge of the input/output processing for the LDEV. 1. A storage system coupled to a host computer , comprising:a management computer;a plurality of storage devices that are provided as a plurality of logical storage devices to the host computer;a plurality of interface packages, each of the plurality of interface packages coupled to the management computer and comprising at least one interface unit;a shared memory that stores control information for the plurality of logical storage devices, said control information including ownership information for the logical storage devices;a plurality of micro-processor packages, each of the plurality of micro-processor packages comprising at least one micro-processor; 'a process that transfers an input/output request to a micro-processor package that is in-charge of the input/output processing for a logical storage device based on the management information when the input/output request for the logical storage device is received from the host computer;', 'wherein each interface unit comprises management information for managing the plurality of micro-processor packages, said micro-processor package in-charge of controlling input/output processing for the storage area of the logical storage devices, and'}wherein each of the ...

COMMUNICATION VIA A MEMORY INTERFACE

A memory space of a module connected to a memory controller via a memory interface may be used as a command buffer. Commands received by the module via the command buffer are executed by the module. The memory controller may write to the command buffer out-of-order. The memory controller may delay or eliminate writes to the command buffer. Tags associated with commands are used to specify the order commands are executed. A status buffer in the memory space of the module is used to communicate whether commands have been received or executed. Information received via the status buffer can be used as a basis for a determination to re-send commands to the command buffer. 1. A module , comprising:a memory interface configured to interface with a memory controller, the memory interface including a memory data interface and a memory command/address interface; and,the module to execute instructions received via the memory data interface from the memory controller, the instructions to be addressed to a memory space of the module that includes an instruction queue, the instruction queue comprising a plurality of column addresses.2. The module of claim 1 , wherein the memory space further includes a status register space claim 1 , a plurality of status register space entries each corresponding to a respective entry in the instruction queue.3. The module of claim 2 , wherein each of the status register space entries claim 2 , when read by the memory controller claim 2 , include an indicator of a status of the corresponding entry in the instruction queue.5. The module of claim 3 , wherein the indicator of the status of an entry in the instruction queue claim 3 , as read by the memory controller claim 3 , indicates whether the corresponding entry in the instruction queue has been executed by the module.6. The module of claim 3 , wherein the indicator of the status of an entry in the instruction queue claim 3 , as read by the memory controller claim 3 , indicates whether the ...

RUNTIME QUANTUM-MEMORY REMAPPING

A quantum circuit program, when executed, implements a quantum circuit in quantum memory. The quantum-circuit program specifies addresses of quantum memory locations. A runtime quantum-memory remapper can route program instructions to the memory addresses they specify or to other memory locations between the time execution of the quantum circuit begins and the time that quantum-circuit execution is completed. The remapping can take place in response to a detection of a condition in which a memory location used by the quantum circuit becomes faulty, e.g., because it lost its quantum-state carrier. Remapping the quantum circuit allows its execution to continue despite the problem with quantum memory, and, in some cases, continue during the remedying of the remapping condition. 1. A runtime quantum-memory remapping process comprising:beginning execution of a quantum circuit using a first mapping of specified addresses to physical quantum memory locations, the specified addresses being specified by a quantum-circuit program that defines the quantum circuit, the first mapping routing a first specified address to a first physical memory location;after the beginning of execution, remapping the specified address to quantum-memory locations to implement a second mapping, the second mapping routing the first specified address to a second physical memory location different from the first physical memory location;after the remapping, continuing execution of the quantum circuit using the second mapping; andcompleting execution of the quantum circuit.2. The runtime quantum-memory remapping process of further comprising detecting a remapping condition claim 1 , the remapping being in response to the detecting the remapping condition.3. The runtime quantum-memory remapping process of further comprising claim 1 , prior to continuing execution of the quantum circuit claim 1 , transferring a quantum state of a first quantum-state carrier at the first physical memory location to a ...

METHOD AND APPARATUS FOR STORE DURABILITY AND ORDERING IN A PERSISTENT MEMORY ARCHITECTURE

An apparatus and method are described for store durability and ordering in a persistent memory architecture. For example, one embodiment of a method comprises: performing at least one store operation to one or more addresses identifying at least one persistent memory device, the store operations causing one or more memory controllers to store data in the at least one persistent memory device; sending a request message to the one or more memory controllers instructing the memory controllers to confirm that the store operations are successfully committed to the at least one persistent memory device; ensuring at the one or more memory controllers that at least all pending store operations received at the time of the request message will be committed to the persistent memory device; and sending a response message from the one or more memory controllers indicating that the store operations are successfully committed to the persistent memory device. 1. A method comprising:performing at least one store operation to one or more addresses identifying at least one persistent memory device, the store operations causing one or more memory controllers to store data in the at least one persistent memory device;sending a request message to the one or more memory controllers instructing the memory controllers to confirm that the store operations are successfully committed to the at least one persistent memory device;ensuring at the one or more memory controllers that at least all pending store operations received at the time of the request message will be committed to the persistent memory device; andsending a response message from the one or more memory controllers indicating that the store operations are successfully committed to the persistent memory device.2. The method as in further comprising:initially ensuring that the store operations have been accepted to memory prior to ensuring that the store operations have been committed to the persistent memory device.3. The method as ...

Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses

In a multiprocessor system, a central memory synchronization module coordinates memory synchronization requests responsive to memory access requests in flight, a generation counter, and a reclaim pointer. The central module communicates via point-to-point communication. The module includes a global OR reduce tree for each memory access requesting device, for detecting memory access requests in flight. An interface unit is implemented associated with each processor requesting synchronization. The interface unit includes multiple generation completion detectors. The generation count and reclaim pointer do not pass one another.

MEMORY MANAGING APPARATUS AND IMAGE PROCESSING APPARATUS

The memory area managing unit (a) sets a protect flag to each virtual area allocated in a virtual memory space, the protect flag indicating whether a use of the virtual area has been finished or not, and (b) when a part or all of a first virtual area would overlap another second virtual area due to expansion or movement of the first virtual area, allows the expansion or the movement of the first virtual area accompanying with overlapping the second virtual area, if the protect flag of the second virtual area indicates that a use of the second virtual area has been finished. If the expansion or the movement is allowed, the memory pool managing unit adds a physical area in a physical memory space corresponding to an overlapping part of the first and second virtual areas into a memory pool to map to another virtual area. 1. A memory managing apparatus , comprising:a memory area managing unit that sets a flag to each virtual area allocated in a virtual memory space, the flag indicating that a use of the virtual area has been finished or not, and when a part or all of a first virtual area would overlap another second virtual area due to expansion or movement of the first virtual area, allows the expansion or the movement of the first virtual area accompanying with overlapping the second virtual area if the flag of the second virtual area indicates that a use of the second virtual area has been finished, and does not allow the expansion or the movement of the first virtual area accompanying with overlapping the second virtual area if the flag of the second virtual area does not indicate that a use of the second virtual area has been finished; anda memory pool managing unit that adds a physical area in a physical memory space corresponding to an overlapping part of the first and the second virtual areas into a memory pool in order to map the physical area to another virtual area, if the expansion or the movement of the first virtual area accompanying with overlapping the ...

VARIABLE HANDLES

According to one technique, a virtual machine generates an object configured to provide secure access to memory through one or more memory fencing operations. Through the object, the virtual machine receives a call that indicates a memory location and specifies a particular memory fencing operation of the one or more memory fencing operations to perform with respect to the memory location. The virtual machine causes performance of the particular memory fencing operation with respect to the memory location. 1. A method comprising:generating an object configured to provide secure access to memory through one or more memory fencing operations;through the object, receiving a call that indicates a memory location and specifies a particular memory fencing operation of the one or more memory fencing operations to perform with respect to the memory location;causing performance of the particular memory fencing operation with respect to the memory location; andwherein the method is performed by one or more processors.2. The method of claim 1 , wherein the object is related to a class that defines the one or more memory fencing operations claim 1 , but without including an implementation of the one or more memory fencing operations for any particular variable kind of a plurality of different variable kinds.3. The method of claim 2 , wherein the plurality of different variable kinds includes one or more of: instance field variable claim 2 , static field variable claim 2 , array element variable claim 2 , or off-heap variable.4. The method of claim 2 , wherein the object is an instance of a sub-class that extends from the class and implements the one or more memory fencing operations with respect to a particular variable kind of the plurality of different variable kinds.5. The method of claim 2 , further comprising:generating a second object that is an instance of the class;through the second object, receiving a second call that indicates a second memory location and specifies a ...

MEMORY DEVICE FIRMWARE UPDATE AND ACTIVATION WITHOUT MEMORY ACCESS QUIESCENCE

Examples include updating firmware for a persistent memory module in a computing system during runtime. Examples include copying a new version of persistent memory module firmware into an available area of random-access memory (RAM) in the persistent memory module, and transferring processing of a current version of persistent memory module firmware to the new version of persistent memory module firmware during runtime of the computing system, without a reset of the computing system and without quiesce of access to persistent memory media in the persistent memory module, while continuing to perform critical event handling by the current version of persistent memory module firmware. Examples further include initializing the new version of persistent memory module firmware; and transferring processing of critical event handling from the current version of persistent memory module firmware to the new version of persistent memory module firmware when initializing the new version of persistent memory module firmware is completed. 1. A persistent memory module comprising:a random-access memory (RAM);a flash memory;a plurality of persistent memory media; and copy a new version of persistent memory module firmware from the flash memory into an available area of the RAM;', 'transfer processing of a current version of persistent memory module firmware to the new version of persistent memory module firmware during runtime of a computing system, without a reset of the computing system and without quiesce of access to the plurality of persistent memory media, while continuing to perform critical event handling by the current version of persistent memory module firmware;', 'initialize the new version of persistent memory module firmware; and', 'transfer processing of critical event handling from the current version of persistent memory module firmware to the new version of persistent memory module firmware when initializing the new version of persistent memory module firmware is ...

MEMORY COMPONENT WITH PATTERN REGISTER CIRCUITRY TO PROVIDE DATA PATTERNS FOR CALIBRATION

A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration. 1. (canceled)2. A controller to control operations of a memory component , the controller comprising: a first command that specifies a first data pattern to be stored in a first register of the memory component;', 'a second command that specifies a second data pattern to be stored in a second register of the memory component; and,', 'a third command to select one of the first data pattern or the second data pattern to be output by the memory component;, 'a first circuit to transmit commands to the memory component, the commands includinga second circuit to receive, from the memory component as a received data pattern, the one of the first data pattern or the second data pattern output by the memory component, as selected by the third command; and,calibration circuitry to based on the received data pattern, adjust a timing of a timing reference signal for sampling data at the second circuit.3. The controller of claim 2 , wherein the commands transmitted by the first circuit include a fourth command that specifies data to be accessed from a memory core of the memory component claim 2 , ...

INDIRECT USER AUTHENTICATION

As disclosed herein a method, executed by a computer, includes receiving, from a user, a request for access to a shared system, wherein the request comprises a user identifier and a user password corresponding to the user, and determining privileges corresponding to the shared system using the user identifier. The method further includes requesting, from an identity manager, a shared identifier and a shared password corresponding to the shared system, receiving, from the identity manager, the shared identifier and the shared password, and using the shared identifier and the shared password to enable the user to use the shared system. A computer system, and a computer program product corresponding to the above method are also disclosed herein. 1receiving, from one or more users, a request for access to a shared system, wherein the request comprises a shared system identifier that indicates the shared system for which access is being requested, a shared user identifier, and a user identifier and a user password corresponding to the one or more users; confirming the one or more users are included in an authorized user list, and', 'confirming the one or more users are a member of an authorized user group,, 'determining if the one or more users are authorized to access the shared system by confirming the user identifier of each of the one or more users includes at least the same level of authorization as the shared user identifier and one or more ofresponsive to determining that the one or more users are authorized to access the shared system, requesting, from an identity manager, the shared user identifier and a shared password corresponding to the shared system;receiving, from the identity manager, the shared user identifier and the shared password, and providing the shared user identifier to each of the one or more users, and automatically authenticating each of the one or more users on the shared system using the shared user identifier and the shared password;using ...

Information processing apparatus and non-transitory computer readable medium for setting function for entity in real space

An information processing apparatus includes a registration unit that registers an entity and an executable function in association with each other, the entity being an entity in real space identified by sensing, the executable function being a function executable in response to the entity being identified again.

TECHNIQUES FOR POWER MANAGEMENT USING LOOPBACK

Techniques and devices for managing power consumption of a memory system using loopback are described. When a memory system is in a first state (e.g., a deactivated state), a host device may send a signal to change one or more components of the memory system to a second state (e.g., an activated state). The signal may be received by one or more memory devices, which may activate one or more components based on the signal. The one or more memory devices may send a second signal to a power management component, such as a power management integrated circuit (PMIC), using one or more techniques. The second signal may be received by the PMIC using a conductive path running between the memory devices and the PMIC. Based on receiving the second signal or some third signal that is based on the second signal, the PMIC may enter an activated state. 1. A method , comprising:receiving, at a memory device of a memory system, a first signal from a host device to activate one or more components of the memory device;activating the one or more components of the memory device based at least in part on receiving the first signal from the host device; andsending, to a power management integrated circuit (PMIC) over a conductive path coupled with a loopback pin of the memory device, a second signal for activating one or more components of the PMIC based at least in part on activating the one or more components of the memory device.2. The method of claim 1 , further comprising:inducing a third signal on a second conductive path coupled with the PMIC based at least in part on sending the second signal using the conductive path, the third signal for activating the one or more components of the PMIC.3. The method of claim 2 , further comprising:toggling the second signal sent over the conductive path between different voltage levels, wherein inducing the third signal on the second conductive path is based at least in part on toggling the second signal.4. The method of claim 1 , further ...

Memory system that utilizes a wide input/output (i/o) interface to interface memory storage with an interposer

A memory system is provided in which at least one memory chip and a memory controller chip are mounted in a side-by-side relationship on an interposer. The memory chip is connected to the interposer via a Wide I/O interface to enable the memory chip and the memory controller chip to communicate with each other via the Wide I/O interface. The memory controller chip has an interface for communicating with an interface of an integrated circuit (IC) chip of the memory system.

CACHING AND TIERING FOR CLOUD STORAGE

Various systems and methods for caching and tiering in cloud storage are described herein. A system for managing storage allocation comprises a storage device management system to maintain an access history of a plurality of storage blocks of solid state drives (SSDs) managed by the storage device management system; and automatically configure each of a plurality of storage blocks to operate in cache mode or tier mode, wherein a ratio of storage blocks operating in cache mode and storage blocks operating in tier mode is based on the access history. 120-. (canceled)21. A system for managing storage allocation , the system comprising: manage a plurality of storage pools, each of the plurality of storage pools including a plurality of storage devices arranged in a tiered structure with solid state drives (SSDs) in a performance tier, and where the SSDs from one storage pool of the plurality of storage pools is not shared with storage devices of another storage pool of the plurality of storage pools;', 'maintain an access history and access consistency of each of a plurality of storage blocks of SSDs managed by the storage device management system; and', 'automatically configure each of a plurality of storage blocks to operate in cache mode or tier mode, wherein a ratio of storage blocks operating in cache mode and storage blocks operating in tier mode is based on the access history;, 'a storage device management system to configure storage blocks with a relatively high average access frequency and a relatively high access consistency to operate in tier mode; and', 'configure storage blocks with a relatively low average access frequency and a relatively low access consistency to operate in cache mode., 'wherein to automatically configure each of the plurality of storage blocks, the storage device management system is to22. The system of claim 21 , wherein the storage device management system is incorporated into a device in a peer-to-peer network.23. The system of claim ...

Accelerator control apparatus, accelerator control method, and program

An accelerator control apparatus includes: a task storage part which holds an executable task(s); a data scheduler which selects a task needing a relatively small input/output data amount on a memory included in an accelerator when the task is executed by the accelerator from the executable task(s) and instructs the accelerator to prepare for data I/O on the memory for the selected task; and a task scheduler which instructs the accelerator to execute the selected task and adds a task that becomes executable upon completion of the selected task to the task storage part, wherein the data scheduler continues, depending on a use status of the memory, selection of a next task from the executable task(s) held in the task storage part and preparation of data I/O for the next task selected.

Managing Data in a Storage System

Various aspects for managing data blocks in a storage system are provided. For instance, a method may include storing, in a buffer memory, a plurality of comparison blocks, initiating a data deduplication process utilizing the plurality of comparison blocks, and performing garbage collection in conjunction with the data deduplication process. Garbage collection may include maintaining a hit count for comparison blocks of a passive set of comparison blocks in the buffer memory and deleting the passive set from the buffer memory when the hit count is decremented to a predetermined value. The hit count may be incremented and decremented based on utilization of a comparison block in the data deduplication process. 1. A non-volatile memory system , comprising:a non-volatile cache memory device including a buffer memory storing a plurality of comparison blocks; and initializing a data deduplication process utilizing the plurality of comparison blocks stored in the non-volatile cache memory device, and', maintaining a hit count for comparison blocks of a passive set of comparison blocks in the buffer memory by incrementing or decrementing the hit count based on utilization of a comparison block in the data deduplication process, and', 'deleting the passive set from the buffer memory responsive to the hit count satisfying a predetermined value., 'performing garbage collection in conjunction with the data deduplication process, the garbage collection comprising], 'a storage controller coupled to the non-volatile cache memory device, the storage controller including one or more processors that execute instructions in one or more programs, causing the storage controller to perform operations comprising2. The non-volatile memory system of claim 1 , wherein the garbage collection further comprises:deleting a comparison block with a zero hit count from the passive set prior to deletion of the passive set.3. The non-volatile memory system of claim 2 , wherein the garbage ...

Method, apparatus and computer program product for managing address in storage system

Techniques manage addresses in a storage system. In such techniques, an address page of an address pointing to target data in the storage system is determined in response to receiving an access request for accessing data in the storage system. A transaction for managing the address page is generated on the basis of the address page, here the transaction at least comprises an indicator of the address page and a state of the transaction. A counter describing how many times the address page is referenced is set. The transaction is executed at a control node of the storage system on the basis of the counter. With such techniques, the access speed for addresses in the storage system can be accelerated, and then the overall response speed of the storage system can be increased.

MEMORY SYSTEM CONNECTOR

According to one embodiment a memory system includes a circuit card and a separable area array connector on the circuit card. The system also includes a memory device positioned on the circuit card, wherein the memory device is configured to communicate with a main processor of a computer system via the area array connector. 1. A memory system comprising:a circuit card;a separable area array connector on the circuit card; anda memory device positioned on the circuit card, wherein the memory device is configured to communicate with a main processor of a computer system via the area array connector.2. The memory system of claim 1 , further comprising a power conversion device on the circuit card.3. The memory system of claim 2 , wherein the power conversion device on the circuit card is configured to receive a single voltage via the separable area array connector and provide a plurality of voltage levels for use by the memory device.4. The memory system of claim 1 , wherein the separable area array connector comprises a land grid array connector.5. The memory system of claim 1 , wherein the separable area array connector connects to a plurality of processor sockets on a main circuit board.6. The memory system of claim 1 , comprising a hub chip coupled to the memory device and configured to control the memory device.7. The memory system of claim 1 , wherein the memory device comprises buffered memory stacks.8. The memory system of claim 7 , further comprising hub chips claim 7 , wherein each hub chip is located on each of the buffered memory stacks claim 7 , wherein each hub chip is configured to control the respective buffered memory stack.9. The memory system of claim 1 , wherein the memory device comprises at least one of: phase change memory claim 1 , active buffered memory and hybrid memory.10. The memory system of claim 1 , further comprising a cooling device coupled to the circuit card.11. The memory system of claim 1 , further comprising channels to couple the ...

Techniques for Identifying Read/Write Access Collisions for a Storage Medium

Examples are disclosed for identifying read/write access collisions for a storage medium. In some examples, a plurality of write access requests for access to a storage medium may be received at a controller for a storage medium. The plurality of write access requests may be associated with separate logical block address (LBA) ranges. The separate write LBA ranges may be stored to sets of first registers. A read access request to the storage medium may also be received and a read LBA range associated with the read access request may be stored to a set of second registers. The separate stored write LBA ranges may then be compared to the read LBA range to identify overlapping ranges that may indicate read/write access collisions to the storage medium. Other examples are described and claimed.

STORAGE DEVICE, STORAGE SYSTEM, AND STORAGE CONTROL METHOD

A storage device includes a first memory having a first access speed, a second memory having a second access speed slower than the first access speed, and a processor coupled to the first memory and the second memory and configured to copy one or a plurality of first data blocks included in a plurality of data blocks stored in the first memory, to the second memory, determine whether a processing amount per unit of time in the first memory reaches a threshold value based on a limit value of the processing amount when the processor receives a read request of a second data block included in the first data blocks, and read the second data block from the first memory when the processing amount does not reach the threshold value, and read the second data block from the second memory when the processing amount reaches the threshold value. 1. A storage device comprising:a first memory having a first access speed, configured to store a plurality of data blocks;a second memory having a second access speed slower than the first access speed; anda processor coupled to the first memory and the second memory and configured to:copy one or a plurality of first data blocks included in the plurality of data blocks stored in the first memory, to the second memory,determine whether a processing amount per unit of time in the first memory reaches a threshold value based on a limit value of the processing amount when the processor receives a read request of a second data block included in the first data blocks, andread the second data block from the first memory when the processing amount does not reach the threshold value, and read the second data block from the second memory when the processing amount reaches the threshold value.2. The storage device according to claim 1 , whereinthe plurality of data blocks are data blocks each having a high access frequency among a plurality of third data blocks included in a logical memory area, andthe processor stores data blocks each having a low ...

MULTI-PROTOCOL STORAGE CONTROLLER

Systems and methods presented herein provide for coupling a storage controller to a plurality of different storage device types. One embodiment of the storage controller includes an interface operable to communicatively couple to a storage device. The storage controller also includes a processor operable to select between hardware protocol detection of the storage device and firmware protocol detection of the storage device, and to detect a protocol of the storage device when the storage device communicatively couples to the interface according to the selected protocol detection. The storage controller then selects a protocol to process input/output requests from a host based on the detected protocol of the storage device. 1. A storage controller , comprising:an interface operable to communicatively couple to a storage device;a processor operable to select between hardware protocol detection of the storage device and firmware protocol detection of the storage device, to detect a protocol of the storage device when the storage device communicatively couples to the interface according to the selected protocol detection, and to select a protocol to process input/output requests from a host based on the detected protocol of the storage device; anda hardware detector that is operable to perform the hardware protocol detection by measuring a time domain reflectometry signal.2. The storage controller of claim 1 , wherein:the processor is further operable to perform a Serial Attached Small Computer System Interface protocol detection and a Peripheral Component Interconnect Express protocol detection at substantially the same time.3. (canceled)4. The storage controller claim 1 , wherein:the hardware detector is further operable to determine that the storage device is disconnected from the interface based on the time domain reflectometry signal.5. The storage controller claim 1 , wherein:the processor is further operable to sample the time domain reflectometry signal, to ...

Dynamic priority control based on latency tolerance

A dynamic priority controller monitors a level of data in a display engine buffer and compares the level of data in the display engine buffer to a plurality of thresholds including a first threshold and a second threshold. When the level of data in the display engine buffer is less than or equal to the first threshold, the dynamic priority controller increases a priority for processing display engine data in a communication channel. When the level of data in the display engine buffer is greater than or equal to the second threshold, the dynamic priority controller decreases the priority for processing the display engine data in the communication channel.

APPARATUS, METHOD AND ARTICLE FOR REDISTRIBUTING POWER STORAGE DEVICES, SUCH AS BATTERIES, BETWEEN COLLECTION, CHARGING AND DISTRIBUTION MACHINES

A network of collection, charging and distribution machines collect, charge and distribute portable electrical energy storage devices. To charge, the machines employ electrical current from an external source. As demand at individual collection, charging and distribution machines increases or decreases relative to other collection, charging and distribution machines, a distribution management system initiates redistribution of portable electrical energy storage devices from one collection, charging and distribution machine to another collection, charging and distribution machine in an expeditious manner. Also, redeemable incentives are offered to users to return or exchange their portable electrical energy storage devices at selected collection, charging and distribution machines within the network to effect the redistribution. 1. A method of operating a distribution management system for portable electrical energy storage devices , the method comprising:receiving, by a distribution management system for portable electrical energy storage devices, information tracking physical exchanges of portable electrical energy storage devices for charged portable electrical energy storage devices at a plurality of distribution machines for distribution of portable electrical energy storage devices;analyzing, by the distribution management system, the information tracking physical exchanges of portable electrical energy storage devices for charged portable electrical energy storage devices to determine a physical redistribution of portable electrical energy storage devices between the plurality of distribution machines; andsending, by the distribution management system, information initiating the physical redistribution of portable electrical energy storage devices between the plurality of distribution machines.2. The method of wherein the sending the information includes causing a message to be sent claim 1 , the message including information identifying a selected one or more ...

Command and data selection in storage controller systems

A storage controller system may include a host controller that queues host commands as data transfer commands in a plurality of queue channels. The storage controller system may also include a data storage controller that selects data transfer commands for execution. The data storage controller may select all data transfer commands associated with a host command when all of the data transfer commands are located at heads of the queue channels. Alternatively, the data storage controller may select for execution data transfer commands at heads of the queue channels when associated cache areas are available to receive data, regardless of whether all of the data transfer commands associated with a host command are at the heads. The host controller may then retrieve the data in the cache areas when all of the data to be sent to the host in response to the host command is being cached.

SPACE EFFICIENT CASCADING POINT IN TIME COPYING

Embodiments for space-efficient cascading point-in-time copying of source data by creating a plurality of cascading point-in-time target copies, the target copies being created at different points in time, are provided. Data is physically copied form the source to a repository to create a physical copy, and a data mapping is created that associates the physical copy with a most recent target copy. 1. A computer implemented method for space efficient cascading point-in-time copying of source data by mapping a plurality of cascading point-in-time target copies , the target copies being created at different points in time , the method comprising:physically copying data from the source data to a repository to create a physical copy; andcreating a data mapping that associates the physical copy with a most recent target copy of said plurality of cascading target point-in-time copies, the data mapping indicating shared mapping and non-shared mapping, the shared mapping indicating that an address of the physical copy in the repository is shared with at least one previously created target copy;wherein the data mapping comprises a leaf of a B-tree structure, and the B-tree structure includes inner nodes and one or more leaves, the inner nodes include information for assisting in searching the B-tree and the one or more leaves indicate the shared mapping and the non-shared mapping.2. The computer implemented method of claim 1 , further including updating the data mapping of one or more target copies of said plurality of cascading target point-in-time copies that are older than a designated target copy of said plurality of cascading target point-in-time copies claim 1 , so as to include information relating to the designated target copy.3. The computer implemented method of claim 1 , further including deleting or modifying the designated target copy.4. The computer implemented method of claim 1 , wherein the data mapping includes an indication of whether the physical copy ...

SYSTEMS AND METHODS FOR MINIMIZING COMMUNICATIONS

A system for allocation of one or more data structures used in a program across a number of processing units takes into account a memory access pattern of the data structure, and the amount of total memory available for duplication across the several processing units. Using these parameters duplication factors are determined for the one or more data structures such that the cost of remote communication is minimized when the data structures are duplicated according to the respective duplication factors while allowing parallel execution of the program. 1. A system for allocating data structures to a plurality of processing nodes , each processing node having a respective local memory , the system comprising:a first processor; anda first memory in electrical communication with the first processor, the first memory comprising instructions which, when executed by a processing unit comprising at least one of the first processor and a second processor, and in electronic communication with a memory module comprising at least one of the first memory and a second memory, program the processing unit to:(a1) select as a first data structure, a data structure having a read-write ratio greater than a read-write threshold;(b1) compute a first duplication factor for the first data structure; and(c1) generate a first statement allocating the first data structure duplicated by the first duplication factor, across the plurality of processing nodes.2. The system of claim 1 , wherein the processing unit is programmed to compute the first duplication factor based on claim 1 , at least in part claim 1 , at least one of: (i) a number of the plurality of processing nodes claim 1 , (ii) the read-write ratio of the first data structure claim 1 , (iii) a first value of total available memory size of the plurality of processing nodes claim 1 , and (iv) a size of the first data structure.3. The system of claim 2 , wherein the processing unit is further programmed to compute the first value of ...

Method and apparatus for efficient processing of disparate data storage commands

A method for improving I/O performance by a storage controller is provided. The method includes receiving a command completion from a storage device and checking for a command stored in a command queue for more than a predetermined time period. If a command has been in the command queue for more than the predetermined time period, then issuing the command and removing the command from the command queue. If no commands have been stored in the command queue for more than the predetermined time period, then determining if there are any uncompleted commands previously issued to the storage device. If there are not any uncompleted commands previously issued to the storage device, then processing a next command in the command queue and removing the next command from the command queue.

Memory command scheduler and memory command scheduling method

A memory command scheduler is provided. The memory command scheduler includes a scheduler queue receiving first and second requests for a memory access from external devices and storing the first and second requests therein; and a controller generating a command of the second request after a preset number of clock cycles from a current clock cycle and transferring the generated command to a memory, if generation of a command of the first request is possible in the current clock cycle and generation of the command of the second request is possible after the preset number of clock cycles from the current clock cycle.

Dynamic Address Negotiation for Shared Memory Regions in Heterogeneous Muliprocessor Systems

Mobile computing devices may be configured to compile and execute portions of a general purpose software application in an auxiliary processor (e.g., a DSP) of a multiprocessor system by reading and writing information to a shared memory. A first process (P1) on the applications processor may request address negotiation with a second process (P2) on the auxiliary processor, obtain a first address map from a first operating system, and send the first address map to the auxiliary processor. The second process (P2) may receive the first address map, obtain a second address map from a second operating system, identify matching addresses in the first and second address maps, store the matching addresses as common virtual addresses, and send the common virtual addresses back to the applications processor. The first and second processes (i.e., P1 and P2) may each use the common virtual addresses to map physical pages to the memory.

COMPUTER SYSTEM HAVING MAIN MEMORY AND CONTROL METHOD THEREOF

Provided are a computer system and a method of controlling the same. The computer system includes: a central processing unit (CPU) configured to drive an application program; and a main memory configured to provide the CPU with a memory space for driving of the application program and to store a processing result of the CPU. The main memory includes: a nonvolatile memory including a first memory area configured to store data and a second memory area configured to store address information of the data; a memory controller configured to control the nonvolatile memory; and a memory manager configured to read the address information from the second memory area and delete the data stored at the first area according to the read address information, in response to a data delete command from the CPU and a control of the memory controller. 1. A computer system comprising:a central processing unit (CPU) configured to drive an application program; anda main memory configured to provide the CPU with a memory space for driving of the application program and to store a processing result of the CPU, a nonvolatile memory including a first memory area configured to store data and a second memory area configured to store address information of the stored data;', 'a memory controller configured to control the nonvolatile memory; and', 'a memory manager configured to read the address information from the second memory area and to delete the data stored at the first area according to the read address information, in response to a data delete command from the CPU and a control of the memory controller., 'wherein the main memory comprises2. The computer system of claim 1 , wherein the nonvolatile memory is a spin transfer torque magneto resistive random access memory (STT-MRAM) claim 1 , a phase change random access memory (PRAM) claim 1 , or a resistive random access memory (RRAM).3. The computer system of claim 1 , wherein the memory manager is embedded in the memory controller.4. The ...

NUMA Scheduling Using Inter-vCPU Memory Access Estimation

In a system having non-uniform memory access architecture, with a plurality of nodes, memory access by entities such as virtual CPUs is estimated by invalidating a selected sub-set of memory units, and then detecting and compiling access statistics, for example by counting the page faults that arise when any virtual CPU accesses an invalidated memory unit. The entities, or pairs of entities, may then be migrated or otherwise co-located on the node for which they have greatest memory locality. 1. A method for managing memory in a system , said system including a plurality of software entities that each access the memory and having a non-uniform memory access architecture (NUMA) with a plurality of nodes , the method comprising:selecting a sample set of memory units;invalidating the sample set of memory units and detecting accesses by any of the software entities to the invalidated memory units;computing a metric as a function of a proportion of accessed memory units relative to the sample set of memory units; andassociating at least one of the software entities with one of the nodes based at least in part on the corresponding metric so as to increase memory locality of the associated software entity.2. The method of claim 1 , in which the software entities are virtual CPUs of virtual machines claim 1 , the method further comprising:invalidating the sample set of memory units by invalidating the sample set in a translation look-aside buffer and memory management unit associated with each respective virtual machine;detecting accesses to the invalidated memory units by sensing page faults; andmigrating the virtual machines between nodes according to their respective metrics.3. The method of claim 2 , further comprising periodically re-invalidating the sample set of memory units for each of a plurality of sample periods and claim 2 , for each virtual CPU claim 2 , compiling per-virtual CPU access statistics as the metrics for each sample period.4. The method of claim 3 , ...

ELECTRICAL DISTANCE-BASED REMAPPING IN A MEMORY DEVICE

Memory device systems and methods for using methods include multiple access lines arranged in a grid. Multiple memory cells are located at intersections of the access lines in the grid. Multiple drivers are included with each configured to transmit a corresponding signal to respective memory cells of the multiple memory cells. Remapping circuitry is configured to remap a near memory cell of the multiple memory cells to a far memory cell of the multiple memory cells. The near memory cell is relatively nearer to a respective driver of the multiple drivers than the far memory cell is to a respective driver of the multiple drivers.

STORAGE SYSTEM AND MANAGEMENT METHOD THEREOF

A storage system capable of executing a managing operation based on timestamp and a management method are disclosed. The storage system includes a control unit and a memory unit connected to the control unit. The management method includes steps of: (a) issuing a control instruction comprising a timestamp to the control unit, wherein when the control unit receives the control instruction, the control unit starts to control the memory unit and accesses at least one storage space from the memory unit; and (b) sequentially counting plural numbers of instruction operations in plural time intervals, wherein the plural numbers of the instruction operations in each of the plural time intervals are stored in the at least one storage space. Since the peak period and the off-peak period of the storage system can be counted based on the timestamp, it facilitates the storage system to set a triggering time to execute a background operation. 1. A storage system comprising:a memory unit comprising at least one storage space; anda control unit connected with the memory unit, wherein when the control unit receives a control instruction, the control unit starts to control the memory unit and accesses the at least one storage space of the memory unit, wherein the control instruction comprises a timestamp, the control unit sequentially counts plural numbers of instruction operations in each of plural time intervals according to the timestamp, and stores the plural numbers of the instruction operations in the plural time intervals into the at least one storage space.2. The storage system according to claim 1 , further comprising an application program module connected with the control unit to issue the control instruction to the control unit.3. The storage system according to claim 2 , wherein at least one off-peak period is selected from the plural time intervals through the control unit according to the plural numbers of the instruction operations in each of the plural time intervals ...

Apparatus for Data Processing, Artificial Intelligence Chip and Electronic Device

Disclosed are an apparatus for data processing, an artificial intelligence chip, and an electronic device. The apparatus for data processing includes: at least one input memory, at least one data conveying component, at least one multiplexed arbitration component, and at least one output memory. The input memory is connected to the data conveying component, the data conveying component is connected to the multiplexed arbitration component, and the multiplexed arbitration component is connected to the output memory.

Accelerating and atomically moving files in an overlay optimizer

An overlay optimizer can be configured to accelerate the moving of files from an overlay and to atomically move files from the overlay. To accelerate the moving of files from the overlay, the overlay optimizer can continuously monitor the consumption of the overlay. If the consumption exceeds an optimized threshold, the overlay optimizer can cause the file system cache to be invalidated to thereby release handles to any closed files that are still cached. To move files atomically from the overlay, the overlay optimizer can be configured to handle attempts to open a file by determining whether the file is in the process of being moved from the overlay. If so, the overlay optimizer can detect which stage the move process has reached and can dynamically adapt the move process to enable the attempt to open the file to be completed successfully and in a consistent manner.

SYSTEM AND METHOD FOR HYBRID DATA RELIABILITY FOR OBJECT STORAGE DEVICES

Provided is a method of storing data in a key-value reliability system including N storage devices that are grouped into a reliability group as a single logical unit and that are managed by a virtual device management layer, N being an integer, the method including determining whether the data meets a threshold corresponding to a reliability mechanism for storing the data, selecting the reliability mechanism when the threshold is met, and storing the data according to the selected reliability mechanism. 1. A method of storing data in a key-value reliability system comprising N storage devices that are grouped into a reliability group as a single logical unit and that are managed by a virtual device management layer , N being an integer , the method comprising:determining whether the data meets a threshold corresponding to a reliability mechanism for storing the data;selecting the reliability mechanism when the threshold is met; andstoring the data according to the selected reliability mechanism.2. The method of claim 1 , wherein the threshold is based on one or more of:object size of the data;throughput consideration of the data;read/write temperature of the data; andunderlying erasure coding capabilities of the N storage devices.3. The method of claim 1 , further comprising using one or more bloom filters or caches for testing the data for the reliability mechanism.4. The method of claim 1 , further comprising inserting metadata with a key corresponding to the data for recording the selected reliability mechanism claim 1 , one or more checksums for each of the N storage devices storing the data claim 1 , object sizes of the values of the data stored in each of the N storage devices storing the data claim 1 , and a location of parity group members of the N storage devices for indicating which of the N storage devices are storing the data.5. The method of claim 1 , wherein the selected reliability mechanism comprises object replication claim 1 , and wherein storing ...

DATA DEDUPLICATION IN AN INTERNET SMALL COMPUTER SYSTEM INTERFACE (iSCSI) ATTACHED STORAGE SYSTEM

Embodiments of the present invention disclose a method, computer program product, and system for data deduplication. Receiving a protocol data unit (PDU) that includes data to be stored on a system and a hash value that corresponds to the data. Determining whether the hash value of the received PDU matches a stored hash value that corresponds to data that is stored in the system. Responsive to determining that the hash value of the received PDU does not match a stored hash value, storing the data included in the received PDU in the system. In another embodiment, the system is an iSCSI attached storage system, and the PDU is an iSCSI PDU. 1. A method for data deduplication , the method comprising:receiving a protocol data unit (PDU) that includes data to be stored on a system and a hash value that corresponds to the data;determining whether the hash value of the received PDU matches a stored hash value that corresponds to data stored in the system; andresponsive to determining that the hash value of the received PDU does not match a stored hash value, storing the data included in the received PDU in the system.2. The method of claim 1 , further comprising:storing the hash value of the received PDU and an associated reference to a storage location on the system at which the data included in the received PDU is stored;wherein the system is an iSCSI attached storage system, and the received PDU is an iSCSI PDU.3. The method of claim 1 , further comprising:responsive to determining that the hash value of the received PDU does match a stored hash value, identifying a storage location on the system of the data corresponding to the matching hash value; andstoring a reference to the identified storage location, wherein the reference to the identified storage location directs requests to access the data included in the received PDU to the storage location of the data corresponding to the determined matching hash value.4. The method of claim 1 , further comprising:responsive ...

SEMICONDUCTOR CHIPS, SEMICONDUCTOR CHIP PACKAGES INCLUDING THE SAME, AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME

Semiconductor chips are provided. The semiconductor chip includes a first data pad, a first data strobe pad and a second data pad sequentially arrayed from a command address pad in a first direction. In addition, the semiconductor chip includes a third data pad, a second data strobe pad and a fourth data pad sequentially arrayed from the command address pad in a second direction. Data are inputted and outputted through the first and fourth data pads or through the second and third data pads in a predetermined bit organization. Related semiconductor chip packages and semiconductor systems are also provided. 1. A semiconductor chip comprising:a first data pad, a first data strobe pad and a second data pad sequentially arrayed from a command address pad in a first direction; anda third data pad, a second data strobe pad and a fourth data pad sequentially arrayed from the command address pad in a second direction,wherein data are inputted and outputted through the first and fourth data pads or through the second and third data pads in a predetermined bit organization.2. The semiconductor chip of claim 1 , wherein the first direction and the second direction are opposite to each other.3. The semiconductor chip of claim 1 , further comprising a first input capacitor unit including a first capacitor claim 1 ,wherein the first input capacitor unit is suitable for electrically disconnecting the first data strobe pad from the first capacitor in the predetermined bit organization.4. The semiconductor chip of claim 1 , further comprising a second input capacitor unit including a second capacitor claim 1 ,wherein the second input capacitor unit is suitable for electrically disconnecting the second data strobe pad from the second capacitor in the predetermined bit organization.5. A semiconductor chip package comprising:a first data pad, a first data strobe pad and a second data pad sequentially arrayed from a first command address pad in a first direction; anda third data pad, a ...

INTERMITTENT SAMPLING OF STORAGE ACCESS FREQUENCY

The intermittent sampling of storage access frequency is performed by determining a duration of a collection window and a duration of an observation window within the collection window. A position of the observation window within the collection window is randomly selected, and frequencies of accesses of one or more storage objects during the observation window are observed. When a new access of a given storage object occurs, a delta time for the given storage object is calculated as the time of the observed access minus the timestamp of the most recent observed prior access of the given storage object. Optionally, the delta time of two sequential accesses of a given storage object in two different observation windows may be calculated as if the two different observation windows are immediately adjacent to each other. 17-. (canceled)8. A computer program product for intermittent sampling of storage access frequency , the computer program product comprising:a computer readable storage medium having computer readable program code embodied therewith, the program code executable by a processor to:determine a duration of a collection window;determine a duration of an observation window within the collection window;randomly select a position of the observation window within the collection window; andobserve frequencies of accesses of one or more storage objects during the observation window.9. The computer program product of claim 8 , wherein the program code executable by the processor to observe the frequencies of the accesses of the one or more storage objects is further executable by the processor to:determine that a new access of a given storage object occurs; andin response to determining that the new access of the given storage object occurs, calculate a delta time for the given storage object as a time of the new access minus a timestamp of a most recent observed prior access of the given storage object.10. The computer program product of claim 9 , wherein the ...

CONTROLLER, MEMORY SYSTEM, AND METHOD

According to the embodiments, a controller includes an arbiter, a command fetch unit, and a processing unit. The arbiter executes a retrieval process. The retrieval process is a process of selecting a queue, to which a command is issued, out of plural queues by retrieval according to a round robin method. The command fetch unit fetches a command from the selected queue. The processing unit executes a process according to the fetched command to a memory chip. The arbiter manages a retrieval position. When a new command is issued to any one of the plural queues in an empty state in which there is no queue to which a command is issued, the arbiter has the retrieval position jump to the queue to which the new command is issued. 1. A controller comprising:an arbiter that executes a retrieval process of selecting a queue to which a command is issued out of a plurality of queues by a retrieval according to a round robin method;a command fetch unit that fetches a command from the selected queue; anda processing unit that executes a process according to the fetched command to a memory chip, whereinthe arbiter manages a retrieval position, and when a new command is issued to any one of the plurality of queues in an empty state in which there is no queue to which a command is issued, the arbiter has the retrieval position jump to the queue to which the new command is issued.2. The controller according to claim 1 , whereinthe plurality of queues are grouped into a plurality of groups for each priority, andthe arbiter manages the retrieval position for each group, sets each of the plurality of groups, one by one, as a target to be retrieved according to the round robin method, and executes the retrieval process within a range of the queues belonging to the group that is the target to be retrieved.3. The controller according to claim 2 , whereinat least one of the plurality of groups has a priority “Urgent” set thereto, andthe arbiter executes the retrieval process in accordance ...

METHOD AND DEVICE FOR DATA PROCESSING

The present provides a method for operating a module by a processor. The method includes generating, by at least one task being executed on the processor, control information for controlling operation of the module. The module includes an arrangement of a plurality of cells, including a bus system. At least some of the cells having arithmetic and logic units. At least some of the cells being arranged in at least two dimensions. The method further including writing, by the processor, the control information into a memory being shared with the module in a list-like manner to form a list of operations. The method further including executing, by the module, the operations listed in the list. 1. A method for operating a module by a processor , the method comprising: by at least one task being executed on the processor,', having', 'arithmetic and logic units;', 'and being arranged in at least two dimensions;, 'and at least some of the cells'}, 'control information for controlling operation of the module having an arrangement of a plurality of cells, including a bus system;'}], 'generating,'} by the processor,', 'the control information', 'being shared with the module', 'into a memory'}, 'in a list-like manner', 'to form a list of operations; and, 'writing,'} by the module,', 'the operations listed in the list., 'executing'}2. The method of claim 1 , wherein the control information is preloaded into the memory for subsequent processing by the module.3. The method according to any one of and claim 1 , wherein a control unit assigned to the module receives one or more commands of the control information from the memory.4. The method of claim 3 , wherein the control unit decodes at least one command and instructs at least the function of at least one cell based on the at least one decoded command.5. The method of claim 4 , wherein the memory forms a ring buffer.6. The method of claim 5 , wherein the control information in the memory is interlinked by pointers to form the list ...

DYNAMIC MEMORY POWER CAPPING WITH CRITICALITY AWARENESS

Systems, apparatuses, and methods for reducing memory power consumption without substantial performance impact by selectively delaying non-critical memory requests are disclosed. A system management unit transfers an amount of power allocated from a memory subsystem to other component(s) responsive to detecting a first condition. In one embodiment, the first condition is detecting one or more processors having tasks to execute. In response to the system management unit transferring the amount of power from the memory subsystem to one or more processors, a memory controller delays non-critical memory requests while performing critical memory requests to memory. 1. A system comprising:one or more processors;a memory subsystem comprising a memory and a memory controller; anda system management unit configured to transfer a portion of a power budget from the memory subsystem to the one or more processors responsive to detecting a first condition;wherein the memory controller is configured to delay non-critical memory requests while performing critical memory requests to the memory, responsive to detecting said transfer.2. The system as recited in claim 1 , wherein the first condition comprises the one or more processors having tasks to execute.3. The system as recited in claim 2 , wherein the first condition further comprises a number of critical memory requests stored in a pending request queue of the memory controller is below a first threshold.4. The system as recited in claim 3 , wherein a request that has at least a given number of dependent instructions;', 'a request that corresponds to a previous request that caused a stall of at least a given number of cycles;', 'a request issued by a thread that holds a lock;', 'a request issued by a previous thread that has not yet reached a synchronization point; and', 'a request otherwise deemed likely to reduce performance if delayed; and, 'a critical memory request is one ofa non-critical memory request is a request not ...

SCALABLE ARCHITECTURE ENABLING LARGE MEMORY SYSTEM FOR IN-MEMORY COMPUTATIONS

A memory system provides deduplication of user data in the physical memory space of the system for user data that is duplicated in the virtual memory space of a host system. A transaction manager (TM) uses a transaction table to maintain data coherency and data concurrency for the virtual memory space. A write data engine manager (WDEM) uses an outstanding bucket number and command queues to maintain data coherency and data concurrency for the physical memory space. The WDEM receives data write requests from the TM and sends a corresponding write command to a selected command queue. A write data engine responds to a write command in a command queue by storing the data in an overflow memory region if the data is not duplicated in the virtual memory space, or by incrementing a reference counter for the data if the data is duplicated in the virtual memory space. 1. A memory system , comprising: a physical memory having a physical memory space of a first predetermined size;', 'at least one transaction manager (TM) that receives data write requests and corresponding data from a host system, the at least one TM using a transaction table to maintain data coherency and data consistency for a virtual memory space of the host system;', 'at least one write data engine manager (WDEM) comprising at least one command queue, the WDEM using an outstanding bucket number (OBN) and command queues to maintain data coherency and data consistency for the physical memory space, the WDEM receiving the data write requests from the TM and sending a write command corresponding to each data write request to a selected command queue of the at least one command queue; and', 'a write data engine (WDE) corresponding to each command queue, the WDE responding to a write command stored in the command queue corresponding to the WDE by storing the data corresponding to a data write request in an overflow memory region if the data is not duplicated in the virtual memory space, or incrementing a ...

THIN PROVISIONING STORAGE DEVICES IN CONNECTION WITH SECURE DELETE OPERATIONS

A method for improving thin provisioning storage devices in connection with secure delete operations is provided. The method may include receiving at a physical storage device a first indicator to initiate writing a secure delete pattern to a plurality of physical storage locations. The secure delete pattern is written to a plurality of allocated physical storage locations based on the received first indicator. When a second indicator is set, the end of the secure delete pattern is reached. The thin provisioning storage device, upon receiving the second indicator, securely erases the plurality of storage device metadata regions where the mapping of virtual storage locations to allocated physical storage locations is stored. Requests to write a secure delete pattern for virtual storage locations without corresponding allocated physical storage locations are ignored. 1. A method for improving thin provisioning storage devices in connection with secure delete operations , comprising:receiving at a physical storage device a first indicator to write a secure delete pattern to a plurality of physical storage locations;writing the secure delete pattern to a plurality of allocated physical storage locations based on the received first indicator; anderasing a plurality of storage device metadata regions based on a second indicator, wherein the metadata regions map the plurality of allocated physical storage locations to a plurality of virtual storage locations.2. The method of claim 1 , wherein writing the secure delete pattern further comprises:searching the plurality of virtual storage locations for the corresponding physical storage locations, wherein the physical storage locations are allocated; andwriting the secure delete pattern to the physical storage locations based on the physical storage locations being allocated.3. The method of claim 1 , wherein the first indicator includes one or more of:a field in a control block; or a protocol command in a separate protocol ...

ELECTRONIC STORAGE MODULE, METHOD FOR ASSIGNING CONTACTS OF AN ELECTRONIC STORAGE MODULE, METHOD FOR IMPLEMENTING AN ASSIGNMENT

Provided are an electronic storage module, a method for assigning contacts of an electronic storage module and a method for implementing an assignment. Exemplary modules include chip cards such as SIM cards (Subscriber Identification Modules), in particular but not limited to cards that use six contacts. The electronic storage module has a plurality of contacts, including at least one reset contact and at least one first set of contacts forming a first communication interface between the electronic storage module and an electronic device including the electronic storage module. The set of contacts constitutes at least one second communication interface. The reset contact makes it possible to indicate which one of the first or second communication interfaces the first set of contacts uses at a given time. 1. An electronic storage module comprising:a plurality of contacts, including at least one reinitialization contact, and at least one first set of contacts constituting a first communication interface between the electronic storage module and an electronic device having said electronic storage module and wherein said first set of contacts constitutes at least one second communication interface, the reinitialization contact allowing indication of which of the first and second communication interfaces said first set of contacts implements at a given instant.2. The electronic storage module as claimed in claim 1 , wherein said reinitialization contact triggers reinitialization of content of the electronic storage module upon a change of state of said reinitialization contact.3. The electronic storage module as claimed in claim 1 , wherein said reinitialization contact triggers the-implementation of a communication interface predetermined by said first set of contacts as a function of a state of said reinitialization contact.4. The electronic storage module as claimed in claim 1 , wherein said electronic storage module has at least one second set of contacts ...

Media content caching

A playback device includes tangible storage configured to receive transfer of media content from a remote communications device to the playback device while the remote communications device is operating in a high power mode. Interface logic is coupled to the tangible storage and configured to signal the remote communications device during the transfer to prepare the remote communications device to enter a low power mode after the transfer is complete. The remote communications device includes a content manager configured to transfer of media content from the remote communications device to a playback device while the remote communications device is operating in a high power mode. Power logic is coupled to the content manager and configured to prepare the remote communications device to enter a low power mode after the transfer is complete, responsive to receipt of a signal from the playback device during the transfer is complete.

ADMINISTERING INTER-CORE COMMUNICATION VIA SHARED MEMORY

Administering inter-core communication via shared memory may be carried out in a system in which each core is associated with a mailbox in a shared memory region. Such administration may include constructing a mailbox latency table describing latency of writing data from each core to each mailbox; constructing a locking latency table describing latency of each core in acquiring a lock for each of the mailboxes; identifying, from the tables, groups of a cores having mailbox and locking latency within a predefined range of acceptable latency values; and for each identified group of cores, establishing, for every pair of cores in the group of cores, a private channel, including pinning, for each private channel established for a pair of cores, one local memory segment per core. 1. A method of administering inter-core communication via shared memory , wherein each core is associated with a mailbox in a shared memory region , the method comprising:constructing a mailbox latency table describing latency of writing data from each core to each mailbox;constructing a locking latency table describing latency of each core in acquiring a lock for each of the mailboxes;identifying, from the tables, groups of a cores having mailbox and locking latency within a predefined range of acceptable latency values; andfor each identified group of cores:establishing, for every pair of cores in the group of cores, a private channel, including pinning, for each private channel established for a pair of cores, one local memory segment per core.2. The method of claim 1 , wherein pinning one local memory segment per core further comprises pinning the local memory segment within a predefined physical distance from the core allocating the local memory segment.3. The method of claim 1 , wherein pinning one local memory segment per core further comprises:calculating, by each core, latency of read and write transfers to all pages of shared memory; andpinning the local memory segment to one or more ...

MEMORY CONTROLLER AND OPERATING METHOD THEREOF

A memory controller is provided which includes a host interface configured to provide an interface for communication with a host; a buffer memory configured to store user data and metadata of the user data; and a DMA controller configured to access the buffer memory to check the metadata and to provide user data corresponding to a logical block address requested from a host to the host interface according to the checking result. The metadata includes status information of the user data stored at the buffer memory. Before providing the host interface with user data corresponding to a first logical block address requested from the host, the DMA controller checks metadata of user data corresponding to a second logical block address requested from the host. 1. A memory controller , comprising:a host interface configured to provide an interface for communication with a host;a buffer memory configured to store first and second user data and associated metadata, the metadata including status information of the associated one of the first and second user data; and receive a request from a host to retrieve the first user data at a first logical block address and the second user data at a second logical block address,', 'check the metadata associated with the first user data, and', 'provide the first user data to the host interface, based on a result of checking the metadata associated with the first user data, before or after simultaneously checking the metadata associated with the second user data., 'a DMA controller configured to,'}2. The memory controller of claim 1 , wherein after providing the host interface with the first user data claim 1 , the DMA controller is configured to provide the host interface with the metadata associated with the second user data.3. The memory controller of claim 1 , wherein when the checking indicates that the second user data is valid claim 1 , the DMA controller is configured to provide the second user data to the host interface.4. The ...

Method and system for managing storage space complexity in a storage unit

Disclosed herein is method and system for managing storage space complexity in a storage unit. In an embodiment, operational parameters related to memory operations and storage parameters related to memory blocks of the storage unit are analyzed to estimate storage capacity of each of the memory blocks. Subsequently, the memory blocks are clustered into plurality of clusters based on the storage capacity. Further, one or more of the plurality of clusters are selected for performing future memory operations based on ranking of the plurality of clusters. In some embodiments, the present disclosure helps in dynamically managing storage space complexity in the storage unit and optimizes the storage space utilization. Also, the present disclosure automatically handles storage volumes, thereby reducing latency in memory backup operations and reducing amount of buffer/cache memory required.

INPUT PROCESSING SYSTEM, INFORMATION STORAGE DEVICE, INFORMATION PROCESSING DEVICE, AND INPUT METHOD

According to an embodiment of the present invention, there is provided an input processing system including: an information storage device; and an information processing device, in which the information storage device includes: an input information storage unit configured to store information for performing input processing and identification information so that both of the information corresponds to each other; an identification information receiving unit configured to receive the identification information from the information processing device; an information transmitting unit configured to transmit, to the information processing device, the information for performing input processing stored to correspond to the identification information received by the identification information receiving unit; an identification information storage unit configured to store the identification information; an identification information transmitting unit configured to transmit the identification information to the information storage device; and an information receiving unit configured to receive the information for performing input processing transmitted by the information transmitting unit. 1. An input processing system comprising:an information storage device; andan information processing device, whereinthe information storage device includes:an input information storage unit configured to store information for performing input processing and identification information so that both of the information corresponds to each other;an identification information receiving unit configured to receive the identification information from the information processing device; andan information transmitting unit configured to transmit, to the information processing device, the information for performing input processing stored to correspond to the identification information received by the identification information receiving unit;the information processing device includes:an identification ...

METADATA TRACK ENTRY SORTING IN A DATA STORAGE SYSTEM

In one aspect of metadata track entry sorting in accordance with the present description, recovery logic sorts a list of metadata entries as a function of a source data track identification of each metadata entry to provide a second, sorted list of metadata entries, and generates a recovery volume which includes data tracks which are a function of one or more data target tracks identified by the sorted list of metadata entries. Because the metadata entry contents of the sorted list have been sorted as a function of source track identification number, the particular time version of a particular source track may be identified more quickly and more efficiently. As a result, recovery from data loss may be achieved more quickly and more efficiently thereby providing a significant improvement in computer technology. Other features and aspects may be realized, depending upon the particular application. 1. A computer program product for use with a data storage system having a storage controller and at least one storage unit controlled by the storage controller and configured to store data in volumes , wherein the storage controller has a processor and a cache , and wherein the computer program product comprises a computer readable storage medium having program instructions embodied therewith , the program instructions executable by a processor of the storage controller to cause storage controller processor operations , the storage controller processor operations comprising:copying a plurality of source data tracks from a source volume and storing the plurality of copied data tracks in a plurality of target data tracks of a backup volume;generating a first list of source track identification descriptor (STIDD) metadata entries for the plurality of copied source data tracks stored in the plurality of target data tracks of the backup volume, each metadata entry identifying a source data track copied from the source volume and an associated target data track of the backup ...

SEMICONDUCTOR MEMORY APPARATUS AND DATA INPUT AND OUTPUT METHOD THEREOF

A semiconductor memory apparatus includes an input data bus inversion unit, a data input line, a termination unit, a data recovery unit and a memory bank. The input data bus inversion unit determines whether or not to invert a plurality of input data based on an operation mode signal and the plurality of input data and generates a plurality of conversion data. The data input line transmits the plurality of conversion data. The termination unit terminates the data input line in response to the operation mode signal. The data recovery unit receives the plurality of conversion data and generates a plurality of storage data. The memory bank configured to store the plurality of storage data. 1. A semiconductor memory apparatus comprising:an input data bus inversion unit configured to determine whether or not to invert a plurality of input data based on an operation mode signal and the plurality of input data and to generate a plurality of conversion data;a data input line configured to transmit the plurality of conversion data;a termination unit configured to terminate the data input line in response to the operation mode signal;a data recovery unit configured to receive the plurality of conversion data and generate a plurality of storage data; anda memory bank configured to store the plurality of storage data.2. The semiconductor memory apparatus according to claim 1 , wherein the input data bus inversion unit comprises:an inversion determination unit configured to discriminate levels of the plurality of input data in response to the operation mode signal and generate an inversion signal; anda data conversion unit configured to invert or pass through the plurality of input data in response to the inversion signal and generate the plurality of conversion data.3. The semiconductor memory apparatus according to claim 2 , wherein the inversion determination unit is configured to enable the inversion signal in response to a first operation mode signal when a majority of the ...

SYSTEM AND METHOD FOR PREDICTING MEMORY PERFORMANCE

A method, computer program product, and computing system for defining an optimal execution time (t) for a concurrent memory operation to be performed on a transactional memory system. An abort probability (p) is associated with the optimal execution time (t) based, at least in part, upon a probability curve. The probability curve is empirically derived and based upon the performance of the transactional memory system. A probable execution time (T) is determined for the concurrent memory operation based, at least in part, upon the abort probability (p). 1. A computer-implemented method comprising:defining an optimal execution time (t) for a concurrent memory operation to be performed on a transactional memory system;associating an abort probability (p) with the optimal execution time (t) based, at least in part, upon a probability curve, wherein the probability curve is empirically derived and based upon the performance of the transactional memory system; and{'sub': 'tm', 'determining a probable execution time (T) for the concurrent memory operation based, at least in part, upon the abort probability (p).'}2. The computer-implemented method of further comprising:defining a concurrency level (c) for the transactional memory system.3. The computer-implemented method of further comprising:{'sub': 'cs', 'claim-text': the optimal execution time (t) for the concurrent memory operation, and', 'the concurrency level (c) of the transactional memory system., 'determining a serial execution time (T) for the concurrent memory operation based, at least in part, upon4. The computer-implemented method of further comprising: [{'sub': 'tm', 'the probable execution time (T), and'}, {'sub': 'cs', 'the serial execution time (T) for the concurrent memory operation.'}], 'determining a performance boost indicator (B) for the concurrent memory operation based, at least in part, upon5. The computer-implemented method of further comprising:defining an abort penalty (P) for the concurrent ...

System, method, and computer program product for inserting a gap in information sent from a drive to a host device

A system, method, and computer program product are provided for inserting a gap in information sent from a drive to a host device. In operation, one or more commands are received at a drive from a host device. Additionally, information is queued to send to the host device. Furthermore, a gap is inserted in the information to send to the host device such that the host device is capable of sending additional commands to the drive.

SCHEDULING OF READ OPERATIONS AND WRITE OPERATIONS BASED ON A DATA BUS MODE

A data bus can be determined to be in a write mode based on a prior operation transmitted over the data bus being a write operation. In response to determining that the data bus is in the write mode, a number of partition queues of a plurality of partition queues that include at least one write operation can be identified. A determination as to whether the number of partition queues of the plurality of partition queues satisfies a threshold number can be made. In response to determining that the number of partition queues satisfies the threshold number, another write operation from the plurality of partition queues can be transmitted over the data bus. 1. A method comprising:determining that a data bus is in a write mode based on a prior operation transmitted over the data bus being a write operation;in response to determining that the data bus is in the write mode, identifying a number of partition queues of a plurality of partition queues that include at least one write operation;determining, by a processing device, whether the number of partition queues of the plurality of partition queues satisfies a threshold number; andin response to determining that the number of partition queues satisfies the threshold number, transmitting another write operation from the plurality of partition queues over the data bus.2. The method of claim 1 , further comprising:in response to determining that the number of partition queues does not satisfy the threshold number, transmitting a read operation from the plurality of partition queues over the data bus.3. The method of claim 2 , further comprising:determining that a particular partition queue of the plurality of partition queues is available, wherein the particular partition queue is available when transmitting the read operation from the particular partition queue over the data bus satisfies a data bus protocol.4. The method of claim 2 , further comprising:in response to transmitting the read operation from the plurality of ...

Method And Apparatus For Supporting Wide Operations Using Atomic Sequences

Implementations of wide atomic sequences are achieved by augmenting a load operation designed to initiate an atomic sequence and augmenting a conditional storing operation that typically terminates the atomic sequence. The augmented load operation is designed to further allocate a memory buffer besides initiating the atomic sequence. The conditional storing operation is augmented to check the allocated memory buffer for any data stored therein. If one or more data words are detected in the memory buffer, the conditional storing operation stores the detected data word(s) and another word provided as operand in a concatenation of memory locations. The achieved wide atomic sequences enable the hardware system to support wide memory operations and wide operations in general.

MEMORY COMPONENT WITH PATTERN REGISTER CIRCUITRY TO PROVIDE DATA PATTERNS FOR CALIBRATION

A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration. 1. (canceled)2. A memory component , comprising:circuitry to detect when the memory component is first powered up;a first register and a second register to respectively store a first register content value and a second register content value that are initialized to known values in response to the circuitry detecting the memory component is first powered up;a first interface to receive commands from a memory controller; and,a second interface to transmit, to the memory controller, a one of the first register content value and the second register content value as selected by a first command received via the first interface.3. The memory component of claim 2 , wherein the first interface is to receive a second command that specifies the first register content value.4. The memory component of claim 3 , wherein the first interface is to receive a third command that specifies the second register content value.5. The memory component of claim 4 , further comprising:a memory core, the first interface to receive a fourth command that specifies data to be accessed from the memory core, the data ...

Container index including a tracking data structure

Example implementations relate to metadata operations in a storage system. An example includes a storage controller loading a manifest from persistent storage into memory, and loading a first container index from persistent storage into the memory. The first container index is associated with the manifest loaded into the memory. The storage controller determines whether a tracking data structure of the first container index includes an identifier of the manifest. In response to a determination that the tracking data structure of the first container index does not include the identifier of the manifest, the storage controller discards the manifest.

Conditional access with timeout

A method can include receiving a first memory load request by a conditional load with time out (CLT) device at a first time. The first memory load request can specify a first condition. A first determination of whether the first condition is satisfied is performed. The CLT device determines a wait period when the first condition is not satisfied. A reply is issued. The reply indicates that the first condition is satisfied when the first condition is satisfied. The reply indicates that the first condition is not satisfied when the duration of the wait period exceeds a time-out threshold. When the first condition is not satisfied, a first memory store request can be received during the wait period and a second determination of whether the first condition satisfied performed. The reply indicates that the first condition is satisfied when the second determination is that the first condition is satisfied.

Memory System with Shared File System

An apparatus includes a non-volatile memory and a processor. The processor is configured to receive, from a host, commands for storage of data in the non-volatile memory, to further receive from the host, for storage in the non-volatile memory, File System (FS) information that specifies organization of the data in a FS of the host, to receive from the host a directive that grants the processor permission and capability to access and modify the FS information, and to access the FS information, using the directive, so as to manage the storage of the data in the non-volatile memory.

RECEIVER ARCHITECTURE FOR MEMORY READS

A receiver architecture for memory reads is described herein. In one embodiment, a memory interface comprises a plurality of transmitters, wherein each of the plurality of transmitters is configured to transmit data to a memory device over a respective one of a plurality of I/O channels. The memory interface also comprises a plurality of receivers, wherein each of the plurality of receivers is coupled to a respective one of the plurality of transmitters, and is configured to receive data from the memory device over the respective one of the plurality of I/O channels. The plurality of receivers are grouped together into a receiver subsystem that is located away from the plurality of transmitters. 1. A memory interface , comprising:a plurality of transmitters, wherein each of the plurality of transmitters is configured to transmit data to a memory device over a respective one of a plurality of I/O channels; anda plurality of receivers, wherein each of the plurality of receivers is coupled to a respective one of the plurality of transmitters, and is configured to receive data from the memory device over the respective one of the plurality of I/O channels;wherein the plurality of receivers are grouped together into a receiver subsystem that is located away from the plurality of transmitters, the plurality of transmitters span a first distance, the plurality of receivers span a second distance, and the first distance is at least five times longer than the second distance.2. (canceled)3. The memory interface of claim 1 , wherein the plurality of receivers comprise at least eight receivers claim 1 , and the plurality of receivers span a distance of 200 μm or less.4. The memory interface of claim 3 , wherein the plurality of transmitters comprise at least eight transmitters claim 3 , and the plurality of transmitters span a distance of at least 1 mm.5. The memory interface of claim 1 , further comprising a plurality of low-impedance paths claim 1 , wherein each of the low- ...

SYSTEMS AND METHODS FOR FACILITATING DATA ENCRYPTION AND DECRYPTION AND ERASING OF ASSOCIATED INFORMATION

Various techniques provide systems and methods for facilitating data encryption/decryption and almost immediate erasure of associated information. In one example, a method includes receiving first data in a first memory. The method further includes receiving a first key in a second memory. The method further includes generating, by a logic circuit, second data based on the first data and the first key. The method further includes providing the second data for transmission. The method further includes erasing the first data and/or the first key in one-half clock cycle of generating the second data. Related methods and devices are also provided. 1. A method comprising:{'b': 1805', '1505, 'receiving () first data in a first memory ();'}{'b': 1810', '1510, 'receiving () a first key in a second memory ();'}{'b': 1815', '1515, 'generating (), by a logic circuit (), second data based on the first data and the first key;'}{'b': '1820', 'providing () the second data for transmission; and'}{'b': '1825', 'erasing () the first key in one-half clock cycle of generating the second data.'}2. The method of claim 1 , wherein the erasing further comprises erasing the first data.3. The method of claim 2 , wherein the erasing comprises:erasing the first data in the first memory by overwriting the first memory with results of bitwise operations on the first data, first key, and second data; anderasing the key in the second memory by overwriting the second memory with results of bitwise operations on the first data, first key, and second data.4. The method of claim 1 , wherein the erasing comprises providing claim 1 , by the logic circuit claim 1 , information associated with the second data to the second memory to overwrite the second memory.5. The method of claim 1 , wherein the erasing comprises erasing the first key in the second memory by overwriting the second memory with a predetermined bit sequence.6. The method of claim 1 , wherein the generating comprises performing bitwise ...

Method and System for Countering Ransomware

Methods, systems and computer readable media are provide for protecting stored data from ransomware. In an embodiment, the data is stored in an external drive connected to the processor. The connection between the processor and external drive is interrupted (e.g., open) except during a data transfer between the processor and the external drive. Connection of the processor to the external drive, permitted for a time period specified by a user or until the transfer of data is complete, occurs in response to manual actuation of a control means interposed between the processor and external drive and optionally, an indication from the user computing system that malware has not been detected on the device. The control means may be a mechanical switch or a fingerprint authentication device.

Data storage systems and methods for improved data relocation based on read-level voltages associated with error recovery

Apparatus, media, methods, and systems are disclosed for improved data relocation based on read-level voltages. A data storage system may include a non-volatile memory device including a source region and a destination region. The destination region may include a first destination block and a second destination block. A controller may read first data in the source region using a first read-level voltage, and read second data in the source region using a second read-level voltage. The controller may associate, based on the first and second read-level voltages, each of the first data and the second data with a respective one of the first and the second destination blocks. The controller may cause each of the first and second data to be stored in the associated one of the first and second destination blocks.

SYSTEM AND METHOD FOR EARLY REMOVAL OF TOMBSTONE RECORDS IN DATABASE

A method of deleting tombstones early includes setting an initial-flag in a first record in the storage system, setting a delete-flag in a second record in the storage system, selecting a set of one or more records in the storage system to be written to an extent of the storage system in a merge operation, each of the one or more records being associated with the first key, and performing the merge operation, wherein the second record is not written to the extent during the merge operation based at least in part on a determination that the first record having the initial-flag set is the oldest record in the set and the second record having the delete-flag set is the newest record in the set. 1. A computer-implemented method of deleting one or more records from a log-structured merge (LSM) tree based storage system during a merge operation , comprising:setting an initial-flag in a first record in the storage system, the initial-flag indicating that the first record is associated with a first key that is not associated with any other active record;setting a delete-flag in a second record in the storage system, the second record being associated with the first key and the delete-flag indicating that a value associated with the first key is designated to be deleted from the storage system;selecting a set of one or more records in the storage system to be written to an extent of the storage system in a merge operation, each of the one or more records being associated with the first key; andperforming the merge operation, wherein the second record is not written to the extent during the merge operation based at least in part on a determination that the first record having the initial-flag set is the oldest record in the set and the second record having the delete-flag set is the newest record in the set.2. The method of claim 1 , wherein the first record and the second record are the same record claim 1 , being the only record in the set.3. The method of claim 1 , wherein ...

DESIGN ASSISTING DEVICE AND NON-TRANSITORY COMPUTER READABLE MEDIUM

A design assisting device includes a selecting unit and a display. The selecting unit selects, from among existing components that fit a specification required for a design target component, taking into consideration procurement information of the existing components, a target component candidate, which is a candidate for the target component, and selects, from among existing components that fit a specification required for a related component related to the target component, taking into consideration procurement information of the existing components, a related component candidate, which is a candidate for the related component. The display displays the target component candidate and the related component candidate. 1. A design assisting device comprising a display and a hardware processor , wherein the hardware processor is configured to:receive a specification required for a design target component and a specification required for a related component;select, from among existing components that fit the specification required for the design target component, taking into consideration the procurement information of the existing components, a target component candidate, which is a candidate for the target component;select, from among existing components that fit the specification required for the related component related to the target component, taking into consideration the procurement information of the existing components, a related component candidate, which is a candidate for the related component;create a candidate list that includes the target component candidate, the related component candidate, a compatibility of a combination of the target component candidate and the related component candidate, and a procurement cost information of the combination of the target component candidate and the related component candidate; andcontrol the display to display the candidate list on the display.2. The design assisting device according to claim 1 , wherein the ...

TECHNIQUES FOR POWER MANAGEMENT USING LOOPBACK

Techniques and devices for managing power consumption of a memory system using loopback are described. When a memory system is in a first state (e.g., a deactivated state), a host device may send a signal to change one or more components of the memory system to a second state (e.g., an activated state). The signal may be received by one or more memory devices, which may activate one or more components based on the signal. The one or more memory devices may send a second signal to a power management component, such as a power management integrated circuit (PMIC), using one or more techniques. The second signal may be received by the PMIC using a conductive path running between the memory devices and the PMIC. Based on receiving the second signal or some third signal that is based on the second signal, the PMIC may enter an activated state. 1. (canceled)2. A method , comprising:sending, from a memory device to a power management integrated circuit (PMIC) via a first loopback pin of the memory device, a first signal to activate one or more components of the PMIC; andsending, from the memory device to a transistor configured to selectively couple the memory device with the PMIC, a second signal to activate the transistor outside a testing phase of operation.3. The method of claim 2 , wherein the second signal is sent via a second loopback pin of the memory device.4. The method of claim 3 , wherein the first loopback pin and the second loopback pin are configured for use during a testing phase of operation.5. The method of claim 3 , further comprising:inducing a third signal on a conductive path coupled with the PMIC based at least in part on sending the first signal via the first loopback pin, the third signal for activating the one or more components of the PMIC.6. The method of claim 5 , further comprising:toggling the first signal sent via the first loopback pin between different voltage levels, wherein inducing the third signal on the conductive path is based at ...

METHOD AND SYSTEM FOR FULL RESOLUTION REAL-TIME DATA LOGGING

A method and data-logging system are provided. The system includes a map-ahead thread configured to acquire blocks of private memory for storing data to be logged, the blocks of private memory being twice as large as the file page size, a master thread configured to write data to the blocks of private memory, in real-time and in full resolution, the data acquired during operation of a machine generating the data and written to the blocks of private memory in real-time, the machine including a controller including a processor communicatively coupled to a memory having processor instructions therein, and a write-behind thread configured to acquire pages of memory that are mapped to pages in a file, copy the data from the blocks of private memory to the acquired file-mapped blocks of memory. 1. A data-logging system comprising:a map-ahead thread configured to acquire blocks of private memory for storing data to be logged, the blocks of private memory being twice as large as the file page size;a master thread configured to write data to the blocks of private memory, in real-time and in full resolution, the data acquired during operation of a machine generating the data and written to the blocks of private memory in real-time, the machine including a controller including a processor communicatively coupled to a memory having processor instructions therein; anda write-behind thread configured to acquire pages of memory that are mapped to pages in a file, copy the data from the blocks of private memory to the acquired file-mapped blocks of memory.2. The data-logging system of claim 1 , wherein the map-ahead thread is configured to automatically select an amount of memory to be maintained in a linked list of unused blocks of private memory using a performance measure of the mapping.3. The data-logging system of claim 1 , wherein the map-ahead thread is configured to write a message to a log file when the amount of file-mapped blocks of memory is outside a predetermined ...

Implied directory state updates

A request is received over a link that requests a particular line in memory. A directory state record is identified in memory that identifies a directory state of the particular line. A type of the request is identified from the request. It is determined that the directory state of the particular line is to change from the particular state to a new state based on the directory state of the particular line and the type of the request. The directory state record is changed, in response to receipt of the request, to reflect the new state. A copy of the particular line is sent in response to the request

Performing copies in a storage system

A system and method for performing copy offload operations. When a copy offload operation from a first volume (pointing to a first medium) to a second volume (pointing to a second medium) is requested, the copy offload operation is performed without accessing the data being copied. A third medium is created, and the first medium is recorded as the underlying medium of the third medium. The first volume is re-pointed to the third medium. Also, a fourth medium is created, the second volume is re-pointed to the fourth medium, and the second medium is recorded as the underlying medium of the targeted range of the fourth medium. All other ranges of the fourth medium have the second medium as their underlying medium.

SAFETY FOR VOLUME OPERATIONS

A system and method for maintaining the safety of volume operations. A storage controller receives a request to delete a first volume. In response to this request, the storage controller can delete a link between the first volume and its anchor medium. The storage controller can also delay the deletion of the first volume's anchor medium. Later on, if the user wishes to restore the first volume, the storage controller can reconnect the first volume to its previous anchor medium, effectively restoring the first volume to its former state and undoing the deletion operation. 1. A computer system comprising:one or more storage devices; and receive a request to delete a first volume;', responsive to determining a first medium is an anchor medium of the first volume, store an indication that the first volume was previously linked to the first medium; and', 'remove any indication that the first volume is valid., 'responsive to receiving the request to delete the first volume], 'a storage controller coupled to the one or more storage devices, wherein the storage controller is configured to2. The computer system as recited in claim 1 , wherein the storage controller is further configured to maintain a volume to medium mapping table to track relationships between volumes and anchor mediums claim 1 , and wherein removing any indication that the first volume is valid comprises deleting a first entry corresponding to the first volume from the volume to medium mapping table.3. The computer system as recited in claim 2 , wherein after receiving the request to delete the first volume claim 2 , the storage controller is further configured to:receive a request to restore the first volume; retrieve the indication that the first volume was previously linked to the first medium; and', 'create a new entry in the volume to medium mapping table, wherein the new entry links the first volume to the first medium., 'responsive to receiving the request to restore the first volume4. The computer ...

Lightweight Random Memory Allocation

In response to a memory allocation request received from an application thread, a random number is obtained (e.g., from a random number list previously populated with multiple random numbers). A starting location in at least a portion of a bitmap associated with a region including multiple blocks of the memory is determined based on the random number. A portion of the bitmap is scanned, beginning at the starting location, to identify a location in the bitmap corresponding to an available block of the multiple blocks, and an indication of this available block is returned to the application thread. 1. A method in a system , the method comprising:receiving, from an application thread, a request for memory to be allocated to the application thread, including an index value;obtaining a random number, the obtaining based on the received index value;determining, based on the random number, a starting location in at least a portion of a bitmap associated with a region including multiple blocks of the memory;scanning, beginning at the starting location, at least the portion of the bitmap to identify a location in the bitmap corresponding to an available block of the multiple blocks; andreturning, to the application thread, an indication of the available block.2. A method as recited in claim 1 , the obtaining the random number comprising obtaining the random number from a list of previously generated random numbers.3. A method as recited in claim 2 , further comprising replacing claim 2 , by a module of a memory allocator claim 2 , one or more random numbers in the list with one or more new random numbers during performance of a high latency operation by the memory allocator that also performs the determining and the scanning.4. A method as recited in claim 2 , the obtaining the random number further comprising:obtaining the random number from a location in the list of previously generated random numbers identified by the index value;updating the index value; andwherein ...

DEVICE AND METHOD FOR PROCESSING MESSAGE

Embodiments provide a device and method for processing messages according to a priority order and for reducing a message processing time when a response event occurs, in a PLC communication module. 1. A method for processing messages of a first processor and a second processor in a communication module of a programmable logic controller (PLC) comprising the first processor , the second processor and a shared memory comprising a first sector for storing high-priority messages and a second sector for storing low-priority messages , the method comprising:determining, by the first processor, a priority order to be processed by the second processor and writing a request message in the first sector or the second sector of the shared memory according to the priority order;processing, by the second processor, communication for the request message of the first sector with precedence over the second sector;checking, by the second processor, the priority order of the request message and writing a response message in the first sector or the second sector of the shared memory according to the priority order; andreading, by the first processor, the response message of the first sector with precedence over the second sector and moving to a corresponding message function address.2. The method according to claim 1 , wherein each of the request message and the response message comprises a message type field claim 1 , a message priority order field claim 1 , and a response message processing function address field.3. The method according to claim 1 , wherein the processing the communication comprises:processing, when the request message exists in the first sector, the communication for the request message;checking, when the request message does not exist in the first sector, whether the request message exists in the second sector of the shared memory; andprocessing the communication for the request message of the second sector.4. The method according to claim 2 , wherein the checking ...

Data Storage Device Control With Power Hazard Mode

In response to a warning that power may be interrupted, a non-volatile data storage sub-system of a host computer system re-orders machine readable instructions that the non-volatile data storage sub-system is going to perform. This re-ordering of instructions decreases the probability that important data will be lost. The re-ordering of instructions is performed according to rules. 1. A method of controlling a non-volatile data storage sub-system , including a non-volatile storage medium and a non-volatile sub-system controller , which is part of a host computer system , the method comprising:entering, by the non-volatile data storage sub-system controller, power hazard mode in response to a power hazard signal; andduring the power hazard mode, re-ordering, by the non-volatile data storage sub-system controller and on an ongoing basis, a list of instructions to be performed by the non-volatile data storage sub-system controller;wherein:at least the re-ordering of the list of instructions is performed by computer software running on computer hardware.2. The method of further comprising:during the power hazard mode, performing, by the non-volatile data storage sub-system, at least a portion of the list of instructions in the re-ordered order to write data to the non-volatile storage medium in a different order than the data would have been written if the re-ordering of the list of instructions had not been performed.3. The method of wherein:the re-ordering by the non-volatile data storage sub-system controller is done according to a set of rules; and (i) all background task related commands are suspended,', '(ii) all commands are executed in order received absent re-ordering;', '(iii) any internal write caching commands, which involve writing data to an external storage medium, are suspended,', '(iv) all write commands are given priority above all other commands,', '(v) all read commands are prioritized behind any write commands;', '(vi) all error-recovery-related ...

System and method for backup generation using composed systems

A system for managing composed information handling systems includes information handling systems and a composed information handling system of the composed information handling systems, which includes at least one compute resource set, at least one control resource set, and at least one hardware resource set. The system also includes a system control processor that obtains a bare metal communication from a compute resource set indicating a write of data, writes a first copy of the data in a storage resource of the at least one hardware resource set, writes a second copy of the data in a trace volume, generates a backup of the data using the trace volume, and stores the backup in a storage.

INFORMATION PROCESSING SYSTEM AND METHOD OF CONTROLLING THE SAME

An information processing system in which a plurality of information processing apparatuses are connected with each other, wherein each information processing apparatus includes a storage unit configured to store data according to each destination information processing apparatus, and a transmission control unit configured to transmit data to be transmitted in the same transmission direction and with the same number of hops collectively among the data stored in the storage unit. 1. An information processing system in which a plurality of information processing apparatuses are connected with each other , wherein a storage unit configured to store data according to each destination information processing apparatus, and', 'a transmission control unit configured to transmit data to be transmitted in the same transmission direction and with the same number of hops collectively among the data stored in the storage unit., 'each information processing apparatus includes'}2. The information processing system according to claim 1 , whereindata to be transmitted to a destination information processing apparatus is divided into more than one piece of data and stored in the storage unit, andthe transmission control unit transmits the divided pieces of data in different transmission directions.3. The information processing system according to claim 1 , wherein each information processing apparatus includes a barrier synchronization unit configured to perform a barrier synchronization when data transmission in a transmission direction of the different transmission directions is completed.4. The information processing system according to claim 1 , wherein each information processing apparatus is connected with each other in a mesh structure or in a torus structure.5. A method of controlling an information processing system in which a plurality of information processing apparatus are connected with each other claim 1 , each information processing apparatus including a storage unit ...

INTEGRATED CIRCUIT DEVICE, MEMORY INTERFACE MODULE, DATA PROCESSING SYSTEM AND METHOD FOR PROVIDING DATA ACCESS CONTROL

An integrated circuit device comprising at least one memory interface module arranged to be operably coupled between at least one data storage device and a plurality of master devices within a data processing system. The at least one memory interface module comprises a plurality of buffers and at least one data access control module. The at least one data access control module being arranged to fetch data from the at least one data storage device in response to a received memory access request comprising a master device identifier, select at least one buffer based at least partly on the master device identifier of the received access request, and load the fetched data into the selected at least one buffer. 1. An integrated circuit device comprising at least one memory interface module arranged to be operably coupled between at least one data storage device and a plurality of master devices within a data processing system; the at least one memory interface module comprising a plurality of buffers and at least one data access control module , the at least one data access control module being arranged to:fetch data from the at least one data storage device in response to a received memory access request comprising a master device identifier;select at least one buffer based at least partly on the master device identifier of the received access request; andload the fetched data into the selected at least one buffer.2. The integrated circuit device of wherein the at least one data access control module is arranged to associate a first set of buffers with a first master device identifier and at least one further set of buffers with at least one further master device identifier.3. The integrated circuit device of wherein the at least one data access control module is further arranged to select at least one buffer into which fetched data is to be loaded from the set of buffers with which the master device identifier of the received access request is associated.4. The ...

SYSTEM, METHOD AND A NON-TRANSITORY COMPUTER READABLE MEDIUM FOR REDUCTION OF CONSUMPTION OF STORAGE SYSTEM RESOURCES

A method that may include receiving, by a storage system, a write request for storing in the storage system multiple input data units that are related to a certain file; comparing, by the storage system, the multiple input data units to stored data units of the certain file to find matching and non-matching input data units; wherein each matching input data unit equals a corresponding stored data unit and each non-matching input data unit differs from a corresponding stored data unit; preventing a storage of each matching input data unit; storing each non-matching input data unit; and updating at least one storage system management data structure to reflect a reception of non-matching input data units while not reflecting a reception of matching input data units. 1. A method , comprising:receiving, by a storage system, a write request for storing in the storage system multiple input data units that are related to a certain file;comparing, by the storage system, the multiple input data units to stored data units of the certain file to find matching and non-matching input data units; wherein each matching input data unit equals a corresponding stored data unit and each non-matching input data unit differs from a corresponding stored data unit;preventing a storage of each matching input data unit;storing each non-matching input data unit; andupdating at least one storage system management data structure to reflect a reception of non-matching input data units while not reflecting a reception of matching input data units.2. The method according to further comprising determining whether an aggregate size of the multiple input data units exceeds a certain size threshold; and wherein the comparing is executed only when the aggregate size of the multiple data units exceeds the certain size threshold.3. The method according to wherein the certain size threshold is determined based upon an aggregate size of the stored data units of the certain file.4. The method according to ...

LIVE MIGRATION OF VIRTUAL DISKS

Live migration of a virtual disk of a virtual machine between storage devices is described. In accordance with one example, a computer system prepares a first area of a first storage device and a second area of a second storage device for a live snapshot of a virtual disk of a virtual machine. A transaction is then executed that includes storing the live snapshot in the first area of the first storage device, copying the live snapshot to the second area of the second storage device, and mirroring a change to the virtual disk that occurs after the creation of the live snapshot, where the mirroring is via one or more write operations to the live snapshot in the first area and to the copy of the live snapshot in the second area. 2. The method of further comprising detecting a failure in at least one of the storing claim 1 , the copying claim 1 , or the mirroring.3. The method of further comprising deleting claim 2 , in response to the detecting the failure claim 2 , the live snapshot in the first area and the copy of the live snapshot in the second area.4. The method of further comprising rolling back claim 2 , in response to the detecting the failure claim 2 , the one or more write operations to the live snapshot in the first area and to the copy of the live snapshot in the second area.5. The method of wherein the preparing of the first area comprises allocating and initializing the area.6. The method of wherein the one or more write operations comprises a first write operation to the first area and a second write operation to the second area claim 1 , and wherein the first write operation and the second write operation are concurrent.7. The method of wherein the copying and mirroring are executed concurrently.8. The method of wherein claim 1 , prior to the preparing claim 1 , the virtual disk is mapped to an area of the first storage device claim 1 , and wherein the changing comprises mapping claim 1 , after the transaction executes successfully claim 1 , the virtual ...

SYSTEM AND METHOD FOR EMULATION OF ENHANCED APPLICATION MODULE REDUNDANCY (EAM-R)

A method includes emulating an Enhanced Application Module Redundancy (EAM-R) system that includes a primary EAM-R board and a secondary EAM-R board. Emulating the EAM-R system includes detecting that data received from a sensor has been written to a memory block associated with the primary EAM-R board, and sending instructions to a secondary computing device to write a copy of the data to a same memory block in the secondary computing device that is associated with the secondary EAM-R board. The EAM-R system is emulated in an emulation system that includes at least one network connection. The emulation system does not include a physical primary EAM-R board or a physical secondary EAM-R board. 1. A method comprising: detecting that data received from a sensor has been written to a memory block associated with the primary EAM-R board, and', 'sending instructions to a secondary computing device to write a copy of the data to a same memory block in the secondary computing device that is associated to with the secondary EAM-R board,, 'emulating an Enhanced Application Module Redundancy (EAM-R) system that includes a primary EAM-R board and a secondary EAM-R board, wherein emulating the EAM-R system compriseswherein the EAM-R system is emulated in an emulation system that includes at least one network connection, andwherein the emulation system does not include a physical primary EAM-R board or a physical secondary EAM-R board.2. The method of claim 1 , wherein the primary EAM-R board and the secondary EAM-R board are connected by two ribbon cables claim 1 , and wherein the emulation system does not include the two ribbon cables.3. The method of claim 2 , wherein the emulation system includes at least one Ethernet cable instead of the two ribbon cables.4. The method of claim 3 , wherein the at least one Ethernet cable supports both bidirectional data exchange and bidirectional signal exchange.5. The method of claim 3 , wherein the emulation system further includes a ...

AVOIDING PHYSICAL FRAGMENTATION IN A VIRTUALIZED STORAGE ENVIRONMENT

A virtualized storage stack includes logical layers above the physical storage layer. Each logical layer allocates data blocks, and the data block allocation is propagated down to the physical storage layer. To facilitate contiguous storage, each layer of the virtualized storage stack maintains additional metadata associated with data blocks. For each data block, the metadata indicates whether the data block is free, provisioned and includes a tag that indicates when the data block was first written. Data blocks that were first written as part of the same write request share the same tag, and are mostly guaranteed to be physically co-located. Block allocations that reuse data blocks having the same tag are preferred. Such preference increases the likelihood of the blocks being contiguous in the physical storage as these blocks were allocated as part of the same first write. 1. A method for defragmenting physical storage that is accessed through a set of layers of a virtualization stack , the method comprising:receiving a first defragmentation request at a lower layer from an upper layer, the first defragmentation request indicating a plurality of storage blocks for defragmentation;determining, at the lower layer, a set of storage blocks that correspond to the plurality of storage blocks; andtransmitting by the lower layer a second defragmentation request to a layer that is below thereto, the second defragmentation request indicating the set of storage blocks for defragmentation.2. The method of claim 1 , wherein the layer below the lower layer is at a bottom of the virtualization stack.3. The method of claim 2 , further comprising determining at the bottom layer that defragmentation is necessary and initiating a first set of data movement operations for defragmentation.4. The method of claim 3 , further comprising determining that the data movement operations were not successful claim 3 , and transmitting by the bottom layer a first failure notification to the lower ...

Device and method for controlling data-reading and -writing

A device for controlling data-reading and -writing includes a memory controller. The memory controller controls the reading and writing of a memory, wherein the memory includes at least a first physical block and a second physical block. The memory controller, upon receives a write request for a data block, duplicately writes mapped data corresponding to data of the data block into mapped positions corresponding to the first physical block and the second physical block according to the write request. The memory controller, upon receives a read request for the data block, selects to read the mapped data corresponding to the data of the data block from the first physical block or the second physical block corresponding to the mapped position according to the read request and a reading condition, to continuously output the data of the data block stored in the memory.

STORAGE DEVICE THROTTLING AMOUNT OF COMMUNICATED DATA DEPENDING ON SUSPENSION FREQUENCY OF OPERATION

A storage device includes a memory and a controller. The controller controls the memory such that, in response to a request for a first read operation on the memory while a first write operation is performed on the memory, the first write operation is suspended, and the first read operation is performed, the suspended first write operation is resumed after the first read operation is completed, and second write operation subsequent to the first write operation is performed on the memory after the resumed first write operation is completed. The controller throttles an amount of data communicated to the memory device for the second write operation or for a second read operation subsequent to the first read operation, based on a frequency that the first write operation is suspended. 1. A storage device comprising:a nonvolatile memory; and compute a suspension count based on a number of read operations between the controller and the nonvolatile memory per unit time;', 'compare the suspension count with a reference count;', 'receive a first write operation and a first read operation to communicate between the controller and the nonvolatile memory;', 'suspend the first write operation when the suspension count is less than the reference count; and', 'resume the suspended first write operation after the first read operation is completed., 'a controller coupled to the nonvolatile memory and configured to2. The storage device of claim 1 , wherein the controller further configured to:set a maximum suspension count; andsuspend the first write operation when the suspension count is less than the maximum suspension count.3. The storage device of claim 1 , wherein the suspension of the first write operation comprises adjusting a number of unit data communicated between the controller and the nonvolatile memory per the unit time in response to the first write operation based on the suspension count.4. The storage device of claim 3 , further comprising:a look-up table, wherein the ...

SYSTEM SUPPORTING MULTIPLE PARTITIONS WITH DIFFERING TRANSLATION FORMATS

A system configuration is provided with multiple partitions that supports different types of address translation structure formats. The configuration may include partitions that use a single level of translation and those that use a nested level of translation. Further, differing types of translation structures may be used. The different partitions are supported by a single hypervisor. 1. A method of facilitating memory access , said method comprising:providing a first partition within a system configuration, the first partition configured to support an operating system (OS) designed for a first address translation architecture, wherein configuration of the first partition to support the OS designed for the first address translation architecture is indicated in a configuration data structure, and wherein the first partition is not configured, as indicated in the configuration data structure, to support an OS designed for a second address translation architecture; andproviding a second partition within the system configuration, the second partition configured to support the OS designed for the second address translation architecture, the second partition not configured to support the OS designed for the first address translation architecture, wherein the first address translation architecture is structurally different from the second address translation architecture.2. The method of claim 1 , wherein the first address translation architecture is for handling address translation requests of the first partition and the second address translation architecture is for handling address translation requests of the second partition.3. The method of claim 1 , wherein the first address translation architecture uses a hash structure and the second address translation architecture uses a hierarchical table structure.4. The method of claim 1 , wherein the first partition uses a single level address translation mechanism for translating guest virtual addresses to host physical ...