SYSTEMS AND METHODS FOR ENERGY-EFFICIENT DATA PROCESSING

An energy-efficient sequencer comprising inline multipliers and adders causes a read source that contains matching values to output an enable signal to enable a data item prior to using a multiplier to multiply the data item with a weight to obtain a product for use in a matrix-multiplication in hardware. A second enable signal causes the output to be written to the data item.

PERFORMANCE AND AREA EFFICIENT SYNAPSE MEMORY CELL STRUCTURE

A synapse memory system includes a plurality of synapse memory cells, a write portion, and read drivers. Each synapse memory cells is disposed at cross points of axon lines and dendrite lines and includes a plurality of analog memory devices and each synapse memory cell is configured to store a weight value according to an output level of a write signal. The plurality of analog memory devices is combined to constitute each synapse memory cell. The write portion is configured to write the weight value to each synapse memory cell and includes a write driver and an output controller. The write driver is configured to output the write signal to each synapse memory cell and the output controller is configured to control the output level of the write signal of the write driver. The read drivers are configured to read the weight value stored in the synapse memory cells.

Artificial intelligence hardware with synaptic reuse

Synaptic reuse allows for a plurality of artificial neurons to be associated with corresponding pluralities of artificial synapses and variable gain amplifiers, to thereby use less space and fewer components to implement and less power to operate than neurons having dedicated paths for each input source. To reduce the likelihood of signal collision, and allow for the independent control and interpretation of input spikes, a router is configured to connect input sources to each of the plurality of artificial neurons in conjunction with a gain configuration controller that is configured to set a gain on each of the plurality of variable gain amplifiers based on a time division schema and an identity of an input source transmitting a spike during a given time.

Online training of neural networks

A computer-implemented method for training parameters of a recurrent neural network (100) is provided. The network (100) comprises one or more layers (110) of neuronal units (111). Each neuronal unit (111) has an internal state (120), which may also be denoted as unit state (120). The method comprises providing training data comprising an input signal (131) and an expected output signal (132) to the recurrent neural network (100). The method further comprises computing，for each neuronal unit (111), a spatial gradient component (141) and computing, for each neuronal unit (111), a temporal gradient component (142). The method further comprises updating the temporal and the spatial gradient component (141) for each neuronal unit (111) at each time instance of the input signal (131). The computing of the spatial and the gradient component (141) may be performed independently from each other. A neural network (100) and a related computer program product are also provided． ...

Silicon-oxide-nitride-oxide-silicon multi-level non-volatile memory device and methods of fabrication thereof

A method of fabricating a multi-level memory cell that includes the steps of forming a shallow trench isolation (STI) in a substrate, performing clean and preclean process such that top surfaces of the STI and substrate are substantially leveled, forming a tunnel dielectric using a radical oxidation process, forming upper and lower silicon oxynitride layers in which an amount of electric charge trapped represents N×analog values stored in the multi-level memory cell, N is a natural number greater than 2, forming a blocking dielectric and patterning to form a memory stack, and forming a lightly-doped drain extension (LDD) adjacent to the memory stack by angled implant such that the LDD extends at least partly under the memory stack.

MULTI-LAYER PHASE CHANGE MEMORY DEVICE

A phase change memory (PCM) cell comprises a first electrode comprised of a first electrically conductive material, a second electrode comprised of a second electrically conductive material, a first phase change layer positioned between the first electrode and the second electrode and being comprised of a first phase change material, and a second phase change layer positioned between the first electrode and the second electrode and being comprised of a second phase change material. The first phase change material has a first resistivity, the second phase change material has a second resistivity, and wherein the first resistivity is at least two times the second resistivity.

Arithmetic device and electronic device

An arithmetic device and an electronic device having small power consumption is provided. An arithmetic device and an electronic device capable of high-speed operation is provided. An arithmetic device and an electronic device capable of suppressing heat generation is provided. The arithmetic device includes a first arithmetic portion and a second arithmetic portion. The first arithmetic portion includes a first CPU core and a second CPU core. The second arithmetic portion includes a first GPU core and a second GPU core. The CPU cores each have a power gating function and each include a first data retention circuit electrically connected to a flip-flop. The first GPU core includes a second data retention circuit capable of retaining an analog value and reading out the analog value as digital data of two or more bits. The second GPU core includes a third data retention circuit capable of retaining a digital value and reading out the digital value as digital data of one bit. The first to ...

Performance and area efficient synapse memory cell structure

A synapse memory system includes: synapse memory cells provided at cross points of axon lines and dendrite lines, each synapse memory cell including plural analog memory devices, each synapse memory cell being configured to store a weight value according to an output level of a write signal, the plural analog memory devices being combined to constitute each synapse memory cell; a write portion configured to write the weight value to each synapse memory cell and including a write driver and an output controller, the write driver being configured to output the write signal to each synapse memory cell, the output controller being configured to control the output level of the write signal of the write driver; and read drivers configured to read the weight value stored in the synapse memory cells.

Multi-layer phase change memory device

A phase change memory (PCM) cell comprises a first electrode comprised of a first electrically conductive material, a second electrode comprised of a second electrically conductive material, a first phase change layer positioned between the first electrode and the second electrode and being comprised of a first phase change material, and a second phase change layer positioned between the first electrode and the second electrode and being comprised of a second phase change material. The first phase change material has a first resistivity, the second phase change material has a second resistivity, and wherein the first resistivity is at least two times the second resistivity.

Resistive switching memory cell

A resistive random access memory (ReRAM) device is provided. The ReRAM device (100) includes a stack structure including a first electrode (126), a metal oxide layer (128) in contact with the first electrode (126), and a second electrode (130) in contact with the metal oxide layer (128). A portion of the stack structure is modified by ion implantation (140), and the modified portion of the stack structure is offset from edges of the stack structure.

Suppressing outlier drift coefficients while programming phase change memory synapses

Non-volatile analog resistive memory cells implementing ferroelectric select transistors

A device includes a non-volatile analog resistive memory cell. The non-volatile analog resistive memory device includes a resistive memory device and a select transistor. The resistive memory device includes a first terminal and a second terminal. The resistive memory device has a tunable conductance. The select transistor is a ferroelectric field-effect transistor (FeFET) device which includes a gate terminal, a source terminal, and a drain terminal. The gate terminal of the FeFET device is connected to a word line. The source terminal of the FeFET device is connected to a source line. The drain terminal of the FeFET device is connected to the first terminal of the resistive memory device. The second terminal of the resistive memory device is connected to a bit line.

ANALOG HARDWARE REALIZATION OF TRAINED NEURAL NETWORKS FOR VOICE CLARITY

Controlling voltage resistance through metal-oxide device

A voltage resistance controlling memristive apparatus has two electrodes. A first metal-oxide layer on the two electrodes, a second electrically conductive metal-oxide layer on the first layer, and a forming contact on the second layer connects the two electrodes. A computer system connected to the forming contact may apply a voltage to the layers and display an overall resistance increase. A computer implemented method identifies filamentary channels in the first metal-oxide layer using sensors, e.g. by determining flow of charged ions through the first layer over time. Parallel filamentary sections are identified. Enabling resistance tuning in identified filamentary sections may comprise transmitting instructions to receive charged ions through the filamentary channels or selectively trimming the resistance of the filamentary sections by applying a predetermined voltage. Applying a predetermined voltage laterally through the filamentary sections, via the filamentary channels, may be uniform ...

Efficient tile mapping for row-by-row convolutional neural network mapping for analog artificial intelligence network inference

Implementing a convolutional neural network (CNN) includes configuring a crosspoint array to implement a convolution layer in the CNN. Convolution kernels of the layer are stored in crosspoint devices of the array. Computations for the CNN are performed by iterating a set of operations for a predetermined number of times. The operations include transmitting voltage pulses corresponding to a subpart of a vector of input data to the crosspoint array. The voltage pulses generate electric currents that are representative of performing multiplication operations at the crosspoint device based on weight values stored at the crosspoint devices. A set of integrators accumulates an electric charge based on the output electric currents from the respective crosspoint devices. The crosspoint array outputs the accumulated charge after iterating for the predetermined number of times. The accumulated charge represents a multiply-add result of the vector of input data and the one or more convolution kernels ...

NEUROMORPHIC MEMORY CIRCUIT AND OPERATING METHOD THEROF

A neuromorphic memory circuit (200) includes a plurality of memory cells (210), and each of the plurality of memory cells (210) includes a first switching element (SW1) having a threshold switching time determined based on a voltage applied to both ends of the first switching element at a time of receiving an input signal (201), and outputting the input signal in response to an elapse of the threshold switching time from a point in time at which the input signal is received (202); a first resistive memory element (Rdelay) connected to the first switching element (SW1); and a synapse circuit (212) to generate an output signal in response to the input signal (201) delayed by the threshold switching time.

Method for designing an initialization function for programming a memory element

Behavior modeling using client-hosted neural networks

Apparatuses, systems, and techniques to detect abnormal behavior on clients using one or more neural networks on said clients. In at least one embodiment, use of or behavior on one or more clients is analyzed by a first neural network to detect abnormal behavior compared to a baseline of accepted behavior, and said baseline of accepted behavior is revised over time by a second neural network based on behavior observed on said one or more clients.

Neural apparatus for a neural network system

A neural apparatus (100) for a neural network system may be configured to receive one or more input signals during a decode time period (301), decode the one or more input signals during the decode time period (303), resulting in a decoded signal, and upon termination of the decode time period, process the decoded signal using internal neuron dynamics (305). The processed signal may be used to encode and emit one or more output signals in a subsequent decode time period (307) to another neural apparatus of the neural network system.

METHOD AND SYSTEM FOR ADAPTING PROGRAMS FOR INTEROPERABILITY AND ADAPTERS THEREFOR

The present invention discloses a bidirectional exchange standard adapter for enabling a given program to interoperate with a different program having another bidirectional exchange standard adapter, comprising: one or more hyper objects including one or more rules defining a two-way functional transform; the functional transform being a data conversion function of data structures and data formats for the given program and for an exchange standard; the one or more hyper objects defining rules for data reading and data writing for the given program; and whereby intercommunication with the another bidirectional exchange standard adapter is facilitated to provide interoperability between the given program and the different program.

Suppressing outlier drift coefficients while programming phase change memory synapses

A computer-implemented method for suppressing outlier drift of a phase change memory (PCM) device includes programming, by a controller, a conductance of the PCM device, wherein the programming includes configuring the conductance of the PCM device to a first conductance value at a first time-point, the first time-point being a programming time-point. The programming further includes determining, at a first pre-compensation time-point, that the conductance of the PCM device has changed to a second conductance value that differs from a target conductance value by no more than a predetermined threshold. Further, the programming includes, based on the above determination, reprogramming the PCM device to the first conductance value at a second time-point, including measuring said pre-compensation again, but at a second pre-compensation time-point.

DYNAMIC CONFIGURATION OF READOUT CIRCUITRY FOR DIFFERENT OPERATIONS IN ANALOG RESISTIVE CROSSBAR ARRAY

A device which comprises an array of resistive processing unit (RPU) cells, first control lines extending in a first direction across the array of RPU cells, and second control lines extending in a second direction across the array of RPU cells. Peripheral circuitry comprising readout circuitry is coupled to the first and second control lines. A control system generates control signals to control the peripheral circuitry to perform a first operation and a second operation on the array of RPU cells. The control signals include a first configuration control signal to configure the readout circuitry to have a first hardware configuration when the first operation is performed on the array of RPU cells, and a second configuration control signal to configure the readout circuitry to have a second hardware configuration, which is different from the first hardware configuration, when the second operation is performed on the array of RPU cells.

Controlling voltage resistance through metal-oxide device

Counter based resistive processing unit for programmable and reconfigurable artificial-neural-networks

Technical solutions are described for storing weight in a crosspoint device of a resistive processing unit (RPU) array. An example system includes a crosspoint array, wherein each array node represents a connection between neurons of the neural network, and wherein each node stores a weight assigned to the node. The crosspoint array includes a crosspoint device at each node. The crosspoint device includes a counter that has multiple single bit counters, and states of the counters represent the weight to be stored at the crosspoint device. Further, the crosspoint device includes a resistor device that has multiple resistive circuits, and each resistive circuit is associated with a respective counter from the counters. The resistive circuits are activated or deactivated according to a state of the associated counter, and an electrical conductance of the resistor device is adjusted based at least in part on the resistive circuits that are activated.

METHOD FOR THE ANALOGUE MULTIPLICATION AND/OR CALCULATION OF A SCALAR PRODUCT WITH A CIRCUIT ASSEMBLY, IN PARTICULAR FOR ARTIFICIAL NEURAL NETWORKS

Processing device based on magnetic tunnel junction (MTJ) element and electronic system including the processing device

Provided is a processing device having improved reliability and power consumption efficiency of analog calculations as well as high cost efficiency due to reduction in a size of a bit-cell, and an electronic system including the processing device. The processing device includes: at least one bit-cell line on which a plurality of bit-cells are connected to each other in series, wherein each of the bit-cells includes: a first magnetic tunnel junction (MTJ) element; a second MTJ element connected to the first MTJ element in parallel; a first switching element connected to the first MTJ element in series; and a second switching element connected to the second MTJ element in series, and wherein on the bit-cell line, two adjacent bit-cells are connected to each other in series in a mirroring structure.

Applications of back-end-of-line (BEOL) capacitors in compute-in-memory (CIM) circuits

An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes ...

Artificial neural networks

The present disclosure relates to a neuron for an artificial neural network. The neuron comprises a dot product engine operative to: receive a set of weights; receive a set of data inputs based on a set of input data signals; and calculate the dot product of the set of data inputs and the set of weights to generate a dot product engine output. The neuron further comprises an activation function module arranged to apply an activation function to a signal indicative of the dot product engine output to generate a neuron output; and gain control circuitry. The gain control circuitry is operative to control: an input gain applied to the input data signals to generate the set of data inputs; and an output gain applied to the dot product engine output or by the activation function module. The output gain is selected to compensate for the applied input gain.

CRESTED BARRIER DEVICE AND SYNAPTIC ELEMENT

Neural network circuits providing early integration before analog-to-digital conversion

Crossbar arrays for computations in memory-augmented neural networks

In a hardware-implemented approach for operating a neural network system, a neural network system is provided comprising a controller, a memory, and an interface connecting the controller to the memory, where the controller comprises a processing unit configured to execute a neural network and the memory comprises a neuromorphic memory device with a crossbar array structure that includes input lines and output lines interconnected at junctions via electronic devices. The electronic devices of the neuromorphic memory device are programmed to incrementally change states by coupling write signals into the input lines based on: write instructions received from the controller and write vectors generated by the interface. Data is retrieved from the neuromorphic memory device, according to a multiply-accumulate operation, by coupling read signals into one or more of the input lines of the neuromorphic memory device based on: read instructions from the controller and read vectors generated by the ...

ARTIFICIAL NEURAL NETWORKS

The present disclosure relates to a neuron for an artificial neural network. The neuron includes: a first dot product engine operative to: receive a first set of weights; receive a set of inputs; and calculate the dot product of the set of inputs and the first set of weights to generate a first dot product engine output. The neuron further includes a second dot product engine operative to: receive a second set of weights; receive an input based on the first dot product engine output; and generate a second dot product engine output based on the product of the first dot product engine output and a weight of the second set of weights. The neuron further includes an activation function module arranged to generate a neuron output based on the second dot product engine output. The first dot product engine and the second dot product engine are structurally or functionally different.

METHOD AND APPARATUS FOR COMPARING A CURRENT OF A SELECTED CELL

A circuit for comparing current drawn by a selected memory cell (2908) for a vector-matrix-multiplier with a reference current corresponding to a current drawn by a reference matrix (2906), the circuit comprising: a first node; a first switch (2903); a second switch (2904); a transistor (2901) for comparing the current drawn by the selected memory cell and received from a the first node with a the reference current, wherein the circuit is configured such that : -in a first time period, the first node is coupled to the reference matrix (2906) by the first switch in order for the transistor to hold the reference current and -in a second time period, following the first time period, the first node is coupled to the selected memory cell in order for the transistor to compare the held reference current with the current drawn by the selected memory cell.

Compensating PCM drift for neuromorphic applications

An apparatus includes an analog phase change memory array, including an array of cells addressable and accessible through first lines and second lines. The apparatus includes device(s) coupled to one or more of the first lines. The device(s) is/are able to be coupled to or decoupled from the one or more first lines to compensate for phase change memory resistance drift in resistance of at least one of the cells in the one or more first lines. The apparatus may also include control circuitry configured to send, using the first lines and second lines, a same set pulse through the device(s) to multiple individual phase change memory resistors in the phase change memory array sequentially once every period.

Electrical memristive devices based on bilayer arrangements

An electrical memristive device has a layer structure. The later structure comprises two electrodes and a bilayer material arrangement that connects the two electrodes. The bilayer material arrangement may, for example, be sandwiched by the two electrodes, in direct contact therewith. The bilayer material arrangement includes an HfOy layer, where 1.3 ± 0.1 ≤ y < 1.9 ± 0.1, as well as a WOx layer in direct contact with the HfOy layer, where 2.5 ± 0.1 ≤ x < 2.9 ± 0.1. The bilayer arrangement involves sub-stoichiometric layers of HfOy and WOx, where the WOx layer may advantageously have a polycrystalline structure in the monoclinic phase, while the HfOy layer is preferably amorphous.

ARRANGEMENT AND METHOD FOR PERFORMING A VECTOR-MATRIX MULTIPLICATION BY MEANS OF CAPACITIVE OR RESISTIVE SYNAPTIC COMPONENTS

PRECISION TUNING OF A PAGE OR WORD OF NON-VOLATILE MEMORY CELLS AND ASSOCIATED HIGH VOLTAGE CIRCUITS FOR AN ANALOG NEURAL MEMORY ARRAY IN AN ARTIFICIAL NEURAL NETWORK

SYSTEMS AND METHODS FOR MIXED-SIGNAL COMPUTING

Computing devices containing magnetic Josephson Junctions with embedded magnetic field control element

A within-chip magnetic field control device is formed in proximity to a Josephson Junction (JJ) structure. The within-chip magnetic field control device includes wiring structures that are located laterally adjacent to the JJ structure. In some embodiments, the magnetic field control device also includes, in addition to the wiring structures, a conductive plate that is connected to the wiring structures and is located beneath the JJ structure. Use of electrical current through the wiring structures induces, either directly or indirectly, a magnetic field into the JJ structure. The strength of the field can be modulated by the amount of current passing through the wiring structures. The magnetic field can be turned off as needed by ceasing to allow current to flow through the wiring structures.

Method for designing an initialization function for programming a memory element

A storage device comprising a memory element which comprises a changeable physical quantity for storing information, the physical quantity in a drifted state. The memory element being configured for setting the physical quantity to an initial state. The physical quantity of the memory element drifts from the initial state to the drifted state. The initial state of the physical quantity is computable by means of an initialization function, which depends on a target state of the physical quantity and the target state of the physical quantity is approximately equal to the drifted state of the physical quantity. An integrated circuit may further comprise an assembly of memory elements and further comprise a neuromorphic neuron apparatus for simulating a layer of a neural network. Other aspects refer to computer implemented methods for (i) setting up a storage device comprising a memory element or (ii) designing an initialization function. Initialization function may be f(G)=a*e-b*G+c where ...

Projected memory device with carbon-based projection component

A projected memory device (1) includes a carbon-based projection component (20). The device (1) includes two electrodes (32, 34), a memory segment (10), and a projection component (20). The projection component (20) and the memory segment (10) form a dual element that connects the two electrodes (32, 34). The projection component (20) extends parallel to and in contact with the memory segment (10). The memory segment (10) includes a resistive memory material, while the projection component (20) includes a thin film of non-insulating material that essentially comprises carbon. In a particular implementation, the non-insulating material and the projection component (20) essentially comprise amorphous carbon. Using carbon and, in particular, amorphous carbon, as a main component of the projection component (20), allows unprecedented flexibility to be achieved when tuning the electrical resistance of the projection component (20).

Neuromorphic device with crossbar array structure

Neuromorphic methods, systems and devices (10, 11, 12) are provided. The embodiment may include a neuromorphic device (10, 11, 12) which may comprise a crossbar array structure (110) and an analog circuit. The crossbar array structure (110) may include N input lines (111, 112) and M output lines (120) interconnected at junctions via N x M electronic devices (131, 132, 32a, 132b, 132c), which, in preferred embodiments, include, each, a memristive device. The input lines (111, 112) may comprise N 1 first input lines (111) and N 2 second input lines (112). The first input lines (111) may be connected to the M output lines (120) via N 1 x M first devices (131, 132) of said electronic devices (131, 132). Similarly, the second input lines (112) may be connected to the M output lines (120) via N 2 x M second devices (132) of said electronic devices (131, 132). The analog circuit (140, 150, 160, 170) may be configured to program the electronic devices (131, 132) so as for the first devices (131 ...

Crossbar arrays

A crossbar array device having electrolyte-gated transistors (EGTs) sharing an electrolyte, 9. Each electrolyte-gated transistor has top, 3, and bottom electrodes, 2, and an active channel region 7 (semiconductor, e.g. PEDOT:PSS or P3HT) wherein the semiconductor is located in an opening (window 6, figs 9, 10A) of an insulating layer 5 formed over the electrodes. The electrolyte is located within a common volume 8. The top, 3, and bottom, 2, electrodes are separated by an insulating region 4. The electrodes 2 and 3 are deposited in a crossbar configuration (fig 9). The semiconductor channels may be separated from the common volume by a selective membrane. A gel or solid electrolyte may fill the common volume sufficiently to contact every active channel region (semiconductor region). Gating of EGTs may be provided by one or more gate electrodes 10 which are positioned in electrical contact with electrolyte 9 received within the common volume 8. The EGT may be an organic electrochemical transistor ...

Arithmetic apparatus, multiply-accumulate system, and setting method

An arithmetic apparatus includes input lines and multiply-accumulate devices. An electrical signal for an input value is input into each of the input lines within a predetermined input period. Multiplication units include a positive weight multiplication unit that generates a positive weight charge for a product value obtained by multiplying the input value by a positive weight value and/or a negative weight multiplication unit that generates a negative weight charge for a product value obtained by multiplying the input value by a negative weight value. They are configured such that a positive weight ratio that is a ratio of a sum total of the positive weight values to a sum total of absolute values of the weight values is any ratio of 0% to 100%. An output unit of the multiply-accumulate device accumulates the generated weight charges to output a multiply-accumulate signal representing a sum of the product values.

Differential mixed signal multiplier with three capacitors

A differential mixed-signal logic processor is provided．The differential mixed-signal logic processor includes a plurality of mixed-signal multiplier branches for multiplication of an analog value A and a N-bit digital value B．Each of plurality of mixed-signal multiplier branches include a first capacitor connected across a second capacitor and a third capacitor to provide a differential output across the second and third capacitors．A capacitance of the first capacitor is equal to half a capacitance of the second and third capacitors． ...

Capacitive processing unit

A structure of a memory device is described. The structure can include an array of memory cells. A memory cell can include at least one metal-oxide-semiconductor (MOS) element, where a source terminal of the at least one MOS element is connected to a drain terminal of the MOS element. The source terminal being connected to the drain terminal can cause the at least one MOS element to exhibit capacitive behavior for storing electrical energy. A first transistor can be connected to the at least one MOS element, where an activation of the first transistor can facilitate a write operation to the memory cell. A second transistor can be connected to the at least one MOS element, where an activation of the second transistor can facilitate a read operation from the memory cell.

Neural network circuits providing early integration before analog-to-digital conversion

Neural network circuits providing early integration before ADC are described. Comparators are adapted to compare a plurality of output analog voltages from a first synaptic array to a predetermined threshold to generate a vector of bits indicating whether the plurality of analog voltages exceed the predetermined threshold, and transmit the vector of bits via a network. At least one ADC is configured to convert the plurality of analog voltages to a vector of digital values, and transmit the vector of digital values via the network. At least one modulator is configured to receive the vector of bits from the network, provide pulses to each of a plurality of input wires of a second synaptic array based on the vector of bits, receive the vector of digital values from the network, and provide pulses to each of the plurality of input wires based on the vector of digital values.

Bias scheme for single-device synaptic element

A neuromorphic synapse array includes a plurality of synaptic array cells being connected by circuitry such that the synaptic array cells are assigned to rows and columns of an array, the synaptic array cells respectively having a single polarity synapse weight, the rows respectively connected to respective input ends of the synaptic array cells, the columns respectively connected to respective output ends of the synaptic array cells, the synaptic array cells aligned in a column of the array being defined as operation column arrays and an array of current mirrors, each current mirror exhibiting a mirror ratio of N: 1, wherein N is a number of columns of the synaptic array cells, respectively connected to the respective rows such that weights corresponding to all of the current mirrors are set to average weights of all of the synaptic array cells that are updated during a learning phase.

Using ferroelectric field-effect transistors (FeFETs) as capacitive processing units for in-memory computing

An electronic circuit includes a plurality of word lines; a plurality of bit lines (703-1, 703-2) intersecting said plurality of word lines (701-1, 701-2) at a plurality of grid points; and a plurality of in-memory processing cells located at said plurality of grid points. Each of said in-memory processing cells includes a first switch having a first terminal coupled to a corresponding one of said word lines and a second terminal; a second switch having a first terminal coupled to said second terminal of said first switch and a second terminal coupled to a corresponding one of said bit lines; and a non-volatile tunable capacitor having one electrode coupled to said second terminal of said first switch and said first terminal of said switch, and having another electrode coupled to ground.

Imaging device, imaging module, electronic device, and imaging system

An imaging device connected to a neural network is provided. An imaging device having a neuron in a neural network includes a plurality of first pixels, a first circuit, a second circuit, and a third circuit. Each of the plurality of first pixels includes a photoelectric conversion element. The plurality of first pixels is electrically connected to the first circuit. The first circuit is electrically connected to the second circuit. The second circuit is electrically connected to the third circuit. Each of the plurality of first pixels generates an input signal of the neuron. The first circuit, the second circuit, and the third circuit function as the neuron. The third circuit includes an interface connected to the neural network.

ADJUSTABLE PROGRAMMING CIRCUIT FOR NEURAL NETWORK

Examples of programming circuits and methods are provided. In one example, an adjustable programming circuit comprises a first adjustable voltage divider; a second adjustable voltage divider; a first operational amplifier, wherein an output terminal of the first operational amplifier provides a first programming voltage; and a second operational amplifier, wherein the first input terminal of the second operational amplifier is coupled to the output terminal of the second operational amplifier and the first input terminal of the second operational amplifier is coupled to the second output terminal of the first adjustable voltage divider.

A NEURO-SYNAPTIC SYSTEM FOR REAL TIME PROCESSING OF TRADING DATA AND ASSOCIATED COMPUTER PROGRAM

This neuro-synaptic system (1) for real time processing of trading data of a financial asset to automatically generate trading recommendations on said financial asset, is characterised in that it comprises one or more circuits, each circuit comprising at least one sub-circuit (2), said sub-circuit comprises: a synaptic unit (22) which is a high-pass filter to generate a filtered signal that extracts the fluctuations of the trading data around a slowly varying part; and a neuronal unit (26) modelling a spiking neuron excited by the filtered signal to generate an output signal comprising spikes, each spike corresponding to a trading order.

Neuromorphic device with crossbar array structure

Matrix Sketching using analog crossbar architectures

A computer-implemented method is presented for performing matrix sketching by employing an analog crossbar architecture. The method includes low rank updating a first matrix for a first period of time, copying the first matrix into a dynamic correction computing device, switching to a second matrix to low rank update the second matrix for a second period of time, as the second matrix is low rank updated, feeding the first matrix with first stochastic pulses to reset the first matrix back to a first matrix symmetry point, copying the second matrix into the dynamic correction computing device, switching back to the first matrix to low rank update the first matrix for a third period of time, and as the first matrix is low rank updated, feeding the second matrix with second stochastic pulses to reset the second matrix back to a second matrix symmetry point.

Drift regularization to counteract variation in drift coefficients for analog accelerators

A drift regularization is provided to counteract variation in drift coefficients in analog neural networks. A method of training an artificial neural network is illustrated. A plurality of weights is randomly initialized. Each of the plurality of weights corresponds to a synapse of an artificial neural network. At least one array of inputs is inputted to the artificial neural network. At least one array of outputs is determined by the artificial neural network based on the at least one array of inputs and the plurality of weights. The at least one array of outputs is compared to ground truth data to determine a first loss. A second loss is determined by adding a drift regularization to the first loss. The drift regularization is positively correlated to variance of the at least one array of outputs. The plurality of weights is updated based on the second loss by backpropagation.

Training of oscillatory neural networks

The network comprises at least one network layer in which a plurality of electronic oscillators, interconnected via programmable coupling elements storing respective network weights, generate oscillatory signals at time delays dependent on the input signal to propagate the input signal from an input to an output of that layer. The network is adapted to provide a network output signal dependent substantially linearly on phase of oscillatory signals in the last layer of the network. The method includes calculating a network error dependent on the output signal and a desired output for the training sample, and calculating updates for respective network weights by backpropagation of the error such that weight-updates for a network layer are dependent on a vector of time delays at the input to that layer and the calculated error at the output of that layer.

Resistive switching memory cell

A resistive random access memory (ReRAM) device is provided. The ReRAM device includes a first electrode, a first resistive structure in contact with the first electrode, a dielectric layer in contact with the first resistive structure, and a second resistive structure in contact with the dielectric layer. The second resistive structure includes a resistive material layer and a high work function metal core. The ReRAM device also includes a second electrode in contact with the second resistive structure.

Worst case noise and bound management for RPU crossbar arrays

Techniques for noise and bound management for DNN training on RPU crossbar arrays using a scaling factor based on a worst-case scenario are provided. A method for noise and bound management includes: obtaining input vector values x for an analog crossbar array of RPU devices, wherein a weight matrix is mapped to the analog crossbar array of RPU devices; and scaling the input vector values x based on a worst-case scenario to provide scaled input vector values x'to use as input to the analog crossbar array of RPU devices, wherein the worst-case scenario includes an assumed maximal weight of the weight matrix multiplied by a sum of absolute values from the input vector values x.

Physical implementation of artificial neural networks

Synapse system and synapse method to realize STDP operation

A synapse system is provided which includes three transistors and a resistance-switching element arranged between two neurons. The resistance-switching element has a resistance value and it is arranged between two neurons. A first transistor is connected between the resistance-switching element and one of the neurons. A second transistor and a third transistor are arranged between the two neurons, and are connected in series which interconnects with the gate of the first transistor. A first input signal is transmitted from one of the neurons to the other neuron through the first transistor. A second input signal is transmitted from one of the neurons to the other neuron through the second transistor and the third transistor. The resistance value of the resistance-switching element is changed based on the time difference between the first input signal and the second input signal.

ANALOG NEURAL MEMORY ARRAY IN ARTIFICIAL NEURAL NETWORK COMPRISING LOGICAL CELLS AND IMPROVED PROGRAMMING MECHANISM

SWITCHED ARTIFICIAL SYNAPSE

PRECISE DATA TUNING METHOD AND APPARATUS FOR ANALOG NEURAL MEMORY IN AN ARTIFICIAL NEURAL NETWORK

NEURONS AND SYNAPSES HAVING FERROELECTRICALLY MODULATED METAL-SEMICONDUCTOR SCHOTTKY DIODES, AND METHOD

Using ferroelectric field-effect transistors (FeFETs) as capacitive processing units for in-memory computing

An electronic circuit includes a plurality of word lines; a plurality of bit lines intersecting said plurality of word lines at a plurality of grid points; and a plurality of in-memory processing cells located at said plurality of grid points. Each of said in-memory processing cells includes a first switch having a first terminal coupled to a corresponding one of said word lines and a second terminal; a second switch having a first terminal coupled to said second terminal of said first switch and a second terminal coupled to a corresponding one of said bit lines; and a non-volatile tunable capacitor having one electrode coupled to said second terminal of said first switch and said first terminal of said switch, and having another electrode coupled to ground.

NEUROMORPHIC OPERATIONS USING POSITS

Systems, apparatuses, and methods related to a neuron built with posits are described. An example system may include a memory device and the memory device may include a plurality of memory cells. The plurality of memory cells can store data including a bit string in an analog format. A neuromorphic operation can be performed on the data in the analog format. The example system may include an analog to digital converter coupled to the memory device. The analog to digital converter may convert the bit string in the analog format stored in at least one of the plurality of memory cells to a format that supports arithmetic operations to a particular level of precision.

Analog neural network systems

The present disclosure relates to a neural network system comprising: a data input configured to receive an input data signal and analog neural network circuitry having an input coupled with the data input. The analog neural network circuitry is operative to apply a weight to a signal received at its input to generate a weighted output signal. The neural network system further comprises compensation circuitry configured to apply a compensating term to the input data signal to compensate for error in the analog neural network circuitry.

Circuit methodology for highly linear and symmetric resistive processing unit

A processing unit, including a first circuit, and a first circuit element connected to the first circuit. The first circuit element is at least charged by the first circuit.

LITHOGRAPHIC MEMRISTIVE ARRAY

MULTIPLY-ACCUMULATE OPERATION DEVICE

SYSTEM FOR CONVERTING NEURON CURRENT INTO NEURON CURRENT-BASED TIME PULSES IN AN ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK

Numerous embodiments are disclosed for converting neuron current output by a vector-by-matrix multiplication (VMM) array into neuron current-based time pulses and providing such pulses as an input to another VMM array within an artificial neural network. Numerous embodiments are disclosed for converting the neuron current-based time pulses into analog current or voltage values if an analog input is needed for the VMM array.

Bipolar all-memristor circuit for in-memory computing

A circuit for performing energy-efficient and high-throughput multiply-accumulate (MAC) arithmetic dot-product operations and convolution computations includes a two dimensional crossbar array comprising a plurality of row inputs and at least one column having a plurality of column circuits, wherein each column circuit is coupled to a respective row input. Each respective column circuit includes an excitatory memristor neuron circuit having an input coupled to a respective row input, a first synapse circuit coupled to an output of the excitatory memristor neuron circuit, the first synapse circuit having a first output, an inhibitory memristor neuron circuit having an input coupled to the respective row input, and a second synapse circuit coupled to an output of the inhibitory memristor neuron circuit, the second synapse circuit having a second output. An output memristor neuron circuit is coupled to the first output and second output of each column circuit and has an output.

METHODS AND SYSTEMS OF OPERATING A NEURAL CIRCUIT IN A NON-VOLATILE MEMORY BASED NEURAL-ARRAY

In one aspect, a method of a neuron circuit includes the step of providing a plurality of 2N−1 single-level-cell (SLC) flash cells for each synapse (Yi) connected to a bit line forming a neuron. The method includes the step of providing an input vector (Xi) for each synapse Yiwherein each input vector is translated into an equivalent electrical signal ESi(current IDACi, pulse TPULSEi, etc). The method includes the step of providing an input current to each synapse sub-circuit varying from 20*ESito (2N−1)*ESi. The method includes the step of providing a set of weight vectors or synapse (Yi), wherein each weight vector is translated into an equivalent threshold voltage level or resistance level to be stored in one of many non-volatile memory cells assigned to each synapse (Yi). The method includes the step of providing for 2Npossible threshold voltage levels or resistance levels in the 2N−1 non-volatile memory cells of each synapse, wherein each cell is configured to store one of the two ...

IMAGING DEVICE, IMAGING MODULE, ELECTRONIC DEVICE, AND IMAGING SYSTEM

An imaging device connected to a neural network is provided. An imaging device having a neuron in a neural network includes a plurality of first pixels, a first circuit, a second circuit, and a third circuit. Each of the plurality of first pixels includes a photoelectric conversion element. The plurality of first pixels is electrically connected to the first circuit. The first circuit is electrically connected to the second circuit. The second circuit is electrically connected to the third circuit. Each of the plurality of first pixels generates an input signal of the neuron. The first circuit, the second circuit, and the third circuit function as the neuron. The third circuit includes an interface connected to the neural network.

IN-MEMORY COMPUTATION CIRCUIT USING STATIC RANDOM ACCESS MEMORY (SRAM) ARRAY SEGMENTATION AND LOCAL COMPUTE TILE READ BASED ON WEIGHTED CURRENT

An in-memory computation circuit includes a memory array including sub-arrays of with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit selectively actuates word lines across the sub-arrays for an in-memory compute operation. A computation tile circuit for each sub-array includes a column compute circuit for each bit line. Each column compute circuit includes a switched timing circuit that is actuated in response to weight data on the bit line for a duration of time set by an in-memory compute operation enable signal. A current digital-to-analog converter powered by the switched timing circuit operates to generate a drain current having a magnitude controlled by bits of feature data for the in-memory compute operation. The drain current is integrated to generate an output voltage.

Data transfer with continuous weighted PPM duration signal

A computer-implemented method for processing signals is provided including advantageously generating a temporally continuous weighted pulse position modulation (CW PPM) duration signal from an input analog signal, converting the CW PPM duration signal to a memory access signal, executing a multiply and accumulate (MAC) operation with the memory access signal, and advantageously generating the input analog signal from a result of the MAC operation by an activation function (AF).

MACHINE LEARNING ACCELERATOR

ALGORITHMS AND CIRCUITRY FOR VERIFYING A VALUE STORED DURING A PROGRAMMING OPERATION OF A NON-VOLATILE MEMORY CELL IN AN ANALOG NEURAL MEMORY IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK

PROGRAMMABLE NEURON FOR ANALOG NON-VOLATILE MEMORY IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK

Configurable in memory computing engine, platform, bit cells and layouts therefore

Various embodiments comprise systems, methods, architectures, mechanisms or apparatus for providing programmable or pre-programmed in-memory computing operations.

SPARSE MODIFIABLE BIT LENGTH DETERMINSTIC PULSE GENERATION FOR UPDATING ANALOG CROSSBAR ARRAYS

ANALOG-DIGITAL HYBRID COMPUTING METHOD AND NEUROMORPHIC SYSTEM USING THE SAME

A neuromorphic system according to an embodiment of the invention includes an input signal section that generates an input signal, a synapse section that includes a plurality of synaptic units that receive the input signal and makes a current to flow according to a set weight, each of the plurality of synaptic units including a plurality of non-volatile memory cells capable of selectively storing a logical state, the non-volatile memory cells being arranged in a memory array that include input electrode lines and output electrode lines crossing each other, and generates an output signal for each output electrode line by the input signal, a digital calculation section that digitizes the output signal generated for each output electrode line and calculates a sum of the digitized output signals, and a controller section that controls the input signal section, the synapse section, and the digital calculation section, and the controller section designates the number of digitized digits for each ...

NEURAL NETWORK ENGINE WITH ASSOCIATED MEMORY ARRAY

In-memory data pooling for machine learning

A method comprises a first block of memory cells to store an input array, and a second block of memory cells. Pooling circuitry is operatively coupled to the first block of memory cells to execute in-place pooling according to a function over the input array to generate an array of output values. Writing circuitry is operatively coupled to the second block to store the array of output values in the second block of memory cells. Analog sensing circuitry is coupled to the first block of memory cells to generate analog values for the input array, wherein the pooling circuitry receives the analog values as inputs to the function. The writing circuitry operatively coupled to the second block is configured to store an analog level in each cell of the second block for the array of output values.

Distributed, event-based computation using neuromorphic cores

Systems for distributed, event-based computation are provided. In various embodiments, the systems include a plurality of neurosynaptic processors and a network interconnecting the plurality of neurosynaptic processors. Each neurosynaptic processor includes a clock uncoupled from the clock of each other neurosynaptic processor. Each neurosynaptic processor is adapted to receive an input stream, the input stream comprising a plurality of inputs and a clock value associated with each of the plurality of inputs. Each neurosynaptic processor is adapted to compute, for each clock value, an output based on the inputs associated with that clock value. Each neurosynaptic processor is adapted to send to another of the plurality of neurosynaptic processors, via the network, the output and an associated clock value.

Scalable excitatory and inhibitory neuron circuitry based on vanadium dioxide relaxation oscillators

A neuron circuit, comprising first and second NDR devices biased each with opposite polarities, said first and second NDR devices being coupled to first and second grounded capacitors.

ANALOG LEARNING ENGINE AND METHOD

A neural network learning mechanism has a device which perturbs analog neurons to measure an error which results from perturbations at different points within the neural network and modifies weights and biases to converge to a target.

COMPENSATION FOR REFERENCE TRANSISTORS AND MEMORY CELLS IN ANALOG NEURO MEMORY IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK

Numerous embodiments are disclosed for compensating for differences in the slope of the current-voltage characteristic curve among reference transistors, reference memory cells, and flash memory cells during a read operation in an analog neural memory in a deep learning artificial neural network. The embodiments are able to compensate for slope differences during both sub-threshold and linear operation of reference transistors.

NEUROMORPHIC DEVICE

A neuromorphic device (700) includes a plurality of cell tiles (TL), each of the plurality of cell tiles including a cell array including a plurality of memory cells storing weights of a neural network, a row driver connected to the plurality of memory cells through a plurality of row lines, and cell analog-digital converters (ADCs) connected to the plurality of memory cells through a plurality of column lines, and a controller (740) configured to select, form the plurality of cell tiles (TL), a plurality of valid cell tiles storing the weights, execute a neural network-based arithmetic operation based on the plurality of valid cell tiles, and redundantly store weights of a first layer among a plurality of layers included in the neural network in a plurality of first valid cell tiles that are divided into a plurality of first tile groups (711A, 711B).

RECURRENT NEURAL NETWORK AND RECURRENT NEURAL NETWORK DEVICE AND METHOD FOR TRAINING A RECURRENT NEURAL NETWORK

A recurrent neural network is disclosed, which comprises a plurality of n damped harmonic oscillators (DHOi), each of the n damped harmonic oscillators being one cell (nci) of the neural network, an input unit (IU) adapted for receiving and inputting time-series input data (S (t)), a recurrent connection unit (RCU) comprising, for each of the cells (nci), at least one connection (wi,j) between the input/output node (IOi) of the corresponding cell (nci) and the input/output node (IOj) of at least another one of the cells (ncj) for transmitting the resulting damped harmonic oscillation (hi) output from the input/output node of the corresponding cell (nci) to the input/output node of the another one of the cells (ncj).

Artificial neuron for neuromorphic chip with resistive synapses

An artificial neuron for a neuromorphic chip comprises a synapse with resistive memory representative of a synaptic weight. The artificial neuron comprises a read circuit, an integration circuit and a logic circuit interposed between the read circuit and the integration circuit. The read circuit is configured to impose on the synapse a read voltage independent of the membrane voltage and to provide an analogue value representative of the synaptic weight. The logic circuit is configured to generate from the analogue value a pulse having a duration. The integration circuit comprises an accumulator of synaptic weights at the terminals of which a membrane voltage is established and a comparator configured to emit a postsynaptic pulse if a threshold is exceeded by the membrane voltage. Moreover, it comprises a source of current controlled by the pulse to inject a current into the accumulator of synaptic weights during this duration.

Convolutional neural network on-chip learning system based on non-volatile memory

Disclosed by the disclosure is a convolutional neural network on-chip learning system based on non-volatile memory, comprising: an input module, a convolutional neural network module, an output module and a weight update module. The on-chip learning of the convolutional neural network module implements the synaptic function by using the characteristic of the memristor, and the convolutional kernel value or synaptic weight value is stored in a memristor unit; the input module converts the input signal into the voltage signal; the convolutional neural network module converts the input voltage signal layer-by-layer, and transmits the result to the output module to obtain the output of the network; and the weight update module adjusts the conductance value of the memristor in the convolutional neural network module according to the result of the output module to update the network convolutional kernel value or synaptic weight value.

A SOMA CIRCUIT

A SPIN HALL ISING MACHINE AND METHOD FOR OPERATING SUCH

SPLIT ARRAY ARCHITECTURE FOR ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK

Numerous embodiments are disclosed for splitting a physical array into multiple arrays for separate vector-by-matrix multiplication (VMM) operations. In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns; and a plurality of sets of output lines, where each column contains a set of output lines; wherein each row is coupled to only one output line in the set of output lines for each column.

DIGITAL OUTPUT MECHANISMS FOR ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK

METHOD AND APPARATUS FOR CONVOLUTION OPERATION OF CONVOLUTIONAL NEURAL NETWORK

The present disclosure discloses a method and apparatus for convolution operation of a convolutional neural network. The method comprises acquiring input voltages used for characterizing pixel values; when the input voltages are scanned through convolutional sliding windows, obtaining times of reusing of the input voltages in the convolutional sliding windows; grouping the input voltages based on a difference in the times of reusing of the input voltages; extracting the input voltages in same groups once and performing convolution calculation with convolution kernels respectively, to obtain a result corresponding to each group; obtaining a result of convolution operation based on the result corresponding to each group, to implement convolution operation in the convolutional neural network. The present disclosure reduces energy consumption during convolution operations effectively.

AI CHIP

An artificial intelligence (AI) chip includes: a plurality of memory dies each for storing data; a plurality of computing dies each of which performs a computation included in an AI process; and a system chip that controls the plurality of memory dies and the plurality of computing dies. Each of the plurality of memory dies has a first layout pattern. Each of the plurality of computing dies has a second layout pattern. A second memory die which is one of the plurality of memory dies is stacked above the first layout pattern of a first memory die which is one of the plurality of memory dies. A second computing die which is one of the plurality of computing dies is stacked above the second layout pattern of a first computing die which is one of the plurality of computing dies.

FEFET UNIT CELLS FOR NEUROMORPHIC COMPUTING

MATCHED FEEDBACK INTEGRATE-AND-FIRE NEURON CIRCUIT

The present invention relates to an integrate-and-fire neuron circuit for signed processing which is characterized by a feedback subcircuit connected to the positive and negative outputs of the circuit. This feedback subcircuit is configured to generate and output positive charge packets to a common line of the neuron circuit on each negative spike output signal and stored weights and to generate and output negative charge packets to the common line based on each positive spike output signal and stored weights. Due to this feedback circuit that is build in the same way as the input weighting circuit, structural matching and therefore higher accuracy and less variation of the behavior over PVT variations is achieved.

Methods and systems for memristor-based neuron circuits

Certain embodiments of the present disclosure support techniques for designing neuron circuits based on memristors. Bulky capacitors as electrical current integrators can be eliminated and nanometer scale memristors can be utilized instead. Using the nanometer feature-sized memristors, the neuron hardware area can be substantially reduced.

Systems and methods for modeling binary synapses

Methods and system for modeling the behavior of binary synapses are provided. In one aspect, a method of modeling synaptic behavior includes receiving an analog input signal and transforming the analog input signal into an N-bit codeword, wherein each bit of the N-bit codeword is represented by an electronic pulse ( 1001 ). The method includes loading the N-bit codeword into a circular shift register ( 1002 ) and sending each bit of the N-bit codeword through one of N switches. Each switch applies a corresponding weight to the bit to produce a weighted bit. A signal corresponding to a summation of the weighted bits is output and represents a synaptic transfer function characterization of a binary synapse ( 1009 ).

Stochastic Memristive Devices Based on Arrays of Magnetic Tunnel Junctions

Embodiments of a Stochastic memristive array (SMA) device based on arrays of voltage-controlled magnetic tunnel junctions (MTJs) are disclosed. The SMA device is based on an array of stochastic (low energy barrier) magnetic tunnel junctions that are connected in parallel which simultaneously exhibits features that include (i) stochasticity and (ii) memristive behavior. The energy barrier of the MJTs may be tuned by an applied voltage (electric field). SMA devices may find applications in emerging computing concepts such as probabilistic computing and memcomputing, among others, providing a pathway towards intelligent hybrid CMOS-spintronic systems.

Altering a targeted brain therapeutic based on a brain circuit model

Techniques that facilitate altering a targeted brain therapeutic are provided. In one example, a system determines parameter data associated with a circuit model of a biological brain. The system also simulates the circuit model based on the parameter data to generate treatment data associated with the biological brain.

Framework for optimization of machine learning architectures

The present disclosure is related to framework for automatically and efficiently finding machine learning (ML) architectures that are optimized to one or more specified performance metrics and/or hardware platforms. This framework provides ML architectures that are applicable to specified ML domains and are optimized for specified hardware platforms in significantly less time than could be done manually and in less time than existing ML model searching techniques. Furthermore, a user interface is provided that allows a user to search for different ML architectures based on modified search parameters, such as different hardware platform aspects and/or performance metrics. Other embodiments may be described and/or claimed.

Techniques for adapting neural networks to devices

A training system for training a machine learning model such as a neural network may have a different configuration and/or hardware components than a target device that employs the trained neural network. For example, the training system may use a higher precision format to represent neural network parameters than the target device. In another example, the target device may use analog and digital processing hardware to compute an output of the neural network whereas the training system may have used only digital processing hardware to train the neural network. The difference in configuration and/or hardware components of the target device may introduce quantization error into parameters of the neural network, and thus affect performance of the neural network on the target device. Described herein is a training system that trains a neural network for use on a target device that reduces loss in performance resulting from quantization error.

Memristive neuromorphic circuit and method for training the memristive neuromorphic circuit

A neural network is implemented as a memristive neuromorphic circuit that includes a neuron circuit and a memristive device connected to the neuron circuit. A conductance balanced voltage pair is provided for the memristive device, where the conductance balanced voltage pair includes a set voltage for increasing the conductance of the memristive device and a reset voltage for decreasing the conductance of the memristive device. Either the set voltage and reset voltage, when applied to the memristive device, effects a substantially same magnitude conductance change in the memristive device over a predetermined range of conductance of the memristive device. The provided voltage pair is stored as a conductance balanced map. A training voltage based on the conductance balanced map is applied to the memristive device to train the neural network.

Incorporating rules into complex automated decision making

A set of input conditions is obtained. A plurality of potential decisions is obtained based at least in part on the set of input conditions. A rule-based system is used to process the plurality of potential decisions and obtain a set of one or more updated potential decisions, wherein: the rule-based system specifies a plurality of rules; a rule specifies a rule condition and a corresponding action, wherein when the rule condition is met, the corresponding action is to be performed; and using the rule-based system to process the plurality of potential decisions includes: for a selected potential decision in the plurality of potential decisions, determining whether the rule condition is met for a selected rule among the plurality of rules, wherein the selected rule condition is dependent on, at least in part, the selected potential decision; and in response to the selected rule condition being met, performing the corresponding action. The set of one or more updated potential decisions to be executed is output.

Non-volatile (nv) memory (nvm) matrix circuits employing nvm matrix circuits for performing matrix computations

Non-volatile (NV) memory (NVM) matrix circuits employing NVM circuits for performing matrix computations are disclosed. In exemplary aspects disclosed herein, an NVM matrix circuit is provided that has a plurality of NVM storage string circuits each comprising a plurality of NVM bit cell circuits each configured to store a memory state. Each NVM bit cell circuit has a stored memory state represented by a resistance, and includes a transistor whose gate node is coupled to a word line among a plurality of word lines configured to receive an input vector of 1×m size for example. Activation of the gate of a given NVM bit cell circuit controls whether its resistance is contributed to a respective source line. This causes a summation current to be generated on each source line based on the weighted summed contribution of each NVM bit cell circuit's resistance to its respective source line.

Disposable laser/flash anneal absorber for embedded neuromorphic memory device fabrication

A conformal disposable absorber is disclosed which is capable of providing efficient heat transfer to an embedded memory device during a localized absorber anneal, without adversary impacting the back-end-of-the-line (BEOL) structure. The disposable absorber is composed of an amorphous carbonitride material that can be designed to have a low reflection coefficient for laser/flash illumination, and a high extinction coefficient for efficient laser/flash illumination absorption. The disposable absorber is formed at a temperature of 400° C. or less.

Ferrules for fiber optic connectors

A ferrule for a fiber optic connector includes: a main body extending from a first end to a second end, the main body defining a bore extending from the first end to the second end; an end surface at the second end of the main body; and a raised portion on the end surface, the raised portion extending from the second end and surrounding the bore; wherein an optical fiber is configured to be positioned within the bore of the main body; and wherein the end surface is configured to be polished to remove the raised portion.

Semiconductor device

According to an embodiment, a semiconductor device includes M write word lines, M read word lines, N write bit lines, N read bit lines, N source lines, and M×N cells. The M×N cells are arranged in a matrix including M rows×N columns. A cell in an m-th row×an n-th column includes a first FET, a second FET, and a capacitor. The first FET is connected to an m-th write word line at a gate, to an n-th write bit line at a drain, and to a source of the second FET at a source. The second FET is connected to an m-th read word line at a gate and to an n-th read bit line at a drain. The capacitor is connected to an n-th source line at one end and to the source of the first RET at the other end.

Methods and systems of neuron leaky integrate and fire circuits

Embodiments include methods and systems of neuron leaky integrate and fire circuit (NLIFC). Aspects include: receiving an input current having both AC component and DC component at an input terminal of the NLIFC, extracting AC component of input current, generating a number of swing voltages at a swing node using extracted AC component of the input current, transferring charge from a pull-up node to a neuron membrane potential (NP) node through an integration diode and a pull-up diode to raise a voltage at NP node over an integration capacitor gradually and the voltage at NP node shows integration value of AC component of input current, implementing leaky decay function of the neuron leaky integrate and fire circuit, detecting a timing of neuron fire using an analog comparator, resetting a neuron membrane potential level for a refractory period after neuron fire, and generating fire output signal of the NLIFC.

Memristor Spiking Architecture

A circuit for a neuron of a multi-stage compute process is disclosed. The circuit comprises a weighted charge packet (WCP) generator. The circuit may also include a voltage divider controlled by a programmable resistance component (e.g., a memristor). The WCP generator may also include a current mirror controlled via the voltage divider and arrival of an input spike signal to the neuron. WCPs may be created to represent the multiply function of a multiply accumulate processor. The WCPs may be supplied to a capacitor to accumulate and represent the accumulate function. The value of the WCP may be controlled by the length of the spike in signal times the current supplied through the current mirror. Spikes may be asynchronous. Memristive components may be electrically isolated from input spike signals so their programmed conductance is not affected. Positive and negative spikes and WCPs for accumulation may be supported.

Reservoir computing networks using oscillators

A reservoir computing system comprising an input layer configured to receive input data from a signal propagation channel and to convert the input data into fixed input values, a reservoir configured to receive the fixed input values and generate a set of trained output values, and an output layer configured to receive the set of trained output values and generate a probability distribution based on the set of trained output values. The reservoir is comprised of a plurality of integrated oscillator components coupled in a fixed, random network, wherein each of the oscillator components is comprised of a device characterized by a current-voltage curve that comprises a region of non-linear behavior, such as a negative differential resistance (NDR) behavior.

Resistive memory crossbar array compatible with cu metallization

A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming a plurality of conductive lines within an interlayer dielectric (ILD), forming a RRAM stack including a bottom electrode, a top electrode, and a bi-layer hardmask, forming a low-k dielectric layer over the RRAM stack, removing a first layer of the bi-layer hardmask during a via opening, and removing a second layer of the bilayer hardmask concurrently with a plurality of sacrificial layers formed over the low-k dielectric layer.

Neural Network Accelerator in DIMM Form Factor

The technology relates to a neural network dual in-line memory module (NN-DIMM), a microelectronic system comprising a CPU and a plurality of the NN-DIMMs, and a method of transferring information between the CPU and the plurality of the NN-DIMMS. The NN-DIMM may include a module card having a plurality of parallel edge contacts adjacent to an edge of a slot connector thereof and configured to have the same command and signal interface as a standard dual in-line memory module (DIMM). The NN-DIMM may also include a deep neural network (DNN) accelerator affixed to the module card, and a bridge configured to transfer information between the DNN accelerator and the plurality of parallel edge contacts via a DIMM external interface.

Systems And Methods For Partial Digital Retraining

Provided herein is an integrated circuit including, in some embodiments, a hybrid neural network including a plurality of analog layers, a digital layer, and a plurality of data outputs. The plurality of analog layers is configured to include programmed weights of the neural network for decision making by the neural network. The digital layer, disposed between the plurality of analog layers and the plurality of data outputs, is configured for programming to compensate for weight drifts in the programmed weights of the neural network, thereby maintaining integrity of the decision making by the neural network. Also provided herein is a method including, in some embodiments, programming the weights of the plurality of analog layers; determining the integrity of the decision making by the neural network; and programming the digital layer of the neural network to compensate for the weight drifts in the programmed weights of the neural network.

Semiconductor device

Input unit to which a voltage is applied, current output unit that outputs a high level current or a low level current in response to the voltage applied to input unit, and stochastic circuit unit that, in response to the voltage applied to input unit, changes a probability that the high level current or the low level current is output from current output unit, in accordance with a sigmoid function used in a mathematical model of a neural activity are included.

Scene understanding using a neurosynaptic system

Embodiments of the invention provide a method for scene understanding based on a sequence of image frames. The method comprises converting each pixel of each image frame to neural spikes, and extracting features from the sequence of image frames by processing neural spikes corresponding to pixels of the sequence of image frames. The method further comprises encoding the extracted features as neural spikes, and classifying the extracted features.

Delta-sigma modulation neurons for high-precision training of memristive synapses in deep neural networks

A neural network comprising: a plurality of interconnected neural network elements, each comprising: a neuron circuit comprising a delta-sigma modulator, and at least one synapse device comprising a memristor connected to an output of said neuron circuit; wherein an adjustable synaptic weighting of said at least one synapse device is set based on said output of said neuron circuit

Compute in memory circuits with multi-vdd arrays and/or analog multipliers

Compute-in memory circuits and techniques are described. In one example, a memory device includes an array of memory cells, the array including multiple sub-arrays. Each of the sub-arrays receives a different voltage. The memory device also includes capacitors coupled with conductive access lines of each of the multiple sub-arrays and circuitry coupled with the capacitors, to share charge between the capacitors in response to a signal. In one example, computing device, such as a machine learning accelerator, includes a first memory array and a second memory array. The computing device also includes an analog processor circuit coupled with the first and second memory arrays to receive first analog input voltages from the first memory array and second analog input voltages from the second memory array and perform one or more operations on the first and second analog input voltages, and output an analog output voltage.

Dynamic Deep Learning Processor Architecture

Methods and systems for dynamically reconfiguring a deep learning processor by operating the deep learning processor using a first configuration. The deep learning processor then tracking one or more parameters of a deep learning program executed using the deep learning processor in the first configuration. The deep learning processor then reconfigures the deep learning processor to a second configuration to enhance efficiency of the deep learning processor executing the deep learning program based at least in part on the one or more parameters.

Network of artificial neurons based on complementary memristive devices

A neural network comprises a plurality of artificial neurons and a plurality of artificial synapses each input neuron being connected to each output neuron by way of an artificial synapse, the network being characterized in that each synapse consists of a first memristive device connected to a first input of an output neuron and of a second memristive device, mounted in opposition to said first device and connected to a second, complemented, input of said output neuron so that said output neuron integrates the difference between the currents originating from the first and second devices.

Neural network and its information processing method, information processing system

A neural network and its information processing method, information processing system. The neural network includes N layers of neuron layers connected to each other one by one, except for a first layer of neuron layer, each of the neurons of the other neuron layers includes m dendritic units and one hippocampal unit; the dendritic unit includes a resistance value graded device, the hippocampal unit includes a resistance value mutation device, and the m dendritic units can be provided with different threshold voltage or current, respectively; and the neurons on the nth layer neuron layer are connected to the m dendritic units of the neurons on the n+1th layer neuron layer; wherein N is an integer larger than 3, m is an integer larger than 1, n is an integer larger than 1 and less than N.

Visual cortical circuit apparatus, visual cortical imitation system and object search system using visual cortical circuit apparatus

Provided us a visual cortical circuit apparatus comprising: a current mirror unit which uses a transistor as a current source to generate a current having the same size as that of a reaction; a transconductance unit which takes, as an input, the current generated by the current mirror unit and outputs a voltage using a transconductance; and a buffer unit for converting the voltage output from the transconductance unit into a current and buffering the current.

Hardware implementation of a temporal memory system

A hardware implementation of a temporal memory system is disclosed. One aspect includes at least one array of memory cells logically organized in rows and columns, wherein each of the memory cells is adapted for storing a scalar value and adapted for changing the stored scalar value. The hardware implementation additionally includes an input system adapted for receiving an input frame as input and for creating a representation for the input, where the input comprises information for addressing the memory cells in the at least one array. The hardware implantation additionally includes at least one addressing unit for identifying a memory cell in the at least one array with a row address and a column address. The at least one addressing unit includes a column addressing unit for receiving the representation or a derivative thereof as input and applying the representation or the derivative as a column address to the array of memory cells, and a row addressing unit for receiving a delayed version of the representation at a specified time in the past as input, and applying this representation as a row address to the array of cells. The hardware implementation further includes a reading unit adapted for reading out scalar values from a selected row of memory cells in the array, based on the row address applied, wherein each scalar values read out by the reading unit corresponds to a likelihood of temporal coincidence between the input representation of the row address and the input representation of the column address, the likelihood being adjustable through the scalar value stored in the memory cell.

Current compensation block and method for programming analog neural memory in deep learning artificial neural network

Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Optionally, compensation measures can be utilized that compensate for changes in voltage or current as the number of cells being programmed changes.

Voltage control of learning rate for rpu devices for deep neural network training

A device, system, product and method of controlling resistive processing units (RPUs), includes applying an input voltage signal to each node of an array of resistive processing units, and controlling a learning rate of the array of resistive processing units by varying an amplitude of the input voltage signal to the array of resistive processing units. A conductance state of the array of resistive processing units is varied according to the amplitude received at each of the resistive processing units of the array of resistive processing units. The controlling of the amplitude of input voltage signal is according to a processor of a control device.

High Precision Low Bit Convolutional Neural Network

Described herein are systems, methods, and computer-readable media for generating and training a high precision low bit convolutional neural network (CNN). A filter of each convolutional layer of the CNN is approximated using one or more binary filters and a real-valued activation function is approximated using a linear combination of binary activations. More specifically, a non-1×1 filter (e.g., a k×k filter, where k>1) is approximated using a scaled binary filter and a 1×1 filter is approximated using a linear combination of binary filters. Thus, a different strategy is employed for approximating different weights (e.g., 1×1 filter vs. a non-1×1 filter). In this manner, convolutions performed in convolutional layer(s) of the high precision low bit CNN become binary convolutions that yield a lower computational cost while still maintaining a high performance (e.g., a high accuracy).

Structural plasticity in spiking neural networks with symmetric dual of an electronic neuron

A neural system comprises multiple neurons interconnected via synapse devices. Each neuron integrates input signals arriving on its dendrite, generates a spike in response to the integrated input signals exceeding a threshold, and sends the spike to the interconnected neurons via its axon. The system further includes multiple noruens, each noruen is interconnected via the interconnect network with those neurons that the noruen's corresponding neuron sends its axon to. Each noruen integrates input spikes from connected spiking neurons and generates a spike in response to the integrated input spikes exceeding a threshold. There can be one noruen for every corresponding neuron. For a first neuron connected via its axon via a synapse to dendrite of a second neuron, a noruen corresponding to the second neuron is connected via its axon through the same synapse to dendrite of the noruen corresponding to the first neuron.

Transform for a neurosynaptic core circuit

Embodiments of the present invention provide a method for feature extraction comprising generating synaptic connectivity information for a neurosynaptic core circuit. The core circuit comprises one or more electronic neurons, one or more electronic axons, and an interconnect fabric including a plurality of synapse devices for interconnecting the neurons with the axons. The method further comprises initializing the interconnect fabric based on the synaptic connectivity information generated, and extracting a set of features from input received via the electronic axons. The set of features extracted comprises a set of features with reduced correlation.

Performing processing-in-memory operations related to spiking events, and related methods, systems and devices

Methods, apparatuses, and systems for in- or near-memory processing are described. Spiking events in a spiking neural network may be processed via a memory system. A memory system may store a group of destination neurons, and at each time interval in a series of time intervals of a spiking neural network (SNN), pass through a group of pre-synaptic spike events from respective source neurons, wherein the group of pre-synaptic spike events are subsequently stored in memory.

Cognitive signal processor for simultaneous denoising and blind source separation

Described is a cognitive signal processor for signal denoising and blind source separation. During operation, the cognitive signal processor receives a mixture signal that comprises a plurality of source signals. A denoised reservoir state signal is generated by mapping the mixture signal to a dynamic reservoir to perform signal denoising. At least one separated source signal is identified by adaptively filtering the denoised reservoir state signal.

Method and system for performing analog complex vector-matrix multiplication

A hardware device and method for performing a multiply-accumulate operation are described. The device includes inputs lines, weight cells and output lines. The input lines receive input signals, each of which is has a magnitude and a phase and can represent a complex value. The weight cells couple the input lines with the output lines. Each of the weight cells has an electrical admittance corresponding to a weight. The electrical admittance is programmable and capable of being complex valued. The input lines, the weight cells and the output lines form a crossbar array. Each of the output lines provides an output signal. The output signal for an output line is a sum of an input signal for each of the input lines connected to the output line multiplied by the electrical admittance of each of the weight cells connecting the input lines to the output line.

Load distribution for a distributed neural network

A method for dynamic load distribution for a distributed neural network is disclosed. The method comprises estimating, in a device of the neural network, an energy usage for processing at least one non-processed layer in the device, and estimating, in the device of the neural network, an energy usage for transmitting layer output of at least one processed layer to a cloud service of the neural network for processing. The method further comprises comparing, in the device of the neural network, the estimated energy usage for processing the at least one non-processed layer in the device with the estimated energy usage for transmitting the layer output of the at least one processed layer to the cloud service. The method furthermore comprises determining to process the at least one non-processed layer in the device when the estimated energy usage for transmitting the layer output of the at least one processed layer to the cloud service is equal or greater than the estimated energy usage for processing the at least one non-processed layer, and determining to transmit the layer output of the at least one processed layer to the cloud service for processing subsequent layers when the estimated energy usage for transmitting the layer output of the at least one processed layer to the cloud service is less than the estimated energy usage for processing the at least one non-processed layer in the device. Corresponding computer program product, apparatus, cloud service assembly, and system are also disclosed.

Continuously learning and optimizing artificial intelligence (ai) adaptive neural network (ann) computer modeling methods and systems

Provided are continuously learning and optimizing artificial intelligence (AI) adaptive neural network (ANN) computer modeling methods and systems, designated “human affect computer modeling” (HACM) or “affective neuron” (AN) and, more particularly, to AI methods, systems and devices, that can recognize, interpret, process and simulate human reactions and affects such as emotional responses to internal and external sensory stimuli, that provides real-time reinforcement learning modeling that reproduces human affects and/or reactions, wherein the human affect computer modeling (HACM) can be used singularly or collectively for modeling and predicting complex human reactions and affects.

Expandable neuromorphic circuit

A neuromorphic circuit according to example embodiments of inventive concepts includes a first neuron array including a plurality of neuron circuits generating a spike signal; a first synapse array including a plurality of first synapse circuits to process and output the spike signal transmitted from the first neuron array; a second synapse array including a plurality of second synapse circuits; a first connecting block positioned between the first synapse array and the second synapse array and connecting the first synapse array and the second synapse array in response to a control signal; and a control logic to generate the control signal. The neuromorphic circuit may easily expand the size of the synapse element array to a desired size by using a connecting block.

Imaging device and electronic device

A data potential generated by the photoelectric conversion operation is input to a pulse generation circuit to output a pulse signal having a spike waveform. In addition, a structure in which product-sum operation of pulse signals is performed is provided, and digital data is generated from a new pulse signal. The digital data is taken into a neural network or the like, whereby processing such as image recognition can be performed. Processing up to taking an enormous amount of image data into a neural network or the like can be performed in the imaging device; thus, processing can be efficiently performed.

Circuit and method for spike time dependent plasticity

The present disclosure relates to a neuron circuit of a spiking neural network comprising: a first resistive switching memory device having a conductance that decays over time; and a programming circuit configured to reset the resistive state of the first resistive switching element in response to a spike in an output voltage of the neuron circuit.

Self-organized solid-state synthetic neuronal structure

A synthetic neuronal structure makes use of a semiconductor-metal phase transition material having material regions separated by discontinuities. The discontinuities represent interfaces such that different phases in two adjacent regions result in a metal-semiconductor interface. The interface supports a charge accumulation and a discharge of accumulated charge when an activation energy provided, for example, by electrical current, localized heating or optical energy, reaches a threshold necessary for breakdown of a potential barrier presented by the interface, and thus mimics a leaky integrate-and-fire neuron. With many such interfaces distributed through the structure, the local inputs to a neuron become a weighted sum of energy from neighboring neurons. Thus, different combinations of signals at one or more inputs connected to the structure will favor different neural pathways through the structure, thereby resulting in a neural network.

Method and apparatus for constructing a neuroscience-inspired artificial neural network with visualization of neural pathways

A method and apparatus for constructing one of a neuroscience-inspired artificial neural network and a neural network array comprises one of a neuroscience-inspired dynamic architecture, a dynamic artificial neural network array and a neural network array of electrodes associated with neural tissue such as a brain, the method and apparatus having a special purpose display processor. The special purpose display processor outputs a display over a period of selected reference time units to demonstrate a neural pathway from, for example, one or a plurality of input neurons through intermediate destination neurons to an output neuron in three dimensional space. The displayed neural network may comprise neurons and synapses in different colors and may be utilized, for example, to show the behavior of a neural network for classifying hand-written digits between values of 0 and 9 or recognizing vertical/horizontal lines in a grid image of lines.

Method and apparatus for constructing, using and reusing components and structures of an artifical neural network

A method and apparatus for constructing a neuroscience-inspired artificial neural network (NIDA) or a dynamic adaptive neural network array (DANNA) or combinations of substructures thereof comprises one of constructing a substructure of an artificial neural network for performing a subtask of the task of the artificial neural network or extracting a useful substructure based on one of activity, causality path, behavior and inputs and outputs. The method includes identifying useful substructures in artificial neural networks that may be either successful at performing a subtask or unsuccessful at performing a subtask. Successful substructures may be implanted in an artificial neural network and unsuccessful substructures may be extracted from the artificial neural network for performing the task. The method and apparatus supports constructing, using and reusing components and structures of a neuroscience-inspired artificial neural network dynamic architecture in software and a dynamic adaptive neural network array.

Multi-operation neural network unit

A neural network unit (NNU) includes N neural processing units (NPU). Each NPU has an arithmetic unit and an accumulator. First and second multiplexed registers of the N NPUs collectively selectively operate as respective first and second N-word rotaters. First and second memories respectively hold rows of N weight/data words and provide the N weight/data words of a row to corresponding ones of the N NPUs. The NPUs selectively perform: multiply-accumulate operations on rows of N weight words and on a row of N data words, using the second N-word rotater; convolution operations on rows of N weight words, using the first N-word rotater, and on rows of N data words, the rows of weight words being a data matrix, and the rows of data words being elements of a convolution kernel; and pooling operations on rows of N weight words, using the first N-word rotater.

Neural network memory

In an example, an apparatus can include an array of memory cells and a neural memory unit controller coupled to the array of memory cells and configured to assert respective voltage pulses during a first training interval to memory cells of the array to change respective threshold voltages of the memory cells from voltages associated with a reset state to effectuate respective synaptic weight changes. The neural memory unit controller can be configured to initiate a sleep interval, during which no pulses are applied to the memory cells, to effectuate respective voltage drifts in the changed respective threshold voltages of the memory cells from a voltage associated with a set state toward the voltage associated with the reset state, and determine an output of the memory cells responsive to the respective voltage drifts in the changed respective threshold voltages after the sleep interval.

Topological material for trapping charge and switching a ferromagnet

In some examples, a device includes a dielectric material, a ferromagnetic material, and a topological material positioned between the dielectric material and the ferromagnetic material. The device is configured to trap electric charge inside the dielectric material or at an interface of the dielectric material and the topological material. The device is configured to switch a magnetization state of the ferromagnetic material based on a current through the topological material or based on a voltage in the topological material.

Circuit methodology for highly linear and symmetric resistive processing unit

A processing unit includes a circuit including a current mirror, and a capacitor providing a weight based on a charge level of the capacitor. The capacitor is charged or discharged by the current mirror.

Semiconductor device and electronic device

A neuron circuit can switch between two functions: as an input neuron circuit, and as a hidden neuron circuit. An error circuit can switch between two functions: as a hidden error circuit, and as an output neuron circuit. A switching circuit is configured to be capable of changing the connections between the neuron circuit, a synapse circuit, and the error circuit. The synapse circuit includes an analog memory that stores data that corresponds to the connection strength between the input neuron circuit and the hidden neuron circuit or between the hidden neuron circuit and the output neuron circuit, a writing circuit that changes the data in the analog memory, and a weighting circuit that weights an input signal in reaction to the data of the analog memory and outputs the weighted output signal. The analog memory includes a transistor comprising an oxide semiconductor with extremely low off-state current.

Method for adjusting output level of multilayer neural network neuron

A method for adjusting output level of a neuron in a multilayer neural network is provided. The multilayer neural network includes a memristor and an analog processing circuit, causing transmission of the signals between the neurons and the signal processing in the neurons to be performed in an analog region. The method includes an adjustment step that adjusts an output level of the neurons of each of the layers, causing the output value to become lower than a write threshold voltage of the memristor and to fall within a maximum output range set for the analog processing circuit executing the generation of the output value in accordance with the activation function when each of the output values of the neurons of each of the layers becomes highest.

Soft memristor for soft neuromorphic system

The present disclosure provides a soft memristor for soft neuromorphic system including a substrate, a first electrode layer formed on the substrate, a metal diffusion barrier layer formed on the first electrode layer, a resistive switching material layer formed on the metal diffusion barrier layer, and a second electrode layer formed on the resistive switching material layer.

Temperature compensated common counter adc method for neural compute

The method provides for a low power and a temperature independent analog to digital convertor for systems which use non-volatile cells for forming neurons to be used for neural network applications. The method uses a common counter which can be an up-counter or a down-counter depending on implementation, but in which the source and sink currents to a comparator are changed with temperature by the same percentage as the average bit line current for specific weight distributions programmed in the non-volatile cells forming the neurons. The method uses charge accumulation for detecting the average neuron current.

Gaussian synapses for probabilistic neural networks

Embodiments relate to a Gaussian synapse device configured so that its transfer characteristics resemble a Gaussian distribution. Embodiments of the Gaussian synapse device include an n-type field-effect transistor (FET) and p-type FET with a common contact so that the two FETs are connected in series. Some embodiments include a global back-gate contact and separate top-gate contact to obtain dual-gated FETs. Some embodiments include two different 2D materials used in the channel to generate the two FETs, while some embodiments use a single ambipolar transport material. In some embodiments, the dual-gated structure is used to dynamically control the amplitude, mean and standard deviation of the Gaussian synapse. In some embodiments, the Gaussian synapse device can be used as a probabilistic computational device (e.g., used to form a probabilistic neural network).

Alignment Techniques to Match Symmetry Point as Zero-Weight Point in Analog Crosspoint Arrays

Zero-shifting techniques in analog crosspoint arrays are provided. In one aspect, an analog array-based vector-matrix multiplication includes: a weight array connected to a reference array, each including a crossbar array having a set of conductive row wires and a set of conductive column wires intersecting the set of conductive row wires, and optimizable crosspoint devices at intersections of the set of conductive column wires and the set of conductive row wires. A method for analog array-based vector-matrix computing is also provided that includes: applying repeated voltage pulses to the crosspoint devices in the weight array until all of the crosspoint devices in the weight array converge to their own symmetry point; and copying conductance values for each crosspoint device from the weight array to the reference array.

Processing apparatus and processing method

The present disclosure provides a processing device and method. The device includes: an input/output module, a controller module, a computing module, and a storage module. The input/output module is configured to store and transmit input and output data; the controller module is configured to decode a computation instruction into a control signal to control other modules to perform operation; the computing module is configured to perform four arithmetic operation, logical operation, shift operation, and complement operation on data; and the storage module is configured to temporarily store instructions and data. The present disclosure can execute a composite scalar instruction accurately and efficiently.

Array-integrated upstream/downstream router for circuit switched parallel connectivity

Array-integrated upstream/downstream routers for circuit-switched parallel connectivity are provided. A system comprises an array of neural cores having at least one dimension, a plurality of signal wires, and a plurality of routers. Each neural core comprises a plurality of ordered input wires, a plurality of ordered output wires, and a plurality of synapses, each synapse operatively coupled to one of the plurality of input wires and one of the plurality of output wires. The plurality of signal wires are disposed along each dimension of the array of neural cores. Each router is operatively coupled to one of the plurality of neural cores and to at least one signal wire along each dimension of the array of neural cores. Each of the plurality of routers is adapted to selectively route a signal from the at least one signal wire to its coupled neural core. Each of the plurality of routers is adapted to selectively route a signal from its coupled neural core to the at least one signal wire.

Three-terminal oxygen intercalation neuromorphic devices

Variable-resistance devices and methods of forming the same include a variable-resistance layer, formed between a first terminal and a second terminal, that varies in resistance based on an oxygen concentration in the variable-resistance layer. An electrolyte layer that is stable at room temperature and that conducts oxygen ions in accordance with an applied voltage is positioned over the variable-resistance layer. A gate layer is configured to apply a voltage on the electrolyte layer and the variable-resistance layer and is positioned over the electrolyte layer.

Systems and Methods for Human Activity Recognition Using Analog Neuromorphic Computing Hardware

Systems, methods, and devices are provided for human activity recognition. An example device includes an integrated circuit for human activity recognition. The integrated circuit includes an analog network of analog components configured to implement a trained neural network model (e.g., an autoencoder) that is trained to generate a plurality of descriptors for a plurality of predefined human activities based on a plurality of features extracted from a plurality of electrical signals from one or more sensors. The device also includes one or more digital components configured to classify human activity (e.g., using a classifier, such as K-Nearest Neighbor) as one of the plurality of predefined human activities according to the plurality of descriptors generated by the integrated circuit. In some implementations, the device further includes the one or more sensors configured to collect the plurality of electrical signals during the human activity.

Hardware architecture for spiking neural networks and method of operating

The present invention provides a hardware architecture for spiking neural networks which is characterized in that it combines a fully-parallel architecture with a time-multiplexed architecture.

Applications of back-end-of-line (beol) capacitors in compute-in-memory (cim) circuits

An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes an accumulation circuit. The accumulation circuit includes a ferroelectric BEOL capacitor to store a value to be accumulated with other values stored by other ferroelectric BEOL capacitors.

In-memory data pooling for machine learning

A method comprises a first block of memory cells to store an input array, and a second block of memory cells. Pooling circuitry is operatively coupled to the first block of memory cells to execute in-place pooling according to a function over the input array to generate an array of output values. Writing circuitry is operatively coupled to the second block to store the array of output values in the second block of memory cells. Analog sensing circuitry is coupled to the first block of memory cells to generate analog values for the input array, wherein the pooling circuitry receives the analog values as inputs to the function. The writing circuitry operatively coupled to the second block is configured to store an analog level in each cell of the second block for the array of output values.

Dynamic adaptation of deep neural networks

Techniques are disclosed for training a deep neural network (DNN) for reduced computational resource requirements. A computing system includes a memory for storing a set of weights of the DNN. The DNN includes a plurality of layers. For each layer of the plurality of layers, the set of weights includes weights of the layer and a set of bit precision values includes a bit precision value of the layer. The weights of the layer are represented in the memory using values having bit precisions equal to the bit precision value of the layer. The weights of the layer are associated with inputs to neurons of the layer. Additionally, the computing system includes processing circuitry for executing a machine learning system configured to train the DNN. Training the DNN comprises optimizing the set of weights and the set of bit precision values.

Floating gate based 3-terminal analog synapse device and a manufacturing method thereof

Provided is a floating gate based 3-terminal analog synapse device including a silicon channel layer; a gate oxide deposited on the silicon channel layer; a charge trap layer deposited on the gate oxide, wherein charges are injected into the charge trap layer; a barrier layer deposited on the charge trap layer, and having lower electron affinity than electron affinity of a material of the charge trap layer; and a gate metal layer deposited on an upper surface of the barrier layer, wherein a gate voltage is applied to the gate metal layer.

Device, system and method for providing information security

A cryptography system comprising a first node having a unique identifier generator configured to generate at least one physical unclonable function (PUF); and a second node configured to remotely send an attestation request to the first node is disclosed. In some embodiments, the cryptography system may form at least part of a distributed ledger and the PUF is configured to respond to the attestation request.

Neuron-centric local learning rate for artificial neural networks to increase performance, learning rate margin, and reduce power consumption

Artificial neural networks (ANNs) are a distributed computing model in which computation is accomplished using many simple processing units (called neurons) and the data embodied by the connections between neurons (called synapses) and the strength of these connections (called synaptic weights). An attractive implementation of ANNs uses the conductance of non-volatile memory (NVM) elements to code the synaptic weight. In this application, the non-idealities in the response of the NVM (such as nonlinearity, saturation, stochasticity and asymmetry in response to programming pulses) lead to reduced network performance compared to an ideal network implementation. Disclosed is a method that improves performance by implementing a learning rate parameter that is local to each synaptic connection, a method for tuning this local learning rate, and an implementation that does not compromise the ability to train many synaptic weights in parallel during learning.

Synaptic weight transfer between conductance pairs with polarity inversion for reducing fixed device asymmetries

Artificial neural networks (ANNs) are a distributed computing model in which computation is accomplished with many simple processing units, called neurons, with data embodied by the connections between neurons, called synapses, and by the strength of these connections, the synaptic weights. An attractive implementation of ANNs uses the conductance of non-volatile memory (NVM) elements to record the synaptic weight, with the important multiply—accumulate step performed in place, at the data. In this application, the non-idealities in the response of the NVM such as nonlinearity, saturation, stochasticity and asymmetry in response to programming pulses lead to reduced network performance compared to an ideal network implementation. A method is shown that improves performance by periodically inverting the polarity of less-significant signed analog conductance-pairs within synaptic weights that are distributed across multiple conductances of varying significance, upon transfer of weight information between less-significant signed analog conductance-pairs to more-significant analog conductance-pairs.

Convolutional neural network

Systems and methods of implementing a more efficient and less resource-intensive CNN are disclosed herein. In particular, applications of CNN in the analog domain using Sampled Analog Technology (SAT) methods are disclosed. Using a CNN design with SAT results in lower power usage and faster operation as compared to a CNN design with digital logic and memory. The lower power usage of a CNN design with SAT can allow for sensor devices that also detect features at very low power for isolated operation.

Methods and systems of operating a neural circuit in a non-volatile memory based neural-array

In one aspect, a method of a neuron circuit includes the step of providing a plurality of 2 N −1 single-level-cell (SLC) flash cells for each synapse (Y i ) connected to a bit line forming a neuron. The method includes the step of providing an input vector (X i ) for each synapse Y i wherein each input vector is translated into an equivalent electrical signal ES i (current I DACi , pulse, T PULSEi , etc). The method includes the step of providing an input current to each synapse sub-circuit varying from 2 0 *ES i to (2 N −1)*ES i . The method includes the step of providing a set of weight vectors or synapse (Y i ), wherein each weight vector is translated into an equivalent threshold voltage level or resistance level to be stored in one of many non-volatile memory cells assigned to each synapse (Y i ). The method includes the step of providing for 2 N possible threshold voltage levels or resistance levels in the 2 N −1 non-volatile memory cells of each synapse, wherein each cell is configured to store one of the two possible threshold voltage levels. The method includes the step of converting the N digital bits of the weight vector or synapse Y i into equivalent threshold voltage level and store the appropriate cell corresponding to that threshold voltage level in one of the many SLC cells assigned to the weight vector or synapse (Y i ). The method includes the step of turning off all remaining 2 N −1 flash cells of the respective synapse (Y i ). Various other methods are presented of forming neuron circuits by providing a plurality of single-level-cell (SLC) and many-level-cell (MLC) non-volatile memory cells, for each synapse (Y i ) electrically connected to form a neuron. The disclosure shows methods of forming neurons in various configurations for non-volatile memory cells (flash, RRAM etc.); of different storage capabilities per cell—both SLC and MLC cells.

Performing complex multiply-accumulate operations

In one example in accordance with the present disclosure a device is described. The device includes at least two memristive cells. Each memristive cell includes a memristive element to store one component of a complex weight value. The device also includes a real input multiplier coupled to the memristive element to multiply an output signal of the memristive element with a real component of an input signal. An imaginary input multiplier of the device is coupled to the memristive element to multiply the output signal of the memristive element with an imaginary component of the input signal.

Two-terminal metastable mixed-conductor memristive devices

Methods for setting a resistance include applying a voltage across a memristive device, that exceeds a threshold based on a difference in chemical potential between a first material and a second material, to change a resistance of the memristive device. The memristive device includes a barrier layer of the second material that is formed between two metastable layers of the first material.

Memory operation method and circuit

A method of operating a synapse array includes applying a pulse sequence to a resistor coupled between a row and a column of the synapse array, and in response to the applying the pulse sequence, lowering a conductance level of the resistor. Each pulse of the pulse sequence includes a pulse number, an amplitude, a leading edge, a pulse width, and a trailing edge, the trailing edge having a duration longer than a duration of the leading edge, and applying the pulse sequence includes increasing the pulse number while increasing one of the amplitude, the pulse width, or the trailing edge duration.

System and methods for mixed-signal computing

Systems and methods of implementing a mixed-signal integrated circuit includes sourcing, by a reference signal source, a plurality of analog reference signals along a shared signal communication path to a plurality of local accumulators; producing an electrical charge, at each of the plurality of local accumulators, based on each of the plurality of analog reference signals; adding or subtracting, by each of the plurality of local accumulators, the electrical charge to an energy storage device of each of the plurality of local accumulators over a predetermined period; summing along the shared communication path the electrical charge from the energy storage device of each of the plurality of local accumulators at an end of the predetermined period; and generating an output based on a sum of the electrical charge from each of the plurality of local accumulators.

Electronic Device

An electronic device applicable to an artificial neuron network. The electronic device includes a first circuit, a second circuit, and first to sixth wirings. The first circuit includes a first transistor, a second transistor, and a capacitor. The second circuit includes a third transistor. A gate of the third transistor is electrically connected to the third wiring. The capacitor capacitively couples the third wiring and the gate of the second transistor. The first circuit is capable of storing a weight as an analog value. The first transistor is typically an oxide semiconductor transistor.

Memory device performing parallel calculation processing, operating method thereof, and operating method of memory controller controlling the memory device

A memory device includes a memory bank including a plurality of banks, each including a memory cell array; a calculation logic including a plurality of processor-in-memory (PIM) circuits arranged in correspondence to the banks, each of the plurality of PIM circuits performing calculation processing using at least one selected from data provided from a host and information read from a corresponding bank among the banks; and a control logic configured to control a memory operation on the memory bank in response to a command and/or an address, each received from the host, or to control the calculation logic to perform the calculation processing, wherein reading operations are respectively performed in parallel on the banks for the calculation processing, offsets having different values are respectively configured for the banks, and information is read from different positions in respective memory cell arrays of the banks and provided to the PIM circuits.

Switched artificial synapse

Electronic neural circuit including at least one pre-neuron having an output voltage VAout, and at least one post-neuron that are linked by at least one excitatory synapse having at least one switching input, wherein the excitatory synapse is supplied with power by the output VAout and receives, on its switching input, a switching signal VAout_bar whose state is complementary to that of the output VAout.

Memory data randomizer

A method is provided of initializing a chip having synaptic NVRAM cells connected row-wise by word lines and column-wise by bit lines. The method includes selecting each word line through a row decoder connected to all word lines to switch all synaptic NVRAM cells of the selected lines. The method includes driving, on the selected lines, a wave generated by a PLL circuit connected to the row decoder. The method includes generating standing waves from the wave on the selected lines by implementing a resonance detection point at an input end of each word line. The method includes applying a write voltage on all bit lines through a column decoder connected to all bit lines. The method includes simultaneously driving each of the synaptic NVRAM cells of the selected lines by different writing currents for different durations in order to set different analog values to the synaptic NVRAM cells.

Synapse circuit with memory

A synapse circuit with an arrayed structured memory for machine learning applications is disclosed. The synapse circuit comprises a controlled variable resistance, a controlled switch connected to a contact terminal of the controlled variable resistance, and a memory cell for storing a weight variable. The memory cell is operatively connected to a control terminal of the controlled switch. A control terminal of the controlled variable resistance is configured for receiving an activation signal. The controlled variable resistance has a first resistance value and a second resistance value substantially larger than the first resistance value. A ratio of the second resistance value to the first resistance value is at least one hundred. A current, flowing through the controlled switch and the controlled variable resistance, (1) is indicative of the activation signal weighted by the stored weight variable if the controlled variable resistance is the first resistance value and (2) is smaller or equal to one picoampere at room temperature if the controlled variable resistance is adopting the second resistance value.

Computation in-memory architecture for analog-to-digital conversion

A device includes a comparator to provide an indication of a difference between Vp on a first terminal coupled to a top plate of each of a first group of differential capacitors, and Vn on a second terminal coupled to a top plate of each of a second group of differential capacitors. The device includes a control circuit coupled to the comparator. The control circuit is to receive a first indication of a difference between Vp and Vn; responsive to the first indication, cause a first driver to provide a reference voltage to bottom plates of one of the first and second groups, and cause a second driver to provide a ground voltage to bottom plates of the other of the first and second groups; receive a second indication of a difference between Vp and Vn; and provide a digital value responsive to the first indication and the second indication.

Memristor apparatus with variable transmission delay

In an example, a memristor apparatus with variable transmission delay may include a first memristor programmable to have one of a plurality of distinct resistance levels, a second memristor, a transistor connected between the first memristor and the second memristor, and a capacitor having a capacitance, in which the capacitor is connected between the first memristor and the transistor. In addition, application of a reading voltage across the second memristor is delayed by a time period equivalent to the programmed resistance level of the first memristor and the capacitance of the capacitor.

Multiply accumulate circuit for binary neural network system

A multiply accumulate circuit receives m one-bit neuron values from a first layer of a neural network system. The multiply accumulate circuit includes m non-volatile memory cells and m current sources. In addition, m current paths are defined by the m non-volatile memory cells and the m current sources collaboratively. A first current path is defined by a first non-volatile memory cell and a first current source. A first terminal of the first current source receives a first supply voltage. A second terminal of the first current source is connected with a first terminal of the first non-volatile memory cell. A second terminal of the first non-volatile memory cell is connected with an output terminal of the multiply accumulate circuit. A control terminal of the first current source receives a first one-bit neuron value.

Temperature assisted programming of flash memory for neuromorphic computing

A method is presented for temperature assisted programming of flash memory for neuromorphic computing. The method includes training a chip in an environment having a first temperature, adjusting the first temperature to a second temperature in the environment, and employing the chip for inference in the second temperature environment. The first temperature is about 125° C. or higher and the second temperature is about 50° C. or lower.

Analog Co-Processor

A co-processor is configured for performing vector matrix multiplication (VMM) to solve computational problems such as partial differential equations (PDEs). An analog Discrete Fourier Transform (DFT) can be implemented by invoking VMM of input signals with Fourier basis functions using analog crossbar arrays. Linear and non-linear PDEs can be solved by implementing spectral PDE solution methods as an alternative to massively discretized finite difference methods, while exploiting inherent parallelism realized through the crossbar arrays. The analog crossbar array can be implemented in CMOS and memristors or a hybrid solution including a combination of CMOS and memristors.

2d and 3d sum-of-products array for neuromorphic computing system

An array of variable resistance cells based on a programmable threshold transistor and a resistor connected in parallel is described, including 3D and split gate variations. An input voltage applied to the transistor, and the programmable threshold of the transistor, can represent variables of sum-of-products operations. Programmable threshold transistors in the variable resistance cells comprise charge trapping memory transistors, such as floating gate transistors or dielectric charge trapping transistors. The resistor in the variable resistance cells can comprise a buried implant resistor connecting the current-carrying terminals (e.g. source and drain) of the programmable threshold transistor. A voltage sensing sense amplifier is configured to sense the voltage generated by the variable resistance cells as a function of an applied current and the resistance of the variable resistance cells.

Circuit methodology for differential weight reading in resistive processing unit devices

A system, comprising: a memory that stores computer-executable components; a processor, operably coupled to the memory, that executes the computer-executable components stored in the memory, wherein the computer-executable components comprise: an expression component that expresses the read current range in an RPU as read current Iwmin and Iwmax, a constant current source component that generates a reference current I, a computing component that subtracts the reference current value within from the read current value to generate an active net current read value that is negative, positive or null; a weighting component that analyzes the active current value and assigns it to a negative, positive or null weight.

Multi-level memristor elements

There is described a two-terminal multi-level memristor element synthesised from binary memristors, which is configured to implement a variable resistance based on unary or binary code words. There is further described a circuit such as a synapse circuit implemented using a multi-level memristor element.

Synapse memory cell driver

A synapse memory system includes: synapse memory cells provided at cross points of axon lines and dendrite lines, each synapse memory cell being associated with nonvolatile random-access memory (NVRAM), each synapse memory cell being configured to store a weight value according to an output level of a write signal; a write portion configured to write the weight value to each synapse memory cell, the write portion including a write driver and an output controller, the write driver being a digital driver configured to output the write signal to a subject synapse memory cell, the output controller being configured to control the output level of the write signal of the write driver; and read drivers configured to read the weight value stored in the synapse memory cells.

Implementing hardware neurons using tunneling devices

Systems and methods for mitigating defects in a crossbar-based computing environment are disclosed. In some implementations, an apparatus comprises: a plurality of row wires; a plurality of column wires connecting between the plurality of row wires; a plurality of non-linear devices formed in each of a plurality of column wires configured to receive an input signal, wherein at least one of the non-linear device has a characteristic of activation function and at least one of the non-linear device has a characteristic of neuronal function.

Neuromorphic arithmetic device and operating method thereof

The neuromorphic arithmetic device comprises an input monitoring circuit that outputs a monitoring result by monitoring that first bits of at least one first digit of a plurality of feature data and a plurality of weight data are all zeros, a partial sum data generator that skips an arithmetic operation that generates a first partial sum data corresponding to the first bits of a plurality of partial sum data in response to the monitoring result while performing the arithmetic operation of generating the plurality of partial sum data, based on the plurality of feature data and the plurality of weight data, and a shift adder that generates the first partial sum data with a zero value and result data, based on second partial sum data except for the first partial sum data among the plurality of partial sum data and the first partial sum data generated with the zero value.

Neuromorphic device including a synapse having carbon nano-tubes

A neuromorphic device is provided. The neuromorphic device may include a pre-synaptic neuron; a row line extending in a row direction from the pre-synaptic neuron; a post-synaptic neuron; a column line extending in a column direction from the post-synaptic neuron; and a synapse disposed at an intersection between the row line and the column line. The synapse may include a first synapse layer including a plurality of first carbon nano-tubes; a second synapse layer including a plurality of second carbon nano-tubes having different structures from the plurality of first carbon nano-tubes; and a third synapse layer including a plurality of third carbon nano-tubes having different structures from the plurality of first carbon nano-tubes and the plurality of second carbon nano-tubes.

Enhancing processing performance of a dnn module by bandwidth control of fabric interface

An exemplary computing environment having a DNN module can maintain one or more bandwidth throttling mechanisms. Illustratively, a first throttling mechanism can specify the number of cycles to wait between transactions on a cooperating fabric component (e.g., data bus). Illustratively, a second throttling mechanism can be a transaction count limiter that operatively sets a threshold of a number of transactions to be processed during a given transaction sequence and limits the number of transactions such as multiple transactions in flight to not exceed the set threshold. In an illustrative operation, in executing these two exemplary calculated throttling parameters, the average bandwidth usage and the peak bandwidth usage can be limited. Operatively, with this fabric bandwidth control, the processing units of the DNN are optimized to process data across each transaction cycle resulting in enhanced processing and lower power consumption.

Battery-based neural network weights

A controllable resistive element and method for updating the resistance of the same includes a state device configured to provide a voltage-controlled resistance responsive to a voltage input. A battery is configured to apply a voltage to the voltage input of the state device based on a charge stored in the battery. A write device is configured to charge the battery responsive to a write signal. An erase device is configured to discharge the battery responsive to an erase signal.

Artificial Neurons Using Diffusive Memristor

A diffusive memristor device and an electronic device for emulating a biological neuron is disclosed. The diffusive memristor device includes a bottom electrode, a top electrode formed opposite the bottom electrode, and a dielectric layer disposed between the top electrode and the bottom electrode. The dielectric layer comprises an oxide doped with a metal.

Precision Programming Circuit For Analog Neural Memory In Deep Learning Artificial Neural Network

Various embodiments of high voltage generation circuits, high voltage operational amplifiers, adaptive high voltage supplies, adjustable high voltage incrementor, adjustable reference supplies, and reference circuits are disclosed. These circuits optionally can be used for programming a non-volatile memory cell in an analog neural memory to store one of many possible values.

Transform for a neurosynaptic core circuit

Embodiments of the present invention provide a method for feature extraction comprising generating synaptic connectivity information for a neurosynaptic core circuit. The core circuit comprises one or more electronic neurons, one or more electronic axons, and an interconnect fabric including a plurality of synapse devices for interconnecting the neurons with the axons. The method further comprises initializing the interconnect fabric based on the synaptic connectivity information generated, and extracting a set of features from input received via the electronic axons. The set of features extracted comprises a set of features with reduced correlation.

Initiating and monitoring the evolution of single electrons within atom-defined structures

A method for the patterning and control of single electrons on a surface is provided that includes implementing scanning tunneling microscopy hydrogen lithography with a scanning probe microscope to form charge structures with one or more confined charges; performing a series of field-free atomic force microscopy measurements on the charge structures with different tip heights, where interaction between the tip and the confined charge are elucidated; and adjusting tip heights to controllably position charges within the structures to write a given charge state. The present disclose also provides a Gibb's distribution machine formed with the method for the patterning and control of single electrons on a surface. A multi bit true random number generator and neural network learning hardware formed with the above described method are also provided.

Battery-based neural network weights

Methods for controlling the resistance of a controllable resistive element include determining an amount of electrical resistance change for the controllable resistive element. A concentration difference is determined for a charge carrier ion in a resistor layer of the controllable resistance element that corresponds to the electrical resistance change for the controllable resistive element. A duration and amplitude of a current pulse is determined that changes the charge carrier ion concentration by the determined difference. A positive or negative current pulse is applied to a controllable resistive element for the determined duration.

Hardware-Implemented Training Of An Artificial Neural Network

The invention relates to a method for hardware-implemented training of a feedforward artificial neural network. The method comprises: generating a first output signal by processing an input signal with the network, wherein a cost quantity to assumes a first cost value; measuring the first cost value; defining a group of at least one synaptic weight of the network for variation; varying each weight of the group by a predefined weight difference; after the variation, generating a second output signal from the input signal to measure a second cost value; comparing the first and second cost values; and determining, based on the comparison, a desired weight change for each weight of the group such that the cost function does not increase if the respective desired weight changes are added to the weights of the group. The desired weight change is based on the weight difference times −1, 0, or +1.

Capsule vector spin neuron implementation of a capsule neural network primitive

Techniques are provided for implementing capsule neural networks (NNs) using vector spin neurons. A vector spin neuron according to an embodiment includes a first magnet, polarized in a first direction, to receive a first input current. The first input current is based on an NN input value and weighting factor. The vector spin neuron also includes a second magnet, polarized in a direction orthogonal to the first direction, to receive a second input current. The second input current is based on a second NN input value and weighting factor. The first and second magnets generate spin polarized currents. In some such embodiments, the vector spin neuron further includes a third magnet, which is unpolarized, and a conductor to couple output regions of the first and second magnets to an input region of the third magnet. The third magnet applies a non-linear activation function to the sum of the spin polarized currents.

Remote Direct Memory Access in Multi-Tier Memory Systems

A memory system having memory components, a remote direct memory access (RDMA) network interface card (RNIC), and a host system, and configured to: allocate a page of virtual memory for an application; map the page of virtual memory to a page of physical memory in the memory components; instruct the RNIC to perform an RDMA operation; perform, during the RDMA operation, a data transfer between the page of physical memory in the plurality of memory components and a remote device that is connected via a computer network to the remote direct memory access network interface card; and at least for a duration of the data transfer, lock a mapping between the page of virtual memory and the page of physical memory in the memory components.

Product-sum operation device, logical calculation device, neuromorphic device, and multiply-accumulate method

A multiply-accumulate calculation device includes: multiple calculation units which generates output signals by multiplying an input signal corresponding to an input value and having a rising part, a signal part, and a falling part by a weight, and output the output signals; an accumulate calculation unit configured to calculate a sum of the output signals output from the plurality of multiple calculation units; and a correction unit configured to execute correction processing for correcting the sum of the output signals on the basis of a correction value including at least one of a first value incorporated into the sum by a current flowing into variable resistors of the multiple calculation units due to the rising part of the input signal, and a second value incorporated into the sum by a current flowing into the variable resistors of the multiple calculation units due to the falling part of the input signal.

Methods and apparatus to generate audience metrics using third-party privacy-protected cloud environments

An example apparatus disclosed herein includes a panelist detector to identify audience measurement panelists associated with database proprietor accounts, a sign-in rate calculator to determine an actual sign-in rate of the audience measurement panelists based on first impressions represented in database proprietor impressions data and second impressions represented in panel data, an adjustment factor generator to determine a first audience adjustment factor corresponding to a first sign-in rate and a second audience adjustment factor corresponding to a second sign-in rate, and a weighting controller to generate a first weighted audience adjustment factor and a second weighted audience adjustment factor by weighting the first and second audience adjustment factors by the actual sign-in rate, the adjustment factor generator to determine a signed-out adjustment factor based on the first and second weighted audience adjustment factors.