УСТРОЙСТВО ПАМЯТИ И СПОСОБ УПРАВЛЕНИЯ ИМ

Изобретение относится к устройствам памяти. Технический результат заключается в расширении арсенала средств того же назначения. Устройство памяти включает массив ячеек памяти, схему перемычек, схему управления, при этом когда подается первый адрес в первом направлении в первом массиве, схема перемычек переносит первые данные, соответствующие первому адресу, в схему управления, и когда подается второй адрес во втором направлении в первом массиве после того, как первые данные перенесены в схему управления, схема управления осуществляет доступ к одному из первого и второго массивов на основе результата сравнения для второго адреса и первых данных. 3 н. и 17 з.п. ф-лы, 16 ил.

DYNAMISCHER SCHREIB-LESESPEICHER UND VERFAHREN ZUM BETREIBEN EINES SOLCHEN

Halbleitergerät, das Schwankungen im Substratpotenzial zu verhindern fähig ist

Dynamischer RAM

Signalspielraumprüfsystem.

Auffrischgerät für eine Halbleiterspeichereinrichtung und Auffrischverfahren hierfür

Ein Auffrischgerät für eine Halbleiterspeichereinrichtung und ein Auffrischverfahren dazu, welches die Testzeit durch gleichzeitiges Auffrischen einer normalen Zelle und einer redundanten Zelle in einem Testmodus reduzieren kann, wird veröffentlicht. Das Auffrischgerät für die Halbleiterspeichereinrichtung kann einen redundanten Zellauffrischungssignalgenerator zum Erzeugen eines redundanten Zellauffrischsignals zum Auffrischen einer redundanten Zelle beinhalten, wenn ein Auffrischen in einem Testmodus gefordert wird, einen Wortleitungsfreigabesignalgenerator zum Erzeugen eines normalen Wortleitungsfreigabesignals und eines redundanten Hauptwortleitungsfreigabesignals in Antwort auf das redundante Zellauffrischungssignal in einem redundanten Zellmodus und einen Wortleitungstreiber zum gleichzeitigen Auffrischen der normalen und redundanten Zellen durch gleichzeitiges Treiben einer normalen Hauptwortleitung und einer redundanten Hauptwortleitung in Antwort auf das redundante Zellauffrischsignal ...

Halbleiterspeichereinrichtung mit einem Normalbetriebsmodus und einem Eigenauffrischungsmodus und einem reduzierten Stromverbrauch und stabilen Betrieb in einem Datenhaltezustand

Synchrone Halbleiterspeichervorrichtung

SPEICHERBLOCKAUSWAHL UNTER VERWENDUNG VON MEHREREN WORTLEITUNGEN ZUR ADRESSIERUNG EINER EINZIGEN SPEICHERZELLENZEILE

Halbleiterspeicheranordnung

Verfahren zum Betreiben eines flüchtigen Schreib-Lese-Speichers als Detektor und Schaltungsanordnung

Verfahren, um einen flüchtigen Schreib-Lese-Speicher (1) als Detektor zu betreiben, wobei vorgegebene Information (I1) in zumindest einen Bereich (11) des flüchtigen Schreib-Lese-Speichers (1) gespeichert ist, mit den Schritten: – Unterbrechen (120) einer Versorgungsspannung (V) für den zumindest einen Bereich (11) des Schreib-Lese-Speichers (1) während eines Zeitraums (T, T1, T2), – Auslesen (130) von Information (I2) aus dem zumindest einen Bereich (11) des Schreib-Lese-Speichers (1) und – Prüfen (140, 150), inwiefern die vorgegebene Information (I1) und die ausgelesene Information (I2) übereinstimmen, oder ob die vorgegebene Information (I1) und die ausgelesene Information (I2) in einem vorgegebenen Zusammenhang (Y) stehen.

Schaltungsanordnung und Verfahren zur Ermittlung einer Zeitkonstante eines Speicherkondensators einer Speicherzelle eines Halbleiterspeichers

Es wird ein Ringoszillator (55) bereitgestellt, der eine Vielzahl von Invertern (5, 20, 35) umfaßt. zwischen zwei Invertern ist eine Leiterbahn (50) angeordnet, an die ein zu messender Speicherkondensator (80) mit seinem zugehörigen Zuleitungswiderstand (85) mittels einer Leiterbahn (186) angekoppelt ist, beziehungsweise mittels eines Transistors (185) ankoppelbar, beziehungsweise abkoppelbar ist. Mittels einer mit dem Ringoszillator (55) verschalteten Meßeinrichtung (100) ist ein Wert für die Oszillationsfrequenz des Ringoszillators (55) ermittelbar, auf dessen Grundlage ein Wert für die Zeitkonstante des Speicherkondensators (80) ermittelbar ist.

Schaltungsanordnung mit einer Ablaufsteuerung, integrierter Speicher sowie Testanordnung mit einer derartigen Schaltungsanordnung

Schaltungsanordnung - mit einer Ablaufsteuerung (2), die in mehrere Zustände (ACT, RERD, PRCH) vesetzbar ist und die in jeweils einem der Zustände einen jeweiligen Befehl (AC, RD, PR) an eine zu steuernde Schaltungskomponente (3) ausgibt, - bei der die Ablaufsteuerung mindestens eine asynchron arbeitende Verzögerungsschaltung (I1 bis I3) aufweist, über die sich die Ablaufsteuerung von einem der Zustände in den jeweils nächsten Zustand bewegt, - bei der der Verzögerungsschaltung (I1 bis I3) ein weiterer Signalpfad parallel geschaltet ist, der eine taktgesteuerte Kippschaltung (FF1 bis FF3) aufweist, wobei die Verzögerungsschaltung und der weitere Signalpfad über ein Schaltmittel (S1 bis S3) alternativ betreibbar sind.

Speicherbaustein mit einem Datengenerator und einer Testlogik und Verfahren zum Testen von Speicherzellen eines Speicherbausteins

Es wird ein Speicherbaustein beschrieben, der einen On-Chip-Datengenerator und eine Scramblereinheit zum Überprüfen der korrekten Funktionsfähigkeit der Speicherzellen aufweist. Weiterhin weist der Speicherbaustein eine Reparatureinheit und redundante Wortleitungen auf, die im Falle einer defekt erkannten Speicherzelle für die regulär zu aktivierende Wortleitung eingesetzt werden. Erfindungsgemäß ist die Scramblereinheit mit der Reparatureinheit verbunden und erhält somit von der Reparatureinheit die Information, ob die redundante Wortleitung, die eine defekte Wortleitung ersetzt, Transistoren von Speicherzellen ansteuert, die mit True-Bitleitungen oder komplementären Bitleitungen verbindbar sind. Auf diese Weise kann die Scramblereinheit die Information, ob eine True- oder eine komplementäre Bitleitung über die Ersatzwortleitung angesteuert wird, bei der Durchführung des Testverfahrens berücksichtigen. Auf diese Weise ist eine effizientere Ausführung des Testverfahrens möglich.

Internal source voltage generating circuit for a semiconductor memory device

An internal voltage source, suitable for operating a semiconductor memory in normal and stress modes, comprises: an external voltage Vext applied to an input terminal and an internal voltage VINT supplied at an output terminal. The internal voltage source is arranged such that VINT rises with that of Vext at a first rate when Vext is below the normal operation range, a second rate when Vext is within the normal operating range Vno - Vsm and a third rate when Vext is above the operating range. The said second rate is lower than the said first rate, and the third rate is higher than the second rate when in the stress mode and equal to the second rate when in the normal mode. The internal voltage source may comprise a voltage generator, a voltage clamping unit with series connected transistors, a voltage divider and a differential amplifier. An external signal may be applied to one of the clamping transistors to select between normal and stress operating modes.

Refresh apparatus for semiconductor memory device and refresh method thereof

Memory with bit swapping on the fly and testing

A memory controller and method that provide a read-refresh (also called "distributed-refresh") mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.

Apparatus and method for testing memory cards

Semiconductor integrated circuit

SPATIAL LIGHT MODULATOR WITH LOAD PUMP PIXEL CELL

CIRCUIT AND PROCEDURE FOR THE CONTROLLING OF A CLOCK SYNCHRONISATION CIRCUIT FOR A LOW POWER REFURBISHING OPERATION

SYSTEM AND PROCEDURE FOR THE DECREASE OF THE CURRENT CONSUMPTION DURING EXTENSIONS REFURBISHING PERIODS OF DYNAMIC DIRECT ACCESS STORAGE COMPONENTS

SERIAL MULTIPLEXIERTE REGISTER ARCHITECTURE FOR VRAM

Semiconductor memory having dual port cell supporting hidden refresh

A method and apparatus for sampling data from a memory

BIST MEMORY TEST SYSTEM

A semiconductor device having a self test circuit including an embedded dynamic random access memory array for storing data, a self test controller for internally generating test data patterns and expected resulting data and for comparing the expected resulting data with actual resulting data, test interface circuitry for loading the test data patterns into the memory and reading back the actual resulting data from the memory, means for selectively programming a voltage level to be applied to a cell plate of the memory according to predetermined test requirements and means for storing an address of a defective memory cell. In addition the semiconductor device includes means for repairing a defective memory row or column in response to a signal received from the self test controller.

Internal voltage generator

Storage device and semiconductor device

BURN-IN TEST CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE

The circuit provides a function for an efficient and reliable burn-in test for detecting the failures of DRAM during the device production process. A voltage detecting circuit detects a high voltage applied to a specific pin beyond the external voltage and generates a burn-in ebable signal. Then, the first and second word lines are enabled according to a low address synchronously inputted with a low address strobe signal(RAS) and the burn-in enable signal. When the specific pin becomes a voltage below the external voltage, the burn-in signal becomes disabled and the first and second word lines are disabled accroding to the burn-in signal. Copyright 1997 KIPO ...

Device for controlling test mode using non-volatile ferroelectric memory

Column selection line controlling method and column selection line controlling circuit

THERMAL CODE OUTPUT CIRCUIT AND A SEMICONDUCTOR MEMORY DEVICE CAPABLE OF ACCURATELY MEASURING A THERMAL CODE

PURPOSE: A thermal code output circuit and a semiconductor memory device are provided to accurately measure a thermal code by outputting a strobing signal capable of strobing the thermal code through a pad. CONSTITUTION: A thermal code output circuit includes a pulse signal generating part(2), a thermal code output part(3), and a strobing signal output part(4). The pulse signal generating part generates a pulse signal after receiving a plurality of period signals in response to a test mode signal. The thermal code output part outputs a plurality of thermal codes in response to the pulse signal. The strobing signal output part selectively outputs a pulse signal or a reference voltage as a strobing signal in response to a test mode signal. COPYRIGHT KIPO 2010 ...

SEMICONDUCTOR MEMORY DEVICE

Semiconductor Memory Apparatus

Decision feedback equalizer

IMPEDANCE REGULATING CIRCUIT AND METHOD THEREOF, ESPECIALLY COMPRISING FIRST AND SECOND OUTPUT BUFFERS WITH VARIABLE IMPEDANCE

PURPOSE: An impedance regulating circuit and a method thereof are provided to regulate impedance of an output buffer of a DDR2 memory from a memory controller easily, by comprising an OCD(Off-Chip Driver) impedance regulation function. CONSTITUTION: A semiconductor device comprises an output buffer outputting a differential signal from an output pair. The impedance of the output buffer is set variably. A circuit disconnects two ports receiving the differential signal while the impedance of the semiconductor device is regulated. A comparator(12) compares the voltage of a shorted point with a reference voltage. A control circuit performs to change the impedance of the output buffer on the basis of the comparison result. © KIPO 2007 ...

SEMICONDUCTOR MODULE WITHOUT TIE BAR IN TAB PIN

According to the present invention, a semiconductor module without a tie bar in a tab pin is disclosed. The semiconductor module comprises: a printed circuit board having an integrated circuit chip loaded thereon; connecting terminals arranged at an edge part of the printed circuit board; via holes arranged in signal lines which correspondingly connect electrical connection pads of the integrated circuit chip to the connecting terminals; and plating lines connected to the via holes. The connecting terminals are plated by using the via holes of the printed circuit board connected to the plating lines. COPYRIGHT KIPO 2016 ...

MEMORY DEVICE HAVING PRECHARGE PART CAPABLE OF INDUCING SENSING STRESS ON TWIST BIT LINES EFFICIENTLY, WAFER BURN-IN TEST METHOD THEREOF, AND METHOD FOR ARRANGING THE PRECHARGE PART, ESPECIALLY CAPABLE OF TESTING SEVERAL CHIPS AT ONE TIME

PURPOSE: A memory device having a precharge part capable of inducing sensing stress on twist bit lines efficiently, a wafer burn-in test method thereof, and a method for arranging the precharge part are provided to induce sensing stress on adjacent bit lines without data collision on the twist bit line and to improve productivity of a wafer burn-in test by inducing the sensing stress on all word lines at one time. CONSTITUTION: A memory cell array(10,30) has at least more than one bit line pair comprising a bit line and a complementary bit line, and the bit line pair has a twist bit line structure. A precharge part(210,230) is connected between the adjacent bit lines belonging to the different bit line pair, and applies a first or a second bit line voltage to the adjacent bit lines. The first bit line voltage and the second bit line voltage are provided to the memory device(200) at each different level during a wafer burn-in test. © KIPO 2006 ...

MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE

MEMORY DEVICE AND MEMORY DEVICE TESTING SYSTEM

A memory device includes a control unit, a multiplexer, a parallelization unit, a data adjustment unit, a memory cell array, and an error detection unit. The control unit generates test mode signals and data adjustment signals in response to address signals and command signals. The multiplexer outputs clock signals as internal data signals when the test mode signals are activated. The parallelization unit generates parallelization signals by parallelizing bit values included in the internal data signals. The data adjustment unit generates bit line signals by inverting the parallelization signals based on the data adjustment signals and inversion control signals. The memory cell array stores bit line signals to the memory cells corresponding to address signals. The error detection unit outputs an error detection result of read signals read from the memory cells as an error detection signal. COPYRIGHT KIPO 2017 ...

SEMICONDUCTOR DEVICE PROVIDED WITH MEMORY

PURPOSE: A semiconductor device provided with a memory is provided to stably maintain a ground potential even when a plurality of word lines are driven at one time. CONSTITUTION: A semiconductor device provided with a memory includes a pair of memory cell arrays(10a,10b) and a precharge controller(12). Two memory cell arrays(10a,10b) are connected to a row decoder. Each of the memory cell arrays(10a,10b) has a plurality of memory cells MC arranged in rows and columns. The memory cells MC are connected to word lines WL extending from the row decoder and bit lines BL. Each of the bit lines BL has a pair of bits over which read or write data D, /D is transferred. The memory cell arrays(10a,10b) are obtained by dividing a memory cell array into two. Thus, word lines WL which are precharged at one time are divided into two groups. © KIPO 2002 ...

MEMORY SYSTEM AND A REFRESH CONTROL METHOD CAPABLE OF REDUCING REFRESH POWER

PURPOSE: A memory system and a refresh control method are provided to improve the performance of the memory system by performing a refresh operation according to refresh property information. CONSTITUTION: A semiconductor memory device(100) includes a plurality of memory cells. A memory controller(200) generates a special command to search refresh property information stored in the semiconductor memory device and controls the refresh operation of the semiconductor memory device. The semiconductor memory device outputs the refresh property information to the memory controller in response to the special command generated from the memory controller. COPYRIGHT KIPO 2013 ...

INVERSION CONTROL CIRCUIT OF DLL FOR PREVENTING INVERSION WITHIN RANGE OF DUTY ERROR MARGIN, CONTROL METHOD OF THE SAME, DLL USING THE SAME, AND SEMICONDUCTOR MEMORY DEVICE

PURPOSE: An inversion control circuit of a DLL(Delay Locked Loop), a control method of the same, a DLL using the same, and a semiconductor memory device are provided to prevent an inversion malfunction due to a duty error and control certainly a locking operation by determining a correct inversion by canceling the inversion within a range of a duty error margin. CONSTITUTION: A variable delay line part(120) is provided to generate a regeneration clock signal to follow a phase of a reception clock signal in response to a delay control signal. A phase detection part(130) is provided to generate a delay control signal and a phase difference detection signal corresponding to a phase difference between the regeneration clock signal and the reception clock signal. An inversion control part(140) is provided to output an inversion determination signal including a duty error margin of the regeneration clock signal as an inversion control signal according to a start signal by determining an inverting ...

Semiconductor device and driving method of semiconductor device

A memory cell includes a capacitor, a first transistor, and a second transistor whose off-state current is smaller than that of the first transistor. The first transistor has higher switching speed than the second transistor. The first transistor, the second transistor, and the capacitor are electrically connected in series. Accumulation of charge in the capacitor and release of charge from the capacitor are performed through the first transistor and the second transistor. In this manner, the power consumption of the semiconductor device can be reduced and data can be written and read at higher speed.

Semiconductor memory device

A trigger producing circuit provides a trigger signal. A delay circuit receives the trigger signal, and provides a delay signal produced by delaying the trigger signal. A clock counter receives clocks, counts the received clocks for a period from reception of the trigger signal to reception of the delay signal, and provides a result of the counting. A determining circuit stores a relationship between the number of clocks and a latency, and determines the latency corresponding to the result of counting provided from the clock counter. A latency register holds the determined latency. A WAIT control circuit externally provides a WAIT signal based on the latency held in the latency register.

A semiconductor device with a plurality of ground planes

A multi-chip module (MCM) with a plurality of ground planes/layers is provided. Each integrated circuit (IC) chip of the MCM has its own ground plane on a substrate in the MCM. This MCM structure may facilitate separate testing of each IC chip without affecting other chips and without being affected by other chips. This MCM structure also may facilitate testing of interconnects/connections between two or more chips.

Three dimensional memory device having embedded dynamic random access memory units

Embodiments of a three-dimensional (3D) memory device and a forming method thereof are disclosed. In an example, a 3D memory device comprises a first semiconductor structure, wherein the first semiconductor structure comprises peripheral circuits, an array of embedded dynamic random access memory (DRAM) units and a first bonding layer comprising a plurality of first bonding contacts. The 3D memory device further comprises a second semiconductor structure, wherein the second semiconductor structure comprises an array of 3D NAND memory strings and a second bonding layer comprising a plurality of second bonding contacts. The 3D memory device further comprises a bonding interface located between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts in the bonding interface.

Semiconductor device

PROGRAMMABLE LSI

Semiconductor device comprising a test structure

A semiconductor memory device comprising a test structure is disclosed. The semiconductor device includes a plurality of memory cells, word lines, bit lines, and test pads; the word lines including a first set and a second set of word lines, connected to a first and second word line test pad, respectively; the bit lines including a first set and a second set of bit lines, connected to a first and second bit line test pad, respectively. The first set of word lines and the first set of bit lines access a first set of memory cells, the first set of word lines and the second set of bit lines access a second set of memory cells, the second set of word lines and the first set of bit lines access a third set of memory cells, and the second set of word lines and the second set of bit lines access a fourth set of memory cells. By applying a predetermined set of test signals to the first and second word line test pads, and the first and second bit line test pads, the disturbance or interference among ...

Semiconductor memory device control method and semiconductor memory device

In a semiconductor memory device which requires a refresh operation, a control method stops supplying a word line voltage which is a boosted voltage higher than an external supply voltage, a memory array substrate voltage which is a negative voltage supplied to a semiconductor substrate, and a bit line precharge voltage for use in reproducing data held in memory cells for a predetermined period at the end of each refresh operation. In this event, voltage output terminals of the word line and memory array substrate voltages are respectively driven to a ground potential. For recovering these voltages, the delivery of the word line voltage is stopped until the memory array substrate voltage rises to some extent.

METHOD AND SYSTEM OF FAST CLEARING OF MEMORY USING A BUILT-IN SELF-TEST CIRCUIT

Systems, devices and methods for clearing memory using a built-in self-test circuit are disclosed. In one embodiment, a device for clearing memory using a built-in self-test circuit comprises a clear memory module added to a memory built-in self-test (MBIST) controller generating a signal for clearing one or more memory modules and one or more wrapper circuits with each wrapper circuit comprising an address generator module forwarding a range of addresses associated with the clearing the memory modules, a write data generator module forwarding a pattern of logical zeroes to the range of addresses and a finite state machine controlling writing the pattern to the range of addresses based on the signal for the clearing the memory modules.

256 Meg DYNAMIC RANDOM ACCESS MEMORY

Abstract not available! Abstract of correspondent: US6710630 A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded ...

MEMORY HAVING VARIABLE REFRESH CONTROL AND METHOD THEREFOR

A memory (10) has a memory array (12), a charge pump (18), a voltage regulator (20), a refresh control circuit (16), and a refresh counter (22). The charge pump (18) provides a substrate bias to the memory array (12). The voltage regulator (20) provides a pump enable signal for maintaining a voltage level of the substrate bias within upper and lower limits. The refresh control circuit (16) controls refresh operations. The refresh counter (22) is coupled to receive the pump enable signal, and in response, provides a refresh timing signal to the refresh control circuit (16) to control a refresh rate of the memory array (12). A programmable fuse circuit (26) is provided to program the refresh rate using the counter (22). The programmable fuse circuit (26) may be programmed during wafer probe testing or board level burn-in. A built-in self test (BIST) circuit (24) may be included to facilitate testing.

APPARATUS AND METHOD FOR SELECTIVELY CONFIGURING A MEMORY DEVICE USING A BI-STABLE RELAY

The disclosed embodiments of the present invention include a semiconductor memory apparatus having a selectable memory capacity. In one embodiment, a system includes input, output, and data storage devices, a processor coupled to the devices, a memory device coupled to the processor, and a configuration circuit interposed between the processor and the memory device to selectively couple lines in the address, control and data busses of the processor to lines in the address, control and data busses of the memory device. In another embodiment, a memory device includes an array coupleable to one or more busses of an external device and a configuration circuit between the array and the busses of the external device to selectively couple the busses to the memory cell array. In a particular embodiment, the configuration circuit includes one or more bi-stable relays, such as Micro-Electrical-Mechanical System (MEMS) relays.

A METHOD AND APPARATUS FOR SAMPLING DATA FROM A MEMORY

Falling edges of a column address strobe (CAS) signal (109) are used to cause dynamic random access memories (DRAMs, 100) to drive data corresponding to the current address onto a data bus coupled to the input of a set of latches (102). A memory latch data (MLAD) signal (112) is used to enable the set of latches. When the MLAD signal is asserted, the latches latch the data at the input in response to a falling edge of the CAS signal. When the MLAD signal is deasserted, the latch does not latch the data at the input in response to the falling edge of the CAS signal.

Semiconductor device having hierarchically structured bit lines and system including the same

To include memory mats each including a sense amplifier that amplifies a potential difference between global bit lines, a plurality of hierarchy switches connected to the global bit lines, and a plurality of local bit lines connected to the global bit lines via the hierarchy switches, and a control circuit that activates the hierarchy switches. The control circuit activates hierarchy switches that are located in the same distance from the sense amplifier along the global bit lines. According to the present invention, because there is no difference in the parasitic CR distributed constant regardless of a local bit line to be selected, it is possible to prevent the sensing sensitivity from being degraded.

Sacrifice read test mode

Testing methods and facilitating circuitry permit activation and latching of multiple word lines in a dynamic memory device in conjunction with external control over digit line equilibrate and activation of sense amplifiers. Such testing methods are adaptable for use prior to row repair or post row repair. Such testing methods permit controlled stressing of cell margin and beta ratio by selective coupling of one or more sacrificial rows to a digit line prior to sensing of data in a target row. Useful design and reliability information may be obtained through application of various embodiments of such testing methods.

Semiconductor memory and system

To fully evaluate a real signal line and a real memory cell adjacent to a dummy signal line and utilize dummy signal line as real signal line, a semiconductor memory includes at least one real signal line connected to real memory cells driven by a real driver and at least one dummy signal line outside the real signal line connected to dummy memory cells, driven by a dummy driver. Real driver and dummy driver drive the real signal line and the dummy signal line synchronous with a common timing signal generated by an operation control circuit. Consequently, a stress evaluation is also performable, e.g., on a real signal line outside of a memory cell array under the same condition of a real signal line on the inner side. Dummy signal line is driven using common timing signal and evaluated, thus being usable as a redundancy signal line to relieve failure.

Synchronous output buffer, synchronous memory device and method of testing access time

An output buffer includes an output terminal, a pull up module, a pull down module and an output latching module. The pull up module pulls up the output terminal to a first source voltage when the pull up module is active. The pull down module pulls down the output terminal to a second source voltage when the pull down module is active. The output latching module latches a data signal in response to a state of an output clock signal in a first operation mode. The output latching module latches the data signal in response to a leading edge of the output clock signal in a second operation mode. The output latching module drives the pull up module and the pull down module in response to the data signal latched by the output latching module, so that the output latching module outputs the data signal to the output terminal in a second operation mode.

Semiconductor device and method of screening the same

A semiconductor device comprising a plurality of circuit blocks to which various potentials, including at least one potential either raised or lowered, are assigned. The device further comprises means for selectively and reversely changing the potentials assigned to the circuit blocks.

Burn-in stress control circuit for a semiconductor memory device

A burn-in stress control circuit for an integrated memory device, such as DRAM, includes a first logic gate for receiving a burn-in enable signal and outputting an inverted burn-in enable signal, a resistor having a first terminal connected to the input terminal of the first logic gate, a first capacitor connected between the second terminal of the resistor and ground. A first transistor having a control terminal connected to the second terminal of the resistor and a first main terminal connected to a source voltage, is activated only when the burn-in enable signal is a high logic signal, thereby outputting the source voltage to a second main terminal of the first transistor. A second transistor having a control terminal connected to an output terminal of the first logic gate, a first main terminal connected to ground and a second main terminal connected to the second main terminal of the first transistor, is activated only when the burn-in enable signal is a low logic signal. Thus, peak ...

Source-clock-synchronized memory system and memory unit

A source-clock-synchronized memory system having a large data storage capacity per memory bank and a high mounting density. The invention includes a memory unit having a first memory riser board B1 mounted on a base board through a first connector C1 and a second memory riser board B2 mounted on the base board BB through a second connector C2. The first memory riser board has a plurality of first memory modules mounted on the front surface thereof and the second memory riser board has a plurality of second memory modules mounted on the front surface thereof. The first and second memory riser boards are arranged in such a way that the back surface of the first memory riser board faces the back surface of the second memory riser board. The invention further includes a board linking connector for connecting signal lines on the first memory riser board to corresponding signal lines on the second memory riser board.

Semiconductor memory device

Semiconductor memory device having cell array divided into a plurality of cell blocks

A semiconductor memory device includes a cell array having a plurality of memory cells grouped into a plurality of cell blocks and arranged in a matrix form, a plurality of word lines, a plurality of bit lines, bit line sense amplifiers (S/A), a cell block selection circuit, a plurality of data I/O lines, row decoders, a plurality of column selection signal lines, column decoders and a data buffer circuit. The data buffer circuit includes a first precharge circuit, connected to the data I/O lines, for precharging the data I/O lines to the same potential as a precharge potential of the bit lines, a second precharge circuit, connected to the data I/O lines, for precharging the data I/O lines to a potential different from the precharge potential of the bit lines, and selective drive circuit for generating control signals to be supplied to the first and second precharge circuit, and selectively driving the first and second precharge circuits to sense the data read out to the data I/O lines ...

Data transfer apparatus with large noise margin and reduced power dissipation

In a data transfer apparatus powered by first and second power supply voltages, a data output circuit generates first complementary output signals, a data transfer circuit having a large load capacitance transfers the first complementary output signals to generate second complementary output signals, and an amplifier circuit amplifies the second complementary output signals to generate third complementary output signals. A first transfer gate circuit is connected between the data output circuit and the data transfer circuit. A second transfer gate circuit is connected between the data transfer circuit and the amplifier circuit. The first, second and third complementary output signals are caused to be approximately at an intermediate level between the first and second voltages.

Auto-programmable current limiter to control current leakage due to bitline to wordline short

A method and structure for disconnecting shorted bitlines from a dynamic random access memory circuit includes supplying a precharge voltage to equalization lines in the integrated circuit, supplying a negative voltage to wordlines in the integrated circuit, activating equalization devices connected to the bitlines and the equalization lines and maintaining the precharge voltage and the negative voltage until a short between one of the bitlines and one of the wordlines causes a corresponding equalization device of the equalization devices to have a permanently elevated threshold voltage.

Semiconductor storage device and method of testing the same

A dynamic random access memory (DRAM) whose charge-holding characteristic regarding a leak of an electric charge through the bit line is tested in a short time is provided. The DRAM comprises a memory cell array including memory cells arranged at intersections of word lines and bit lines, plural sense amplifiers disposed at a pair of the bit lines, plural bit line pre-charge circuits for pre-charging and equalizing a potential in the pair of the bit lines, and a switching circuit for selecting an ordinary operation mode or a test mode. It further comprises a word line deactivator for deactivating all of word lines in the test mode, a sense amplifier deactivator for deactivating all of sense amplifiers in the test mode, and a bit line potential fixing circuit for fixing the bit lines to the same logic level of a high or a low level in the test mode.

Method and apparatus for reducing bleed currents within a DRAM array having row-to-column shorts

A DRAM memory array is disclosed that uses a current limiting circuit employing current feedback to clamp the current flow to reduced levels than were previously possible. The current limiting circuit comprises a long length, depletion mode transistor that has its gate voltage reduced when row-to-column shorts exist to limit the bleed current. An alternative embodiment uses a P-channel FET in series with the depletion mode transistor and has its gate tied to a negative supply and passes current until both digit lines approach approximately 0.3 Volts.

SEMICONDUCTOR MEMORY DEVICE HAVING BURN-IN TEST FUNCTION

Data invert jump instruction test for built-in self-test

A data invert jump instruction test for a built-in self-test of a memory device is provided. The data invert system comprises a read only memory (72) operable to store a plurality of test algorithms wherein at least one of the test algorithms includes a data invert jump instruction (160). Also included is a data invert circuit (178) coupled to the read only memory (72) and a toggle register (188) within the data invert circuit (178). The toggle register (188) is set to one when the data invert jump instruction (160) occurs for the first time in the test algorithm. This causes the data invert circuit (178) to output the inverse of the data inputted through the data invert circuit (178).

Semiconductor device with self refresh test mode

A semiconductor device (such as a DRAM) includes a memory array that has dynamic memory cells. In a self refresh test mode, a self refresh test mode controller monitors and/or controls various blocks and internal signals in the semiconductor device. The self refresh test mode controller may communicate with a remote testing device through various conductors including one or more DQ lines and/or one or more address lines. The self refresh test mode controller provides at least one or more of the following four functions: (1) the ability to control internal signals while in self refresh test mode; (2) the ability to monitor internal signals while in self refresh test mode; (3) the ability to put in a programmable delay, change the delay, or change internal timing while in self refresh test mode (add delay or make delay programmable, adjustable); (4) the ability to have the device do a device read in a self refresh test mode (the DQ pins may be used to read particular data on the row, while ...

MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME

A memory device includes a plurality of memory blocks, a setting circuit configured to set a first mode, in which a first number of memory blocks are refreshed at a time, and a second mode, in which a second number of memory blocks are refreshed at a time, under control of a memory controller, the second number being smaller than the first number, a storage circuit configured to store additional refresh information, and a refresh control unit configured to control the second number of memory blocks to be refreshed at a time whenever a refresh command is applied when the additional refresh information is deactivated, and to control the first number of memory blocks to be refreshed at a time whenever the refresh command is applied when the additional refresh information is activated in a case in which the second mode is set by the setting circuit.

Semiconductor integrated circuit having bonding optional function

Current consumption of an input unit with respect to a bonding option pad is reduced, and erroneous operation of a circuit connected to this bonding option pad is prevented. A boundary scan test circuit is selectively set to an operable or disabled state by a control gate according to a signal from a function set circuit that sets the operation mode according to a potential of a bonding pad. By particularly controlling the operable and disabled state of an input circuit located at the first stage of the test circuit, power consumption can be reduced and erroneous operation while the test circuit is disabled is prevented.

Address wrap function for addressable memory devices

The invention is a selectable function that permits the address portion of data words to be separated from the storable content portion and that address portion to be used for different purposes without disturbing the stored contents in the memory array. The invention may be viewed as a command capability that permits analysis of signals for errors in such items as addresses, impedance calibration, timing, and component drift that develop in and between regions of an overall memory array. Techniques are advanced involving data responsive selectable array circuitry modification for such operations as address correctness verification, machine timing and component drift correction purposes. The principles are illustrated with memory systems built of Synchronous Dynamic Random Access Memory with Double Data Rate (SDRAM-DDR) elements.

Semiconductor memory, system, and operating method of semiconductor memory

Partial refresh information indicating enabling/disabling of a refresh operation is set according to an external input and is output as a partial set signal. A refresh request signal is output periodically corresponding to a memory block for which a refresh operation is enabled. The partial set signal is masked so as to enable a refresh operation for all of the memory blocks during a period in which the partial refresh information is changed by the external input. Thus, it is possible to prevent disabling of a refresh operation in response to a refresh request even when timing of changing the partial refresh information and timing of occurrence of the refresh request signal overlap. Consequently, the refresh operation can be executed securely, and malfunctioning of the semiconductor memory can be prevented.

Programmable LSI

A low-power programmable LSI that can perform configuration (dynamic configuration) at high speed and can quickly start is provided. The programmable LSI includes a plurality of logic elements and a memory element for storing configuration data to be input to the plurality of logic elements. The plurality of logic elements each include a configuration memory. Each of the plurality of logic elements performs different arithmetic processing and changes an electrical connection between the logic elements in accordance with the configuration data stored in the configuration memory. The memory element is formed using a storage element including a transistor whose channel is formed in an oxide semiconductor layer and a node set in a floating state when the transistor is turned off.

Semiconductor device with impedance control circuit

A semiconductor device includes an output impedance control circuit, connected to a ZQ pad and an output buffer circuit, for controlling an impedance of the output buffer circuit according to an impedance of an external resistor connected with the ZQ pad.

Apparatus and method for reducing test resources in testing DRAMS

An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.

METHOD FOR OPERATING SEMICONDUCTOR DEVICE

Provided is a highly reliable semiconductor device, a semiconductor device with a reduced circuit area, a memory element having favorable characteristics, a highly reliable memory element, or a memory element with increased storage capacity per unit volume. A semiconductor device includes a capacitor and a switching element. The capacitor includes a first electrode, a second electrode, and a dielectric. The dielectric is positioned between the first electrode and the second electrode. The switching element includes a first terminal and a second terminal. The first terminal is electrically connected to the first electrode. The following steps are sequentially performed: a first step of turning on the switching element in a first period, a second step of turning off the switching element in a second period, and a third step of turning on the switching element in a third period.

Semiconductor memory device

Switch MOSFETs are interposed between a sense amplifier disposed in a dynamic RAM and complementary bit lines: after signal voltages were read out by the selecting operations of the word lines from a plurality of dynamic memory cells selected, to the plurality of pairs of complementary bit lines in accordance with their individual storage informations, the switch control signal of the switch MOSFETs is changed from a select level to a predetermined intermediate level. The switch MOSFETs, as fed with the intermediate potential at their gates, are turned ON as a result that sense nodes are set to one level in accordance with the amplifying operations of the sense amplifier. An amplification signal generated by the amplifying operation is transmitted through the column select circuit to input/output lines in response to the column select signal, and the switch control signal is returned from the intermediate potential level to the select level in response to the selecting operation of the ...

Semiconductor device and method of testing the same

An object is to provide a semiconductor device in which it is possible to determine whether or not a minute delay time given by a delay circuit is within a specified value or not, and a method of testing the semiconductor device. In response to a data strobe signal TDQS for testing, the delay circuits DC0 and DC1 produce delay data strobe signals IDQS0 and IDQS1 delayed by delay times DT0 and DT1. Outputted as a reverse signal from the inverter INV0, is a reverse data strobe signal RIDQS0 in response to the delay data strobe signal IDQS0, and delayed by an allowable delay time IT. Inputted into the NAND gate ND0, are the reverse data strobe signal RIDQS0 and the delay data strobe signal IDQS1. When, in comparison with the phase of the delay data strobe signal IDQS0, the phase of the delay data strobe signal IDQS1 is delayed by the allowable delay time IT or more, a pulse signal PL0 is not outputted from the NAND gate ND0.

Method and apparatus for reducing bleed currents within a DRAM array having row-to-column shorts

A DRAM memory array is disclosed that uses a current limiting circuit employing current feedback to clamp the current flow to reduced levels than were previously possible. The current limiting circuit comprises a long length, depletion mode transistor that has its gate voltage reduced when row-to-column shorts exist to limit the bleed current. An alternative embodiment uses a P-channel FET in series with the depletion mode transistor and has its gate tied to a negative supply and passes current until both digit lines approach approximately 0.3 Volts.

1S-1C DRAM WITH A NON-VOLATILE CBRAM ELEMENT

One embodiment of a memory device comprises a selector and a storage capacitor in series with the selector. A further embodiment comprises a conductive bridging RAM (CBRAM) in parallel with a storage capacitor coupled between the selector and zero volts. A plurality of memory devices form a 1S-1C or a 1S-1C-CBRAM cross-point DRAM array with 4F2 or less density.

Semiconductor memory device having redundancy function

The semiconductor memory device includes normal word lines, spare word lines and bit lines. Space between the spare word lines is made wider than the space between the normal word lines. Further, the space between the normal word line and the spare word line is also made wider. Thus possibility of contact defect caused by a foreign matter in the steps of manufacturing can be reduced. Further, the size of the storage node of a spare memory cell is made larger than that of the storage node of a normal memory cell. Thus capacitance of the spare memory cell can be increased. Thus possibility of defects in spare memory cells is reduced ensuring repairment.

Semiconductor memory device

A semiconductor memory device realizing a reduced cycle time while improving the ease of use is to be provided. Where a memory cell requires a periodic refresh action to hold stored information, a time multiplexing mode of performing, when a first memory operation on any memory cell to read or write stored information or information to be stored and a second memory operation, having a different address designation from the first memory operation, or a refresh operation compete for the same time segment, the second memory operation before or after such first memory operation, wherein the minimum access time needed for the first memory operation and the second memory operation or the refresh operation performed before or after the first memory operation is set shorter than the sum of the length of time required for the first memory operation and that required for the second memory operation or the refresh operation on condition that sets of information stored in the memory cells are not mutually ...

Semiconductor memory device having a plurality of low power consumption modes

A semiconductor memory device that decreases power consumption and increases performance. The semiconductor memory device includes a plurality of memory cells that undergo refreshing to maintain data. The semiconductor memory device includes a normal operation mode for performing normal operation with the memory cells, and a plurality of low power consumption modes for decreasing power consumption when the semiconductor memory device is in a standby state. The semiconductor memory device includes a mode setting circuit that sets one of the low power consumption modes.

MEMORY AND MEMORY SYSTEM INCLUDING THE SAME

A memory includes a plurality of word lines each of which are connected to one or more memory cells, an address detection unit suitable for detecting a target address of a target word line among the plurality of word lines, wherein the target word line has an activation history satisfying a predetermined condition, and a control unit suitable for activating one or more word line among the plurality of word lines each time a refresh command is applied, and activating one or more adjacent word lines in response to a refresh command after detection of the target address, wherein the adjacent word line is adjacent to the target word line and identified by the target address.

Circuits and methods of temperature compensation for refresh oscillator

A memory device has refresh cycles to refresh memory cells of the memory device. The time interval between one refresh cycle to the next refresh cycle is a refresh interval. The refresh interval depends on a frequency of an oscillating signal. A refresh timer adjusts the frequency of the oscillating signal based on changes in the temperature to adjust the refresh interval.

MEMORY AND MEMORY SYSTEM INCLUDING THE SAME

A memory including a first cell block comprising a plurality of first word line groups, and one or more first redundancy word line groups each corresponding to one hit signal of a plurality of hit signals; a second cell block comprising a plurality of second word line groups, and one or more second redundancy word line groups each corresponding to one hit signal of the plurality of hit signals; and a control unit suitable for selecting a cell block and a word line in response to a first input address and refreshing a selected word line based on an input address inputted after the first input address, while refreshing one or more adjacent word lines adjacent to a first selected word line, which is selected by the first input address, in response to the first input address and the hit signals when the first selected word line is adjacent to a redundancy word line, wherein the first input address is first inputted in a target refresh section.

MEMORY DEVICE AND SEMICONDUCTOR DEVICE USING THE SAME

A memory device whose speed at the time of operation such as writing or reading is high and whose number of semiconductor elements per memory cell is small is provided. The memory device includes a control unit, an arithmetic unit, and a buffer memory device. The buffer memory device stores data sent from a main memory device and/or the arithmetic unit, in accordance with an instruction from the control unit. The buffer memory device includes a plurality of memory cells. The memory cells each include a transistor including a channel formation region including an oxide semiconductor, and a memory element to which charge with an amount in accordance with a value of the data is supplied through the transistor. Further, a data retention time of the memory cell corresponding to a valid bit is shorter than a data retention time of the memory cell corresponding to a data field.

Self-Refresh Based Power Saving Circuit and Method

A circuit includes a memory interface control circuit and a self-refresh adjustable impedance driver circuit having at least one adjustable impedance circuit. The memory interface control circuit selectively provides an impedance control signal based on memory self-refresh information. The self-refresh adjustable impedance driver circuit adjusts an impedance value of the adjustable impedance circuit in response to the impedance control signal. In addition, the self-refresh adjustable impedance driver circuit provides a memory interface signal based on the memory self-refresh information.

MEMORY DEVICE AND SEMICONDUCTOR DEVICE

A memory device in which data can be retained for a long time is provided. The memory device includes a memory element and a transistor which functions as a switching element for controlling supply, storage, and release of electrical charge in the memory element. The transistor includes a second gate electrode for controlling the threshold voltage in addition to a normal gate electrode. Further, the off-state current of the transistor is extremely low because an active layer thereof includes an oxide semiconductor. In the memory device, data is stored not by injection of electrical charge to a floating gate surrounded by an insulating film at high voltage but by control of the amount of electrical charge of the memory element through the transistor whose off-state current is extremely low.

Write control signal generation circuit, semiconductor IC having the same and method of driving semiconductor IC

A write control signal generation circuit includes a delay/comparison/transmission block that outputs one of a delayed write command signal and a write command signal according to a test mode signal, and a control signal generation unit that generates a write control signal by delaying the output of the delay/comparison/transmission block corresponding to a variable amount of delay.

Sеmiсоnduсtоr mеmоrу, sуstеm, аnd оpеrаting mеthоd оf sеmiсоnduсtоr mеmоrу

Раrtiаl rеfrеsh infоrmаtiоn indiсаting еnаbling/disаbling оf а rеfrеsh оpеrаtiоn is sеt ассоrding tо аn ехtеrnаl input аnd is оutput аs а pаrtiаl sеt signаl. А rеfrеsh rеquеst signаl is оutput pеriоdiсаllу соrrеspоnding tо а mеmоrу blосk fоr whiсh а rеfrеsh оpеrаtiоn is еnаblеd. Тhе pаrtiаl sеt signаl is mаskеd sо аs tо еnаblе а rеfrеsh оpеrаtiоn fоr аll оf thе mеmоrу blосks during а pеriоd in whiсh thе pаrtiаl rеfrеsh infоrmаtiоn is сhаngеd bу thе ехtеrnаl input. Тhus, it is pоssiblе tо prеvеnt disаbling оf а rеfrеsh оpеrаtiоn in rеspоnsе tо а rеfrеsh rеquеst еvеn whеn timing оf сhаnging thе pаrtiаl rеfrеsh infоrmаtiоn аnd timing оf оссurrеnсе оf thе rеfrеsh rеquеst signаl оvеrlаp. Соnsеquеntlу, thе rеfrеsh оpеrаtiоn саn bе ехесutеd sесurеlу, аnd mаlfunсtiоning оf thе sеmiсоnduсtоr mеmоrу саn bе prеvеntеd.

Sеmiсоnduсtоr mеmоrу, sуstеm, аnd оpеrаting mеthоd оf sеmiсоnduсtоr mеmоrу

Раrtiаl rеfrеsh infоrmаtiоn indiсаting еnаbling/disаbling оf а rеfrеsh оpеrаtiоn is sеt ассоrding tо аn ехtеrnаl input аnd is оutput аs а pаrtiаl sеt signаl. А rеfrеsh rеquеst signаl is оutput pеriоdiсаllу соrrеspоnding tо а mеmоrу blосk fоr whiсh а rеfrеsh оpеrаtiоn is еnаblеd. Тhе pаrtiаl sеt signаl is mаskеd sо аs tо еnаblе а rеfrеsh оpеrаtiоn fоr аll оf thе mеmоrу blосks during а pеriоd in whiсh thе pаrtiаl rеfrеsh infоrmаtiоn is сhаngеd bу thе ехtеrnаl input. Тhus, it is pоssiblе tо prеvеnt disаbling оf а rеfrеsh оpеrаtiоn in rеspоnsе tо а rеfrеsh rеquеst еvеn whеn timing оf сhаnging thе pаrtiаl rеfrеsh infоrmаtiоn аnd timing оf оссurrеnсе оf thе rеfrеsh rеquеst signаl оvеrlаp. Соnsеquеntlу, thе rеfrеsh оpеrаtiоn саn bе ехесutеd sесurеlу, аnd mаlfunсtiоning оf thе sеmiсоnduсtоr mеmоrу саn bе prеvеntеd.

Semiconductor device and electronic component

A semiconductor device capable of retaining a signal sensed by a sensor element is provided. The semiconductor device includes a sensor element, a first transistor, a second transistor, and a third transistor. One electrode of the sensor element is electrically connected to a first gate. The first gate is electrically connected to one of a source and a drain of the third transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor. A semiconductor layer includes a metal oxide.

Phase controlled high speed interfaces

DYNAMIC MEMORY AND METHOD FOR TESTING A DYNAMIC MEMORY

The invention relates to a dynamic memory comprising a memory cell array (10), a test controller (12) for testing the memory cell array (10) and an oscillator (14) for controlling the refreshing of said memory cell array (10). According to the invention, said memory includes means (16) for using the oscillator (14) as a time base for the test controller. Hereby, a slow time base is achieved, which may be used for different self-tests of the memory.

Memory embedded logic integrated circuit mounting memory circuits having different performances on the same chip

A semiconductor integrated circuit includes a first DRAM circuit (13-1) having a first memory cell array having a plurality of memory cells each including a first MOS transistor, and a first potential generating circuit which generates at least one potential used to operate the plurality of memory cells in the first memory cell array, the first DRAM circuit being formed in a semiconductor chip (11), and a second DRAM circuit (13-2) having a second memory cell array having a plurality of memory cells each including a second MOS transistor different in characteristic from the first MOS transistor, and a second potential generating circuit which generates at least one potential used to operate the plurality of memory cells in the second memory cell array, the second DRAM circuit being formed in the semiconductor chip.

Semiconductor memory device and test method thereof

Example embodiments disclose a semiconductor memory device and a test method thereof. The semiconductor memory device includes a memory cell array that provides first and second data groups at a first data rate and an output circuit, in a normal mode of operation, serially outputs the first and second data groups at a first data rate on an external terminal. In a test mode of operation, the output circuit outputs the first data group or the second data group at a second data rate on the external terminal in response to control signals, without switching the test mode. The second data rate may be lower than the first data rate.

Memory systems and memory modules

One embodiment of the present invention sets forth a memory module that includes at least one memory chip, and an intelligent chip coupled to the at least one memory chip and a memory controller, where the intelligent chip is configured to implement at least a part of a RAS feature. The disclosed architecture allows one or more RAS features to be implemented locally to the memory module using one or more intelligent register chips, one or more intelligent buffer chips, or some combination thereof. Such an approach not only increases the effectiveness of certain RAS features that were available in prior art systems, but also enables the implementation of certain RAS features that were not available in prior art systems.

Embedded DRAM having Low Power Self-Correction Capability

Apparatuses and methods for low power combined self-refresh and self-correction of a Dynamic Random Access Memory (DRAM) array. During a self-refresh cycle, a first portion of a first row of the DRAM array is accessed and analyzed for one or more errors, wherein a bit width of the first portion is less than a bit width of the first row. If one or more errors are detected, the one or more errors are corrected to form a corrected first portion. The corrected first portion is selectively written back to the first row. If no errors are detected in the first portion, a write back of the first portion to the first row is prevented.

Bit-replacement technique for dram error correction

The disclosed embodiments provide a dynamic memory device, comprising a set of dynamic memory cells and a set of replacement dynamic memory cells. The set of replacement dynamic memory cells includes data cells which contain replacement data bits for predetermined faulty cells in the set of dynamic memory cells, and address cells which contain address bits identifying the faulty cells, wherein each data cell is associated with a group of address cells that identify an associated faulty cell in the set of dynamic memory cells. The dynamic memory device also includes a remapping circuit, which remaps a faulty cell in the set of dynamic memory cells to an associated replacement cell in the set of replacement cells.

Semiconductor memory device and test method thereof

A semiconductor memory device includes a plurality of memory cells; a data comparison section configured to compare input data to be stored in the memory cells with output data outputted from the memory cells in a test operation, an address storage section configured to store addresses corresponding to defected memory cells of the memory cells in response to a comparison result of the data comparison section, and a comparison period control section configured to generate a period control signal for controlling an activation period of the data comparison section.

Semiconductor device and driving method thereof

In a memory module including a memory cell array including memory cells arranged in matrix, each including a first transistor using an oxide semiconductor and a first capacitor; a reference cell including a p-channel third transistor, a second capacitor, and a second transistor using an oxide semiconductor; and a refresh timing detection circuit including a resistor and a comparator, wherein when a potential is supplied to the first capacitor through the first transistor, a potential is supplied to the second capacitor through the second transistor, wherein a drain current value of the third transistor is changed in accordance with the potential stored in the second capacitor, and wherein when the drain current value of the third transistor is higher than a given value, a refresh operation of the memory cell array and the reference cell are performed.

Advanced memory device having improved performance, reduced power and increased reliability

An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

Memory system and refresh control method thereof

A memory system and a refresh control method thereof are provided. The memory system includes a semiconductor memory device including a plurality of memory cells and a memory controller configured to generate a special command for searching for refresh information stored in the semiconductor memory device and to control a refresh operation of the semiconductor memory device. The semiconductor memory device is configured to output the refresh information to the memory controller in response to the special command generated by the memory controller.

Semiconductor memory cell array and semiconductor memory device having the same

A semiconductor memory cell array includes a plurality of bit-lines, a plurality of word-lines, a plurality of memory cells, a plurality of dummy memory cells, a plurality of dummy bit-lines, and a plurality of dummy word-lines. The dummy bit-lines are in outer regions of the bit-lines. The dummy word-lines are in outer regions of the word-lines. The dummy bit-lines are maintained in a floating state. The dummy word-lines retain a turn-off voltage

Memory system

A memory system includes: a controller configured to provide a hidden auto refresh command; and a memory configured to perform a refresh operation in response to the hidden auto refresh command. The controller and the memory communicate with each other so that each refresh address of the controller and the memory has the same value as each other.

Memory device, method of operating the same, and apparatus including the same

A method of operating a memory device includes masking at least one bank among a plurality of banks in response to a mode register writing command; and performing a refresh operation on a plurality of rows in one of unmasked banks in response to a first per-bank refresh command.

Refresh circuit of a semiconductor memory device and refresh control method of the semiconductor memory device

A refresh circuit and a semiconductor memory device including the refresh circuit are disclosed. The refresh circuit includes a mode register, a refresh controller and a multiplexer circuit. The mode register generates a mode register signal having information relating to a memory bank on which a refresh operation is to be performed. The refresh controller generates a self-refresh active command and a self-refresh address based on a self-refresh command and an oscillation signal. The multiplexer circuit may include a plurality of multiplexers. Each of the multiplexers selects one of an active command and the self-refresh active command in response to bits of the mode register signal. Each of the multiplexers generates a row active signal based on the selected command, and selects one of an external address and the self-refresh address to generate a row address.

Semiconductor memory device changing refresh interval depending on temperature

A semiconductor memory device includes a memory core circuit having memory cells for storing data, a circuit configured to refresh the memory core circuit at a refresh interval, a temperature detecting unit configured to detect temperature, and a control circuit configured to shorten the refresh interval immediately in response to detection of a predetermined temperature rise by the temperature detecting unit and to elongate the refresh interval after refreshing every one of the memory cells at least once in response to detection of a temperature drop by the temperature detecting unit.

Semiconductor memory device for controlling write recovery time

A semiconductor memory device includes a CAS latency mode detecting means for outputting a CAS latency control signal in response to a CAS latency mode; and an auto-precharge control means for controlling timing of an auto-precharge operation in response to the CAS latency control signal.

INTEGRATED CIRCUIT DEVICE HAVING PROGRAMMABLE INPUT CAPACITANCE

An embodiment is directed to an integrated circuit device having programmable input capacitance. For example, a programmable register of a memory device may store a value representative of an adjustment to the input capacitance value of a control pin. An embodiment is directed to controlling the skew of a synchronous memory system by allowing programmability of the lighter loaded pins in order to increase their load to match the more heavily loaded pins. By matching lighter loaded pins to more heavily loaded pins, the system exhibits improved synchronization of propagation delays of the control and address pins. In addition, an embodiment provides the ability to vary the loading depending on how many ranks are on the device. 1. An integrated circuit device comprising:a pin to receive an external signal; anda programmable register that stores a value that represents an adjustment to an input capacitance of the pin.2. The integrated circuit device of claim 1 , wherein the external signal is a control signal.3. The integrated circuit device of claim 1 , wherein the value that represents the adjustment is based at least in part on a rank configuration associated with the integrated circuit device.4. The integrated circuit device of claim 3 , wherein the adjustment is an increase in capacitance loading.5. The integrated circuit device of claim 1 , wherein the integrated circuit device is a dynamic random access memory (DRAM) device.6. A memory device claim 1 , comprising:a first pin having a first load that is substantially fixed; anda second pin having a second load that is programmably adjustable.7. The memory device of claim 6 , wherein the second pin is configured to receive a control signal.8. The memory device of claim 6 , wherein the second load is based at least in part on a rank configuration associated with the memory device.9. The memory device of claim 6 , wherein the second load is programmably increased.10. The memory device of claim 6 , wherein the first ...

Semiconductor device having plural data input/output terminals

Disclosed herein is a device that includes a plurality of first terminals; a first circuit including a plurality of first nodes; a buffer circuit including a plurality of second nodes connected to the first terminals through a plurality of first interconnection lines, respectively, and a plurality of third nodes connected to the first nodes of the first circuit through a plurality of second interconnection lines, respectively; and a second circuit configured to perform at least one of first and second operations. The first operation is such that a plurality of first signals, that appear respectively on the first interconnection lines, are outputted in series, and the second operation is such that a plurality of second signals, that are supplied in series, are transferred respectively to the first interconnection lines.

Controller to detect malfunctioning address of memory device

A controller including a non-volatile memory to store a repair address, and a memory control unit operatively coupled with the non-volatile memory. The memory control unit comprising a memory test function configured to detect a malfunctioning address of primary data storage elements within a memory device. The memory device being another semiconductor device separate from the controller. The memory test function configured to store the repair address in the non-volatile memory, the repair address indicating the malfunctioning address of the primary data storage element.

SEMICONDUCTOR DEVICE WITH MEMORY DEVICE

A memory mat () includes a main body portion () that includes a first capacitor (A), a linear conductive film () that is formed between the main body portion () and a peripheral circuit (), and a second capacitor (B) that is formed to be in contact with the conductive film () at a bottom of the second capacitor (B). The first capacitor (A) is in contact with a contact layer () at a bottom of the first capacitor (A). 1. A semiconductor device comprisinga memory mat and a peripheral circuit that is formed around said memory mat,wherein said memory mat includes:a main body portion that includes a first capacitor;a linear conductive film that is formed between the main body portion and said peripheral circuit; anda second capacitor that is formed to be in contact with the conductive film at a bottom of the second capacitor, andthe first capacitor is formed to be in contact with a contact layer at a bottom of the first capacitor.2. The semiconductor device according to claim 1 , whereinthe main body portion includes a bit line that extends along a first direction in a plane with said memory mat, andthe conductive film is formed along a second direction orthogonal to the first direction between the main body portion and said peripheral circuit in the first direction.3. The semiconductor device according to claim 2 , further comprisinga dummy bit line that extends along the first direction between the main body portion and said peripheral circuit in the second direction.4. The semiconductor device according to claim 2 , wherein at least one end of the conductive film is bent away from said peripheral circuit in the first direction.5. The semiconductor device according to claim 1 , wherein the conductive film is formed so as to surround the main body portion.6. The semiconductor device according to claim 1 , whereinthe conductive film includes:a first conductive film that is formed along a second direction orthogonal to a first direction between the main body portion and ...

DRAM MEMORY CELLS RECONFIGURED TO PROVIDE BULK CAPACITANCE

A semiconductor device includes a Dynamic Random Access Memory (DRAM) memory array. The DRAM memory array includes a plurality of DRAM memory cells. Each of the DRAM memory cells includes a capacitor. Switching circuitry within the semiconductor device is configured to be switched to a state in which the switching circuitry connects capacitors of at least two of the DRAM memory cells together to provide a bulk capacitance between a first node and a second node. 1. A semiconductor device comprising:a plurality of DRAM memory cells, each of the DRAM memory cells comprising a capacitor; andswitching circuitry configured to be switched to a state in which the switching circuitry connects capacitors of at least two of the DRAM memory cells together to provide a bulk capacitance between a first node and a second node,wherein the at least two DRAM memory cells are repurposed in the state.2. The semiconductor device of claim 1 , wherein when the switching circuitry is switched to said state claim 1 , the capacitors of the at least two DRAM memory cells are connected in series.3. The semiconductor device of claim 1 , wherein when the switching circuitry is switched to said state claim 1 , the capacitors of the at least two DRAM memory cells are connected in parallel.4. The semiconductor device of claim 1 , wherein each of the at least two DRAM memory cells further comprises a transistor capable of being turned on or off based on a gate voltage.5. The semiconductor device of claim 4 , wherein the switching circuitry comprises a circuit for controlling the gate voltage claim 4 , and wherein when the switching circuitry is switched to said state claim 4 , the gate voltage is set to and held at a level that turns on the transistor.6. The semiconductor device of claim 4 , wherein the transistor of each of the at least two DRAM memory cells is a MOS transistor.7. The semiconductor device of claim 4 , wherein for each of the at least two DRAM memory cells claim 4 , the respective ...

Apparatus and method for hidden-refresh modification

A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when the control signal is deasserted for a predetermined duration. A hidden-refresh controller couples to an array of dynamic memory cells during a hidden-refresh of the array of dynamic memory cells. The hidden-refresh controller is further configured to monitor a control signal identifying a request from a processor at a memory device and refresh the dynamic data at a first refresh rate when the control signal is asserted. The hidden-refresh controller is further configured to refresh the dynamic data at a second refresh rate when the control signal is deasserted for a predetermined duration.

Valid command detection based on stack position identifiers in memory devices configured for stacked arrangements

Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.

MEMORY DEVICE COMPRISING ELECTRICALLY FLOATING BODY TRANSISTOR

A semiconductor memory instance is provided that includes an array of memory cells. The array includes a plurality of semiconductor memory cells arranged in at least one column and at least one row. Each of the semiconductor memory cells includes a floating body region configured to be charged to a level indicative of a state of the memory cell. Further includes are a plurality of buried well regions, wherein each of the buried well regions can be individually selected, and a decoder circuit to select at least one of the buried well regions. 120-. (canceled)21. A method of operating an array of semiconductor memory cells , the array comprising at least two memory sub-arrays , each memory sub-array comprising:a plurality of said semiconductor memory cells arranged in at least one column and at least one row, each said semiconductor memory cell comprising:a floating body region configured to be charged to a level indicative of a state of the memory cell;a first region in electrical contact with said floating body region, located at a surface of said floating body region;a second region in electrical contact with said floating body region, located at a surface of said floating body region, spaced apart from said first region;a gate positioned between said first region and said second region; anda third region in electrical contact with said floating body region, located below said floating body region;said method comprising:selecting at least one of said at least two memory sub-arrays; andoperating said at least one of said memory sub-arrays independently of operation of a remainder of said at least two memory sub-arrays not selected.22. The method of operating an array of semiconductor memory cells of claim 21 , wherein said selecting at least one of said at least two memory sub-arrays is performed by applying a first bias condition to said at least one of said memory sub-arrays and a second bias condition to at least one of said at least two memory sub-arrays not ...

METHOD OF FORMING SEMICONDUCTOR MEMORY DEVICE

A method of forming semiconductor memory device includes the following steps. Firstly, a substrate is provided and the substrate includes a cell region. Then, plural bit lines are disposed within the cell region along a first direction, with each of the bit line includes a tri-layered spacer structure disposed at two sides thereof. Next, plural of first plugs are formed within the cell region, with the first plugs being disposed at two sides of each bit lines. Furthermore, plural conductive patterns are formed in alignment with each first plugs. Following theses, a chemical reaction process is performed to modify the material of a middle layer of the tri-layered spacer structure, and a heat treatment process is performed then to remove the modified middle layer, thereto form an air gap layer within the tri-layered spacer structure. 1. A method of forming a semiconductor memory device , comprising:providing a substrate, the substrate comprising a periphery region and a memory cell region;forming a plurality of bit lines extended along a first direction on the substrate, within the memory cell region, wherein a spacer structure is formed at two sides of each of the bit lines and the spacer structure comprises a tri-layer structure;forming a plurality of first plugs on the substrate within the memory cell region, at two sides of each of the bit lines;forming a plurality of conductive patterns, the conductive patterns being in alignment and directly in contact with the first plugs;after forming the conductive patterns, performing a chemical reaction process, to transform a second spacer of the tri-layer structure of the spacer structure to form a transformed second spacer; andremoving the transformed second spacer to form an air-gap layer in the spacer structure.2. The method of forming a semiconductor memory device according to claim 1 , further comprising:forming a gate structure on the substrate within the periphery region, the gate structure extended along a second ...

SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE

A memory in which a write cycle time is longer than time for one clock cycle can be mounted on a processor. The processor includes a processor core, a bus, and a memory section. The memory section includes a first memory. A cell array of the first memory is composed of gain cells. The processor core is configured to generate a write enable signal. The first memory is configured to generate a wait signal on the basis of the write enable signal. The processor core is configured to delay access to the memory section by time for n clock cycles, on the basis of the wait signal. (n+) clock cycles can be assigned to a write cycle of the first memory. 1. A semiconductor device comprising:a memory section comprising a memory cell, the memory section configured to generate a wait signal; anda processor core configured to delay access to the memory section on the basis of the wait signal,wherein a write cycle time of the memory cell is longer than a read cycle time of the memory cell.2. The semiconductor device according to claim 1 ,wherein the memory cell comprises a transistor, andwherein a channel formation region of the transistor comprises an oxide semiconductor.3. The semiconductor device according to claim 1 , wherein the memory section comprises at least one of an SRAM claim 1 , a flash memory claim 1 , an ferroelectric RAM claim 1 , a magnetoresistive RAM claim 1 , a resistance RAM claim 1 , and a phase change RAM.4. A semiconductor device comprising: a clock generator configured to generate a first clock signal and a second clock signal; and', 'a memory section comprising a memory cell,, 'a microcontroller unit comprisingwherein frequencies of the first clock signal and the second clock signal are different from each other, andwherein a first write cycle time of the memory cell when the microcontroller unit is operated by the first clock signal is longer than a second write cycle time of the memory cell when the microcontroller unit is operated by the second clock ...

Compact Semiconductor Memory Device Having Reduced Number of Contacts, Methods of Operating and Methods of Making

An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link. 154-. (canceled)55. A semiconductor memory array comprising: a floating body region configured to store data as charge therein to define a state of said memory cell selected from at least first and second states, wherein current flow through said memory cell is larger when said memory cell is in one of said first and second states than when said memory cell is in the other of said first and second states; and', 'a back-bias region configured to inject charge into or extract charge out of said floating body region to maintain said state of said memory cell;, 'a plurality of links or strings of semiconductor memory cells, wherein each of said semiconductor memory cells includeswherein said back-bias region is commonly connected to at least two of said semiconductor memory cells.56. The semiconductor memory array of claim 55 , wherein each of said semiconductor memory cells comprises first and second conductive regions interfacing with said floating body region.57. The semiconductor memory array of claim 56 , wherein each of said semiconductor memory cells further comprises a gate region positioned between said first and second conductive regions.58. The semiconductor memory array of claim 56 , wherein said floating body region has a first conductivity type selected from p-type and n-type conductivity types claim 56 , said first conductive region claim 56 , said second conductive region claim 56 , and said back-bias region have a second conductivity type selected from said p-type and n-type conductivity types claim 56 , said second conductivity type being ...

Method for forming dynamic random access memory structure

The present invention provides a method for forming a dynamic random access memory (DRAM) structure, the method including: firstly, a substrate is provided, a cell region and a peripheral region are defined on the substrate, a plurality of buried word lines is then formed in the cell region of the substrate, next, a shallow trench isolation structure is formed in the peripheral region adjacent to the cell region, wherein a concave top surface is formed on the shallow trench isolation structure, afterwards, a first dummy bit line gate is formed within the shallow trench isolation structure of the peripheral area, and a second dummy bit line gate is formed in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.

REFRESH VERIFICATION CIRCUIT, SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM

A refresh verification circuit may include a filtering circuit configured to receive a refresh pulse and to generate a filtering pulse in response to a duration of the enable period of the refresh pulse. 1. A refresh verification circuit comprising:a filtering circuit configured to receive a refresh pulse and to generate a filtering pulse in response to a duration of the enable period of the refresh pulse.2. The refresh verification circuit according to claim 1 , wherein during an enable period of the refresh pulse coupling of a memory cell and a sense amplifier is allowed.3. The refresh verification circuit according to claim 1 , wherein during an enable period of the refresh pulse an operation for recovering a potential of a memory cell is allowed.4. The refresh verification circuit according to claim 1 , further comprising:a first counting circuit configured to generate a first counting code in response to the filtering pulse;a second counting circuit configured to generate a second counting code in response to a refresh command; anda comparison circuit configured to generate a result signal in response to the first counting code and the second counting code.5. The refresh verification circuit according to claim 4 , wherein the first counting circuit increases a code value of the first counting code each time the filtering pulse is inputted.6. The refresh verification circuit according to claim 4 , wherein the second counting circuit increases a code value of the second counting code each time the refresh command is inputted.7. The refresh verification circuit according to claim 4 , wherein the comparison circuit enables the result signal when the code value of the first counting code and the code value of the second counting code are the same claim 4 , and disables the result signal when the code value of the first counting code and the code value of the second counting code are different.8. The refresh verification circuit according to claim 1 , wherein the ...

Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements

Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal. 1. A semiconductor device , comprising:a memory device from a plurality of memory devices aligned in a vertical stack; anda latency determiner configured to determine a signal latency;wherein the signal latency is configured to be adjusted based on a position of the memory device within the vertical stack.2. The semiconductor device of claim 1 , wherein a programmed latency is stored in a register.3. The semiconductor device of claim 2 , further comprising a latency adjustor configured to adjust the signal latency claim 2 , as appropriate claim 2 , based on the programmed latency.4. The semiconductor device of claim 3 , wherein the latency adjustment is configured to be performed using a data strobe on a common vertical connection.5. The semiconductor device of claim 1 , wherein the latency adjustment is configured to even out latency differences at a memory interface chip or substrate.6. The semiconductor device of claim 1 , wherein a stack position identifier is used to identify the position of the memory device within the vertical stack.7. A semiconductor device claim 1 , comprising:a memory device from a plurality of ...

SEMICONDUCTOR DEVICE HAVING HIERARCHICALLY STRUCTURED BIT LINES AND SYSTEM INCLUDING THE SAME

A method for sensing data in an open bit line dynamic random access memory includes activating a word line in a first memory block of a first memory mat to transfer charge from memory cells to first sub-bit lines, the first memory mat being between a second memory mat and a third memory mat, activating first hierarchy switches corresponding to the first memory block to transfer charge from first sub-bit lines to global bit lines of the first memory mat, and activating second hierarchy switches corresponding to a second memory block in a second memory mat, to connect sub-bit lines to global bit lines of the second memory mat, the first memory block and the second memory block being equidistant from a first sense amplifier array located between the first memory mat and the second memory mat. 1. A method for sensing data in an open bit line dynamic random access memory having a plurality of memory mats with sense amplifier arrays therebetween , each of the memory mats having a plurality of memory blocks and a plurality of global bit lines extending across the memory blocks , each of the memory blocks having a plurality of word line , a plurality of sub-bit lines , and memory cells being located at the intersections of the word lines and sub-bit lines , and a plurality of hierarchy switches connecting sub-bit lines to respective global bit lines , the method comprising:activating a word line in a first memory block of a first memory mat to transfer charge from memory cells to first sub-bit lines, the first memory mat being between a second memory mat and a third memory mat;activating first hierarchy switches corresponding to the first memory block to transfer charge from first sub-bit lines to global bit lines of the first memory mat;activating second hierarchy switches corresponding to a second memory block in a second memory mat, to connect sub-bit lines to global bit lines of the second memory mat, the first memory block and the second memory block being equidistant ...

SEMICONDUCTOR MEMORY DEVICE

To increase a storage capacity of a memory module per unit area, and to provide a memory module with low power consumption, a transistor formed using an oxide semiconductor film, a silicon carbide film, a gallium nitride film, or the like, which is highly purified and has a wide band gap of 2.5 eV or higher is used for a DRAM, so that a retention period of potentials in a capacitor can be extended. Further, a memory cell has n capacitors with different capacitances and the n capacitors are each connected to a corresponding one of n data lines, so that a variety of the storage capacitances can be obtained and multilevel data can be stored. The capacitors may be stacked for reducing the area of the memory cell. 1. (canceled)2. A semiconductor device comprising:a bit line;a word line;a first data line;a second data line; anda memory cell including a transistor, a first capacitor and a second capacitor, the transistor having a channel in an oxide semiconductor film,wherein one of a source and a drain of the transistor is electrically connected to the bit line,wherein the other of the source and the drain of the transistor is electrically connected to one electrode of the first capacitor and one electrode of the second capacitor,wherein a gate of the transistor is electrically connected to the word line,wherein the other electrode of the first capacitor is electrically connected to the first data line,wherein the other electrode of the second capacitor is electrically connected to the second data line, andwherein the first capacitor is provided over a step portion.3. The semiconductor device according to claim 2 , wherein a capacitance of the first capacitor and a capacitance of the second capacitor are different.4. The semiconductor device according to claim 2 , wherein a capacitance of the second capacitor is from 0.1 fF to 1 fF claim 2 , inclusive.5. The semiconductor device according to claim 2 ,wherein an insulating layer is provided over the first capacitor, ...

CONTROLLER TO DETECT MALFUNCTIONING ADDRESS OF MEMORY DEVICE

A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address. 1. (canceled)2. A packaged device comprising:a memory device; and identify one or more primary memory cells of the memory device for repair; and', 'initiate the repair of the identified one or more primary memory cells using secondary memory cells on the memory device after the memory device has been packaged with the memory controller in the packaged device., 'a memory control unit coupled to the memory device, the memory control unit comprising logic to3. The packaged device of claim 2 , wherein the logic further to:initiate the repair of the identified one or more primary memory cells without blowing at least one of a fuse or an anti-fuse on the memory device.4. The packaged device of claim 2 , wherein to initiate the repair claim 2 , the logic to send a command comprising one or more memory addresses of the one or more primary memory cells to the memory device claim 2 , the command to cause the memory device to store the one or more memory addresses in an address matching register on the memory device.5. The packaged device of claim 4 , wherein the command comprises a mode register set (MRS) command.6. The packaged device of claim 4 , wherein the logic further to:test operation of the memory device to identify the one or more primary memory cells of the memory device for repair.7. The packaged device of claim 2 , wherein the ...

Integrated Assemblies Which Include Non-Conductive-Semiconductor-Material and Conductive-Semiconductor-Material, and Methods of Forming Integrated Assemblies

Some embodiments include an integrated assembly which has digit-line-contact-regions laterally spaced from one another by intervening regions. Non-conductive-semiconductor-material is over the intervening regions. Openings extend through the non-conductive-semiconductor-material to the digit-line-contact-regions. Conductive-semiconductor-material-interconnects are within the openings and are coupled with the digit-line-contact-regions. Upper surfaces of the conductive-semiconductor-material-interconnects are beneath a lower surface of the non-conductive-semiconductor-material. Metal-containing-digit-lines are over the non-conductive-semiconductor-material. Conductive regions extend downwardly from the metal-containing-digit-lines to couple with the conductive-semiconductor-material-interconnects. Some embodiments include methods of forming integrated assemblies. 127-. (canceled)28. An integrated assembly , comprising:laterally-spaced digit-line-contact-regions; the digit-line-contact-regions being comprised by pillars of active-region-material; intervening regions being between the laterally-spaced digit-line-contact-regions;non-conductive-semiconductor-material over the intervening regions; openings extending through the non-conductive-semiconductor-material to the digit-line-contact-regions; a lower surface of the non-conductive-semiconductor-material being vertically-spaced from upper surfaces of the digit-line-contact-regions;conductive-semiconductor-material-interconnects within the openings and coupled with the digit-line-contact-regions, upper surfaces of the conductive-semiconductor-material-interconnects being beneath the lower surface of the non-conductive-semiconductor-material; andmetal-containing-digit-lines over the non-conductive-semiconductor-material; conductive regions extending downwardly from the metal-containing-digit-lines to couple with the conductive-semiconductor-material-interconnects.29. The integrated assembly of wherein the conductive- ...

DYNAMIC RANDOM ACCESS MEMORY STRUCTURE AND METHOD FOR PREPARING THE SAME

The present disclosure provides a DRAM cell structure. The DRAM cell structure includes a substrate, a gate structure disposed in the substrate, a source region and a drain region disposed in the substrate respectively at two sides of the gate structure, a landing pad disposed over the drain region, a plurality of carbon nanotubes disposed on the landing pad, a top electrode disposed over the plurality of carbon nanotubes, and a dielectric layer disposed between the top electrode and the plurality of carbon nanotubes. 1. A dynamic random access memory (DRAM) cell structure comprising:a substrate;a gate structure disposed in the substrate;a source region and a drain region disposed in the substrate respectively at two sides of the gate structure;a landing pad disposed over the drain region;a plurality of carbon nanotubes (CNTs) disposed on the landing pad, wherein the plurality of carbon nanotubes comprise different diameters;a top electrode disposed over the plurality of carbon nanotubes; anda dielectric layer disposed between the top electrode and the plurality of carbon nanotubes.2. The DRAM cell structure of claim 1 , further comprising a dielectric structure disposed on the substrate.3. The DRAM cell structure of claim 2 , further comprising a contact plug disposed in the dielectric structure claim 2 , wherein the contact plug electrically connects the drain region and the landing pad.4. The DRAM cell structure of claim 2 , further comprising a bit line structure disposed on the source region claim 2 , wherein the dielectric structure covers the bit line structure.5. The DRAM cell structure of claim 1 , wherein an extending direction of the plurality of carbon nanotubes is substantially perpendicular to a surface of the substrate.6. (canceled)7. A method for preparing a DRAM cell structure claim 1 , comprising:providing a substrate comprising at least an active region, at least a gate structure disposed in the active region, and a source region and a drain ...

Internal signal monitoring circuit

Disclosed herein is an apparatus that includes a first circuit configured to measure a first time period from a first active edge of one of plurality of internal signals to a second active edge of one of the plurality of internal signals, and a second circuit configured to compare the first time period with a second time period to generate an alert signal.

MULTI-CHANNEL MEMORY DEVICE WITH INDEPENDENT CHANNEL POWER SUPPLY STRUCTURE AND METHOD OF CONTROLLING POWER NET

A multi-channel memory device includes a first channel memory and a second channel memory that are independently accessible within a same chip and that respectively include first and second power channel connection lines; a decoupling unit that can operationally connect or separate the first and second power channel connection lines in response to a decoupling driving signal; and a switching control unit that can apply the decoupling driving signal to the decoupling unit in response to a channel power control signal such that power supply voltages independently applied to the first and second channel memories are respectively used in corresponding first and second power channel connection lines. 1. A multi-channel memory device comprising:a first channel memory and a second channel memory that are independently accessible within a same chip and that respectively include first and second external power channel connection lines;a decoupling unit configured to operationally connect or separate the first and second external power channel connection lines in response to a decoupling driving signal; anda switching control unit configured to apply the decoupling driving signal to the decoupling unit in response to a channel power control signal wherein external power supply voltages independently applied to the first and second channel memories are respectively used in corresponding first and second external power channel connection lines.2. The multi-channel memory device of claim 1 , wherein each of the first and second channel memories comprises one of a DRAM cell or an MRAM cell.3. The multi-channel memory device of claim 1 , wherein the first and second external power channel connection lines are connected to each other when a corresponding switch of the decoupling unit is closed.4. The multi-channel memory device of claim 1 , wherein the first and second external power channel connection lines are separated from each other when a corresponding switch of the ...

Programmable lsi

A low-power programmable LSI that can perform configuration (dynamic configuration) at high speed and can quickly start is provided. The programmable LSI includes a plurality of logic elements and a memory element for storing configuration data to be input to the plurality of logic elements. The plurality of logic elements each include a configuration memory. Each of the plurality of logic elements performs different arithmetic processing and changes an electrical connection between the logic elements in accordance with the configuration data stored in the configuration memory. The memory element is formed using a storage element including a transistor whose channel is formed in an oxide semiconductor layer and a node set in a floating state when the transistor is turned off.

MEMORY DEVICE HAVING ADJUSTABLE REFRESH PERIOD AND METHOD OF OPERATING THE SAME

A memory device includes a plurality of rows of memory cells, a refresh period determination unit, and a refresh control unit. The plurality of rows of memory cells includes a first row and one or more second rows. The refresh period determination unit is configured to set a refresh period according to read data from the first row. A refresh control unit is configured to control refreshing the one or more second rows based on the refresh period and to control obtaining the read data from the first row based on an adjustment interval. 1. A memory device , comprising:a plurality of rows of memory cells, comprising a first row and one or more second rows;a refresh period determination unit configured to set a refresh period according to read data from the first row; anda refresh control unit configured to control refreshing the one or more second rows based on the refresh period and to control obtaining the read data from the first row based on an adjustment interval.2. The memory device of claim 1 , wherein a row of the plurality of rows is configured to be assigned as the first row during an adjustment cycle and as one of the one or more second rows during another adjustment cycle.3. The memory device of claim 1 , wherein the refresh period determination unit comprises:an error detection unit configured to generate, for each refresh period adjusting cycle defined based on the adjustment interval, an error detection result, the error detection result having a predetermined logic value if the read data contains an error; anda shift register configured to store error detection results from the error detection unit corresponding to a predetermined number of consecutive adjustment cycles, the predetermined number of consecutive adjustment cycles including a present adjustment cycle,wherein the refresh period determination unit is configured to set the refresh period according to a prior refresh period and/or a predetermined increment responsive to a number of error ...

BUFFER CIRCUIT WITH ADAPTIVE REPAIR CAPABILITY

A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic. 1. (canceled)2. A buffer circuit for a memory comprising:a primary interface to receive row address information and column address information for a given data transfer operation;a match circuit to compare the received row address information to stored failure row address information, the match circuit to compare the received column address information to stored failure column address information; anda gating circuit to maintain a state of a matching row address identified by the match circuit during the compare of the received column address information to the stored failure column address information.3. The buffer circuit according to claim 2 , wherein the gating circuit further comprises:circuitry to gate a matching column address output of the match circuit with matching row address information, the matching row and column address information logically combined to generate a substitute repair address for accessing substitute storage for data associated with the failure row and column addresses.4. The buffer circuit according to claim 3 , ...

SEMICONDUCTOR DEVICE

A programmable logic device including an asynchronous circuit is provided. The programmable logic device includes a lookup table, a first circuit, and a second circuit. The first circuit receives a first signal and a second signal. The second circuit sends a third signal. The first circuit sends a fourth signal and a fifth signal, when receiving the third signal. The fourth signal has the same logic as the first signal. The fifth signal has the same logic as the second signal. The lookup table sends a sixth signal and a seventh signal, when receiving the fourth signal and the fifth signal. The second circuit sends an eighth signal, when receiving the sixth signal and the seventh signal. The first circuit sends a ninth signal, when receiving the eighth signal. The lookup table includes a memory. The sixth signal and the seventh signal are generated from data stored in the memory. 1. A semiconductor device comprising:a lookup table comprising a memory;a first circuit; anda second circuit,wherein the first circuit receives a first signal and a second signal,wherein the second circuit sends a third signal,wherein when the first circuit receives the third signal, the first circuit sends a fourth signal and a fifth signal,wherein when the lookup table receives the fourth signal and the fifth signal, the lookup table sends a sixth signal and a seventh signal,wherein when the second circuit receives the sixth signal and the seventh signal, the second circuit sends an eighth signal,wherein when the first circuit receives the eighth signal, the first circuit sends a ninth signal, andwherein the sixth signal and the seventh signal are generated from data stored in the memory.2. The semiconductor device according to claim 1 , wherein supply of a power supply voltage to the lookup table is stopped by the ninth signal.3. The semiconductor device according to claim 1 , wherein the memory comprises a transistor containing a metal oxide in a channel formation region of the ...

Buffered memory module having multi-valued on-die termination

In a memory module having an integrated-circuit buffer device coupled to one or more integrated-circuit memory devices, the buffer device receives write data signals from an external control component via a set of data inputs, the write data signals indicating write data to be stored within one or more of the memory devices. Logic within the buffer device sequentially applies controllable termination impedance configurations at the data inputs based on an indication received from the control component and an internal state of the buffer device, applying a first controllable termination impedance configuration at each of the data inputs during a first internal state of the buffer device corresponding to the reception of the write data signals on the data inputs, and applying a second controllable termination impedance configuration at each of the data inputs during a second internal state of the buffer device that succeeds the first internal state.

CONTROLLER TO DETECT MALFUNCTIONING ADDRESS OF MEMORY DEVICE

A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address. 1. A controller comprising:an internal memory to store an address; and identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller,', 'store the malfunctioning address in the internal memory, and', 'transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address., 'a memory control unit operatively coupled with the internal memory, the memory control unit comprising logic to2. The controller of wherein the logic to identify the malfunctioning address of primary data storage elements identifies the malfunctioning address based on results of a memory test function.3. The controller of wherein logic corresponding to the memory test function resides on the controller.4. The controller of wherein the logic to identify the malfunctioning address of primary data storage elements obtains a repair address from testing logic located on a device other than the controller.5. The controller of wherein the indication of the address associated with the malfunctioning address is the repair address obtained from the testing logic located on the device other than the ...

MEMORY DEVICE COMPRISING ELECTRICALLY FLOATING BODY TRANSISTOR

A semiconductor memory instance is provided that includes an array of memory cells. The array includes a plurality of semiconductor memory cells arranged in at least one column and at least one row. Each of the semiconductor memory cells includes a floating body region configured to be charged to a level indicative of a state of the memory cell. Further includes are a plurality of buried well regions, wherein each of the buried well regions can be individually selected, and a decoder circuit to select at least one of the buried well regions. 120-. (canceled)21. A semiconductor memory instance comprising:a plurality of memory sub-arrays, each said memory sub-array comprising:a plurality of semiconductor memory cells arranged in at least one column and at least one row, each said semiconductor memory cell comprising: a floating body region configured to be charged to a level indicative of a state of the memory cell;a buried well region contacting said floating body regions of said plurality of semiconductor cells, wherein said buried well region is common to said plurality of semiconductor memory cells in said memory sub-array; anda first decoder circuit to select at least one of said at least one column or at least one of said at least one row; anda second decoder circuit to select at least one of said memory sub-arrays.22. The semiconductor memory instance of claim 21 , wherein each said memory cell is configured to provide at least two stable states.23. The semiconductor memory instance of claim 21 , wherein each said memory cell further comprises a first region in electrical contact with said floating body region and a second region in electrical contact with said floating body region.24. The semiconductor memory instance of claim 23 , wherein each said memory cell further comprises a gate positioned between said first and second regions.25. The semiconductor memory instance of claim 21 , further comprising an address signal as an input to said second decoder ...

Semiconductor memory device

A semiconductor device may include a stack structure that includes a plurality of layers vertically stacked on a substrate, and a plurality of gate electrodes that vertically extend to penetrate the stack structure. Each of the plurality of layers may include a plurality of semiconductor patterns that extend in parallel along a first direction, a bit line that is electrically connected to the semiconductor patterns and extends in a second direction intersecting the first direction, a first air gap on the bit line, and a data storage element that is electrically connected to a corresponding one of the semiconductor patterns. The first air gap is interposed between the bit line of a first layer of the plurality of layers and the bit line of a second layer of the plurality of layers.

Reservoir capacitor and semiconductor device including the same

A reservoir capacitor includes a first capacitor group having two or more capacitors, which are serially coupled to each other between a first power voltage supply terminal and a second power voltage supply terminal, a second capacitor group having two or more capacitors, which are serially coupled to each other between a third power voltage supply terminal and a fourth power voltage supply terminal and a connection line suitable for electrically coupling a first coupling node between the capacitors of the first capacitor group to a second coupling node between the capacitors of the second capacitor group.

Gate dielectric repair on three-node access device formation for vertical three-dimensional (3d) memory

Systems, methods and apparatus are provided for a three-node access device in vertical three-dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines. The method includes depositing alternating layers of a dielectric material and a sacrificial material to form a vertical stack. Forming a plurality of first vertical openings to form elongated vertical, pillar columns with sidewalls in the vertical stack. Conformally depositing a gate dielectric in the plurality of first vertical openings. Forming a conductive material on the gate dielectric. Removing portions of the conductive material to form a plurality of separate, vertical access lines. Repairing a first side of the gate dielectric exposed where the conductive material was removed. Forming a second vertical opening to expose sidewalls adjacent a first region of the sacrificial material. Selectively removing the sacrificial material in the first region to form first horizontal openings. Repairing a second side of the gate dielectric exposed where the sacrificial material was removed in the first region. Depositing a first source/drain region, a channel region, and a second source/drain region in the first horizontal openings.

ON-DIE TERMINATION CONTROL

A memory control component outputs a memory write command to a memory IC and also outputs write data to be received via data inputs of the memory IC. Prior to reception of the write data within the memory IC, the memory control component asserts a termination control signal that causes the memory IC to apply to the data inputs a first on-die termination impedance during reception of the write data followed by a second on-die termination impedance after the write data has been received. The memory control component deasserts the termination control signal to cause the memory IC to apply no termination impedance to the data inputs. 120-. (canceled)21. A dynamic random access memory (DRAM) component comprising:a storage register; one or more commands that specify storage of a digital control value within the storage register, the digital control value specifying a termination impedance;', 'a write command; and', 'a chip-select signal indicating that the DRAM component is to receive write data associated with the write command;, 'a first interface to receivea second interface to receive the write data during a given time; and couple to the second interface, prior to the given time and responsive to the chip-select signal and the write command, one or more termination elements having the termination impedance specified by the digital control value, and', 'decouple the one or more termination elements from the second interface at conclusion of the given time, after the write data has been received via the second interface., 'control circuitry to22. The DRAM component of wherein the control circuity comprises state circuitry that transitions to a data-write operating state in response to the write command and the chip-select signal claim 21 , and wherein the given time corresponds to a time period in which the state circuitry remains in the data-write operating state.23. The DRAM component of wherein:the first interface is further to receive a read command;the state ...

ANTIFUSE DEVICE AND METHOD OF OPERATING THE SAME

An antifuse device is disclosed. The antifuse device includes a plurality of active regions, a plurality of word lines extending along a first direction and cut through the active regions, a plurality of bit lines and a plurality of source lines extending along a second direction and stride across the active regions. The bit lines and the source lines are arranged alternatively along the first direction. Plural antifuse capacitors are disposed along the source lines and connected between the source lines and the active regions. 1. An antifuse device , comprising:a substrate having a plurality of active regions;a plurality of word lines formed in the substrate and extending along a first direction, each of the active regions being cut by two adjacent word lines and divided into a first doped region and two second doped regions;a plurality of bit lines formed on the substrate and extending along a second direction, the first doped region of each of the active regions being connected to one of the bit lines through a bit line contact structure disposed on the first doped region;a plurality of source lines formed on the substrate and extending along the second direction, the second doped regions of the active regions being respectively connected to one of the source lines through a source line contact structure disposed on each of the second doped regions; anda plurality of capacitors arranged along the second direction and respectively sandwiched between the source line contact structure and one of the bitlines.2. The antifuse device according to claim 1 , wherein the first direction and the second direction are perpendicular.3. The antifuse device according to claim 1 , wherein the active regions extend along a third direction that is not perpendicular to the first direction.4. The antifuse device according to claim 1 , wherein the bit lines and the source lines are alternately arranged along the second direction from the top view.5. The antifuse device according to ...

Memory device error check and scrub mode and error transparency

An error check and scrub (ECS) mode enables a memory device to perform error checking and correction (ECC) and count errors. An associated memory controller triggers the ECS mode with a trigger sent to the memory device. The memory device includes multiple addressable memory locations, which can be organized in segments such as wordlines. The memory locations store data and have associated ECC information. In the ECS mode, the memory device reads one or more memory locations and performs ECC for the one or more memory locations based on the ECC information. The memory device counts error information including a segment count indicating a number of segments having at least a threshold number of errors, and a maximum count indicating a maximum number of errors in any segment.

Memory Cells and Memory Arrays

Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

Memory device having 2-transistor vertical memory cell and shared channel region

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first data line located in a first level of the apparatus; a second data line located in a second level of the apparatus; a first memory cell located in a third level of the apparatus between the first and second levels, the first memory cell including a first transistor coupled to the first data line, and a second transistor coupled between the first data line and a charge storage structure of the first transistor; and a second memory cell located in a fourth level of the apparatus between the first and second levels, the second memory cell including a third transistor coupled to the second data line, and a fourth transistor coupled between the second data line and a charge storage structure of the third transistor, the first transistor coupled in series with the third transistor between the first and second data lines.

MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND A COMMON PLATE

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a substrate, a conductive plate located over the substrate to couple a ground connection, a data line located between the substrate and the conductive plate, a memory cell, and a conductive line. The memory cell includes a first transistor and a second transistor. The first transistor includes a first region electrically coupled between the data line and the conductive plate, and a charge storage structure electrically separated from the first region. The second transistor includes a second region electrically coupled to the charge storage structure and the data line. The conductive line is electrically separated from the first and second regions and spans across part of the first region of the first transistor and part of the second region of the second transistor and forming a gate of the first and second transistors. 1. An apparatus comprising:a substrate;a conductive plate located over the substrate to couple a ground connection;a data line located between the substrate and the conductive plate; a first transistor including a first region electrically coupled between the data line and the conductive plate, and a charge storage structure electrically separated from the first region; and', 'a second transistor including a second region electrically coupled to the charge storage structure and the data line; and, 'a memory cell includinga conductive line electrically separated from the first and second regions, part of the conductive line spanning across part of the first region of the first transistor and forming a gate of the first and second transistors.2. The apparatus of claim 1 , wherein the first region includes p-type semiconductor material claim 1 , and the second region includes n-type semiconductor material.3. The apparatus of claim 1 , wherein the second region comprises a semiconducting oxide material.4. The apparatus of claim 1 , further ...

SELECTIVE ERROR CODING

A system and method of performing selective error coding in memory management of a memory device are described. The method includes performing a process of detecting and correcting memory errors in the memory of the memory device either prior to or after a chip mark associated with the memory device is in place. The method also includes localizing hard errors of the memory device based on a second process of detecting the memory errors in the memory of the memory device, the hard errors being persistent memory errors that persist from the process of detecting and correcting the memory errors to the second process, determining an extent of the hard errors based on the localizing, and preventing placement of the chip mark or removing the chip mark after de-allocating one or more ranges of addresses based on a result of the determining the extent of the hard errors. 1. A method of performing selective error coding in memory management of a memory device , the method comprising:performing, using a processor, a process of detecting and correcting memory errors in the memory of the memory device, the process including correcting bit errors based on an error-correcting code embedded with data in the memory device, either prior to or after a chip mark associated with the memory device is in place, the chip mark indicating all addresses of the memory device as bad;localizing hard errors of the memory device, using the processor, based on a second process of detecting the memory errors in the memory of the memory device, the hard errors being persistent memory errors that persist from the process of detecting and correcting the memory errors to the second process;determining an extent of the hard errors based on the localizing; andpreventing placement of the chip mark or removing the chip mark to resume memory use of the memory device after de-allocating one or more ranges of addresses of the memory of the memory device based on a result of the determining the extent of the ...

MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE

A method and apparatus for organizing memory for a computer system including a plurality of memory devices, connected to a logic device, particularly a memory system having a plurality of stacked memory dice connected to a logic die, with the logic device having capability to analyze and compensate for differing delays to the stacked devices stacking multiple dice divided into partitions serviced by multiple buses connected to a logic die, to increase throughput between the devices and logic device allowing large scale integration of memory with self-healing capability. 1 each of said dies further comprising a plurality of partitions; and,', 'vaults in said dies comprising a grouping of said partitions in a said dies, 'a plurality of semiconductor dies stacked and connected together; and,'}. A memory device for use in computer systems comprising: This application is a continuation of U.S. application Ser. No. 14/519,759, filed on Oct. 21, 2014. U.S. application Ser. No. 14/519,759 is a continuation of Ser. No. 13/684,260, filed on Nov. 23, 2012 which is now U.S. Pat. No. 8,879,296, which claims priority from U.S. Provisional Patent Application Ser. No. 61/563,682, entitled “Memory system and method using stacked memory device dice”, filed Nov. 25, 2011, which are incorporated herein by reference in their entireties.This invention relates to memory devices, and, more particularly, to a memory system having a plurality of stacked memory dice connected to a logic die, with greater particularity the invention relates to stacking multiple dice divided into partitions serviced by multiple buses on a logic die, and with still greater particularity the invention relates to methods and apparatus for stacking multiple memory modules on a logic die with increased throughput through alteration of the number and position of partitions and timing.As the operating speed of processor has increased and multi-core processors have been introduced, data throughput of processor has been ...

System on package

A system on package includes a first package and a second package stacked on the first package and electrically connected to one another through metal contacts. The first package includes a first printed circuit board (PCB), a system on chip which is connected to the first PCB through bumps, and a first memory device which is connected to the system on chip through micro bumps connected to vias in the system on chip. The second package includes a second PCB, a second memory device connected to the second PCB, a third memory device connected to the second PCB, and a memory controller which is connected to the second PCB and controls the third memory device.

MEMORY MODULE AND MANUFACTURING METHOD THEREOF

A memory module includes a printed circuit board; first memory chips disposed in parallel with a long axis of the printed circuit board along a first column; second memory chips disposed in parallel with the long axis of the printed circuit board along a second column; and passive elements disposed between the first memory chips and the second memory chips, wherein the passive elements are connected between input/output pins of each of the first and second memory chips and tap pins. 1. A memory module comprising:a printed circuit board (PCB);first memory chips on the PCB in a first column that is parallel with a long axis of the PCB;second memory chips on the PCB in a second column that is parallel with the long axis of the PCB; andpassive elements between the first memory chips and the second memory chips, the passive elements being connected between input/output pins of each of the first and second memory chips and tap pins.2. The memory module of claim 1 , wherein the printed circuit board comprises: 'the first memory chips and the second memory chips are on an uppermost or lowermost layer of the plurality of layers.', 'a plurality of layers, and wherein'}3. The memory module of claim 1 , wherein the input/output pins of each of the first and second memory chips are in a direction perpendicular to the long axis.4. The memory module of claim 1 , wherein the input/output pins of each of the first and second memory chips are in a direction parallel with the long axis.5. The memory module of claim 1 , wherein the passive elements comprise:capacitors connected between the input/output pins and the tap pins.6. The memory module of claim 1 , wherein the passive elements comprise:input/output resistors connected between the input/output pins and the tap pins.7. The memory module of claim 6 , wherein when the memory module is inactivated claim 6 , the tap pins are configured to electrically connect to the input/output resistors.8. The memory module of claim 6 , wherein ...

MEMORY DEVICE ERROR CHECK AND SCRUB MODE AND ERROR TRANSPARENCY

An error check and scrub (ECS) mode enables a memory device to perform error checking and correction (ECC) and count errors. An associated memory controller triggers the ECS mode with a trigger sent to the memory device. The memory device includes multiple addressable memory locations, which can be organized in segments such as wordlines. The memory locations store data and have associated ECC information. In the ECS mode, the memory device reads one or more memory locations and performs ECC for the one or more memory locations based on the ECC information. The memory device counts error information including a segment count indicating a number of segments having at least a threshold number of errors, and a maximum count indicating a maximum number of errors in any segment. 123-. (canceled)24. A dynamic random access memory (DRAM) device , comprising:a memory array including multiple rows;a first register as a row error counter to indicate a total number of code word errors detected in an error check and scrub (ECS) mode where the DRAM device is to internally read and correct bit errors in the rows of the memory array; anda second register as an errors per row counter to indicate an address of a row with a largest number of code word errors in the ECS mode.25. The DRAM device of claim 24 , wherein the first and second registers comprise Mode Registers.26. The DRAM device of claim 24 , further comprising:an input/output (I/O) interface to receive a command to set a bit of a mode register to enter the ECS mode.27. The DRAM device of claim 26 , wherein in the ECS mode claim 26 , the I/O interface is to receive a command sequence including an ECS entry command (ECS) claim 26 , an Activate command (ACT) claim 26 , a Write command (WR) claim 26 , and a Precharge command (PRE).28. The DRAM device of claim 24 , further comprising:error checking and correction (ECC) logic to detect and correct the bit errors.29. The DRAM device of claim 28 , wherein the ECC logic is to ...

Semiconductor Device and Method for Driving Semiconductor Device

The semiconductor device includes a first memory cell, and a second memory cell thereover. The first memory cell includes first and second transistors, and a first capacitor. The second memory cell includes third and fourth transistors, and a second capacitor. A gate of the first transistor is electrically connected to one of a source and a drain of the second transistor and the first capacitor. A gate of the third transistor is electrically connected to one of a source and a drain of the fourth transistor and the second capacitor. One of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor. The second and fourth transistors include an oxide semiconductor. A channel length direction of the first and third transistors is substantially perpendicular to a channel length direction of the second and fourth transistors. 1. (canceled)2. A semiconductor device comprising:a plurality of memory cell arrays arranged in a first direction;a plurality of first wirings; anda plurality of second wirings,wherein the plurality of first wirings and the plurality of second wirings extend in a second direction substantially perpendicular to the first direction,wherein each of the memory cell arrays includes a plurality of memory cell strings arranged in the second direction,wherein the plurality of memory cell strings extend in a third direction substantially perpendicular to the first direction and the second direction,wherein each of the memory cells string includes a plurality of memory cells and third to fifth wirings extending in the third direction,wherein each of the memory cells includes a first transistor, a second transistor, and a capacitor,wherein a channel length direction of the first transistor is substantially parallel to the third direction,wherein the second transistor includes an oxide semiconductor,wherein a gate of the first transistor is electrically connected to one of a source and a drain of ...

Efficient calibration of memory devices

A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A temporal calibration mechanism reduces the time and resources for calibration by reducing the number tests needed to sufficiently determine the boundaries of the data eye of the memory device. For one or more values of the voltage reference, the temporal calibration mechanism performs a minimal number of tests to find the edges of the data eye for the hold and setup times.

MULTI-RESISTANCE MRAM

Apparatuses, systems, and methods are disclosed for magnetoresistive random access memory. A magnetic tunnel junction (MTJ) for storing data may include a reference layer. A free layer of an MTJ may be separated from a reference layer by a barrier layer. A free layer may be configured such that one or more resistance states for an MTJ correspond to one or more positions of a magnetic domain wall within the free layer. A domain stabilization layer may be coupled to a portion of a free layer, and may be configured to prevent migration of a domain wall into the portion of the free layer. 1. An apparatus comprising: a wall extension region configured to provide a plurality of resistance states for the memory cell corresponding to positions of a magnetic domain wall within the wall extension region; and', 'an end region configured to exclude the domain wall., 'a magnetoresistive random access memory (MRAM) die, the MRAM die comprising a plurality of memory cells, a memory cell comprising a fixed layer, a barrier layer, and a free layer, the barrier layer disposed between the fixed layer and the free layer, the free layer comprising2. The apparatus of claim 1 , further comprising a domain stabilization layer coupled to the end region of the free layer claim 1 , the domain stabilization layer configured to stabilize a magnetization direction for the end region of the free layer.3. The apparatus of claim 2 , wherein the domain stabilization layer comprises an antiferromagnetic layer.4. The apparatus of claim 3 , wherein the antiferromagnetic layer is configured to induce a unidirectional magnetic anisotropy in a portion of the free layer.5. The apparatus of claim 2 , wherein the domain stabilization layer comprises a multilayer.6. The apparatus of claim 5 , wherein the multilayer comprises one or more of: a cobalt/platinum multilayer and a cobalt/palladium multilayer.7. The apparatus of claim 5 , wherein the multilayer is configured to induce a coercivity increase in a ...

MEMORY MODULE AND OPERATING METHOD

A memory module includes; dynamic random access memories (DRAMs), a controller configured to control operation of the DRAMs, and an active device configured, in response to detection of an error occurring in at least one of the DRAMs, to generate an interrupt and store error information corresponding to the error.

MECHANISMS FOR PREVENTING LEAKAGE CURRENTS IN MEMORY CELLS

Memory cells and operation methods thereof are provided. A memory device includes a number of memory cells. Each of the memory cells includes a first transistor, a switch and a capacitor. The first transistor has a drain connected to a corresponding bit-line. The switch has a first terminal connected to a source of the first transistor and a second terminal coupled to a reference voltage. The capacitor has a first plate and a second plate, and the first plate of the capacitor is electrically connected to a gate of the first transistor. The second plate of the capacitor is connected to a corresponding word line. The switch is turned off when the memory cell is not selected to perform a write operation or a read operation. 1. A memory device , comprising: a first transistor, having a drain connected to a corresponding bit-line;', 'a switch, having a first terminal connected to a source of the first transistor and a second terminal coupled to a reference voltage; and', 'a capacitor, having a first plate and a second plate, wherein the first plate of the capacitor is electrically connected to a gate of the first transistor, the second plate of the capacitor is connected to a corresponding word line, and the switch is turned off when the memory cell is not selected to perform a write operation or a read operation., 'a plurality of memory cells, each comprising2. The memory device as claimed in claim 1 , wherein the switch comprises a second transistor having a drain connected to the source of the first transistor and a source coupled to the reference voltage.3. The memory device as claimed in claim 2 , wherein the first transistor and the second transistor are NMOS transistors.4. The memory device as claimed in claim 2 , wherein the first transistor and the second transistor are turned on when the memory cell is selected to perform the read operation.5. The memory device as claimed in claim 2 , wherein the first transistor and the second transistor are turned on when the ...

Systems and Methods of Vector-DMA cache-XOR for MPCC Erasure Coding

System and method embodiments are provided for managing storage systems. In an embodiment, a network component for managing data storage includes a storage interface configured to couple to a plurality of storage devices; and a vector-direct memory access (DMA) cache-exclusive OR (XOR) engine coupled to the storage interface and configured for a multiple parities convolution codes (MPCC) erasure coding to accelerate M parities parallel calculations and the erasures cross-iterations decoding, wherein a single XOR-engine with caches and a vector-DMA address generator is shared by the MPCC erasure coding engine for pipelining external dual data rate (DDR4) memory accesses, where M is a positive integer greater than two. 1. A network component for managing data storage , comprising:a storage interface configured to couple to a plurality of storage devices; anda vector-direct memory access (DMA) cache-exclusive OR (XOR) engine coupled to the storage interface and configured for a multiple parities convolution codes (MPCC) erasure coding to accelerate M parities parallel calculations and erasures cross-iterations decoding, wherein a single XOR-engine with caches and a vector-DMA address generator is shared by an MPCC erasure coding engine for pipelining external dual data rate (DDR4) memory accesses, where M is a positive integer greater than two.2. The network component of claim 1 , wherein the vector-DMA cache-XOR engine comprises a processor a level 1 (L1) cache claim 1 , a level 3 (L3) cache claim 1 , a zero-copy receiver parsing component claim 1 , an L1 vector DMA controller claim 1 , and a packet spread transmitter.3. The network component of claim 1 , wherein the vector-DMA cache-XOR engine is configured to perform zero-copy packet-by-packet XOR operations to recover data loss in the storage devices.4. The network component of claim 1 , wherein the vector-DMA cache-XOR engine is configured to write a plurality of data blocks to external dual in-line memory modules ...

Signal Timing Alignment based on a Common Data Strobe in Memory Devices Configured for Stacked Arrangements

Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal. 1. A semiconductor device , comprising:a memory device from a plurality of memory devices aligned in a vertical stack; anda latency determiner configured to determine a signal latency;wherein the signal latency is configured to be adjusted based on a position of the memory device within the vertical stack.2. The semiconductor device of claim 1 , wherein a programmed latency is stored in a register.3. The semiconductor device of claim 2 , further comprising a latency adjustor configured to adjust the signal latency claim 2 , as appropriate claim 2 , based on the programmed latency.4. The semiconductor device of claim 3 , wherein the latency adjustment is configured to be performed using a data strobe on a common vertical connection.5. The semiconductor device of claim 1 , wherein the latency adjustment is configured to even out latency differences at a memory interface chip or substrate.6. The semiconductor device of claim 1 , wherein a stack position identifier is used to identify the position of the memory device within the vertical stack.7. A semiconductor device claim 1 , comprising:a memory device from a plurality of ...

SEMICONDUCTOR MEMORY TRAINING METHOD AND RELATED DEVICE

The present application relates to a semiconductor memory training method and related devices, belonging to the technical field of semiconductors. The method comprises: obtaining the stored historical training result of a semiconductor memory, the historical training result comprising a historical expected delay value and a historical expected voltage; setting a delay threshold and a current training voltage range, the delay threshold being less than or equal to the historical expected delay value, the current training voltage range comprising the historical expected voltage; obtaining a current minimum delay value for the semiconductor memory under the historical expected voltage; and using the stored historical training result as a current training result of the semiconductor memory, if the current minimum delay value for the semiconductor memory under the historical expected voltage is no less than the delay threshold. 1. A semiconductor memory training method , comprising:obtaining a stored historical training result of a semiconductor memory, the historical training result comprising a historical expected delay value and a historical expected voltage;setting a delay threshold and a current training voltage range, the delay threshold being less than or equal to the historical expected delay value, the current training voltage range comprising the historical expected voltage;obtaining a current minimum delay value for the semiconductor memory under the historical expected voltage; andusing the stored historical training result as a current training result of the semiconductor memory, if the current minimum delay value for the semiconductor memory under the historical expected voltage is no less than the delay threshold.2. The semiconductor memory training method according to claim 1 , wherein the semiconductor memory has a plurality of reference voltages; and before obtaining the stored historical training result claim 1 , the semiconductor memory training method ...

SEMICONDUCTOR DEVICE WITH A DATA-RECORDING MECHANISM

An electronic device includes: a detection circuit configured to determine one or more operating data, one or more device sensor data, or a combination thereof associated with operation of the electronic device; a trigger circuit operably coupled to the circuit, the trigger circuit configured to generate a stress input based on detecting one or more target criteria from the one or more operating data, the one or more device sensor data, or a combination thereof; and a degradation sensor operably coupled to the trigger circuit, the degradation sensor having a threshold voltage and being configured to record the target criteria that occurs during operation of the electronic device, wherein the degradation sensor is configured to record the target criteria based on degradation of the threshold voltage according to the stress input. 1. An electronic device , comprising:a detection circuit configured to determine one or more operating data, one or more device sensor data, or a combination thereof associated with operation of the electronic device;a trigger circuit operably coupled to the detection circuit, the trigger circuit configured to generate a stress input based on the detection circuit detecting one or more target criteria from the one or more operating data, the one or more device sensor data, or the combination thereof; anda degradation sensor operably coupled to the trigger circuit, the degradation sensor having a threshold voltage and being configured to store information corresponding to the target criteria based on degradation of the threshold voltage according to the stress input.2. The electronic device of claim 1 , wherein:the degradation sensor is a PMOS device configured to degrade according to negative bias temperature instability (NBTI), andthe trigger circuit is configured to generate the stress input that increases the threshold voltage according to the NBTI.3. The electronic device of claim 1 , wherein:the degradation sensor is an NMOS device ...

Integrated Assemblies Which Include Non-Conductive-Semiconductor-Material and Conductive-Semiconductor-Material, and Methods of Forming Integrated Assemblies

Some embodiments include an integrated assembly which has digit-line-contact-regions laterally spaced from one another by intervening regions. Non-conductive-semiconductor-material is over the intervening regions. Openings extend through the non-conductive-semiconductor-material to the digit-line-contact-regions. Conductive-semiconductor-material-interconnects are within the openings and are coupled with the digit-line-contact-regions. Upper surfaces of the conductive-semiconductor-material-interconnects are beneath a lower surface of the non-conductive-semiconductor-material. Metal-containing-digit-lines are over the non-conductive-semiconductor-material. Conductive regions extend downwardly from the metal-containing-digit-lines to couple with the conductive-semiconductor-material-interconnects. Some embodiments include methods of forming integrated assemblies. 1. A method of forming an integrated assembly , comprising:providing a construction having laterally-spaced digit-line-contact-regions, and having intervening regions between the laterally-spaced digit-line-contact-regions;forming an expanse of non-conductive-semiconductor-material which extends across the digit-line-contact-regions and the intervening regions; a lower surface of the non-conductive-semiconductor-material being vertically-spaced from upper surfaces of the digit-line-contact-regions;forming openings extending through the non-conductive-semiconductor-material to the digit-line-contact-regions;forming conductive-semiconductor-material-interconnects within the openings and coupled with the digit-line-contact-regions, upper surfaces of the conductive-semiconductor-material-interconnects being beneath the lower surface of the non-conductive-semiconductor-material; andforming metal-containing-digit-lines over the non-conductive-semiconductor-material, with conductive regions extending downwardly from the metal-containing-digit-lines to couple with the conductive-semiconductor-material-interconnects. ...

METHOD FOR FABRICATING SEMICONDUCTOR MEMORY DEVICE WITH BURIED CAPACITOR AND FIN-LIKE ELECTRODES

A method for forming a semiconductor device is disclosed. A substrate having a semiconductor substrate, an insulator layer on the semiconductor substrate, and a silicon device layer on the insulator layer is provided. At least one capacitor cavity with corrugated sidewall surface is formed within the insulator layer between the semiconductor substrate and the silicon device layer. At least one buried capacitor is formed in the at least one capacitor cavity. The at least one buried capacitor comprises inner and outer electrodes with a capacitor dielectric layer therebetween. At least one transistor is formed on the substrate. The at least one transistor comprises a source region, a drain region, a channel region between the source region and the drain region, and a gate over the channel region. The source region is electrically connected to the inner electrode of the at least one buried capacitor. 1. A method for forming a semiconductor device , comprising:providing a substrate comprising a semiconductor substrate, an insulator layer on said semiconductor substrate, and a silicon device layer on said insulator layer;forming at least one capacitor cavity with corrugated sidewall surface within said insulator layer between said semiconductor substrate and said silicon device layer;forming at least one buried capacitor in said at least one capacitor cavity, said at least one buried capacitor comprising inner and outer electrodes with a capacitor dielectric layer therebetween; andforming at least one transistor on said substrate, wherein said at least one transistor comprises a source region, a drain region, a channel region between said source region and said drain region, and a gate over said channel region, and wherein said source region is electrically connected to said inner electrode of said at least one buried capacitor.2. The method according to further comprising:forming alternating layers in said substrate to form said insulator layer.3. The method according to ...

REFRESH IN NON-VOLATILE MEMORY

The present disclosure includes apparatuses and methods related to refresh in memory. An example apparatus can refresh a memory cell of an array of memory cells in response to the array of memory cells being accessed a threshold number of accesses. 120-. (canceled)21. An apparatus , comprising:an array of memory cells; and determine a refresh rate of the array of memory cells based on a threshold miss rate; and', 'refresh a memory cell of the array of memory cells based on the refresh rate., 'a processor configured to22. The apparatus of claim 21 , wherein the threshold miss rate is based on a number of memory cells that fail to refresh.23. The apparatus of claim 22 , wherein the number of memory cells fail to refresh within a threshold number of accesses for the memory cell.24. The apparatus of claim 21 , wherein the memory cell fails in response to being accessed a threshold number of times without being refreshed.25. The apparatus of claim 22 , wherein the processor is configured to reduce a miss rate by increasing the refresh rate.26. The apparatus of claim 22 , wherein the refresh rate is at most 1/T claim 22 , where T is a number of times the memory cell can be accessed before it will fail if not refreshed.27. The apparatus of claim 22 , wherein the processor is configured to determine the refresh rate periodically based on dynamic data.28. The apparatus of claim 22 , wherein the processor is configured to determine the refresh rate periodically based on a type of workload.29. An apparatus claim 22 , comprising:an array of memory cells; and determine a threshold miss rate based on a number of memory cells that fail to refresh;', 'determine a refresh rate of the array of memory cells based on the threshold miss rate; and', 'refresh a memory cell of the array of memory cells in response to the array of memory cells being accessed a threshold number of accesses, wherein the threshold is based on the refresh rate., 'a processor configured to30. The apparatus of ...

CONTROLLER TO DETECT MALFUNCTIONING ADDRESS OF MEMORY DEVICE

A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address. 1. (canceled)2. A controller comprising:an internal memory to store a row address for repair; and transmit a first register setting command to initiate a row repair mode in an external memory device;', 'transmit an activation command comprising an indication of the row address for repair;', 'transmit a precharge command; and', 'transmit a second register setting command to terminate the row repair mode in the external memory device., 'a memory control unit operatively coupled with the internal memory, the memory control unit comprising logic to3. The controller of claim 2 , wherein the memory control unit is to transmit the second register setting command a predetermined precharge time period after transmitting the precharge command.4. The controller of claim 2 , wherein the internal memory comprises a non-volatile memory device.5. The controller of claim 2 , wherein the activation command to initiate a repair of the row address for repair using redundant data storage elements and an indication of an address associated with the row address for repair in an address matching register.6. The controller of claim 2 , wherein the activation command to initiate a repair of the row address for repair without blowing fuses in the external memory device.7. The controller of claim 2 , wherein the first register setting command comprises a mode ...

MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND DETECTING METHOD

To provide a memory device which can perform verification operation for detecting a memory cell whose data holding time is shorter than a predetermined length, accurately in a short time. Each memory cell includes at least a first capacitor, a second capacitor, and a transistor which functions as a switching element for controlling supply, storage, and release of charge in the first capacitor and the second capacitor. The capacitance of the first capacitor is thousand or more times the capacitance of the second capacitor, preferably ten thousand or more times the capacitance of the second capacitor. In normal operation, charge is stored using the first capacitor and the second capacitor. In performing verification operation for detecting a memory cell whose data holding time is shorter than a predetermined length, charge is stored using the second capacitor. 1. (canceled)2. A memory device comprising: a first capacitor;', 'a second capacitor; and', 'a transistor,, 'a cell array comprising a plurality of memory cells, at least one of the plurality of memory cells comprisingwherein one of a source electrode and a drain electrode of the transistor is directly connected to the first capacitor and the second capacitor,wherein a capacitance of the first capacitor is larger than a capacitance of the second capacitor, andwherein the transistor comprises an oxide semiconductor film.3. The memory device according to claim 2 , wherein the transistor comprises:the source electrode and the drain electrode over the oxide semiconductor film;a gate insulating film over the oxide semiconductor film; anda gate electrode over the gate insulating film.4. The memory device according to claim 2 , wherein the source electrode and the drain electrode are provided on and in contact with the oxide semiconductor film.5. The memory device according to claim 2 , wherein the oxide semiconductor film comprises indium claim 2 , gallium claim 2 , and zinc.6. The memory device according to claim 2 , ...

DYNAMIC RANDOM ACCESS MEMORY

A dynamic random access memory is provided, including a main body and a transmission port. The main body has a substrate, a light-emitting module and a light-guiding portion. The substrate is provided with a memory module, the light-emitting module has a carrier board and a light-emitting portion disposed on the carrier board, the light-guiding portion is arranged corresponding to the light-emitting portion, and at least a part of light from the light-emitting portion is projected to outside of the dynamic random access memory through the light-guiding portion. The transmission port is disposed on the substrate, and the transmission port is electrically connected with the memory module. 1. A dynamic random access memory , including:a main body, having a substrate, a light-emitting module and a light-guiding portion, the substrate provided with a memory module, the light-emitting module having a carrier board and a light-emitting portion disposed on the carrier board, the light-guiding portion being arranged corresponding to the light-emitting portion, at least a part of light from the light-emitting portion being projected to outside of the dynamic random access memory through the light-guiding portion;a transmission port, disposed on the substrate and electrically connected with the memory module.2. The dynamic random access memory of claim 1 , wherein the light-guiding portion is formed with a scattering structure claim 1 , the part of the light from the light-emitting portion is projected toward the scattering structure and scattered claim 1 , penetrates through the light-guiding portion evenly claim 1 , and is projected to the outside of the dynamic random access memory.3. The dynamic random access memory of claim 2 , wherein the scattering structure is evenly distributed inside the light-guiding portion claim 2 , and the part of the light from the light-emitting portion is first projected toward the scattering structure and then projected out from a ...

SEMICONDUCTOR DEVICE AND ELECTRONIC COMPONENT

A semiconductor device capable of retaining a signal sensed by a sensor element is provided. The semiconductor device includes a sensor element, a first transistor, a second transistor, and a third transistor. One electrode of the sensor element is electrically connected to a first gate. The first gate is electrically connected to one of a source and a drain of the third transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor. A semiconductor layer includes a metal oxide. 1. A semiconductor device comprising a sensor element , a first transistor , a second transistor , and a third transistor ,wherein the sensor element comprises a pair of electrodes,wherein the first transistor comprises a first gate and a second gate facing the first gate with a semiconductor layer therebetween,wherein one electrode of the sensor element is electrically connected to the first gate,wherein the first gate is electrically connected to one of a source and a drain of the third transistor,wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor, andwherein the semiconductor layer comprises a metal oxide.2. The semiconductor device according to claim 1 ,wherein the sensor element is a photoelectric conversion element, a piezoelectric element, or a heat sensitive element.3. A semiconductor device comprising a photodiode claim 1 , a first transistor claim 1 , and a second transistor claim 1 ,wherein the first transistor comprises a first gate and a second gate facing the first gate with a semiconductor layer therebetween,wherein one electrode of the photodiode is electrically connected to the first gate,wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor,wherein the other of the source and the drain of the first transistor is electrically connected to the other electrode of the photodiode, ...

Nonvolatile Logic Array with Built-In Test Result Signal

A system on chip (SoC) provides a nonvolatile memory array that is configured as n rows by m columns of bit cells. Each of the bit cells is configured to store a bit of data. There are m bit lines each coupled to a corresponding one of the m columns of bit cells. There are m write drivers each coupled to a corresponding one of the m bit lines. An AND gate is coupled to the m bit lines and has an output line coupled to an input of a test controller on the SoC. An OR gate is coupled to the m bit lines and has an output line coupled to an input of the test controller.

Memory architecture with alternating segments and multiple bitlines

Systems and methods presented herein provide a memory system which includes a memory cell array. The memory cell array includes first and second segments with corresponding local bitlines connected to one or more memory cells. The memory cell array also includes first and a second metallization layers. The second metallization layer includes first and second global bitlines. The first metallization layer includes local bitlines. In each of the first segments, local bitlines are connected to one of the first global bitlines. In each of the second segments, local bitlines are connected to one of the second global bitlines.

SEMICONDUCTOR DEVICES HAVING ELECTRO-OPTICAL SUBSTRATES

Memory devices having electro-optical substrates are described herein. In one embodiment, a memory device includes a plurality of memories carried by an electro-optical substrate. The electro-optical substrate can include a circuit board and an optical routing layer on the circuit board. The memories can be (a) electrically coupled to the circuit board and (b) optically coupled to the optical routing layer. In some embodiments, the optical routing layer is a polymer waveguide. 1. A memory device , comprising:an electro-optical substrate including a waveguide and multiple grating couplings, wherein the waveguide defines a plurality of receive optical paths and a plurality of transmit optical paths, wherein the receive optical paths are optically separated from one another, and wherein the transmit optical paths are optically separated from one another; anda plurality of memories carried by the electro-optical substrate, wherein the memories are electrically coupled to the electro-optical substrate, wherein individual ones of the memories are optically coupled, via a corresponding one of the grating couplings, to (a) a corresponding one of the receive optical paths and (b) a corresponding one of the transmit optical paths, and wherein the receive optical paths and the transmit optical paths are different for each of the memories.2. The memory device of claim 1 , further comprising an optical connector optically coupled to the receive optical paths and the transmit optical paths claim 1 , wherein individual ones of the memories are optically coupled to the optical connector via (a) the corresponding one of the receive optical paths and (b) the corresponding one of the transmit optical paths.3. The memory device of wherein the optical connector is configured to be optically coupled to an external device.4. The memory device of wherein the optical connector is a multi-fiber push on (MPO) connector.5. The memory device of wherein the electro-optical substrate further ...

SELF-CALIBRATED SYSTEM ON A CHIP (SoC)

A self-calibrated system on a chip includes a semiconductor substrate, at least one silicon intellectual property (SIP) circuit including dynamic random access memories (DRAMs), a calibration circuit, and a function circuit, a cyclic oscillator, and a control circuit. Each DRAM has a coarsely-tuned capacitance value and a coarsely-tuned resistance value. The calibration circuit has a finely-tuned capacitance value and a finely-tuned resistance value. The cyclic oscillator transmits an oscillating clock signal to the control circuit to choose and provide the coarsely-tuned capacitance value, the coarsely-tuned resistance value, the finely-tuned capacitance value and the finely-tuned resistance value for the function circuit, thereby adjusting a function parameter. 1. A self-calibrated system on a chip (Soc) comprising:a semiconductor substrate; a plurality of dynamic random access memories formed on the semiconductor substrate, wherein each of the plurality of dynamic random access memories has a coarsely-tuned capacitance value and a coarsely-tuned resistance value;', 'a calibration circuit, formed on the semiconductor substrate, having finely-tuned capacitance values and finely-tuned resistance values; and', 'a function circuit formed on the semiconductor substrate and coupled to the plurality of dynamic random access memories and the calibration circuit, wherein the function circuit has a function parameter;, 'at least one silicon intellectual property (SIP) circuit, formed on the semiconductor substrate, comprisinga cyclic oscillator, formed on the semiconductor substrate, generating an oscillating clock signal within a given period; anda control circuit formed on the semiconductor substrate and coupled to the cyclic oscillator, the plurality of dynamic random access memories, and the calibration circuit, wherein the control circuit receives the oscillating clock signal and calculates number of pulses of the oscillating clock signal, when the number of the pulses ...

Semiconductor Memory Device with Hierarchical Bitlines

A dynamic random access memory (DRAM) device has a hierarchical bitline structure with local bitlines and global bitlines formed on different metal layers. The local bitlines are separated into a plurality of local bitline sections, and bitline isolation switches are configured to connect or disconnect the local bitline sections to or from the global bitlines. As a result, the local bitlines with higher per-length capacitance can be made shorter, since the global bitline with lower per-length capacitance is used to route the signal from the cell capacitances of the memory cells to the remote sense amplifiers. 1. A memory device , comprising:a plurality of first lines;a plurality of second lines, each second line including a plurality of second line sections;a plurality of memory cells at intersections of the first lines and the second lines, each memory cell including a cell transistor, and each second line section coupled to the cell transistors of a predetermined number of the memory cells;a plurality of third lines, each third line being associated with at least one of the second lines, wherein the third lines have lower per-length capacitance than the second lines; anda plurality of isolation switches, each isolation switch being associated with at least one of the second line sections and configured to connect the associated second line section to one of the third lines.2. The memory device of claim 1 , wherein the second line isolation switches are connected between the associated one of the second line sections and said one of the third lines.3. The memory device of claim 1 , wherein the second line sections are electrically disconnected from each other.4. The memory device of claim 1 , wherein the second lines are formed on a first layer different from a second layer on which the third lines are formed.5. The memory device of claim 1 , wherein the isolation switches are turned on or off according to a voltage applied to switchlines that are formed on pitch ...

CAPACITOR-LESS MEMORY CELL, DEVICE, SYSTEM AND METHOD OF MAKING SAME

A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell include forming the capacitor-less memory cell in an active area of a substantially physically isolated portion of a bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor. 1. An apparatus , comprising:a capacitor-less memory cell including a vertically-oriented transistor and a horizontally-oriented transistor formed on an active area of a bulk substrate, the horizontally-oriented transistor having a source region common with a drain region of the vertically-oriented transistor in the active area.2. The apparatus of claim 1 , wherein at least a portion of the active area is at least substantially physically isolated from the bulk substrate by a gate of the vertically-oriented transistor configured along a lateral cavity extending into the bulk substrate and undercutting the portion of the active area.3. The apparatus of claim 2 , wherein the capacitor-less memory cell further includes a substrate stem connecting the active area and the bulk substrate claim 2 , the substrate stem defining the lateral cavity.4. The apparatus of claim 3 , wherein the vertically-oriented transistor includes a gate oxide continuously extending along a side of the active area and the substrate stem.5. The apparatus of claim 4 , wherein the gate of the vertically-oriented transistor includes a conductive material coupled with the gate oxide continuously extending along a side of the active area and the substrate stem.6. The apparatus of claim 1 , further comprising an array of ...

ELECTRONIC DEVICE AND DYNAMIC RANDOM ACCESS MEMORY THEREOF

A dynamic random access memory includes a main body which has a substrate portion and a light-emitting portion and a transmission port, the substrate portion includes a board and a first coating layer, the board has a light-transmittable portion and a first face, the first coating layer is coated on the first face and has an emergent light-transmittable portion corresponding to the light-transmittable portion, and the substrate portion has a memory module. The transmission port is disposed on the substrate portion and electrically connected with the memory module. The electronic device includes the dynamic random access memory and further includes a shell portion. The shell portion is covered on two opposite lateral faces of the dynamic random access memory and at least shields the light-emitting portion, and the shell portion further has a second light-transmittable portion corresponding to the emergent light-transmittable portion. 1. A dynamic random access memory , including:a main body, having a substrate portion and a light-emitting portion, the substrate portion including a board and a first coating layer, the board having a light-transmittable portion and a first face, the first coating layer being coated on the first face, the first coating layer being formed with an emergent light-transmittable portion corresponding to the light-transmittable portion, light from the light-emitting portion being projectable through the light-transmittable portion and projectable via the emergent light-transmittable portion to an exterior of the dynamic random access memory, the substrate portion being provided with a memory module;a transmission port, disposed on the substrate portion and electrically connected with the memory module.2. The dynamic random access memory of claim 1 , wherein the board further has a second face claim 1 , the substrate portion further includes a second coating layer coated on the second face claim 1 , the second coating layer is formed with an ...

SEMICONDUCTOR DEVICES HAVING ELECTRO-OPTICAL SUBSTRATES

Memory devices having electro-optical substrates are described herein. In one embodiment, a memory device includes a plurality of memories carried by an electro-optical substrate. The electro-optical substrate can include a circuit board and an optical routing layer on the circuit board. The memories can be (a) electrically coupled to the circuit board and (b) optically coupled to the optical routing layer. In some embodiments, the optical routing layer is a polymer waveguide. 1. A memory device , comprising:an electro-optical substrate having a plurality of receive optical paths and a plurality of transmit optical paths, wherein the receive optical paths are optically separated from one another, and wherein the transmit optical paths are optically separated from one another; and receive optical signals via the corresponding ones of the receive optical paths,', 'transmit optical signals via the corresponding ones of the transmit optical paths and', 'receive power via the electro-optical substrate., 'a plurality of memories carried by the electro-optical substrate, wherein the memories are electrically coupled to the electro-optical substrate, wherein individual ones of the memories are optically coupled to (a) a corresponding one of the receive optical paths and (b) a corresponding one of the transmit optical paths, and wherein the memories are configured to—'}2. The memory device of wherein the electro-optical substrate includes an electrical substrate and a waveguide defining the receive optical paths and the transmit optical paths claim 1 , and wherein the memories are (a) electrically coupled to the electrical substrate and (b) optically coupled to the waveguide.3. The memory device of wherein the waveguide comprises one or more layers of polymer material and does not include a pre-formed substrate.4. The memory device of wherein the waveguide is affixed to the electrical substrate.5. The memory device of wherein the electrical substrate is a printed circuit ...

COMPENSATION CAPACITORS LAYOUT IN SEMICONDUCTOR DEVICE

Apparatuses and methods for arranging compensation capacitors are described. An example apparatus includes: a first conductive layer including a portion; a second conductive layer: a contact coupled to the portion of the first conductive layer; a third conductive layer between the first conductive layer and the second conductive layer, coupled to the contact; one or more capacitor elements wherein each capacitor element of the one or more capacitor elements includes one end coupled to the second conductive layer and another end coupled to the third conductive layer. 1. An apparatus , comprising:a first conductive layer including a power portion and an intermediate portion, the power portion being configured to provide a power supply voltage;a second conductive layer;a third conductive layer between the first conductive layer and the second conductive layer;a contact between the first conductive layer and the third conductive layer, the contact including one end coupled to the intermediate portion of the first conductive layer and another end coupled to the third conductive layer;one or more capacitor elements, wherein each capacitor element of the one or more capacitor elements includes one end coupled to the second conductive layer and another end coupled to the third conductive layer.2. The apparatus of claim 1 , wherein the third conductive layer comprises polycrystalline silicon.3. The apparatus of claim 1 , wherein at least one capacitor element of the one or more capacitor elements comprises:a first electrode layer including a top portion coupled to the third conductive layer;a second electrode layer including a bottom portion coupled to the second conductive layer; andan insulating layer between the first and second electrode layers and configured to insulate the first electrode layer from the second electrode layer.4. The apparatus of claim 3 , wherein the first electrode layer comprises a cylindrical shape with a hollow and further comprises the top portion ...

MEMORY DEVICE WRITE CIRCUITRY

Devices and methods include, for a memory device, generating a main input-output line signal on a main input-output line using driving circuitry. The main input-output line is coupled to multiple sensing amplifiers. Each of the sensing amplifiers each locally generate a local data line from the main data line. Each of the sensing amplifiers also includes multiple local sensing amplifiers that are selectively coupled to the generated local data line for overwriting data in the respective local sensing amplifiers. 2. The memory device of claim 1 , wherein the driving circuitry is configured to receive a first voltage and to drive the main input-output line using the first voltage.3. The memory device of claim 2 , wherein the level shifter is configured to receive a second voltage and to drive the local data line using the second voltage.4. The memory device of claim 3 , wherein the first voltage is less than the second voltage.5. The memory device of claim 3 , wherein the first voltage is half of the second voltage.6. The memory device of comprising a main input-output false line that is complementary to the main input-output line claim 1 , wherein the main input-output false line is generated by the driving circuitry.7. The memory device of claim 6 , wherein the level shifter is configured to generate a local false line using the main input-output false line claim 6 , wherein the local false line is complementary to the local data line.8. The memory device of claim 7 , wherein the driving circuitry is configured to receive a first voltage to drive the main input-output line and the main input-output false line claim 7 , wherein the level shifter is configured to receive a second voltage to drive the local data line and the local false line claim 7 , and wherein the first voltage is lower than the second voltage.9. The memory device of claim 8 , wherein the first voltage is half of the second voltage.10. The memory device of claim 1 , wherein the level shifter ...

Compact Semiconductor Memory Device Having Reduced Number of Contacts, Methods of Operating and Methods of Making

An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.

Semiconductor Device and Method for Driving Semiconductor Device

The semiconductor device includes a first memory cell, and a second memory cell thereover. The first memory cell includes first and second transistors, and a first capacitor. The second memory cell includes third and fourth transistors, and a second capacitor. A gate of the first transistor is electrically connected to one of a source and a drain of the second transistor and the first capacitor. A gate of the third transistor is electrically connected to one of a source and a drain of the fourth transistor and the second capacitor. One of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor. The second and fourth transistors include an oxide semiconductor. A channel length direction of the first and third transistors is substantially perpendicular to a channel length direction of the second and fourth transistors. 1. A semiconductor device comprising:a first transistor comprising silicon in a channel formation region;a first insulating layer over the channel formation region;a first gate electrode over the first insulating layer;a plurality of second transistors over the first transistor, the plurality of second transistors overlapping each other in a cross-sectional view; anda plurality of third transistors over the first transistor, the plurality of third transistors being arranged adjacent to each other in a top view,wherein one of the plurality of the second transistors and one of the plurality of third transistors are provided adjacent to each other.2. A semiconductor device comprising:a first transistor comprising silicon in a channel formation region;a first insulating layer over the channel formation region;a first gate electrode over the first insulating layer;a plurality of second transistors over the first transistor, the plurality of second transistors overlapping each other in a cross-sectional view;a plurality of third transistors over the first transistor, the plurality of third ...

DYNAMIC RANDOM ACCESS MEMORY

A dynamic random access memory, including a main body, a processing unit, a display screen and a transmit port. The main body has a substrate and a shell portion disposed by two opposite side faces of the substrate, the substrate is provided with a memory module; the processing unit is disposed in the main body; the display screen is attached to the main body and viewable from outside of the dynamic random access memory, the display screen is electrically connected with the processing unit, the processing unit can control a display state of the display screen; and the transmit port is disposed on the substrate, and the transmit port is electrically connected with the memory module. 1. A dynamic random access memory , including:a main body, having a substrate and a shell portion disposed by two opposite side faces of the substrate, the substrate provided with a memory module;a processing unit, disposed in the main body;a display screen, fixedly attached to the main body and viewable from outside of the dynamic random access memory, electrically connected with the processing unit, the processing unit being able to control a display state of the display screen;a transmit port, disposed on the substrate and electrically connected with the memory module;wherein the processing unit is electrically connected with a temperature sensing unit, the temperature sensing unit is able to sense a temperature of at least one of the substrate, the memory module and the display screen to produce a sensing signal, and the processing unit is able to control the display screen to show a temperature state according to the sensing signal;wherein the display screen includes a pattern portion and a background portion, the processing unit is able to control color states of the pattern portion and the background portion, respectively, according to the sensing signal, and the pattern portion and the background portion are, at the same time, in different colors.2. The dynamic random access ...

MEMORY DEVICE COMPRISING ELECTRICALLY FLOATING BODY TRANSISTOR

A semiconductor memory instance is provided that includes an array of memory cells. The array includes a plurality of semiconductor memory cells arranged in at least one column and at least one row. Each of the semiconductor memory cells includes a floating body region configured to be charged to a level indicative of a state of the memory cell. Further includes are a plurality of buried well regions, wherein each of the buried well regions can be individually selected, and a decoder circuit to select at least one of the buried well regions. 120-. (canceled)21. A semiconductor memory instance comprising:an array of semiconductor memory cells, the array comprising at least two memory sub-arrays, each memory sub-array comprising: a first bipolar device having a first floating base region, a first collector, and a first emitter; and', 'a second bipolar device having a second floating base region, a second collector, and a second emitter;', 'wherein said first floating base region is common to said second floating base region;', 'wherein said first collector is common to said second collector;', 'wherein said first and second collectors are commonly connected to at least two of said memory cells in one of said memory sub-arrays;', 'wherein when a first semiconductor memory cell of said at least two of said semiconductor memory cells is in a first state and a second semiconductor memory cell of said at least two of said semiconductor memory cells is in a second state, application of a bias applied through said first and second collectors maintains said first semiconductor memory cell in said first state and said second semiconductor memory cell in said second state;, 'a plurality of said semiconductor memory cells arranged in at least one column and at least one row, wherein at least two of said semiconductor memory cells each includea first decoder circuit to select at least one of said at least one column or at least one of said at least one row; anda second decoder ...

SEMICONDUCTOR MEMORY DEVICE WITH BURIED CAPACITOR AND FIN-LIKE ELECTRODES, AND FABRICATION METHOD THEREOF

A semiconductor device includes a substrate having a semiconductor substrate, an insulator layer on the semiconductor substrate, and a silicon device layer on the insulator layer. At least one capacitor cavity with corrugated sidewall surface is disposed within the insulator layer between the semiconductor substrate and the silicon device layer. At least one buried capacitor is provided in the at least one capacitor cavity. The at least one buried capacitor includes an inner electrode and an outer electrode with a capacitor dielectric layer therebetween. 1. A semiconductor device , comprising:a substrate comprising a semiconductor substrate, an insulator layer on said semiconductor substrate, and a silicon device layer on said insulator layer;at least one capacitor cavity with corrugated sidewall surface within said insulator layer between said semiconductor substrate and said silicon device layer;at least one buried capacitor located in said at least one capacitor cavity, said at least one buried capacitor comprising an inner electrode and an outer electrode with a capacitor dielectric layer therebetween; andat least one transistor on said silicon device layer, wherein said at least one transistor comprises a source region, a drain region, a channel region between said source region and said drain region, and a gate over said channel region, and wherein said source region is electrically connected to said inner electrode of said at least one buried capacitor.2. The semiconductor device according to claim 1 , wherein said insulator layer comprises alternating insulating layers.3. The semiconductor device according to claim 2 , wherein said alternating insulating layers comprise alternating silicon oxide layers and silicon nitride layers.4. The semiconductor device according to claim 3 , wherein each of said silicon oxide layers has a thickness of about 2-20 nm and each of said silicon nitride layers has a thickness of about 2-20 nm.5. The semiconductor device ...

SEMICONDUCTOR DEVICES, HYBRID TRANSISTORS, AND RELATED METHODS

Methods of forming a semiconductor device are disclosed. A method comprising forming a hybrid transistor supported by a substrate. Forming the hybrid transistor comprises forming a source including a first low bandgap high mobility material, and forming a channel including a high bandgap low mobility material coupled with the first low bandgap high mobility material. Forming the hybrid transistor further comprises forming a drain including a second low bandgap high mobility material coupled with the a high bandgap low mobility material, and forming a gate separated from the channel via a gate oxide material. Methods of forming a transistor are also disclosed. 1. A method of forming a semiconductor device , the method comprising: forming a hybrid transistor supported by a substrate comprising:forming a source including a first low bandgap high mobility material;forming a channel including a high bandgap low mobility material coupled with the first low bandgap high mobility material;forming a drain including a second low bandgap high mobility material coupled with the a high bandgap low mobility material; andforming a gate separated from the channel via a gate oxide material.2. The method of claim 1 , wherein forming the hybrid transistor supported by the substrate includes forming a vertically configured transistor including forming the source claim 1 , the channel claim 1 , and the drain stacked on the substrate in a vertical orientation.3. The method of claim 1 , wherein forming the hybrid transistor supported by the substrate includes forming a horizontally configured transistor including forming the source claim 1 , the channel claim 1 , and the drain on the substrate in a horizontal orientation.4. The method of claim 1 , wherein forming the channel includes forming the high bandgap low mobility material to have a length that is shorter than a length of the gate.5. The method of claim 1 , wherein the first low bandgap high mobility material is a first doped ...

TRENCH ISOLATION IMPLANTATION

Embodiments of the disclosure include a shallow trench isolation structure having a dielectric material with energetic species implanted to a predetermined depth of the dielectric material. Embodiments further include methods of fabricating the trench structures with the implant of energetic species to the predetermined depth. In various embodiments the implant of energetic species is used to densify the dielectric material to provide a uniform wet etch rate across the surface of the dielectric material. Embodiments also include memory devices, integrated circuits, and electronic systems that include shallow trench isolation structures having the dielectric material with the high flux of energetic species implanted to the predetermined depth of the dielectric material. 120-. (canceled)21. A semiconductor structure comprising:a semiconductor substrate having a shallow trench isolation (STI) structure formed therein,wherein the STI structure includes a trench containing a dielectric material having an energetic species implanted therein.22. The semiconductor structure of claim 21 , further comprising:a pad oxide formed over the semiconductor substrate; anda stop material formed over the pad oxide,wherein the dielectric material includes the energetic species implanted to a depth in the trench at least as great as the depth of the stop material and the pad oxide outside the trench.23. The semiconductor structure of claim 21 , wherein the dielectric material includes the energetic species implanted to at least three percent (3%) of a depth of the trench from the upper surface.24. The semiconductor structure of claim 21 , wherein the dielectric material includes the energetic species implanted to about eighty percent (80%) of a depth of the trench from the upper surface.25. The semiconductor structure of claim 21 , wherein the dielectric material includes the energetic species implanted to a depth of greater than about ten percent (10%) and less than about forty (40%) of ...

DYNAMIC RANDOM ACCESS MEMORY

A dynamic random access memory is provided, including a main body and a transmission port. The main body has a substrate, a light-emitting module and a light-guiding portion. The substrate is provided with a memory module, the light-emitting module has a carrier board and a light-emitting portion disposed on the carrier board, the light-guiding portion is arranged corresponding to the light-emitting portion, and at least a part of light from the light-emitting portion is projected to outside of the dynamic random access memory through the light-guiding portion. The transmission port is disposed on the substrate, and the transmission port is electrically connected with the memory module. 1. A dynamic random access memory , including:a main body, having a substrate, a light-emitting module and a light-guiding portion, the substrate provided with a memory module, the light-emitting module having a carrier board detachably connected to the substrate and a light-emitting portion disposed on the carrier board, the light-guiding portion being arranged corresponding to the light-emitting portion, at least a part of light from the light-emitting portion being projected to outside of the dynamic random access memory through the light-guiding portion;a transmission port, integrally disposed on the substrate and electrically connected with the memory module;wherein the substrate and the light-emitting module are separatably connected with each other;wherein the carrier board includes two lateral wings which respectively protrude on two opposite ends of the carrier board, each lateral wing is thinner than the carrier board, and two fasteners are detachably disposed through the two lateral wings respectively and fixed to the substrate;wherein the substrate and the light-guiding portion are plate-shaped, the substrate, the carrier board and the light-guiding portion are aligned with one another at top end, and the substrate and the light-guiding portion partially overlap with each ...

Method for operating semiconductor device

Provided is a highly reliable semiconductor device, a semiconductor device with a reduced circuit area, a memory element having favorable characteristics, a highly reliable memory element, or a memory element with increased storage capacity per unit volume. A semiconductor device includes a capacitor and a switching element. The capacitor includes a first electrode, a second electrode, and a dielectric. The dielectric is positioned between the first electrode and the second electrode. The switching element includes a first terminal and a second terminal. The first terminal is electrically connected to the first electrode. The following steps are sequentially performed: a first step of turning on the switching element in a first period, a second step of turning off the switching element in a second period, and a third step of turning on the switching element in a third period.

Test method of semiconductor device

The semiconductor device includes a bit line, a transistor, a retention node, and a capacitor. The transistor has a function of charging or discharging the retention node. The capacitor has a function of retaining a potential of the retention node. A voltage greater than the sum of a writing voltage and a threshold voltage is applied to a gate of the transistor. When the transistor is turned on, a first potential is supplied to the bit line with a reference potential in a floating state. A voltage less than the sum of the writing voltage and the threshold voltage is applied to the gate of the transistor. When the transistor is turned on, a second potential is supplied to the bit line with a reference potential in a floating state. With use of the first and second potentials, the threshold voltage of the transistor is calculated without being influenced by parasitic capacitance and variations in the storage capacitance of the capacitor.

MEMORY DEVICE AND METHOD OF CONTROLLING REFRESH OPERATION IN MEMORY DEVICE

A method of controlling a refresh operation for a memory device is disclosed. The method includes storing a first row address corresponding to a first row of a memory cell array, storing one or more second row addresses corresponding to one or more second rows of the memory cell array, the one or more second row addresses corresponding to the first row address, sequentially generating row addresses as a refresh row address during a first refresh interval, for each generated row address, when a generated row address identical to one of the one or more second row addresses is detected, stopping the generation of row addresses and sequentially outputting the one second row address and the first row address as the refresh row address, restarting the generation of the row addresses as the refresh row address after outputting the one second row address and the first row address. 1. A method of controlling a refresh operation for a memory device , the method comprising:storing a first row address corresponding to a first row of a memory cell array;storing one or more second row addresses corresponding to one or more second rows of the memory cell array, the one or more second row addresses corresponding to the first row address;sequentially generating row addresses as a refresh row address during a first refresh interval;for each generated row address, when a generated row address identical to one of the one or more second row addresses is detected, stopping the generation of row addresses and sequentially outputting the one second row address and the first row address as the refresh row address; andrestarting the generation of row addresses as the refresh row address after outputting the one second row address and the first row address.2. The method of claim 1 , wherein the first row address designates a first row including a weak cell having a data retention time shorter than a second refresh interval shorter than the first refresh interval claim 1 , and the one or more ...

MEMORY DEVICE COMPRISING ELECTRICALLY FLOATING BODY TRANSISTOR

A semiconductor memory instance is provided that includes an array of memory cells. The array includes a plurality of semiconductor memory cells arranged in at least one column and at least one row. Each of the semiconductor memory cells includes a floating body region configured to be charged to a level indicative of a state of the memory cell. Further includes are a plurality of buried well regions, wherein each of the buried well regions can be individually selected, and a decoder circuit to select at least one of the buried well regions. 120-. (canceled)21. A semiconductor memory instance comprising:an array of semiconductor memory cells, the array comprising at least two memory sub-arrays, each memory sub-array comprising: a first bipolar device having a first floating base region, a first collector, and a first emitter; and', 'a second bipolar device having a second floating base region, a second collector, and a second emitter;', 'wherein said first floating base region is common to said second floating base region;', 'wherein said first collector is common to said second collector;', 'wherein said first and second collectors are commonly connected to at least two of said memory cells in one of said memory sub-arrays;, 'a plurality of said semiconductor memory cells arranged in at least one column and at least one row, wherein at least two of said semiconductor memory cells each includea first decoder circuit to select at least one of said at least one column or at least one of said at least one row; anda second decoder circuit to select at least one of said memory sub-arrays.22. The semiconductor memory instance of claim 21 , wherein said second decoder circuit is configured to selectively disable at least one of said at least two memory sub-arrays.23. The semiconductor memory instance of claim 21 , wherein said second decoder circuit is configured to apply a bias to said first and second collectors of at least two of said at least two semiconductor memory ...

CAPACITORLESS DRAM CELL

The invention relates to a capacitorless DRAM cell, the cell comprising a heterostructure, a gate structure adjoining the heterostructure in a first direction, a drain structure adjoining the heterostructure in a second direction perpendicular to the first direction, and a source structure adjoining the heterostructure in the direction opposite the second direction, the heterostructure comprising one or more semiconducting channel layers and one or more electrically insulating barrier layers, the channel layers and the barrier layers being alternatingly stacked in the first direction. 1. A capacitorless DRAM cell , the cell comprising:a heterostructure comprising one or more semiconducting channel layers and one or more electrically insulating barrier layers, wherein the channel layers and the barrier layers are alternatingly stacked in a first direction;a gate structure adjoining the heterostructure in the first direction, wherein the gate structure buries the heterostructure;a drain structure adjoining the heterostructure in a second direction perpendicular to the first direction; anda source structure adjoining the heterostructure in a direction opposite the second direction.2. The DRAM cell of claim 1 , wherein the heterostructure comprises a single barrier layer and a single channel layer.3. The DRAM cell of claim 1 , wherein the heterostructure comprises two barrier layers and a single channel layer.4. The DRAM cell of claim 1 , wherein the heterostructure comprises two barrier layers and two channel layers.5. The DRAM cell of claim 1 , wherein the heterostructure comprises three barrier layers and two channel layers.6. The DRAM cell of claim 1 , wherein the heterostructure comprises at least two barrier layers claim 1 , wherein each barrier layer is made of a different material.7. The DRAM cell of claim 1 , wherein the heterostructure comprises at least two channel layers claim 1 , wherein each channel layer is made of a different material.8. The DRAM cell of ...

Semiconductor device

The first circuit has a function of retaining data in a first period during which a power supply voltage is supplied. The second circuit has functions of saving the data retained in the first circuit in the first period and retaining the data saved from the first circuit in a second period during which application of the power supply voltage is stopped. The third circuit has functions of saving the data retained in the second circuit in the second period and retaining the data saved from the second circuit in a third period during which application of the power supply voltage is stopped. The second circuit is capable of being written with the data for a shorter time than the third circuit. The third circuit is capable of maintaining the data for a longer time than the second circuit.

SEMICONDUCTOR MEMORY DEVICE

The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell array overlaps with the driver circuit. Accordingly, the integration degree of the semiconductor memory device can be increased as compared to the case where a driver circuit and a memory cell array are provided in the same plane of a substrate containing a singe crystal semiconductor material. 1. (canceled)2. A semiconductor memory device comprising:a driver circuit;an insulating layer over the driver circuit; and a transistor; and', 'a capacitor overlapping with and electrically connected to the transistor,, 'a memory cell over the insulating layer, the memory cell comprisingwherein the capacitor comprising a first layer comprising a first conductive material and a second layer comprising a second conductive material,wherein the first layer comprises a first portion and a second portion,wherein the second layer comprises a portion,wherein the portion of the second layer is sandwiched between the first portion and the second portion in a horizontal direction, andwherein the memory cell is electrically connected to the driver circuit.3. The semiconductor memory device according to claim 2 , wherein the memory cell overlaps with the driver circuit.4. The semiconductor memory device according to claim 2 , wherein a channel region of the transistor comprises an oxide semiconductor material.5. The semiconductor memory device according to claim 2 , wherein the capacitor and a channel region of the transistor overlap with each other.6. The semiconductor memory device according to claim 2 , wherein the semiconductor memory device is a DRAM memory device.7. The semiconductor memory device according to claim 2 , wherein the driver circuit comprises a transistor ...

SEMICONDUCTOR MEMORY STRUCTURE AND METHOD FOR PREPARING THE SAME

The present disclosure provides a semiconductor memory structure including a substrate, a plurality of first trenches disposed in the substrate, a plurality of second trenches disposed in the substrate and spaced apart from the first trenches, a plurality of buried digit lines disposed in the first trenches, and a plurality of buried word lines disposed in the second trenches. The first trenches include a first depth, and the second trenches include a second depth. The second depth of the second trenches is greater than the first depth of the first trenches. Top surfaces of the buried word lines are lower than bottom surfaces of the buried digit lines. 1. A semiconductor memory structure comprising:a substrate;a plurality of first trenches disposed in the substrate, the first trenches comprising a first depth;a plurality of second trenches disposed in the substrate and spaced apart from the first trenches, wherein the second trenches comprises a second depth greater than the first depth;a plurality of buried digit lines disposed in the first trenches; anda plurality of buried word lines disposed in the second trenches,wherein top surfaces of the buried digit lines are lower than bottom surfaces of the buried word lines.2. The semiconductor memory structure of claim 1 , wherein the first trenches and the second trenches are alternately arranged.3. The semiconductor memory structure of claim 1 , further comprising a plurality of first isolation structures individually disposed on the buried digit lines in the first trenches.4. The semiconductor memory structure of claim 1 , further comprising a plurality of second isolation structures disposed in the second trenches claim 1 , wherein the buried word lines are spaced apart from the substrate by the second isolation structures.5. The semiconductor memory structure of claim 1 , further comprising a plurality of first doped regions individually disposed in the substrate under the first trenches.6. The semiconductor memory ...

Method for preparing a semiconductor memory structure

The present disclosure provides a method for preparing a semiconductor memory structure. The method includes the following steps: providing a substrate comprising a plurality of active regions extending in a first direction; forming a plurality of first trenches in the substrate, the first trenches comprising a first depth and extending in a second direction different from the first direction; forming a plurality of buried digit lines in the first trenches; forming a plurality of second trenches in the substrate, the second trenches comprising a second depth and extending in a third direction different from the first direction and the second direction; deepening portions of the second trenches to form a plurality of third trenches in the substrate, the third trenches comprising a third depth; and forming a plurality of buried word lines in the third trenches.

Semiconductor Device

A semiconductor device that can retain data for a long time is provided. The semiconductor device includes a first transistor and a second transistor. The first transistor contains an oxide semiconductor in a channel formation region. The second transistor includes a first gate and a second gate. A gate of the first transistor is connected to a first electrode of the first transistor. The first electrode of the first transistor is connected to the second gate. A negative potential is applied to a second electrode of the first transistor. The first electrode and the second electrode of the first transistor include a first end portion and a second end portion, respectively. The first end portion and the second end portion face each other. The first end portion includes a first arc and the second end portion includes a second arc when seen from the top. The radius of curvature of the second arc is larger than that of the first arc.