Semiconductor memory device and operating method thereof

A semiconductor memory device includes a reference voltage generation block suitable for selecting and outputting one of a plurality of reference voltages in response to a voltage division enable signal, as an input reference voltage, in response to a selection enable signal; and a control signal generation block suitable for generating the voltage division enable signal and the selection enable signal in response to a reference voltage information.

3-amido-1,2-benzoisoxazole derivatives, process for preparation, and use thereof

The present invention relates to 3-amido-1,2-benzoisoxazole derivatives and their salts represented by formula 1, processes for preparation and usees thereof. More particularly, it relates to a method for improving its bioavailability introducing amino acid residue to the amine group of a 3-amido-1,2-benzoisoxazole. The compounds according to the present invention are used as an antagonist against Leukotriene-B-4 receptor, an inhibitor or therapeutics of osteoroposis, thus inhibiting osteolysis and stimulating osteogensis.

3-amido-1,2-benzoisoxazole derivatives, process for preparation, and use thereof

The present invention relates to 3-amido-1,2-benzoisoxazole derivatives and their salts represented by formula 1, processes for preparation and usees thereof. More particularly, it relates to a method for improving its bioavailability introducing amino acid residue to the amine group of a 3-amido-1,2-benzoisoxazole. The compounds according to the present invention are used as an antagonist against Leukotriene-B-4 receptor, an inhibitor or therapeutics of osteoroposis, thus inhibiting osteolysis and stimulating osteogensis.

Reservoir capacitor and semiconductor device including the same

A reservoir capacitor includes a first capacitor group having two or more capacitors, which are serially coupled to each other between a first power voltage supply terminal and a second power voltage supply terminal, a second capacitor group having two or more capacitors, which are serially coupled to each other between a third power voltage supply terminal and a fourth power voltage supply terminal and a connection line suitable for electrically coupling a first coupling node between the capacitors of the first capacitor group to a second coupling node between the capacitors of the second capacitor group.

METHOD FOR FORMING CAPACITOR AND SEMICONDUCTOR DEVICE USING THE SAME

A semiconductor device includes a MOS capacitor including a gate, a source, and a drain, a cylinder capacitor including a top electrode, a dielectric layer, and a bottom electrode, and a metal interconnection that connects the gate to the bottom electrode. 1. A decoupling capacitor unit in a semiconductor device comprising:a first capacitor connected between a power supply voltage source and a ground voltage source;a second capacitor connected between the power supply voltage source and the ground voltage source; andfirst and second cylinder capacitors connected in series between the power supply voltage source and the ground voltage source.2. The decoupling capacitor unit of claim 1 , wherein the first capacitor is a PMOS capacitor and the second capacitor is an NMOS capacitor.3. The decoupling capacitor unit of claim 2 , wherein the PMOS capacitor is formed over a N-well in a semiconductor substrate claim 2 , the PMOS capacitor comprising:a gate formed over the N-well and coupled to the ground voltage;a source formed in the N-well and coupled to the power supply voltage; anda drain formed in the N-well and coupled to the power supply voltage.4. The decoupling capacitor unit of further comprising:a gate oxide layer formed between the gate of the PMOS capacitor and the N-well in the semiconductor substrate.5. The decoupling capacitor unit of claim 3 , wherein the first cylinder capacitor comprises:a first bottom electrode connected to the gate of the PMOS capacitor;a first dielectric layer formed over the first bottom electrode; anda top electrode formed over the first dielectric layer, wherein the first and second cylinder capacitors are connected in series via the top electrode.6. The decoupling capacitor unit of claim 5 , further comprising:a first metal interconnection configured to connect the first bottom electrode and the gate of the PMOS capacitor.7. The decoupling capacitor unit of claim 2 , wherein the NMOS capacitor is formed over a semiconductor ...

SEMICONDUCTOR INTEGRATED CIRCUIT

A semiconductor integrated circuit includes a first voltage line to which a first ground voltage is applied, a second voltage line to which a second ground voltage is applied, a third voltage line to which a first power supply voltage is applied, and a coupling unit including a MOS transistor having a source coupled to the first voltage line, a drain coupled to the second voltage line, and a gate coupled to the third voltage line. 1. A semiconductor integrated circuit comprising:a first voltage line to which a first ground voltage is applied;a second voltage line to which a second ground voltage is applied;a third voltage line to which a first power supply voltage is applied; anda coupling unit including a MOS transistor having a source coupled to the first voltage line, a drain coupled to the second voltage line, and a gate coupled to the third voltage line.2. The semiconductor integrated circuit of claim 1 , further comprising:a fourth voltage line to which a second power supply voltage is applied; anda pre-driver configured to be driven by the second power supply voltage and the second ground voltage, receive data in synchronization with a clock signal, and drive a pull-up signal and a pull-down signal.3. The semiconductor integrated circuit of claim 2 , further comprising an output driver configured to be driven by the first power supply voltage and the first ground voltage claim 2 , receive the pull-up signal and the pull-down signal claim 2 , and drive output data.4. The semiconductor integrated circuit of claim 2 , further comprising:a first voltage stabilization unit coupled between the first power supply voltage and the first ground voltage; anda second voltage stabilization unit coupled between the second power supply voltage and the second ground voltage.5. A semiconductor integrated circuit comprising:a coupling unit configured to reduce high frequency power noises, wherein the coupling unit includes:a well region formed between isolation films on a ...

Semiconductor apparatus for preventing crosstalk between signal lines

A semiconductor integrated circuit apparatus includes a semiconductor substrate, a plurality of signal lines, and at least one interface member. The signal lines are disposed on the semiconductor substrate. The interface member is disposed in the semiconductor substrate between the adjacent signal lines among the signal lines to pierce the semiconductor substrate.

INTERNAL VOLTAGE GENERATION CIRCUIT AND METHOD

An internal voltage generation method includes the steps of: setting first to third sections by using a reference voltage; determining to which section an internal voltage level corresponds, among the first to third sections; and generating the internal voltage by controlling a voltage pumping amount according to a section corresponding to the internal voltage level. 1. An internal voltage generation method comprising the steps of:setting first to third sections by using a reference voltage;determining to which section an internal voltage level corresponds, among the first to third sections; andgenerating the internal voltage by controlling a voltage pumping amount according to the section corresponding to the internal voltage level.2. The internal voltage generation method according to claim 1 , wherein setting first to third sections by using the reference voltage comprises dividing the level of the reference voltage by a predetermined interval using a plurality of resistors claim 1 , and generates a plurality of sub voltages.3. The internal voltage generation method according to claim 1 , wherein the voltage level of the first section is higher than the voltage level of the second section claim 1 , and the voltage level of the second section is higher than the voltage level of the third section.4. The internal voltage generation method according to claim 3 , wherein determining to which section the internal voltage level corresponds comprises generating a detection signal by determining to which section the internal voltage level corresponds claim 3 , andwherein generating the internal voltage comprises controlling the voltage pumping amount in response to the detection signal.5. The internal voltage generation method according to claim 4 , wherein the detection signal comprises first to third detection signals claim 4 , andwherein determining to which section the internal voltage level corresponds comprises activating the first detection signal when the internal ...

WIRELESS SIGNAL TRANSMITTING/RECEIVING APPARATUS FOR SEMICONDUCTOR SYSTEM

A wireless signal transmitting/receiving apparatus for a semiconductor system is disclosed The apparatus includes a serializer/deserializer (SERDES) circuit and a coupling pad. The SERDES circuit outputs a parallel input signal as a serial signal during transmission, and outputs a serial input signal as a parallel signal during reception. The coupling pad generates an inductively coupled wireless signal according to the serial signal outputted from the SERDES circuit, and provides a signal generated by inductive coupling with an external device as the serial input signal of the SERDES circuit. 1. A wireless signal transmitting/receiving apparatus for a semiconductor system , comprising:a transmission control unit coupled to receive transmit data from a signal transmission line;a reception control unit coupled to provide received data to the signal transmission line;a serializer/deserializer (SERDES) circuit coupled to the transmission control unit and the reception control unit, the SERDES circuit serializing parallel data received from the transmission control unit and providing parallel data to the reception control unit;an input/output circuit configured to separate and amplify the serializing parallel data to provide the serializing parallel data to a coupling pad, and provide a received signal from the coupling pad to the SERDES circuit; andthe coupling pad configured to generate a wireless signal corresponding to the separated and amplified signal and to provide signals corresponding to wireless signals received from an external device to the input/output circuit.2. The apparatus according to claim 1 , wherein the input/output circuit further comprising a single-to-differential buffer for generating a single input signal as a differential output signal.3. The apparatus according to claim 1 , further comprising a path control unit coupled between the transmission control unit claim 1 , the reception control unit and the SERDES circuit configured to provide ...

SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS HAVING THROUGH SILICON VIAS

A semiconductor integrated circuit apparatus includes a semiconductor substrate, a plurality of through-silicon vias (TSVs) formed in the semiconductor substrate, and an impedance path blocking unit located between the plurality of TSVs. 1. A semiconductor integrated circuit apparatus comprising:a semiconductor substrate;a plurality of through-silicon vias (TSVs) formed in the semiconductor substrate; andan impedance path blocking unit located between the plurality of TSVs.2. The semiconductor integrated circuit apparatus according to claim 1 , wherein the impedance path blocking unit comprises a dummy via formed in the semiconductor substrate and having a substantially similar structure as the TSVs.3. The semiconductor integrated circuit apparatus according to claim 2 , wherein the dummy via is in a floating state.4. The semiconductor integrated circuit apparatus according to claim 1 , wherein the impedance path blocking unit is formed at substantially the same distance from respective TSVs having a voltage difference.5. The semiconductor integrated circuit apparatus according to claim 1 , wherein the impedance path blocking unit is formed in a center of a region surrounded by the TSVs.6. The semiconductor integrated circuit apparatus according to claim 1 , wherein the plurality of TSVs have a voltage difference from each other.7. A semiconductor integrated circuit apparatus comprising:a semiconductor substrate;first to fourth TSVs formed through the semiconductor substrate; anda dummy via arranged at substantially a same distance from the first to fourth TSVs, and configured to block parasitic impedance paths between the first to fourth TSVs, respectively.8. The semiconductor integrated circuit apparatus according to claim 7 , wherein the dummy via a substantially similar structure as the first to fourth TSVs.9. The semiconductor integrated circuit apparatus according to claim 8 , further comprising an insulation layer interposed between the dummy via and the ...

METHOD FOR REDUCING OUTPUT DATA NOISE OF SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR APPARATUS IMPLEMENTING THE SAME

Provided is a method for reducing output data noise of a semiconductor apparatus which includes a plurality of output buffers to output data. The method includes the steps of: driving low data to a specific output buffer among the plurality of output buffers, and driving data transiting from a high level to a low level to the other output buffers; and measuring the magnitude of data noise occurring in output data of the specific output buffer, and deciding slew rates of the plurality of output buffers based on the measurement result. 1. A method for reducing output data noise of a semiconductor apparatus which includes a plurality of output buffers to output data , the method comprising the steps of:driving low data to a specific output buffer among the plurality of output buffers, and driving data transiting from a high level to a low level to the other output buffers; andmeasuring the magnitude of data noise occurring in output data of the specific output buffer, and deciding slew rates of the plurality of output buffers based on the measurement result.2. The method according to claim 1 , wherein the step of measuring the magnitude of data noise and deciding the slew rates is comprises the steps of:measuring the magnitude of the data noise occurring in the output data of the specific output buffer and converting the measured magnitude into a digital code value; andcontrolling the slew rates of the plurality of output buffers based on the digital code value.3. The method according to claim 2 , wherein the step of measuring the magnitude of the data noise and converting the measured magnitude comprises the step of removing a DC component from the output data of the specific output buffer and extracting an AC component as the data noise.4. The method according to claim 2 , wherein the step of measuring the magnitude of the data noise and converting the measured magnitude comprises the steps of:amplifying the magnitude of the data noise;rectifying the amplified data ...

Semiconductor apparatus

A semiconductor apparatus may include a transmission circuit, a reception circuit, and a pad commonly coupled to the transmission circuit and the reception circuit. When either the transmission circuit or the reception circuit is activated, parasitic capacitance of a line coupled to the transmission circuit, the reception circuit, and the pad is varied.

Semiconductor device and semiconductor package using the same

A semiconductor device may include a comparator and a pad. The comparator may compare a voltage level of a reference node with a voltage level of a reference voltage to generate a code. The comparator may include an output driver modeling unit configured to adjust a current flowing to the reference node depending on a code value of the code to the reference node. The pad may be coupled to the reference node. A total impedance of the reference node, the output driver modeling unit, and components and signal lines coupled therebetween may correspond to a total impedance of the reference node, the pad, and components and signal lines coupled therebetween.

Reservoir capacitor and semiconductor device including the same

A reservoir capacitor includes a first capacitor group having two or more capacitors, which are serially coupled to each other between a first power voltage supply terminal and a second power voltage supply terminal, a second capacitor group having two or more capacitors, which are serially coupled to each other between a third power voltage supply terminal and a fourth power voltage supply terminal and a connection line suitable for electrically coupling a first coupling node between the capacitors of the first capacitor group to a second coupling node between the capacitors of the second capacitor group.

BUFFER CIRCUIT

A buffer circuit configured to receive first and second input signals through first and second input transistors coupled to a first power voltage node, output a first output signal through a first output node and a second output signal through a second output node based on the first and second input signals. A load circuit is coupled among the first output node, the second output node, and a second power voltage node and a resistance value is adjusted based on at least one of the first and second output signals. 1. A buffer circuit comprising:a first input transistor coupled between a first power voltage node and a second output node, and configured to change a voltage level of the second output node based on a first input signal;a second input transistor coupled between the first power voltage node and a first output node, and configured to change a voltage level of the first output node based on a second input signal;a first load resistor coupled between the second output node and a second power voltage node;a second load resistor coupled between the first output node and the second power voltage node; andat least one switching transistor configured to couple the first load resistor and the second load resistor to each other in parallel based on the at least one of a first output signal from the first output node and a second output signal from the second output node.2. The buffer circuit of claim 1 , wherein the buffer circuit is configured to decrease a duty ratio of the first output signal output from the first output node by turning on the at least one switching transistor in a time period when the voltage level of the first output node is a logic high level.3. The buffer circuit of claim 1 , wherein the buffer circuit is configured to increase a duty ratio of the first output signal output from the first output node by turning on the at least one switching transistor in a time period when the voltage level of the second output node is a logic high level.4. ...

Power metal mesh and semiconductor memory device and method including the same

A power metal mesh and a semiconductor memory device including the same are provided. As the power metal mesh configured to reduce noise coupling generated between adjacent chips disposed on an interposer, a band stop filter unit including an inductor and a capacitor coupled in parallel is disposed between the adjacent chips to effectively reduce the noise coupling of a specific frequency band generated between the adjacent chips.

SEMICONDUCTOR DEVICE

This technology provides a semiconductor device capable of controlling an equivalent series resistance (ESR) generated from decoupling capacitors. To this end, the semiconductor device may include a plurality of decoupling capacitors electrically coupled between a first wire and a second wire in parallel, and a plurality of switches coupled between common source/drain terminals of two adjacent decoupling capacitors of the plurality of decoupling capacitors and the second wire. 1. A semiconductor device comprising:a plurality of decoupling capacitors electrically coupled between a first wire and a second wire in parallel; anda plurality of switches coupled between common source/drain terminals of two adjacent decoupling capacitors of the plurality of decoupling capacitors and the second wire.2. The semiconductor device of claim 1 , further comprising a switch control unit suitable for controlling the plurality of switches.3. The semiconductor device of claim 2 , wherein the switch control unit selectively turns on or off the plurality of switches in response to a plurality of control signals.4. The semiconductor device of claim 2 , wherein the plurality of decoupling capacitors are grouped into a plurality of groups.5. The semiconductor device of claim 4 , wherein the switch control unit turns on or off the plurality of switches in response to a plurality of control signals applied to the respective groups.6. The semiconductor device of claim 2 , wherein the switch control unit comprises a mode register set (MRS)7. The semiconductor device of claim 1 , wherein each of the plurality of switches comprises at least one transistor.8. The semiconductor device of claim 1 , whereinthe first wire is a power source voltage line, andthe second wire is a ground voltage line.9. The semiconductor device of claim 1 , wherein claim 1 , when N switches are turned off claim 1 , gates of (N+1) decoupling capacitors having common source/drain terminals coupled to the turned-off ...

METHOD FOR REDUCING OUTPUT DATA NOISE OF SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR APPARATUS IMPLEMENTING THE SAME

Provided is a semiconductor apparatus which includes a plurality of output buffers configured to connect a plurality of power sources, and a data noise measuring unit configured to fix an output data of a selected output buffer among the plurality of output buffers to have a specific level, measure a noise of the output data using a capacitance and control a slew rate of the plurality of output buffers based on the noise. 1. A semiconductor apparatus comprising:a plurality of output buffers configured to electrically connect a plurality of power sources; anda data noise measuring unit configured to fix an output data of a selected output buffer among the plurality of output buffers to have a specific level, measure a noise of the output data using a capacitance and control a slew rate of the plurality of output buffers to based on the noise.2. The semiconductor apparatus according to claim 1 , wherein the data noise measuring unit is configured to generate a slew rate control signal to control the slew rate.3. The semiconductor apparatus according to claim 2 , wherein when the magnitude of the noise is larger than a reference value claim 2 , the slew rates of the plurality of output buffers are decreased in response to the slew rate control signal.4. The semiconductor apparatus according to claim 2 , wherein when the magnitude of the noise is smaller than a reference value claim 2 , the slew rates of the plurality of output buffers are increased in response to the slew rate control signal.5. The semiconductor apparatus according to claim 1 , wherein during initial setting claim 1 , low data is driven to the selected output buffer claim 1 , and data transiting from a high level to a low level are driven to the other output buffers.6. The semiconductor apparatus according to claim 1 , wherein during initial setting claim 1 , high data is driven to the selected output buffer claim 1 , and data transiting from a low level to a high level are driven to the other output ...

SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF

A semiconductor memory device includes a reference voltage generation block suitable for selecting and outputting one of a plurality of reference voltages in response to a voltage division enable signal, as an input reference voltage, in response to a selection enable signal; and a control signal generation block suitable for generating the voltage division enable signal and the selection enable signal in response to a reference voltage information. 1. A semiconductor memory device comprising:a reference voltage generation block suitable for selecting and outputting one of a plurality of reference voltages in response to a voltage division enable signal, as an input reference voltage, in response to a selection enable signal; anda control signal generation block suitable for generating the voltage division enable signal and the selection enable signal in response to a reference voltage information.2. The semiconductor memory device according to claim 1 , wherein the reference voltage information includes information regarding operation of the reference voltage generation block.3. The semiconductor memory device according to claim 2 , wherein the selection enable signal is activated earlier than the voltage division enable signal in a first operation period claim 2 , and the voltage division enable signal is deactivated earlier than the selection enable signal in a second operation period.4. The semiconductor memory device according to claim 1 , wherein the reference voltage generation block comprises:an enable signal generation unit suitable for generating an enable signal in response to an internal refresh signal and the voltage division enable signal;a voltage division unit suitable for voltage-dividing the power supply voltage in response to the enable signal, and generating the plurality of reference voltages;a decoding unit suitable for decoding external mode control signals, and generating decoding signals; anda selection unit suitable for selecting one among ...

Transmission circuit, and semiconductor apparatus and system using the same

A transmission circuit may be provided. The transmission circuit may include a strobe control circuit and an output driver. The strobe control circuit may generate strobe driving signals based on information and a clock signal. The output driver may generate a strobe signal by driving a signal transmission line. The transmission circuit may drive the signal transmission line to a specified level for a predetermined time after transmission of the strobe signal is completed.

Amplifier, and receiving circuit, semiconductor apparatus, and system using the amplifier

A receiving circuit may include an amplifier. The amplifier may include a first amplification circuit and a second amplification circuit. The first amplification circuit may be configured to differentially amplify a first input signal and a reference signal and configured to generate output signals. The second amplification circuit may be configured to differentially amplify a second input signal and the reference signal and configured to generate the output signals.

Oscillating signal generating circuit and a semiconductor apparatus using the same

An oscillating signal generating circuit drives an oscillating signal to a first logic level based on a first control signal, which is generated by delaying the oscillating signal through a clock delaying circuit, and drives the oscillating signal to a second logic level based on a second control signal, which is generated by delaying the oscillating signal by a fixed delay amount.

Oszillationssignal-erzeugungsschaltung und eine halbleitervorrichtung unter verwendung derselben

Eine Oszillationssignal-Erzeugungsschaltung treibt ein Oszillationssignal auf einen ersten Logikpegel auf der Grundlage eines ersten Steuersignals, das durch Verzögern des Oszillationssignals durch eine Taktverzögerungsschaltung erzeugt wird, und treibt das Oszillationssignal auf einen zweiten Logikpegel auf der Grundlage eines zweiten Steuersignals, das durch Verzögern des Oszillationssignals um einen festen Verzögerungsbetrag erzeugt wird.

Transmission circuit, and semiconductor apparatus and system using the same

A transmission circuit may be provided. The transmission circuit may include a strobe control circuit and an output driver. The strobe control circuit may generate strobe driving signals based on information and a clock signal. The output driver may generate a strobe signal by driving a signal transmission line. The transmission circuit may drive the signal transmission line to a specified level for a predetermined time after transmission of the strobe signal is completed.

3-amido-1,2-benzisoxazolderivate, herstellungsverfahren und deren verwendung

Oscillating signal generating circuit and a semiconductor apparatus using the same

An oscillating signal generating circuit drives an oscillating signal to a first logic level based on a first control signal, which is generated by delaying the oscillating signal through a clock delaying circuit, and drives the oscillating signal to a second logic level based on a second control signal, which is generated by delaying the oscillating signal by a fixed delay amount.

Pre-charge control circuit and voltage generation circuit including the same

A voltage generation circuit includes a voltage generation unit configured to generate a reference voltage using a power supply voltage and output the reference voltage through a voltage output node. The voltage generation circuit also includes a pre-charge unit configured to drive the voltage output node using the power supply voltage in response to a pre-charge control signal. The voltage generation circuit further includes a pre-charge control unit configured to generate at least one sampling voltage using the power supply voltage and generate the pre-charge control signal according to a result obtained by comparing the at least one sampling voltage with the reference voltage.

Semiconductor apparatus reducing a parasitic capacitance

A semiconductor apparatus may include a transmission circuit, a reception circuit, and a pad commonly coupled to the transmission circuit and the reception circuit. When either the transmission circuit or the reception circuit is activated, parasitic capacitance of a line coupled to the transmission circuit, the reception circuit, and the pad is varied.

Semiconductor devices and semiconductor systems relating to the prevention of a potential difference between signals from being reversed

A semiconductor device may be provided. The semiconductor device may be configured to adjust a level of a first strobe signal to a predetermined level during a first time period. The semiconductor device may be configured to adjust a swing width of the first strobe signal during a second time period.