Receiver of semiconductor memory apparatus

A receiver of a semiconductor memory apparatus includes a first input transistor configured to be turned ON when an input signal is equal to or more than a predetermined level; a second input transistor configured to be turned ON when the input signal is equal to or less than the predetermined level; a first output node voltage control unit configured to increase a voltage level of an output node when the first input transistor is turned ON; a second output node voltage control unit configured to decrease the voltage level of the output node when the second input transistor is turned ON; a third input transistor configured to increase the voltage level of the output node when an inversion signal of the input signal is equal to or less than the predetermined voltage level; and a fourth input transistor configured to decrease the voltage level of the output node when the inversion signal of the input signal is equal to or more than the predetermined voltage level.

INPUT BUFFER CIRCUIT OF SEMICONDUCTOR APPARATUS

The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal. 1. An input buffer circuit of a semiconductor apparatus , comprising:a bias voltage level control unit configured to output a control bias voltage by decreasing a bias voltage, when a level of the bias voltage becomes higher than a target level;a first buffering unit configured to generate a compare signal by comparing a voltage level of an input signal with a level of a reference voltage, when being activated by receiving the control bias voltage; anda second buffering unit configured to generate an output signal by comparing the voltage levels of the input signal and the compare signal.2. The input buffer circuit of a semiconductor apparatus according to claim 1 , wherein the bias voltage level control unit outputs the bias voltage as the control bias voltage claim 1 , when the bias voltage level is lower than the target voltage level.3. The input buffer circuit of a semiconductor apparatus according to claim 2 , wherein the bias voltage level control unit includes:a level detector configured to generate a detection signal by detecting the bias voltage level;a voltage dropper configured to generate a down voltage by decreasing the bias voltage; anda selector configured to selectively output the bias voltage or the down voltage as the control bias voltage, in response to the detection ...

Delay locked loop circuit and memory device having the same

A DLL circuit includes a multiphase clock signal generating unit configured to produce a plurality of multiphase clock signals by delaying a reference clock signal for a unit delay time and to produce an enable signal that is enabled when one of the plurality of the multiphase clock signals synchronizes with the reference clock signal at a frequency, and a multiphase clock signal selecting unit configured to delay one of the plurality of the multiphase clock signals for a predetermined time in response to a first control signal, to compare a phase of a delayed multiphase clock signal with a phase of the reference clock signal, and to output one of the plurality of the multiphase clock signals as a delayed clock signal, wherein a phase of the delayed clock signal synchronizes with the phase of the reference clock signal when the enable signal is enabled.

Semiconductor integrated circuit capable of overcoming clock signal jitter

A semiconductor integrated circuit includes a voltage supplying unit that supplies a first regulated voltage and a second regulated voltage by using a first reference voltage and a second reference voltage, respectively, and a clock buffer unit that supplies an output clock clocking within a range of the first regulated voltage and the second regulated voltage.

DELAY LOCKED LOOP AND DELAY LOCKING METHOD HAVING BURST TRACKING SCHEME

A Delay Locked Loop (DLL) includes a replica delay unit configured to delay an output clock to generate a feedback clock; a phase detector configured to measure a phase difference between the feedback clock and an input clock; a quantization unit configured to quantize the phase difference measured by the phase detector; and a delay unit configured to delay the input clock based on a quantization result from the quantization unit to generate the output clock.

Phase mixer and delay locked loop including the same

A phase mixer includes a phase mixing unit configured to mix a phase of a first input signal and a phase of a second input signal in response to a phase control signal and output a phase mixed signal whose phase is varied by one or more units of a unit phase value, and a phase value adjusting unit configured to control an operation of the phrase mixing unit so that the unit phase value is adjusted in response to a code signal coding at least one of a process, voltage, or temperature (PVT) variation.

Low power variable delay circuit

A variable delay circuit includes at least a fixed delay unit, a first selection unit, and variable delay unit. The fixed delay unit receives an input signal and a first delay selection signal indicative of a first delay, and outputs a first delayed signal that is substantially the input signal delayed by the first delay. The first selection unit receives the input signal, the first delayed signal, and a second delay selection signal, and outputs either the input signal or the first delayed signal based on the second delay selection signal to the variable delay unit. The variable delay unit also receives a third delay selection signal indicative of a third delay, and outputs a output signal that is substantially the output signal of the selection unit delayed by a third delay. The first delay is 0 or X multiples of M delay units. The third delay is a delay selected from 0 to N delay units.

Delay locked loop and delay locking method having burst tracking scheme

A Delay Locked Loop (DLL) includes a replica delay unit configured to delay an output clock to generate a feedback clock; a phase detector configured to measure a phase difference between the feedback clock and an input clock; a quantization unit configured to quantize the phase difference measured by the phase detector; and a delay unit configured to delay the input clock based on a quantization result from the quantization unit to generate the output clock.

DELAY LOCKED LOOP CIRCUIT AND DELAY LOCKING METHOD

A delay locked loop circuit includes a phase detecting unit for detecting a phase difference between a reference clock signal and a feedback clock signal, and for producing a phase difference detection signal, a code generating unit for producing a digital code signal according to the phase difference detection signal, a control current generating unit for generating a control current using the digital code signal, and a current controlled delay line for producing the feedback clock signal by delaying the reference clock signal by a delay time varied by the control current.

Semiconductor memory apparatus

A semiconductor memory apparatus includes a clock generator configured to generate an internal clock signal, an asynchronous data input buffer configured to buffer a data input signal through a data pad to output a buffered data signal, and a synchronous data input buffer configured to buffer the buffered data signal synchronously with the internal clock signal, wherein a length of a line, through which the internal clock signal is transmitted to the synchronous data input buffer, is configured to be substantially the same with a length of a line, through which the buffered data is transmitted to the synchronous data input buffer.

PHASE MIXER AND DELAY LOCKED LOOP INCLUDING THE SAME

A phase mixer includes a phase mixing unit configured to mix a phase of a first input signal and a phase of a second input signal in response to a phase control signal and output a phase mixed signal whose phase is varied by one or more units of a unit phase value, and a phase value adjusting unit configured to control an operation of the phrase mixing unit so that the unit phase value is adjusted in response to a code signal coding at least one of a process, voltage, or temperature (PVT) variation.

Voltage level comparison circuit of semiconductor memory apparatus, voltage adjustment circuit using voltage level comparison circuit, and semiconductor memory apparatus using the same

A voltage adjustment circuit of a semiconductor memory apparatus includes a control voltage generating unit configured to distribute an external voltage for selectively outputting a plurality of distribution voltages as a control voltage in response to a control signal, the plurality of the distribution voltages each have different voltage levels, a comparing unit configured to include a voltage supply unit configured to control an external voltage supplied to a first node and a second node if a level of an output voltage is higher than a level of a reference voltage in response to a level of the control voltage, and a detection signal generating unit configured to drop potential levels of the first and second nodes according to the levels of the output voltage and the reference voltage, and to output the potential level of the second node as a detection signal, and a voltage generating unit configured to drive the external voltage according to a potential level of the detection signal ...

Buffer circuit of semiconductor memory apparatus

A buffer circuit of a semiconductor memory apparatus includes a buffering section configured to increase or decrease a voltage level of an output node by comparing a voltage level of an input signal with a voltage level of a reference voltage. A voltage compensation section applies a voltage to the output node in proportion to a variation of the reference voltage when the level of the reference voltage is lower than a target level.

Duty cycle correction circuit with reduced current consumption

A duty cycle correction circuit includes a signal generating unit including a first signal generating unit coupled to a power supply voltage terminal and configured to output a complementary output signal of an output signal in response to a clock signal, and a second signal generating unit coupled to the power supply voltage terminal and configured to output the output signal in response to a complementary clock signal of the clock signal; a variable resistor unit coupled between the first and second signal generating units configured to vary an amount of current flowing into the signal generating unit according to a duty correction control signal, the duty correction control signal having a voltage level determined based on a voltage level of the output signal; and a current source coupled between the variable resistor unit and a ground voltage terminal configured to supply current to the signal generating unit.

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device is able to generate an output enable signal in response to a read command and CAS latency information. The semiconductor memory device includes a delay locked loop configured to detect a phase difference of an external clock signal and a feedback clock signal, generate a delay control signal corresponding to the detected phase difference, and generate a DLL clock signal by delaying the external clock signal for a time corresponding to the delay control signal, a delay configured to output an active signal as an output enable reset signal in response to the delay control signal and an output enable signal generator configured to be reset in response to the output enable reset signal and generate an output enable signal in response to a read signal and a CAS latency signal by counting the external clock signal and the DLL clock signal.

SAMPLING CIRCUIT

A sampling circuit for use in a semiconductor device, includes a first sampling unit configured to sample a data signal in synchronism with a reference clock signal and output a first output signal, a second sampling unit configured to sample a delayed data signal in synchronism with the reference clock signal and output a second output signal, and an output unit configured to combine the first and second output signals and output a sampling data signal.

INTERNAL SUPPLY VOLTAGE GENERATING CIRCUIT AND METHOD FOR GENERATING INTERNAL SUPPLY VOLTAGE

An internal supply voltage generating circuit includes a clock comparator configured to compare a first clock signal having clock information corresponding to a level of a reference voltage with a second clock signal having clock information corresponding to a level of an internal supply voltage, a control signal generator configured to generate a driving control voltage having a voltage level corresponding to an output signal of the clock comparator, and a driver configured to drive a terminal of the internal supply voltage in response to the driving control voltage.

Semiconductor IC device having power-sharing and method of power-sharing thereof

A semiconductor IC device capable of power-sharing includes a first power line configured to be supplied with a first power, a second power line configured to be supplied with a second power, a switching block configured to connect the first power line with the second power line in response to a first control signal, and a power-sharing control block configured to generate the control signal in accordance with a plurality of operation command signals.

Method and mobile communication terminal for communicating voice message using packet-switched scheme

Disclosed are a mobile communication terminal for and a method of transmitting/receiving voice messages using a packet-switched scheme. According to the present invention, it is possible to allow mobile carriers to promote the use efficiency of communication channels since mobile communication terminals transmit/receive voice messages over a data channel rather than a voice channel.

OUTPUT DRIVING DEVICE

An output driving device capable of improving a slew rate is provided. The output driving device includes a push-pull type driving unit configured with a pull-up PMOS transistor and a pull-down NMOS transistor, wherein body biases of the pull-up PMOS transistor and the pull-down NMOS transistor are controlled for control of a slew rate of an output signal of the driving unit.

LATENCY CONTROL CIRCUIT, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND METHOD FOR CONTROLLING LATENCY

A latency control circuit includes a path calculator configured to calculate a delay value of a path that an input signal is to go through inside a chip and output the delay value as path information, a delay value calculator configured to output delay information representing a delay value for delaying the input signal based on a latency value of the input signal and the path information, and a delayer configured to delay the input signal by a delay corresponding to the delay information.

POWER NOISE DETECTING DEVICE AND POWER NOISE CONTROL DEVICE USING THE SAME

A power noise detecting device includes a plurality of power lines, and a power noise detecting part configured to detect power noise by rectifying voltages of the plurality of power lines and converting the rectified voltages into effective voltages.

Duty cycle correction circuit and semiconductor integrated circuit apparatus including the same

A duty cycle correction circuit includes a phase splitter configured to control a phase of a DLL clock signal to generate a rising clock signal and a falling clock signal, a clock delay unit configured to delay the rising clock signal and the falling clock signal in response to control signals to generate a delayed rising clock signal and a delayed falling clock signal, a duty ratio correction unit configured to generate a correction rising clock signal and a correction falling clock signal that toggle in response to an edge timing of the delayed rising clock signal and the delayed falling clock signal, and a delay control unit configured to detect duty cycles of the correction rising clock signal and the correction falling clock signal to generate the control signals.

Output driving device

An output driving device capable of improving a slew rate is provided. The output driving device includes a push-pull type driving unit configured with a pull-up PMOS transistor and a pull-down NMOS transistor, wherein body biases of the pull-up PMOS transistor and the pull-down NMOS transistor are controlled for control of a slew rate of an output signal of the driving unit.

INTERNAL SUPPLY VOLTAGE GENERATING CIRCUIT AND METHOD FOR GENERATING INTERNAL SUPPLY VOLTAGE

An internal supply voltage generating circuit includes a clock comparator configured to compare a first clock signal having clock information corresponding to a level of a reference voltage with a second clock signal having clock information corresponding to a level of an internal supply voltage, a control signal generator configured to generate a driving control voltage having a voltage level corresponding to an output signal of the clock comparator; and a driver configured to drive a terminal of the internal supply voltage in response to the driving control voltage.

Semiconductor memory device and method for generating output enable signal

A semiconductor memory device is able to generate an output enable signal in response to a read command and CAS latency information. The semiconductor memory device includes a delay locked loop configured to detect a phase difference of an external clock signal and a feedback clock signal, generate a delay control signal corresponding to the detected phase difference, and generate a DLL clock signal by delaying the external clock signal for a time corresponding to the delay control signal, a delay configured to output an active signal as an output enable reset signal in response to the delay control signal and an output enable signal generator configured to be reset in response to the output enable reset signal and generate an output enable signal in response to a read signal and a CAS latency signal by counting the external clock signal and the DLL clock signal.

VOLTAGE REGULATOR

A voltage regulator with an adaptive bandwidth, including a first buffer chain, a voltage generating unit, a trimming capacitor unit, a second buffer chain, and a control unit. The first buffer chain delays a clock signal using an external voltage as a supply voltage. The voltage generating unit generates a regulated voltage on the basis a reference voltage. The trimming capacitor unit controls a load capacitance of the voltage generating unit. The second buffer chain delays the clock signal using the regulated voltage as a supply voltage. The control unit adjusts the load capacitance by detecting a delay difference of clocks output from the first and second buffer chains.

Input buffer circuit of semiconductor apparatus

The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.

DATA PATTERN DETECTING CIRCUIT AND OUTPUT DRIVER INCLUDING THE SAME

Disclosed is an output driver capable of solving problems that occur when outputting the same data successively by using a data pattern detecting circuit. The data pattern detecting circuit includes a first data storage unit configured to receive data of a first line and store the received data until a next data is inputted through the first line, a second data storage unit configured to receive data of a second line and store the received data until a next data is inputted through the second line, and a detection signal output unit configured to activate a pattern detection signal when data stored in the first data storage unit and data stored in the second data storage unit have the same logic level.

Voltage regulator for a synchronous clock system to reduce clock tree jitter

A voltage regulator with an adaptive bandwidth, including a first buffer chain, a voltage generating unit, a trimming capacitor unit, a second buffer chain, and a control unit. The first buffer chain delays a clock signal using an external voltage as a supply voltage. The voltage generating unit generates a regulated voltage on the basis a reference voltage. The trimming capacitor unit controls a load capacitance of the voltage generating unit. The second buffer chain delays the clock signal using the regulated voltage as a supply voltage. The control unit adjusts the load capacitance by detecting a delay difference of clocks output from the first and second buffer chains.

Short message service management system equipped with additional data transfer function

Disclosed is an SMS management system equipped with an additional data transfer function. The SMS management system includes a message transmission module, wherein the message transmission module includes: a capacity calculating unit for calculating the volume of the message content entered by the message input unit and calculating a residual capacity by deducting the volume from the maximum capacity of a short message; an additional data processing unit for attaching additional data to the short message within the limit of the residual capacity calculated by the capacity calculating unit; and a message transmission unit for transmitting the short message with the attached additional data processed by the additional data processing unit to the recipient's mobile station number entered by the number input unit.

SEMICONDUCTOR MEMORY APPARATUS

A semiconductor memory apparatus includes a clock generator configured to generate an internal clock signal, an asynchronous data input buffer configured to buffer a data input signal through a data pad to output a buffered data signal, and a synchronous data input buffer configured to buffer the buffered data signal synchronously with the internal clock signal, wherein a length of a line, through which the internal clock signal is transmitted to the synchronous data input buffer, is configured to be substantially the same with a length of a line, through which the buffered data is transmitted to the synchronous data input buffer.

Input buffer circuit of semiconductor apparatus

The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.

Sampling circuit

A sampling circuit for use in a semiconductor device, includes a first sampling unit configured to sample a data signal in synchronism with a reference clock signal and output a first output signal, a second sampling unit configured to sample a delayed data signal in synchronism with the reference clock signal and output a second output signal, and an output unit configured to combine the first and second output signals and output a sampling data signal.

Semiconductor integrated circuit

A semiconductor integrated circuit can include a first voltage pad, a second voltage pad, and a voltage stabilizing unit that is connected between the first voltage pad and the second voltage pad. The first voltage pad can be connected to a first internal circuit, and the second voltage pad can be connected to a second internal circuit.

Latency control circuit, semiconductor memory device including the same, and method for controlling latency

A latency control circuit includes a path calculator configured to calculate a delay value of a path that an input signal is to go through inside a chip and output the delay value as path information, a delay value calculator configured to output delay information representing a delay value for delaying the input signal based on a latency value of the input signal and the path information, and a delayer configured to delay the input signal by a delay corresponding to the delay information.

Power noise detecting device and power noise control device using the same

A power noise detecting device includes a plurality of power lines, and a power noise detecting part configured to detect power noise by rectifying voltages of the plurality of power lines and converting the rectified voltages into effective voltages.

Internal supply voltage generating circuit and method for generating internal supply voltage

An internal supply voltage generating circuit includes a clock comparator configured to compare a first clock signal having clock information corresponding to a level of a reference voltage with a second clock signal having clock information corresponding to a level of an internal supply voltage, a control signal generator configured to generate a driving control voltage having a voltage level corresponding to an output signal of the clock comparator; and a driver configured to drive a terminal of the internal supply voltage in response to the driving control voltage.

Reservoir capacitor and semiconductor device including the same

A reservoir capacitor includes a first capacitor group having two or more capacitors, which are serially coupled to each other between a first power voltage supply terminal and a second power voltage supply terminal, a second capacitor group having two or more capacitors, which are serially coupled to each other between a third power voltage supply terminal and a fourth power voltage supply terminal and a connection line suitable for electrically coupling a first coupling node between the capacitors of the first capacitor group to a second coupling node between the capacitors of the second capacitor group.

Method and mobile communication terminal for communicating voice message using packet-switched scheme

Disclosed are a mobile communication terminal for and a method of transmitting/receiving voice messages using a packet-switched scheme. According to the present invention, it is possible to allow mobile carriers to promote the use efficiency of communication channels since mobile communication terminals transmit/receive voice messages over a data channel rather than a voice channel.

SEMICONDUCTOR MEMORY CHIP AND INTEGRATED CIRCUIT

A semiconductor memory chip includes: a driving voltage reception unit configured to receive a power supply voltage and a ground voltage; a first data driving unit configured to be supplied with the power supply voltage and the ground voltage, and drive first data to output the driven first data through a first data line; a second data driving unit configured to be supplied with the power supply voltage and the ground voltage, and drive second data to output the driven second data through a second data line; and a MOS transistor coupled between the first data line and the second data line. 1. A semiconductor memory chip provided with a power supply voltage and a ground voltage comprising:a first data driving unit provided with the power supply voltage and the ground voltage and configured to drive first data to output the driven first data through a first data line;a second data driving unit provided with the power supply voltage and the ground voltage and configured to drive second data to output the driven second data through a second data line; anda MOS transistor coupled between the first data line and the second data line.2. The semiconductor memory chip of claim 1 , further comprising a driving voltage reception unit configured to receive the power supply voltage and the ground voltage and provide the power supply voltage and the ground voltage to the first and second data driving units.3. The semiconductor memory chip of claim 2 , wherein the driving voltage reception unit comprises a capacitor coupled between a power supply voltage transmission medium including a terminal and a ground voltage transmission medium including a terminal.4. The semiconductor memory chip of claim 2 , wherein components comprising the driving voltage reception unit and the first and second data driving units are packaged claim 2 , and wherein the power supply voltage and the ground voltage are provided to the first and second data driving units through power lines provided in the ...

SUB-MOUNT, LIGHT EMITTING DEVICE INCLUDING SUB-MOUNT AND METHODS OF MANUFACTURING SUCH SUB-MOUNT AND/OR LIGHT EMITTING DEVICE

A sub-mount adapted for AC and DC operation of devices mountable thereon, light emitting devices including such a sub-mount, and methods of manufacturing such a sub-mount are provided. The sub-mount includes a base substrate having first and second surfaces, a conductive pattern on the first surface, first and second pairs of first and second electrodes on the second surface and vias extending through the base substrate between the first and second surfaces. The conductive pattern includes a first set of mounting portions and two via portions along a first electrical path between the first pair of first and second electrodes, and a second set of mounting portions and two via portions along a second electrical path between the second pair of first and second electrodes, the via portions connecting respective portions of the conductive pattern to respective electrodes. 1. A sub-mount adapted for AC and DC operation of devices mountable thereon , the sub-mount comprising:a base substrate including a first surface and a second surface, the first surface being different from the second surface;a conductive pattern on the first surface;a first pair of first and second electrodes on the second surface of the base substrate;a second pair of first and second electrodes on the second surface of the base substrate; anda plurality of vias extending through the base substrate between the first surface and the second surface,wherein:the conductive pattern includes a first set of mounting portions and two via portions along a first electrical path between the first pair of first and second electrodes, and a second set of mounting portions and two via portions along a second electrical path between the second pair of first and second electrodes, the first path being independent of the second path, andeach of the via portions connecting respective portions of the conductive pattern to a respective one of the electrodes of the first and second pair of first and second electrodes ...

METHOD FOR REDUCING OUTPUT DATA NOISE OF SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR APPARATUS IMPLEMENTING THE SAME

Provided is a method for reducing output data noise of a semiconductor apparatus which includes a plurality of output buffers to output data. The method includes the steps of: driving low data to a specific output buffer among the plurality of output buffers, and driving data transiting from a high level to a low level to the other output buffers; and measuring the magnitude of data noise occurring in output data of the specific output buffer, and deciding slew rates of the plurality of output buffers based on the measurement result. 1. A method for reducing output data noise of a semiconductor apparatus which includes a plurality of output buffers to output data , the method comprising the steps of:driving low data to a specific output buffer among the plurality of output buffers, and driving data transiting from a high level to a low level to the other output buffers; andmeasuring the magnitude of data noise occurring in output data of the specific output buffer, and deciding slew rates of the plurality of output buffers based on the measurement result.2. The method according to claim 1 , wherein the step of measuring the magnitude of data noise and deciding the slew rates is comprises the steps of:measuring the magnitude of the data noise occurring in the output data of the specific output buffer and converting the measured magnitude into a digital code value; andcontrolling the slew rates of the plurality of output buffers based on the digital code value.3. The method according to claim 2 , wherein the step of measuring the magnitude of the data noise and converting the measured magnitude comprises the step of removing a DC component from the output data of the specific output buffer and extracting an AC component as the data noise.4. The method according to claim 2 , wherein the step of measuring the magnitude of the data noise and converting the measured magnitude comprises the steps of:amplifying the magnitude of the data noise;rectifying the amplified data ...

CONTROLLER AND DISPLAY DEVICE INCLUDING THE SAME

Disclosed is a display device including a display panel having a plurality of pixels, each of the pixels including at least two subpixels, the display panel including a first display area and a second display area, the second display area being disposed to overlap an optical module, a memory configured to store shape information of the second display area including position information of a starting point, vertical length information of the second display area, and line-based direction information and width information indicating the border of the second display area, and a controller configured to change an image that is displayed in at least one of the first display area and the second display area using the shape information of the second display area and to perform control such that the changed image is displayed on the display panel. 1. A display device comprising:a display panel having a plurality of pixels, each of the pixels comprising at least two subpixels, the display panel comprising a first display area and a second display area, the second display area being disposed to overlap an optical module;a memory configured to store shape information of the second display area comprising position information of a starting point, vertical length information of the second display area, and line-based direction information and width information for indicating a border of the second display area; anda controller configured to change an image that is displayed in at least one of the first display area and the second display area of the display panel using the shape information of the second display area and to perform control such that the changed image is displayed on the display panel.2. The display device according to claim 1 , whereinthe shape information of the second display area comprises left border information about a left border located at a left side based on a central axis of the second display area and right border information about a right border ...

Controller and display device including the same

Disclosed is a display device including a display panel having a plurality of pixels, the display panel comprising a first display area having first resolution and a second display area having second resolution, the second resolution being lower than the first resolution, and a controller configured to generate display area information of each of the plurality of pixels, to blur an image that is displayed in the second display area based on the display area information, and to perform control such that the blurred image is displayed on the display panel.

CONTROLLER AND DISPLAY DEVICE INCLUDING THE SAME

Disclosed is a display device including a display panel having a plurality of pixels, the display panel comprising a first display area and a second display area, the second display area being disposed so as to overlap an optical module, and a controller configured to generate display area information of each of the plurality of pixels and border information of pixels provided in a border area located within a predetermined range from a border between the first display area and the second display area, to change an image that is displayed in at least one of the first display area or the second display area based on the display area information and the border information upon determining that the optical module is operated, and to perform control such that the changed image is displayed on the display panel. 1. A display device comprising:a display panel having a plurality of pixels, the display panel comprising a first display area and a second display area, the second display area being disposed so as to overlap an optical module; anda controller configured to generate display area information of each of the plurality of pixels and border information of pixels provided in a border area located within a predetermined range from a border between the first display area and the second display area, to change an image that is displayed in at least one of the first display area and the second display area based on the display area information and the border information upon determining that the optical module is operated, and to perform control such that the changed image is displayed on the display panel.2. The display device according to claim 1 , wherein the controller changes image data of pixels claim 1 , the display area information of each of which has a value corresponding to the second display area to black image data upon determining that the optical module is operated.3. The display device according to claim 1 , whereinthe border area comprises a first border ...

CONTROLLER AND DISPLAY DEVICE INCLUDING THE SAME

Disclosed is a display device including a display panel having a plurality of pixels, the display panel including a first display area having first resolution and a second display area having second resolution, the second resolution being lower than the first resolution, and a controller configured to generate border information of pixels provided in a border area located within a predetermined range from the border between the first display area and the second display area, to correct an image that is displayed in the border area based on the border information, and to perform control such that the corrected image is displayed on the display panel. 1. A display device comprising:a display panel having a plurality of pixels, the display panel comprising a first display area having first resolution and a second display area having second resolution, the second resolution being lower than the first resolution; anda controller configured to generate border information of pixels provided in a border area located within a predetermined range from a border between the first display area and the second display area, to change an image that is displayed in the border area based on the border information, and to perform control such that the changed image is displayed on the display panel.2. The display device according to claim 1 , wherein the controller adjusts luminance of image data of the pixels provided in the border area.3. The display device according to claim 1 , wherein the controller performs adjustment such that luminance of image data of the pixels provided in the border area has a value between luminance of image data of pixels provided in an area other than the border area in the first display area and luminance of image data of pixels provided in an area other than the border area in the second display area.4. The display device according to claim 3 , wherein the controller performs adjustment such that the luminance of the image data of the pixels provided ...

Reservoir capacitor and semiconductor device including the same

A reservoir capacitor includes a first capacitor group having two or more capacitors, which are serially coupled to each other between a first power voltage supply terminal and a second power voltage supply terminal, a second capacitor group having two or more capacitors, which are serially coupled to each other between a third power voltage supply terminal and a fourth power voltage supply terminal and a connection line suitable for electrically coupling a first coupling node between the capacitors of the first capacitor group to a second coupling node between the capacitors of the second capacitor group.

Power metal mesh and semiconductor memory device and method including the same

A power metal mesh and a semiconductor memory device including the same are provided. As the power metal mesh configured to reduce noise coupling generated between adjacent chips disposed on an interposer, a band stop filter unit including an inductor and a capacitor coupled in parallel is disposed between the adjacent chips to effectively reduce the noise coupling of a specific frequency band generated between the adjacent chips.

Semiconductor memory device having pads

A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.

Semiconductor memory device having pads

A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.

SEMICONDUCTOR DEVICE

This technology provides a semiconductor device capable of controlling an equivalent series resistance (ESR) generated from decoupling capacitors. To this end, the semiconductor device may include a plurality of decoupling capacitors electrically coupled between a first wire and a second wire in parallel, and a plurality of switches coupled between common source/drain terminals of two adjacent decoupling capacitors of the plurality of decoupling capacitors and the second wire. 1. A semiconductor device comprising:a plurality of decoupling capacitors electrically coupled between a first wire and a second wire in parallel; anda plurality of switches coupled between common source/drain terminals of two adjacent decoupling capacitors of the plurality of decoupling capacitors and the second wire.2. The semiconductor device of claim 1 , further comprising a switch control unit suitable for controlling the plurality of switches.3. The semiconductor device of claim 2 , wherein the switch control unit selectively turns on or off the plurality of switches in response to a plurality of control signals.4. The semiconductor device of claim 2 , wherein the plurality of decoupling capacitors are grouped into a plurality of groups.5. The semiconductor device of claim 4 , wherein the switch control unit turns on or off the plurality of switches in response to a plurality of control signals applied to the respective groups.6. The semiconductor device of claim 2 , wherein the switch control unit comprises a mode register set (MRS)7. The semiconductor device of claim 1 , wherein each of the plurality of switches comprises at least one transistor.8. The semiconductor device of claim 1 , whereinthe first wire is a power source voltage line, andthe second wire is a ground voltage line.9. The semiconductor device of claim 1 , wherein claim 1 , when N switches are turned off claim 1 , gates of (N+1) decoupling capacitors having common source/drain terminals coupled to the turned-off ...

ELECTRICAL CHARACTERISTICS OF PACKAGE SUBSTRATES AND SEMICONDUCTOR PACKAGES INCLUDING THE SAME

Package substrates are provided. The package substrate may include a power line and a ground line on a first surface of a substrate body; a plurality of signal lines on the first surface between the power line and the ground line; and a lower ground pattern and a lower power pattern positioned on a second surface of the substrate body opposite to the first surface. The lower ground pattern may be disposed to be opposite to the power line and the lower power pattern may be disposed to be opposite to the ground line. Related semiconductor packages are also provided. 1. A package substrate comprising:a power line and a ground line configured on a first surface of a substrate body;a couple of signal lines on the first surface between the power line and the ground line; anda lower ground pattern and a lower power pattern positioned on a second surface of the substrate body opposite to the first surface,wherein the lower ground pattern is disposed to be opposite to the power line and the lower power pattern is disposed to be opposite to the ground line.2. The package substrate of claim 1 , wherein the lower ground pattern is disposed to face the power line and fully overlaps with the power line when viewed from a plan view.3. The package substrate of claim 1 , wherein the lower power pattern is disposed to face the ground line and fully overlaps with the ground line when viewed from a plan view.4. The package substrate of claim 1 , wherein when the lower ground pattern is vertically projected onto the first surface claim 1 , the projected lower ground pattern overlaps with at least a portion of the power line; andwherein when the lower power pattern is vertically projected onto the first surface, the projected lower power pattern overlaps with at least a portion of the ground line.5. The package substrate of claim 1 , further comprising an upper power pattern and an upper ground pattern on the first surface claim 1 ,wherein the upper power pattern is electrically ...

Semiconductor memory device having pads

A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.

METHOD FOR REDUCING OUTPUT DATA NOISE OF SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR APPARATUS IMPLEMENTING THE SAME

Provided is a semiconductor apparatus which includes a plurality of output buffers configured to connect a plurality of power sources, and a data noise measuring unit configured to fix an output data of a selected output buffer among the plurality of output buffers to have a specific level, measure a noise of the output data using a capacitance and control a slew rate of the plurality of output buffers based on the noise. 1. A semiconductor apparatus comprising:a plurality of output buffers configured to electrically connect a plurality of power sources; anda data noise measuring unit configured to fix an output data of a selected output buffer among the plurality of output buffers to have a specific level, measure a noise of the output data using a capacitance and control a slew rate of the plurality of output buffers to based on the noise.2. The semiconductor apparatus according to claim 1 , wherein the data noise measuring unit is configured to generate a slew rate control signal to control the slew rate.3. The semiconductor apparatus according to claim 2 , wherein when the magnitude of the noise is larger than a reference value claim 2 , the slew rates of the plurality of output buffers are decreased in response to the slew rate control signal.4. The semiconductor apparatus according to claim 2 , wherein when the magnitude of the noise is smaller than a reference value claim 2 , the slew rates of the plurality of output buffers are increased in response to the slew rate control signal.5. The semiconductor apparatus according to claim 1 , wherein during initial setting claim 1 , low data is driven to the selected output buffer claim 1 , and data transiting from a high level to a low level are driven to the other output buffers.6. The semiconductor apparatus according to claim 1 , wherein during initial setting claim 1 , high data is driven to the selected output buffer claim 1 , and data transiting from a low level to a high level are driven to the other output ...

ELECTRONIC COMPONENT PACKAGE AND METHOD OF MANUFACTURING THE SAME

An electronic component package includes a frame having a cavity, an electronic component disposed in the cavity of the frame, a first metal layer disposed on an inner wall of the cavity of the frame, an encapsulant encapsulating the electronic component, and a redistribution layer disposed below the frame and the electronic component. 1. An electronic component package comprising:a frame having a cavity;an electronic component disposed in the cavity of the frame;a first metal layer disposed on an inner wall of the cavity of the frame;an encapsulant encapsulating at least portion of the electronic component; anda redistribution layer disposed below the frame and the electronic component.2. The electronic component package of claim 1 , wherein the first metal layer encloses around side surfaces of the electronic component.3. The electronic component package of claim 2 , wherein the first metal layer entirely covers the inner wall of the cavity of the frame.4. The electronic component package of claim 1 , further comprising a second metal layer disposed on a lower surface of the frame.5. The electronic component package of claim 4 , wherein the second metal layer is connected to the first metal layer.6. The electronic component package of claim 4 , wherein the second metal layer entirely covers the lower surface of the frame.7. The electronic component package of claim 4 , further comprising a third metal layer disposed on an upper surf ace of the frame.8. The electronic component package of claim 7 , wherein the third metal layer is connected to the first metal layer.9. The electronic component package of claim 7 , wherein the third metal layer entirely covers the upper surface of the frame.10. The electronic component package of claim 7 , wherein the second and third metal layers are redistribution patterns or dummy patterns.11. The electronic component package of claim 10 , further comprising a penetration wiring penetrating through the frame.12. The electronic ...

Electronic component package and method of manufacturing the same

An electronic component package includes a frame having a cavity, an electronic component disposed in the cavity of the frame, a first metal layer disposed on an inner wall of the cavity of the frame, an encapsulant encapsulating the electronic component, and a redistribution layer disposed below the frame and the electronic component.

Photomask

Sub-mount, light emitting device including sub-mount and methods of manufacturing such sub-mount and/or light emitting device

Method for forming pattern

Light emitting device including a light emitting element mounted on a sub-mount

A sub-mount adapted for AC and DC operation of devices mountable thereon, light emitting devices including such a sub-mount, and methods of manufacturing such a sub-mount are provided. The sub-mount includes a base substrate having first and second surfaces, a conductive pattern on the first surface, first and second pairs of first and second electrodes on the second surface and vias extending through the base substrate between the first and second surfaces. The conductive pattern includes a first set of mounting portions and two via portions along a first electrical path between the first pair of first and second electrodes, and a second set of mounting portions and two via portions along a second electrical path between the second pair of first and second electrodes, the via portions connecting respective portions of the conductive pattern to respective electrodes.

Method for forming a pattern by silylation

Mask pattern of a semiconductor device and a method of manufacturing fine patterns using the same

A mask pattern for manufacturing a resist pattern of a semiconductor device through photolithography is provided with an additional mask pattern whose size is such that resist patterns are not formed after exposure on the spaces thereof. Using such a mask pattern, a manufacturing method of fine patterns enables the formation of specific patterns having an improved profile.

Sub-mount, light emitting device including sub-mount and methods of manufacturing such sub-mount and/or light emitting device

Process for making a motif

Sampling circuit

【課題】入力されるデジタル信号のパルス幅を拡張させた後、サンプリング動作が行われるようにすることができる半導体装置のサンプリング回路を提供すること。 【解決手段】本発明のサンプリング回路は、データ信号を受信し、クロック信号を基準としてサンプリングする第１のサンプリング部と、前記データ信号を所定時間の分だけ遅延させた信号を受信し、前記クロック信号を基準としてサンプリングする第２のサンプリング部と、前記第１のサンプリング部および第２のサンプリング部の出力信号を結合してサンプリングデータ信号を出力する出力部とを備える。 【選択図】図３

Trip mechanism for circuit breaker

Disclosed is a trip mechanism for a circuit breaker, capable of maintaining a constant characteristic of a normal trip operation in spite of changes in installation angles of the circuit breaker including a horizontal installation, a perpendicular installation and an inclination installation, the trip mechanism including, a coil 211 configured to generate a magnetic absorption force due to a fault current on a circuit, a stationary core 211c fixed to a lower portion of the coil within the coil, a movable core 214 movable down to the stationary core within the coil by the magnetic absorption force generated from the coil, and a trip lever 216 rotatably connected to the movable core so as to be pulled by the movable core when the movable core is downwardly moved and configured to trigger the switching mechanism such that the movable contactor is moved to an open circuit position.

Mask and method for manufacturing the same

A mask and a method far manufacturing the same, which can form a correct pattern on a semiconductor wafer having steps, includes a mask substrate having steps oppositely correspond with stepped structure on said semiconductor wafer and a opaque mask pattern for cutting off a light on a mask substrate where said steps is formed, to thereby enable the same exposure focus to be formed in step region and non-step region on a semiconductor wafer. Further, a clean and correct pattern can be formed by controlling the amount of exposure irradiated onto step region and non-step region on a semiconductor wafer.

Photo mask and method for manufacturing same

A photo mask and method for manufacturing the same increase the capacitance of a capacitor by improving the proximity effect of a mask pattern. The photo mask includes a transparent substrate, an opaque mask pattern for defining an optical transmission area on the substrate, and an optical transmittance control film pattern for suppressing proximity effect in the optical transmission area. The proximity effect is suppressed by forming an optical transmittance control film pattern in the transmission area between the individual portions of the opaque mask pattern, so that the mask pattern shape can be exactly transferred onto a substrate.

Sub-mount, light-emitting device and method of manufacturing a sub-mount

ein lichtemittierendes Bauelement mit einer Sub-Halterung sowie ein Verfahren zur Herstellung einer Sub-Halterung. Spezieller bezieht sich die Erfindung auf eine Sub-Halterung und ein lichtemittierendes Bauelement, das eine Sub-Halterung verwendet, die für Wechselstrom(AC)- und/oder Gleichstrom(DC)-Betrieb optimiert sind. Eine Sub-Halterung gemäß der Erfindung beinhaltet ein Basissubstrat (100), ein leitfähiges Muster (110) auf dem Basissubstrat, ein erstes Paar von ersten und zweiten Elektroden (130, 140) und ein zweites Paar von ersten und zweiten Elektroden (132, 142) auf dem Basissubstrat sowie eine Mehrzahl von Durchkontakten (120), die sich durch das Basissubstrat erstrecken, wobei das leitfähige Muster einen ersten Satz von Montagebereichen (112) und zwei Durchkontaktbereiche entlang eines ersten elektrischen Pfades zwischen dem ersten Paar von ersten und zweiten Elektroden sowie einen zweiten Satz von Montagebereichen (112) und zwei Durchkontaktbereiche entlang eines zweiten elektrischen Pfades zwischen dem zweiten Paar von ersten und zweiten Elektroden beinhaltet, wobei der erste Pfad unabhängig von dem zweiten Pfad ist und wobei jeder der Durchkontaktbereiche jeweilige Bereiche des leitfähigen Musters mit einer jeweiligen der Elektroden des ersten und zweiten Paars von ersten und zweiten Elektroden durch einen jeweiligen der Durchkontakte hindurch verbindet. Verwendung z.B. für lichtemittierende ...  a light-emitting device with a sub-holder and a method for producing a sub-holder. More particularly, the invention relates to a sub-mount and a light-emitting device using a sub-mount optimized for AC and / or DC (DC) operation. A sub-mount according to the invention includes a base substrate (100), a conductive pattern (110) on the base substrate, a first pair of first and second electrodes (130, 140), and a second pair of first and second electrodes (132, 142 ) on the base substrate and a plurality of vias (120) extending through the base substrate, the ...

Gray-tone mask and pattern formation and ion implantation methods using the same

A mask having a mask pattern (3) with multiple steps is provided, as are methods of forming a pattern and implanting ions using such a mask. In a mask for transcribing a mask pattern on a semiconductor substrate using light, the mask pattern includes a gray-tone mask pattern (3,103,105,107,109) in which optical transmittance is selectively varied, so that the transmittance of light passing through the mask is controlled to vary in a selective manner. When implanting ions after forming an ion implanting mask pattern on a semiconductor substrate using such a mask, the depth of ions implanted on the semiconductor substrate can be varied, and the number of masks required for frequent ion implantation processes can be reduced.

Mask for adjusting line width of photoresist pattern

Controller and display device including the same

Disclosed is a display device including a display panel having a plurality of pixels, the display panel including a first display area having first resolution and a second display area having second resolution, the second resolution being lower than the first resolution, and a controller configured to generate border information of pixels provided in a border area located within a predetermined range from the border between the first display area and the second display area, to correct an image that is displayed in the border area based on the border information, and to perform control such that the corrected image is displayed on the display panel.

Trip mechanism for circuit breaker

Disclosed is a trip mechanism for a circuit breaker, capable of maintaining a constant characteristic of a normal trip operation in spite of changes in installation angles of the circuit breaker including a horizontal installation, a perpendicular installation and an inclination installation, the trip mechanism including, a coil configured to generate a magnetic absorption force due to a fault current on a circuit, a stationary core fixed to a lower portion of the coil within the coil, a movable core movable down to the stationary core within the coil by the magnetic absorption force generated from the coil, and a trip lever rotatably to connected to the movable core so as to be pulled by the movable core when the movable core is downwardly moved and configured to trigger the switching mechanism such that the movable contactor is moved to an open circuit position.

Process for making a pattern by silylation

Duty cycle correction circuit and semiconductor integrated circuit apparatus including the same

A duty cycle correction circuit includes a phase splitter configured to control a phase of a DLL clock signal to generate a rising clock signal and a falling clock signal, a clock delay unit configured to delay the rising clock signal and the falling clock signal in response to control signals to generate a delayed rising clock signal and a delayed falling clock signal, a duty ratio correction unit configured to generate a correction rising clock signal and a correction falling clock signal that toggle in response to an edge timing of the delayed rising clock signal and the delayed falling clock signal, and a delay control unit configured to detect duty cycles of the correction rising clock signal and the correction falling clock signal to generate the control signals.

Mask for use in measuring flare, method of manufacturing the mask, method of identifying flare-affected region on wafer, and method of designing new mask to correct for flare

A mask for use in measuring flare produced by a projection lens of a photolithography system, a method of manufacturing the mask, a method of identifying a flare-affected region on a wafer, and a method for correcting for the flare to produce photoresist patterns of desired line widths are provided. A first photolithographic process is performed to form photoresist patterns on a test wafer using a mask including a light shielding region having a plurality of light transmission patterns and a light transmission region, and the photoresist patterns formed by light passing through the light transmission patterns of the light shielding region are compared to the photoresist patterns formed by light passing through the light transmission region. The amount of flare produced by the projection lens is quantified using the results of the comparison, and thus it is possible to identify a flare-affected region on the wafer. In addition, it is possible to form uniform photoresist patterns on the wafer by determining the open ratio of the flare-affected region and calculating an effective amount of the flare in the flare-affected region from the amount of flare of the lens and the open ratio. More specifically, a mask is produced in which the line widths of mask patterns are configured, i.e., corrected compared to the first mask, taking into consideration the effective amount of the flare.

Voltage Level Comparison Circuit of Semiconductor Memory Apparatus, Voltage Adjustment Circuit Using Voltage Level Comparison Circuit, and Semiconductor Memory Apparatus Using the Same

A voltage adjustment circuit of a semiconductor memory apparatus includes a control voltage generating unit configured to distribute an external voltage for selectively outputting a plurality of distribution voltages as a control voltage in response to a control signal, the plurality of the distribution voltages each have different voltage levels, a comparing unit configured to include a voltage supply unit configured to control an external voltage supplied to a first node and a second node if a level of an output voltage is higher than a level of a reference voltage in response to a level of the control voltage, and a detection signal generating unit configured to drop potential levels of the first and second nodes according to the levels of the output voltage and the reference voltage, and to output the potential level of the second node as a detection signal, and a voltage generating unit configured to drive the external voltage according to a potential level of the detection signal and to output the external voltage as the output voltage.

Polymer having butadiene sulfone repeating unit and resist composition comprising the same

A polymer having a repeating unit comprising a copolymer of butadiene sulfone and maleic anhydride, and a chemically amplified resist composition comprising the polymer. The resist composition includes a photosensitive polymer having a first repeating unit comprising a copolymer of butadiene sulfone and maleic anhydride, the first repeating unit represented by a formula:and a second repeating unit copolymerized with the first repeating unit.

Polymer having butadiene sulfone repeating unit and resist composition comprising the same

A polymer having a repeating unit comprising a copolymer of butadiene sulfone and maleic anhydride, and a chemically amplified resist composition comprising the polymer. The resist composition includes a photosensitive polymer having a first repeating unit comprising a copolymer of butadiene sulfone and maleic anhydride, the first repeating unit represented by a formula: and a second repeating unit copolymerized with the first repeating unit.

Process for making a pattern by silylation

Semiconductor integrated circuit capable of overcoming clock signal jitter

A semiconductor integrated circuit includes a voltage supplying unit that supplies a first regulated voltage and a second regulated voltage by using a first reference voltage and a second reference voltage, respectively, and a clock buffer unit that supplies an output clock clocking within a range of the first regulated voltage and the second regulated voltage.

Photomask

Mask for use in measuring flare, method of manufacturing the mask, method of identifying flare-affected region on wafer, and method of designing new mask to correct for flare

A mask for use in measuring flare produced by a projection lens of a photolithography system, a method of manufacturing the mask, a method of identifying a flare-affected region on a wafer, and a method for correcting for the flare to produce photoresist patterns of desired line widths are provided. A first photolithographic process is performed to form photoresist patterns on a test wafer using a mask including a light shielding region having a plurality of light transmission patterns and a light transmission region, and the photoresist patterns formed by light passing through the light transmission patterns of the light shielding region are compared to the photoresist patterns formed by light passing through the light transmission region. The amount of flare produced by the projection lens is quantified using the results of the comparison, and thus it is possible to identify a flare-affected region on the wafer. In addition, it is possible to form uniform photoresist patterns on the wafer by determining the open ratio of the flare-affected region and calculating an effective amount of the flare in the flare-affected region from the amount of flare of the lens and the open ratio. More specifically, a mask is produced in which the line widths of mask patterns are configured, i.e., corrected compared to the first mask, taking into consideration the effective amount of the flare.

Fine pattern prodn with high resolution using simplified efficient method - by applying first photoresist, silylating and glassifying surface, making mask with second resist layer and etching down to substrate

Prodn. of a fine pattern comprises the stages: (1) coating a process substrate (I) with photoresist (II) to form a first resist layer (III) and silylation of the surface to form a silylated layer (IV); (2) glassifying (V) with O2 to form a glassified layer (V); (3) coating (V) with (II) to form a second resist layer (VI); (4) selective exposure and development of (VI) in a given pattern; and (5) etching (V) and (III), using (VI) as mask. ADVANTAGE - Prod. of a fine pattern is simplified and the productivity is increased, since (V) is used as intermediate layer. The resolution is high. In an example, a Si wafer (1) was coated with chemically amplified resist (2). This was silylated in gas or aq. phase to form a 2000-3000 A thick silylation layer (21) and glassified with O2 (22) in RIE appts., forming a glassified layer (23) of SiOx in the organic material. A second resist layer (4) was applied, exposed with UV light (5) through a photomask (6) and developed. The glassified layer was etched with 100 Ncc O2/min at an energy of 2 kW, then the first resist was etched in 25Ncc CF4/min + 60 Ncc O2/min at 2kW in the same appts.

Semiconductor integrated circuit

A semiconductor integrated circuit can include a first voltage pad, a second voltage pad, and a voltage stabilizing unit that is connected between the first voltage pad and the second voltage pad. The first voltage pad can be connected to a first internal circuit, and the second voltage pad can be connected to a second internal circuit.

Duty cycle correction circuit and semiconductor integrated circuit apparatus including the same

Semiconductor memory device having pads

A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.

Controller configured to generate display area information and display device including the same

Disclosed is a display device including a display panel having a plurality of pixels, the display panel comprising a first display area having first resolution and a second display area having second resolution, the second resolution being lower than the first resolution, and a controller configured to generate display area information of each of the plurality of pixels, to blur an image that is displayed in the second display area based on the display area information, and to perform control such that the blurred image is displayed on the display panel.

Domain crossing circuit of a semiconductor memory apparatus

The domain crossing circuit of a semiconductor memory apparatus for improving a timing margin includes a sampler that provides a sampling internal signal generated by delaying an internal input signal by a predetermined time in response to a clock and an edge information signal that defines an output timing of the sampling internal signal and an output stage that allows the sampling internal signal to be synchronized with the clock in response to the edge information signal to be output as a final output signal.

Domain crossing circuit of a semiconductor memory apparatus

A domain crossing circuit of a semiconductor memory apparatus, the domain crossing circuit comprising first and second count signals generated at substantially a same clock period, and representing predetermined clock differences with reference to an internal clock signal with respect to same bit combination data, and a data processing unit configured to provide output data corresponding to input data based on the second count signal in response to the input data synchronized to an external clock signal.

Semiconductor memory device having high electrical performance and mask and photolithography friendliness

A semiconductor memory device comprises a plurality of rows, each row comprising a plurality of active regions arranged at a pitch wherein the active regions in adjacent rows are shifted with respect to each other by one half of the pitch, wherein a distance between each active region in a row is equal to a distance between active regions in adjacent rows.

Logo detection module, timing controller including the same, and driving method of the same

A logo detection module includes a preprocessing unit extracts partial image data corresponding to a predetermined logo detection window region from image data, and acquire gray values based on RGB pixel values of a plurality of pixels included in the extracted partial image data, a logo template generation unit calculates a cumulative gray average value for each pixel based on the gray values of the plurality of pixels acquired using first partial image data, determine a logo pixel based on the calculated cumulative gray average value for each pixel, and generate a logo map including the logo pixel, and a logo compensation unit matches the plurality of pixels included in second partial image data extracted from second image data input after the logo map is generated and the logo pixels included in the logo map to calculate a matching rate, and determine logo compensation based on the calculated matching rate.

Semiconductor memory device having pads

A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.

Semiconductor memory device having pads

Semiconductor memory device having pads

A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.

具有焊墊的半導體記憶體裝置

Semiconductor memory device having pads

A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.

Controller configured to generate display area information and display device including the same

Disclosed is a display device including a display panel having a plurality of pixels, the display panel comprising a first display area having first resolution and a second display area having second resolution, the second resolution being lower than the first resolution, and a controller configured to generate display area information of each of the plurality of pixels, to blur an image that is displayed in the second display area based on the display area information, and to perform control such that the blurred image is displayed on the display panel.

Controller configured to generate display area information and display device including the same

Disclosed is a display device including a display panel having a plurality of pixels, the display panel comprising a first display area having first resolution and a second display area having second resolution, the second resolution being lower than the first resolution, and a controller configured to generate display area information of each of the plurality of pixels, to blur an image that is displayed in the second display area based on the display area information, and to perform control such that the blurred image is displayed on the display panel.

Semiconductor integrated circuit

Low power variable delay circuit

Method of forming line/space patterns

A method of forming a line/space pattern includes forming a plurality of first pattern structures on a layer of hard mask material disposed on a substrate, forming a plurality of second pattern structures along sidewalls of the first pattern structures, removing the first pattern structures such that the second pattern structures stand alone on the layer of hard mask material, forming a first mask that exposes a location where a space of the line/space pattern to be formed is to have a width greater than the distance between adjacent ones of the second pattern structures, removing those of the second pattern structures which are exposed by the first mask such that others of the second pattern structures remain on the layer of hard mask material, forming a second mask that covers a location where a line of the line/space pattern to be formed is to have a width that is greater than the widths of the second pattern structures, forming a hard mask by etching the hard mask material layer using the second mask and the remaining second pattern structures as an etch mask, and etching the substrate using the hard mask as an etch mask.

Semiconductor memory device having high electrical performance and mask and photolithography friendliness

A semiconductor memory device comprises a plurality of rows, each row comprising a plurality of active regions arranged at a pitch wherein the active regions in adjacent rows are shifted with respect to each other by one half of the pitch, wherein a distance between each active region in a row is equal to a distance between active regions in adjacent rows.

Electronic component package and method of manufacturing the same

An electronic component package includes a frame having a cavity, an electronic component disposed in the cavity of the frame, a first metal layer disposed on an inner wall of the cavity of the frame, an encapsulant encapsulating the electronic component, and a redistribution layer disposed below the frame and the electronic component.

Electrical characteristics of package substrates and semiconductor packages including the same

Package substrates are provided. The package substrate may include a power line and a ground line on a first surface of a substrate body; a plurality of signal lines on the first surface between the power line and the ground line; and a lower ground pattern and a lower power pattern positioned on a second surface of the substrate body opposite to the first surface. The lower ground pattern may be disposed to be opposite to the power line and the lower power pattern may be disposed to be opposite to the ground line. Related semiconductor packages are also provided.

Semiconductor memory device having pads

A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.