Speicherzelle mit Retention unter Verwendung eines resistiven Speichers

Es wird eine Vorrichtung beschrieben, die eine Speicherzelle mit Retention unter Verwendung eines resistiven Speichers aufweist. Die Vorrichtung umfasst Folgendes: ein Speicherelement mit einer ersten invertierenden Vorrichtung, die über Kreuz mit einer zweiten invertierenden Vorrichtung geschaltet ist, eine Wiederherstellungsschaltung, die wenigstens ein resistives Speicherelement aufweist, wobei die Wiederherstellungsschaltung mit einem Ausgang der ersten invertierenden Vorrichtung gekoppelt ist, eine dritte invertierende Vorrichtung, die mit dem Ausgang der ersten invertierenden Vorrichtung gekoppelt ist, eine vierte invertierende Vorrichtung, die mit einem Ausgang der dritten invertierenden Vorrichtung gekoppelt ist, und eine Speicherschaltung, die wenigstens ein resistives Speicherelement aufweist, wobei die Speicherschaltung mit einem Ausgang der dritten invertierenden Vorrichtung gekoppelt ist.

Verfahren zum Herstellen eines Festkörperelektrolytmaterialbereichs

Verfahren zum Herstellen eines Festkörperelektrolytmaterialbereichs (16) für ein Speicherelement (10) einer Festkörperelektrolytspeicherzelle (1), – bei welchem der Festkörperelektrolytmaterialbereich (16) aus oder mit einem Chalcogenidmaterial (16') ausgebildet wird, – bei welchem zunächst mindestens ein erster Materialbereich (16'') aus mindestens einem dem Chalcogenidmaterial (16') zugrunde liegenden ersten Material (16-1) in im Wesentlichen reiner Form ausgebildet wird, und zwar aus der Gruppe von Materialien, die gebildet wird von Ge und Si, – bei welchem dann an der so erhaltenen Struktur ein thermischer Behandlungsschritt unter Anwesenheit mindestens eines zweiten dem Chalcogenidmaterial (16') zugrunde liegenden Materials (16-2) durchgeführt wird, und – bei welchem dadurch das Chalcogenidmaterial (16') des Festkörperelektrolytmaterialbereichs (16) erzeugt wird, und zwar mit oder aus einer Verbindung aus der Gruppe, die gebildet wird von GeSex, GeSx, SiSex und SiSx, – wobei das mindestens ...

Vorrichtung und Verfahren zum Betreiben einer integrierten Schaltung

Das Verfahren zum Betreiben einer integrierten Schaltung einschließlich des Schrittes eines Schreibens zu einer Speicherzelle, die einen ersten und einen zweiten logischen Zustand annehmen kann, und wobei eine Änderung von dem zweiten logischen Zustand zu dem ersten logischen Zustand länger dauert als eine Änderung von dem ersten logischen Zustand zu dem zweiten logischen Zustand, umfasst ein Lesen des logischen Zustands der Speicherzelle, ein Ändern des logischen Zustands zu dem ersten logischen Zustand oder Halten desselben in dem ersten logischen Zustand abhängig von dem gelesenen logischen Zustand der Speicherzelle, und ein Ändern des logischen Zustands zu dem zweiten logischen Zustand oder Halten desselben in dem ersten logischen Zustand abhängig von dem logischen Zustand, der geschrieben werden soll.

Solid electrolyte storage cell comprises cathode, anode and solid electrolytes, where anode has intercalation material and metal species, which are unfixed in intercalation material

The storage cell comprises a cathode (2), an anode and solid electrolytes, where the anode has an intercalation material and metal species, which are unfixed in intercalation material. The metal species are silver atoms and ions. The intercalation material has carbon, silicon, inorganic material, electrically conductive organic polymer, material of artificial graphite, oil coke, coal tar, coke, carbon fibers, acetylene, graphite sphere, high-crystalline oil coke, hard carbon. The solid electrolyte is a chalcogenide material (3) and another metal species. Independent claims are also included for the following: (1) a method for manufacturing solid electrolyte storage cell (2) a solid electrolyte storage cell arrangement.

Verfahren zum Hertstellen einer Speicherzelle, Speicherzelle und Speicherzellen-Anordnung

Aufzeichnungsverfahren zur Vermeidung von unnötigem Anlegen einer Spannung an ein Speicherelement

Mikroelektronische Vorrichtung mit Speicherelementen und Verfahren zu ihrer Herstellung

Data holding test executing system for resistive switching memory device i.e. conductive bridging RAM memory device, has applies bias voltage to conductive bridging RAM memory cell of memory device, before or during data holding test

The system applies a bias voltage to a conductive bridging RAM memory cell (1) of a resistive switching memory device that is to be tested, before or during a data holding test. The memory cell is switchable between a high impedance condition and a low impedance condition i.e. ON condition, where the system applies the bias voltage to the memory cell before and/or during application of test signals to the memory cell. An anode (3) of the memory cell is connected with a plate of the memory device or a selection transistor of the memory cell dependent on bias voltage conditions. An independent claim is also included for a method for executing a data holding test for resistive switching memory devices.

Memristive device based on reversible intercalated ion transfer between two meta-stable phases

Memristive devices based on ion-transfer between two meta-stable phases in an ion intercalated material are provided. In one aspect, a memristive device is provided. The memristive device includes: a first inert metal contact; a layer of a phase separated material disposed on the first inert metal contact, wherein the phase separated material includes interstitial ions; and a second inert metal contact disposed on the layer of the phase separated material. The first phase of the phase separated material can have a different concentration of the interstitial ions from the second phase of the phase separated material such that the first phase of the phase separated material has a different electrical conductivity from the second phase of the phase separated material. A method for operating the present memristive device is also provided.

METHOD AND MEANS FOR PREVENTING DEGRADATION OF THRESHOLD VOLTAGE OF FILAMENT-FORMING MEMORY SEMICONDUCTOR DEVICE

... 1498110 Memory resetting ENERGY CONVERSION DEVICES Inc 15 Aug 1975 [19 Aug 1974] 34122/75 Heading G4C A memory in which data is stored by selectively setting a filament of an amorphorus semiconductor material having a high resistance to a crystalline state in which it has a low resistance is reset by applying thereto a burst of reset pulses spaced apart so that the filament, heated by each pulse, cools only partially between successive pulses. This fully resets the filament and it is stated that the threshold voltage, at which the filament is set, is degraded as a result of successive set-reset cycles or high ambient temperatures less than in the prior art. The reset pulses are each of substantially less duration than a set pulse and may be of lower current than a set pulse. Successive reset pulses in each burst may increase in voltage. A plurality of such memories may be formed into a matrix on a semiconductor chip, individual memories being selected by X and Y select units.

PROGRAMMABLE MICROELECTRONIC STRUCTURE AS WELL AS PROCEDURE FOR YOUR PRODUCTION AND PROGRAMMING

MEMORY DEVICE AND CBRAM MEMORY WITH INCREASED RELIABILITY

ALTERNATING CURRENT MEASUREMENT FOR A RESISTIVEN A MEMORY

Silver-selenide/chalcogenide glass stack for resistance variable memory

ELECTRODE STRUCTURE FOR USE IN AN INTEGRATED CIRCUIT

Programmable microelectronic devices and methods of forming and programming same

Sense amplifier circuitry for resistive type memory

Example embodiments include a resistive type memory current sense amplifier circuit including differential output terminals, first and second input terminals, pre-charge transistors, and current modulating transistors coupled directly to the pre-charge transistors. The pre-charge configuration provides high peak currents to charge the bit line and reference line during a "ready" or "pre-charge" stage of operation of the current sense amplifier circuit. The current modulating transistors are configured to operate in a saturation region mode during at least a "set" or "amplification" stage. The current modulating transistors continuously average a bit line current and a reference line current during the "set" or "amplification" stage, thereby improving noise immunity of the circuit. During a "go" or "latch" stage of operation, a logical value "0" or "1" is latched at the differential output terminals based on positive feedback of a latch circuit.

The resistance change of the resistance change of a device memory and method of forming

AND RESISTIVE RANDOM ACCESS MEMORY DEVICE

ELECTRONIC MEMORY

Cette mémoire comporte une matrice (ML,K) d'unités de mémoire et un contrôleur de mémoire (104) connecté au conducteur commun (CLk) et au conducteur de colonne (BLk), et conçu pour lire sélectivement chaque cellule de mémoire (PMCl,k), en fermant l'interrupteur (Tl,k) associé à la cellule de mémoire (PMCl,k) en cours de lecture, en ouvrant les interrupteurs (Tl,k) associés aux autres cellules de mémoire (PMCl,k) de la colonne (k) de la cellule de mémoire (PMCl,k) en cours de lecture, et en mesurant un courant circulant dans le conducteur commun (CLk) et le conducteur de colonne (BLk) et traversant la cellule de mémoire (PMCl,k) en cours de lecture, La mémoire comporte un système de réglage de résistance (106) conçu pour appliquer un signal de réglage ayant : si l'interrupteur (Tl,k) est en position fermée de lecture, une première valeur, et si l'interrupteur (Tl*,k*) est en position ouverte de lecture, une seconde valeur, différente de la première valeur.

METHOD OF DETERMINING ELECTRICAL PARAMETERS FOR PROGRAMMING AND RESISTIVE RANDOM ACCESS MEMORY

L'invention concerne un procédé de détermination de paramètres électriques servant à programmer une mémoire vive résistive dans un état isolant et dans un état conducteur, par formation ou dissolution d'un filament. Le procédé comprend les étapes suivantes : - fournir un jeu de paramètres comprenant une durée de rétention cible, une valeur maximale de résistance à l'état conducteur et une valeur minimale de résistance à l'état isolant ; - simuler des courbes de rétention de l'état conducteur correspondant à différentes dimensions de filament ; - déterminer la courbe de rétention atteignant la valeur maximale après un temps de rétention égal à la durée de rétention cible ; - déterminer une valeur initiale de résistance à l'état conducteur à partir de ladite courbe de rétention de l'état conducteur ; - déterminer le paramètre de programmation de l'état conducteur à partir de la valeur initiale de résistance à l'état conducteur ; - simuler des courbes de rétention de l'état isolant correspondant ...

ELECTRONIC MODULE LOGIC NON-VOLATILE

L'invention concerne un module logique (M) comportant : - des moyens de mise en œuvre d'une fonction logique (MF), lesdits moyens (MF) comportant au moins une entrée (E1, E2) et au moins une sortie (S), ladite au moins une sortie (S) représentant au moins partiellement le résultat de ladite fonction logique, - au moins un premier élément (1) comportant au moins un état résistif, - au moins un deuxième élément (4) formé par une mémoire résistive bipolaire, - ledit premier élément (1) et ledit deuxième élément (4) ayant une électrode commune (3, 5) reliée à ladite sortie (S).

Resistive memory device and method of fabricating the same

HIGH-RELIABILITY HIGH-SPEED MEMRISTOR

ELECTRONIC DEVICE

An electronic device is provided. The electronic device according to an embodiment of the present invention incudes a first electrode and a second electrode which are separated from each other in a first direction; and a first material layer which is interposed between the first electrode and the second electrode and has a variable resistance property or a threshold switching property. At least one of the first electrode and the second electrode includes sub electrodes and second material layers which are alternately arranged in the first direction. Each of the second material layers has a thickness which shows ohmic behavior in an operation current. So, the electronic device having a semiconductor device with improved operation property and reliability can be provided. COPYRIGHT KIPO 2016 ...

AC SENSING FOR A RESISTIVE MEMORY

Alternating current is used to sense a logic state of a memory cell that has a resistive memory element. The memory element can be in an array and a memory device can include the array and peripheral circuitry for reading or sensing each memory cell in the array. The peripheral circuitry can include a clock/control circuit providing a control signal, which controls when a row of memory cells are sensed, a switching circuit for receiving a cellplate count signal and a bit count signal provided by the clock/control circuit, a cellplate line signal and a bit line signal from the memory cell, the switching circuit producing a first output signal and a second output signal, wherein one of the first output signal and the second output signal is at a supply voltage and the other of the first output signal and the second output signal alternates polarity with each sensing operation and a comparison circuit receiving the first output signal and the second output signal and outputting a signal corresponding ...

METHOD FOR DETERMINING RESISTIVE STATE OF RESISTIVE MEMORY CELL, MEMORY CIRCUIT AND CIRCUIT FOR DETERMINING RESISTIVE STATE OF RESISTIVE MEMORY CELL, WHERE DETERMINED RESISTIVE STATE OF MEMORY CELL INDICATES DATA BIT STORED BY MEMORY CELL

PURPOSE: A method for determining a resistive state of a resistive memory cell, a memory circuit and a circuit for determining the resistive state of the resistive memory cell are provided to determine the resistive state of the memory cell by comparing a reference current with a current depending on the resistive state of the memory cell. CONSTITUTION: A memory circuit includes a resistive memory cell(105) and at least one reference resistive memory cell(110,115). A read circuit(145) has a first input connected to the resistive memory cell and a second input connected to the reference resistive memory cell. The read circuit further includes an output part delivering an output signal according to the relation between a reference current from the reference resistive memory cell and the resistive state of the memory cell. © KIPO 2007 ...

ELECTRONIC DEVICE

An electronic device is provided. The electronic device according to an embodiment of the present invention is an electronic device including a semiconductor memory. The electronic device may include a multilayer structure which includes first to third electrodes, an insulating layer interposed between the first electrode and the second electrode and a variable resistance layer interposed between the second electrode and the third electrode; and a selection device layer which is formed on the sidewall of the multilayer structure. COPYRIGHT KIPO 2016 ...

Multi-function resistance change memory cells and apparatuses including the same

Various embodiments comprise apparatuses having a number of memory cells including drive circuitry to provide signal pulses of a selected time duration and/or amplitude, and an array of resistance change memory cells electrically coupled to the drive circuitry. The resistance change memory cells may be programmed for a range of retention time periods and operating speeds based on the received signal pulse. Additional apparatuses and methods are described.

Reduced diffusion in metal electrode for two-terminal memory

Providing for two-terminal memory that mitigates diffusion of external material therein is described herein. In some embodiments, a two-terminal memory cell can comprise an electrode layer. The electrode layer can be at least in part permeable to ionically or chemically reactive material, such as oxygen or the like. The two-terminal memory can further comprise a diffusion mitigation material disposed between the electrode layer and external material. This diffusion mitigation material can be selected to mitigate or prevent diffusion of the undesired element(s) or compound(s), to mitigate or avoid exposure of such element(s) or compound(s) to the electrode layer. Accordingly, degradation of the two-terminal memory as a result of contact with the undesired element(s) or compound(s) can be mitigated by various disclosed embodiments.

SEMICONDUCTOR DEVICE

Provided is a semiconductor device having a nonvolatile variable resistance element mounted thereon. The semiconductor device is provided with a resistance value conversion circuit section which outputs a resistance value of the nonvolatile variable resistance element by converting the resistance value into a potential or a current; a comparison circuit section which compares the output from the resistance value conversion circuit section with a potential or a current at some nodes within the semiconductor device; and a resistance value varying circuit section for varying the resistance value of the nonvolatile variable resistance element based on the comparison results obtained from the comparison circuit section.

WRITE AND ERASE SCHEME FOR RESISTIVE MEMORY DEVICE

A method for programming a two terminal resistive memory device, the method includes applying a bias voltage to a first electrode of a resistive memory cell of the device; measuring a current flowing through the cell; and stopping the applying of the bias voltage if the measured current is equal to or greater than a predetermined value.

APPARATUS AND METHOD FOR PROGRAMMING AN ARRAY OF NONVOLATILE MEMORY CELLS INCLUDING SWITCHABLE RESISTOR MEMORY ELEMENTS

A non-volatile memory cell includes a switchable resistor memory element in series with a switch device. An array of such cells may be programmed using only positive voltages. A method for programming such cells also supports a direct write of both 0 and 1 data states without requirement of a block erase operation, and is scalable for use with relatively low voltage power supplies. A method for reading such cells reduces read disturb of a selected memory cell by impressing a read bias voltage having a polarity opposite that of a set voltage employed to change the switchable resistor memory element to a low resistance state. Such programming and read methods are well suited for use in a three-dimensional memory array formed on multiple levels above a substrate, particularly those having extremely compact array line drivers on very tight layout pitch.

NONVOLATILE RESISTANCE CHANGE ELEMENT

According to one embodiment, a nonvolatile resistance change element includes a first electrode, a second electrode and a first layer. The first electrode includes a metal element. The second electrode includes an n type semiconductor. The first layer is formed between the first electrode and the second electrode and includes a semiconductor element. The first layer includes a conductor portion made of the metal element. The conductor portion and the second electrode are spaced apart.

MICROELECTRONIC PHOTONIC STRUCTURE AND DEVICE AND METHOD OF FORMING THE SAME

A microelectronic photonic structure and a device and a system including the structure are disclosed. The photonic structure includes an ion conductor and a plurality of electrodes. Optical properties of the structure are altered by applying energy across the electrodes.

Front to back resistive random access memory cells

A resistive random access memory cell formed in an integrated circuit includes a first resistive random access memory device including an anode and a cathode, a second resistive random access memory device including an anode and a cathode, the cathode of the second resistive random access memory device connected to the anode of the first resistive random access memory device, a programming transistor having a first source/drain terminal connected to a programming potential node, a second source/drain terminal connected to the anode of the first resistive random access memory device and the cathode of the second resistive random access memory device, and a gate connected to a program-enable nod, and at least one switch transistor having a gate connected to the anode of the first resistive random access memory device and the cathode of the second resistive random access memory device.

RESISTIVE RANDOM ACCESS MEMORY, NONVOLATILE MEMORY, AND METHOD OF MANUFACTURING RESISTIVE RANDOM ACCESS MEMORY

A resistive random access memory includes a lower electrode; a metal oxide film formed on the lower electrode and having a variable resistance, the metal oxide film having a first portion containing a metal element forming the metal oxide film and a second portion richer in oxygen than the first portion; and an upper electrode formed on the metal oxide film.

Memory circuit having memory cells which have a resistance memory element

In a memory circuit having memory cells which are connected in series between a ground line PL and a bit line BL and in each case have a resistance memory element said element having a bipolar switching behavior having an anode electrode and a cathode electrode, and a drive transistor connected in parallel with the resistance memory element, the drive transistors of the memory cells in each case are connected to a word line in order to switch the drive transistor on and off in such a way that a current path is formed via the associated drive transistor in a non-activated state of a memory cell and a current path is formed via the associated resistance memory element in an activated state of a memory cell, a first changeover switch being arranged at one end and a second changeover switch at other ends of the series of memory cells in order alternately to produce a connection between the series-connected memory cells and the ground line and the bit line in a manner dependent on an applied ...

Electronic memory device

An electronic device includes a first electrode, a second electrode, and a solid electrolyte made of an ion-conducting material, the first and second electrodes being configured to form a metal dendrite. The device further includes a third electrode, an interface layer contacting the third electrode and a third surface of the electrolyte, the interface layer being an ionic insulator and an electronic insulator. The third electrode and the dendrite are arranged such that the device has two resistive states.

Arrangement and method for reading from resistance memory cells

A method and apparatus for reading from a memory arrangement, in particular, for reading from a CBRAM or another memory arrangement based on resistively switching memory cells includes charging a bit line to a voltage value, discharging the bit line by a cell resistance, and subsequently assessing a resulting voltage difference in a measuring device, in particular, a differential sense amplifier.

Method for operating a PMC memory cell and CBRAM memory circuit

The present invention relates to a method for operating a PMC memory cell for use in a CBRAM memory array, wherein the PMC memory cell includes a solid electrolyte which is adapted to selectively develop and diminish a conductive path depending on an applied electrical field. The PMC memory cell is programmed to change to a programmed state by applying a programming voltage, and the PMC memory cell is erased to change to an erased state by applying an erase voltage. A refresh voltage is applied to the PMC memory cell at a predetermined time to stabilize the programmed state of the PMC memory cell, wherein the refresh voltage is selected such as that, while applying the refresh voltage, a programming of the PMC memory cell in the erased state to a programmed state is prevented, and that, by applying the refresh voltage, a stabilizing of the programmed state of the PMC memory cell is performed.

CBRAM memory device and method for writing to a resistive memory cell in a CBRAM memory device

A memory device and method of operating the same. In one embodiment, the memory device includes a resistive memory cell including a resistive memory element wherein the resistive memory element is designed to acquire a low resistance state when applying a programming voltage and acquire to a high resistance state when applying an erasing voltage; and wherein the writing time for changing the resistance state of the resistive memory element can be relatively reduced.

Nonvolatile memory device and method for manufacturing same

According to one embodiment, a nonvolatile memory device includes a first wiring layer. The device includes a second wiring layer intersecting with the first wiring layer. And the device includes a first memory layer provided at a position where the first wiring layer and the second wiring layer intersect. And the first memory layer contacts with the first wiring layer, and the first wiring layer is a layer which is capable of supplying a metal ion to the first memory layer.

Level Shifters, Memory Systems, and Level Shifting Methods

Level shifters, memory systems, and level shifting methods are described. According to one arrangement, a level shifter includes an input configured to receive an input signal in a first voltage domain, an output configured to output an output signal from the level shifter in a second voltage domain different than the first voltage domain, a plurality of pull-down devices, and wherein one of the pull-down devices is coupled with the input and the output, a plurality of cross-coupled devices coupled with the pull-down devices and configured to provide transitions in the output signal as a result of transitions in the input signal, a plurality of current limiting devices coupled with the cross-coupled devices and configured to limit a flow of current from a source to the cross-coupled devices, and a plurality of dynamic devices configured to selectively provide charging current from the source to the cross-coupled devices.

Semiconductor memory device

A semiconductor memory device comprises a semiconductor substrate; a memory block formed on the semiconductor substrate and including plural stacked cell array layers of cell arrays each comprising a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of contacts extending in the stack direction of the cell array layers and connecting the first lines in the cell arrays with diffusion regions formed on the semiconductor substrate. A certain one of the cell array layers is smaller in the number of the first lines divided and the number of contacts connected than the cell array layers in a lower layer located closer to the semiconductor substrate than the certain one.

RESISTIVE MEMORY DEVICE AND METHOD OF OPERATING THE SAME

A resistive memory device includes a memory cell array that has a plurality of resistive memory cells that are arranged respectively on regions where a plurality of first signal lines and a plurality of second signal lines cross each other. A write circuit is connected to a selected first signal line that is connected to a selected memory cell from among the plurality of memory cells, and provides pulses to the selected memory cell. A voltage detector detects a node voltage at a connection node between the selected first signal line and the write circuit. A voltage generation circuit generates a first inhibit voltage and a second inhibit voltage that are applied respectively to unselected first and second signal lines connected to unselected memory cells from among the plurality of memory cells, and changes a voltage level of the second inhibit voltage based on the node voltage that is detected.

Nonvolatile memory devices that use resistance materials and internal electrodes, and related methods and processing systems

A nonvolatile memory device, a method of fabricating the nonvolatile memory device and a processing system including the nonvolatile memory device. The nonvolatile memory device may include a plurality of internal electrodes that extend in a direction substantially perpendicular to a face of a substrate, a plurality of first external electrodes that extend substantially in parallel with the face of the substrate, and a plurality of second external electrodes that also extend substantially in parallel with the face of the substrate. Each first external electrode is on a first side of a respective one of the internal electrodes, and each second external electrode is on a second side of a respective one of the internal electrodes. These devices also include a plurality of variable resistors that contact the internal electrodes, the first external electrodes and the second external electrodes.

Integrated Circuit and Method of Improved Determining a Memory State of a Memory Cell

According to one embodiment, a method of determining a memory state of a resistivity changing memory cell is provided. A first electrode of the resistivity changing memory cell is set to a first potential. The method further includes setting the second electrode to a second potential being different from the first potential, thereby generating a memory state sensing current flowing through the resistivity changing memory cell; controlling the strength of the second potential in dependence on the strength of the memory state sensing current such that the strength of the memory state sensing current is kept constant.

RRAM memory cell with multiple filaments

In some embodiments, the present disclosure relates to a memory circuit having a first resistive random access memory (RRAM) element and a second RRAM element arranged within a dielectric structure over a substrate. The first RRAM element has a first conjunct electrode separated from a first disjunct electrode by a first data storage layer. The second RRAM element has a second conjunct electrode separated from a second disjunct electrode by a second data storage layer. A control device is disposed within the substrate and has first terminal coupled to the first conjunct electrode and the second conjunct electrode and a second terminal coupled to a word-line.

Multilevel resistive information storage and retrieval

The present invention relates to resistive random-access memory (RRAM or ReRAM) systems, as well as methods of employing multiple state variables to form degenerate states in such memory systems. The methods herein allow for precise write and read steps to form multiple state variables, and these steps can be performed electrically. Such an approach allows for multilevel, high density memory systems with enhanced information storage capacity and simplified information retrieval.

Application of relaxation voltage pulses to programmble impedance elements during read operations

An integrated circuit (IC) device can include a plurality of memory cells with programmable impedance elements. A circuit can be configured to read a data value stored by an element of a memory cell by application of at least one read voltage pulse and at least one relaxation voltage pulse across the terminals of the element; wherein the read voltage pulse has a same polarity as a voltage used to program the element, the relaxation voltage pulse has a different polarity than the read voltage pulse, and neither the read or relaxation voltage pulses program the element to a particular impedance state.

Sensing of resistance variable memory devices

A resistance variable memory device such as e.g., a PCRAM memory device, with either a 4T (transistor) or 2T memory cell configuration and either a dual cell plate or word line configuration. The device includes additional circuitry configured to write or erase addressed cells while keeping the voltage across non-addressed cells at approximately 0V. The device also includes circuitry that reads the addressed cells in a manner that increases the sensing window without causing the potential across the cell to be greater than approximately 200 mV. The device may also sense the state of its addressed cells closer in time to when the cells are accessed, in comparison to typical sensing techniques.

1S-1C DRAM WITH A NON-VOLATILE CBRAM ELEMENT

One embodiment of a memory device comprises a selector and a storage capacitor in series with the selector. A further embodiment comprises a conductive bridging RAM (CBRAM) in parallel with a storage capacitor coupled between the selector and zero volts. A plurality of memory devices form a 1S-1C or a 1S-1C-CBRAM cross-point DRAM array with 4F2 or less density.

PCRAM cell manufacturing

An exemplary embodiment of the present invention includes a method for forming a programmable cell by forming an opening in a dielectric material to expose a portion of an underlying first conductive electrode, forming a recessed chalcogenide-metal ion material in the opening and forming a second conductive electrode overlying the dielectric material and the chalcogenide-metal ion material. A method for forming a recessed chalcogenide-metal ion material comprises forming a glass material to be recessed approximately 50% or less, in the opening in the dielectric material, forming a metal material on the glass material within the opening and diffusing metal ions from the metal material into the glass material by using ultraviolet light or ultraviolet light in combination with a heat treatment, to cause a resultant metal ion concentration in the glass material.

Electronic device

An electronic device includes a semiconductor unit. The semiconductor unit includes a first electrode and a second electrode spaced apart from each other in a first direction; and a first material layer interposed between the first electrode and the second electrode and having a variable resistance characteristic or a threshold switching characteristic, wherein the first electrode, or the second electrode, or both includes a plurality of sub-electrodes and a plurality of second material layers that are alternately arranged in the first direction, and wherein each of the second material layers has a thickness that is sufficiently small to enable the second material layers to exhibit an ohmic-like behavior for a current flowing therein at an operating current of the semiconductor unit.

Access signal adjustment circuits and methods for memory cells in a cross-point array

Systems, integrated circuits, and methods to utilize access signals to facilitate memory operations in scaled arrays of memory elements are described. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements and line driver. The line driver can be configured to access a resistive memory element in the cross-point array.

METHOD FOR DETERMINING TARGET RESISTANCE LEVELS FOR A RESISTIVE MEMORY CELL, AND ASSOCIATED MEMORY DEVICE

An aspect of the invention relates to a method for determining target resistance levels for a resistive memory cell. During the method at least one second target resistance level (R3) based on a first target resistance level (R4), and on a first resistance dispersion value (σΔ,R4) representative of the dispersion of a first set of final resistance values obtained, after relaxing of the memory cell, for initial values of the resistance of the memory cell distributed over a first given initialisation interval (I4) having a predetermined width (Δ4), are determined. Another aspect of the invention relates to a memory device comprising memory cells and an electronic control device configured to control the memory cells at target resistance levels determined in accordance with said method.

STORAGE ELEMENT AND MEMORY DEVICE

PROBLEM TO BE SOLVED: To provide a storage element exhibiting superior low current operation and having excellent retention properties, and to provide a memory device. SOLUTION: In the storage element 1 laminating a lower electrode 10, a memory layer 20 and an upper electrode 30 in this order, the memory layer 20 has a resistance change layer 22 including a layer containing the most tellurium (Te), and an ion source layer 21 containing aluminum (Al) within the range of 27.7-47.4 atom%. Consequently, metal elements precipitated into the resistance change layer 22 during erasure dissolve easily into the ion source layer 21, and the resistive state after writing and erasure is maintained. COPYRIGHT: (C)2012,JPO&INPIT ...

Circuit arrangement for information storage in cells of the CBRAM-type, has write transistor and constant current source arranged in symmetrical current circuit

A circuit arrangement for storage of information in a storage cell of the CBRAM-type, in which the storage cell (CBJ) can be connected to a constant current source (IWR). The connection of the storage cell (CBJ) to the constant current source (IWR) is carried out via a write transistor (TRWR) and the write transistor and constant current source are arranged in a symmetrical current circuit.

Non-volatile (sic) resistive storage cell with solid electrolyte matrix between first and second electrode as active layer useful in semiconductor technology has elements from groups IVb and Vb and transition metals in active layer

Non-volatile (sic) resistive storage cell with solid electrolyte matrix (300) between first (100) and second (200) electrode as active layer. Active layer includes first, second and third layers, where first and third layers (300a and 300c) have composition MmX(1-m) and Mm'X(1-m') respectively, where M = element selected from groups IVb and Vb and transition metals, X and Y = O, S, Se or Te and m and m' =0-1. INDEPENDENT CLAIM is included for preparation of storage cell involving deposition of a dielectric layer on first electrode. Second layer (300b) is formed from Z-chalcogenide compound, where one of electrodes can be Z-chalcogenide compound, where Z = Ag, Cu, Sn, Na, Li, or K.

Non-volatile memory cell e.g. flash memory cell, for semiconductor device, has transistors reducing leakage currents that flow through non-volatile programmable resistors, respectively

The memory cell (500) has two transistors (501, 502) whose source and drain connections are, respectively, coupled with nodes (503, 504). Transistors (509, 510) reduce leakage currents, which flow through non-volatile programmable resistors (507, 508), respectively. Source or drain connections of the resistors are coupled with connectors of the resistors or with connectors of the transistor (501, 502), respectively. An independent claim is also included for a semiconductor device with a non-volatile memory cell.

Festkörperelektrolyt-Speicherzelle sowie Festkörperelektrolyt-Speicherzellenarray

Festkorperelektrolyt-Speicherzelle mit wahlfreiem Zugriff, mit einem Festkörperelektrolytblock, der wenigstens drei Festkörperelektrolyt-Kontaktierbereiche aufweist, mit Elektroden, die mit dem Festkorperelektrolyt-Kontaktierbereichen elektrisch verbunden sind, wobei in dem Festkörperelektrolytblock leitende Pfade ausbildbar, löschbar oder detektierbar sind durch Anlegen von Spannungen zwischen den Festkorperelektrolyt-Kontaktierbereichen, wobei die Kontaktierbereiche räumlich voneinander getrennt sind, derart, dass leitende Pfade, die von unterschiedlichen Festkorperelektrolyt-Kontaktierbereichen ausgehen und/oder in unterschiedlichen Festkörperelektrolyt-Kontaktierbereichen enden, nicht miteinander uberlappen, wobei wenigstens zwei Festkörperelektrolyt-Kontaktierbereiche auf einer ersten Oberfläche angeordnet sind, und eine leitfähige Widerstandsschicht zwischen den wenigstens zwei Festkörperelektrolyt-Kontaktierbereichen auf der ersten Oberfläche angeordnet und mit den wenigstens zwei ...

Storage circuit has multiple parallel bit lines, which are connected to storage cells, and multiple switches which are connected with corresponding pair of bit lines of multiple bit lines

The storage circuit (10) has multiple parallel bit lines (21,22,23,24,25,26,27,28) connected to a storage cell (12). The storage circuit has multiple switches (51,52,53,54) which are connected with a corresponding pair of bit lines of the multiple bit lines in order to short circuit the corresponding pair. The bit lines of the corresponding pair are connected with two different read amplifiers (41,42,43,44). The bit lines of the corresponding pair next adjacent to a further bit lines are between the bit lines of the corresponding pair. Independent claims are also included for the following: (1) a microelectronic element, which has a storage circuit (2) a method for operating storage circuit, which involves connecting storage cell, bit lines.

Programmieren programmierbarer resistiver Speichervorrichtungen

Vorrichtung zum Programmieren ausgewählter Speichervorrichtungen in einem resistiven Kreuzpunktarray (412) von programmierbaren resistiven Speichervorrichtungen, wobei die Schaltung folgende Merkmale umfasst: einen Vorverstärker (610) zum Anlegen eines Programmierungspotentials an eine ausgewählte der Speichervorrichtungen, während ein Arraypotential an andere der Speichervorrichtungen angelegt wird, wobei das Array- und das Programmierungspotential etwa gleich sind, wobei eine Äquipotentialisolation der ausgewählten Speichervorrichtung erreicht wird, und eine Schaltung zum Ausschalten des Programmierungspotentials, wenn ein Erfassungsstrom, der durch die ausgewählte Speichervorrichtung fließt, anzeigt, dass die ausgewählte Speichervorrichtung programmiert wurde, wobei der Vorverstärker eine Versatzeinstellung aufweist, und die Schaltung vor dem Programmieren den Versatz des Vorverstärkers einstellt, bis das Array- und das Programmierungspotential etwa gleich sind.

A light-activated switching resistor, an optical sensor incorporating a light-activated switching resistor, and methods of using such devices

Generating a reference current for sensing

Apparatus and method of generating a reference current to sense the state (high/low resistance) of Correlated Electron Switching CES memory cells in a memory array, and comprising current reference generating tracking circuit(s). The tracking circuit (16 fig 1) comprises a tracking bit cell 60 comprising low resistance (as manufactured) first 62 and second 64 CES elements in series with reference and ground column lines respectively, whilst third and fourth CES elements (66, 68 programmed high resistance) are arranged in parallel between column and ground reference lines. The tracking circuit may cascade many tracking bit cells (ie. 16 or 32) in a resistive ladder arrangement (figure 5b). Hence application of a voltage across the tracking circuit provides an optimum reference current proportional to the geometric mean of the high and low resistance (impedance) of the ladders CES elements. The reference current is mirrored to a plurality of sense amplifiers coupled to each of the CES memory ...

A light-activated switching resistor, an optical sensor incorporating a light-activated switching resistor, and methods of using such devices

Stabilization of resistive memory

NON VOLATILE MEMORY CELL WITH AN ADJUSTABLE RESISTANCE AND TRANSISTOR

IMPROVED PROCEDURE FOR THE PRODUCTION OF MEMORY CELLS OF THE TYPE PMC

MEMORY WITH OPTIONAL ACCESS WITH PROGRAMMABLE LEADER AND PERTINENT PROGRAMMING PROCEDURE

MEMORY MODULE WITH SWITCHING GLASS LAYER

PROGRAMMABLE METALLIZATION STRUCTURE WITH SOLIDIFICATION NEAR THE SURFACE AND MANUFACTURING PROCESS FOR IT

A PROGRAMMABLE CONDUCTOR RANDOM ACCESS MEMORY AND A METHOD FOR WRITING THERETO

Microelectronic photonic structure and device and method of forming the same

PROGRAMMABLE MICROELECTRONIC DEVICES AND METHODS OF FORMING AND PROGRAMMING SAME

A microelectronic programmable structure (300) and methods of forming and programming the structure (300) are disclosed. The programmable structure (300) generally includes an ion conductor (340) and a plurality of electrodes (320, 330). Electrical properties of the structure (300) may be altered by applying a bias across the electrodes (320, 330), and thus information may be stored using the structure (300).

PROGRAMMABLE SUB-SURFACE AGGREGATING METALLIZATION STRUCTURE AND METHOD OF MAKING SAME

A programmable sub-surface aggregating metallization structure (100) includes an ion conductor (110) such as a chalcogenide glass which includes metal ions and at least two electrodes (120, 130) disposed at opposing surfaces of the ion conductor (110). Preferably, the ion conductor (110) includes a chalcogenide material with Group IB or Group IIB metals. One of the two electrodes (120, 130) is preferably configured as a cathode and the other as an anode. When a voltage is applied to between the anode and cathode, a metal dendrite (140) grows from the cathode through the ion conductor (11) toward the anode. The grow rate of the dendrite may be stopped by removing the voltage or the dendrite may be retracted back toward the cathode by reversing the voltage polarity at the anode and the cathode. When a voltage is applied for a sufficient length of time, a continuous metal dendrite grows through the ion conductor (110) and connects the electrodes (120, 130), thereby shorting the device. The ...

Solid electrolyte switching device, FPGA using same, memory device, and method for manufacturing solid electrolyte switching device

FILAMENT-TYPE SEMICONDUCTOR SWITCH DEVICE AND METHOD OF MAKING THE SAME

RESISTIVE MEMORY, PROGRAMMING AND METHODS OF MANUFACTURE THEREOF

METHOD FOR MANAGING THE ENDURANCE OF A NON-VOLATILE REWRITABLE MEMORY AND DEVICE FOR PROGRAMMING SUCH A MEMORY

METHOD FOR DETERMINING PARAMETERS OF PROGRAMMING FOR PROGRAMMING AND RESISTIVE RANDOM ACCESS MEMORY

RESISTIVE RANDOM ACCESS MEMORY DEVICE

Un aspect de l'invention concerne un dispositif de mémoire vive résistive comportant : - une première électrode ; - un électrolyte solide en oxyde métallique ; - une deuxième électrode, les première et deuxième électrodes étant respectivement agencées de part et d'autre dudit électrolyte solide en oxyde métallique, la deuxième électrode étant apte à fournir des ions mobiles circulant dans l'électrolyte solide en oxyde métallique vers la première électrode pour former un filament conducteur entre les première et deuxième électrodes lorsqu'une différence de potentiel est appliquée entre les première et deuxième électrodes ; ledit dispositif comportant une couche d'interface comprenant un oxyde métallique, la couche d'interface s'étendant au moins partiellement sur la première électrode, l'électrolyte solide en oxyde métallique s'étendant au moins partiellement sur la couche d'interface.

METHOD FOR PLAYING AN ELECTRONIC MEMORY DEVICE

Un aspect de l'invention concerne un procédé (100) de lecture d'un dispositif mémoire électronique comportant une pluralité N de cellules mémoires de type mémoire vive résistive Ci avec i variant de 1 à N et N ≥ 2, chaque cellule mémoire Ci ayant une résistance Ri, le procédé comportant les étapes suivantes : - une étape (110) d'association d'une valeur de résistance à chaque résistance Ri pour l'obtention d'une combinaison particulière de N valeurs de résistance ; - une étape (120) d'application d'une fonction mathématique à la combinaison particulière de N valeurs de résistance pour l'obtention d'une valeur de résistance résultante ; - une étape (130) de détermination de l'état logique du dispositif mémoire électronique.

METHOD OF USING ELECTROCHEMICAL COMPONENTS FOR STORING ENERGY AND DATA AND ELECTRONIC CIRCUIT CONFIGURATION

METHOD FOR DETERMINING A MEMORY WINDOW AND RESISTIVE RANDOM ACCESS MEMORY

Procédé (1) de détermination d'une fenêtre mémoire d'au moins une cellule mémoire vive résistive, la cellule mémoire vive résistive comportant un état hautement résistif et un état faiblement résistif, le passage de la mémoire vive résistive d'un état initial parmi l'état hautement résistif ou l'état faiblement résistif à un autre état puis le retour à l'état initial formant un cycle, ledit procédé comprenant les étapes suivantes : ○ mesurer les valeurs des résistances des états hautement résistif et faiblement résistif à un cycle j donné, j étant un nombre entier ; ○ déterminer la fenêtre mémoire à utiliser pendant les n cycles suivant le cycle donné j, n étant un nombre entier, la fenêtre mémoire étant calculée en prenant en compte au moins les résistances des états hautement et faiblement résistif au cycle j.

STORAGE ELEMENT AND OPERATING METHOD OF STORAGE ELEMENT

MEMORY DEVICE

유전체 메모리 소자를 가진 메모리 셀

... 일부 실시예들은 제 1 전극, 제 2 전극, 및 제 1 전극과 제 2 전극 사이에 위치된 유전체를 가진 메모리 셀을 구비한 장치 및 방법들을 포함한다. 유전체는 메모리 셀에 저장된 정보의 제 1 값을 나타내게 메모리 셀이 제 1 전극의 물질의 일부로부터 유전체 내에 도전성 경로를 형성할 수 있게 구성될 수 있다. 또한, 유전체는 메모리 셀에 저장된 정보의 제 2 값을 나타내게 메모리 셀이 도전성 경로를 단절시킬 수 있게 구성될 수 있다.

RESISTIVE MEMORY AND METHOD

SELECT DEVICE FOR CROSS POINT MEMORY STRUCTURES

COMPLEMENTARY BIT PCRAM (PROGRAMMABLE CONDUCTOR RAM) AND METHOD OF OPERATION

A method and apparatus is disclosed for sensing the resistance state of a Programmable Conductor Random Access Memory (PCRAM) element using complementary PCRAM elements, one holding the resistance state being sensed and the other holding a complementary resistance state. A sense amplifier detects voltages discharging through the high and low resistance elements to determine the resistance state of an element being read. © KIPO & WIPO 2007 ...

Memory cell retention enhancement through erase state modification

Cross point memory array devices

Semiconductor memory device

NON-VOLATILE MEMORY ARRAY WITH RESISTIVE SENSE ELEMENT BLOCK ERASE AND UNI-DIRECTIONAL WRITE

A non-volatile memory cell (130) and associated method of use are disclosed. In accordance with various embodiments, the memory cell includes a switching device (132) and a resistive sense element (RSE) (110) connected in series between first (138) and second (141A) control lines. The first control line is supplied with a variable voltage and the second control line is maintained at a fixed reference voltage. A first resistive state of the RSE is programmed by lowering the variable voltage of the first control line below the fixed reference voltage of the second control line to flow a body-drain current through the switching device. A different, second resistive state of the RSE is programmed by raising the variable voltage of the first control line above the fixed reference voltage to flow a drain-source current through the switching device.

PROGRAMMING A MEMORY CELL WITH A DIODE IN SERIES BY APPLYING REVERSE BIAS

A method of programming a memory cell comprises applying a reverse bias to the memory cell using a temporary resistor in series with the memory cell. The memory cell comprises a diode and a resistivity switching material element in series. The state of the resistivity switching material element changes from a first initial state to a second state different from the first state.

Memory devices using a plurality of diodes as program selectors for memory cells

At least one junction diode fabricated in standard CMOS logic processes can be used as program selectors for the memory cells that can be programmed based on the directions of current flow. These memory cells are MRAM, RRAM, CBRAM, or other memory cells that have a resistive element coupled to the P terminal of the first diode and to the N terminal of a second diode. The diodes can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diodes. By applying a high voltage to a resistive element and switching the N terminal of the first diode to a low voltage while disabling the second diode, a current flows through the memory cell can change the resistance into one state. Similarly, by applying a low voltage to a resistive element and switching the P terminal of the second diode to a high voltage while disabling the first diode, a current flows through the memory cell can change the resistance into another state. The P+ active region of the diode can be isolated from the N+ active region in an N well by using dummy MOS gate, SBL, or STI isolations.

One-time programmable memories using polysilicon diodes as program selectors

Polysilicon diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, using electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse etc. as OTP element The diode can be constructed by P+/N+ implants on a polysilicon as a program selector. The OTP device has an OTP element coupled to a polysilicon diode. The OTP devices can be used to construct a two-dimensional OTP memory with the N-terminals of the diodes in a row connected as a wordline and the OTP elements in a column connected as a bitline. By applying a high voltage between a selected bitline and a selected wordline to turn on a diode in a selected cell for suitable duration of time, a current flows through an OTP element may change the resistance state. The cell data in the OTP memory can also be read by turning on a selected wordline and to couple a selected bitline to a sense amplifier. The wordlines may have high-resistivity local wordlines coupled to low-resistivity global wordlines through conductive contact(s) or via(s).

Reversible resistive memory using diodes formed in cmos processes as program selectors

Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for reversible resistive memory cells that can be programmed based on magnitude, duration, voltage-limit, or current-limit of a supply voltage or current. These cells are PCM, RRAM, CBRAM, or other memory cells that have a reversible resistive element coupled to a diode. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. The memory cells can be used to construct a two-dimensional memory array with the N terminals of the diodes in a row connected as a wordline and the reversible resistive elements in a column connected as a bitline. By applying a voltage or a current to a selected bitline and to a selected wordline to turn on the diode, a selected cell can be programmed into different states reversibly based on magnitude, duration, voltage-limit, or current-limit. The data in the reversible resistive memory can also be read by turning on a selected wordline to couple a selected bitline to a sense amplifier. The wordlines may have high-resistivity local wordlines coupled to low-resistive global wordlines through conductive contact(s) or via(s).

Programmably reversible resistive device cells using cmos logic processes

Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for reversible resistive devices, such as PCM, RRAM, CBRAM, or other memory cells. The reversible resistive devices have a reversible resistive element coupled to a diode. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. By applying a voltage or a current between a reversible resistive element and the N terminal of a diode, the reversible resistive device can be programmed into different states based on magnitude, duration, voltage-limit, or current-limit in a reversible manner. The P+ active region of the diode can be isolated from the N+ active region in the N well by using dummy MOS gate, SBL, or STI/LOCOS isolations.

Resistor structure for a non-volatile memory device and method

A non-volatile resistive switching memory device. The device includes a first electrode, a second electrode, a switching material in direct contact with a metal region of the second electrode, and a resistive material disposed between the second electrode and the switching material. The resistive material has an ohmic characteristic and a resistance substantially the same as an on state resistance of the switching device. The resistive material allows for a change in a resistance of the switching material upon application of voltage pulse without time delay and free of a reverse bias after the voltage pulse. The first voltage pulse causes a programming current to flow from the second electrode to the first electrode. The resistive material further causes the programming current to be no greater than a predetermined value.

Programmable metallization memory cell with planarized silver electrode

Programmable metallization memory cells having a planarized silver electrode and methods of forming the same are disclosed. The programmable metallization memory cells include a first metal contact and a second metal contact, an ion conductor solid electrolyte material is between the first metal contact and the second metal contact, and either a silver alloy doping electrode separates the ion conductor solid electrolyte material from the first metal contact or the second metal contact, or a silver doping electrode separates the ion conductor solid electrolyte material from the first metal contact. The silver electrode includes a silver layer and a metal seed layer separating the silver layer from the first metal contact.

Memory unit and method of operating the same

A memory unit includes memory cells each having a memory element and a transistor, word lines and first and second bit lines, and a drive section. In performing setting operation for a first memory element located on one word line and in performing resetting operation for a second memory element located on the one word line, the drive section applies a given word line electric potential to the one word line, and sets an electric potential of a bit line on a lower electric potential side out of the first and the second bit lines corresponding to the first memory element to a value higher than a value of an electric potential of a bit line on the lower electric potential side corresponding to the second memory element by an amount of given electric potential difference.

Memory apparatus

A memory apparatus includes: a plurality of memory cells which includes a first resistance change element; and a read-out circuit which determines the size of a resistance value of the first resistance change element by comparing the resistance state of a memory cell selected among the plurality of memory cells to the resistance state of a reference memory cell, wherein the reference memory cell includes a second resistance change element, a resistance value of the second resistance change element with respect to an applied voltage is smaller than that in a high resistance state of the first resistance change element, and the second resistance change element shows the same resistance change characteristic as the first resistance change element.

Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance

The invention relates to a method and apparatus providing a memory cell array in which each resistance memory cell is connected in series to a capacitive element. Access transistors are not necessary to perform read and write operations on the memory cell. In one exemplary embodiment, the capacitive element is a capacitor.

Semiconductor memory device and controlling method thereof

According to one embodiment, a semiconductor memory device includes a memory cell array in which memory cells each including at least a rectification element and a variable resistance element, which are connected in series, a peripheral circuit, a sense amplifier configured to sense the memory cells via the peripheral circuit, and a control circuit configured to control operations of the memory cell array and the sense amplifier. The control circuit is configured to boost a potential of a selected bit line, which is one of a first even bit line and a first odd bit line of a first side, by charge sharing of a second even bit line and a second odd bit line which are nonselected bit lines and physically neighbor the first even bit line or the first odd bit line of the first side, which is connected to a selected one of the memory cells.

Memory element and memory device

There are provided a memory element and a memory device excellently operating at a low current, and having the satisfactory retention characteristics. The memory element includes a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer disposed on the first electrode side, and being in a single- or multi-layer structure including a layer containing a highest percentage of tellurium (Te) as an anionic component, and an ion source layer disposed on the second electrode side, and containing a metallic element and one or more chalcogen elements including tellurium (Te), sulfur (S), and selenium (Se) with aluminum (Al) of 27.7 atomic % or more but 47.4 atomic % or less.

Memory cell operation

Methods, devices, and systems associated with memory cell operation are described. One or more methods of operating a memory cell include charging a capacitor coupled to the memory cell to a particular voltage level and programming the memory cell from a first state to a second state by controlling discharge of the capacitor through a resistive switching element of the memory cell.

Nonvolatile memory device and method for manufacturing same

According to one embodiment, a nonvolatile memory device includes a first wiring layer. The device includes a second wiring layer intersecting with the first wiring layer. And the device includes a first memory layer provided at a position where the first wiring layer and the second wiring layer intersect. And the first memory layer contacts with the first wiring layer, and the first wiring layer is a layer which is capable of supplying a metal ion to the first memory layer.

Small-Grain Three-Dimensional Memory

The present invention discloses a small-grain three-dimensional memory (3D-MSG). Each of its memory cells comprises a thin-film diode with critical dimension no larger than 40 nm. The thin-film diode comprises at least a small-grain material, whose grain size G is substantially smaller than the diode size D. The small-grain material is preferably a nano-crystalline material or an amorphous material. The critical dimension f of the small-grain diode is smaller than the critical dimension F of the single-crystalline transistor.

Semiconductor memory device

A semiconductor memory device comprises a plurality of memory layers arranged in multilayer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lines, and a plurality of memory cells connected at intersections of the first lines and the second lines; a pulse generator operative to generate pulses required for data access to the memory cell; and a control means operative to control the pulse generator such that the pulse output from the pulse generator has energy in accordance with the memory layer to which the access target memory cell belongs.

Memory Cells, Methods of Programming Memory Cells, and Methods of Forming Memory Cells

Some embodiments include methods of programming a memory cell. A plurality of charge carriers may be moved within the memory cell, with an average charge across the moving charge carriers having an absolute value greater than 2. Some embodiments include methods of forming and programming an ionic-transport-based memory cell. A stack is formed to have programmable material between first and second electrodes. The programmable material has mobile ions which are moved within the programmable material to transform the programmable material from one memory state to another. An average charge across the moving mobile ions has an absolute value greater than 2. Some embodiments include memory cells with programmable material between first and second electrodes. The programmable material includes an aluminum nitride first layer, and includes a second layer containing a mobile ion species in common with the first layer.

Sense amplifier circuitry for resistive type memory

Example embodiments include a resistive type memory current sense amplifier circuit including differential output terminals, first and second input terminals, pre-charge transistors, and current modulating transistors coupled directly to the pre-charge transistors. The pre-charge configuration provides high peak currents to charge the bit line and reference line during a “ready” or “pre-charge” stage of operation of the current sense amplifier circuit. The current modulating transistors are configured to operate in a saturation region mode during at least a “set” or “amplification” stage. The current modulating transistors continuously average a bit line current and a reference line current during the “set” or “amplification” stage, thereby improving noise immunity of the circuit. During a “go” or “latch” stage of operation, a logical value “0” or “1” is latched at the differential output terminals based on positive feedback of a latch circuit.

Electronic memory device

An electronic device includes a first electrode, a second electrode, and a solid electrolyte made of an ion-conducting material, the first and second electrodes being configured to form a metal dendrite. The device further includes a third electrode, an interface layer contacting the third electrode and a third surface of the electrolyte, the interface layer being an ionic insulator and an electronic insulator. The third electrode and the dendrite are arranged such that the device has two resistive states.

Operating method for memory device and memory array and operating method for the same

An operating method for a memory device and a memory array and an operating method for the same are provided. The operating method for the memory device comprises following steps. A memory device is made being in a set state. A method for making the memory device being in the set state comprises applying a first bias voltage to the memory device. The memory device in the set state is read. A method for reading the memory device in the set state comprises applying a second bias voltage to the memory device. A recovering bias voltage is applied to the memory device. The step for applying the recovering bias voltage is performed after the step for applying the first bias voltage or the step for applying the second bias voltage.

Memory devices, circuits and, methods that apply different electrical conditions in access operations

A memory device can include a plurality of physical blocks that each include a number of memory elements programmable between at least two different impedance states, the memory elements being subject to degradation in performance; and bias circuits configured to applying healing electrical conditions to at least one spare physical block that does not contain valid data; wherein the healing electrical conditions are different from write operation electrical conditions, and reverse degradation of the memory elements of the at least one spare physical block.

ELECTRONIC DEVICE

An electronic device includes a semiconductor memory unit. The semiconductor memory unit includes a plurality of first lines extending in a first direction, a plurality of second lines extending in a second direction intersecting the first direction, and a plurality of variable resistance patterns that is positioned at intersections of the first lines and the second lines and disposed between the first lines and the second lines in a vertical direction. Each of the variable resistance patterns has an elongated shape in a plan view and a portion of each of the variable resistance patterns is disposed outside a region in which a corresponding first line and a corresponding second line overlap with each other. 1. An electronic device comprising a semiconductor memory unit , wherein the semiconductor memory unit comprises:a plurality of first lines extending in a first direction;a plurality of second lines extending in a second direction intersecting the first direction; anda plurality of variable resistance patterns positioned at intersections of the first lines and the second lines and disposed between the first lines and the second lines in a direction that is perpendicular to the first and second directions,wherein each of the variable resistance patterns has an elongated shape in a plan view and a portion of each of the variable resistance patterns extends outside a region in which a corresponding first line and a corresponding second line overlap with each other.2. The electronic device according to claim 1 , wherein a direction of a major axis of each of the variable resistance patterns intersects the first and second directions.3. The electronic device according to claim 2 , wherein claim 2 , when a third direction intersects the first and second directions and an angle between the third direction and the first direction is substantially the same as an angle between the third direction and the second direction claim 2 , the direction of the major axis is ...

METAL FILAMENT RERAM CELL WITH CURRENT LIMITING DURING PROGRAM AND ERASE

A ReRAM memory cell includes a ReRAM element, a programming circuit coupled to the ReRAM element and defining a programming circuit path in the ReRAM memory cell, and an erase circuit coupled to the ReRAM element and defining an erase circuit path in the ReRAM memory cell. The programming circuit path is separate from the erase circuit path. 1. A ReRAM memory cell for use in a memory array , the ReRAM memory cell comprising:a ReRAM element having a first terminal and a second terminal, the first terminal connected to an ion-source electrode in the ReRAM element and coupled to a row power line in a row of the memory array;a programming circuit coupled to the ReRAM element and defining a programming circuit path in the ReRAM memory cell, the programming circuit including an n-channel transistor coupled between the second terminal of the ReRAM element and a first column bit line in a column of the memory array, the n-channel transistor having a gate coupled to an n-word line in the row of the memory array; andan erase circuit coupled to the ReRAM element and defining an erase circuit path in the ReRAM memory cell, the erase circuit including a p-channel transistor coupled between the second terminal of the ReRAM element and a second column bit line in the column in the memory array, the p-channel transistor having a gate coupled to a p-word line in the row of the memory array.2. (canceled)3. (canceled)4. A ReRAM memory cell for use in a memory array , the ReRAM memory cell comprising:a ReRAM element having a first terminal and a second terminal, the first terminal connected to an ion-source electrode in the ReRAM element;a programming circuit coupled to the ReRAM element and defining a programming circuit path in the ReRAM memory cell, the programming circuit including a p-channel programming transistor coupled between the first terminal of the ReRAM element and a first column bit line in a column of the memory array, the p-channel programming transistor having a gate ...

CIRCUIT AND LAYOUT FOR RESISTIVE RANDOM-ACCESS MEMORY ARRAYS

A ReRAM memory array includes rows and columns of ReRAM cells. Each ReRAM cell in a row and column of the array includes a ReRAM device having an ion source end coupled to a bias line associated with the row of the array containing the ReRAM device. A first transistor is coupled between the solid electrolyte end of the ReRAM device and a bit line associated with the column of the array containing the ReRAM cell. The first transistor has a gate coupled to a first word line associated with the row containing the ReRAM cell. A second transistor is coupled between the solid electrolyte end of the ReRAM device and the bit line associated with the column of the array containing the ReRAM cell. The second transistor has a gate coupled to a second word line associated with the row containing the ReRAM cell. 1. A ReRAM memory array including rows and columns of ReRAM cells , each ReRAM cell in a row and column of ReRAM cells comprising:a ReRAM device having an ion source end and a solid electrolyte end, the ion source end coupled to a bias line associated with the row of the array containing the ReRAM device;a first n-channel transistor coupled between the solid electrolyte end of the ReRAM device and a bit line associated with the column of the array containing the ReRAM cell, the first n-channel transistor having a gate coupled to a first word line associated with the row containing the ReRAM cell; anda second n-channel transistor coupled between the solid electrolyte end of the ReRAM device and the bit line associated with the column of the array containing the ReRAM cell, the second n-channel transistor having a gate coupled to a second word line associated with the row containing the ReRAM cell;wherein the first word line and the second word line associated with the row containing the memory cell are electrically connected together.2. The ReRAM memory array of further including a sense amplifier coupled to the bit line for each column in the array.3. The ReRAM memory ...

THERMAL DISPERSION LAYER IN PROGRAMMABLE METALLIZATION CELL

Some embodiments relate to a memory device. The memory device includes a programmable metallization cell random access memory (PMCRAM) cell. The programmable metallization cell comprises a dielectric layer disposed over a bottom electrode, the dielectric layer contains a central region. A conductive bridge is formable and erasable within the dielectric layer and the conductive bridge is contained within the central region of the dielectric layer. A metal layer is disposed over the dielectric layer. A heat dispersion layer is disposed between the bottom electrode and the dielectric layer. 1. A memory device , comprising:a bottom electrode;a dielectric layer disposed over the bottom electrode;a top electrode disposed over the dielectric layer, wherein a conductive bridge is selectively formable within the dielectric layer to couple the bottom electrode to the top electrode; anda heat dispersion layer disposed between the bottom electrode and the dielectric layer.2. The memory device of claim 1 , wherein the heat dispersion layer is comprised of a material having a thermal conductivity greater than 100 W/m−K.3. The memory device of claim 1 , wherein the heat dispersion layer is comprised of aluminum nitride claim 1 , silicon carbide claim 1 , beryllium oxide claim 1 , or boron nitride.4. The memory device of wherein the memory device is configured to switch between a high-resistance state and a low-resistance state;wherein, when in the high-resistance state, a conductive pillar is disposed within a central region of the dielectric layer, the conductive pillar having a bottom surface in contact with an upper surface of the heat dispersion layer and having a top surface spaced apart from the top electrode by an upper portion of the dielectric layer; andwherein, when in the low-resistance state, the conductive pillar remains disposed within the central region of the dielectric layer and a conductive bridge is formed to extend through the upper portion of the dielectric ...

MEMORY CIRCUIT USING RESISTIVE RANDOM ACCESS MEMORY ARRAYS IN A SECURE ELEMENT

A memory circuit using resistive random access memory (ReRAM) arrays in a secure element. The ReRAM arrays can be configured as content addressable memories (CAMs) or random access memories (RAMs) on the same die, with the control circuitry for performing comparisons of reference patterns and input patterns located outside of the ReRAM arrays. By having ReRAM arrays configured as CAMs and RAMs on the same die, certain reference patterns can be stored in CAMs and others in RAMs depending on security needs. For additional security, a heater can be used to erase reference patterns in the ReRAM arrays when desired. 1. (canceled)2. The secure element of claim 11 , further comprising a compare circuit for comparing the first block of a plurality of ReRAM cells configured for storing the first reference pattern to the second block of a plurality of ReRAM cells configured for receiving the first input pattern claim 11 , wherein the compare circuit is located outside of the first ReRAM array and the second ReRAM array.3. The secure element of claim 2 , further comprising a second die separate from the first die claim 2 , wherein the compare circuit is located on the second die.4. The secure element of claim 11 , further comprising a heater located on the first ReRAM array configured as a CAM claim 11 , wherein the first heater is configured to heat the first ReRAM array and erase the first reference pattern.5. The secure element of claim 11 , further comprising a heater located on the second ReRAM array configured as a RAM claim 11 , wherein the second heater is configured to heat the second ReRAM array and erase the second reference pattern.6. The secure element of claim 11 , further comprising:a third ReRAM array configured as a content CAM located on the first die, wherein the CAM comprises a fourth block of a plurality of ReRAM cells configured for storing a third reference pattern and a fifth block of a plurality of ReRAM cells configured for receiving a second input ...

Resistive Devices and Methods of Operation Thereof

In one embodiment, a method of operating a resistive switching device includes applying a signal comprising a pulse on a first terminal of a two terminal resistive switching device having the first terminal and a second terminal. The resistive switching device has a first state and a second state. The pulse includes a first ramp from a first voltage to a second voltage over a first time period. The first time period is at least 0.1 times a total time period of the pulse. 1. A semiconductor device comprising:a two terminal resistive switching device having a first terminal and a second terminal and having a first state and a second state;an access device having a first access terminal and a second access terminal coupled to the first terminal of the resistive switching device; a first ramp voltage from a first voltage to a second voltage over a first time period,', 'a second ramp voltage from the second voltage to a third voltage over a second time period, wherein the second ramp voltage has an opposite slope to the first ramp voltage, wherein the first time period is at least 0.1 times a total time period of the first time period plus the second time period, wherein the second time period is at least 0.1 times the total time period of the first time period plus the second time period; and, 'a signal generator configured to generate'}an access circuit configured to apply the signal on the first access terminal, wherein the resistive switching device is configured to change from the first state to the second state in response to the signal.2. The device of claim 1 , wherein the access device is a diode claim 1 , or a transistor.3. The device of claim 1 , wherein the access device is a transistor claim 1 , and wherein the first terminal is a gate of the transistor.4. The device of claim 1 , wherein the access device is a transistor claim 1 , and wherein the first terminal is a source/drain of the transistor.5. The device of claim 1 , wherein the resistive switching ...

CONCURRENT READ AND WRITE OPERATIONS IN A SERIAL FLASH DEVICE

A method of controlling an NVM device can include: (i) receiving, by an interface, a write command from a host; (ii) beginning execution of a write operation on a first array plane of a memory array in response to the write command, where the memory array includes a plurality of NVM cells arranged in a plurality of array planes; (iii) receiving, by the interface, a read command from the host; (iv) suspending the write operation in response to detection of the read command during execution of the write operation; (v) beginning execution of a read operation on a second array plane in response to the read command; and (vi) resuming the write operation after the read operation has at least partially been executed. 1. A non-volatile memory (NVM) device , comprising:a) an interface configured to receive write and read commands from a host;b) a memory array comprising a plurality of NVM cells arranged in a plurality of array planes; andc) a memory controller configured to execute a write operation on a first of the plurality of array planes in response to the write command, and to execute a read operation on a second of the plurality of array planes in response to the read command, wherein the memory controller is configured to suspend the write operation in response to detection of the read command during execution of the write operation, and wherein the memory controller is configured to resume the write operation after the read operation has at least partially been executed.2. The NVM device of claim 1 , wherein the read command comprises a plurality of clock cycles added to allow time for the write operation to be suspended.3. The NVM device of claim 1 , wherein the read command comprises a plurality of dummy cycles added to allow time for the write operation to be suspended.4. The NVM device of claim 1 , wherein the read command comprises suspension of a clock signal to allow time for the write operation to be suspended.5. The NVM device of claim 1 , wherein the ...

ACCESS SIGNAL ADJUSTMENT CIRCUITS AND METHODS FOR MEMORY CELLS IN A CROSS-POINT ARRAY

Systems, integrated circuits, and methods to utilize access signals to facilitate memory operations in scaled arrays of memory elements are described. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements and line driver. The line driver can be configured to access a resistive memory element in the cross-point array. 1. (canceled)2. A memory device comprising:a cross-point array comprising a plurality of two-terminal memory elements; anda target magnitude generator coupled to the cross-point array and configured to generate a target magnitude for an access signal applied to the cross-point array, the target magnitude generator comprising a disturb isolation circuit to isolate or reduce disturb effects associated with the plurality of two-terminal memory elements, the disturb isolation circuit comprising a current enhancement array.3. The memory device of claim 2 , wherein the current enhancement array comprises a plurality of resistive memory elements configured to generate an amount of current at a portion of the target magnitude.4. The memory device of claim 3 , wherein the plurality of resistive memory elements in the current enhancement array are coupled in parallel.5. The memory device of claim 3 , wherein the amount of current generated by the current enhancement array is equivalent to a current generated by a resistive memory element with the target magnitude of the access signal.6. The memory device of claim 3 , wherein each of the plurality of resistive memory elements is coupled to a corresponding bit line of a plurality of bit lines of the current enhancement array.7. The memory device of claim 6 , wherein the target magnitude generator further comprises:a multiplexer; anda current selector, wherein the current selector is configured to control the multiplexer to select a subset of the plurality of bit lines of the current enhancement array from which to receive the amount of current.8. ...

All around electrode for novel 3D RRAM applications

A resistive switching memory device can include three or more electrodes interfacing a switching layer, including a top electrode, a bottom electrode, and a side electrode. The top and bottom electrodes can be used for forming conductive filaments and for reading the memory device. The side electrode can be used to control the resistance state of the switching layer. 1. A resistive switching memory structure comprising:a substrate; wherein the dielectric layer is operable as a resistive switching layer,', 'wherein the dielectric layer has a bottom surface facing the substrate, a top surface opposite the bottom surface, and a side surface;, 'a dielectric layer above the substrate,'}a first electrode facing the bottom surface;a second electrode facing the top surface;a third electrode interfacing the side surface;2. A resistive switching memory structure as inwherein the dielectric layer comprises a metal oxide material.3. A resistive switching memory structure as inwherein the first or second electrode interfaces the bottom or top electrode, respectively.4. A resistive switching memory structure as in further comprisinga current limiter element disposed between the first electrode and the bottom surface.5. A resistive switching memory structure as in further comprisinga current limiter element disposed between the second electrode and the top surface.6. A resistive switching memory structure as inwherein the third electrode interfaces the dielectric layer at two opposite sides or at all sides around the dielectric layer.7. A resistive switching memory structure as inwherein the third electrode is separated from the first or second electrode by an insulator layer.8. A resistive switching memory structure as inwherein a lateral dimension of the dielectric layer is smaller than a lateral dimension of the first or second electrode.9. A resistive switching memory structure as inwherein the dielectric layer comprises a vertical interface,wherein the vertical interface is ...

METHODS OF FORMING RESISTIVE MEMORY ELEMENTS

A resistive memory element comprises a first electrode, an active material over the first electrode, a buffer material over the active material and comprising longitudinally extending, columnar grains of crystalline material, an ion reservoir material over the buffer material, and a second electrode over the ion reservoir material. A memory cell, a memory device, an electronic system, and a method of forming a resistive memory element are also described. 1. A method of forming a resistive memory element , comprising:forming a switchable resistivity material over an electrode, the switchable resistivity material comprising one or more of a metal oxide and a chalcogenide;{'sub': x', 'x', 'x', 'x', 'y', 'x', 'y', 'x', 'y', 'x', 'y', 'x', 'y', 'x', 'y', 'x', 'y', 'x', 'y', 'x', 'y, 'forming a buffer material over the switchable resistivity material, the buffer material comprising longitudinally extending, columnar grains of one or more of TiN, TaN, WN, TiNC, TaNC, WNC, TiNB, TaNB, WNB, TiNSi, TaNSi, and WNSi;'}forming a material over the buffer material, the material comprising a chalcogen and one or more of Cu, Ag, and Al; andforming another electrode over the material.2. The method of claim 1 , wherein forming a switchable resistivity material over an electrode comprises forming one or more of SiO claim 1 , AlO claim 1 , HfO claim 1 , HfSiO claim 1 , ZrO claim 1 , ZrSiO claim 1 , TiO claim 1 , TiSiO claim 1 , TaO claim 1 , TaSiO claim 1 , NbO claim 1 , NbSiO claim 1 , VO claim 1 , VSiO claim 1 , WO claim 1 , WSiO claim 1 , MoO claim 1 , MoSiO claim 1 , CrO claim 1 , and CrSiOover the electrode.3. The method of claim 1 , wherein forming a buffer material over the switchable resistivity material comprises forming the buffer material to further comprise one or more of O claim 1 , S claim 1 , Se claim 1 , and Te.4. The method of claim 1 , wherein forming a buffer material over the switchable resistivity material comprises forming the buffer material to have a thickness ...

Memory Cells, Non-Volatile Memory Arrays, Methods Of Operating Memory Cells, Methods Of Writing To And Writing From A Memory Cell, And Methods Of Programming A Memory Cell

In one aspect, a method of operating a memory cell includes using different electrodes to change a programmed state of the memory cell than are used to read the programmed state of the memory cell. In one aspect, a memory cell includes first and second opposing electrodes having material received there-between. The material has first and second lateral regions of different composition relative one another. One of the first and second lateral regions is received along one of two laterally opposing edges of the material. Another of the first and second lateral regions is received along the other of said two laterally opposing edges of the material. At least one of the first and second lateral regions is capable of being repeatedly programmed to at least two different resistance states. Other aspects and implementations are disclosed.

INTEGRATED CIRCUITS WITH PROGRAMMABLE NON-VOLATILE RESISTIVE SWITCH ELEMENTS

Integrated circuits with programmable resistive switch elements are provided. A programmable resistive switch element may include two non-volatile resistive elements connected in series and a programming transistor. The programmable resistive switch elements may be configured in a crossbar array and may be interposed within the user data path. Driver circuits may also be included for selectively turning on or turning off the switches by applying positive and optionally negative voltages. 1. An integrated circuit , comprising:an array of programmable non-volatile switch elements;a first logic driver circuit that is coupled to a column of programmable non-volatile switch elements in the array; anda second logic driver circuit that is coupled to a row of programmable non-volatile switch elements in the array, wherein the first and second logic driver circuits drive wires configured to convey active user signals.2. The integrated circuit of claim 1 , wherein the first logic driver circuit is a tristate buffer circuit.3. The integrated circuit of claim 2 , wherein the second logic driver circuit is also a tristate buffer circuit.4. The integrated circuit of claim 1 , further comprising:a first shift register that stores first configuration signals; anda first plurality of multiplexers configured to route a selected one of the first configuration signals from the first shift register and the active user signals to the first logic driver circuit.5. The integrated circuit of claim 4 , further comprising:a second shift register that stores second configuration signals; anda second plurality of multiplexers configured to route a selected one of the second configuration signals from the second shift register and the active user signals to the second logic driver circuit.6. The integrated circuit of claim 1 , further comprising:a programming source driver circuit that is coupled to the column of programmable non-volatile switch elements in the array, wherein the programming ...

APPARATUS FOR LOW POWER WRITE AND READ OPERATIONS FOR RESISTIVE MEMORY

Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected. 1. An apparatus comprising:a resistive memory cell coupled to a bit line and a select line;a first pass-gate coupled to the bit line;a second pass-gate coupled to the select line; anda differential write driver to receive a differential input and to drive a differential output to the first and second pass-gates, wherein the differential write driver to cause a first output of the differential output to have a different drive strength than a second output of the differential output.2. The apparatus of claim 1 , wherein the differential write driver comprises an adjustable p-type current source.3. The apparatus of further comprises a variable voltage generator to provide a bias for the adjustable p-type current source according to the first or second outputs or both.4. The apparatus of claim 1 , wherein the differential write driver comprises an adjustable n-type current source.5. The apparatus of further comprises a variable voltage generator to provide a bias for the adjustable n-type current source ...

HIGH-RELIABILITY HIGH-SPEED MEMRISTOR

A memristor has a first electrode, a second electrode parallel to the first electrode, and a switching layer disposing between the first and second electrodes. The switching layer contains a conduction channel and a reservoir zone. The conduction channel has a Fermi glass material with a variable concentration of mobile ions. The reservoir zone is laterally disposed relative to the conduction channel, and functions as a source/sink of mobile ions for the conduction channel In the switching operation, under the cooperative driving force of both electric field and thermal effects, the mobile ions are moved into or out of the laterally disposed reservoir zone to vary the concentration of the mobile ions in the conduction channel to change the conductivity of the Fermi glass material. 1. A memristor , comprising:a first electrode;a second electrode parallel to the first electrode; anda switching layer disposing between the first and second electrode, and containing a conduction channel and a reservoir zone, the conduction channel having a Fermi glass material having a variable concentration of mobile ions, the reservoir zone being laterally disposed relative to the conduction channel and functioning as a source/sink of mobile ions for the conduction channel during a switching operation, in which the mobile ions are moved into or out of the laterally disposed reservoir zone to vary the concentration of the mobile tons In the conduction channel to change a conductivity of the Fermi glass material.2. A memristor as in claim 1 , wherein the Fermi glass material is a solid solution of a metal and the mobile ions.3. A memristor as in claim 2 , wherein the metal is tantalum.4. A memristor as in claim 3 , wherein the mobile ions are oxygen anions.5. A memristor as in claim 1 , wherein the Fermi glass material is selected from the group of oxides claim 1 , nitrides claim 1 , sulfides claim 1 , phosphorides claim 1 , chalcogenides claim 1 , carbides claim 1 , boronides claim 1 , ...

Circuit and System of Using Junction Diode of MOS as Program Selector for Programmable Resistive Devices

A programmable resistive device cell using at least one MOS device as selector can be programmed or read by turning on a source junction diode of the MOS or a channel of the MOS. A programmable resistive device cell can include at least one programmable resistive element and at least one MOS device. The programmable resistive element can be coupled to a first supply voltage line. The MOS can have a source coupled to the programmable resistive element, a bulk coupled to a drain, a drain coupled to a second supply voltage line, and a gate coupled to a third supply voltage line. The programmable resistive element can be configured to be programmable or readable by applying voltages to the first, second, and/or third supply voltage lines to turn on the source junction of the MOS and/or to turn on the channel of the MOS.

SWITCHING BLOCK CONFIGURATION BIT COMPRISING A NON-VOLATILE MEMORY CELL

A configuration bit for a switching block routing array comprising a non-volatile memory cell is provided. By way of example, the configuration bit and switching block routing array can be utilized for a field programmable gate array, or other suitable circuit(s), integrated circuit(s), application specific integrated circuit(s), electronic device or the like. The configuration bit can comprise a switch that selectively connects or disconnects a node of the switching block routing array. A non-volatile memory cell connected to the switch can be utilized to activate or deactivate the switch. In one or more embodiments, the non-volatile memory cell can comprise a volatile resistance switching device connected in serial to a gate node of the switch, configured to trap charge at the gate node to activate the switch, or release the charge at the gate node to deactivate the switch. 1a non-volatile switch comprising an input node, an output node and a control gate, the input node connected to a first conductive line of a switching block routing array and the output node connected to a second conductive line of the switching block routing array;a volatile switch having a first contact and a second contact, the second contact is conductively connected to the control gate of the non-volatile switch; anda program circuit configured to selectively provide a voltage from a voltage source to the first contact of the volatile switch.. A circuit, comprising: This application for patent is a continuation of and claims priority to U.S. application Ser. No. 15/469,179, titled SWITCHING BLOCK CONFIGURATION BIT COMPRISING A NON-VOLATILE MEMORY CELL and filed Mar. 24, 2017, which is hereby incorporated by reference herein in its entirety and for all purposes.U.S. application Ser. No. 14/717,185 entitled “NON-VOLATILE MEMORY CELL UTILIZING VOLATILE SWITCHING TWO TERMINAL DEVICE AND A MOS TRANSISTOR” and filed May 20, 2015, U.S. application Ser. No. 14/588,185 entitled “SELECTOR DEVICE FOR ...

Logic integrated circuit and semiconductor device

An object of the present invention is to provide a logic integrated circuit that increases reliability of configuration information held in a switch while maintaining high tamper resistance and a small chip area. The logic integrated circuit according to the present invention includes: a three-terminal resistance change switch including a first resistance change switch and a second resistance change switch connected in series; a reading circuit which reads first data based on a resistance state of the first resistance change switch and second data based on a resistance state of the second resistance change switch; and a first error detection circuit which compares the first data with the second data and issue an output based on a result of the comparison.

RRAM MEMORY CELL WITH MULTIPLE FILAMENTS

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a conductive element disposed within a dielectric structure over the substrate. The conductive element has a top surface extend between outermost sidewalls of the conductive element. A first resistive random access memory (RRAM) element is arranged within the dielectric structure and has a first data storage layer directly contacting the top surface of the conductive element. A second RRAM element is arranged within the dielectric structure and has a second data storage layer directly contacting the top surface of the conductive element. 1. An integrated chip , comprising:a conductive element disposed within a dielectric structure over a substrate, wherein the conductive element comprises a top surface extending between outermost sidewalls of the conductive element;a first resistive random access memory (RRAM) element arranged within the dielectric structure and having a first data storage layer directly contacting the top surface of the conductive element; anda second RRAM element arranged within the dielectric structure and having a second data storage layer directly contacting the top surface of the conductive element.2. The integrated chip of claim 1 , wherein a bottom surface of the conductive element has smaller width than the top surface of the conductive element.3. The integrated chip of claim 2 , further comprising:one or more lower interconnect layers disposed within a lower inter-level dielectric (ILD) structure that is between the bottom surface of the conductive element and the substrate.4. The integrated chip of claim 3 , wherein the conductive element is a different material than the one or more lower interconnect layers.5. The integrated chip of claim 3 , further comprising:an insulating layer disposed over the lower ILD structure and laterally surrounding a part of the conductive element, wherein the conductive element has a lower surface that is ...

Current Forming Of Resistive Random Access Memory (RRAM) Cell Filament

A memory device includes a metal oxide material disposed between and in electrical contact with first and second conductive electrodes, and an electrical current source configured to apply one or more electrical current pulses through the metal oxide material. For each of the one or more electrical current pulses, an amplitude of the electrical current increases over time during the electrical current pulse to form a conductive filament in metal oxide material. 1. A method of forming a conductive filament in metal oxide material disposed between and in electrical contact with first and second conductive electrodes , the method comprising:applying one or more electrical current pulses through the metal oxide material;wherein for each of the one or more electrical current pulses, an amplitude of the electrical current increases over time during the electrical current pulse.2. The method of claim 1 , wherein for each of the one or more of the electrical current pulses claim 1 , the amplitude of the electrical current increases in discrete steps.3. The method of claim 2 , wherein for each of the one or more of the electrical current pulses claim 2 , a number of the discrete steps exceeds that of any of the one or more of the electrical current pulses preceding the electrical current pulse.4. The method of claim 1 , wherein for each of the one or more of the electrical current pulses claim 1 , a maximum of the electrical current amplitude exceeds that of any of the one or more of the electrical current pulses preceding the electrical current pulse.5. The method of claim 1 , wherein for each of the one or more of the electrical current pulses claim 1 , a duration of the one electrical current pulse exceeds that of any of the one or more of the electrical current pulses preceding the electrical current pulse.6. The method of claim 1 , wherein all of the one or more of the electrical current pulses have a same duration.7. The method of claim 1 , wherein for each of the one ...

RESISTIVE RANDOM ACCESS MEMORY DEVICE

A resistive random access memory device includes a first electrode; a solid electrolyte made of metal oxide extending onto the first electrode; a second electrode able to supply mobile ions circulating in the solid electrolyte made of metal oxide to the first electrode to form a conductive filament between the first and second electrodes when a voltage is applied between the first and second electrodes; an interface layer including a transition metal from groups 3, 4, 5 or 6 of the periodic table and a chalcogen element; the interface layer extending onto the solid electrolyte made of metal oxide, the second electrode extending onto the interface layer. 1. A method of manufacturing a resistive random access memory device , the method comprising:forming a first electrode;forming, on the first electrode, a solid electrolyte made of metal oxide extending at least partially onto the first electrode;forming, on the solid electrolyte made of metal oxide, an interface layer; depositing, on the solid electrolyte made of metal oxide, a layer comprising a chalcogen element and a soluble conductive element;', 'depositing, on the layer comprising the chalcogen element and the soluble conductive element, a layer comprising a transition metal from groups 3, 4, 5 or 6 of the periodic table;', 'thermal annealing for at least partially diffusing the transition metal into the layer comprising the chalcogen element and the soluble conductive element, and for obtaining the interface layer; and, 'forming, on the interface layer, a soluble second electrode, the second electrode being configured to supply mobile ions circulating in the solid electrolyte made of metal oxide to the first electrode to form a conductive filament between the first and second electrodes when a voltage is applied between the first and second electrodes, wherein forming the interface layer comprises'}wherein forming the second electrode comprises depositing, on the interface layer, an ion source layer comprising ...

A Switching Resistor And Method Of Making Such A Device

A switching resistor has a low resistance state and a high resistance state. The switching resistor comprises a dielectric layer disposed between a first electrode and a second electrode. The switching resistor further comprises a textured boundary surface between the first electrode and the dielectric layer. The textured boundary surface promotes the formation of a conductive pathway in the dielectric layer between the first electrode and the second electrode. 139-. (canceled)40. A switching resistor having a low resistance state and a high resistance state , comprising a dielectric layer disposed between a first electrode and a second electrode , wherein the dielectric is an oxide of silicon , and a textured boundary surface between the first electrode and the dielectric layer , wherein the dielectric layer includes column structures extending from the textured boundary surface between the first electrode and the dielectric layer towards the second electrode , wherein the textured boundary surface is configured to promote the formation of a conductive pathway in the dielectric layer , at the edge of a column structure , between the first electrode and the second electrode for intrinsic resistance switching.41. The switching resistor of claim 40 , wherein the textured boundary surface comprises a predetermined texture pattern.42. The switching resistor of claim 40 , wherein the textured boundary surface comprises random texturing.43. The switching resistor of claim 40 , wherein the first electrode and second electrodes are formed of metal or silicon.44. The switching resistor of claim 40 , wherein the dielectric layer is formed on the first electrode.45. The switching resistor of claim 40 , wherein at least one of the column structures is configured to form said conductive pathway in response to the application of an electroforming voltage to the switching resistor.46. The switching resistor of claim 45 , wherein boundaries between the column structures have a ...

PROGRAMMABLE ARTIFICIAL NEURON AND ASSOCIATED PROGRAMMING METHOD

A programmable artificial neuron emitting an output signal controlled by at least one control parameter, includes, for each control parameter, a capacitor and at least one block including at least one multiplexer configured to be in two states: a programming state and an operating state; a transistor; and a non-volatile resistive random access memory connected in series with the transistor, the capacitor and the resistive random access memory being mounted in parallel. The multiplexer is configured to, when it is in the programming state, set a resistance value of the resistive random access memory to set the value of the control parameter; when it is in the operating state, conserve the set resistance value of the resistive random access memory. 2. The programmable artificial neuron according to claim 1 , wherein the transistor is a MOS transistor.3. The programmable artificial neuron according to claim 1 , wherein the non-volatile resistive random access memory is an OxRAM claim 1 , CBRAM or PCRAM type memory.4. The programmable artificial neuron according to claim 1 , wherein claim 1 , when the control parameter is a time constant claim 1 , the programmable artificial neuron comprises a block and a capacitor.5. The programmable artificial neuron according to claim 1 , wherein claim 1 , when the control parameter is a refractory period claim 1 , the programmable artificial neuron comprises a block and a capacitor.6. The programmable artificial neuron according to claim 1 , wherein claim 1 , when the control parameter is a spike frequency adaptation behaviour claim 1 , the programmable artificial neuron comprises two blocks and a capacitor.7. A method for programming a programmable artificial neuron according to claim 1 , comprising for each block claim 1 , the following steps:electrically disconnecting the block from the artificial neuron, electrically connecting the gate of the transistor of the block to a voltage source and electrically connecting the resistive ...

One-Time Programmable Device with Integrated Heat Sink

Junction diodes fabricated in standard CMOS logic processes can be used as program selectors with at least one heat sink or heater to assist programming for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The heat sink can be at least one thin oxide area, extended OTP element area, or other conductors coupled to the OTP element to assist programming. A heater can be at least one high resistance area such as an unsilicided polysilicon, unsilicided active region, contact, via, or combined in serial, or interconnect to generate heat to assist programming. The OTP device has at least one OTP element coupled to at least one diode in a memory cell. The diode can be constructed by P+ and N+ active regions in a CMOS N well, or on an isolated active region as the P and N terminals of the diode. The isolation between P+ and the N+ active regions of the diode in a cell or between cells can be provided by dummy MOS gate, SBL, or STI/LOCOS isolations. The OTP element can be polysilicon, silicided polysilicon, silicide, polymetal, metal, metal alloy, local interconnect, metal-0, thermally isolated active region, CMOS gate, or combination thereof.

Memory Sense Amplifiers and Memory Verification Methods

Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time, a second input configured to receive a reference signal, modification circuitry configured to provide a data signal at the first input from the memory element having a plurality of different voltages corresponding to respective ones of different memory states of the memory cell at the different moments in time, and comparison circuitry coupled with the modification circuitry and configured to compare the data signal and the reference signal at the different moments in time and to provide an output signal indicative of the memory state of the memory cell at the different moments in time as a result of the comparison to implement a plurality of verify operations of the memory states of the memory cell at the different moments in time. 1. A memory sense amplifier comprising:a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time;a second input configured to receive a reference signal;modification circuitry configured to provide a data signal at the first input from the memory element having a plurality of different voltages corresponding to respective ones of different memory states of the memory cell at the different moments in time; andcomparison circuitry coupled with the modification circuitry and configured to compare the data signal and the reference signal at the different moments in time and to provide an output signal indicative of the memory state of the memory cell at the different moments in time as a result of the comparison to implement a plurality of verify operations of the memory states of the memory cell at the different moments in time.2. The amplifier of wherein the modification circuitry ...

SYNAPSE AND SYNAPTIC ARRAY, AND COMPUTING SYSTEM USING THE SAME AND DRIVING METHOD THEREOF

The present invention relates to a synapse and synaptic array, and a computing system using the same. The synaptic device according to an exemplary embodiment of the present invention includes a transistor in which a synaptic input signal is applied to any one electrode of source and drain electrodes; and a plurality of two-terminal variable resistance memory devices in which a first electrode is electrically globally connected to a gate electrode of the transistor, wherein a separate memory voltage is applied to a second electrode of each variable resistance memory device to adjust a gate voltage applied to the gate electrode, thereby controlling a synaptic output signal which is output to the other one of the source and drain electrodes. 1. A synapse , comprising:a transistor in which a synaptic input signal is applied to any one electrode of source and drain electrodes; anda plurality of two-terminal variable resistance memory devices in which a first electrode is electrically commonly connected to a gate electrode of the transistor,wherein a separate memory voltage is applied to a second electrode of each variable resistance memory device to adjust a gate voltage applied to the gate electrode, thereby controlling a synaptic output signal which is output to the other one of the source and drain electrodes.2. The synapse of claim 1 , wherein the total conductance of all variable resistance memory devices is modulated to adjust the gate voltage claim 1 , by modulating the conductance of each variable resistance memory device according to each memory voltage.3. The synapse of claim 1 , wherein a memory voltage of a bias is applied to a first variable resistance memory device claim 1 , andwherein a memory voltage of a potentiation pulse or depression pulse is applied to a second variable resistance memory device.4. The synapse of claim 1 , wherein while the conductance of a first variable resistance memory device increases claim 1 , the conductance of a second ...

DIFFERENTIAL IONIC ELECTRONIC TRANSISTORS

An ionic transistor including a first source, a first drain spaced apart from the first source, and a first storage layer electrically connected to the first source and the first drain. The ionic transistor also includes a second source spaced apart from the first source, a second drain spaced apart from the second source, and a second storage layer electrically connected to the second source and the second drain. The ionic transistor further includes an electrolyte layer situated between and electrically connected to the first and second storage layers. The ionic transistor may be implemented as non-volatile memory in a machine learning (ML) application.

CIRCUITRY AND METHODS FOR PROGRAMMING RESISTIVE RANDOM ACCESS MEMORY DEVICES

A method for programming a ReRAM cell including a ReRAM device connected in series with an access transistor includes biasing the ReRAM cell with a programming potential that configures the access transistor in a common-source configuration and applying at least one programming voltage pulse to a gate of the access transistor, the programming voltage pulse having a magnitude selected to limit programming current to a preselected value. 1. A ReRAM cell comprising:an output node coupled to a current source;a ReRAM device having an ion source end and a solid electrolyte end, the ion source end coupled to an output node; andan access transistor coupled between a first bitline associated with the memory cell and the solid electrolyte end of the ReRAM device, the access transistor having gate coupled to a wordline associated with the memory cell.2. The ReRAM cell of wherein the current source comprises a current source transistor coupled to a second bitline associated with the memory cell.3. The ReRAM cell of wherein the access transistor comprises an re-channel transistor.4. The memory cell of wherein the current source comprises at least a p-channel transistor.5. A ReRAM cell comprising:a first bitline;a second bitline;an output node;a pullup ReRAM device having an ion source end and a solid electrolyte end, the solid electrolyte end coupled to the first bitline;a first access transistor coupled between the ion source end of the pullup ReRAM device and the output node;a pulldown ReRAM device having an ion source end and a solid electrolyte end, the ion source end coupled to the second bitline; anda second access transistor coupled between the solid electrolyte end of the pulldown ReRAM device and the output node.6. The ReRAM cell of further comprising a programming transistor coupled between the output node and a wordline source node claim 5 , the programming transistor having a gate coupled to a wordline associated with the memory cell.7. The ReRAM cell of wherein:the ...

ELECTRONIC DEVICE INCLUDING MEMORY CELLS HAVING VARIABLE RESISTANCE CHARACTERISTICS

An electronic device includes a semiconductor memory. The semiconductor memory includes a stack structure including a first electrode, a second electrode, a third electrode, an insulating layer interposed between the first electrode and the second electrode, and a variable resistance layer interposed between the second electrode and the third electrode; and a selection element layer disposed over at least a part of a sidewall of the stack structure. 1. An electronic device comprising a semiconductor memory unit , the semiconductor memory unit comprising:a stack structure including a first electrode, a second electrode, a third electrode, an insulating layer interposed between the first electrode and the second electrode, and a variable resistance layer interposed between the second electrode and the third electrode; anda selection element layer disposed over at least a part of a sidewall of the stack structure so that the selection element layer selectively couples the first electrode and the second electrode.2. The electronic device according to claim 1 , wherein the selection element layer includes any one of an OTS (Ovonic Threshold Switching) material layer claim 1 , an MIEC (Mixed Ionic Electronic Conducting) material layer claim 1 , an MIT (Metal Insulator Transition) material layer claim 1 , and a tunneling insulating layer.3. The electronic device according to claim 1 , wherein the selection element layer has a band gap smaller than that of the insulating layer.4. The electronic device according to claim 1 , wherein the selection element layer switches between an insulating state and a conductive state according to a level of a voltage or current applied to the selection element layer.5. The electronic device according to claim 1 , wherein the selection element layer includes an operating portion and a remaining portion claim 1 ,wherein the operating portion of the selection element layer is adjacent to the insulating layer and selectively couples the first ...

ONE-TIME PROGRAMMABLE MEMORY DEVICES USING FinFET TECHNOLOGY

An OTP (One-Time Programmable) memory including OTP memory cells that utilize OTP elements fabricated in CMOS FinFET processes. The OTP memory cell can also include at least one selector built upon at least one fin structure that has at least one CMOS gate to divide the fin structure into at least a first and a second active region. The selector can be implemented as a MOS device, dummy-gate diode, or Schottky diode as selector such as by using different types of source/drain implants. The OTP element that can be implemented as polysilicon, silicided polysilicon, CMOS metal gate, any layers of metal as interconnect, or active region. In one embodiment, the OTP element can be a fin structure and can be built upon the same fin structure as the at least one of the selector. By using different source/drain implant schemes on the two active regions, the selector can be turned on as MOS device, MOS device and/or diode, dummy-gate diode, or Schottky diode. 1 an OTP element, the OTP element being coupled to a first supply voltage line; and', 'a selector including at least a first active region and a second active region built upon at least one fin structure divided by at least one MOS gate, both the first and second active regions residing in a common CMOS well or isolated substrate, the second active region being coupled to the OTP element, the first active region coupled to a second supply voltage line, and the at least one MOS gate coupled to a third voltage supply line,, 'a plurality of OTP memory cells, at least one of the OTP memory cells including at leastwherein the OTP element is configured to be programmable by applying voltages to the first, second, and third supply voltage lines and by turning on the selector to thereby change the OTP element into a different logic state.. A One-Time Programmable (OTP) memory, comprising: This application is a continuation of U.S. patent application Ser. No. 14/644,020, filed on Mar. 10, 2015 and entitled “One-Time Programmable ...

Memory Sense Amplifiers and Memory Verification Methods

Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time, a second input configured to receive a reference signal, modification circuitry configured to provide a data signal at the first input from the memory element having a plurality of different voltages corresponding to respective ones of different memory states of the memory cell at the different moments in time, and comparison circuitry coupled with the modification circuitry and configured to compare the data signal and the reference signal at the different moments in time and to provide an output signal indicative of the memory state of the memory cell at the different moments in time as a result of the comparison to implement a plurality of verify operations of the memory states of the memory cell at the different moments in time.

Low voltage embedded memory having cationic-based conductive oxide element

Low voltage embedded memory having cationic-based conductive oxide elements is described. For example, a material layer stack for a memory element includes a first conductive electrode. A cationic-based conductive oxide layer is disposed on the first conductive electrode. The cationic-based conductive oxide layer has a plurality of cation vacancies therein. A second electrode is disposed on the cationic-based conductive oxide layer.

Memory Sense Amplifiers and Memory Verification Methods

Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time, a second input configured to receive a reference signal, modification circuitry configured to provide a data signal at the first input from the memory element having a plurality of different voltages corresponding to respective ones of different memory states of the memory cell at the different moments in time, and comparison circuitry coupled with the modification circuitry and configured to compare the data signal and the reference signal at the different moments in time and to provide an output signal indicative of the memory state of the memory cell at the different moments in time as a result of the comparison to implement a plurality of verify operations of the memory states of the memory cell at the different moments in time.

Memory Systems and Memory Programming Methods

Memory systems and memory programming methods are described. According to one aspect, a memory system includes program circuitry configured to provide a program signal to a memory cell to program the memory cell from a first memory state to a second memory state, detection circuitry configured to detect the memory cell changing from the first memory state to the second memory state during the provision of the program signal to the memory cell to program the memory cell, and wherein the program circuitry is configured to alter the program signal as a result of the detection and to provide the altered program signal to the memory cell to continue to program the memory cell from the first memory state to the second memory state. 138-. (canceled)39. A memory system comprising:a bit line;a memory cell coupled with the bitline, and wherein the memory cell is configured to have a plurality of different memory states at different moments in time;a first voltage source configured to provide a first program signal to the bit line and the memory cell at a first moment in time to change the memory cell from a first of the memory states to a second of the memory states;a second voltage source configured to provide a second program signal to the bit line and the memory cell at a second moment in time while the memory cell is in the second memory state; andwherein the first and second program signals have different voltages and the first moment in time occurs before the second moment in time.40. The memory system of wherein the memory cell has different electrical resistances corresponding to respective ones of the different memory states.41. The memory system of wherein the memory cell has an increased electrical resistance in the second memory state compared with the electrical resistance of the memory cell in the first memory state.42. The memory system of further comprising an access transistor configured to selectively electrically couple the bit line with the memory cell.43. ...

RESISTANCE CHANGE DEVICE, MANUFACTURING METHOD FOR THE SAME, AND STORAGE APPARATUS

A resistance change device includes a first resistance change layer that occludes and discharges ions of at least one type, and resistance of the first resistance change layer, changes in accordance with an amount of the ions in such a manner that the resistance decreases when the ions are discharged and the resistance increases when the ions are occluded; a second resistance change layer that occludes and discharges the ions, and resistance of the second resistance change layer changes in accordance with the amount of the ions in such a manner that the resistance increases when the ions are discharged and the resistance decreases when the ions are occluded; and an ion conductive layer that carries the ions and is provided between the first resistance change layer and the second resistance change layer. 1. A resistance change device comprising:a first resistance change layer that occludes and discharges ions of at least one type, and resistance of the first resistance change layer changes in accordance with an amount of the ions in such a manner that the resistance decreases when the ions are discharged and the resistance increases when the ions are occluded;a second resistance change layer that occludes and discharges the ions, and resistance of the second resistance change layer changes in accordance with the amount of the ions in such a manner that the resistance increases when the ions are discharged and the resistance decreases when the ions are occluded; andan ion conductive layer that carries the ions and is provided between the first resistance change layer and the second resistance change layer.2. The resistance change device according to claim 1 ,wherein the ions discharged from the first resistance change layer pass through the Ion conductive layer to be occluded in the second resistance change layer, andthe ions discharged from the second resistance change layer pass through the ion conductive layer to be occluded in the first resistance change layer.3. ...

Nonvolatile memory device having resistance change memory layer

A nonvolatile memory device according to an embodiment includes a substrate, a source electrode structure disposed on the substrate, a channel structure disposed to be contact a sidewall surface of the source electrode structure, a resistance change memory layer disposed on a sidewall surface of the channel structure, a drain electrode structure disposed to contact the resistance change memory layer, a plurality of gate dielectric structures extending in the first direction and disposed to be spaced apart from each other in a second direction, and a plurality of gate electrode structures disposed to extend in the first direction in the plurality of the gate dielectric structure.

Memory Systems and Memory Programming Methods

Memory systems and memory programming methods are described. According to one arrangement, a memory system includes a memory array comprising a plurality of memory cells individually configured to have a plurality of different memory states, access circuitry configured to apply signals to the memory cells to program the memory cells to the different memory states, and a controller to configured to control the access circuitry to apply a first of the signals to one of the memory cells to program the one memory cell from a first memory state to a second memory state different than the first memory state, to determine that the one memory cell failed to place into the second memory state as a result of the application of the first signal, and to control the access circuitry to apply a second signal to the one memory cell to program the one memory cell from the first memory state to the second memory state as a result of the determination, wherein the first and second signals have a different electrical characteristic. 138-. (canceled)39. A memory system comprising:a memory element configured to have different electrical resistances in different memory states;circuitry configured to provide a plurality of signals to the memory element to change the electrical resistance of the memory element from a first resistance corresponding to a first of the memory states to a second resistance corresponding to a second of the memory states; andwherein the memory element has the first resistance after the provision of a first of the signals to the memory element and the electrical resistance of the memory element changes from the first resistance to the second resistance as a result of the provision of a second of the signals to the memory element after the provision of the first signal to the memory element.40. The system of wherein the second signal has an increased electrical characteristic compared with the first signal.41. The system of wherein the increased electrical ...

RRAM MEMORY CELL WITH MULTIPLE FILAMENTS

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first resistive random access memory (RRAM) element over a substrate. The first RRAM element has a first terminal and a second terminal. A second RRAM element is arranged over the substrate and has a third terminal and a fourth terminal. The third terminal is electrically coupled to the first terminal of the first RRAM element. A reading circuit is coupled to the second terminal and the fourth terminal. The reading circuit is configured to read a single data state from both a first non-zero read current received from the first RRAM element and a second non-zero read current received from the second RRAM element. 1. An integrated chip , comprising:a first resistive random access memory (RRAM) element over a substrate, wherein the first RRAM element has a first terminal and a second terminal;a second RRAM element arranged over the substrate and having a third terminal and a fourth terminal, wherein the third terminal is electrically coupled to the first terminal of the first RRAM element; anda reading circuit coupled to the second terminal and the fourth terminal, wherein the reading circuit is configured to read a single data state from both a first non-zero read current received from the first RRAM element and a second non-zero read current received from the second RRAM element.2. The integrated chip of claim 1 , further comprising:a control device having a fifth terminal and a sixth terminal, the sixth terminal being coupled to the first terminal and the third terminal, wherein the first non-zero read current and the second non-zero read current are respectively proportional to a voltage applied to the fifth terminal of the control device.3. The integrated chip of claim 1 , wherein the first RRAM element comprises a data storage structure disposed between a bottom electrode and a top electrode claim 1 , the bottom electrode having a top surface that ...

Cross-Point Memory Cells, Non-Volatile Memory Arrays, Methods of Reading a Memory Cell, Methods of Programming a Memory Cell, Methods of Writing to and Reading from a Memory Cell, and Computer Systems

Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, and methods of writing to and reading from a memory cell are described. In one embodiment, a cross-point memory cell includes a word line extending in a first direction, a bit line extending in a second direction different from the first direction, the bit line and the word line crossing without physically contacting each other, and a capacitor formed between the word line and the bit line where such cross. The capacitor comprises a dielectric material configured to prevent DC current from flowing from the word line to the bit line and from the bit line to the word line. 141-. (canceled)42. A memory cell comprising:a first electrode;a second electrode;semiconductive material intermediate the first and second electrodes and configured to have different capacitance states at different moments in time corresponding to different ones of a plurality of programmed states of the memory cell; andwherein the semiconductive material has different dielectric thicknesses corresponding to the different capacitance states at the different moments in time.43. The memory cell of further comprising a dielectric material intermediate one of the first and second electrodes and the semiconductive material claim 42 , and wherein the dielectric material has a substantially constant capacitance while the memory cell is in the different programmed states.44. The memory cell of wherein a region of the semiconductive material comprises different concentrations of a plurality of mobile dopants while the memory cell is in the different programmed states.45. The memory cell of wherein the dielectric material comprises barrier material which is impervious to movement of the mobile dopants from the semiconductive material to the barrier material.46. The memory cell of wherein a region of the semiconductive material is electrically conductive while the memory cell is in one ...

Memory Devices and Memory Operational Methods

Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state. 120-. (canceled)21. A memory system comprising:a plurality of tiles individually comprising a plurality of sub-tiles, wherein the sub-tiles individually comprise a plurality of memory cells;a plurality of access circuits coupled with respective ones of the tiles and wherein the access circuits are individually configured to provide the memory cells of the respective tiles in different memory states; andwherein one of the access circuits provides the memory cells of one of the sub-tiles of a respective one of the tiles in one of the memory states during a common write operation.22. The memory system of wherein the sub-tiles individually comprise a common conductor coupled with all of the memory cells of the individual sub-tile.23. The memory system of wherein the common write operation is a block erase write operation.24. The memory system of wherein another of the access circuits simultaneously provides the memory cells of another of the sub-tiles of a respective other of the tiles in the one memory state during the common write operation.25. The memory system of wherein an individual one of the access circuits is coupled with a plurality of the tiles.26. A memory writing method comprising:providing a plurality of sub-tiles individually having a common conductor which is coupled with a plurality of ...

Cross-Point Memory Cells, Non-Volatile Memory Arrays, Methods of Reading a Memory Cell, Methods of Programming a Memory Cell, Methods of Writing to and Reading from a Memory Cell, and Computer Systems

Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, and methods of writing to and reading from a memory cell are described. In one embodiment, a cross-point memory cell includes a word line extending in a first direction, a bit line extending in a second direction different from the first direction, the bit line and the word line crossing without physically contacting each other, and a capacitor formed between the word line and the bit line where such cross. The capacitor comprises a dielectric material configured to prevent DC current from flowing from the word line to the bit line and from the bit line to the word line. 1: A cross-point memory cell comprising:a word line extending in a first direction;a bit line extending in a second direction different from the first direction, the bit line and the word line crossing without physically contacting each other; anda capacitor capable of being repeatedly programmed to at least two different capacitance states formed between the word line and the bit line where such cross, the capacitor comprising a capacitor dielectric material configured to prevent DC current from flowing from the word line to the bit line and from the bit line to the word line.2: The memory cell of wherein:the capacitor comprises a crystalline semiconductive metal-containing mass that is overall stoichiometrically cation deficient to form mobile cation vacancies in a space lattice; andthe capacitor dielectric material comprises a barrier dielectric material received between the word line and the bit line in physical touching contact with the crystalline semiconductive metal-containing mass and that is impervious to movement of the mobile cation vacancies from said mass into the barrier dielectric material, the semiconductive mass and the barrier dielectric material being of different composition relative one another which is at least characterized by at least one different ...

ARRAY VOLTAGE REGULATING TECHNIQUE TO ENABLE DATA OPERATIONS ON LARGE MEMORY ARRAYS WITH RESISTIVE MEMORY ELEMENTS

Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to preserve states of memory elements in association with data operations using variable access signal magnitudes for other memory elements, such as implemented in third dimensional memory technology. In some embodiments, a memory device can include a cross-point array with resistive memory elements. An access signal generator can modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. A tracking signal generator is configured to track the modified magnitude of the signal and to apply a tracking signal to other resistive memory elements associated with other subsets of bit lines, the tracking signal having a magnitude at a differential amount from the modified magnitude of the signal. 1. (canceled)2. A memory device comprising:an array of memory elements including discrete re-writable non-volatile two-terminal resistive memory elements disposed between word lines and bit lines, the array of memory elements comprising a first slice of memory elements located at a first position and a second slice of memory elements located at a second position; anda slice-rolling controller configured to generate and apply a first access signal, having a first modified magnitude, to the first slice of memory elements during a first interval of time and generate and apply a second access signal, having a second modified magnitude, to the second slice of memory elements during a second interval of time subsequent to the first interval of time, the second position being farther from the slice-rolling controller than the first position, and the second modified magnitude being greater than the first modified magnitude.3. The memory device of claim 2 , wherein the slice-rolling controller is configured to receive the first ...

PROGRAMMABLE INTERPOSERS FOR ELECTRICALLY CONNECTING INTEGRATED CIRCUITS

Programmable interposers for connecting integrated circuits, methods for programming programmable interposers, and integrated circuit packaging are provided. The programmable interposers are electrically reconfigurable to allow custom system-in-package (SiP) operation and configuration, field configurability, and functional obfuscation for secure integrated circuits fabricated in non-trusted environments. The programmable interposer includes, in one implementation, an interposer substrate and a programmable metallization cell (PMC) switch. The PMC switch is formed on the interposer substrate and is coupled between a signal input and a signal output. The PMC switch is electrically configurable between a high resistance state and a low resistance state. 1. A programmable interposer for electrically connecting integrated circuits , the programmable interposer comprising:an interposer substrate; anda programmable metallization cell (PMC) switch formed on the interposer substrate and coupled between a signal input and a signal output, wherein the PMC switch is electrically configurable between a high resistance state and a low resistance state.2. The programmable interposer of claim 1 , further comprising a configuration controller coupled to the PMC switch and configured to set the PMC switch in the low resistance state or the high resistance state.3. The programmable interposer of claim 2 , wherein the PMC switch is a first PMC switch claim 2 , wherein the programmable interposer further comprising a second PMC switch claim 2 , wherein the configuration controller is further configured to set the second PMC switch in the low resistance state or the high resistance state.4. The programmable interposer of claim 1 , wherein the PMC switch includes a PMC element having:an insulating material,an ion conductor formed at least partially within the insulating material,an oxidizable electrode positioned proximate to the ion conductor, andan indifferent electrode positioned ...

CONDUCTIVE BRIDGING RANDOM ACCESS MEMORY FORMED USING SELECTIVE BARRIER METAL REMOVAL

A method for manufacturing a semiconductor memory device includes depositing a bottom metal line layer on a dielectric layer, and patterning the bottom metal line layer into a plurality of bottom metal lines spaced apart from each other. In the method, a plurality of switching element dielectric portions are formed on respective ones of the plurality of bottom metal lines, and a top metal line layer is deposited on the plurality of switching element dielectric portions. The method further includes patterning the top metal line layer into a plurality of top metal lines spaced apart from each other. The plurality of top metal lines are oriented perpendicular to the plurality of bottom metal lines. 1. A method for manufacturing a semiconductor memory device , comprising:depositing a bottom metal line layer on a dielectric layer;patterning the bottom metal line layer into a plurality of bottom metal lines spaced apart from each other;forming a plurality of switching element dielectric portions on respective ones of the plurality of bottom metal lines;depositing a top metal line layer on the plurality of switching element dielectric portions; andpatterning the top metal line layer into a plurality of top metal lines spaced apart from each other;wherein the plurality of top metal lines are oriented perpendicular to the plurality of bottom metal lines.2. The method according to claim 1 , wherein the plurality of top metal lines claim 1 , the plurality of bottom metal lines claim 1 , and the plurality of switching element dielectric portions are parts of a memory cell array having a cross-point structure.3. The method according to claim 1 , wherein the switching element dielectric portions are components of respective conductive bridging random access memory devices.4. The method according to claim 3 , wherein the switching element dielectric portions comprise at least one of amorphous silicon claim 3 , amorphous silicon germanium claim 3 , silicon oxide claim 3 , hafnium ...

MEMORY DEVICE INCLUDING NONVOLATILE MEMORY CELL

A memory device may include nonvolatile memory cells. A first memory cell of the nonvolatile memory cells may have a first resistance value in a first state and a second memory cell of the nonvolatile memory cells may have a second resistance value less than the first resistance value in a second state. A third memory cell of the nonvolatile memory cells may have a third resistance value less than the first resistance value and greater than the second resistance value in a third state, and a fourth memory cell of the nonvolatile memory cells may have a fourth resistance value less than the third resistance value and greater than the second resistance value in a fourth state. 1. A memory device including nonvolatile memory cells , each of which comprises:an active pattern including first to fourth regions successively arranged in one direction;a first gate structure crossing the active pattern on the second region and including a first gate electrode and a first insulating layer; anda second gate structure crossing the active pattern on the fourth region and including a second gate electrode and a second insulating layer, a first voltage is applied to the second gate electrode when the second insulating layer is in a first state such that a current that passes through the second region becomes a first current,', 'the first voltage is applied to the second gate electrode when the second insulating layer is in a second state such that a current that passes through the second region becomes a second current,', 'the first voltage is applied to the second gate electrode when the second insulating layer is in a third state such that a current that passes through the second region becomes a third current,', 'the second current and the third current are higher than the first current, and', 'the second current is different from the third current., 'wherein the nonvolatile memory cell is configured such that2. The memory device of claim 1 , wherein if the nonvolatile memory ...

Memory Systems and Memory Programming Methods

Memory systems and memory programming methods are described. In one arrangement, a memory system includes a memory cell configured to have a plurality of different memory states, an access circuit coupled with the memory cell and configured to provide a first signal to a memory element of the memory cell to program the memory cell from a first memory state to a second memory state, and a current source coupled with the memory cell and configured to generate a second signal which is provided to the memory element of the memory cell after the first signal to complete programming of the memory cell from the first memory state to the second memory state. 1. A memory system comprising:a memory cell configured to have a plurality of different memory states;an access circuit coupled with the memory cell and configured to provide a first signal to a memory element of the memory cell to program the memory cell from a first memory state to a second memory state; anda current source coupled with the memory cell and configured to generate a second signal which is provided to the memory element of the memory cell after the first signal to complete programming of the memory cell from the first memory state to the second memory state.2. The system of wherein the memory element has different electrical resistances corresponding to the first and second memory states.3. The system of wherein the memory element comprises a dielectric material intermediate a plurality of electrodes claim 2 , and wherein the memory element has a high electrical resistance in the first memory state and the provision of the first signal to the memory element initially forms an electrically conductive structure electrically intermediate the electrodes providing the memory element with a low electrical resistance corresponding to the second memory state.4. The system of wherein the second signal is provided to the memory element after the electrically conductive structure is formed.5. The system of wherein ...

RESISTANCE CHANGE MEMORY AND FORMING METHOD OF THE RESISTANCE CHANGE DEVICE

A resistance change memory has a resistance change device and a control circuit for controlling application of voltage to the resistance change device. The resistance change device has a first electrode, a second electrode, and a resistance change layer interposed between the first electrode and the second electrode. A material for the second electrode includes one of members selected from the group consisting of W, Ti, Ta, and nitrides thereof. During forming of the resistance change device, the control circuit performs a second forming treatment succeeding to a first forming treatment. The first forming treatment includes application of voltage such that the potential of the first electrode is higher than the potential of the second electrode. The second forming treatment includes application of voltage such that the potential of the second electrode is higher than the potential of the first electrode. 1. A resistance change memory comprising:a resistance change device including a first electrode, a second electrode, and a resistance change layer interposed between the first electrode and the second electrode; anda control circuit configured to perform a first forming treatment to form an initial first portion of a filament between the first electrode and the second electrode and then a second forming treatment to form an initial second portion of the filament.2. The resistance change memory according to claim 1 , wherein the initial second portion electrically connects the initial first portion to the second electrode.3. The resistance change memory according to claim 1 , wherein the filament formed by the initial first portion and the initial second portion electrically connects the first electrode to the second electrode.4. The resistance change memory according to claim 1 , wherein the first forming treatment includes application of voltage such that the potential of the first electrode is higher than the potential of the second electrode claim 1 , and the ...

CIRCUITRY AND METHODS FOR PROGRAMMING RESISTIVE RANDOM ACCESS MEMORY DEVICES

A method for programming a ReRAM cell including a ReRAM device connected in series with an access transistor includes biasing the ReRAM cell with a programming potential that configures the access transistor in a common-source configuration and applying at least one programming voltage pulse to a gate of the access transistor, the programming voltage pulse having a magnitude selected to limit programming current to a preselected value. 1. A ReRAM cell comprising:an output node coupled to a current source;a ReRAM device having an ion source end and a solid electrolyte end, the ion source end coupled to an output node; andan access transistor coupled between a first bitline associated with the memory cell and the solid electrolyte end of the ReRAM device, the access transistor having gate coupled to a wordline associated with the memory cell.2. The ReRAM cell of wherein the current source comprises a current source transistor coupled to a second bitline associated with the memory cell.3. The ReRAM cell of wherein the access transistor comprises an n-channel transistor.4. The memory cell of wherein the current source comprises at least a p-channel transistor.5. A ReRAM cell comprising:a first bitline;a second bitline;an output node;a pullup ReRAM device having an ion source end and a solid electrolyte end, the solid electrolyte end coupled to the first bitline;a first access transistor coupled between the ion source end of the pullup ReRAM device and the output node;a pulldown ReRAM device having an ion source end and a solid electrolyte end, the ion source end coupled to the second bitline; anda second access transistor coupled between the solid electrolyte end of the pulldown ReRAM device and the output node.6. The ReRAM cell of further comprising a programming transistor coupled between the output node and a wordline source node claim 5 , the programming transistor having a gate coupled to a wordline associated with the memory cell.7. The ReRAM cell of wherein:the ...

HYBRID RESISTIVE MEMORY

The present disclosure relates to a memory circuit comprising: a transistor layer; a plurality of first memory elements positioned in a first level above the transistor layer; and a plurality of filament switching resistive memory elements positioned in a second level higher than the first level. 1. A memory circuit comprising:a transistor layer;a plurality of first memory elements positioned in a first level above the transistor layer;a plurality of filament switching resistive memory elements positioned in a second level higher than the first level, wherein the first memory elements and the filament switching resistive memory elements are positioned in different levels; andat least one first interconnection level separating the first and second levels.2. The memory circuit of claim 1 , wherein the plurality of first memory elements comprises:one or more phase change memory elements; and/orone or more ferroelectric tunnel junction memory elements; and/orone or more oxide random access memory elements.3. The memory circuit of claim 1 , wherein the plurality of filament switching resistive memory elements comprises one or more conductive bridging memory elements and/or one or more oxide random access memory elements.4. The memory circuit of claim 1 , wherein the first level is positioned directly on the transistor layer.5. The memory circuit of claim 1 , wherein the first memory elements and the filament switching resistive memory elements are positioned in different levels of a same region of the device.6. The memory circuit of claim 5 , wherein the at least one first interconnection level is dedicated to the routing of the first memory elements claim 5 , the memory circuit further comprising at least one second interconnection level separating the first and second levels or being higher than the second level claim 5 , dedicated to the routing of the filament switching resistive memory elements.7. The memory circuit of claim 1 , wherein the plurality of first memory ...

DRIFT AND NOISE CORRECTED MEMRISTIVE DEVICE

A memristor memory device comprises a memristive memory cell, an input terminal, an output terminal, and a gate terminal. The input terminal and the output terminal are directly attached to the memristive memory cell, and the gate terminal is electrically isolated from the memristive memory cell. The gate terminal is configured for receiving an electrical signal for a volatile modulation of a conductance of the memristive memory cell, by which a correction of non-ideal conductance modulations of the memristor memory device is achieved. 1. A memristor memory device comprising a memristive memory cell , the memristor memory device comprising:an input terminal;an output terminal; anda gate terminal; the input terminal and the output terminal are directly attached to the memristive memory cell;', 'the gate terminal is electrically isolated from the memristive memory cell; and', 'the gate terminal is configured for receiving an electrical signal for a volatile modulation of a conductance of the memristive memory cell to correct non-ideal conductance modulations of the memristor memory device., 'wherein2. The memristor memory device according to claim 1 , wherein the non-ideal conductance modulations comprise at least one of a temporal resistance drift and a temperature-induced disturbance of the resistance.3. The memristor memory device according to claim 1 , wherein the memristive memory cell comprises a phase change material or a filamentary electrolyte.4. The memristor memory device according to claim 1 , wherein:the memristor memory device comprises a plurality of the memristive memory cells; andthe gate terminal is common to the plurality of the memristive memory cells.5. The memristor memory device according to claim 4 , wherein the plurality of memristive memory devices is arranged in a crossbar array building a memristor memory unit.6. The memristor memory device according to claim 1 , further comprising:a temperature effect control unit which output is adapted ...

Semiconductor memory device

A semiconductor memory device includes a substrate, a stacked body comprising a plurality of first conductors extending in a first direction away from a surface of the substrate and spaced from one another in second and third directions intersecting the first direction and each other, the stacked body having a first region and a second region, a plurality of second conductors extending in the second direction, a plurality of third conductors extending in the third, each third conductor connected to a first end, in the second direction, of a plurality of second conductors in the first region, a plurality of fourth connectors extending in the first direction, each fourth conductor connected to the plurality of second conductors in the second region, and memory cells located between adjacent surfaces of the first and second conductors in the first region.

Memory component, memory device, and method of operating memory device

A memory component including first and second electrodes with a memory layer therebetween, the memory layer having first and second memory layers, the first memory layer containing aluminum and a chalcogen element of tellurium, the second memory layer between the first memory layer and the first electrode and containing an aluminum oxide and at least one of a transition metal oxide and a transition metal oxynitride having a lower resistance than the aluminum oxide.

Write method for writing to variable resistance nonvolatile memory element and variable resistance nonvolatile memory device

A write method for writing to a variable resistance nonvolatile memory element, comprising applying a set of strong recovery-voltage pulses at least once to the variable resistance nonvolatile memory element when it is determined that the resistance state of the variable resistance nonvolatile memory element fails to change to a second resistance state, remaining in a first resistance state, the set of strong recovery-voltage pulses including pulses: (1) a first strong recovery-voltage pulse which has a greater amplitude than a normal second voltage for changing the resistance state to the first resistance state, and has the same polarity as the second voltage; and (2) a second strong recovery-voltage pulse which follows the first strong recovery-voltage pulse and has a longer pulse width than the pulse width of the normal first voltage for changing the resistance state to the second resistance state, and has the same polarity as the first voltage.

SWITCHING ATOMIC TRANSISTOR AND METHOD FOR OPERATING SAME

Disclosed are a switching atomic transistor with a diffusion barrier layer and a method of operating the same. By introducing a diffusion barrier layer in an intermediate layer having a resistance change characteristic, it is possible to minimize variation in the entire number of ions in the intermediate layer involved in operation of the switching atomic transistor or to eliminate the variation to maintain stable operation of the switching atomic transistor. In addition, it is possible to stably implement a multi-level cell of a switching atomic transistor capable of storing more information without increasing the number of memory cells. Also, disclosed are a vertical atomic transistor with a diffusion barrier layer and a method of operating the same. By producing an ion channel layer in a vertical structure, it is possible to significantly increase transistor integration. 1. A switching atomic transistor comprising:a substrate;a source electrode formed on the substrate;a drain electrode formed on the substrate and spaced apart from the source electrode;an intermediate layer formed over the source electrode or the drain electrode to fill the space between the source electrode and the drain electrode;a diffusion barrier layer formed on the intermediate layer to prevent diffusion of ions of the intermediate layer; andan ion source gate electrode formed on the diffusion barrier layer to supply ions to the intermediate layer upon an initial operation.2. The switching atomic transistor of claim 1 , wherein the source electrode or the drain electrode is formed of at least one material selected from a group consisting of p-doped Si claim 1 , n-doped Si claim 1 , WN claim 1 , AlN claim 1 , TaN claim 1 , HfN claim 1 , TiN claim 1 , titanium oxynitride (TiON) claim 1 , and tungsten oxynitride (WON).3. The switching atomic transistor of claim 1 , wherein the intermediate layer is formed of at least one material selected from a group consisting of CuInS claim 1 , CuInSe claim ...

ACCESS SIGNAL ADJUSTMENT CIRCUITS AND METHODS FOR MEMORY CELLS IN A CROSS-POINT ARRAY

Systems, integrated circuits, and methods to utilize access signals to facilitate memory operations in scaled arrays of memory elements are described. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements and line driver. The line driver can be configured to access a resistive memory element in the cross-point array. 1. (canceled)2. A memory device comprising:a first two-terminal cross-point array comprising a plurality of two-terminal memory elements arranged in a plurality of slices; anda target magnitude generator coupled to the first two-terminal cross-point array, the target magnitude generator comprising a second array of memory elements configured to condition an input voltage received at a first terminal of the second array to generate, at a second terminal of the second array, a target voltage magnitude for an access signal applied to one of the plurality of slices of the first two-terminal cross-point array.3. The memory device of claim 2 , wherein each of the plurality of slices represents a group of the two-terminal memory elements formed by at least one word line.4. The memory device of claim 3 , further comprising:a word line voltage generator coupled to the two-terminal cross-point array, the word line voltage generator comprising the target magnitude generator and a positional voltage adjuster.5. The memory device of claim 4 , further comprising:a word line driver coupled between the word line voltage generator and the at least one word line.6. The memory device of claim 2 , wherein the second array of memory elements comprises a first word line coupled to the first terminal and to a first memory element in the second array.7. The memory device of claim 6 , wherein the second array of memory elements comprises a first bit line coupled to the second terminal and to the first memory element in the second array.8. The memory device of claim 7 , wherein the first memory element in the ...

METHOD FOR PROGRAMMING SWITCHING ELEMENT

In order to realize a switching element that is highly reliable and can be highly integrated, in a method for programming a switching element of the present invention, programming of the switching element is performed by increasing or decreasing a resistance value R of a resistive-change film by applying a first pulse voltage to a first electrode or a second electrode, a measurement of the resistance value R is performed, verification in which it is determined whether or not the measured resistance value R is equal to a desired value is performed, and reprogramming of the switching element is performed by applying a second pulse voltage whose polarity is the same as that of the first pulse voltage to the same electrode to which the first pulse voltage is applied on the basis of the resistance value R when the resistance value R is not equal to the desired value. 1. A method for programming a switching element including a first electrode , a second electrode , and a resistive-change film which is provided between the first electrode and the second electrode and whose resistance value R increases or decreases according to an electric potential difference between the first electrode and the second electrode , in whichprogramming of the switching element is performed by increasing or decreasing the resistance value R of the resistive-change film by applying a first pulse voltage to the first electrode or the second electrode,a measurement of the resistance value R is performed and verification in which it is determined whether or not the measured resistance value R is equal to a desired value is performed, andreprogramming of the switching element is performed by applying a second pulse voltage whose polarity is the same as that of the first pulse voltage to the same electrode to which the first pulse voltage is applied on the basis of the resistance value R when the resistance value R is not equal to the desired value.2. The method for programming a switching element ...

MEMORY CIRCUIT AND METHOD OF PROGRAMMING MEMORY CIRCUIT

A method includes applying a first voltage setting to a memory cell for a first period of time in response to a command for programming a first logical state to the memory cell, obtaining a first stored logical state of the memory cell after the applying the first voltage setting operation, and if the first stored logical state differs from the first logical state, applying a second voltage setting to the memory cell. 1. A method , comprising:applying a first voltage setting to a memory cell for a first period of time in response to a command for programming a first logical state to the memory cell;obtaining a first stored logical state of the memory cell after the applying the first voltage setting operation; and 'applying a second voltage setting to the memory cell.', 'if the first stored logical state differs from the first logical state2. The method of claim 1 , further comprising: 'reporting a successful programming attempt.', 'if the first stored logical state is the same as the first logical state3. The method of claim 1 , further comprising:performing a first retrial comprising applying the first voltage setting to the memory cell for the first period of time.4. The method of claim 3 , further comprising:obtaining a second stored logical state of the memory cell after the performing the first retrial operation; applying the second voltage setting to the memory cell; and', 'performing a second retrial comprising applying the first voltage setting to the memory cell for the first period of time., 'if the second stored logical state differs from the first logical state5. The method of claim 1 , wherein applying the second voltage setting to the memory cell operation comprises applying the second voltage setting to the memory cell for a second period of time claim 1 , the first period of time being different from the second period of time.6. The method of claim 1 , whereinapplying the first voltage setting to the memory cell comprises applying a first voltage ...

SELF-TERMINATING WRITE FOR A MEMORY CELL

A programmable impedance based memory device includes a programmable impedance element, read circuitry configured to determine a resistance of the programmable impedance element during a write operation; and, write circuitry configured to change the resistance of the programmable impedance element as part of performing the write operation, wherein the write circuitry is further configured to terminate the write operation based on the read circuitry detecting that the resistance of the programmable impedance element has passed a threshold value. 1. A method of performing write operations on a programmable impedance element based memory cell , the method comprising:performing a write operation to change a resistance of a programmable impedance element;monitoring the resistance of the programmable impedance element during the write operation;in response to detecting that the resistance of the programmable impedance element has passed a threshold value, terminating the write operation.2. The method of claim 1 , wherein detecting that the resistance of the programmable impedance element has passed the threshold value comprises comparing the resistance of the programmable impedance element to the threshold value.3. The method of claim 1 , wherein the write operation comprises a write high operation claim 1 , and wherein detecting that the resistance of the programmable impedance element has passed the threshold value comprises detecting that the resistance of the programmable impedance element has passed a predefined resistance threshold value that defines a high state.4. The method of claim 1 , wherein the write operation comprises a write low operation claim 1 , and wherein detecting that the resistance of the programmable impedance element has passed the threshold value comprises detecting that the resistance of the programmable impedance element has passed a predefined resistance threshold value that defines a low state.5. The method of claim 1 , wherein performing ...

Reduced diffusion in metal electrode for two-terminal memory

Providing for two-terminal memory that mitigates diffusion of external material therein is described herein. In some embodiments, a two-terminal memory cell can comprise an electrode layer. The electrode layer can be at least in part permeable to ionically or chemically reactive material, such as oxygen or the like. The two-terminal memory can further comprise a diffusion mitigation material disposed between the electrode layer and external material. This diffusion mitigation material can be selected to mitigate or prevent diffusion of the undesired element(s) or compound(s), to mitigate or avoid exposure of such element(s) or compound(s) to the electrode layer. Accordingly, degradation of the two-terminal memory as a result of contact with the undesired element(s) or compound(s) can be mitigated by various disclosed embodiments.

Three-Dimensional Array of Re-Programmable Non-Volatile Memory Elements Having Vertical Bit Lines and a Single-Sided Word Line Architecture

A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A single-sided word line architecture provides a word line exclusively for each row of memory elements instead of sharing one word line between two rows of memory elements thereby avoids linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling between adjacent rows of local bit lines and therefore leakage currents beyond the word line.

Finfet Structures for Programmable Resistive Devices

A programmable resistive memory having a plurality of programmable resistive cells. At least one of the programmable resistive cell includes a programmable resistive element and at least one selector. The selector can be built in at least one fin structure and at least one active region divided by at least one MOS gate into a first active region and a second active region. The first active region can have a first type of dopant to provide a first terminal of the selector. The second active region can have a first or a second type of dopant to provide a second terminal of the selector. The MOS gate can provide a third terminal of the selector. The first terminal of the selector can be coupled to the first terminal of the programmable resistive element. The programmable resistive element can be programmed by conducting current flowing through the selector to thereby change the resistance state. 1. A programmable resistive memory , comprising: a programmable resistive element; and', 'at least one selector built in at least one fin structure coupled to the resistive element, the at least one fin structure being a semiconductor structure and including at least an active region divided by at least one MOS gate into a first active region with a first type of dopant to provide a first terminal of the selector, and a second active region with the first type or a second type of dopant to provide a second terminal of the selector, the at least one MOS gate providing a third terminal of the selector, both active regions being fabricated from sources or drains of CMOS devices and residing in a common CMOS well or an isolated substrate, the first terminal of the selector coupled to a first terminal of the programmable resistive element, the programmable resistive element being programmable by conducting a current flowing through the programmable resistive element and the selector., 'a plurality of programmable resistive cells, at least one of the programmable resistive cell ...

VARIABLE RESISTANCE MEMORY DEVICE

A variable resistance memory device includes lower conductive lines on a substrate, upper conductive lines on the lower conductive lines to cross the lower conductive lines, and memory cells between the lower conductive lines and the upper conductive lines. The lower conductive lines are extended in a first direction and are spaced apart from each other in a second direction crossing the first direction. Each of the lower conductive lines include a first line portion extended in the first direction, a second line portion offset from the first line portion in the second direction and extended in the first direction, and a connecting portion connecting the first line portion to the second line portion. 1. A variable resistance memory device , comprising:lower conductive lines on a substrate, the lower conductive lines being extended in a first direction and being spaced apart from each other in a second direction crossing the first direction;upper conductive lines on the lower conductive lines to cross the lower conductive lines; andmemory cells between the lower conductive lines and the upper conductive lines, a first line portion extended in the first direction;', 'a second line portion offset from the first line portion in the second direction and extended in the first direction; and', 'a connecting portion connecting the first line portion to the second line portion., 'wherein each of the lower conductive lines includes'}2. The variable resistance memory device of claim 1 , wherein the connecting portions of the lower conductive lines are aligned with each other in a third direction crossing the first and second directions.3. The variable resistance memory device of claim 2 , wherein the memory cells are at intersection points between the first line portion and the upper conductive lines and between the second line portion and the upper conductive lines.4. The variable resistance memory device of claim 2 , further comprising upper contacts claim 2 , which are ...

Silicon Compatible Tin-based Cationic Filamentary Device

The present disclosure describes devices, systems, and methods of manufacture that relate to cationic filamentary (CF) devices. An example CF device includes a first electrode, a second electrode, and an insulator. The first electrode includes an electrochemically inert material. The second electrode includes an electrochemically active material. The electrochemically active material includes Sn, An insulator disposed between the first electrode and the second electrode such that a positive voltage applied to the second electrode with respect to the first electrode causes formation of a conductive filament in the insulator extending from the second electrode toward the first electrode. 1. A cationic filamentary (CF) device comprising:a first electrode, wherein the first electrode comprises an electrochemically inert material;a second electrode, wherein the second electrode comprises an electrochemically active material, wherein the electrochemically active material comprises Sn; andan insulator disposed between the first electrode and the second electrode such that a positive voltage applied to the second electrode with respect to the first electrode causes formation of a conductive filament in the insulator extending from the second electrode toward the first electrode.2. The CF device according to claim 1 , wherein the electrochemically inert material comprises at least one of: W claim 1 , Pt claim 1 , Au claim 1 , Mo claim 1 , Co claim 1 , Cr claim 1 , Al claim 1 , Ru claim 1 , Ir claim 1 , Sc claim 1 , doped poly-Si claim 1 , TiW claim 1 , or TaN claim 1 , indium tin oxide (ITO) claim 1 , fluorine doped tin oxide (FTO) claim 1 , and doped zinc oxide.3. The CF device according to claim 1 , wherein Sn is present as a component of an alloy or compound.4. The CF device according to claim 1 , wherein the insulator comprises at least one of: HfO claim 1 , TaO claim 1 , SiO claim 1 , WO claim 1 , MoO claim 1 , ZrO claim 1 , ZnO claim 1 , SrTiO claim 1 , TiO claim 1 , ...

APPARATUS FOR LOW POWER WRITE AND READ OPERATIONS FOR RESISTIVE MEMORY

Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected. 1. An apparatus comprising:a resistive memory cell coupled to a bit line and a select line;a first pass-gate coupled to the bit line;a second pass-gate coupled to the select line; anda multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates according to logic level of the input data.2. The apparatus of claim 1 , wherein the multiplexer to receive at least two inputs of different pulse widths.3. The apparatus of further comprises logic to adjust pulse widths of the at least two inputs.4. The apparatus of claim 2 , wherein the at least two inputs are first and second write enable pulses claim 2 , the first write enable pulse for controlling duration of writing a logical high to the resistive memory claim 2 , and the second write enable pulse for controlling duration of writing a logical low to the resistive memory.5. The apparatus of claim 1 , wherein the resistive memory is at least one of:STT-MRAM;ReRAM; orCBRAM.6. The apparatus of further ...

RRAM, and Methods of Storing and Retrieving Information for RRAM

Some embodiments include methods of storing and retrieving data for an RRAM array. The array is subdivided into a plurality of memory bits, with each memory bit having at least two memory cells. A memory bit is programmed by simultaneously changing resistive states of all memory cells within the memory bit. The memory bit is read by determining summed current through all memory cells within the memory bit. Some embodiments include RRAM having a plurality of memory cells. Each of the memory cells is uniquely addressed through a bitline/wordline combination. Memory bits contain multiple memory cells coupled together, with the coupled memory cells within each memory bit being in the same resistive state as one another. 1. Resistive random access memory , comprising:a plurality of memory cells comprising programmable material; the programmable material having selectively interchangeable resistive states; each of the memory cells being uniquely addressed through a bitline/wordline combination; andmemory bits comprising multiple memory cells coupled together; the coupled memory cells within each memory bit being in the same resistive state as one another.2. The resistive random access memory of wherein the memory bits comprise paired memory cells; and wherein the paired memory cells of memory bits are addressed by paired wordlines and individual bitlines.3. The resistive random access memory of wherein the memory bits comprise paired memory cells; and wherein the paired memory cells of memory bits are addressed by paired bitlines and individual wordlines.4. The resistive random access memory of comprising more than two coupled memory cells in each memory bit.5. The resistive random access memory of wherein the resistive random access memory comprises phase change memory.6. The resistive random access memory of wherein the resistive random access memory comprises multivalent metal oxide.7. The resistive random access memory of wherein the resistive random access memory ...

RRAM, and Methods of Storing and Retrieving Information for RRAM

Some embodiments include methods of storing and retrieving data for an RRAM array. The array is subdivided into a plurality of memory bits, with each memory bit having at least two memory cells. A memory bit is programmed by simultaneously changing resistive states of all memory cells within the memory bit. The memory bit is read by determining summed current through all memory cells within the memory bit. Some embodiments include RRAM having a plurality of memory cells. Each of the memory cells is uniquely addressed through a bitline/wordline combination. Memory bits contain multiple memory cells coupled together, with the coupled memory cells within each memory bit being in the same resistive state as one another. 1. A method of storing and retrieving data for a resistive random access memory array , comprising:subdividing the resistive random access memory array into a plurality of memory bits, each memory bit comprising at least two memory cells;programming a memory bit by substantially simultaneously changing resistive states of all memory cells within the memory bit; andreading the memory bit by determining summed current through all memory cells within the memory bit.2. The method of wherein the memory cells of a memory bit are read simultaneously.3. The method of wherein the memory cells of a memory bit are not read simultaneously.4. The method of wherein each memory bit comprises two memory cells; wherein each memory cell is uniquely addressed by the combination of a wordline and a bitline; and wherein the memory cells of memory bits are addressed by paired wordlines and individual bitlines.5. The method of wherein each memory bit comprises two memory cells; wherein each memory cell is uniquely addressed by the combination of a wordline and a bitline; and wherein the memory cells of memory bits are addressed by paired bitlines and individual wordlines.6. The method of wherein the resistive random access memory comprises phase change memory.7. The method of ...

Nonvolatile Resistive Memory Device and Manufacturing Method Thereof

A nonvolatile resistive switching memory comprising an insulating substrate, a lower electrode, a lower graphene barrier layer, a resistive switching functional layer, an upper graphene barrier layer, and an upper electrode, wherein the lower and/or the upper graphene barrier layer is/are capable of preventing the metal ions/atoms in the lower/upper metal electrode from diffusing into the resistive switching functional layer under an applied electric field. According to the nonvolatile resistive switching memory device of the present invention and manufacturing method thereof, a monolayer or multilayer graphene film as a metal ions/atoms barrier layer is inserted between the upper/lower metal electrode and the resistive switching functional layer, which is capable of preventing the metal ions/atoms in the lower/upper metal electrode from diffusing into the resistive switching functional layer during the programming or erasing process of the resistive switching device, thereby improving the reliability of the device.

Selector device for two-terminal memory

Solid-state memory having a non-linear current-voltage (I-V) response is provided. By way of example, the solid-state memory can be a selector device. The selector device can be formed in series with a non-volatile memory device via a monolithic fabrication process. Further, the selector device can provide a substantially non-linear I-V response suitable to mitigate leakage current for the non-volatile memory device. In various disclosed embodiments, the series combination of the selector device and the non-volatile memory device can serve as one of a set of memory cells in a 1-transistor, many-resistor resistive memory cell array.

CONDUCTIVE BRIDGING RANDOM ACCESS MEMORY FORMED USING SELECTIVE BARRIER METAL REMOVAL

A method for manufacturing a semiconductor memory device includes depositing a bottom metal line layer on a dielectric layer, and patterning the bottom metal line layer into a plurality of bottom metal lines spaced apart from each other. In the method, a plurality of switching element dielectric portions are formed on respective ones of the plurality of bottom metal lines, and a top metal line layer is deposited on the plurality of switching element dielectric portions. The method further includes patterning the top metal line layer into a plurality of top metal lines spaced apart from each other. The plurality of top metal lines are oriented perpendicular to the plurality of bottom metal lines. 1. A semiconductor memory device , comprising:a plurality of bottom metal lines spaced apart from each other and disposed on a dielectric layer;a plurality of switching element dielectric portions disposed on respective ones of the plurality of bottom metal lines;a barrier metal layer disposed on outer portions of the plurality of switching element dielectric portions to define an opening therebetween; anda plurality of top metal lines spaced apart from each other and disposed on the plurality of switching element dielectric portions and in the opening;wherein the plurality of top metal lines are oriented perpendicular to the plurality of bottom metal lines.2. The semiconductor memory device according to claim 1 , wherein the plurality of top metal lines claim 1 , the plurality of bottom metal lines claim 1 , and the plurality of switching element dielectric portions are parts of a memory cell array having a cross-point structure.3. The semiconductor memory device according to claim 1 , wherein the switching element dielectric portions are components of respective conductive bridging random access memory devices.4. The semiconductor memory device according to claim 3 , wherein the switching element dielectric portions comprise at least one of amorphous silicon claim 3 , ...

Thermal dispersion layer in programmable metallization cell

Some embodiments relate to a method for manufacturing a memory device. The method includes forming a bottom electrode over a substrate. A heat dispersion layer is formed over the bottom electrode. A dielectric layer is formed over the heat dispersion layer. A top electrode is formed over the dielectric layer. The heat dispersion layer comprises a first dielectric material.

THIN FILMS PRINTED WITH CHALCOGENIDE GLASS INKS

A device formation method may include printing a chalcogenide glass ink onto a surface to form a chalcogenide glass layer, where the chalcogenide glass ink comprises chalcogenide glass and a fluid medium. The method may further include sintering the chalcogenide glass layer at a first temperature for a first duration. The method may also include annealing the chalcogenide glass layer at a second temperature for a second duration. A device may include a substrate and a printed chalcogenide glass layer on the substrate, where the printed chalcogenide glass layer includes annealed chalcogenide glass, and where the printed chalcogenide glass layer is free from cracks. 1. A device formation method comprising:printing a chalcogenide glass ink onto a surface to form a chalcogenide glass layer, wherein the chalcogenide glass ink comprises chalcogenide glass and a fluid medium;sintering the chalcogenide glass layer at a first temperature for a first duration; andannealing the chalcogenide glass layer at a second temperature for a second duration.2. The method of claim 1 , wherein the chalcogenide glass is in the form of nanoparticles suspended in the fluid medium.3. The method of claim 2 , wherein the nanoparticles have a diameter that is less than or equal to 100 nm.4. The method of claim 1 , wherein the fluid medium is an amine claim 1 , and wherein the chalcogenide glass is dissolved in the amine.5. The method of claim 1 , wherein the first temperature is 80° C. claim 1 , wherein the first duration is at least 2 days claim 1 , wherein the second temperature is 300° C. claim 1 , and wherein the second duration is at least 15 minutes.6. The method of claim 1 , wherein the chalcogenide glass layer is free from cracks after the annealing.7. The method of claim 1 , wherein a transmission spectrum of the chalcogenide glass layer is unchanged by the annealing and an annealing temperature is less than a glass transition temperature of the chalcogenide glass.8. The method of claim ...

TRENCH FORMATION SCHEME FOR PROGRAMMABLE METALLIZATION CELL TO PREVENT METAL REDEPOSIT

Some embodiments relate to a method for forming a memory device. The method includes forming a lower dielectric layer over a conductive wire. A stack of memory layers is formed within the lower dielectric layer and over the conductive wire. The stack of memory layers comprises a top electrode, a bottom electrode, and a data storage layer between the top electrode and the bottom electrode. A removal process is performed on the stack of memory layers to define a programmable metallization cell that comprises the top electrode, the bottom electrode, and the data storage layer. The programmable metallization cell comprises a central region and a peripheral region that extends upwardly from the central region. A top surface of the programmable metallization cell and a top surface of the lower dielectric layer are coplanar. 1. A method for forming a memory device , the method comprising:forming a lower dielectric layer over a conductive wire;forming a stack of memory layers within the lower dielectric layer and over the conductive wire, wherein the stack of memory layers comprises a top electrode, a bottom electrode, and a data storage layer between the top electrode and the bottom electrode; andperforming a removal process on the stack of memory layers to define a programmable metallization cell that comprises the top electrode, the bottom electrode, and the data storage layer, wherein the programmable metallization cell comprises a central region and a peripheral region that extends upwardly from the central region, and wherein a top surface of the programmable metallization cell and a top surface of the lower dielectric layer are coplanar.2. The method of claim 1 , wherein the removal process includes performing a planarization process into the stack of memory layers until the top surface of the lower dielectric layer is reached.3. The method of claim 2 , wherein the planarization process comprises one or more slurry for a non-selective chemical-mechanical ...

Temperature Based Logic Profile for Variable Resistance Memory Cells

A data storage device may generally be constructed and operated with at least one variable resistance memory cell having a first logic state threshold that is replaced with a second logic state threshold by a controller. The first and second logic states respectively corresponding to a predicted resistance shift that is based upon an operating temperature profile.

Semiconductor memory device and method of controlling data thereof

A control circuit is configured to perform a state determination operation to sense voltages of a plurality of first wiring lines, the voltages changing based on current flowing from the first wiring lines to a plurality of second wiring lines via a plurality of variable resistive elements. Then, the control circuit is configured to adjust voltages to be applied to the first and second wiring lines in a reset operation or a set operation based on the voltages of the first wiring lines sensed in the state determination operation.

ACCESS SIGNAL ADJUSTMENT CIRCUITS AND METHODS FOR MEMORY CELLS IN A CROSS-POINT ARRAY

Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to generate access signals to facilitate memory operations in scaled arrays of memory elements, such as memory implemented in third dimensional memory technology formed BEOL directly on top of a FEOL substrate that includes data access circuitry. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements disposed among word lines and subsets of bit lines, and an access signal generator. The access signal generator can be configured to modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. The modified magnitude can be a function of the position of the resistive memory element in the cross-point array. 1. A non-volatile memory device , comprising:a three dimensional array including at least two slices of two-terminal resistive memory elements (MEs), each ME being configured to retain stored data in an absence of electrical power and the at least two slices each extending in at least one of XY, YZ, or XZ planes of the three dimensional array; andan access signal generator configured to generate a modified access signal by modifying a magnitude of an access signal configured to access a selected ME based at least in part on a position of the selected ME in the array.2. The non-volatile memory device of claim 1 , wherein the access signal generator is further configured to adjust the magnitude of the access signal as a function of a distance between the position of the selected ME and the access signal generator.3. The non-volatile memory device of claim 1 , wherein the access signal generator is further configured to adjust the magnitude of the access signal to compensate for a deviation from a target magnitude.4. The non-volatile memory ...

DEVICE FOR SELECTING A STORAGE CELL

A device for selecting a storage cell, includes a first electrode, a second electrode and an oxide layer disposed between the first electrode and the second electrode, wherein the oxide layer is doped with a first element from column IV of the periodic table. 1. A device for selecting a memory cell , the device comprising a first electrode , a second electrode and an oxide layer arranged between the first electrode and the second electrode , wherein the oxide layer is doped with a first element from column IVA of the periodic table.2. The device according to claim 1 , wherein the oxide layer is entirely doped with the first element.3. The device according to claim 1 , wherein the first element is present in the oxide layer at an atomic concentration comprised between 0.5% and 3%.4. The device according to claim 1 , wherein the oxide layer comprises a material among the following: hafnium oxide claim 1 , tantalum oxide.5. The device according to claim 1 , wherein the oxide layer is doped with silicon.6. An elementary cell comprising a device according to and a resistive non-volatile memory cell connected in series with the device.7. The elementary cell according to claim 6 , wherein the memory cell is a memory cell of OxRAM claim 6 , CBRAM or PCRAM type.8. The elementary cell according to claim 5 , wherein the memory cell comprises a first electrode claim 5 , a second electrode and an oxide layer arranged between the first electrode and the second electrode claim 5 , the memory cell and the device each having a voltage for forming a switching zone in their respective oxide layer claim 5 , the oxide layer of the device being doped in such a way that the forming voltage of the device is greater than the forming voltage of the memory cell.9. The elementary cell according to claim 8 , wherein the first element is present in the oxide layer of the device at an atomic concentration comprised between 0.5% and 2%.10. The elementary cell according to claim 8 , wherein the ...

Temperature compensation of conductive bridge memory arrays

Methods for operating a semiconductor memory array including dynamically adjusting control line voltages (e.g., unselected word line or unselected bit line voltages) based on one or more array conditions associated with the semiconductor memory array are described. The one or more array conditions may include a temperature associated with the semiconductor memory array or a particular number of write cycles associated with the semiconductor memory array. In some embodiments, an intermediate voltage is generated based on the one or more array conditions and applied to the unselected word lines and the unselected bit lines of the semiconductor memory array. The one or more intermediate voltages may be generated such that a first voltage difference across unselected memory cells sharing a selected word line is different from a second voltage difference across other unselected memory cells sharing a selected bit line based on the one or more array conditions.

INTERCALATED METAL/DIELECTRIC STRUCTURE FOR NONVOLATILE MEMORY DEVICES

Some embodiments relate to an integrated chip including a memory device. The memory device includes a bottom electrode disposed over a semiconductor substrate. An upper electrode is disposed over the bottom electrode. An intercalated metal/dielectric structure is sandwiched between the bottom electrode and the upper electrode. The intercalated metal/dielectric structure comprises a lower dielectric layer over the bottom electrode, an upper dielectric layer over the lower dielectric lower, and a first metal layer separating the upper dielectric layer from the lower dielectric layer. 1. An integrated chip including a memory device , the memory device comprising:a bottom electrode disposed over a semiconductor substrate;an upper electrode disposed over the bottom electrode; andan intercalated metal/dielectric structure sandwiched between the bottom electrode and the upper electrode, the intercalated metal/dielectric structure comprising a lower dielectric layer over the bottom electrode, an upper dielectric layer over the lower dielectric layer, and a first metal layer separating the upper dielectric layer from the lower dielectric layer.2. The integrated chip of claim 1 , wherein when the memory device is in a first state claim 1 , a lower conductive filament extends from the bottom electrode through the lower dielectric layer and to the first metal layer claim 1 , and an upper conductive filament extends from the first metal layer through the upper dielectric layer and to the upper electrode.3. The integrated chip of claim 2 , wherein when the memory device is in a second state claim 2 , at least a portion of the lower conductive filament is removed or broken so the lower dielectric layer separates the bottom electrode from the first metal layer claim 2 , and/or at least a portion of the upper conductive filament is removed or broken so the upper dielectric layer separates the first metal layer from the upper electrode.4. The integrated chip of claim 1 , wherein the ...

Memory Cells, Memory Systems, and Memory Programming Methods

Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.

Integrated circuit system with non-volatile memory stress suppression and method of manufacture thereof

An integrated circuit system, and a method of manufacture thereof, including: an integrated circuit die; a non-volatile memory cell in the integrated circuit die and having a bit line for reading a data condition state of the non-volatile memory cell; and a voltage clamp in the integrated circuit die, the voltage clamp having a semiconductor switch connected to the bit line for reducing voltage excursions on the bit line.

Method for Operating a Conductive Bridging Memory Device

A method is disclosed for operating a Conductive Bridge Random Access Memory (CBRAM) device that includes an electrolyte element sandwiched between a cation supply top electrode and a bottom electrode. The method comprises conditioning the CBRAM device by applying a forming current pulse having a pulse width (t) of 100 ns or less and a pulse amplitude (I) of 10 uA or less, and when programming, setting the conditioned CBRAM device to a Low Resistance State (LRS) by applying a set current pulse having a pulse width (t) of 100 ns or less and a pulse amplitude (I) equal to or larger than the forming current pulse amplitude (I). 1. A method for operating a memory comprising at least one Conductive Bridge Random Access Memory (CBRAM) device , the at least one CBRAM device comprising an electrolyte element sandwiched between a cation supply top electrode and an inert bottom electrode , the method comprising:{'sub': 'f', 'conditioning the at least one CBRAM device by applying a forming current pulse having a pulse amplitude (I) of 10 uA or less.'}2. The method of claim 1 , wherein the pulse amplitude (I) is 1 uA or less.3. The method of claim 2 , wherein the forming current pulse has a pulse width (t) of 100 ns or less.4. The method of claim 1 , wherein the memory comprises an array of the CBRAM devices claim 1 , whereby the CBRAM devices in the array are conditioned in parallel.5. The method of claim 1 , further comprising setting the conditioned at least one CBRAM device to a Low Resistance State (LRS) by applying a set current pulse having a pulse width (t) of 100 ns or less claim 1 , and a current pulse amplitude (I) equal to or higher than the forming current pulse amplitude (I).6. The method claim 5 , wherein the set current pulse amplitude (I) is above 10 uA.7. The method claim 5 , wherein the set current pulse amplitude (I) is less than the forming current pulse amplitude (I).8. The method of claim 5 , further comprising determining the set current pulse amplitude ...