One-Die Flotox-Based Combo Non-Volatile Memory

A memory access apparatus that controls access to at least one memory array has an array of programmable comparison cells that retain a programmed pass code and compare it with an access pass code. When there is a match between the access pass code and the programmed pass code, the memory access apparatus generates a match signal for allowing access to the at least one memory array. If there is no match, the data within the at least one memory array may be corrupted or destroyed. Each nonvolatile comparison cell has a pair of series connected charge retaining transistors. The programmed pass code is stored in the charge retaining transistors. Primary and complementary query pass codes are applied to the charge retaining transistors and are logically compared with the stored pass code and based on the programmed threshold voltage levels determine if the query pass code is correct.

Method and apparatus for management of over-erasure in NAND-based NOR-type flash memory

A method and apparatus for operating an array block of dual charge retaining transistor NOR flash memory cells by erasing the dual charge retaining transistor NOR flash memory cells to set their threshold voltage levels to prevent leakage current from corrupting data during a read operation. Erasure of the array block of NOR flash memory cells begins by selecting one of block section of the array block and strongly and deeply erasing, over-erase verifying, and programming iteratively until the charge retaining transistors have their threshold voltages between the lower voltage limit and the upper voltage limit of the first program state. Other block sections are iteratively selected and erased, over-erase verified, and programmed repeatedly until the charge retaining transistors have their threshold voltages between the lower voltage limit and the upper voltage limit of the first program state until the entire block has been erased and reprogrammed to a positive threshold level.

Nonvolatile programmable logic switch

An aspect of the present embodiment, there is provided a nonvolatile programmable logic switch including a first memory cell transistor, a second memory cell transistor, a pass transistor and a first substrate electrode applying a substrate voltage to the pass transistor, wherein a writing voltage is applied to the first wiring, a first voltage is applied to one of a second wiring and a third wiring and a second voltage which is lower than the first voltage is applied to the other of the second wiring and the third wiring, and the first substrate voltage which is higher than the second voltage and lower than the first voltage is applied to a well of the pass transistor, when data is written into the first memory cell transistor or the second memory cell transistor.

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

A nonvolatile semiconductor memory device includes: forming a stacked body by alternately stacking a plurality of interlayer insulating films and a plurality of control gate electrodes; forming a through-hole extending in a stacking direction in the stacked body; etching a portion of the interlayer insulating film facing the through-hole via the through-hole to remove the portion; forming a removed portion; forming a first insulating film on inner faces of the through-hole and the portion in which the interlayer insulating films are removed; forming a floating gate electrode in the portion in which the interlayer insulating films are removed; forming a second insulating film so as to cover a portion of the floating gate electrode facing the through-hole; and burying a semiconductor pillar in the through-hole. 1. A nonvolatile semiconductor memory device comprising:a stacked body in which a plurality of interlayer insulating films and a plurality of control gate electrodes are alternately stacked and a through-hole extending in a stacking direction is formed;a semiconductor pillar buried in the through-hole;a floating gate electrode provided between the control gate electrodes;a first insulating film provided between the semiconductor pillar and the floating gate electrode, and the control gate electrodes; anda second insulating film provided between the semiconductor pillar and the floating gate electrode.2. The device according to claim 1 , wherein a diameter of the through-hole is larger than a thickness of each of the interlayer insulating films.3. The device according to claim 1 , wherein the floating gate electrode has a circular shape surrounding the semiconductor pillar.4. The device according to claim 1 , wherein the floating gate electrode is formed of silicon.5. The device according to claim 1 , wherein the control gate electrodes are formed of a metal or silicon doped with an impurity.6. The device according to claim 1 , wherein the semiconductor pillar ...

Methods and Apparatus for Non-Volatile Memory Cells

Non-volatile memory cells and methods. In an apparatus, an array of non-volatile storage cells formed in a portion of a semiconductor substrate includes a first storage cell having a first bit cell and a second bit cell; a second storage cell having a third bit cell and a fourth bit cell; and a column multiplexer coupled to a plurality of column lines, selected ones of the column lines coupled to a first source/drain terminal of the first and the second storage cell and coupled to a second source/drain terminal of the first and second storage cell, the column multiplexer coupling a voltage to one of the column lines connected to the first storage cell corresponding to the data, and coupling a voltage to one of the column lines connected to the second storage cell corresponding to the complementary data. Methods for operating the non-volatile memory cells are disclosed.

Erasable programmable non-volatile memory

An erasable programmable non-volatile memory includes a first select transistor, a first floating gate transistor, a second select transistor and a second floating gate transistor. A select gate and a first source/drain terminal of the first select transistor receive a first select gate voltage and a first source line voltage, respectively. A first source/drain terminal and a second source/drain terminal of the first floating gate transistor are connected with a second source/drain terminal of the first select transistor and a first bit line voltage, respectively. A select gate and a first source/drain terminal of the second select transistor receive a second select gate voltage and a second source line voltage, respectively. A first source/drain terminal and a second source/drain terminal of the second floating gate transistor are connected with the second source/drain terminal of the second select transistor and a second bit line voltage, respectively.

STACKED NANOSHEET FIELD EFFECT TRANSISTOR FLOATING-GATE EEPROM CELL AND ARRAY

Semiconductor device, memory arrays, and methods of forming a memory cell include or utilize one or more memory cells. The memory cell(s) include a first nanosheet transistor connected to a first terminal, a second nanosheet transistor located on top of the first nanosheet transistor and connected in parallel to the first nanosheet transistor and connected to a second terminal, where the first and second nanosheet transistors share a common floating gate and a common output terminal, and an access transistor connected in series to the common output terminal and a low voltage terminal, the access transistor configured to trigger hot-carrier injection to the common floating gate to change a voltage of the common floating gate. 1. A semiconductor device , comprising:a first nanosheet transistor connected to a first terminal;a second nanosheet transistor located on top of the first nanosheet transistor and connected in parallel to the first nanosheet transistor and connected to a second terminal, where the first and second nanosheet transistors share a common floating gate and a common output terminal; andan access transistor connected in series to the common output terminal and a low voltage terminal, the access transistor configured to trigger hot-carrier injection to the common floating gate to change a voltage of the common floating gate.2. The semiconductor device of claim 1 , wherein the first nanosheet transistor is an n-type nanosheet transistor and the second nanosheet transistor is a p-type nanosheet transistor.3. The semiconductor device of claim 2 , wherein hot-carrier injection is triggered when a voltage across one of the n-type nanosheet transistor and the p-type nanosheet transistor is about 3.0 volts.4. The semiconductor device of claim 1 , wherein a voltage of the common floating gate determines a logical state of the semiconductor device.5. The semiconductor device of claim 1 , wherein the first nanosheet transistor includes a first low injection- ...

Data storage with data randomizer in multiple operating modes

Methods of operating a memory include programming a particular portion of a data state to a memory cell with a data randomizer in a first operating mode, and programming a remaining portion of the data state to the memory cell with the data randomizer in a second operating mode different than the first operating mode.

MIXED SIGNAL NEUROMORPHIC COMPUTING WITH NONVOLATILE MEMORY DEVICES

Building blocks for implementing Vector-by-Matrix Multiplication (VMM) are implemented with analog circuitry including non-volatile memory devices (flash transistors) and using in-memory computation. In one example, improved performance and more accurate VMM is achieved in arrays including multi-gate flash transistors when computation uses a control gate or the combination of control gate and word line (instead of using the word line alone). In another example, very fast weight programming of the arrays is achieved using a novel programming protocol. In yet another example, higher density and faster array programming is achieved when the gate(s) responsible for erasing devices, or the source line, are re-routed across different rows, e.g., in a zigzag form. In yet another embodiment a neural network is provided with nonlinear synaptic weights implemented with nonvolatile memory devices. 1. An array of flash transistors , comprising: a source (S),', 'a drain (D),', 'a channel between the source and the drain;', 'a floating gate disposed over a portion of the channel, the floating gate controlling a conductivity of the portion in response to an amount of charge (electrons or holes) stored on the floating gate; and', 'an erase gate comprising a gate coupled to the floating gate so as to fully or partially erase the amount of charge stored on the floating gate;, 'a plurality of transistors disposed in an array of rows and columns, each of the transistors includingeach row comprising a plurality of blocks each including a plurality of the transistors in the row;a set of the blocks, the set comprising one of the blocks in each of a plurality of a different one of the rows; and the erase gates in the set of blocks, so that all the erase gates in the set of blocks are at a same voltage potential, or', 'the sources (or drains) in the set of blocks, so that all the sources (or drains) in the set of blocks are at a same voltage potential., 'a first line moving across the rows ...

MEMORY ARRANGEMENT

A memory arrangement having a memory cell array, wherein each column is associated with a bit line and each row is associated with a word line, wherein the columns have first columns of memory cells that store useful data, and columns of memory cells of a second column type that store prescribed verification data, wherein during a read access operation the memory cells of at least the columns of memory cells of the second column type set the associated bit line to a value that corresponds to a logic combination of the values stored by the memory cells of the column of the second column type that belong to rows of memory cells addressed during the read access operation, and a detection circuit that is configured to, during a read access operation, detect whether a bit line associated with a column of memory cells of the second column type is set to a value that corresponds to the logic combination of values stored by memory cells of the column of the second column type of memory cells and whose values belong to different rows of memory cells. 1. A memory arrangement , comprising:a memory cell array having columns and rows of memory cells, bit lines and word lines, wherein each column is associated with a bit line and each row is associated with a word line;wherein the columns of memory cells have columns of memory cells of a first column type that are configured to store useful data, and have columns of memory cells of a second column type that are configured to store prescribed verification data;wherein the memory cells of at least the columns of memory cells of the second column type are configured, and connected to the bit lines, such that during a read access operation the memory cells of a column of memory cells set the bit line associated with the column to a value that corresponds to a logic combination of the values stored by the memory cells of the column that belong to rows of memory cells addressed during the read access operation; anda detection circuit ...

3D MEMORY DEVICE INCLUDING SHARED SELECT GATE CONNECTIONS BETWEEN MEMORY BLOCKS

Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a data line, a first memory cell string including first memory cells located in different levels of the apparatus, first access lines to access the first memory cells, a first select gate coupled between the data line and the first memory cell string, a first select line to control the first select gate, a second memory cell string including second memory cells located in different levels of the apparatus, second access lines to access the second memory cells, the second access lines being electrically separated from the first access lines, a second select gate coupled between the data line and the second memory cell string, a second select line to control the second select gate, and the first select line being in electrical contact with the second select line. 1a data line;first, second, third, and fourth memory cells strings coupled to the data line;a first select line and a first additional select line associated with the first memory cell string;a second select line and a second additional select line associated with the second memory cell string;a third select line and a third additional select line associated with the third memory cell string;a fourth select line and a fourth additional select line associated with the fourth memory cell string;a first conductive connection coupled to the first and second select lines;a second conductive connection coupled to the third and fourth select lines;a third conductive connection coupled to the first additional select line and the third additional select line; anda fourth conductive connection coupled to the second additional select line and the fourth additional select line.. An apparatus comprising: This application is a continuation of U.S. application Ser. No. 16/921,613, filed Jul. 6, 2020, which is a continuation of U.S. application Ser. No. 16/228,534, filed Dec. 20, 2018, now issued as U.S. Pat. No. ...

MEMORY DEVICE CAPABLE OF IMPROVING ERASE AND PROGRAM EFFICIENCY

A memory device includes a first well, a second well, a first active area, a second active area, a third active area, a first poly layer and a second poly layer. The first well is of a first conductivity type. The second well is of a second conductivity type different from the first conductivity type. The first active area is of the second conductivity type and is formed on the first well. The second active area is of the first conductivity type and is formed on the first well and between the first active area and the second well. The third active area is of the first conductivity type and is formed on the second well. The first poly layer is formed above the first well and the second well. The second poly layer is formed above the first well. 1. A memory device comprising:a first well of a first conductivity type;a second well of a second conductivity type different from the first conductivity type;a first active area of the second conductivity type formed on the first well;a second active area of the first conductivity type formed on the first well and between the first active area and the second well;a third active area of the first conductivity type formed on the second well;a first poly layer formed above the first well and the second well; anda second poly layer formed above the first well;wherein a first overlap area of the first poly layer and the second active area is smaller than a second overlap area of the first poly layer and the third active area.2. The memory device of claim 1 , further comprising:an isolation layer formed below the first well and the second well;wherein the isolation layer comprises a buried layer of the first conductivity type, a deep well of the first conductivity type and/or a substrate of the second conductivity type.3. The memory device of claim 2 , further comprising:a substrate of the second conductivity type formed below the isolation layer.4. The memory device of claim 1 , further comprising:a middle substrate layer formed ...

Charge Pump Circuit Capable of Generating Voltages in Erasing Operation, Program Operation and Read Operation

A charge pump circuit includes a power switch, a first pull-low circuit, an output pull-low circuit, a first charge pump stage and an output charge pump stage. The power switch receives an enabling signal. The first pull-low circuit and the output pull-low circuit receive a pull-low signal. The first charge pump stage includes a first boost capacitor used to receive a first phase signal, a first transfer transistor, a first gate-control transistor and a first storage capacitor used to receive a second phase signal. The output charge pump stage includes an output boost capacitor used to receive a third phase signal, an output transfer transistor and an output gate-control transistor. The charge pump circuit generates voltages in an erasing operation, a program operation and a read operation according to the enabling signal, the pull-low signal, the first phase signal, the second phase signal and the third phase signal.

Extended write modes for non-volatile static random access memory architectures having word level switches

Disclosed herein is a method of performing a non-volatile write to a memory containing a plurality of volatile memory cells grouped into words, with each volatile memory cell having at least one non-volatile memory cell associated therewith. The method includes steps of a) receiving a non-volatile write instruction including at least one address and at least one data word to be written to that at least one address, b) writing the at least one data word to the volatile memory cells of a word at the at least one address, and c) writing data from the volatile memory cells written to during step b) to the non-volatile memory cells associated to those volatile memory cells by individually addressing those non-volatile memory cells for non-volatile writing, but not writing data from other volatile memory cells to their associated non-volatile memory cells because those non-volatile memory cells are not addressed.

Memory circuit, memory unit, and signal processing circuit

A memory circuit includes a transistor having a channel in an oxide semiconductor layer, a capacitor, a first arithmetic circuit, a second arithmetic circuit, a third arithmetic circuit, and a switch. An output terminal of the first arithmetic circuit is electrically connected to an input terminal of the second arithmetic circuit. The input terminal of the second arithmetic circuit is electrically connected to an output terminal of the third arithmetic circuit via the switch. An output terminal of the second arithmetic circuit is electrically connected to an input terminal of the first arithmetic circuit. An input terminal of the first arithmetic circuit is electrically connected to one of a source and a drain of the transistor. The other of the source and the drain of the transistor is electrically connected to one of a pair of electrodes of the capacitor and to an input terminal of the third arithmetic circuit.

Ternary content addressable memory and decision generation method for the same

A TCAM comprises a plurality of first search lines, a plurality of second search lines, a plurality of memory cell strings and one or more current sensing units. The memory cell strings comprise a plurality of memory cells. Each of the memory cells is coupled to one of the first search lines and one of the second search lines. The current sensing units, coupled to the memory cell strings. In a search operation, a determination that whether any of the data stored in the memory cell strings matches a data string to be searched is made according to whether the one or more current sensing units detect current from the memory cell strings, or according to the magnitude of the current flowing out from the memory cell strings detected by the one or more current sensing units.

Content Addressable Memory Device Having Electrically Floating Body Transistor

A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data. 124-. (canceled)25. A content addressable memory array comprising a plurality of content addressable memory cells arranged in a plurality of rows and columns , wherein each said content addressable memory cell comprises:a first floating body transistor;a second floating body transistor;a third transistor; anda fourth transistor;wherein said first floating body transistor is connected to a gate of said third transistor; andwherein said second floating body transistor is connected to a gate of said fourth transistor.26. The content addressable memory array of claim 25 , wherein said first floating body transistor and said second floating body transistor store complementary data.27. The content addressable memory array of claim 25 , wherein said first floating body transistor and said second floating body transistor store the same data.28. The content addressable memory array of claim 25 , wherein said third and fourth transistors are connected in parallel.29. The content addressable memory array of claim 25 , wherein said third and fourth transistors are connected in series.31. The content addressable memory array of claim 25 , wherein said first floating body transistor and said second floating body transistor comprise a buried well region.32. The content addressable memory array of claim 25 , wherein said first floating body transistor and said second floating body transistor comprise a buried insulator region.33. The content addressable memory array of claim 25 , further comprising a third floating body transistor.34. The content addressable memory array of claim 25 , wherein said content addressable memory cell may ...

PREVENTING PARASITIC CURRENT DURING PROGRAM OPERATIONS IN MEMORY

The present disclosure includes apparatuses, methods, and systems for preventing parasitic current during program operations in memory. An embodiment includes a sense line, an access line, and a memory cell. The memory cell includes a first transistor having a floating gate and a control gate, wherein the control gate of the first transistor is coupled to the access line, and a second transistor having a control gate, wherein the control gate of the second transistor is coupled to the access line, a first node of the second transistor is coupled to the sense line, and a second node of the second transistor is coupled to the floating gate of the first transistor. The memory cell also includes a diode, or other rectifying element, coupled to the sense line and a node of the first transistor. 1. An apparatus , comprising:a sense line; and a transistor having a floating gate and a control gate; and', 'a diode coupled to the sense line and a node of the transistor., 'a memory cell, wherein the memory cell includes2. The apparatus of claim 1 , wherein:the apparatus includes an access line; andthe control gate of the transistor is coupled to the access line.3. The apparatus of claim 1 , wherein the memory cell includes an additional transistor claim 1 , wherein:a first node of the additional transistor is coupled to the sense line; anda second node of the additional transistor is coupled to the floating gate of the transistor.4. The apparatus of claim 1 , wherein:the apparatus includes an access line; andthe memory cell includes an additional transistor having a control gate, wherein the control gate of the additional transistor is coupled to the access line.5. The apparatus of claim 1 , wherein the diode is in series with the sense line and the node of the transistor.6. The apparatus of claim 1 , wherein the diode is a bipolar junction diode.7. An apparatus claim 1 , comprising:a plurality of sense lines; and a transistor having a floating gate and a control gate; and', ' ...

SEMICONDUCTOR DEVICES AND METHODS OF OPERATING THE SAME

A semiconductor device includes a source layer; a plurality of channel structures; a plurality of gate electrodes; and a common source line. At least one of the plurality of gate electrodes provides a GIDL line. For an erasing operation, an erasing voltage applied to the common source line reaches a target voltage, and, after the erasing voltage reaches the target voltage, a step increment voltage is applied to the erasing voltage, such that the erasing voltage has a voltage level higher than a voltage level of the target voltage. After the step increment voltage has been applied for a desired time period, the voltage level of the erasing voltage is decreased to the target voltage level for the remainder of the erasing operation. 1. A semiconductor device comprising:a source layer on a substrate;a plurality of channel structures on the substrate, the plurality of channel structures each including a vertical insulating layer and a vertical channel layer, the plurality of channel structures extending in a first direction perpendicular to an upper surface of the substrate; a plurality of gate electrodes on the source layer and spaced apart from each other along the first direction on a sidewall of each of the plurality of channel structures, and at least one gate electrode of the plurality of gate electrodes is configured to provide a gate-induced drain leakage (GIDL) line;a common source line penetrating through the plurality of gate electrodes, the common source line extending in the first direction and electrically connected to the source layer; and apply an erasing voltage to the common source line until the erasing voltage reaches a target voltage,', 'increase the erasing voltage to a desired step-up voltage which has a level higher than a level of the target voltage, for a desired step-up time period after the erasing voltage reaches the target voltage, and', 'reduce the erasing voltage to the target voltage after the desired step-up time period expires., 'a ...

1T1b AND 2T2b FLASH-BASED, DATA-ORIENTED EEPROM DESIGN

An one-transistor-one-bit (1T1b) Flash-based EEPROM cell is provided along with improved key operation schemes including applying a negative word line voltage and a reduced bit line voltage for perform erase operation, which drastically reduces the high voltage stress on each cell for enhancing the Program/Erase cycles while reducing cell size. An array made by the 1T1b Flash-based EEPROM cells can be operated with Half-page or Full-page divided programming and pre-charging period for each program cycle. Utilizing PGM buffer made of Vdd devices in the cell array further save silicon area. Additionally, a two-transistor-two-bit (2T2b) EEPROM cell derived from the 1T1b cell is disclosed with additional cell size reduction but with the operation of program and erase the same as that for the 1T1b cells with benefits of no process change but much enhanced storage density, superior Program/Erase endurance cycle, and capability for operating in high temperature environment. 1. An one-transistor-one-bit (1T1b) Flash-based EEPROM array circuit comprising:a 1T1b Flash-based EEPROM cell array divided into a plurality of pages, each page being laid in a row having a number of bytes in X direction, each byte including eight bits, each bit being associated with a memory cell having a triple P-well (TPW) node, a word line WL node connected to a common WL for each page in the X direction, a bit line BL node configured to connect a global BL in Y direction perpendicular to the X direction, and a source line SL node configured to connect a global SL in the Y direction, wherein the plurality of pages is arranged in the number of columns of bytes in the Y direction, each column of bytes sharing a common TPW node connected to all TPW nodes of all memory cells in the column;a decoder circuit connected to each common WL in the X direction associated with each of the plurality of pages;a low-voltage PGM buffer circuit made from PMOS and NMOS devices with power supply voltages of 3V or less ...

DETERMINING DATA STATES OF MEMORY CELLS

Methods of operating a memory include determining a voltage level of a plurality of voltage levels at which a memory cell is deemed to first activate in response to applying the to a control gate of that memory cell for each memory cell of a plurality of memory cells, determining a plurality of voltage level distributions from numbers of memory cells of a first subset of memory cells deemed to first activate at each voltage level of the plurality of voltage levels, determining a transition between a pair of voltage level distributions for each adjacent pair of voltage level distributions, and assigning a respective data state to each memory cell of a second subset of memory cells responsive to the determined voltage level at which that memory cell is deemed to first activate and respective voltage levels of the transitions for each adjacent pair of voltage level distributions. 1. A method of operating a memory , comprising:for each memory cell of a plurality of memory cells, determining a voltage level of a plurality of voltage levels at which that memory cell is deemed to first activate in response to applying the plurality of voltage levels to a control gate of that memory cell;determining a plurality of voltage level distributions from numbers of memory cells of a first subset of memory cells of the plurality of memory cells deemed to first activate at each voltage level of the plurality of voltage levels;for each adjacent pair of voltage level distributions of the plurality of voltage level distributions, determining a transition between that pair of voltage level distributions corresponding to a respective voltage level of the plurality of voltage levels;assigning a respective data state of a plurality of data states to each memory cell of a second subset of memory cells of the plurality of memory cells responsive to the determined voltage level at which that memory cell is deemed to first activate and the respective voltage levels of the transitions for each ...

Method for Forming a PN Junction and Associated Semiconductor Device

An integrated circuit includes an insulating layer overlying a semiconductor substrate. A semiconductor layer of a first conductivity type overlies the insulating layer. A plurality of projecting regions that are spaced apart from each other overly the semiconductor layer. A sequence of PN junctions are in the semiconductor layer. Each PN junction is located at an edge of an associated projecting region. Each PN junction also extends vertically from an upper surface of the semiconductor layer to the insulating layer. 1. An integrated circuit comprising:a semiconductor substrate;an insulating layer overlying the semiconductor substrate;a semiconductor layer of a first conductivity type overlying the insulating layer;a plurality of projecting regions that are spaced apart from each other overlying the semiconductor layer; anda sequence of PN junctions in the semiconductor layer, each PN junction located at an edge of an associated projecting region and vertically extending from an upper surface of the semiconductor layer to the insulating layer.2. The integrated circuit according to claim 1 , wherein the plurality of projecting regions comprises disconnected strips extending along a top surface of the semiconductor layer claim 1 , the disconnected strips being parallel to each other.3. The integrated circuit according to claim 1 , wherein the sequence of PN junctions forms a plurality of diodes claim 1 , each diode including a heavily doped region of the first conductivity type that abuts a lightly doped region of the first conductivity type that abuts a doped region of a second conductivity type.4. The integrated circuit according to claim 3 , wherein some of the diodes form a current bridge rectifier.5. The integrated circuit according to claim 4 , wherein the current bridge rectifier comprises a Graetz bridge.6. The integrated circuit according to claim 1 , wherein the sequence of PN junctions comprises first areas of a second conductivity type overdoped relative ...

SEMICONDUCTOR DEVICE

A semiconductor device includes first and second memory cells, a first word line, and a first and second bit lines, and a row control circuit. The first memory cell has a first gate electrode and a first channel having one end and another end. The second memory cell has a second gate electrode and a second channel having one end and another end. The first word line electrically connected with each of the first gate electrode and the second gate electrode. The first and second bit lines electrically connected with the first and second channels, respectively. When a threshold voltage of each of the first and second memory cells are caused to be shifted, the semiconductor device causes a first voltage between the first gate electrode and the first channel and a second voltage between the second gate electrode and the second channel to be differentiated. 1. A semiconductor device comprising;a first memory cell having a first gate electrode and a first channel having one end and another end;a second memory cell having a second gate electrode and a second channel having one end and another end;a first word line electrically connected with each of the first gate electrode and the second gate electrode;a first bit line electrically connected with the one end of the first channel;a second bit line electrically connected with the one end of the second channel;a source line electrically connected with each of the other end of the first channel and the other end of the second channel; anda row control circuit adapted to supply the first word line with a first program voltage, whereinwhen a threshold voltage of each of the first memory cell and the second memory cell is caused to be shifted, the semiconductor device causes a first voltage between the first gate electrode and the first channel and a second voltage between the second gate electrode and the second channel to be differentiated.2. The device according to claim 1 , whereina first length of the first word line between ...

SPLIT-GATE, 2-BIT NON-VOLATILE MEMORY CELL WITH ERASE GATE DISPOSED OVER WORD LINE GATE, AND METHOD OF MAKING SAME

A memory device includes a semiconductor substrate, first and second regions in the substrate having a conductivity type different than that of the substrate, with a channel region in the substrate extending between the first and second regions. The channel region is continuous between the first and second regions. A first floating gate is disposed over and insulated from a first portion of the channel region. A second floating gate is disposed over and insulated from a second portion of the channel region. A first coupling gate is disposed over and insulated from the first floating gate. A second coupling gate is disposed over and insulated from the second floating gate. A word line gate is disposed over and insulated from a third portion of the channel region between the first and second channel region portions. An erase gate is disposed over and insulated from the word line gate. 17-. (canceled)8. A method of forming a memory cell , comprising:forming a first insulation layer on a semiconductor substrate having a first conductivity type;forming a first conductive layer on the first insulation layer;forming a second insulation layer on the first conductive layer;forming a second conductive layer on the second insulation layer;forming a third insulation layer on the second conductive layer;forming a trench that extends through the third insulation layer, the second conductive layer, and the second insulation layer;forming insulation spacers along a sidewall of the trench;extending the trench through the first conductive layer between the insulation spacers;forming a word line gate in the trench, wherein the word line gate is disposed vertically over and insulated from the substrate;forming an erase gate in the trench, wherein the erase gate is disposed vertically over and insulated from the word line gate;removing portions of the second conductive layer while maintaining first and second portions of the second conductive layer as respective first and second ...

Content Addressable Memory Device Having Electrically Floating Body Transistor

A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.

Semiconductor storage device and memory system

A semiconductor storage device includes a first memory string having first, second, and third memory cells and a first select transistor, a second memory string having fourth, fifth, and sixth memory cells and a second select transistor, a third memory string having seventh, eighth, and ninth memory cells and a third select transistor, a first word line connected to gates of the first, fourth, and seventh memory cells, a second word line connected to gates of the second, fifth, and eighth memory cells, and a third word line connected to gates of the third, sixth, and ninth memory cells. A write operation for writing multi-bit data in the memory cells includes first and second write operations. In the second write operations performed through the first, second, and third word lines, respective ones of the first, fifth, and ninth memory cell are initially selected.

TWO-PART PROGRAMMING METHODS

Memory devices include control logic configured to set a first start program voltage and a first stop program voltage, to load actual first data for cells to be programmed to a level greater than or equal to a first level, and to load inhibit data for cells to be programmed to a level less than a second level. After programming the cells to be programmed to the level greater than or equal to the first level, the control logic is further configured to set a second start program voltage and a second stop program voltage, to load inhibit data for the cells programmed to the level greater than or equal to the first level, and to load actual second data for the cells to be programmed to the level less than the second level, wherein the first level is one level higher than the second level. 1. A memory device , comprising:control logic;wherein the control logic is configured to set a first start program voltage and a first stop program voltage;wherein the control logic is configured to cause the memory device to load actual first data for memory cells to be programmed to a respective level greater than or equal to a first particular level;wherein the control logic is configured to cause the memory device to load inhibit data for memory cells to be programmed to a respective level less than a second particular level;wherein the control logic is configured to cause the memory device to program the memory cells to be programmed to a respective level greater than or equal to the first particular level with the actual first data using program pulses in a first range from the first start program voltage to the first stop program voltage;wherein the control logic is configured to set a second start program voltage and a second stop program voltage;wherein the control logic is configured to cause the memory device to load inhibit data for the memory cells programmed to a respective level greater than or equal to the first particular level;wherein the control logic is configured ...

SENSING CIRCUITS OF NONVOLATILE MEMORY DEVICES AND METHODS OF OPERATING NONVOLATILE MEMORY DEVICES

A sensing circuit of nonvolatile memory device includes a precharge current generator, an adjusting transistor, and an adaptive control voltage generator. The precharge current generator connected to a sensing node and generates a precharge current provided to a bit-line of the nonvolatile memory device, in response to a precharge signal. The adjusting transistor, connected between the sensing node and a first node, adjusts an amount of the precharge current provided to the bit-line in response to a first control voltage. The adaptive control voltage generator generates a control current proportional to an operating temperature, in response to the precharge signal and a second control voltage and boosts a level of the first control voltage in proportion to the operating temperature. The second control voltage is inversely proportional to the operating temperature. 1. A sensing circuit of nonvolatile memory device , the sensing circuit comprising:a precharge current generator connected to a sensing node, the precharge current generator configured to generate a precharge current provided to a bit-line of the nonvolatile memory device, in response to a precharge signal;an adjusting transistor connected between the sensing node and a first node coupled to the bit-line, the adjusting transistor configured to adjust an amount of the precharge current provided to the bit-line in response to a first control voltage; andan adaptive control voltage generator configured to generate a control current which is proportional to an operating temperature of the nonvolatile memory device, in response to the precharge signal and a second control voltage and configured to boost a level of the first control voltage in proportion to the operating temperature, based on the control current, wherein the second control voltage is inversely proportional to the operating temperature.2. The sensing circuit of claim 1 , further comprising:a current adjusting circuit connected to the first node ...

PARALLEL-CONNECTED MERGED-FLOATING-GATE NFET-PFET EEPROM CELL AND ARRAY

A shared floating gate device, the device including an nFET, a pFET including a different material than that of the nFET, and a floating gate. 1. A shared floating gate device , the device comprising:an nFET;a pFET comprising a different material than that of the nFET; anda floating gate.2. The device of claim 1 , wherein the nFET and the pFET share the floating gate to form an electrically erasable and programmable non-volatile memory device.3. The device of claim 1 , wherein the nFET includes an nFET gate dielectric claim 1 ,wherein the pFET includes a pFET gate dielectric, andwherein the pFET gate dielectric comprises different materials.4. The device of claim 3 , wherein the different materials are selected so that a difference of energy barriers for a hot-carrier injection formed by the nFET gate dielectric and the pFET gate dielectric is 1 eV or less.5. The device of claim 1 , wherein the nFET comprises one of:{'sub': 2', '3, 'YO;'}{'sub': '2', 'ZrO; and'}{'sub': '2', 'HfO.'}7. The device of claim 1 , wherein the pFET comprises one of:{'sub': 3', '4, 'SiN;'}{'sub': 2', '3, 'YO;'}{'sub': '2', 'ZrO; and'}{'sub': '2', 'HfO.'}8. An electrically erasable programmable read-only memory (EEPROM) cell claim 1 , the cell comprising:an nFET including a source;a pFET including a drain and comprising a different material than that of the nFET;a floating gate; andan nFET access transistor including a drain connected to the source of the nFET and the drain of the pFET.9. The cell of claim 8 , wherein the nFET and the pFET share the floating gate to form an electrically programmable and erasable non-volatile memory device.10. The cell of claim 8 , wherein the nFET includes an nFET gate dielectric claim 8 ,wherein the pFET includes a pFET gate dielectric, andwherein the pFET gate dielectric comprises different materials.11. The cell of claim 10 , wherein the different materials are selected so that a difference of energy barriers for a hot-carrier injection formed by the nFET ...

CIRCUIT THAT SELECTS EPROMS INDIVIDUALLY AND IN PARALLEL

An integrated circuit including a first EPROM, a second EPROM, and a circuit. The first EPROM is configured to provide a first state and a second state. The second EPROM is configured to provide a third state and a fourth state. The circuit is configured to select the first EPROM and the second EPROM individually and in parallel with each other. 1. An integrated circuit , comprising:a first EPROM configured to provide a first state and a second state;a second EPROM configured to provide a third state and a fourth state; anda circuit configured to select the first EPROM and the second EPROM individually and in parallel with each other.2. The integrated circuit of claim 1 , wherein the first EPROM has a first channel width and the second EPROM has a second channel width that is different than the first channel width.3. The integrated circuit of claim 1 , wherein the first EPROM is a first type of EPROM and the second EPROM is a second type of EPROM that is different than the first type of EPROM.4. The integrated circuit of claim 1 , wherein the first state corresponds to a first un-programmed resistance claim 1 , the second state corresponds to a first programmed resistance claim 1 , the third state corresponds to a second un-programmed resistance claim 1 , and the fourth state corresponds to a second programmed resistance claim 1 , wherein each resistance of the first un-programmed resistance claim 1 , the first programmed resistance claim 1 , the second un-programmed resistance claim 1 , and the second programmed resistance is a different resistance value than each of the other three resistances.5. The integrated circuit of claim 4 , comprising:a third EPROM configured to provide a fifth state and a sixth state, wherein the fifth state corresponds to a third un-programmed resistance and the sixth state corresponds to a third programmed resistance and each resistance of the first un-programmed resistance, the first programmed resistance, the second un-programmed ...

Serialized neural network computing unit

A serialized neural network computing unit is disclosed. This computing unit comprises: a bit line; a memory array having a plurality of memory blocks, each memory block have one or more than one memory cells, each cell connected to the bit line; a control circuit configured to: apply a serialized input to the memory cells in a sequence such that outputs of the memory cells are produced in a sequence in response to the serialized input, wherein each of the outputs corresponds to a multiplication of the input and a weight value stored in the memory cell; and set a group of reference current levels, each having a specific current amount, for the control circuit to control the memory cells in generating respective output currents corresponding to the set of reference current levels.

FLOATING GATE OTP/MTP STRUCTURE AND METHOD FOR PRODUCING THE SAME

A method of forming a FG OTP/MTP cell with a P+ drain junction at the NCAP region and the resulting device are provided. Embodiments include forming MVPW regions laterally separated in a p-sub; forming a MVNW region in the p-sub between the MVPW regions; forming a first RX, a second RX, and a third RX in the MVPW and MVNW regions, respectively; forming a first and a second pair of floating gates separated over and perpendicular to the first and second RX and the second and third RX, respectively; forming a N+ source region between and adjacent to each FG of the first and the second pair in the second RX; and forming a pair of P+ drain regions in the second RX, each P+ drain region adjacent to a FG of the first pair and a FG of the second pair and remote from the N+ source region. 1. A method comprising:forming a first middle-voltage p-type well (MVPW) region and a second MVPW region laterally separated in a p-type substrate (p-sub);forming a middle-voltage n-type well (MVNW) region in the p-sub between and adjacent to the first MVPW region and the second MVPW region;forming a first active region (RX), a second RX, and a third RX in the first MVPW region, the MVNW region, and the second MVPW region, respectively;forming a first pair of floating gates and a second pair of floating gates laterally separated over and perpendicular to the first RX and the second RX and the second RX and the third RX, respectively;forming a n-type (N+) source region between and adjacent to each floating gate (FG) of the first pair and the second pair in the second RX; andforming a pair of p-type (P+) drain regions in the second RX, each P+ drain region adjacent to a FG of the first pair and a FG of the second pair and remote from the N+ source region.2. The method according to claim 1 , comprising forming each FG by:forming a middle-voltage (MV) gate oxide layer over portions of the first MVPW region, the first RX region, the MVNW region, the second RX region, the second MVPW region, and ...

SPLIT GATE NON-VOLATILE MEMORY (NVM) WITH IMPROVED PROGRAMMING EFFICIENCY

Device and method of forming a non-volatile memory (NVM) device are disclosed. The NVM device includes NVM cells disposed on a substrate in a device region. The NVM cell includes a floating gate (FG) with first and second FG sidewalls disposed on the substrate and an intergate dielectric layer disposed over the FG and substrate. Re-entrants are disposed at corners of the intergate dielectric which are filled by dielectric re-entrant spacers. An access gate (AG) with first and second AG sidewalls is disposed on the substrate adjacent to the FG such that the second AG sidewall is adjacent to a first FG sidewall and separated by the intergate dielectric layer and the re-entrant spacers prevent AG from filling the re-entrants. A first source/drain (S/D) region is disposed in the substrate adjacent to the first AG sidewall and a second S/D region is disposed in the substrate adjacent to the second FG sidewall. 1. A method of forming a non-volatile memory (NVM) cell comprising:providing a substrate prepared with a device region;forming a floating gate (FG) on the substrate, wherein the FG includes first and second FG sidewalls;forming an intergate dielectric layer on the substrate, wherein the intergate dielectric layer covers the FG and substrate, and the intergate dielectric layer comprises re-entrants at corners of the intergate dielectric layer respectively located at a first interface between the first FG sidewall and the substrate and at a second interface between the second FG sidewall and the substrate;forming dielectric re-entrant spacers in the re-entrants, wherein the dielectric re-entrant spacers fill the re-entrants at the corners of the intergate dielectric layer;forming an access gate (AG) on the substrate adjacent to the FG, wherein the AG includes first and second AG sidewalls, wherein the second AG sidewall is adjacent to the first FG sidewall and separated by the intergate dielectric layer, and wherein the re-entrant spacers prevent AG from filling the ...

High Density Split-Gate Memory Cell

A method of forming a memory device that includes forming on a substrate, a first insulation layer, a first conductive layer, a second insulation layer, a second conductive layer, a third insulation layer. First trenches are formed through third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer, leaving side portions of the first conductive layer exposed. A fourth insulation layer is formed at the bottom of the first trenches that extends along the exposed portions of the first conductive layer. The first trenches are filled with conductive material. Second trenches are formed through the third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer. Drain regions are formed in the substrate under the second trenches. A pair of memory cells results, with a single continuous channel region extending between drain regions for the pair of memory cells. 1. A memory device , comprising:a substrate of semiconductor material of a first conductivity type;spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions also extending in the first direction; first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending between the first and second regions,', 'a first floating gate disposed over and insulated from a first portion of the channel region adjacent to the first region,', 'a second floating gate disposed over and insulated from a second portion of the channel region adjacent to the second region,', 'an erase gate disposed over and insulated from a third portion of the channel region between the first and second channel region portions,', 'a first coupling gate disposed over and insulated ...

Integrated circuits and methods for operating integrated circuits with non-volatile memory

Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a semiconductor substrate doped with a first conductivity-determining impurity. The semiconductor substrate has formed therein a first well doped with a second conductivity-determining impurity that is different from the first conductivity-determining impurity, a second well, formed within the first well, and doped with the first conductivity-determining impurity, and a third well spaced apart from the first and second wells and doped with the first conductivity-determining impurity. The integrated circuit further includes a floating gate structure formed over the semiconductor substrate. The floating gate structure includes a first gate element disposed over the second well and being separated from the second well with a dielectric layer, a second gate element disposed over the third well and being separated from the third well with the dielectric layer, and a conductive connector.

PRE-CHARGE VOLTAGE FOR INHIBITING UNSELECTED NAND MEMORY CELL PROGRAMMING

Techniques are provided for pre-charging NAND strings during a programming operation. The NAND strings are in a block that is divided into vertical sub-blocks. During a pre-charge phase of a programming operation, an overdrive voltage is applied to some memory cells and a bypass voltage is applied to other memory cells. The overdrive voltage allows the channel of an unselected NAND string to adequately charge during the pre-charge phase. Adequate charging of the channel helps the channel voltage to boost to a sufficient level to inhibit programming of an unselected memory cell during a program phase. Thus, program disturb is prevented, or at least reduced. The technique allows, for example, programming of memory cells in a middle vertical sub-block without causing program disturb of memory cells that are not to receive programming. 1. An apparatus , comprising:a plurality of NAND strings of memory cells organized into an array, each NAND string having a first set of memory cells and a second set of memory cells, the first set between a first end of the NAND string and the second set; and apply a pre-charge voltage to the first end of an unselected NAND string during a pre-charge phase of a programming operation of a selected memory cell on a selected NAND string;', 'apply an overdrive voltage to control gates of programmed memory cells of the first set while applying a bypass voltage to a control gate of an unprogrammed memory cell of the second set and while applying the pre-charge voltage to the first end such that the pre-charge voltage charges a channel coupled to an unselected memory cell on the unselected NAND string to the pre-charge voltage, the unprogrammed memory cell positioned between the first set of memory cells and the unselected memory cell; and', 'raise the voltage at the channel of the unselected memory cell from the pre-charge voltage to an inhibit voltage during a program phase of the programming operation which applies a program voltage to a ...

Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells.

Method for driving semiconductor device and semiconductor device

To read multilevel data from a memory cell having a transistor using silicon and a transistor using an oxide semiconductor, without switching a signal for reading the multilevel data in accordance with the number of the levels of the multilevel data. The potential of the bit line is precharged, the electrical charge of the bit line is discharged via a transistor for writing data, and the potential of the bit line which is changed by the discharging is read as multilevel data. With such a structure, the potential corresponding to data held in a gate of the transistor can be read by only one-time switching of a signal for reading data.

CELL STRUCTURE AND OPERATION OF SELF-ALIGNED PMOS FLASH MEMORY

Techniques described herein generally relate to the fabrication of a P-type metal-oxide-semiconductor (PMOS) flash memory cell in a semiconductor substrate. The PMOS flash memory cell may include a P-substrate layer formed above the semiconductor substrate, a N-well formed in the P-substrate layer, a floating-gate formed above the N-well. Further, the PMOS memory cell may include a control-gate formed above the floating-gate, a select-gate formed above the N-well and extending over at least a portion over the floating-gate, a P-source formed in the N-well, and a P-Drain. The P-source is formed adjacent to the floating-gate, and the P-drain is formed adjacent to the select-gate. 1. A P-type metal-oxide-semiconductor (PMOS) flash memory cell in a semiconductor substrate , comprising:a P-substrate layer formed above the semiconductor substrate;a N-well formed in the P-substrate layer;a floating-gate formed above the N-well;a control-gate formed above the floating-gate;a select-gate formed above the N-well and extending over at least a portion over the floating-gate;a P-source formed in the N-well, wherein the P-source is formed adjacent to the floating-gate; anda P-drain formed in the N-well, wherein the P-drain is formed adjacent to the select-gate.2. The PMOS flash memory cell of claim 1 , further comprising:a word-line connected with the control-gate for applying a voltage to the control-gate;a select-line connected with the select-gate for applying a voltage to the select-gate; anda bit-line connected with the P-source for applying a voltage to the P-source.3. The PMOS flash memory cell of claim 1 , further comprising:a tunnel oxide layer formed on the N-well, wherein the tunnel oxide layer is above the N-well and below the floating-gate.4. The PMOS flash memory cell of claim 1 , wherein the PMOS flash memory cell is programmed byapplying a positive-voltage to the control-gate,applying a negative-voltage to the P-source, andopening the select-gate and the P-drain.5 ...

PARALLEL-CONNECTED MERGED-FLOATING-GATE NFET-PFET EEPROM CELL AND ARRAY

A shared floating gate device, the device including an. nFET, a pFET including a different material than that of the nFET, and a floating gate. 1. A device , comprising;an nFET;a pFET ; anda floating gate,wherein the nFET and the pFET share floating gate.2. The device of claim 1 , wherein the nFET and the pFET share the floating gate to form an electrically erasable and programmable non-volatile memory device.3. The device of claim 1 , wherein the nFET includes an nFET gate dielectric claim 1 ,wherein the pFET includes a pFET gate dielectric, andwherein the pFET gate dielectric and the nFET dielectric comprise different materials.4. The device of claim 3 , wherein the different materials are selected so that a difference of energy barriers for a hot-carrier injection formed by the nFET gate dielectric and the pFET gate dielectric is 1 eV or less.5. The device of claim 1 , wherein the nFET comprises one of:{'sub': 2', '3, 'YO;'}{'sub': '2', 'ZrO; and'}{'sub': '02', 'HfO.'}6. The device of claim 1 , wherein the pFET comprises one of:{'sub': 3', '4, 'SiN;'}{'sub': 2', '3, 'YO;'}{'sub': '2', 'ZrO; and'}{'sub': '2', 'HfO.'}7. An electrically erasable programmable read-only memory (EEPROM) cell claim 1 , the cell comprising:an nFET;a pFET; anda floating gate,wherein the NFET and the pFET share the floating gate.8. The cell of claim 7 , wherein the nFET and the pFET share the floating gate to form an electrically programmable and erasable non-volatile memory device.9. The cell of claim 7 , wherein the nFET includes an nFET gate dielectric claim 7 ,wherein the pFET includes a pFET gate dielectric, andwherein the pFET gate dielectric and the nFET dielectric comprise different materials.10. The cell of claim 9 , wherein the different materials are selected so that a difference of energy barriers for a hot-carrier injection formed by the nFET gate dielectric and pFET gate dielectric is 1 eV or less.11. The cell of claim 7 , wherein the nFET comprises one of:{'sub': 2', '3, 'YO ...

Memory cell with high endurance for multiple program operations

A memory cell includes a read transistor, a first floating gate transistor, a program transistor, a second floating gate transistor, and a common floating gate. The common floating gate is coupled to the second floating gate transistor and the first floating gate transistor. The memory cell is programmed and erased through the common floating gate on the second floating gate transistor, and is read through the first floating gate transistor and the read transistor.

Memory cell with low reading voltages

A memory cell includes a program select transistor, a program element, a read select transistor, a read element, and an erase element. The program select transistor is coupled to a program source line, a program select line, and a program control line. The program element is coupled to the second terminal of the program select transistor, a program bit line, and the program control line. The read select transistor is coupled to a read source line, a read select line, and a bias control line. The read element is coupled to the second terminal of the read select transistor, a read bit line, and the bias control line. The erase element is coupled to an erase control line. A floating gate is coupled to the erase element, the program element and the read element.

NONVOLATILE MEMORY STRUCTURE

A nonvolatile memory structure includes a first PMOS transistor and a first floating-gate transistor on a first active region in a substrate, a second PMOS transistor and a second floating-gate transistor on a second active region in the substrate, and an n-type erase region in the substrate. A source line connects with sources of the first and the second PMOS transistors. A bit line connects with drains of the first and the second floating-gate transistors. A word line connects with first and the second select gates in the first and the second PMOS transistors respectively. An erase line connects with the n-type erase region. The first floating-gate transistor includes a first floating gate with an extended portion extending on a first portion of the n-type erase region. 1. A nonvolatile memory structure , comprising:a substrate comprising a first active region, a second active region, and an n-type erase region, wherein the n-type erase region is insulated from the first active region and the second active region;a first PMOS transistor and a first floating-gate transistor on the first active region respectively, wherein the first PMOS transistor includes a first select gate, the first floating-gate transistor includes a first floating gate between the first select gate and the n-type erase region, and the first floating gate comprises an extended portion extending on a first portion of the n-type erase region;a second PMOS transistor and a second floating-gate transistor on the second active region respectively, wherein the second PMOS transistor includes a second select gate, the second floating-gate transistor includes a second floating gate between the second select gate and the n-type erase region, and the second floating gate comprises an extended portion extending on a second portion of the n-type erase region;a source line connecting with sources of the first PMOS transistor and the second PMOS transistor;a bit line connecting with drains of the first ...

VOLTAGE SWITCHING CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME

A voltage switching circuit includes: a control signal generation block configured to include a high voltage switching block which controls an electric current flowing according to a high voltage in response to a voltage level of a low voltage control signal and generates complementary high voltage control signals; and a high voltage transfer block configured to be driven according to the complementary high voltage control signals, and generate a switching signal, the voltage level of which is raised based on the high voltage so that the switching signal has substantially the same level as the high voltage. 1. A semiconductor memory apparatus comprising:a controller;a memory region including a plurality of semiconductor memory cells which are electrically coupled between a plurality of word lines and a plurality of bit lines, and configured to be controlled by the controller;a voltage providing block configured to provide a high voltage according to control signals of the controller;a row selection block including a high voltage switching block which generates a low voltage control signal by decoding an address signal according to control signals of the controller and generates complementary high voltage control signals based on the low voltage control signal and the high voltage, and configured to generate a switching signal, the voltage level of which is raised based on the complementary high voltage control signals and the high voltage so that the switching signal has substantially the same level as the high voltage; anda block switch configured to be driven by the switching signal, and transfer the high voltage to the memory region.2. The semiconductor memory apparatus according to claim 1 , wherein the row selection block comprises:a control signal generation block configured to include high voltage switches which control an electric current flowing according to the high voltage in response to the voltage level of the low voltage control signal and generate the ...

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells. 1. (canceled)2. A method for controlling a nonvolatile semiconductor memory device ,the nonvolatile semiconductor memory device comprising: a first selection gate transistor,', 'a second selection gate transistor, and', 'a plurality of serially-connected memory cells provided between the first selection gate transistor and the second selection gate transistor,, 'a memory cell array including a first memory cell connected with a first word line and capable of being programmed in one stage and storing data of one bit,', 'a second memory cell connected with a second word line and capable of being programmed in multi stages and storing data of three bits, the second memory cell being closer to the first selection gate transistor as compared with the first memory cell,', 'a third memory cell connected with a third word line and capable of being programmed in the multi stages and storing data of three bits, the third memory cell being closer to the first selection gate transistor as compared with the second memory cell, and', 'a fourth memory cell connected with a fourth word line and capable of being programmed in the multi stages and storing data of three bits, the ...

TWO-PART PROGRAMMING METHODS

Method of operating a memory include increasing respective threshold voltages of a first subset of memory cells of a plurality of memory cells to threshold voltage levels higher than a particular voltage level in response to applying a first plurality of programming pulses, and subsequently increasing respective threshold voltages of a second subset of memory cells of the plurality of memory cells to threshold voltage levels lower than the particular voltage level in response to applying a second plurality of programming pulses, wherein the first plurality of programming pulses have respective voltage levels within a first range of voltage levels, the second plurality of programming pulses have respective voltage levels within a second range of voltage levels, and a lowest voltage level of the first range of voltage levels is lower than or equal to a highest voltage level of the second range of voltage levels. 1. A method of operating a memory , comprising:increasing respective threshold voltages of a first subset of memory cells of a plurality of memory cells to threshold voltage levels higher than a particular voltage level in response to applying a first plurality of programming pulses to control gates of the plurality of memory cells, wherein the first plurality of programming pulses each have a respective voltage level within a first range of voltage levels; andafter applying the first plurality of programming pulses to the control gates of the plurality of memory cells, increasing respective threshold voltages of a second subset of memory cells of the plurality of memory cells to threshold voltage levels lower than the particular voltage level in response to applying a second plurality of programming pulses to the control gates of the plurality of memory cells, wherein the second plurality of programming pulses each have a respective voltage level within a second range of voltage levels;wherein a lowest voltage level of the first range of voltage levels is ...

METHODS OF OPERATING A MEMORY WITH REDISTRIBUTION OF RECEIVED DATA

Methods of operating a memory include receiving a plurality of digits of data for programming to a plurality of memory cells of the memory, redistributing the received plurality of digits of data in a reversible manner to generate a plurality of digits of redistributed data each corresponding to a respective memory cell of the plurality of memory cells, and for each memory cell of the plurality of memory cells, programming the corresponding digit of redistributed data for that memory cell to a first digit position of a respective data state of that memory cell, programming a second digit of data having a first data value to a second digit position of the respective data state of that memory cell, and programming a third digit of data having a second data value to a third digit position of the respective data state of that memory cell. 1. A method of operating a memory , comprising:receiving a plurality of digits of data for programming to a plurality of memory cells of the memory;redistributing the received plurality of digits of data in a reversible manner, thereby generating a plurality of digits of redistributed data, wherein each digit of redistributed data of the plurality of digits of redistributed data corresponds to a respective memory cell of the plurality of memory cells; and programming the corresponding digit of redistributed data for that memory cell to a first digit position of a respective data state of that memory cell;', 'programming a second digit of data having a first data value to a second digit position of the respective data state of that memory cell; and', 'programming a third digit of data having a second data value to a third digit position of the respective data state of that memory cell., 'for each memory cell of the plurality of memory cells2. The method of claim 1 , further comprising: 'programming a fourth digit of data having a third data value to a fourth digit position of the respective data state of that memory cell.', 'for each ...

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells. 1a cell unit including a first and a second selection gate transistor and a memory string provided between said first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; anda data write circuit operative to write data into said memory cell,wherein the number of program stages for at least one of memory cells on both ends of said memory string is lower than the number of program stages for other memory cells, andsaid data write circuit executes the first stage program to said memory cell having the number of program stages lower than the number of program stages for said other memory cells after the first stage program to said other memory cells.. A nonvolatile semiconductor memory device, comprising: This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2009-98416, filed on Apr. 14, 2009, the entire contents of which are incorporated herein by reference.The present invention relates to a nonvolatile semiconductor memory device, in particular to a NAND-type flash memory.As an electrically ...

Integrated Structure Comprising Neighboring Transistors

An integrated structure includes a first MOS transistor with a first controllable gate region overlying a first gate dielectric and a second MOS transistor neighboring the first MOS transistor and having a second controllable gate region overlying the first gate dielectric. A common conductive region overlies the first and second gate regions and is separated therefrom by a second gate dielectric. The common conductive region includes a continuous element located over a portion of the first and second gate regions and a branch extending downward from the continuous element toward the substrate as far as the first gate dielectric. The branch located between the first and second gate regions. 1. An integrated structure comprising:a substrate;a first MOS transistor overlying the substrate and comprising a first controllable gate region separated from the substrate by a first gate dielectric;a second MOS transistor neighboring the first MOS transistor and comprising a second controllable gate region separated the substrate by the first gate dielectric; anda common conductive region overlying the first and second gate regions and separated therefrom by a second gate dielectric, the common conductive region comprising a continuous element located over a portion of the first and second gate regions and a branch extending downward from the continuous element toward the substrate as far as the first gate dielectric, the branch located between the first and second gate regions and spaced from both the first and second gate regions.2. The structure according to claim 1 , wherein the first and second gate regions are aligned.3. The structure according to claim 1 , wherein orthogonal projections onto the substrate of two facing profiles of the first and second gate regions are free from rounded portions.4. The structure according to claim 1 , wherein the second gate dielectric comprises a silicon nitride layer sandwiched between two silicon dioxide layers.5. The structure ...

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells. 1. (canceled)2. A nonvolatile semiconductor memory device comprising:a cell unit including a first selection gate transistor and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and including a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; anda data write circuit operative to execute writing data to the memory cells, the writing data having one or more program stages, wherein{'sub': 1', '1', '2', '2', '1', '2, 'the memory cells include a first memory cell, to be executed an M-stage program, M=an integer of 1 or more, a second memory cell, to be executed an M-stage program, M=an integer larger than Mand being nearer to the first selection gate transistor than the first memory cell, and a third memory cell, to be executed the M-stage program and being nearer to the first selection gate transistor than the second memory cell, and'} [{'sub': 2', '2', '2', '2, 'executes the m-th stage program, m=an integer of 1 to M, to the second memory cell after execution of the m-th stage program to the third memory cell,'}, {'sub': 1', '1', ...

METHODS OF OPERATING A MEMORY WITH REDISTRIBUTION OF RECEIVED DATA

Methods of operating a memory include receiving data for programming to a plurality of memory cells of the memory, redistributing the received data in a reversible manner, programming the redistributed data to the plurality of memory cells, and programming respective second data to each memory cell of the plurality of memory cells containing the redistributed data, wherein the respective second data for any memory cell of the plurality of memory cells has a same data value as the respective second data for each remaining memory cell of the plurality of memory cells. 1. A method of operating a memory , comprising:receiving data for programming to a plurality of memory cells of the memory;redistributing the received data in a reversible manner, thereby generating redistributed data;programming the redistributed data to the plurality of memory cells; andprogramming respective second data to each memory cell of the plurality of memory cells containing the redistributed data, wherein the respective second data for any memory cell of the plurality of memory cells has a same data value as the respective second data for each remaining memory cell of the plurality of memory cells.2. The method of claim 1 , wherein programming the redistributed data to the plurality of memory cells comprises programming a respective digit of a plurality of digits of the redistributed data to each memory cell of the plurality of memory cells.3. The method of claim 2 , wherein the respective second data for any memory cell of the plurality of memory cells is configured to program that memory cell to one of two pre-selected data states of a plurality of data states regardless of a value of the respective digit of the redistributed data for that memory cell.4. The method of claim 1 , wherein the respective second data for each memory cell of the plurality of memory cells comprises one or more digits.5. The method of claim 1 , wherein programming the respective second data to any memory cell of ...

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells. 1a cell unit including a first and a second selection gate transistor and a memory string provided between said first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; anda data write circuit operative to write data into said memory cell,wherein the number of program stages for at least one of memory cells on both ends of said memory string is lower than the number of program stages for other memory cells, andsaid data write circuit executes the first stage program to said memory cell having the number of program stages lower than the number of program stages for said other memory cells after the first stage program to said other memory cells.. A nonvolatile semiconductor memory device, comprising: This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2009-98416, filed on Apr. 14, 2009, the entire contents of which are incorporated herein by reference.The present invention relates to a nonvolatile semiconductor memory device, in particular to a NAND-type flash memory.As an electrically ...

Flash Memory Cell with Dual Erase Modes for Increased Cell Endurance

An integrated circuit device may at least one memory cell configured for dual erase modes. Each memory cell may be configured to be erased via two different nodes, which may be selectively used (e.g., in any switched or alternating manner) to reduce the erase cycling at each individual node and thereby increase (e.g., double) the lifespan of the cell. For example, the device may include flash memory cells having a pair of program/erase nodes (e.g., an erase gate and a word line) formed over each respective floating gate, wherein the program/erase nodes are selectively used (e.g., in any switched or alternating manner) for the cell erase function.

SENSING CIRCUIT FOR NON-VOLATILE MEMORY

A sensing circuit includes a sensing stage. The sensing stage includes a voltage clamp, a P-type transistor and an N-type transistor. The voltage clamp receives a first power supply voltage and generates a second power supply voltage. The source terminal of the P-type transistor receives the second power supply voltage. The gate terminal of the P-type transistor receives a cell current from a selected circuit of a non-volatile memory. The drain terminal of the N-type transistor is connected with the drain terminal of the P-type transistor. The gate terminal of the N-type transistor receives a bias voltage. The source terminal of the N-type transistor receives a ground voltage. In a sensing period, the second power supply voltage from the voltage clamp is fixed and lower than the first power supply voltage. 1. A sensing circuit connected with a non-volatile memory , the sensing circuit comprising:a sensing stage comprising a voltage clamp, a first P-type transistor and a first N-type transistor, wherein an input terminal of the voltage clamp receives a first power supply voltage, an output terminal of the voltage clamp generates a second power supply voltage, a source terminal of the first P-type transistor receives the second power supply voltage, a gate terminal of the first P-type transistor receives a cell current from a selected circuit of the non-volatile memory, a drain terminal of the first N-type transistor is connected with a drain terminal of the first P-type transistor, a gate terminal of the first N-type transistor receives a first bias voltage, and a source terminal of the first N-type transistor receives a ground voltage;a reference current generator comprising a second N-type transistor, wherein a drain terminal of the second N-type transistor is connected with the gate terminal of the first P-type transistor, a gate terminal of the second N-type transistor receives a reference voltage, and a source terminal of the second N-type transistor receives ...

Three-dimensional p-i-n memory device and method reading thereof using hole current detection

A p-i-n junction structure is formed within a memory film laterally surrounded by an alternating plurality of electrically insulating layers and electrically conductive layers to provide a three-dimensional memory structure. The p-i-n junction includes a lower junction between an intrinsic semiconductor channel portion and a lower doped semiconductor portion and an upper junction between the intrinsic semiconductor channel portion and an upper doped semiconductor portion. The memory film can be subsequently formed on a sidewall of the memory opening, and the intrinsic semiconductor channel portion can be deposited on the memory opening and the lower doped semiconductor portion. The upper doped semiconductor portion can be formed above a topmost electrically conductive layer. The lower doped semiconductor portion can provide hole charge carriers for electrical current.

PRE-CHARGE VOLTAGE FOR INHIBITING UNSELECTED NAND MEMORY CELL PROGRAMMING

Techniques are provided for pre-charging NAND strings during a programming operation. The NAND strings are in a block that is divided into vertical sub-blocks. During a pre-charge phase of a programming operation, an overdrive voltage is applied to some memory cells and a bypass voltage is applied to other memory cells. The overdrive voltage allows the channel of an unselected NAND string to adequately charge during the pre-charge phase. Adequate charging of the channel helps the channel voltage to boost to a sufficient level to inhibit programming of an unselected memory cell during a program phase. Thus, program disturb is prevented, or at least reduced. The technique allows, for example, programming of memory cells in a middle vertical sub-block without causing program disturb of memory cells that are not to receive programming. 1. An apparatus , comprising: apply a pre-charge voltage to a first end of an unselected NAND string during a pre-charge phase of a programming operation of a selected memory cell on a selected NAND string connected to a selected word line, wherein the selected NAND string and the unselected NAND string reside in the first vertical sub-block and the second vertical sub-block, the first vertical sub-block is between the first end of the unselected NAND string and the second vertical sub-block;', 'apply an overdrive voltage to programmed word lines in the first vertical sub-block while applying a bypass voltage to unprogrammed word lines in the second vertical sub-block and while applying the pre-charge voltage to the first end of the unselected NAND string, the unselected NAND string having an unselected memory cell connected to the selected word line;', 'apply boost voltages to word lines in the first vertical sub-block and unselected word lines in the second vertical sub-block; and', 'apply a program voltage to the selected word line in the second vertical sub-block while applying the boost voltages to the word lines in the first ...

Method for Forming a PN Junction and Associated Semiconductor Device

A method can be used to make a semiconductor device. A number of projecting regions are formed over a first semiconductor layer that has a first conductivity type. The first semiconductor layer is located on an insulating layer that overlies a semiconductor substrate. The projecting regions are spaced apart from each other. Using the projecting regions as an implantation mask, dopants having a second conductivity type are implanted into the first semiconductor layer, so as to form a sequence of PN junctions forming diodes in the first semiconductor layer. The diodes vertically extend from an upper surface of the first semiconductor layer to the insulating layer. 1. A method of making a semiconductor device , the method comprising:forming a plurality of projecting regions over a first semiconductor layer having a first conductivity type, wherein the first semiconductor layer is located on an insulating layer overlying a semiconductor substrate, the projecting regions being spaced apart from each other; andusing the projecting regions as an implantation mask, performing a first implantation of dopants having a second conductivity type into the first semiconductor layer, so as to form a sequence of PN junctions forming diodes in the first semiconductor layer, the diodes vertically extending from an upper surface of the first semiconductor layer to the insulating layer.2. The method according to claim 1 , further comprising performing a second implantation of dopants having the first conductivity type in the first semiconductor layer claim 1 , so that each diode includes a heavily doped region of the first conductivity type that is next to a lightly doped region of the first conductivity type that is next to a doped region of the second conductivity type.3. The method according to claim 1 , further comprising performing a second implantation of dopants having the first conductivity type in the first semiconductor layer claim 1 , wherein the first and the second ...

APPARATUS FOR DETERMINING DATA STATES OF MEMORY CELLS

Memory having a controller configured to cause the memory to determine a plurality of activation voltage levels for the plurality of memory cells, determine a plurality of activation voltage level distributions based on a subset of the plurality of activation voltage levels with each of the activation voltage level distributions corresponding to a respective first subset of memory cells of a plurality of first subsets of memory cells of the plurality of memory cells, determine a plurality of transition voltage levels based on the plurality of activation voltage level distributions, and assign a respective data state of a plurality of data states to each memory cell of a second subset of memory cells of the plurality of memory cells based on the determined activation voltage of that memory cell and the determined plurality of transition voltage levels. 1. A memory , comprising:an array of memory cells comprising a plurality of memory cells; and determine a plurality of activation voltage levels for the plurality of memory cells, wherein each activation voltage level of the plurality of activation voltage levels corresponds to a minimum voltage level of a plurality of predefined voltage levels that is determined to cause a respective memory cell of the plurality of memory cells to activate in response to applying that activation voltage level to a control gate of the respective memory cell;', 'determine a plurality of activation voltage level distributions based on a subset of the plurality of activation voltage levels, wherein each activation voltage level distribution of the plurality of activation voltage level distributions corresponds to a respective first subset of memory cells of a plurality of first subsets of memory cells of the plurality of memory cells;', 'determine a plurality of transition voltage levels based on the plurality of activation voltage level distributions, wherein each transition voltage level of the plurality of transition voltage levels ...

ONE CHECK FAIL BYTE (CFBYTE) SCHEME

Various embodiments, disclosed herein, can include apparatus and methods to perform a one check failure byte (CFBYTE) scheme in programming of a memory device. In programming memory cells in which each memory cell can store multiple bits, the multiple bits being a n-tuple of bits of a set of n-tuples of bits with each n-tuple of the set associated with a level of a set of levels of threshold voltages for the memory cells. Verification of a program algorithm can be structured based on a programming algorithm that proceeds in a progressive manner by placing a threshold voltage of one level/distribution at a time. The routine of this progression can be used to perform just one failure byte check for that specific target distribution only, thus eliminating the need to check failure byte for all subsequent target distribution during every stage of program algorithm. Additional apparatus, systems, and methods are disclosed. 1. A memory system comprising:an array of memory cells, the memory cells being multiple-bit memory cells; and program selected memory cells at multiple voltage levels from a lowest voltage level to a highest voltage level;', 'after programming the selected memory cells at each voltage level other than the highest voltage level, perform failure byte checks of cells programmed at the respective programmed voltage level until such cells satisfy a byte failure criterion at such respective programmed voltage level;', 'upon determining that the byte failure criterion is satisfied at such respective programmed voltage level, program the selected memory cells at the next higher voltage level; and', 'perform a failure byte check for all programmed voltage levels., 'a controller operable to2. The memory system of claim 1 , wherein the multiple-bit memory cells are N-bit memory cells with N being an integer equal to or greater than two and the multiple voltage levels are equal to 2in number.3. The memory system of claim 1 , wherein the lowest voltage level is ...

3D MEMORY DEVICE INCLUDING SHARED SELECT GATE CONNECTIONS BETWEEN MEMORY BLOCKS

Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a data line, a first memory cell string including first memory cells located in different levels of the apparatus, first access lines to access the first memory cells, a first select gate coupled between the data line and the first memory cell string, a first select line to control the first select gate, a second memory cell string including second memory cells located in different levels of the apparatus, second access lines to access the second memory cells, the second access lines being electrically separated from the first access lines, a second select gate coupled between the data line and the second memory cell string, a second select line to control the second select gate, and the first select line being in electrical contact with the second select line. 1. (canceled)2. An apparatus comprising:data lines;first memory cell strings coupled to the data lines;second memory cell strings coupled to the data lines;first access lines associated with the first memory cell strings;second access lines associated with the second memory cell strings, the second access lines electrically separated from the first access lines;first select lines associated with the first memory cell strings, the first select lines located between the data lines and the first memory cell strings;second select lines associated with the second memory cell strings, the second select lines located between the data lines and the second memory cell strings;a first conductive connection coupled to a first select line of the first select lines and to a first select line of the second select lines; anda second conductive connection coupled to a second select line of the first select lines and to a second select of the second select lines.3. The apparatus of claim 1 , wherein each of the first select lines and the second select lines has a length in a first direction claim 1 , and each of the ...

NON-VOLATILE MEMORY (NVM) STRUCTURE USING HOT CARRIER INJECTION (HCI)

Certain aspects of the present disclosure are generally directed to non-volatile memory (NVM) and techniques for operating and fabricating NVM. Certain aspects provide a memory cell for implementing NVM. The memory cell generally includes a first semiconductor region, a second semiconductor region, and a third semiconductor region, the second semiconductor region being disposed between and having a different doping type than the first and third semiconductor regions. The memory cell also includes a fourth semiconductor region disposed adjacent to and having the same doping type as the third semiconductor region, a first front gate region disposed adjacent to the second semiconductor region, and a first floating front gate region disposed adjacent to the third semiconductor region. In certain aspects, the memory cell includes a back gate region, wherein the second semiconductor region is between the first front gate region and at least a portion of the back gate region. 1. A memory cell comprising:a first semiconductor region;a second semiconductor region;a third semiconductor region, the second semiconductor region being disposed between and having a different doping type than the first and third semiconductor regions;a fourth semiconductor region disposed adjacent to and having the same doping type as the third semiconductor region;a first front gate region disposed adjacent to the second semiconductor region;a first floating front gate region disposed adjacent to the third semiconductor region; anda back gate region, wherein the second semiconductor region is between the first front gate region and at least a portion of the back gate region.2. The memory cell of claim 1 , wherein the third semiconductor region has less doping concentration than the fourth semiconductor region.3. The memory cell of claim 1 , further comprising:a fifth semiconductor region having a different doping type than the first semiconductor region;a sixth semiconductor region;a seventh ...

TWO-PART PROGRAMMING METHODS

Memory having an array of memory cells might include control logic configured to cause the memory to inhibit memory cells of a first subset of memory cells from programming during each programming pulse of a first plurality of programming pulses and enable those memory cells for programming for at least one programming pulse of a second plurality of programming pulses, inhibit memory cells of a second subset of memory cells from programming during each programming pulse of the second plurality of programming pulses and enable those memory cells for programming for at least one programming pulse of the first plurality of programming pulses, and enable memory cells of a third subset of memory cells for programming during at least one programming pulse of the first plurality of programming pulses and during at least one programming pulse of the second plurality of programming pulses. 1. A memory , comprising:an array of memory cells; andcontrol logic; for each memory cell of a first subset of memory cells of a plurality of memory cells selected for programming during a programming operation, inhibit that memory cell from programming during each programming pulse of a first plurality of programming pulses of the programming operation and enable that memory cell for programming for at least one programming pulse of a second plurality of programming pulses of the programming operation;', 'for each memory cell of a second subset of memory cells of the plurality of memory cells, inhibit that memory cell from programming during each programming pulse of the second plurality of programming pulses and enable that memory cell for programming for at least one programming pulse of the first plurality of programming pulses; and', 'for each memory cell of a third subset of memory cells of the plurality of memory cells, enable that memory cell for programming during at least one programming pulse of the first plurality of programming pulses and during at least one programming pulse ...

Nonvolatile Memory

A nonvolatile memory includes circuits each having first control transistors, memory transistors, second control transistors and memory transistors repeatedly connected in series in sequence. Inversion layers are formed in the direction intersecting the serial direction with turning on of the control transistors. A selection circuit selects a connection of the inversion layer placed under the first control transistor and its corresponding read/write circuit. The control transistors placed on both sides adjacent to the memory transistor are turned on to perform reading. The first control transistors placed on both sides of the second control transistor as viewed from side to side are turned on to perform writing into the other of the right and left memory transistors via one of the right and left memory transistors. The selection circuit connects the read/write circuit and the inversion layer in such a manner that the same read/write circuit is used in reading and writing for the same memory transistor.

Bi-directional floating gate nonvolatile memory

A memory transistor has a pair of separate floating gates overlying end regions of a channel and a control gate that overlies the floating gates and a central region of the channel. The memory transistor effectively operates as a pair of floating gate transistors with an intervening select transistor. Each floating gate can be charged to store a distinct binary, analog, or multi-bit value. The direction of the channel current controls which floating gate receives channel hot electron injection during programming and which floating gate state is sensed during reading. A read operation biases the word line higher that the threshold voltage used to store data and compares the resulting channel to reference currents to identify a stored binary, analog, or multi-bit value. The threshold voltage range can include negative threshold voltages, which increases the available range for multi-bit-per-floating gate storage. The memory transistors can be integrated into a contactless array architecture having approximately one global bit/virtual ground line for every four floating gates along a row.

Fabricating bi-directional nonvolatile memory cells

A memory transistor having a pair of separate floating gates overlying end regions of a channel and a control gate that overlies the floating gates and a central region of the channel effectively operates as a pair of floating gate transistors with an intervening select transistor. Each floating gate can be charged to store a distinct binary, analog, or multi-bit value. An erase operation can use a negative voltage on the control and a positive voltage on an underlying well or source/drain region to cause tunneling that discharges one or both floating gates. Applying a limited current to a source/drain region during an erase operation can cause the source/drain region and a floating gate to rise together and avoid band-to-band tunneling and resulting hole injection into the floating gate.

Erasing storage nodes in a bi-directional nonvolatile memory cell

A memory transistor having a pair of separate floating gates overlying end regions of a channel and a control gate that overlies the floating gates and a central region of the channel effectively operates as a pair of floating gate transistors with an intervening select transistor. Each floating gate can be charged to store a distinct binary, analog, or multi-bit value. An erase operation can use a negative voltage on the control and a positive voltage on an underlying well or source/drain region to cause tunneling that discharges one or both floating gates. Applying a limited current to a source/drain region during an erase operation can cause the source/drain region and a floating gate to rise together and avoid band-to-band tunneling and resulting hole injection into the floating gate.

Configurable single bit/dual bits memory

A configurable memory device includes an array of configurable memory units arranged into rows and columns. The configurable memory unit includes a memory cell comprising a first storage element configured to store a first value and a second storage element configured to store a second value. The memory unit can be either a single-ended or a differential configuration. In the single-ended configuration, the stored value of each storage element is interpreted as one bit. In the differential configuration, the stored first and second values of the storage elements are interpreted as a differential single bit. An external control signal determines in which configuration the unit is in.

Semiconductor memory device and method for operating thereof

반도체 메모리 장치는 메모리 셀 어레이, 주변 회로 및 제어 로직을 포함한다. 상기 메모리 셀 어레이는 복수의 메모리 블록을 포함한다. 상기 주변 회로는 상기 복수의 메모리 블록 중 선택된 메모리 블록에 대한 리드 동작을 수행한다. 상기 제어 로직은 상기 주변 회로의 리드 동작을 제어한다. 상기 선택된 메모리 블록은 복수의 비트 라인들과 연결되고, 상기 복수의 비트 라인들은 복수의 비트 라인 그룹으로 그룹화된다. 상기 복수의 비트 라인 그룹에 대하여, 상기 주변 회로는 상이한 기준 전류를 적용하여 데이터 센싱을 수행한다. A semiconductor memory device includes an array of memory cells, peripheral circuits, and control logic. The memory cell array includes a plurality of memory blocks. The peripheral circuit performs a read operation on a selected memory block among the plurality of memory blocks. The control logic controls a read operation of the peripheral circuit. The selected memory block is connected to a plurality of bit lines, and the plurality of bit lines are grouped into a plurality of bit line groups. For the plurality of bit line groups, the peripheral circuit performs data sensing by applying different reference currents.

메모리 소자, 상기 메모리 소자를 위한 메모리 배열 및 상기 메모리 배열의 구동 방법

본 발명의 높은 집적도 메모리 배열 구조는 메모리 셀들이 정한바 대로 배열된 메모리 셀 배열 및 상기 메모리 셀 배열의 메모리 스트링을 선택하기 위한 서로 다른 문턱 전압을 갖는 선택 트랜지스터들을 포함하며, 상기 선택 트랜지스터들에 적절한 바이어스 전압을 인가하는 것에 의해서 특정 메모리 스트링들을 선택할 수 있어 인접 메모리 셀들에 의한 방해 없이 메모리 배열에 대한 동작을 진행할 수 있다. 불휘발성 메모리 소자, 메모리 배열, 플래시 메모리, 가상 접지

Non-volatile memory device

본 발명은 비휘발성 메모리 소자에 관한 것으로, 보다 자세하게는 한 개의 트랜지스터로 2 비트를 구현할 수 있고 셀프 컨버전스 이레이즈 특성을 지니는 사이드월 플로팅 게이트 소자를 사용하여 멀티 레벨 비트 노어 플래시 어레이를 구현하고 효과적으로 프로그램, 이레이즈, 리드 동작을 수행하는 비휘발성 메모리 소자에 관한 것이다. The present invention relates to a nonvolatile memory device, and more particularly, to implement a multi-level bit NOR flash array using a sidewall floating gate device that can implement two bits with one transistor and has a self-converging erase characteristic. The present invention relates to a nonvolatile memory device for performing an erase, read, and read operation. 본 발명의 상기 목적은 폴리실리콘 게이트, 한 쌍의 사이드월 플로팅 게이트, 블럭 산화막 및 소오스/드레인 영역을 포함하는 트렌지스터; 상기 폴리실리콘 게이트와 연결되며 기판에 종으로 배치되는 워드 라인; 상기 소오스 영역과 연결되며 상기 워드 라인과 수직으로 배치되는 제 1 비트 라인 및 상기 드레인 영역과 연결되며 기판에 워드 라인과 수직으로 배치되는 제 2 비트 라인을 단위 셀로 구성하는 것을 특징으로 하는 비휘발성 메모리 소자에 의해 달성된다. The object of the present invention is a transistor comprising a polysilicon gate, a pair of sidewall floating gate, a block oxide film and a source / drain region; A word line connected to the polysilicon gate and vertically disposed on a substrate; A non-volatile memory comprising a first bit line connected to the source region and disposed vertically to the word line and a second bit line connected to the drain region and disposed vertically to a word line on a substrate as a unit cell Achieved by the device. 따라서, 본 발명의 비휘발성 메모리 소자는 한 개의 트랜지스터로 2 비트를 구현할 수 있고 셀프 컨버전스 이레이즈 특성을 지니는 사이드월 플로팅 게이트 소자를 사용하여 멀티 레벨 비트 노어 플래시 어레이를 구현하고 효과적으로 프로그램, 이레이즈, 리드 동작을 수행하기 위한 셀 레이아웃을 제공함으로써 면적을 1/4수준으로 줄이고 오버 이레이즈 문제와 드레인 턴온 문제가 발생하지 않는 신뢰성 있는 소자를 제공할 수 있다. Accordingly, the nonvolatile memory device of the present invention implements a multi-level bit NOR flash array using sidewall floating gate devices capable of implementing 2 bits with one transistor and having self-converging erase characteristics, and effectively programs, erases, and By providing a cell layout for performing a read operation, the area can be reduced to a quarter level, and a reliable device can be provided ...

Nonvolatile semiconductor memory

불휘발성 반도체 메모리가 적어도 제1 및 제2 플로팅 게이트들, 제1 및 제2 제어 게이트들, 및 소스 및 드레인을 포함한다. 제1 플로팅 게이트는 반도체 기판 상에 게이트 절연막을 경유하여 형성된다. 제2 플로팅 게이트는 제1 플로팅 게이트가 없는 영역 상에 게이트 절연막을 경유하여 형성된다. 제1 제어 게이트는 제1 플로팅 게이트 상에 절연막을 경유하여 형성된다. 제2 제어 게이트는 제2 플로팅 게이트 상에 절연막을 경유하여 형성된다. 소스 및 드레인은 제1 및 제2 플로팅 게이트들을 사이에 두도록 반도체 기판 내에 형성된다. The nonvolatile semiconductor memory includes at least first and second floating gates, first and second control gates, and a source and a drain. The first floating gate is formed on the semiconductor substrate via the gate insulating film. The second floating gate is formed on the region where the first floating gate does not exist via the gate insulating film. The first control gate is formed on the first floating gate via an insulating film. The second control gate is formed on the second floating gate via the insulating film. A source and a drain are formed in the semiconductor substrate to sandwich the first and second floating gates.

Nonvolatile semiconductor memory device

Electronic device including discontinuous storage elements

一种电子器件，可包括不连续存储元件(64)，其位于沟槽(22，23)之内。该电子器件可包括具有沟槽的衬底，该沟槽具有壁和底部并且从衬底(12)的主表面延伸。该电子器件还可包括不连续存储元件，其中该不连续存储元件的一部分至少位于该沟槽之内。该电子器件可进一步包括第一栅电极，其中至少部分该不连续存储元件的一部分位于该第一栅电极和该沟槽的壁之间。该电子器件可进一步包括位于该第一栅电极和该衬底的该主表面之上的第二栅电极。

High density splitting bar memory cell

本发明公开了一种形成存储器设备的方法，该方法包括在衬底上形成第一绝缘层、第一导电层、第二绝缘层、第二导电层、第三绝缘层。第一沟槽穿过第三绝缘层、第二导电层、第二绝缘层和第一导电层形成，从而使第一导电层的侧面部分暴露。第四绝缘层形成在第一沟槽的底部处，第四绝缘层沿着第一导电层的暴露部分延伸。第一沟槽填充有导电材料。第二沟槽穿过第三绝缘层、第二导电层、第二绝缘层和第一导电层形成。漏极区形成在第二沟槽下方的衬底中。产生一对存储器单元，其中单个连续沟道区在所述对存储器单元的漏极区之间延伸。

Electrically erasable programmable read-only memory as well as forming method and erasure method thereof

一种电可擦可编程只读存储器及其形成方法、擦除方法，其中，所述电可擦可编程只读存储器，包括：半导体衬底，位于半导体衬底内具有沿第一方向排布的若干有源区；位于有源区上的字线；分别位于字线两侧的有源区上的浮栅介质层、位于浮栅介质层上的浮栅、位于浮栅上的控制栅介质层、位于控制栅介质层上的控制栅，所述浮栅的宽度大于有源区的宽度；位于字线和浮栅与控制栅之间的隔离氧化层；分别位于浮栅和控制栅的远离字线一侧的有源区内的位线掺杂区。本发明电可擦可编程只读存储器通过位线端擦除的方式，结构上改善浮栅对控制删和位线掺杂区的耦合系数，在实现按位擦写功能的同时提高擦写的性能。

Non-volatile semiconductor memory

(57)【要約】 【課題】 耐久性に優れた不揮発性半導体記憶装置を提 供する。 【解決手段】 ビット線消去動作において、セルブロッ ク１０２ｍ内の各メモリセル１m(m-2)，１m(m-1)につい てのみ消去動作を行い、同じワード線ＷＬmに接続され ているその他のメモリセル１については消去動作を行わ ないようにする場合、ビット線ＢＬm-3〜ＢＬm-1の電位 が０Ｖにされ、それ以外のビット線（非選択のビット 線）には＋１０Ｖが供給される。ワード線ＷＬmの電位 は１５Ｖにされる。また、ワード線ＷＬm以外の各ワー ド線の電位は０Ｖにされる。これにより、セルブロック １０２ｍ内の各メモリセル１m(m-2)，１m(m-1)について のみデータの消去が行われる。

Ultra low power non-volatile memory module

An improved ultra-low power NVM module, which exhibits low power consumption and reduced layout area. An array of compact flash memory cells are programmed and erased in response to positive and negative boosted voltages. However, the compact flash memory cells are read using conventional supply voltages, thereby minimizing power consumption during a read operation. The ultra-low power NVM module of the present invention can be fabricated using conventional VLSI process steps. The ultra-low power NVM module of the present invention also allows simple operation in all modes (i.e., program, erase, read and standby).

Non-volatile memory which is programmable from a power source

PURPOSE: A non-volatile memory cell is provided to immediately give any IC circuit a good logic signal in case of power-up of the non-volatile memory cell, and memories a received binary signal as a non-volatile signal by responding to a voltage variation from a power-supply including a non-volatile memory. CONSTITUTION: A non-volatile memory(120) is connected between the first and second power buses for providing a programming voltage higher than an operation voltage. The non-volatile memory includes a memory circuit connected between the first and second power buses. The memory circuit includes an input node, an output node, and a non-volatile element connected to the input/output nodes, and responds to an input binary signal from an input node by latching the input binary signal. The non-volatile element responds to a programming voltage between the first and second power buses by memorizing the first and second state as a non-volatile state. After a power provided to the first and second power buses is interrupted, the non-volatile element is latched under a binary state.

Steering gate and bit line segmentation in non-volatile memories

조향 및 비트 라인(예를 들면, 플래시 EEPROM 시스템에서)들은 메모리 셀 어레이의 행을 따라 세그먼트된다. 일실시예에서, 그 세그먼트들중 하나의 조향 및 비트 라인들은 동시에 각각의 글로벌 조향 및 비트 라인에 연결된다. 개별 조향 게이트 세그먼트에 포함되는 메모리 셀의 열의 개수는 보다 소수의 조향 게이트 세그먼트를 구비하기 위해서 개별 비트 라인 세그먼트에 포함된 열의 개수의 배수이다. 이는 조향 게이트에 대해 필요한 트랜지스터를 선택하는 세그먼트의 개수를 감소시킴으로써 상당한 회로 면적을 감소시키는데, 왜냐하면 이러한 트랜지스터들은 더 높은 전압을 처리하기 위해서 비트 라인 세그먼트를 선택하는데 사용되는 트랜지스터보다도 대형이어야 하기 때문이다. 다른 실시예에서, 로컬 조향 게이트 라인 세그먼트는 그 개수를 감소시키기 위해서 결합되며, 각 세그먼트의 감소된 개수는 그후 세그먼트를 선택하도록 디코더의 외측에 다수의 대형 스위칭 트랜지스터의 필요없이 어드레스 디코더와 직접 연결된다. Steering and bit lines (eg in a flash EEPROM system) are segmented along a row of a memory cell array. In one embodiment, the steering and bit lines of one of the segments are simultaneously connected to each global steering and bit line. The number of columns of memory cells included in the individual steering gate segments is a multiple of the number of columns included in the individual bit line segments to have fewer steering gate segments. This reduces significant circuit area by reducing the number of segments selecting the necessary transistors for the steering gate, since these transistors must be larger than the transistors used to select the bit line segments to handle higher voltages. In another embodiment, the local steering gate line segments are combined to reduce the number, and the reduced number of each segment is then directly connected with the address decoder without the need for multiple large switching transistors outside the decoder to select the segment. .

Semiconductor device

Nonvolatile memory device and cell array of the same and method for sensing data of the same

하나의 플래쉬메모리셀에 읽기여유를 크게하면서 많은양의 정보를 저장할 수 있는 비휘발성 메모리소자와 그의 셀어레이 및 그의 데이타 센싱방법을 제공하기 위한 것으로써, 이와 같은 목적을 달성하기 위한 비휘발성 메모리소자는 반도체기판, 상기 반도체기판상에 제 1 게이트절연막, 상기 제 1 게이트절연막 상에서 서로 격리되어 형성된 제 1, 제 2 플로팅게이트, 상기 제 1, 제 2 플로팅게이트 일측의 반도체기판에 각각 형성된 불순물영역, 상기 제 1, 제 2 플로팅게이트를 포함한 상기 반도체기판상에 형성된 제 2 게이트절연막, 상기 제 1 플로팅게이트 상부 및 일측을 감싸도록 상기 제 2 게이트절연막상에 형성된 제 1 컨트롤게이트와, 상기 제 2 플로팅게이트 상부 및 일측을 감싸며 상기 제 1 컨트롤게이트와 격리되어 상기 제 2 게이트절연막상에 형성된 제 2 컨트롤게이트를 단위소자의 구성요소로 하여 구성됨을 특징으로 한다. A nonvolatile memory device capable of storing a large amount of information in a single flash memory cell while storing a large amount of information, a cell array thereof, and a data sensing method thereof. Is a semiconductor substrate, a first gate insulating film on the semiconductor substrate, first and second floating gates formed on the first gate insulating film, and are separated from each other, and an impurity region formed on the semiconductor substrate on one side of the first and second floating gates, A second gate insulating film formed on the semiconductor substrate including the first and second floating gates, a first control gate formed on the second gate insulating film to surround an upper side and one side of the first floating gate, and the second floating film It surrounds an upper portion and one side of the gate and is isolated from the first control gate to form the second gate insulating layer. And the generated second control gates, characterized by a configured as a component of the unit element.

Field effect transistor and non-volatile memory device

불휘발성 기억장치의 각각의 메모리 셀에 대해, 제1 및 제2 반도체 영역이 각각 소스와 드레인으로서 소용되도록 기판에 제공되고 그 사이에는 채널 영역이 형성된다. 상기 채널 영역의 다른 범위상에는 제1 및 제2 부유 게이트가 제공되고, 그 위에 제어 게이트가 형성된다. 기판의 것과 동일한 전도성 타입의 제3 및 제4 반도체 영역이 제1 및 제2 부유 게이트의 하부에 각각 위치되고 드레인 및 소스 영역에 각각 인접한다. 제3 및 제4 반도체 영역의 불순물 농도는 기판의 것보다 높다. 제1 및 제2 반도체 영역이 열전자를 제1 부유 게이트로 트래핑하기 위한 제1 전위차로 바이어스될 때 제3 반도체 영역에 의해 높은 전계가 만들어지고, 제1 및 제2 반도체 영역이 열전자를 제2 부유 게이트로 트래핑하기 위한 제1 전위차와 어느 정도 상반되는 제2 전위차로 바이어스될 때 제4 반도체 영역에 의해 높은 전계가 만들어진다. For each memory cell of the nonvolatile memory device, first and second semiconductor regions are provided on the substrate so as to serve as a source and a drain, respectively, and a channel region is formed therebetween. On other ranges of the channel region, first and second floating gates are provided, on which control gates are formed. Third and fourth semiconductor regions of the same conductivity type as those of the substrate are located below the first and second floating gates, respectively, and adjacent to the drain and source regions, respectively. Impurity concentrations of the third and fourth semiconductor regions are higher than those of the substrate. When the first and second semiconductor regions are biased with a first potential difference for trapping hot electrons into the first floating gate, a high electric field is created by the third semiconductor region, and the first and second semiconductor regions cause the second electrons to float the hot electrons. A high electric field is created by the fourth semiconductor region when biased with a second potential difference that is somewhat incompatible with the first potential difference for trapping into the gate.

Nonvolatile semiconductor memory and manufacturing and using the same

불휘발성 반도체 메모리는 다수의 멀티 비트 메모리 셀들로 구성되고, 각각의 메모리 셀은, 소스 영역 및 드레인 영역 사이에 규정된 체널 영역상에 형성된 제1게이트 절연막 상의 상호 절연되고 나란히 형성되는 제1 및 제2 부유 게이트와, 각각의 부유 게이트의 표면을 덮도록 형성된 제2게이트 절연막과, 상기 제2게이트 절연막 상에 형성된 제어 게이트를 포함한다. 제1 부유 게이트는 채널 영역의 소스쪽 위에 위치하고, 제2 부유 게이트는 채널 영역의 드레인 쪽 위에 위치한다. 적어도 제1부유 게이트는 제2 부유 게이트 또는 제어 게이트보다 극히 작은 게이트 길이를 갖는 측벽 폴리실리콘으로 형성된다. 따라서, 메모리셀의 최종 채널 길이가 현저히 감소되고, 따라서 각 메모리셀의 점유 면적 및 필요한 주변 회로의 점유 면적은 감소될 수 있다 The nonvolatile semiconductor memory is composed of a plurality of multi-bit memory cells, each memory cell being first and second insulated and formed side by side on a first gate insulating film formed on a channel region defined between a source region and a drain region. A second floating gate, a second gate insulating film formed to cover the surface of each floating gate, and a control gate formed on the second gate insulating film. The first floating gate is located above the source side of the channel region and the second floating gate is located above the drain side of the channel region. At least the first floating gate is formed of sidewall polysilicon having a gate length that is extremely smaller than the second floating gate or the control gate. Thus, the final channel length of the memory cells is significantly reduced, so that the occupied area of each memory cell and the necessary occupied area of the peripheral circuit can be reduced.

Multi-bit nanocrystal memory

一种具有纳米晶体栅极结构的改进型存储器单元(图20)可以在加工工艺中使用多个沟槽(52，57)来形成。该纳米晶体栅极结构(20)包括在基片(10)上的隧道氧化物层(21)、纳米晶体层(22)以及控制氧化物层(23)。形成第一沟槽(52)，并且在基片中接近第一沟槽底部的地方形成掺杂区域(54，55)。在形成至少一个掺杂区域之后，去除纳米晶体结构(20)的一部分。填充第一沟槽(31)，并且在非常接近于第一沟槽的位置上形成第二沟槽(57)。随后，去除纳米晶体栅极结构(20)在第二沟槽底部附近的第二部分。该加工工艺通过使用多个沟槽来减小纳米晶体栅极结构的尺寸，从而提高存储器单元的性能。

Non-volatile memory having multi-bit-capable cells having two-layer floating gate structure and method of programming the same

EPROM with non-volatile cells

Transistor, a transistor array and a non-volatile semiconductor memory

수명이 길고, 구조 및 기록 특성에 변동이 적고, 동작 속도가 빠르고 미세화가 가능하며 과잉 소거의 문제가 적고 구조가 간단한 메모리셀을 제공한다. Provided is a memory cell with a long lifespan, little variation in structure and recording characteristics, fast operation speed, miniaturization, low over erase problem, and simple structure. 채널 영역(4) 상에 게이트 절연막(8)을 통해 각 부유 게이트 전극(5, 6)이 배열되어 있다. 각 부유 게이트 전극 상에 터널 절연막(10)을 통해 제어 게이트 전극이 형성되어 있다. 제어 게이트 전극의 중앙부는, 채널 영역(4) 상에 배치되고, 선택 게이트(11)를 구성하고 있다. 선택 게이트(11)를 사이에 두는 각 소스·드레인 영역(3)과 선택 게이트(11)에 의해, 선택 트랜지스터(12)가 구성된다. 부유 게이트 전극과 제어 게이트 전극과의 사이의 커플링 용량은, 부유 게이트 전극과 기판(2)과의 사이의 커플링 용량보다도 매우 커지도록 설정되어 있다. Each floating gate electrode 5, 6 is arranged on the channel region 4 via the gate insulating film 8. A control gate electrode is formed on each floating gate electrode through the tunnel insulating film 10. The central portion of the control gate electrode is disposed on the channel region 4 and constitutes the selection gate 11. The select transistor 12 is configured by the source / drain regions 3 and the select gate 11 sandwiching the select gate 11. The coupling capacitance between the floating gate electrode and the control gate electrode is set so as to be much larger than the coupling capacitance between the floating gate electrode and the substrate 2.

Nonvolatile memory and method of making same

비휘발성 메모리의 트랜지스터(10)의 전하 저장 위치를 방전시키는 방법은 트랜지스터의 제어 게이트(28) 및 웰 영역(12)에 제1 및 제2 전압들을 각각 인가하는 단계를 포함한다. 제1 전압은 트랜지스터의 제어 게이트에 인가되며, 제어 게이트의 적어도 일부는 트랜지스터의 선택 게이트(18)에 인접하여 위치된다. 트랜지스터는 제어 게이트 밑에 위치된 트랜지스터의 구조의 유전물질(22, 26) 내에 배치된 나노클러스터들(24)을 갖는 전하 저장 위치를 포함한다. 마지막으로, 제2 전압은 제어 게이트 밑에 위치된 웰 영역(12)에 인가된다. 제1 전압 및 제2 전압을 인가하는 단계는 전하 저장 위치의 나노클러스터들로부터 전자들을 방전시키기 위해 구조에 전압차를 발생시킨다. The method of discharging the charge storage location of the transistor 10 in a nonvolatile memory includes applying first and second voltages to the control gate 28 and the well region 12 of the transistor, respectively. The first voltage is applied to the control gate of the transistor, at least a portion of which is located adjacent to the select gate 18 of the transistor. The transistor includes a charge storage location with nanoclusters 24 disposed within dielectric material 22, 26 of the structure of the transistor located under the control gate. Finally, the second voltage is applied to the well region 12 located below the control gate. Applying the first and second voltages generates a voltage difference in the structure to discharge the electrons from the nanoclusters in the charge storage location. 비휘발성 메모리, 제어 게이트, 선택 게이트, 유전물질, 나노클러스터  Nonvolatile Memory, Control Gates, Select Gates, Dielectrics, Nanoclusters

Semiconductor devices and operating methods of the same

본 발명의 일 실시 예에 따른 반도체 장치는 기판에 매립되고, 제1 도전형의 불순물이 도프된 도전 물질을 포함하는 소스층과, 상기 기판 상에 배치되며, 각각이 수직 절연층과 수직 채널층을 가지고, 상기 기판의 상면에 수직한 제1 방향으로 연장되는 복수의 채널 구조체들과, 상기 소스층 상에 배치되며, 상기 복수의 채널 구조체들 각각의 측벽 상에 상기 제1 방향을 따라 이격되어 배치되는 복수의 게이트 전극들과, 상기 복수의 게이트 전극들을 관통하며, 상기 제1 방향으로 연장되고, 상기 소스층과 전기적으로 연결되는 공통 소스 라인을 포함하고, 상기 복수의 게이트 전극들 중에서 적어도 하나는 게이트 유도 드레인 누설(GIDL) 라인을 제공하고, 이레이즈 동작 동안 상기 공통 소스 라인으로 인가되는 이레이즈 전압은 목표 전압에 도달하고, 상기 이레이즈 전압이 상기 목표 전압에 도달한 후, 상기 이레이즈 전압이 상기 목표 전압보다 높은 전압을 갖도록 단위 스텝 전압이 추가로 인가되며, 상기 단위 스텝 전압이 추가로 인가된 후, 상기 이레이즈 전압은 다시 상기 목표 전압으로 스텝 다운된다.

Manufacture of superconducting multilayer substrate

(57)【要約】 【課題】 不揮発性半導体記憶装置が、より高集積化し た状態で、データ保持の信頼性を下げることなく、ま た、チャネル抵抗を上げるなどのことなく、安定して動 作するようにする。 【解決手段】 半導体基板１０１の所定領域に、ゲート 絶縁膜１０２を介して、多結晶シリコンからなるフロー ティングゲート１０３ａ，１０３ｂが形成されている。 また、そのフローティングゲート１０３ａ，１０３ｂ上 には、絶縁分離膜１０４を介して多結晶シリコンなどか らなる制御ゲート１０５ａ，１０５ｂが形成されてい る。そして、フローティングゲート１０３ａおよび制御 ゲート１０５ａとフローティングゲート１０３ｂおよび 制御ゲート１０５ｂとは、面積が異なるものとなってい る。

Split-gate flash memory, method of fabricating same and method for control thereof

A split-gate flash memory, a method of fabricating the split-gate flash memory and a method for control thereof are disclosed. The split-gate flash memory includes: a semiconductor substrate including a first memory region and a second memory region that are separate from each other; and a word-line structure between the first memory region and the second memory region. The word-line structure includes, stacked on the surface of the semiconductor substrate sequentially from bottom to top, a word-line oxide layer, a read gate, a dielectric oxide layer and an erase gate. The read and erase gates can each function as a word line of the split-gate flash memory for enabling a read or erase operation. During the erase operation, a voltage applied on the erase gate has an insignificant impact on the underlying semiconductor substrate, which is helpful in reducing channel leakage in the semiconductor substrate.

NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

L'invention concerne un dispositif mémoire non volatile à semi-conducteur. Ce dispositif mémoire est réalisé sous forme d'une mémoire à valeurs multiples et la quantité d'informations pouvant être stockée est augmentée sans augmenter le nombre de transistors mémoire et l'aire occupée par ceux-ci. Une portion d'électrode de grille (20a) de chaque transistor mémoire comprend une structure de grille flottante à deux couches comprenant deux électrodes de grille flottante (22a, 22b) et une électrode de grille de commande (24) qui sont essentiellement plaquées verticalement l'une sur l'autre. Le dispositif mémoire est ainsi réalisé sous forme d'une mémoire à valeurs multiples capable de prévoir un état "1" où des électrons sont injectés dans la première électrode de grille flottante (22a), un état "0" où des électrons sont injectés dans les première et seconde électrodes de grille flottante (22a, 22b) et un étant "2" où les électrons sont retirés des première et seconde électrodes de grille flottante (22a, 22b). L'invention est utilisable dans le domaine de fabrication de dispositifs mémoire à semi-conducteur. A semiconductor non-volatile memory device is disclosed. This memory device is implemented as a multi-valued memory and the amount of information that can be stored is increased without increasing the number of memory transistors and the area occupied by them. A gate electrode portion (20a) of each memory transistor includes a two-layer floating gate structure including two floating gate electrodes (22a, 22b) and a control gate electrode (24) which are essentially vertically plated. 'one on top of the other. The memory device is thus realized as a multi-valued memory capable of providing a "1" state where electrons are injected into the first floating gate electrode (22a), a "0" state where electrons are injected into the first floating gate electrode (22a). the first and second floating ...

METHOD FOR PROGRAMMING NONVOLATILE MEMORY CELL COMPRISING A SHARED SELECTION TRANSISTOR GRID

One Check Failure Byte (CFBYTE) method

다양한 실시예는 메모리 디바이스의 프로그래밍에서 CFBYTE(one check failure byte) 방식을 수행하는 장치 및 방법을 포함할 수 있다. 각각의 메모리 셀이 다수의 비트를 저장할 수 있는 메모리 셀의 프로그래밍에서, 다수의 비트는 n-튜플의 비트 세트 중 n-튜플의 비트이며, 이러한 세트의 각각의 n-튜플은 메모리 셀에 대한 임계 전압의 n-튜플 레벨 세트의 일 레벨과 연계된다. 프로그램 알고리즘의 검증은 한 번에 하나의 레벨/분포의 임계 전압을 배치함으로써 점진적으로 진행되는 프로그래밍 알고리즘에 기초하여 구성될 수 있다. 이 진행의 루틴을 사용하여, 특정 대상 분배에 대해서만 일 실패 바이트 체크만 수행할 수 있으므로, 프로그램 알고리즘의 모든 단계에서 모든 후속 대상 분배에 대한 실패 바이트를 체크할 필요가 없다. 추가의 장치, 시스템 및 방법이 개시된다. Various embodiments may include an apparatus and method for performing a one check failure byte (CFBYTE) scheme in programming a memory device. In programming of a memory cell in which each memory cell can store a number of bits, the number of bits is a bit of an n-tuple of a set of bits of an n-tuple, and each n-tuple of this set is a threshold for the memory cell. Associated with one level of a set of n-tuple levels of voltage. Verification of the program algorithm may be constructed based on a progressive programming algorithm by placing threshold voltages of one level/distribution at a time. Using the routines in this proceeding, only one failed byte check can be performed for a particular target distribution, so there is no need to check the failed byte for every subsequent target distribution at every step of the program algorithm. Additional devices, systems and methods are disclosed.

METHOD FOR MANUFACTURING POWER DIODES, ESPECIALLY FOR FORMING A GRATEZ BRIDGE, AND CORRESPONDING DEVICE

Le procédé de fabrication de plusieurs diodes (D1, D2, D3) comprend une première implantation (10) de dopants d'un deuxième type de conductivité dans une première couche semiconductrice (5) ayant un premier type de conductivité située sur une couche isolante (3) recouvrant un substrat semiconducteur (1) et surmontée de régions saillantes mutuellement espacées (CGf), de façon à former une succession de jonctions PN formant lesdites diodes dans ladite première couche semiconductrice (5) s'étendant jusqu'à la couche isolante (3) en bordure des régions saillantes (bCGf). The method for manufacturing a plurality of diodes (D1, D2, D3) comprises a first implantation (10) of dopants of a second conductivity type in a first semiconductor layer (5) having a first conductivity type located on an insulating layer ( 3) covering a semiconductor substrate (1) and surmounted by mutually spaced projection regions (CGf), so as to form a succession of PN junctions forming said diodes in said first semiconductor layer (5) extending to the insulating layer ( 3) bordering the projecting regions (bCGf).

Non-volatile semiconductor memory cell utilizing trapped charge generated by channel-initiated secondary electron injection

The present invention provides a semiconductor device that comprises a tub region located in a semiconductor substrate, wherein the tub region has a tub electrical contact connected thereto. The semiconductor device further comprises a trap charge insulator layer located on the first insulator layer and a control gate located over the trap charge insulator layer. The control gate has a gate contact connected thereto for providing a second bias voltage to the semiconductor device that, during programming, is opposite in polarity to that of the first bias voltage.

Nonvolatile latch circuit and logic circuit, and semiconductor device using the same

새로운 불휘발성 래치 회로 및 상기 불휘발성 래치 회로를 사용한 반도체 장치를 제공하기 위해, 불휘발성 래치 회로는 제 1 소자의 출력이 제 2 소자의 입력에 전기적으로 접속되고, 상기 제 2 소자의 출력이 상기 제 1 소자의 입력에 전기적으로 접속되는 루프 구조를 갖는 래치부; 및 상기 래치부의 데이터를 보유하기 위한 데이터 보유부를 포함한다. 상기 데이터 보유부에서, 채널 형성 영역을 형성하기 위한 반도체 재료로서 산화물 반도체를 사용한 트랜지스터가 스위칭 소자로서 사용된다. 또한, 상기 트랜지스터의 소스 전극 또는 드레인 전극에 전기적으로 접속된 인버터가 포함된다. 상기 트랜지스터를 사용하여, 상기 래치부에 보유된 데이터는 상기 인버터의 게이트 용량 소자 또는 별도로 제공되는 용량 소자에 기록될 수 있다. In order to provide a new nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, the nonvolatile latch circuit is characterized in that the output of the first element is electrically connected to the input of the second element, A latch portion having a loop structure electrically connected to an input of the first element; And a data holding unit for holding data of the latch unit. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel forming region is used as a switching element. Further, an inverter electrically connected to the source electrode or the drain electrode of the transistor is included. Using the transistor, data held in the latch portion can be written to a gate capacitance element of the inverter or a separately provided capacitance element.

FOUR STATE MEMORY CELL

L'invention concerne une cellule mémoire électriquement programmable à quatre états comprenant au-dessus d'une région de canal d'un premier type de conductivité une grille de commande isolée (24), des régions de source (30) et de drain (31) du deuxième type de conductivité, chacune de ces régions de source et de drain comprenant au voisinage du canal une zone à faible niveau de dopage (26, 27), une grille flottante (29, 28) recouvrant au moins en partie chacune desdites zones à faible niveau de dopage, l'épaisseur d'isolant sous chacune des grilles flottantes étant inférieure à l'épaisseur d'isolant sous la grille de commande et étant suffisamment faible pour qu'une injection de charges puisse se produire par effet tunnel.

Nonvolatile memory circuit and structure

A nonvolatile memory includes five transistors. The memory has an MOS transistor in series with two pairs of transistors, where each pair includes a floating gate transistor and a metal-oxide-semiconductor transistor electrically connected in parallel. The memory structure may be formed with three levels of silicon-containing or metal-containing layers. The memory structure is less susceptible to read disturb errors compared to a prior art dual-bit nonvolatile memory structure.

Electronic device including gate lines, bit lines, or a combination thereof

An electronic device can include memory cells that are connected to gate lines, bit lines, or a combination thereof. In one embodiment, at least two sets of memory cells can be oriented substantially along a first direction, (e.g., rows or columns). A first gate line may be electrically connected to fewer rows or columns of memory cells as compared to a second gate line. For example, the first gate line may only be electrically connected to the first set of memory cells, and the second gate line may be electrically connected to the second and third sets of memory cells. In another embodiment, a first bit line may be electrically connected to fewer rows or columns of memory cells as compared to a second bit line. In still another embodiment, another set of memory cells may be oriented substantially along another direction that is substantially perpendicular to the first direction.