СПОСОБ ЗАПИСИ ДАННЫХ В ЭНЕРГОНЕЗАВИСИМОЕ ЗАПОМИНАЮЩЕЕ УСТРОЙСТВО, СПОСОБ ИСПОЛЬЗОВАНИЯ УСТРОЙСТВА НА ИНТЕГРАЛЬНЫХ СХЕМАХ, УСТРОЙСТВО НА ИНТЕГРАЛЬНЫХ СХЕМАХ

Изобретение касается записи информации в энергонезависимое запоминающее устройство. Технический результат изобретения заключается в способе записи данных в энергонезависимое запоминающее устройство типа электрически стираемого программируемого постоянного запоминающего устройства (ЭСППЗУ) в кредитной карточке с встроенной микроЭВМ, обеспечивающем область состояния записи в ЭСППЗУ, которая проверяется при каждом восстановлении кредитной карточки. Если предшествующая операция ввода была безуспешной, возможно, из-за умышленного манипулирования карточкой, выполняется процедура восстановления. Если восстановление проведено успешно, можно прогонять прикладную задачу карточки. В противном случае карточка является непригодной. 10 з.п.ф-лы, 6 ил.

Einen Flashspeicher verwendendes Speichergerät

Verfahren zum bidirektionalen Datentransfer zwischen einem Terminal und einer Chipkarte sowie Chipkarte

PROZESSOR MIT EINGEBETTETEN IN-CIRCUIT PROGRAMMIERUNGSSTRUKTUREN

VERSCHIEBUNG AUFEINANDER FOLGENDER SEKTOREN INNERHALB EINES DATENBLOCKS IN EINEM FLASH-MASSENSPEICHER

Verfahren und Vorrichtung zur Änderung von Software in einem Steuergerät sowie entsprechendes Steuergerät

Verfahren und Vorrichtung zur Änderung von Software in einem ersten Speicherbereich in einem Steuergerät zur Steuerung von Betriebsabläufen, wobei die Ausführung alter Softwareteile durch die Ausführung neuer Softwareteile ersetzt wird und die alten Softwareteile in dem ersten Speicherbereich eingeschrieben sind, wobei die neuen Softwareteile in einem zweiten Speicherbereich eingeschrieben werden und durch eine erste Verzweigung im ersten Speicherbereich statt der alten Softwareteile im ersten Speicherbereich, die neuen Softwareteile im zweiten Speicherbereich ausgeführt werden, wobei nach Ausführung der neuen Softwareteile durch eine zweite Verzweigung im zweiten Speicherbereich wieder in den ersten Speicherbereich rückverzweigt wird und die Ausführung der weiteren von den alten Softwareteilen verschiedene Software im ersten Speicherbereich fortgesetzt wird, wobei die alten Softwareteile im ersten Speicherbereich verbleiben.

Programming flash memory of control unit, especially motor vehicle control unit connected via controller area network (CAN) bus, using communications link which can be switched between programming and communications elements

A device for programming a control unit (100) in which the control unit is linked to an external programming device (101) via a communications interface (110). An internal communications connection (104) links the interface with a control unit (103) that has programming (108) and communications (107) elements and a switching unit (105) with which a communications link can be switched between the programming element and the communications element. Independent claims are made for a switching device with connections for a communications link and a method for programming a control unit.

METHOD AND SYSTEM FOR STORING DATA IN A MEMORY

For writing data into the memory regions of an EEPROM 40 a predetermined number of times, the data are written into the memory regions of which serial addresses are arranged to wrap around so that it is possible to write data into the memory regions the predetermined number of times greater than a number of times determined by the re-writing property of the memory. In use, the contents of those regions which store the count of the number of times writing has occurred to a given region are checked to locate an effective memory region which has the last address in the group of regions of which each one stores a count equal to that stored in the region which has the first address of the group. This allows stored data to be maintained for a predetermined time even in a state where the power supply is cut off. ...

Flash solid state disk card

Method of writing data to non-volatile memory

Reprogramming a non-volatile memory system

A non-volatile memory system is provided. The system comprises non-volatile memory divided into a plurality of segments each segment having an address in an address space and wherein at least one of the segments is unused. The system further comprises means for copying any one segment to be reprogrammed into a RAM, the RAM having a size at least equal to the segment size, means for reprogramming the contents of the RAM, means for erasing the unused segment, writing means for writing the reprogrammed code into the at least one unused memory segment, and control means arranged to amend the address space to show the same address of the reprogrammed segment.

Programmable code store circuitry for a nonvolatile semiconductor memory device

REPROGRAMMABLE CARTRIDGE

A portable data storage device.

A portable data storage device (10)includes a universal serial bus (usb)coupling device (1)and an interface device (2)is coupled to the usb coupling device (1). The portable data storage device (10)also includes a memory control device (3)and a non volatile solid-state memory device (4). The memory control device (3)is coupled betweem the interface device (2)and the memory device (4)to control the flow of data from the memory device (4)to the usb coupling device (1) ...

A portable data storage device

PLACE ADMINISTRATION FOR THE ADMINISTRATION OF A NON VOLATILE HIGH SPEED MEMORY

DATA WRITE DEVICE, DATA RECORDING MODE AND PROGRAM

PROCEDURE FOR THE LETTER OF DATA INTO A NOT VOLATILE MEMORY

PROGRAM A FLASH MEMORY

NON VOLATILE MEMORY AND PROCEDURE WITH TAX DATA ADMINSTRATION

PROCEDURE FOR THE FLASH MEMORY ADMINISTRATION

BROADCAST AND EMPFANGSSYSTEM AND CONDITION ENTRANCE SYSTEM FOR IT

PROCEDURE FOR THE LETTER OF DATA INTO A NOT VOLATILE MEMORY

CHIPKARTE MIT AUSTAUSCHINDIKATION

The method involves embedding chip software (14) in a terminal (16), a monitor (17), and a keyboard (18). The chip software detects defective storage cells (12) i.e. electrically EPROM cells, and produces information about necessary exchange of a chip card during exceeding a preset threshold and during reaching an end of a service life of the card. The threshold is calculated based on a number of defective storage cells. The software delivers information about the necessary exchange of the chip card to a card issuer (27) e.g. bank, using a data connection (26) with a transaction receiver.

PROCEDURE FOR THE RE-ESTABLISHMENT OF ADMINISTRATIVE DATA RECORDS BLOCK-BY-BLOCK ONES OF AN ERASABLE MEMORY

PLACE ADMINISTRATION FOR THE ADMINISTRATION OF A NON VOLATILE HIGH SPEED MEMORY

PLACE ADMINISTRATION FOR THE ADMINISTRATION OF A NON VOLATILE HIGH SPEED MEMORY

PLACE ADMINISTRATION FOR THE ADMINISTRATION OF A NON VOLATILE HIGH SPEED MEMORY

PLACE ADMINISTRATION FOR THE ADMINISTRATION OF A NON VOLATILE HIGH SPEED MEMORY

PLACE ADMINISTRATION FOR THE ADMINISTRATION OF A NON VOLATILE HIGH SPEED MEMORY

PLACE ADMINISTRATION FOR THE ADMINISTRATION OF A NON VOLATILE HIGH SPEED MEMORY

PLACE ADMINISTRATION FOR THE ADMINISTRATION OF A NON VOLATILE HIGH SPEED MEMORY

PLACE ADMINISTRATION FOR THE ADMINISTRATION OF A NON VOLATILE HIGH SPEED MEMORY

PLACE ADMINISTRATION FOR THE ADMINISTRATION OF A NON VOLATILE HIGH SPEED MEMORY

Method of using flash memory for storing metering data

A METHOD AND A UNIT FOR PROGRAMMING A MEMORY

MEMORY REWRITING SYSTEM FOR VEHICLE CONTROLLER

... ▓▓▓▓ A memory rewriting system for a vehicle controller is▓provided. The system comprises a vehicle controller and an▓external rewriting device. A vehicle controller comprises a▓rewritable memory storing first security data. The first▓security data is used to determine whether rewriting to the▓rewritable memory is permitted. The rewriting device transfers▓new security data to the vehicle controller. The vehicle▓controller deletes the first security data and writes the new▓security data into the rewritable memory. Rewriting the new▓security data is performed by a program stored in a▓non-rewritable memory. Thus, the security data that is used▓to determine whether rewriting to the rewritable memory is▓permitted is rewritten with the new security data. Therefore,▓if the existing security data stored in the vehicle controller▓is invalidated, the security feature of the vehicle can be▓recovered. The vehicle may includes an anti-theft system. In▓this case, rewriting to the rewritable memory is ...

METHOD AND SYSTEM FOR UPDATING A STORED DATA VALUE IN A NON-VOLATILE MEMORY

A method of updating a stored data value in a non-volatile memory is provide d. The method comprising: reading the stored data value from the non-volatile memory; reading a stored differential value from a volatile memory; receiving an updated data value; calculating a calculated differential value from the difference between the updated data value and the sum of the stored data value and the stored differential value; comparing the calculated differential value with a threshold differential value; and writing the updated data value to t he non-volatile memory if the calculated differential value exceeds the threshold differenti al value.

METHOD OF AND APPARATUS FOR TRANSMITTING DATA FOR INTERACTIVE TV APPLICATIONS

A method of transmitting data to a receiver/decoder comprises: transmitting first type visual and/or audio data to the receiver/decoder; and transmitting second type reference data associated with the first type visual and/or audio data to the receiver/decoder to enable the receiver/decoder to generate further visual and/or audio data in dependence on the reference data; wherein the first type data and the second type data have a predetermined timing relationship.

Network control apparatus memory and method for modifying its instructions.

СПОСІБ ЗБЕРЕЖЕННЯ СЕКЦІЙ ПОТОКУ ДАНИХ, ЩО ТРАНСЛЮЮТЬСЯ (ВАРІАНТИ), І ПРИСТРІЙ ДЛЯ ЙОГО ЗДІЙСНЕННЯ

Пропонується спосіб збереження принаймні однієї з множини MPEG секцій потоку даних MPEG, що транслюється, причому MPEG секція має хоч би одну ознаку MPEG секції. Потік даних MPEG приймається, і ця одна MPEG секція відфільтровується з потоку даних MPEG згідно принаймні з однією ознакою MPEG секції. Потім MPEG секція зберігається.

Data writing to non- volatile memory

Portable data storage device incorporating multiple flash memory units

A portable data storage device is disclosed which includes an Interface (3) for enabling the portable data storage device to be used for data transfer with a host Computer (5), and an Interface controller (7) for controlling the interface (3). There is also a master control unit (9) for controlling the writing of data to and reading data from a non-volatile memory. The non-volatile memory includes at least one single layer cell flash memory (11) and at least one multiple layer cell flash memory (13). Upon receiving a write instruction, the master control unit (9) determines which of the memories (11, 13) data contained in the instruction should be written to, and writes the data as appropriate similarly, upon receiving a read instruction, the master control unit (9) reads the data from the appropriate one of the memories (11, 13) and transmits the data out of the device.

Content data storage device and its control method

A content data storage device which stores content data in nonvolatile memories from which data is erasable in units of blocks includes a bus width conversion unit converting a transmission bus to buses of a plurality of systems, a storage unit including a plurality of sets of memories, a plurality of switching units selectively switching between derivation of the content data and derivation of command signals and addresses, a controller configuring to perform (i) conversion control, (ii) state control, (iii) supply control, and (iv) switching control, the controller controlling the operationfor reading and writing the content data with reference to the nonvolatile memories, and, a plurality of switch on and off units selectively switching on or off the content data, the command signals and the addresses.

Non-volatile memory and method with memory planes alignment

Pipelined parallel programming operation in a non-volatile memory system

MBARQUE, DISPOSITIF COMPORTANT UNE TELLE MEMOIRE ET INSTALLATION POUR L'INSCRIPTION D'INFORMATIONS DANS CETTE MEMOIRE

Mémoire pour dispositif d'introduction de données dans un calculateur embarque. Les données introduites dans le calculateur embarqué sont relatives, notamment, à des paramètres de vol d'un avion à bord duquel se trouvent le dispositif et le calculateur. La mémoire comporte un élément 1 du type à état solide, un boîtier 7 pour cet élément, un connecteur 6 pour l'inscription et la lecture d'informations dans l'élément 1 et des conducteurs de liaison entre le connecteur 6 et l'élément 1. Applications : mémorisation de plan de vol.

Integrated circuit memory card and method or count of units in a memory card.

METHOD AND APPARATUS FOR CONTROL OF FLASH MEMORY.

ADAPTER FOR a LATER MODIFICATION OF the DATA OF SOFTWARE Of UNDISPOSITIF OF ORDER

Un système de communication de données avec un dispositif de commande (7) du véhicule comporte un adaptateur flash (2), qui est enfiché avec une clé de véhicule (3) dans la serrure de contact (6) d'un véhicule automobile. La clé du véhicule (3) est authentifiée au moment de l'introduction dans la serrure de contact (6). Ensuite, l'adaptateur flash (2) peut déclencher une comparaison entre les données stockées dans la clé et le véhicule.

WRITING OF DATA IN A NONVOLATILE MEMORY OF SMART CARD

La description concerne notamment un procédé d'écriture de données dans une mémoire non volatile de carte à puce. La description concerne également une carte à puce et un programme d'ordinateur aptes à mettre en œuvre un tel procédé, un support de stockage comprenant un tel programme d'ordinateur, ainsi qu'un système comprenant une carte à puce et un dispositif permettant d'écrire dans la carte.

Smart card of counting of data and reading device

L'invention concerne un circuit intégré de carte à mémoire passive de comptage d'unités comprenant p étages de mémoire de comptage de données (10, 11, 12) contenant des nombres de cases respectifs n1 ...np , une écriture étant effectuée dans une case d'un étage supérieur chaque fois que toutes les cases de l'étage inférieur ont été validées, les cases des étages inférieurs étant ensuite effacées. Ce circuit comprend p-1 étages témoin (21, 22) identiques aux p-1 étages de rang supérieur des p étages de comptage, la logique d'adressage des étages témoin étant telle que les cases de ces étages témoin sont adressées en écriture simultanément avec les cases des étages de comptage correspondants et, après une écriture, sont adressées en effacement en même temps que les cases des étages inférieurs à celui qui vient d'être validé.

METHOD OF ADDRESSING A NON-VOLATILE MEMORY OVER A BUS I² C AND MEMORY DEVICE CORRESPONDING

Le procédé d'adressage d'un circuit intégré de mémoire non volatile (NVM) du type EEPROM sur un bus du type I2C, et comportant J broches d'identification matérielle (E0, E1, E2), avec J un entier compris entre 1 et 3, affectées de potentiels respectifs définissant un code d'affectation sur J bits, le procédé comprenant : - un premier mode d'adressage (M1) utilisé sélectivement lorsque le code d'affectation est égal à un code de référence fixé sur J bits, comprenant un adressage du plan-mémoire de la mémoire non volatile par une adresse-mémoire (MEMADR) contenue dans les derniers bits de poids faible (LSB) de ladite adresse d'esclave (SLADR) et dans les N premiers octets reçus (DATA1, DATA2), et - un deuxième mode d'adressage (M2) utilisé sélectivement lorsque le code d'affectation est différent du code de référence, comprenant un adressage du plan-mémoire par une adresse-mémoire (MEMADR) contenue dans les N+1 premiers octets reçus.

Method and device for secured writing of data in rewritable memory, for use in microelectronics and chip cards

On définit une mémoire comprenant un fichier cyclique possédant m enregistrements organisés en boucle, avec m entier allant de 1 à n+1, les enregistrements 1 à n étant accessibles tandis que l'enregistrement n+1, l'indicateur d'intégrité et le rang de chaque enregistrement étant cachés à l'utilisateur. On recherche l'enregistrement m = n+1, et on vérifie l'état de son indicateur d'intégrité. En cas d'indicateur d'intégrité mauvais, on écrit la donnée à inscrire dans l'enregistrement m = n+1, et en cas de succès, on incrémente d'une unité l'enregistrement m = n+1+1 = 1 qui devient caché, laissant accessibles les enregistrements 2 à n+1 tandis qu'en cas d'échec, on n'apporte aucune modification à l'enregistrement m = n+1 qui reste caché, les autres enregistrements 1 à n restant accessibles à l'utilisateur. En cas d'indicateur d'intégrité bon, on écrit la donnée à inscrire dans l'enregistrement m=n+1+1=1, et en cas de succès, on incrémente d'une unité le rang de l'enregistrement m = 1+1 = ...

WRITE BUS I2C EEPROM

L'invention concerne un circuit de mémoire EEPROM (3) comportant, entre un registre de réception des données (36) et un décodeur de colonne (33), une mémoire tampon (39) dont la taille correspond à la taille d'un page de données.

Aircraft flight computing system memory - using solid state reprogrammable type state memory carried in aircraft

WRITING IN REAL-TIME MADE SAFE FOR NONVOLATILE MEMORY

WRITING IN REAL-TIME MADE SAFE FOR NONVOLATILE MEMORY

WRITING IN REAL-TIME MADE SAFE FOR NONVOLATILE MEMORY

WRITING IN REAL-TIME MADE SAFE FOR NONVOLATILE MEMORY

WRITING IN REAL-TIME MADE SAFE FOR NONVOLATILE MEMORY

WRITING IN REAL-TIME MADE SAFE FOR NONVOLATILE MEMORY

WRITING IN REAL-TIME MADE SAFE FOR NONVOLATILE MEMORY

WRITING IN REAL-TIME MADE SAFE FOR NONVOLATILE MEMORY

PIPELINED PARALLEL PROGRAMMING OPERATION IN A NON-VOLATILE MEMORY SYSTEM

MEMORY CARD, SEMICONDUCTOR DEVICE, AND METHOD OF CONTROLLING SEMICONDUCTOR MEMORY

SIMULTANEOUS EXTERNAL READ OPERATION DURING INTERNAL PROGRAMMING IN A FLASH MEMORY DEVICE

A system (300) and method for performing a simultaneous external read operation during internal programming of a memory device (301) is described. The memory device is configured to store data randomly and includes a source location (305), a destination location (303), a data register (307), and a cache register (309). The data register (307) is configured to simultaneously write data to the destination (303) and to the cache register (309). The system (300) further includes a processing device (107) (e.g., a microprocessor or microcontroller) for verifying an accuracy of any data received through electrical communication with the memory device. The processing device (107) is additionally configured to provide for error correction if the received data are inaccurate, add random data to the data, if required, and then transfer the error-corrected and/or random data modified data back to the destination location (303). © KIPO & WIPO 2007 ...

NOVEL METHOD AND STRUCTURE FOR RELIABLE DATA COPY OPERATION FOR NON- VOLATILE MEMORIES

An improved flash EEPROM memory-based storage subsystem includes one or more flash memory arrays, each with a duplicity of data registers and a controller circuit. When data are read from a flash array into a data register, the data is copied to a second register so that, during the ensuing program operation into the same array, the data may be transferred to the controller for the purpose of checking the data validity. This creates an improved performance system that doesn't suffer data transfer latency during copy operations but that is able to guarantee the validity of the data involved in such operations. © KIPO & WIPO 2007 ...

Disposal of circuit and process for authentication of the content of a memory area

EXTENDED SELECT GATE LIFETIME

A memory device may include two or more memory cells in an integrated circuit, at least one flash cell acting as a select gate coupled to the two or more memory cells, and an interface to accept a select gate erase command and a select gate program command during normal operation of the integrated circuit. The integrated circuit may be capable to perform operations to erase the at least one select gate in response to the select gate erase command, and program the at least one select gate in response to the select gate program command.

METHOD FOR FLASH-MEMORY MANAGEMENT

A SIM card including: (a) a first NVM for storing user data; and (b) a second NVM, separate from the first NVM, for storing management data related to the user data. Preferably, the first NVM is block-erasable and the second NVM is word-erasable. Preferably, the first NVM is a flash memory and the second NVM is an EEPROM. Preferably, the management data includes a mapping table for mapping virtual addresses, of the first NVM, to physical device addresses. Preferably, the user data and the management data are organized in a file system. Most preferably, the management data includes at least one file allocation table. Most preferably, the management data includes at least one files directory, wherein at least one files directory includes at least one item selected from the group consisting of: a file name, a file size, a file attribute, and a physical address of a file sector.

DATA OPERATIONS IN FLASH MEMORIES UTILIZING DIRECT DATA FILE STORAGE

Host system data files are written directly to a large erase block flash memory system with a unique identification of each file and offsets of data within the file but without the use of any intermediate logical addresses or a virtual address space for the memory. Directory information of where the files are stored in the memory is maintained within the memory system by its controller, rather than by the host.

MOVING SEQUENTIAL SECTORS WITHIN A BLOCK OF INFORMATION IN A FLASH MEMORY MASS STORAGE ARCHITECTURE

A method and apparatus are disclosed for increasing the system performance of a digital system having a controller for controlling nonvolatile devices for storing blocks of information, each block having a group of sectors. When sectors within a block are being rewritten in sequential order, the controller writes the new sector information into a sector location of another block without the need to move any of the sectors within the original block thereby reducing the number of read and write cycles needed to avoid erase-before-write operations. A "moved" flag (1042), stored in the sector location of each block, indicates that the sector has been transferred to another block or, alternatively, a move locator word (170) maintains status information regarding the position of the sectors within the blocks that have been moved.

RECORDING MEDIUM RECORDING CONTROL METHOD AND RECORDING CONTROL DEVICE

A recording control method for writing data onto a recording medium. A predetermined number of small blocks are handled as data read/write units. Data can be erased as a large block consisting of small blocks. Write in small block units can be performed between large blocks and small blocks at random. Write of small blocks in a large block is performed in the order of the addresses. When write of a small block in a large block is complete, if the next small block to be written is contained in the same large block containing the small block which has been written and if the address of the next small block to be written follows the address of the small block which has been written, write of the small block to be written is executed.

High-Performance Flash Memory Data Transfer

A flash memory system including a flash memory device and a controller, operable according to an advanced data transfer mode is disclosed. The flash memory device is operable both in a “legacy” mode, in which read data is presented by the memory synchronously with each cycle of a read data strobe from the controller, and in which input data is latched by the memory synchronously with each cycle of a write data strobe from the controller. In the advanced mode, which can be initiated by the controller forwarding an initiation command to the memory, the flash memory itself sources the read data strobe, and presents data synchronously with both the falling and rising edges of that read data strobe. In the advanced mode, the input data is presented by the controller synchronously with both edges of the write data strobe. The voltage swing of the data and control signals is reduced from conventional standards, to reduce power consumption.

Method for copying flash memory with duplexed processor board

The present invention discloses a method for copying flash memories of multiple processor boards without the need of a separate copying device. Particularly, the present invention discloses a system with a duplex processor boards and inserting the flash memories onto the processor boards. Afterwards, the program is loaded into the flash memory of one processor and transferred to the flash memory of the other processor.

Semiconductor IC device having a control register for designating memory blocks for erasure

A semiconductor integrated circuit device having a processing unit and a memory which stores data to be processed by the processing unit and which provides data to the processing unit through the data bus in response to accessing instructions from the processing unit through the address bus. The memory has a plurality of memory blocks each of which has a plurality of electrically programmable nonvolatile memory cells arranged in rows and columns in which each nonvolatile memory cell is coupled to one of a plurality of word lines and one of a plurality of data lines of the memory. The memory blocks formed can be facilitated with different memory capacities, including through controlling the number of rows or columns of memory cells associated therewith. Sources of all of the memory cells within each memory block are connected to a single source line which is fed by a predetermined voltage from a corresponding one of plural source voltage control circuits, for flash erasing the memory cells ...

Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device including a memory means having a plurality of storage areas divided in a capacity serving as a management unit, a first managing means for, when data is to be written in the storage areas, circularly arranging the plurality of storage areas such that the plurality of storage areas physically or logically arranged, and managing the storage areas such that the plurality of storage areas are used in accordance with an order of an arrangement of the plurality of storage areas, a second managing means for managing whether data recorded in the plurality of storage areas is changed after a predetermined timing, and a control means for, when data is written in the storage area and a predetermined condition is satisfied, selecting a storage area having data which is not changed after a timing when the second managing means is initialized, moving the data in the selected storage area to another storage area, and initializing the second managing means when ...

Semiconductor storage apparatus

A semiconductor storage apparatus is provided which can be used as a primary storage apparatus and a secondary storage apparatus and which allows both high accessibility and non-volatile storage of information. A volatile RAM section is a semiconductor memory adapted to load information to be stored and can be accessed at a high speed from the outside by way of a central control section. A non-volatile RAM section is another semiconductor memory into which information can be electrically reloaded and which does not require a power supply for holding stored contents. Under the control of a save/reload control section of the central control section, a memory mutual access control section is activated and saving/reloading of stored information is performed between the volatile RAM section and the non-volatile RAM section by a volatile RAM access control section and a non-volatile RAM access control section.

PROGRAM AND READ TRIM SETTING

A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device according to observed or tested programming speed and reliability.

Management of memory blocks that directly store data files

Host system data files are written directly to a large erase block flash memory system with a unique identification of each file and offsets of data within the file but without the use of any intermediate logical addresses or a virtual address space for the memory. Directory information of where the files are stored in the memory is maintained within the memory system by its controller, rather than by the host. A type of memory block is selected to receive additional data of a file that depends upon the types of blocks into which data of the file have already been written. Blocks containing data are selected for reclaiming any unused capacity therefrom by a process that selects blocks in order starting with those containing the least amount of valid data.

Partial block data programming and reading operations in a non-volatile memory

Data in less than all of the pages of a non-volatile memory block are updated by programming the new data in unused pages of either the same or another block. In order to prevent having to copy unchanged pages of data into the new block, or to program flags into superceded pages of data, the pages of new data are identified by the same logical address as the pages of data which they superceded and a time stamp is added to note when each page was written. When reading the data, the most recent pages of data are used and the older superceded pages of data are ignored. This technique is also applied to metablocks that include one block from each of several different units of a memory array, by directing all page updates to a single unused block in one of the units.

Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein

A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME

A semiconductor device includes: a first sector (12) having data that are all to be erased and having flash memory cells; a second sector (14) having data that are all to be retained and having flash memory cells; a sector select circuit (16) selecting a pair of sectors from among sectors during erasing the data in the first sector, said pair of sectors being the first sector and the second sector; and an SRAM array (storage) (30) retaining the data of the second sector. The present invention can provide a semiconductor device in which a reduced number of sector select circuits is used so that the area of memory cell array can be reduced and provide a method of controlling the semiconductor device.

Method and apparatus for predictive flash memory erase and write times

A NOR-gate architecture memory with an erase and write time table. The memory processor creates an erase and write time table in a table block. The table contains the most recent times for erase and write operations for each data block in the memory. When a storage operation is initiated, the processor accesses the table and estimates the amount of time it will take to perform the data storage operation and then communicates that back to a host computer. Each data storage operation results in a new table being created that is written into the data block. To save erase and write operations for the table block, the new table is written directly after the most recent table unless there is not enough space. An erase and write operation is only performed on the table block if there is not enough space for the new table.

Semiconductor storage device having page copying function

Data read from memory cells of one page in a memory cell array that corresponds to a page address of a copy source is sensed and latched by a sense/latch circuit. The sense/latch circuit has a plurality of latch circuits, and the plurality of latch circuits is specified according to the column address. The latch circuit specified in accordance with the column address is supplied with the data to be rewritten. The latch circuit specified in accordance with its address latches the data to be rewritten, whereby rewriting of the data is performed. The data of one page after rewritten is written into the page in the memory cell array that corresponds to the page address of a copy destination.

Method for Controlling Non-Volatile Semiconductor Memory System

In a memory system using a storage medium, which is inserted into an electronic apparatus via a connector to add a memory function thereto, the storage medium has a GROUND terminal, a power supply terminal, a control terminal and a data input/output terminal, and the connector has a function of being sequentially connected to each of the terminals. When the storage medium is inserted into the connector, the GROUND terminal and control terminal of the storage medium are connected to corresponding terminals of the connector before the power supply terminal and data input/output terminal of the storage medium are connected to corresponding terminals of the connector. Thus, it is possible to improve the stability when a memory card is inserted into or ejected from the memory system.

Memory arrangement

A memory arrangement and method for operating the memory arrangement comprising a nonvolatile memory and at least one address translation unit, the nonvolatile memory having memory pages and at least one additional memory page, the memory pages and the additional memory page having physical addresses and the address translation unit translating logically addressable addresses into the physical addresses of the memory pages and of the additional memory page. The nonvolatile memory stores data which make address translation possible within an unaddressable area in the memory pages and in the additional memory page. For the purposes of programming a memory page, a copy of data and a copy of the data of the unaddressable area are stored in a further memory for processing and the data of the unaddressable area are changed. Once programming has been completed, the processed copy of the data and the changed data of the unaddressable area are stored in the additional memory page.

Internal copy to handle NAND program fail

An embodiment of a semiconductor package apparatus may include technology to attempt to program data in a first portion of a nonvolatile memory, determine if the attempt was successful, and recover the data to a second portion of the nonvolatile memory with an internal data move operation if the attempt is determined to be not successful. Other embodiments are disclosed and claimed.

Writing data in a non-volatile memory of a smart card

A smart card compares an object identification parameter associated with a write command with an object identification parameter stored in the non-volatile memory of the smart card. If the comparison is positive, the data embedded in the write command is written at a at a predefined address whose value is stored in the non-volatile memory, an address corresponding to the sum of the stored predefined address and the size of the written data is calculated, and the calculated address is stored in the non-volatile memory in place of the predefined address. If the comparison is negative, the data is written at a default address, an address corresponding to the sum of the default address and the size of the written data is calculated, and the calculated address is stored in the non-volatile memory as the predefined address.

SYSTEMS AND METHODS FOR DISTRIBUTING PROGRAMMING SPEED AMONG BLOCKS WITH DIFFERENT PROGRAM-ERASE CYCLE COUNTS

Non-volatile memory systems and method for managing P/E cycling is disclosed. Memory systems include multi-plane (e.g., 2-plane or 4-plane) programming operations in which new blocks within a plane replace faulty/bad blocks. Existing blocks, having undergone several P/E cycles more than the new block(s), require a lower programming voltage and are programmed using an adaptive (reduced) programming voltage. New block(s) require an additional voltage, and a delta voltage is added to the programming voltage to increase the gate-to-channel voltage. To prevent the delta voltage from over-programming the existing blocks, a voltage equal to the delta voltage is applied bit lines of the existing blocks, thereby reducing the effective gate-to-channel voltage on the existing blocks. In this manner, the same programming voltage is applied to planes in a multi-plane programming operation, and the existing blocks receive a relatively lower gate-to-channel voltage, while the new block(s) receive a relatively ...

MEMORY DEVICE WITH SINGLE TRANSISTOR DRIVERS AND METHODS TO OPERATE THE MEMORY DEVICE

A memory device with single transistor drivers and methods to operate the memory device are described. In some embodiments, the memory device may comprise memory cells at cross points of access lines of a memory array, a first even single transistor driver configured to drive a first even access line to a discharging voltage during an IDLE phase, to drive the first even access line to a floating voltage during an ACTIVE phase, and to drive the first even access line to a read/program voltage during a PULSE phase, and a first odd single transistor driver configured to drive a first odd access line, the first odd access line physically adjacent to the first even access line, to the discharging voltage during the IDLE phase, to drive the first odd access line to the floating voltage during the ACTIVE phase, and to drive the first odd access line to a shielding voltage during the PULSE phase.

ADJUSTING READ-LEVEL THRESHOLDS BASED ON WRITE-TO-WRITE DELAY

A method includes performing a first write operation that writes data to a first memory unit of a group of memory units in a memory device, determining a write-to-write (W2W) delay based on a time difference between the first write operation and a second write operation on a memory unit in the group of memory units, wherein the second write operation occurred prior to the first write operation, identifying a threshold time criterion that is satisfied by the W2W delay, identifying a first read voltage level associated with the threshold time criterion, and associating the first read voltage level with a second memory unit of the group of memory units. The second memory unit can be associated with a second read voltage level that satisfies a selection criterion based on a comparison of the second read voltage level to the first read voltage level.

Non-volatile memory device

Provided is a non-volatile memory device including a memory cell array including cell strings each including memory cells and a string select transistor connected to a string select line; a page buffer circuit including page buffers each including a forcing latch configured to store forcing information; and a control logic circuit configured to, during a program operation on a selected word line, control at least two of a first voltage applied to the string select line in a first interval before a bit line forcing operation for transferring the forcing information to the selected cell string, a second voltage applied to the string select line in a second interval in which the bit line forcing operation is performed, and a third voltage applied to the string select line in a third interval after the bit line forcing operation is performed, to be different from each other.

UNIPOLAR PROGRAMMING OF MEMORY CELLS

Systems, methods, and apparatuses are provided for unipolar programming of memory cells in a semiconductor device. A memory has a plurality of self-selecting memory cells and circuitry configured to program a self-selecting memory cell of the plurality of self-selecting memory cells to a first data state or a second data state by applying a current pulse to the self-selecting memory cell. The current is a set pulse or a reset pulse. The set pulse and the reset pulse have a same polarity.

PERFORMING SELECTIVE COPYBACK IN MEMORY DEVICES

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising determining a data validity metric value with respect to a set of memory cells of the memory device; responsive to determining that the data validity metric value satisfies a first threshold criterion, performing a data integrity check on the set of memory cells to obtain a data integrity metric value; and responsive to determining that the data integrity metric value satisfies a second threshold criterion, performing an error handling operation on the data stored on the set of memory cells to generate corrected data.

Memory for accessing multiple sectors of information substantially concurrently

A memory storage system of an embodiment includes a non-volatile memory unit and memory control circuitry coupled to the memory unit. The memory control circuitry is configured to access multiple sectors of information substantially concurrently.

Interleaved flash storage system and method

A flash storage system accesses data interleaved among flash storage devices. The flash storage system receives a data block including data portions, stores the data portions in a data buffer, and initiates data transfers for asynchronously writing the data portions into storage blocks interleaved among the flash storage devices. Additionally, the flash storage system may asynchronously read data portions of a data block interleaved among the storage blocks, store the data portions in the data buffer, and access the data portions from the data buffer.

Communication device with storage function

According to one embodiment, a communication device includes a data storage device and following units. The reception unit receives data from another communication device. The data storage device includes a data area controlled by a file system and a temporary area beyond control of the file system. The processing unit operates in one of first and second start modes, the processing unit being started faster in the second start mode than in the first start mode. The processing unit operating in the second start mode writes the received data to the temporary area, copies the received data in the temporary area to the data area after completion of data reception, and erases the received data in the temporary area after copying.

SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR PHYSICAL QUANTITY SENSOR DEVICE

In aspects of the invention, an auxiliary memory circuit includes a shift register wherein a plurality of flip-flops are cascade-connected and a plurality of inversion circuits that invert and output outputs of each D flip-flop. A main memory circuit includes a switch, which acts in accordance with a signal from the auxiliary memory circuit, and an EPROM connected in series to the switch and driven by a writing voltage. A variable resistance circuit includes a switch, which acts in accordance with a signal from the auxiliary memory circuit, and a resistor connected in series to the switch. With aspects of the invention, it is possible for terminals of the writing voltage and a writing voltage to be commonized. Also, it is possible to provide a low-cost semiconductor physical quantity sensor device that can carry out electrical trimming with the voltage when writing into the EPROM kept constant. 1. A semiconductor integrated circuit , comprising:a data input terminal that inputs serial digital data;a ground terminal that supplies ground potential;a power source terminal that supplies power source voltage;an auxiliary memory circuit that temporarily stores trimming data input from the data input terminal;a programmable read only main memory circuit that stores trimming data stored in the auxiliary memory circuit using an electrical rewrite action;a writing terminal that inputs an external clock, or that supplies a first writing voltage, equal to or higher than the power source voltage, for writing data into the main memory circuit;a variable resistance circuit that, based on the first writing voltage input from the writing terminal, generates a second writing voltage, which is equal to or higher than the power source voltage and wherein the first writing voltage is divided by resistance of the main memory circuit, for writing data into the main memory circuit, and supplies the second writing voltage to the main memory circuit; anda signal distinguishing means that ...

APPARATUSES AND METHODS OF OPERATING FOR MEMORY ENDURANCE

Methods of operating an apparatus such as a computing system and/or memory device for memory endurance are provided. One example method can include receiving m digits of data having a first quantity of digits represented by a first data state that is more detrimental to memory cell wear than a second data state. The m digits of data are encoded into n digits of data having a second quantity of digits represented by the first data state. The value n is greater than the value m. The second quantity is less than or equal to the first quantity. The n digits of data are stored in an apparatus having memory cells. 1. A method , comprising:receiving m digits of data having a first quantity of digits represented by a first data state that is more detrimental to memory cell wear than a second data state;encoding the m digits of data into n digits of data, the n digits of data having a second quantity of digits represented by the first data state, n being greater than m, the second quantity being less than or equal to the first quantity; andstoring the n digits of data in an apparatus having memory cells.2. The method of claim 1 , further comprising:retrieving the n digits of data from the apparatus; anddecoding the n digits of data into the m digits of data.3. The method of claim 2 , wherein the apparatus comprises a memory device and further comprising communicating the n digits of data between a host and the memory device claim 2 , wherein the encoding and the decoding occurs at the host.4. The method of claim 2 , wherein the apparatus comprises a memory device and further comprising communicating the m digits of data between a host and the memory device claim 2 , wherein the encoding and the decoding occurs at the memory device.5. The method of claim 1 , wherein the m digits of data comprise m bits of data claim 1 , the n digits of data comprise n bits of data claim 1 , and the memory cells comprise single level memory cells.6. The method of claim 1 , wherein the memory ...

Select gate programming in a memory device

Methods for programming select gates, memory devices, and memory systems are disclosed. In one such method for programming, a program inhibit voltage is transferred from a source to unselected bit lines. Bit line-to-bit line capacitance, between the unselected bit lines and selected bit lines to be program inhibited, boosts the bit line voltage of the selected, inhibited bit lines to a target inhibit voltage. In one embodiment, the voltage on the selected, inhibited bit line can be increased in a plurality of inhibit steps whereby either one, two, or all of the steps can be used during the programming of unprogrammed select gates.

Memory block identified by group of logical block addresses, storage device with movable sectors, and methods

In an embodiment, only one sector of a plurality of sectors in a physical block of a plurality of physical blocks has a sector status location configured to store information that indicates a move status of an other sector of the plurality sectors of the physical block of the plurality of physical blocks, where the only one sector of the plurality of sectors in the physical block of the plurality of physical blocks is configured to store a sector of data in addition to the information that indicates the move status.

METHOD FOR MEASURING INTERFERENCE IN A MEMORY DEVICE

A method for measuring interference in a memory device is provided. The method includes: programming a selected memory cell among a plurality of memory cells connected in series between a bit line and a source line; measuring a first noise value of the programmed selected memory cell; programming an adjacent memory cell adjacent to the selected memory cell among the plurality of memory cells; measuring a second noise value of the selected memory cell, after the programming of the adjacent memory cell is completed; and determining interference on the selected memory cell based on the first noise value and the second noise value. The first noise value and the second noise value are measured by detecting a low frequency noise of a cell current of the selected memory cell. 1. A method for measuring interference in a memory device , the method comprising:programming a selected memory cell among a plurality of memory cells connected in series between a bit line and a source line;measuring a first noise value of the programmed selected memory cell;programming an adjacent memory cell adjacent to the selected memory cell among the plurality of memory cells;measuring a second noise value of the selected memory cell, after the programming of the adjacent memory cell is completed; anddetermining interference on the selected memory cell based on the first noise value and the second noise value,wherein the first noise value and the second noise value are measured by detecting a low frequency noise of a cell current of the selected memory cell.2. The method of claim 1 , further comprising measuring an initial noise value of the selected memory cell before the programming of the selected memory cell.3. The method of claim 2 , wherein the measuring of the initial noise value includes:applying a pass voltage to the selected memory cell and the adjacent memory cell in an erase state; anddetecting the low frequency noise of the cell current of the selected memory cell in a state in ...

METHOD AND APPARATUS FOR CONFIRUIING WRITE PERFORMANCE FOR ELECTRICALLY WRITABLE MEMORY DEVICES

Methods and systems are provided that may include a nonvolatile memory to store information, where the nonvolatile memory is associated with a configuration register to indicate a write speed setting for at least one write operation to the nonvolatile memory. A circuit may supply current to achieve an indicated write speed setting for the at least one write operation to the nonvolatile memory. 1. A method , comprising:selecting, for a memory device having a plurality of memory cells, a write bandwidth for the memory device from a plurality of write bandwidths;determining a current setting for performing write operations of the memory device based at least in part on the write bandwidth for the memory device; andperforming a write operation on the plurality of memory cells using the determined current setting.2. The method of claim 1 , further comprising:reading a write bandwidth setting from a memory register, wherein selecting the write bandwidth is based at least in part on the write bandwidth setting.3. The method of claim 1 , wherein selecting the write bandwidth is performed before writing information associated with the write operation.4. The method of claim 1 , wherein selecting the write bandwidth is based at least in part on an operating environment of the memory device.5. The method of claim 1 , wherein selecting the write bandwidth is based at least in part on whether the memory device is being operated in an end product.6. The method of claim 1 , wherein selecting the write bandwidth comprises:identifying a setting of a programmable switch; andselecting the write bandwidth based at least in part on the setting of the programmable switch.7. The method of claim 1 , wherein selecting the write bandwidth is based at least in part on a determined power consumption of a system that includes the memory device.8. The method of claim 1 , wherein selecting the write bandwidth is based at least in part on a determined amount of current that can be supplied to the ...

PROGRAMMABLE INPUT/OUTPUT CIRCUIT

A apparatus, having a processing system and an input buffer coupled with both the processing system and one of two IO pads, and a reference buffer coupled to both the input buffer and the second of the IO pads such that the reference generator controls the input threshold of the input buffer in response to an analog voltage received from an external circuit on the second of the TO pads. 120-. (canceled)21. An apparatus comprising:a processing system configured to generate first output signals directed to an external circuit, and further configured to receive first input signals;an input/output (I/O) pad communicatively coupled with the processing system and configured to establish, at least in part, a link with an external circuit;a programmable I/O circuit coupled between the I/O pad and the processing system, the programmable I/O circuit configured to generate a second output signal provided to the I/O pad, the programmable I/O circuit being further configured to provide the first input signal to the processing system; anda programmable reset circuit configured to generate a programmable reset signal provided to the I/O pad, the programmable reset signal being capable of resetting a component of the external circuit.22. The apparatus of claim 21 , wherein the programmable reset circuit includes a programmable external reset cell configured to generate the programmable reset signal claim 21 , and wherein the programmable reset signal is capable of resetting a device core included in the external circuit.23. The apparatus of claim 22 , wherein the programmable reset circuit further includes a first non-volatile memory element configured to store a polarity state associated with the programmable reset signal.24. The apparatus of claim 23 , wherein the first non-volatile memory element is coupled to the programmable external reset cell claim 23 , and wherein the programmable external reset cell is configured to generate the programmable reset signal having a polarity ...

MEMORY DEVICE AND A MEMORY SYSTEM INCLUDING THE SAME

A memory device including: a memory cell array including a plurality of memory cells forming a plurality of strings in a vertical direction with a substrate; and a control logic configured to detect a not-open string (N/O string) from the plurality of strings in response to a write command and convert pieces of target data to be programmed on a plurality of target memory cells in the N/O string so that the pieces of target data have a value that limits a number of times a program voltage is applied to the plurality of target memory cells. 1. A memory device , comprising:a memory cell array comprising a plurality of memory cells forming a plurality of strings in a vertical direction with a substrate; anda control logic configured to detect a not-open string (N/O string) from the plurality of strings in response to a write command and convert pieces of target data to be programmed on a plurality of target memory cells in the N/O string so that the pieces of target data have a value that limits a number of times a program voltage is applied to the plurality of target memory cells.2. The memory device of claim 1 , further comprising a voltage generator configured to generate a plurality of voltages to be provided to the memory cell array claim 1 ,wherein the control logic is further configured to control the voltage generator to apply a check voltage higher than a reference voltage to a plurality of word lines connected to the plurality of memory cells.34-. (canceled)5. The memory device of claim 2 , wherein the reference voltage is used to verify a top-level program state of the plurality of memory cells.6. The memory device of claim 2 , wherein the reference voltage is used to verify an erase state of the plurality of memory cells.7. The memory device of claim 6 , wherein the plurality of memory cells form one sub-block or one block claim 6 , andthe control logic is further configured to control an erase operation on the plurality of memory cells before detecting the ...

IC CARD AND IC CARD SYSTEM HAVING SUSPEND/RESUME FUNCTIONS

An IC card and an IC card system are disclosed in which command processing performance is improved by storing current state data related to a first command upon interruption of an execution cycle for the first command by a second command. Upon completion of the second command, the current state information is reloaded and execution of the first command is resumed. 1. A MultiMedia (MMC) card comprising:a flash memory for storing data related to a program command;a static random access memory (SRAM) configured to store flag values associated with an execution of the program command;an interface device configured to receive the program command, a first command and an interrupt command from a host device; anda controller configured to perform an execution of the program command in the flash memory, to halt the execution of the program command upon receiving the interrupt command, to store the flag values related to the execution of the program command at a predetermined memory location in the SRAM, to perform an execution of a first command in the flash memory upon receiving the first command, and to perform an execution of remaining portion of the program command upon again receiving the program command from the host device after completing the execution of the first command,wherein the first command has a higher priority that was determined by the host device than the program command.2. The MMC card of claim 1 , wherein the controller performs the execution of remaining portion of the program command based on the flag values.3. A storage medium comprising:at least one flash memory for storing data related to a program command;a volatile memory configured to store a state information associated with an execution of the program command; anda controller configured to perform an execution of the program command in the at least one flash memory, to halt the execution of the program command upon receiving an interrupt or a similar command from a host device, to store the ...

Memory system and method for operating semiconductor memory device

A method for operating a semiconductor memory device may include applying a program pulse for programming data of a first page included in the semiconductor memory device. The method may include determining whether the number of times of applying the program pulse has exceeded a first critical value. The method may include performing an error bit check on a second page coupled to the same word line as the first page, based on the determined result of whether the first critical value has been exceeded.

EXTERNAL MEMORY DEVICE

An external memory device configured to communicate with an external electronic device includes: a semiconductor substrate including a first edge and a second edge perpendicular to the first edge; a semiconductor integrated circuit device provided on the semiconductor substrate, the semiconductor integrated circuit device including a memory device configured to store data provided from the external electronic device, an input/output interface configured to interface with the external electronic device, and a controller configured to control the memory device in response to a signal transmitted through the input/output interface; an insulating layer covering the semiconductor integrated circuit device; and external input/output pins provided adjacent to the first edge on the insulating layer and configured to establish an electrical connection between the external electronic device and the semiconductor integrated circuit device.

NONVOLATILE MEMORY DEVICE PERFORMING TWO-WAY CHANNEL PRECHARGE

A nonvolatile memory device that performs two-way channel precharge during programming is provided. A program operation of the nonvolatile memory device simultaneously performs a first precharge operation in a bit line direction and a second precharge operation in a source line direction on channels of a plurality of cell strings before programming a selected memory cell to initialize the channels. The first precharge operation precharges the channels of the plurality of cell strings using a first precharge voltage applied to the bit line through first and second string selection transistors, and the second precharge operation precharges the channels of the plurality of cell strings using a second precharge voltage applied to the source line through first and second ground selection transistors. 1. A program method of a nonvolatile memory device comprising a plurality of cell strings connected between a plurality of bit lines and a source line , each cell string comprising a first string selection transistor , a second string selection transistor , a plurality of memory cells , a second ground selection transistor , and a first ground selection transistor being arranged in series between a bit line and the source line , the program method comprising:initializing channels with respect to the plurality of cell strings; andperforming a program operation on a selected memory cell among the plurality of memory cells,wherein the initializing of the channels comprises:performing a first precharge on the channels of the plurality of cell strings using a first precharge voltage applied to the plurality of bit lines through the first and second string selection transistors;performing a second precharge on the channels of the plurality of cell strings using a second precharge voltage applied to the source line through the first and second ground selection transistors;applying a ground voltage or a first negative voltage lower than the ground voltage to a first string selection ...

NONVOLATILE MEMORY DEVICE WITH INTERMEDIATE SWITCHING TRANSISTORS AND PROGRAMMING METHOD

To program in a nonvolatile memory device including a cell region including first metal pads and a peripheral region including second metal pads and vertically connected to the cell region by the first metal pads and the second metal pads, a memory block is provided with a plurality of sub blocks disposed in a vertical direction where the memory block includes a plurality of cell strings each including a plurality of memory cells connected in series and disposed in the vertical direction. A plurality of intermediate switching transistors are disposed in a boundary portion between two adjacent sub blocks in the vertical direction. Each of the plurality of intermediate switching transistors is selectively activated based on a program address during a program operation. The selectively activating each of the plurality of intermediate switching transistors includes selectively turning on one or more intermediate switching transistors in a selected cell string based on the program address. 1. A nonvolatile memory device comprising:a plurality of first metal pads in a cell region;a plurality of second metal pads in a peripheral region under the cell region, wherein the peripheral region is vertically connected to the cell region by the first metal pads and the second metal pads;a first memory block in the cell region, the first memory block being divided into a plurality of sub blocks and including a plurality of cell strings each comprising a plurality of memory cells connected in series and disposed in a vertical direction;a plurality of intermediate switching transistors disposed in a boundary portion between two adjacent sub blocks in the first memory block in the vertical direction; anda control circuit in the peripheral region, the control circuit being configured to selectively turn on one or more intermediate switching transistors in a selected cell string of the first memory block independently of intermediate switching transistors in unselected cell strings of ...

Use of differing granularity heat maps for caching and migration

For data processing in a computing storage environment by a processor device, the computing storage environment incorporating at least high-speed and lower-speed caches, and tiered levels of storage, groups of data segments are migrated between the tiered levels of storage such that if a selected group is cached in the lower-speed cache and is determined to become uniformly hot, migrating the selected group from the lower-speed cache to the SSD portion while refraining from processing data retained in the lower-speed cache until the selected group is fully migrated to the SSD portion.

MEMORY DEVICES INCLUDING CAPACITOR STRUCTURES HAVING IMPROVED AREA EFFICIENCY

Semiconductor structures including a plurality of conductive structures having a dielectric material therebetween are disclosed. The thickness of the dielectric material spacing apart the conductive structures may be adjusted to provide optimization of capacitance and voltage threshold. The semiconductor structures may be used as capacitors, for example, in memory devices. Various methods may be used to form such semiconductor structures and capacitors including such semiconductor structures. Memory devices including such capacitors are also disclosed. 1. A method of forming at least one capacitor structure comprising laterally spaced conductive structures , the method comprising:selecting a voltage to be applied to the at least one capacitor;selecting a dielectric material having a known dielectric constant;forming the conductive structures laterally spaced from one another a distance equal to a thickness of the dielectric material to be disposed in the space therebetween sufficient to withstand the selected applied voltage without breakdown; anddisposing the dielectric material between the laterally spaced, vertically extending conductive structures.2. The method of claim 1 , wherein forming the conductive structures comprises:forming laterally spaced discrete regions of a sacrificial material on a conductive material;applying a spacer material over the discrete regions of sacrificial material and exposed surfaces of the conductive material;removing a portion of the spacer material above the discrete regions to form spacers laterally adjacent sidewalls of each of the discrete regions;removing the discrete regions between the spacers to expose a surface of the conductive material; andremoving a portion of the conductive material exposed between the spacers to form the conductive structures overlying an intermediate material.3. The method of claim 2 , wherein removing the discrete regions to expose a surface of the conductive material between the spacers comprises ...

MEMORY DEVICE, MEMORY MODULE, AND MEMORY SYSTEM

A memory device includes a memory cell array, a data pattern providing unit, and a write circuit. The memory cell array includes a plurality of memory regions. The data pattern providing unit is configured to provide a predefined data pattern. The write circuit is configured to, when a first write command and an address signal are received from an external device, write the predefined data pattern provided from the data pattern providing unit to a memory region corresponding to the address signal. 118-. (canceled)19. A memory device comprising:a memory cell array including a first memory bank and a second memory bank, each of the first and the second memory banks being accessible independently;a write circuit configured to perform a pattern write operation upon receiving a pattern write command and a first address, and to perform a normal write operation upon receiving a normal write command, a second address and a write data;a data pattern providing unit configured to provide a selected data pattern to the write circuit in response to the pattern write command, the selected data pattern being a data pattern to be written into the memory cell array; anda data input buffer configured to receive the write data from an external device and to provide the write data to the write circuit during the normal write operation;wherein, during the pattern write operation, the selected data pattern is written into the first memory bank designated by the first address and, during the normal write operation, the write data received from the external device is written into the second memory bank designated by the second address, andwherein at least a portion of the normal write operation in the second memory bank is performed in parallel with the pattern write operation in the first memory bank.20. The memory device of claim 19 , wherein the memory device is a dynamic random access memory (DRAM).21. The memory device of claim 20 , wherein the write data is received through DQ pins ...

STORAGE STRUCTURE AND ERASE METHOD THEREOF

The invention provides a storage structure and an erase method thereof, which can perform an erase operation on memory blocks B. . . B, where n is an integer greater than or equal to 2. The storage structure includes a first memory bank, a second memory bank and a controller, wherein the memory blocks are sequentially alternately arranged in the first memory bank and the second memory bank. The controller is used to control the memory blocks to sequentially undergo an erase operation. The erase operation includes sequentially performing a first process and a second process. When memory block Bundergoes the second process, the memory block Bundergoes the first process, where i ∈ [1, n−1]. 1. A storage structure capable of performing an erase operation on memory blocks B. . . B , where n is an integer greater than or equal to 2 , the storage structure comprising a first memory bank , a second memory bank , and a controller , wherein the memory blocks are sequentially alternately arranged in the first memory bank and the second memory bank , and the controller is configured to control the memory blocks to undergo an erase operation , wherein the erase operation comprises sequentially performing a first process and a second process;{'sub': ['i', 'i+1'], '#text': 'wherein when memory block Bundergoes the second process, the memory block Bundergoes the first process, where i ∈ [1, n−1].'}2. The storage structure according to claim 1 , wherein after the memory block Bcompletes the first process claim 1 , the memory block Bundergoes the second process and the memory block Bundergoes the first process at the same time; then the erase operation is performed on the remaining memory blocks sequentially until the memory block Bundergoes the second process and the memory block Bundergoes the first process at the same time claim 1 , then the memory block Bundergoes the second process.3. The storage structure according to claim 1 , wherein the first process includes a pre- ...

Semiconductor memory device and operation method thereof

Providing a semiconductor memory device capable of knowing whether a reading of the setting information which is set during the power-on operation had been completed correctly or not. The flash memory in the present invention reads the fuse memory when it is detected that the power supply has reached the power-on detection level, and determines whether the reading of the fuse memory had been completed correctly. When not completed correctly, the fuse memory is read again within the maximum read count, and the setting information (which was read from the fuse memory) is written into the CF register. Furthermore, the identification information (that identifies whether the reading of the fuse memory has been completed correctly or not) is stored in the register.

Flash Memory System With EEPROM Functionality

The present invention relates to a flash memory device with EEPROM functionality. The flash memory device is byte-erasable and bit-programmable. 1. (canceled)2. A non-volatile memory device comprising:an array of memory cells arranged in rows and columns, each row corresponding to a word line and each column corresponding to a bit line, and each memory cell comprising a floating gate, a bit line terminal for connecting to a bit line, a word line terminal for connecting to a word line, and a source line terminal for connecting to a source line; anda word line select line for controlling access by a word line to the byte of memory cells;wherein the device is configured to erase a byte of memory cells without any other memory cells in the array being concurrently erased.3. The device of claim 2 , further comprising: a word line deselect line for preventing access by a word line to the byte of memory cells.4. A non-volatile memory device comprising:an array of memory cells arranged in rows and columns, each row corresponding to a word line and each column corresponding to a bit line, and each memory cell comprising a floating gate, a bit line terminal for connecting to a bit line, a word line terminal for connecting to a word line, and a source line terminal for connecting to a source line; anda first source line select line for controlling access by a first source line to the byte of memory cells;wherein the device is configured to erase a byte of memory cells without any other memory cells in the array being concurrently erased.5. The device of claim 2 , further comprising: a first source line select line for controlling access by a first source line to the byte of memory cells.6. The device of claim 3 , further comprising: a first source line select line for controlling access by a first source line to the byte of memory cells.7. The device of claim 4 , further comprising: a second source line select line for controlling access by a second source line to the byte of ...

DATA STORAGE DEVICE WITH OPERATION BASED ON TEMPERATURE DIFFERENCE

Embodiments of the present disclosure may relate to a memory controller that may include a memory interface and a logic circuitry component coupled with the memory interface. In some embodiments, the logic circuitry component is to program one or more NAND cells of a multi-level NAND memory array via the memory interface with a first set of data in a first pass, determine a first temperature of the multi-level NAND memory array in association with the first pass, determine a second temperature of the multi-level NAND memory array, determine a temperature difference between the second temperature and the first temperature, and perform one or more operations based at least in part on a result of the determination of the temperature difference. Other embodiments may be described and/or claimed. 1. A memory controller comprising:a memory interface; and program one or more NAND cells of a multi-level NAND memory array via the memory interface with a first set of data in a first pass;', 'determine a first temperature of the multi-level NAND memory array in association with the first pass;', 'determine a second temperature of the multi-level NAND memory array;', 'determine a temperature difference between the second temperature and the first temperature; and', 'perform one or more operations based at least in part on a result of the determination of the temperature difference, wherein the one or more operations include one or more of: program the one or more NAND cells with a second set of data in a second pass, in response to the temperature difference being less than or equal to a predefined threshold value; and send a flag indicating that the temperature difference exceeded the predefined threshold value to a host controller, to facilitate an external data read of the one or more NAND cells, data correction associated with the one or more NAND cells, or recovery of data encoded by the one or more NAND cells, in response to the temperature difference being greater than ...

PAGE WRITES FOR TRIPLE LEVEL CELL FLASH MEMORY

A method for page writes for triple or higher level cell flash memory is provided. The method includes receiving data in a storage system, from a client that is agnostic of page write requirements for triple or higher level cell flash memory, wherein the page write requirements specify an amount of data and a sequence of writing data for a set of pages to assure read data coherency for the set of pages. The method includes accumulating the received data, in random-access memory (RAM) in the storage system to satisfy the page write requirements for the triple or higher level cell flash memory in the storage system. The method includes writing at least a portion of the accumulated data in accordance with the page write requirements, from the RAM to the triple level cell, or the higher level cell, flash memory in the storage system as an atomic write. 1. A method , comprising:accumulating an amount of the data in random-access memory (RAM) in the storage system to satisfy page write requirements for a portion of a multi-level cell flash memory in a storage system; anddetermining page write requirements for differing types of flash memory within the storage system, the page write requirements providing an order for writing to pages of each of the differing types of flash memory.2. The method of claim 1 , wherein the differing types of flash memory include flash memory from different vendors.3. The method of claim 1 , wherein the differing types of flash memory include flash memory having different storage capacity.4. The method of claim 1 , wherein the client is one of a client that is external to the storage system claim 1 , sending user data claim 1 , or a client internal to the storage system claim 1 , sending metadata or error coded user data.5. The method of claim 1 , wherein:the page write requirements for the portion of multi-level cell flash memory comprise writing the lower page, the upper page and an extra page to assure read coherency of cells, wherein the ...

MEMORY DEVICE

A memory device includes programmable memory cells and a programming circuit for programming a selected memory cell to a target logic state by applying one or more programming current pulses. A temperature sensor operates to sense a temperature of the memory device. A reading circuit reads a current logic state of the selected memory cell after a predetermined programming current pulse of the programming current pulses. The reading circuit includes a sensing circuit that senses a current logic state of the selected memory cell according to a comparison between a reading electric current depending on the current logic state of the selected memory cell and a reference current. An adjusting circuit adjusts one or the other of the reading electric current and the reference electric current to be provided to the sensing circuit according to the temperature of the memory device.

FLASH MEMORY PROGRAMMING CHECK CIRCUIT

The present application relates to the technical field of memories, in particular to a flash memory programming check circuit, comprising: a memory cell, wherein a bit line is led out from the memory cell, and a pulse sequence signal with a gradually increasing voltage amplitude is applied to the bit line, so that during a high level period of the pulse sequence signal, the memory cell undergoes a program operation, and during a low level period of the pulse sequence signal, the memory cell undergoes a read detection operation; a pulse sequence generation unit used to generate the pulse sequence signal with a gradually increasing voltage amplitude to the bit line; and a reset unit used to control, when a programming control signal starts to be generated, a voltage of the bit line to drop. 1. A flash memory programming check circuit , the flash memory programming check circuit comprising:a memory cell, wherein a bit line is led out from the memory cell, and a pulse sequence signal with a gradually increasing voltage amplitude is applied to the bit line, so that during a high level period of the pulse sequence signal, the memory cell undergoes a program operation, and during a low level period of the pulse sequence signal, the memory cell undergoes a read detection operation;a pulse sequence generation unit used to generate the pulse sequence signal to the bit line; anda reset unit used to control, when a programming control signal starts to be generated, a voltage of the bit line to drop.2. The flash memory programming check circuit according to claim 1 , wherein the pulse sequence generation unit comprises:a charge pump module used to output a step wave with a gradually rising voltage; anda detection control module connected between an output end of the charge pump module and the bit line of the memory cell and used to perform periodical turn-off according to control of a detection control signal, to convert the input step wave with a gradually rising voltage into ...

Memory system with memory region read counts and a memory group read count and operating method thereof

A memory system includes a storage medium including a memory region group having a plurality of memory regions; a memory configured to store a plurality of region read counts respectively corresponding to the plurality of memory regions and a group read count corresponding to the memory region group; a count management circuit configured to, when a first memory region among the plurality of memory regions is read-accessed, based on a first region read count corresponding to the first memory region among the plurality of region read counts, increase the group read count and reduce remaining region read counts other than the first region read count among the plurality of region read counts; and a reliability management circuit configured to perform a reliability management operation for the memory region group, based on the group read count.

NEW MEMORY ARCHITECTURE FOR SERIAL EEPROMS

In an embodiment an electrically erasable programmable readable memory includes a plurality of memory cells organised in a memory plane arranged in a matrix fashion in rows and in columns, wherein each memory cell includes a state transistor having a source region, a drain region, an injection window situated on the side of the drain, a control gate and a floating gate and an isolation transistor having a source region, a drain region and a gate; and an isolation barrier including a buried layer and at least one wall extending from the buried layer to a surface of a substrate, wherein the at least one wall is perpendicular to the buried layer, and wherein the isolating barrier forms an interior substrate surrounding at least one of the memory cells and isolating it from the remainder of the substrate. 1. A memory of electrically erasable programmable read only memory type arranged in and on a semiconductor substrate , the memory comprising: a state transistor comprising a source region, a drain region, an injection window situated on a side of the drain, a control gate and a floating gate; and', 'an isolation transistor having a source region, a drain region and a gate; and, 'a plurality of memory cells organized in a memory plane arranged in a matrix fashion in rows and in columns, each memory cell comprising a buried layer; and', 'at least one wall extending from the buried layer to a surface of the substrate,, 'an isolation barrier comprisingwherein the at least one wall is perpendicular to the buried layer, andwherein the isolating barrier forms an interior substrate surrounding at least one of the memory cells and isolating it from the remainder of the substrate.2. The memory according to claim 1 ,wherein the control gate of the state transistor is connected to a control gate line of the memory,wherein the source region of the isolation transistor is connected to a source line of the memory,wherein the gate of the isolation transistor is connected to a word ...

NON-DESTRUCTIVE MODE CACHE PROGRAMMING IN NAND FLASH MEMORY DEVICES

A method of cache programming of a NAND flash memory in a triple-level-cell (TLC) mode is provided. The method includes discarding an upper page of a first programming data from a first set of data latches in a plurality of page buffers when a first group of logic states are programmed and verified. The plurality of page buffers include the first, second and third sets of data latches, configured to store the upper page, middle page and lower page of programming data, respectively. The method also includes uploading a lower page of second programming data to a set of cache latches, transferring the lower page of the second programming data from the set of cache latches to the third set of data latches after discarding the lower page of the first programming data, and uploading a middle page of the second programming data to the set of cache latches. 1. A memory device , comprising:memory cells arranged in rows and columns, each memory cell configured to store n-bit of data, wherein n is a whole number larger than 1; and the periphery circuit comprises page buffers, each page buffer comprising n data latches and coupled to a column of memory cells through a bit line; and', store the n logic pages of the current programming data in the n data latches for programming the selected row of memory cells;', 'release one or more of the n data latches, by discarding one or more of the n logic pages of the current programming data correspondingly, before the programming the selected row of memory cells according to the n logic pages of the current programming data is completed;', 'store one or more of n logic pages of new programming data in the released data latches before the programming the selected row of memory cells according to the n logic pages of the current programming data is completed; and', {'sup': 'n', 'recover the discarded one or more of the n logic pages of the current programing data when there is a programming failure, based on remaining logic pages of the ...

Programming method for nand flash memory device to reduce electrons in channels

In a programming method for a NAND flash memory device, a self-boosting scheme is used to eliminate excess electrons in the channel of an inhibit cell string that would otherwise cause programming disturb. The elimination is enabled by applying a negative voltage to word lines connected to the inhibit cell string before boosting the channel, and this leads to bringing high program immunity. A row decoder circuitry to achieve the programming operation and a file system architecture based on the programming scheme to improve the efficiency of file management are also described.

NOR FLASH MEMORY CIRCUIT AND DATA WRITING METHOD

The present disclosure relates to a NOR flash memory circuit, a data writing method, a data reading method, and a data erasing method. The NOR flash memory circuit includes: a NOR memory array, a source voltage selection unit, a well voltage selection unit, a word line gating unit, a bit line gating unit, a data reading unit, and an analog voltage generating unit. During data writing, a source is floated, and a well electrode is connected to ground; and a first forward voltage is applied to a bit line where a memory cell to be written data into is located, and a second forward voltage is applied to a word line where the memory cell to be written data into is located. During data reading, a source is grounded, and well electrodes are grounded; and a third forward voltage is applied to a word line. 1. A data writing method for NOR flash memory , the data writing method comprises:floating the source of each memory cell in a NOR flash memory array, and connecting a well electrode to ground;gating a bit line in the NOR flash memory array, wherein a memory cell into which data is to be written is located at the bit line; the primary electrons move toward a drain of the memory cell and collide with a side wall of a drain region of the memory cell to accelerate holes downward, and', 'the holes collide with a substrate of the memory cell to generate secondary electrons;, 'applying a first forward voltage to the bit line, so that electron-hole pairs are generated in the memory cell and primary electrons are generated, wherein'}gating a word line where the memory cell is located; andapplying a second forward voltage to the word line of the memory cell, so that the secondary electrons generate tertiary electrons under the action of a vertical electric field to inject the tertiary electrons into a floating gate of the memory cell, in order to achieve data writing.2. The data writing method for NOR flash memory as in claim 1 , whereinthe first forward voltage is not less than 4 V ...

COMPUTING SYSTEM WITH CACHE MANAGEMENT MECHANISM AND METHOD OF OPERATION THEREOF

A computing system includes: a memory storage unit, having memory blocks, configured as a memory cache to store storable objects; and a device control unit, coupled to the memory storage unit, configured to: calculate an entropy level for the storable objects based on an eviction policy; calculate a block entropy for each of the memory blocks based on the entropy level of the storable objects in the memory blocks; select an erase block from the memory blocks, wherein the erase block is an instance of the memory blocks with the lowest value of the block entropy; and perform an erase operation on the erase block. 1. A computing system comprising:a memory storage unit, having memory blocks, configured as a memory cache to store storable objects; anda device control unit, coupled to the memory storage unit, configured to:calculate an entropy level for the storable objects based on an eviction policy;calculate a block entropy for each of the memory blocks based on the entropy level of the storable objects in the memory blocks;select an erase block from the memory blocks, wherein the erase block is an instance of the memory blocks with the lowest value of the block entropy; andperform an erase operation on the erase block.2. The system as claimed in wherein the device control unit is configured to calculate the entropy level based on the eviction policy including a least recent policy.3. The system as claimed in wherein the device control unit is configured to calculate the entropy level based on the eviction policy including a least frequent policy.4. The system as claimed in wherein the device control unit is configured to calculate the entropy level based on the eviction policy including an expiration policy.5. The system as claimed in wherein the device control unit is configured to initiate unsolicited initiation of selection of the erase block and performance of the erase operation on the erase block.6. The system as claimed in wherein the device control unit is ...

SEMICONDUCTOR MEMORY DEVICE AND PROGRAMMING METHOD THEREOF

A semiconductor memory device includes a memory cell array, a peripheral circuit and a control logic. The memory cell array includes a plurality of memory cells each of which stores 2 or more bits of data. The peripheral circuit is configured to perform a program operation for the memory cells in the memory cell array. The control logic is configured to control the peripheral circuit and the memory cell array such that, during a program operation for target memory cells to be programmed among the memory cells, a preprogram for memory cells to be programmed to the highest program state is performed based on a predetermined value, and after the preprogram has been performed, a main program for the target memory cells to be programmed is performed. 1. A semiconductor memory device comprising:a memory cell array a plurality of memory cells each of which stores N-bit data (N is an integer greater than 1);a peripheral circuit configured to perform a program operation to the memory cells in the memory cell array; anda control logic configured to control the peripheral circuit and the memory cell array such that, during a program operation to target memory cells to be programmed among the memory cells, a preprogram is performed to memory cells to be programmed to a highest program state among the target memory cells based on a preprogram reference voltage, and then a main program is performed to the target memory cells.2. The semiconductor memory device according to claim 1 ,wherein each of the target memory cells stores 2-bit data and is initially in an erase state, andwherein the control logic controls the peripheral circuit and the memory cell array such that a preprogram is performed to memory cells to be programmed to the highest program state among the target memory cells based on a first reference voltage corresponding to the highest program state.3. The semiconductor memory device according to claim 1 ,wherein each of the target memory cells stores 2-bit data and is ...

Multi-level cell memory device and operating method thereof

According to an example embodiment of inventive concepts, an operating method of a non-volatile memory device includes: performing a first hard decision read operation that includes applying a first voltage if a selected word line of the non-volatile memory device; storing a result of the first hard decision read operation at a first latch of a page buffer in the non-volatile memory device; performing a second hard decision read operation that includes applying a second voltage to the selected word line, the second voltage being higher than the first voltage; and generating a first soft decision value using a result of the first hard decision read operation stored at the first latch.

Memory, display device including the same, and writing method of the same

A memory is provided, which comprises an electrically erasable and programmable read only memory (EEPROM) configured to store an operation system and to be rewritable in response to a write operation signal, an address comparator configured to be connected to Inter Integrated Circuit (I2C) lines and output the write operation signal to the EEPROM in response to an external signal, a digital-to-analog converter (DAC) unit configured to determine whether to connect a DAC resistor and the I2C lines in response to the external signal and a pull-up resistor unit configured to be connected to the I2C lines.

Memory device, memory module, and memory system

A memory device includes a memory cell array, a data pattern providing unit, and a write circuit. The memory cell array includes a plurality of memory regions. The data pattern providing unit is configured to provide a predefined data pattern. The write circuit is configured to, when a first write command and an address signal are received from an external device, write the predefined data pattern provided from the data pattern providing unit to a memory region corresponding to the address signal.

MEMORY SYSTEM

According to one embodiment, a memory system includes a non-volatile memory and a memory controller. The non-volatile memory includes a plurality of groups, each including a plurality of memory cells. The memory controller is configured to determine whether to execute a refresh process for a first group based on whether a first temperature in a write process for the first group and a second temperature after the write process for the first group satisfy a first condition. 1. A memory system comprising:a non-volatile memory including a plurality of groups, each of the plurality of groups including a plurality of memory cells, the plurality of groups including at least a first group; anda memory controller configured todetermine whether to execute a refresh process for the first group based on whether a first temperature in a write process for the first group and a second temperature after the write process for the first group satisfy a first condition.2. The memory system according to claim 1 , whereinthe memory controller is configured todetermine to execute the refresh process for the first group when the first temperature is equal to or lower than a first threshold value and the second temperature is equal to or higher than a second threshold value, the second threshold value being higher than the first threshold value.3. The memory system according to claim 2 , whereinthe memory controller is configured tomake the second threshold value lower upon a degree of wear-out of the first group being equal to or higher than a third threshold value.4. The memory system according to claim 3 , whereinthe degree of wear-out of the first group is the number of write-and-erase cycles with respect to the first group.5. The memory system according to claim 2 , whereinthe memory controller is configured tomake the first threshold value higher upon a degree of wear-out of the first group being equal to or higher than a fourth threshold value.6. The memory system according to claim ...

MEMORY DEVICE AND METHOD OF OPERATING THE MEMORY DEVICE

The present technology relates to an electronic device. A memory device configured to perform a sensing operation based on a charge degree of a sensing node includes a memory cell array including a plurality of memory cells, a peripheral circuit including a page buffer connected to a selected memory cell among the plurality of memory cells through a bit line, and configured to perform a sensing operation on the selected memory cell, and control logic configured to control the peripheral circuit to precharge a source line among lines connected to the memory cell array and perform the sensing operation based on a degree at which a sensing node in the page buffer is charged, during the sensing operation. 1. A memory device comprising:a memory cell array including a plurality of memory cells;a peripheral circuit including a page buffer connected to a selected memory cell among the plurality of memory cells through a bit line, and configured to perform a sensing operation on the selected memory cell; anda control logic configured to control the peripheral circuit to precharge a source line among lines connected to the memory cell array and perform the sensing operation based on a degree at which a sensing node in the page buffer is charged, during the sensing operation.2. The memory device of claim 1 , wherein the page buffer includes a sensing node charge controller connected to the sensing node to discharge the sensing node.3. The memory device of claim 2 , wherein the sensing node charge controller discharges the sensing node after receiving a sensing command from outside before the sensing operation corresponding the sensing command.4. The memory device of claim 3 , wherein the sensing node charge controller is disconnected from the sensing node when the sensing operation is started after the sensing node is discharged.5. The memory device of claim 1 , wherein the sensing node is sequentially charged from a ground voltage.6. The memory device of claim 1 , wherein ...

MEMORY DEVICE AND OPERATING METHOD THEREOF

A memory device having improved performance includes: a plurality of memory cells programmed to one of a plurality of program states divided based on a threshold voltage; and a plurality of page buffers coupled to the plurality of memory cells through a plurality of bit lines. Each of the plurality of page buffers includes a latch for storing data sensed from a corresponding bit line among the plurality of bit lines, and discharges the corresponding bit line while performing a latch setting operation including setting data stored in the latch in a verify operation on the plurality of program states. 1. A memory device comprising:a plurality of memory cells programmed to one of a plurality of program states divided based on a threshold voltage; anda plurality of page buffers coupled to the plurality of memory cells through a plurality of bit lines,wherein each of the plurality of page buffers includes a latch configured to store data sensed from a corresponding bit line among the plurality of bit lines, and discharges the corresponding bit line while performing a latch setting operation including setting data stored in the latch in a verify operation on the plurality of program states.2. The memory device of claim 1 , wherein each of the plurality of page buffers includes:a first transistor connected between a common sensing node and a first node connected to the corresponding bit line;a second transistor connected between the common sensing node and a second node connected to a power voltage; anda third transistor connected between the first node and a reference power source.3. The memory device of claim 2 , wherein claim 2 , when discharging the corresponding bit line claim 2 , each of the plurality of page buffers is configured to turn off the first transistor claim 2 , and apply the reference power source to the first node through the third transistor.4. The memory device of claim 2 , wherein claim 2 , when discharging the corresponding bit line claim 2 , each of ...

ELECTRONIC DEVICE AND MEMORY CONTROLLER AND ASSOCIATED ACCESSING METHOD

The present invention provides a memory controller including an artificial intelligence (AI) module and a microprocessor. In the operations of the memory controller, the AI module receives a read command from a host device, and generates an auxiliary command according to the read command. The microprocessor is configured to select a first L2P mapping table according to a logical address included in the read command, and refer to the first L2P mapping table to read data from a memory module. The microprocessor is further configured to read a second L2P mapping table from the memory module according to the auxiliary command, wherein the second L2P mapping table does not include the logical address included in the read command. 1. A memory controller , comprising:an artificial intelligence (AI) module, to receive a read command from a host device, and to generate an auxiliary command according to the read command and at least one decision logic; anda microprocessor, coupled to the AI module, to select a first logical address to physical address mapping table (L2P mapping table) according to a logical address included in the read command, and to refer to the first L2P mapping table to read data from a memory module;a buffer memory, coupled to the microprocessor, to buffer a second L2P mapping table from the memory module according to the auxiliary command, wherein the second L2P mapping table does not include the logical address included in the read command.2. The memory controller of claim 1 , wherein the buffer memory stores the second L2P mapping table from the memory module before the microprocessor receives an access command that requires the second L2P mapping table.3. The memory controller of claim 1 , wherein before the memory controller receives the read command from the host device claim 1 , the AI module receives a plurality of specific read commands associated with the read command many times to generate/update the at least one decision logic.4. The memory ...

Data Storage Device and Data Writing Method Thereof

The present invention provides a data storage device including a flash memory and a controller. The controller receives a plurality of write commands and a plurality of data sectors from the host. During the period of receiving the data sectors, the controller records that the received data sectors have not been confirmed when the total size of received data sectors has not yet reached a predetermined size, writes a plurality of specific data sectors of the data sectors, which have been received from the host, into the flash memory and transmits a plurality of write-confirm signals corresponding to the specific data sectors to the host when the total size of received data has reached the predetermined size. 1. A data storage device , comprising:a flash memory; anda controller, receiving a plurality of write commands arranged to write a plurality of data sectors into the flash memory from a host, receiving the data sectors from the host in sequence according to the received write commands, wherein during the period of receiving the data sectors, the controller records that the received data sectors have not been confirmed when total size of received data sectors has not reached a predetermined size, writes a plurality of specific data sectors of the data sectors, which have been received from the host, into the flash memory when the total size of received data sectors has reached the predetermined size, and transmits a plurality of write-confirm signals corresponding to the specific data sectors to the host after all of the specific data sectors are written into the flash memory.2. The data storage device as claimed in claim 1 , wherein the predetermined size is equal to the write unit of the flash memory.3. The data storage device as claimed in claim 2 , wherein the write unit of the flash memory is a page.4. The data storage device as claimed in claim 1 , wherein the data storage device operates in a cache-off mode of the specification of Embedded Multi Media Card ...

METHOD FOR PROGRAMMING 3D NAND FLASH MEMORY

The present disclosure relates to a method for programming a 3D NAND flash memory, which includes: S) providing a 3D flash memory array, and eliminating residual charges; S) strobing a bit line where an upper sub-storage module is located; S) applying a drain voltage to the drain of a to-be-programmed memory cell, and floating a source thereof; S) applying a programming voltage to the gate of the to-be-programmed memory cell, to complete programming; and S) after completing the programming of the upper sub-storage module, and when the upper sub-storage module keeps a programmed state, strobing a bit line where a lower sub-storage module is located, and repeating operation S) and operation S) to achieve programming of the lower sub-storage module. In the method for programming a 3D NAND flash memory according to the present disclosure, programming is completed based on tertiary electron collision. 1. A method for programming a 3D NAND flash memory , comprising:{'b': '1', 'S) providing a 3D NAND flash memory array having a plurality of storage modules each of which including an upper sub-storage module and a lower sub-storage module, and eliminating residual charges in the 3D NAND flash memory array;'}{'b': '2', 'S) strobing a bit line where the upper sub-storage module is located, to program a to-be-programmed memory cell in the upper sub-storage module;'}{'b': '3', 'S) applying a drain voltage to the drain of the to-be-programmed memory cell, and floating the source of the to-be-programmed memory cell, to generate primary electrons in the to-be-programmed memory cell, wherein the primary electrons accelerate to collide with a substrate to generate secondary electrons;'}{'b': '4', 'S) applying a programming voltage to the gate of the to-be-programmed memory cell, to enable the secondary electrons to generate tertiary electrons and to inject the tertiary electrons into a floating gate of the to-be-programmed memory cell, to complete programming; and'}{'b': 5', '3', '4 ...

Non-volatile memory device for performing precharge to cell string and program method thereof

A non-volatile memory device including a memory cell array including a plurality of cell strings, wherein each cell string of the plurality of cell stings includes a string selection transistor, a plurality of memory cells, and a ground selection transistor connected in series between a bit line and a common source line; and a control circuit configured to perform a program operation on a selected memory cell from among the plurality of memory cells and pre-charge a selected cell string including the selected memory cell in a pre-charge section included in a verification section, wherein the selected cell string is pre-charged as a first pre-charge voltage is applied to a selected bit line connected to the selected memory cell.

MEMORY CONTROLLER, MEMORY SYSTEM WITH IMPROVED THRESHOLD VOLTAGE DISTRIBUTION CHARACTERISTICS, AND OPERATION METHOD

A memory controller includes an over-program controller that preprograms and then erases the memory cells such that each of the memory cells has a first threshold voltage level, wherein fast cells are detected among the memory cells according to a threshold voltage less than or equal to a second threshold voltage less than the first threshold voltage, and a processor that generates fast cell information identifying the fast cells among the memory cells and stores the fast cell information in a buffer. The over-program controller controls the over-programming of the fast cells and normal programming of normal cells among the memory cells based on the fast cell information stored in the buffer.

NON-VOLATILE MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE DEVICE, AND METHOD OF OPERATING THE DEVICE

A non-volatile memory device includes a memory cell array including memory cells, a page buffer circuit including page buffers respectively connected to bit lines, a buffer memory, and a control logic configured to control a read operation on the memory cells. In the read operation, the control logic obtains valley search detection information including read target block information and word line information by performing a valley search sensing operation on a distribution of threshold voltages of the memory cells, obtains a plurality of read levels using a read information model by inputting the valley search detection information into the read information model, and performs a main sensing operation for the read operation.

Storage device including nonvolatile memory device, operating method of storage device, and operating method of electronic device including nonvolatile memory device

Disclosed is a storage device which includes a nonvolatile memory device and a memory controller, and an operating method of the storage device includes sending, at the memory controller, a first read command and first offset information to the nonvolatile memory device, performing, at the nonvolatile memory device, first read operations based on the first read command and the first offset information, sending, at the nonvolatile memory device, a result of the first read operations as first data to the memory controller, sending, at the memory controller, a second read command, read voltage levels, and second offset information to the nonvolatile memory device, performing, at the nonvolatile memory device, second read operations based on the second read command, the read level information, and the second offset information, and sending, at the nonvolatile memory device, results of the second read operations as second data to the memory controller.

Nonvolatile memory device for invalidating data stored therein, memory system including the same, and operating method thereof

A memory device includes a plurality of word lines and a plurality of bit lines intersecting the word lines, a memory cell array comprising a plurality of memory cells coupled between the word lines and the bit lines at intersections between the word lines and the bit lines, respectively, an address decoder suitable for decoding an address to access a memory cell selected among the memory cells, and a controller suitable for writing and reading data to and from the selected memory cell by applying voltages to the word lines and bit lines, wherein the controller invalidates data stored in memory cells coupled to a target word line among the word lines by applying an invalidation voltage to the target word line for a set time.

CONTROLLER AND METHOD OF OPERATING THE SAME

A controller controls an operation of a semiconductor memory device including a reference storage area and a normal storage area. The controller includes a power supply sensor, a command generator, and a refresh count manager. The power supply sensor generates a power-on signal indicating that a memory system including the controller is powered-on. The command generator generates a read command for reading reference data stored in the reference storage area in response to the power-on signal and transfer the read command to the semiconductor memory device. The refresh count manager analyzes the read reference data received from the semiconductor memory device and determines whether a threshold voltage distribution of memory cells included in the reference storage area is changed. The command generator controls the semiconductor memory device to perform a refresh operation on the reference data stored based on a result of the determination of the refresh count manager. 1. A controller that controls an operation of a semiconductor memory device including a reference storage area and a normal storage area , the controller comprising:a power supply sensor configured to generate a power-on signal indicating that a memory system including the controller is powered-on;a command generator configured to generate a read command for reading reference data stored in the reference storage area in response to the power-on signal and transfer the read command to the semiconductor memory device; anda refresh count manager configured to analyze the read reference data received from the semiconductor memory device and determine whether a threshold voltage distribution of memory cells included in the reference storage area is changed,wherein the command generator controls the semiconductor memory device to perform a refresh operation on the reference data stored in the reference storage area based on a result of the determination of the refresh count manager.2. The controller of claim ...

NON-VOLATILE COMPUTER DATA STORAGE PRODUCTION-LEVEL PROGRAMMING

A non-volatile computer data storage programming system includes a scan chain modification configured to receive a default model defining a scan chain of an industry standardized device. A controller is in signal communication with the scan chain modification system, and is configured to program an industry standardized device. A non-volatile computer data storage device is configured to receive data from the industry standardized device. The scan chain modification system modifies the default model to generate a new model including a reduced scan chain, and the controller programs the industry standardized device based on the new model such that the industry standardized device is programmed with the reduced scan chain. 1. A non-volatile computer data storage programming system comprises:a scan chain modification system configured to receive a default model defining a scan chain of an industry standardized device;a controller in signal communication with the scan chain modification system, the controller configured to program an industry standardized device; anda non-volatile computer data storage device configured to receive data from the industry standardized device,wherein the scan chain modification system modifies the default model to generate a new model including a reduced scan chain, andwherein the controller programs the industry standardized device based on the new model such that the industry standardized device is programmed with the reduced scan chain.2. The system of claim 1 , wherein the industry standardized device having the new scan chain is configured to program the non-volatile computer data storage device.3. The system of claim 2 , wherein the scan chain defines a first register length claim 2 , and wherein the scan chain modification system includes a chain modification module configured to modify the default model to generate the new model defining a new scan chain that defines a second register length that is less than the first register ...

METHOD OF WRITING DATA IN NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY DEVICE PERFORMING THE SAME AND METHOD OF OPERATING MEMORY SYSTEM USING THE SAME

In a method of writing data in a nonvolatile memory device, a write command, a write address and write data to be programmed are received. Offset information representing a verification level is received. The offset information is provided when the write data corresponds to a distribution deterioration pattern by checking an input/output (I/O) pattern of the write data. When the offset information is received, the write data is programmed based on the offset information such that at least one state among a plurality of states included in a distribution of threshold voltages of memory cells in which the write data is stored is changed. 1. A method of writing data in a nonvolatile memory device , the method comprising:receiving a write command, a write address and write data to be programmed;receiving offset information representing a verification level, the offset information being provided when the write data corresponds to a distribution deterioration pattern by checking an input/output (I/O) pattern of the write data; andwhen the offset information is received, programming the write data based on the offset information such that at least one state among a plurality of states included in a distribution of threshold voltages of memory cells in which the write data is stored is changed.2. The method of claim 1 , wherein the distribution deterioration pattern includes a first deterioration pattern associated with data retention characteristic and a second deterioration pattern associated with read disturbance characteristic.3. The method of claim 2 , wherein:when the write data is write cold data that is written less than a first number of times, it is determined that the write data corresponds to the first deterioration pattern, andwhen the write data is read hot data that is read more than a second number of times, it is determined that the write data corresponds to the second deterioration pattern.4. The method of claim 2 , wherein:the plurality of states include a ...

ADDITIVE LIBRARY FOR DATA STRUCTURES IN A FLASH MEMORY

Systems and methods for managing data structures in a flash memory. A library is provided that supports read requests and write requests. The library allows reads and writes to be implemented without requiring the client to understand how the data structure is implemented in the flash memory. 1receiving a write request from a client at the flash memory, wherein the flash memory includes a controller and a library that includes a plurality of calls that are performed by the controller, wherein the controller is configured to perform the write request wherein the write request is to write an update to a data structure stored in the flash memory in accordance with the particular call;determining, by the controller, how to implement the write request in the flash memory, wherein the controller overwrite a location in the flash memory when an overwrite operation can be performed, wherein the update is written to an in-memory table or to a new location in the flash memory when the overwrite operation cannot be performed.. A method for writing data to a data structure implemented in a flash memory, the method comprising: This application is a Continuation of U.S. patent application Ser. No. 15/196,283 filed Jun. 29, 2016 and issued as U.S. Pat. No. 10,146,438 on Dec. 4, 2018, the disclosure of which is incorporated by reference herein in its entirety.Embodiments of the invention relate to a flash memory and to systems and methods for processing datasets including large datasets and data structures. More particularly, embodiments of the invention relate to a library that support the implementation of data structures in a flash memory and methods for implementing data structures in a flash memory.As the amount of data in computing systems continues to increase, there is a strong desire for improvements that allows the datasets to be efficiently processed. DRAM (Dynamic Random Access Memory) and the like are often too small to efficiently process large data sets. Algorithms ...

PAGE WRITES FOR TRIPLE LEVEL CELL FLASH MEMORY

A method for page writes for triple or higher level cell flash memory is provided. The method includes receiving data in a storage system, from a client that is agnostic of page write requirements for triple or higher level cell flash memory, wherein the page write requirements specify an amount of data and a sequence of writing data for a set of pages to assure read data coherency for the set of pages. The method includes accumulating the received data, in random-access memory (RAM) in the storage system to satisfy the page write requirements for the triple or higher level cell flash memory in the storage system. The method includes writing at least a portion of the accumulated data in accordance with the page write requirements, from the RAM to the triple level cell, or the higher level cell, flash memory in the storage system as an atomic write. 1. A method for page writes for triple level cell or higher level cell flash memory , comprising:receiving, in a storage system, data from a client that is independent of page write requirements for flash memory;accumulating an amount of the data in random-access memory (RAM) in the storage system to satisfy the page write requirements for a portion of triple level cell, or higher level cell, flash memory in the storage system; andwriting at least a lower page and an upper page in accordance with the page write requirements, from the RAM to the portion of triple level cell, or the higher level cell, flash memory in the storage system as an atomic write.2. The method of claim 1 , further comprising:supporting the atomic write with an energy reserve.3. The method of claim 1 , further comprising:writing further data to a portion of flash memory in the storage system having page write requirements differing from the portion of triple level cell, or the higher level cell, flash memory.4. The method of claim 1 , wherein the client is one of a client that is external to the storage system claim 1 , sending user data claim 1 , or ...

PROGRAMMING INTERRUPTION MANAGEMENT

The present disclosure is related to programming interruption management. An apparatus can be configured to detect an interruption during a programming operation and modify the programming operation to program a portion of the memory array to an uncorrectable state in response to detecting the interruption. 1. An apparatus , comprising:a memory array; anda controller configured to:detect an interruption during a programming operation; andmodify the programming operation to program a portion of the memory array to an uncorrectable state in response to detecting the interruption.2. The apparatus of claim 1 , wherein the controller is configured to detect the interruption during the programming operation by detecting a signal toggle using a number of trims set in the controller.3. The apparatus of claim 1 , wherein the controller is configured to modify the programming operation by setting data latches on all active pages to accept a programming signal.4. The apparatus of claim 3 , wherein the controller is configured to modify the programming operation by providing the programming signal to program all memory cells of the active pages.5. The apparatus of claim 3 , wherein the controller is configured to detect and flag each of the pages programmed to the uncorrectable state as being programmed during the interruption in the programming operation.6. The apparatus of claim 1 , wherein the controller is configured to move data from the block having the pages programmed to the uncorrectable state to a new block.7. The apparatus of claim 1 , wherein the controller is configured to detect pages programmed to the uncorrectable state as being corrupt.8. A method for managing a programming interruption claim 1 , comprising:detecting an interruption in a programming operation; andmodifying the programming operation in response to detecting the interruption in the programming operations by providing a modified programming signal that programs active pages of the programming ...

OPTIMIZATION OF REFERENCE VOLTAGES IN A NON-VOLATILE MEMORY (NVM)

Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). Data are stored to and retrieved from a group of memory cells in the NVM using a controller circuit. The data are retrieved using a first set of read voltages which are applied to the respective memory cells. The first set of read voltages are accumulated into a history distribution, which is evaluated to arrive at a second set of read voltages based upon characteristics of the history distribution. A calibration operation is performed on the memory cells using the second set of read voltages as a starting point. A final, third set of read voltages is obtained during the calibration operation to provide error rate performance at an acceptable level. The third set of read voltages are thereafter used for subsequent read operations. 1. A method comprising:storing data to a group of memory cells in a non-volatile memory (NVM);reading the data from the group of memory cells by applying a first set of read voltages thereto;accumulating the first set of read voltages into a history distribution; andcalibrating the group of memory cells by selecting a second set of read voltages based on the history distribution, adjusting the second set of read voltages to arrive at a third set of read voltages, and using the third set of read voltages to subsequently read the data from the group of memory cells.2. The method of claim 1 , wherein the first set of read voltages is characterized as multiple sets of read voltages having different voltage levels applied during each of a succession of read operations in which the data are read from the group of memory cells.3. The method of claim 1 , wherein the accumulating step comprises arranging the first set of read voltages into a histogram claim 1 , performing a curve fit operation upon the histogram claim 1 , and selecting the second set of read voltages as a midpoint of the curve fit operation.4. The method of ...

STORAGE DEVICE AND OPERATING METHOD THEREOF

A storage device includes: a memory device including a plurality of memory cells configured to store data and a plurality of word lines connected to the plurality of memory cells and a memory controller in communication with the memory device and configured to control the memory device, including controlling the memory device to perform a read operation perform, upon a failure of the read operation on the memory cell, a read retry operation by changing the read voltage based on a history read table, and wherein the memory controller is further configured to update the history read table, upon a success of the read retry operation, based on whether the word line connected to the memory cell is a last programmed word line according to a program order among word lines connected to the group of memory cells. 1. A storage device , comprising:a memory device including a plurality of memory cells configured to store data and a plurality of word lines connected to the plurality of memory cells; anda memory controller in communication with the memory device and configured to control the memory device, including controlling the memory device to (1) perform a read operation on a group of memory cells using a read voltage on a memory cell and (2) perform, upon a failure of the read operation on the memory cell, a read retry operation to perform another read operation on the memory cell by changing the read voltage based on a history read table that is stored in at least one of the memory device or the memory controller and includes information on read voltages, andwherein the memory controller is further configured to update the history read table, upon a success of the read retry operation, based on whether the word line connected to the memory cell is a last programmed word line according to a program order among word lines connected to the group of memory cells.2. The storage device of claim 1 , wherein the memory controller is further configured to update the history read ...

ADDITIVE LIBRARY FOR DATA STRUCTURES IN A FLASH MEMORY

Systems and methods for managing data structures in a flash memory. A library is provided that supports read requests and write requests. The library allows reads and writes to be implemented without requiring the client to understand how the data structure is implemented in the flash memory. 1receiving a request from a client at a library to perform an operation in the flash memory without requiring the client to know that the operation is being performed the flash memory and without requiring the client to specify how the operation is performed, wherein the library includes a plurality of calls for performing read operations and write operations in the flash memory;when the request is a write request to write first data, performing the write request by writing the first data with an overwrite operation when the overwrite operation can be performed and performing the write request by writing the first data to an in-memory table or to a new location in the flash memory when the overwrite operation cannot be performed; andwhen the request is a read request for second data, reading the second data from the flash memory, wherein the second data is updated from the in-memory table when at least a portion of the second data is present in the in-memory table and has not been written to the flash memory.. A method for interacting with data stored in a flash memory, the method comprising: This application is a Continuation of U.S. patent application Ser. No. 15/196,283 filed Jun. 29, 2016 and issued as U.S. Pat. No. 10,146,438 on Dec. 4, 2018, the disclosure of which is incorporated by reference herein in its entirety.Embodiments of the invention relate to a flash memory and to systems and methods for processing datasets including large datasets and data structures. More particularly, embodiments of the invention relate to a library that support the implementation of data structures in a flash memory and methods for implementing data structures in a flash memory.As the ...

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING SEMICONDUCTOR MEMORY DEVICE

According to one embodiment, a semiconductor memory device includes: first and second select transistors; first and second select gate lines; first and second interconnects; first and second memory cell transistors; and first and second word lines. In a write operation, after execution of a verify operation, in a period in which the second select transistor is ON, a voltage of the first word line changes from a first voltage to a second voltage and a voltage of the second word line changes from a third voltage applied in the verify operation to a fourth voltage, and after the voltage of the first word line changes to the second voltage and the voltage of the second word line changes to the fourth voltage, a voltage of the second select gate line changes from a fifth voltage to a sixth voltage. 1. A semiconductor memory device comprising:a first select transistor;a first select gate line coupled to a gate of the first select transistor;a first interconnect coupled to the first select transistor;a second select transistor;a second select gate line coupled to a gate of the second select transistor;a second interconnect coupled to the second select transistor;first and second memory cell transistors coupled between the first select transistor and the second select transistor;a first word line coupled to the first memory cell transistor; anda second word line coupled to the second memory cell transistor, whereinin a write operation on the first memory cell transistor which includes a program operation and a verify operation, after execution of the verify operation, in a period in which the second select transistor is ON, a voltage of the first word line changes from a first voltage to a second voltage and a voltage of the second word line changes from a third voltage, which is applied in the verify operation, to a fourth voltage, andafter the voltage of the first word line changes to the second voltage and the voltage of the second word line changes to the fourth voltage ...

MEMORY SYSTEM AND OPERATING METHOD THEREOF

A memory device includes a memory block including a plurality of pages, a peripheral circuit configured to perform a first program operation for storing first page data and a second program operation for storing second page data after the first program operation, a status register configured to store status information, a cache program operation controller configured to control the peripheral circuit to load the second page data from an external controller when the first program operation is being performed, and a status register controller configured to store in the status register first failure information indicating whether the first program operation passes, store in the status register validity information indicating whether the first failure information is valid information within a predetermined time period from when the second program operation starts, and provide the external controller with the status information including the first failure information and the validity information. 1. A memory device , comprising:a memory block including a plurality of pages;a peripheral circuit configured to perform a first program operation for storing first page data in a first page among the plurality of pages and perform a second program operation for storing second page data in a second page among the plurality of pages after the first program operation;a status register configured to store status information including information related to each of the first program operation and the second program operation;a cache program operation controller configured to control the peripheral circuit to load the second page data from an external controller when the first program operation is being performed; anda status register controller configured to:store, in the status register, first failure information indicating whether the first program operation passes or fails;store, in the status register, validity information indicating whether the first failure information is ...

Memory device and method of operating the same

Provided herein is a memory device and a method of operating the same. The memory device includes a plurality of memory blocks, each including a plurality of memory cells, and a peripheral circuit configured to perform program operations, read operations and erase operations on the plurality of memory blocks. The memory device also includes control logic configured to, when the read operation is performed on any one of the plurality of memory blocks, set a channel initialization time used to initialize channels of memory cells included in the one memory block based on an inhibition count value indicating a number of times that a corresponding operation is inhibited from being performed on the one memory block, and control the peripheral circuit so that the channels are initialized during the channel initialization time before the read operation is performed.

Method and Apparatus for Reading a Flash Memory Device

A method for reading a flash memory device includes storing configuration files of reliability-state Classification Neural Network (CNN) models and Regression Neural Network (RNN) inference models, and storing reliability-state tags corresponding to reliability states. The current number of P/E cycles is identified and a reliability-state CNN model is selected corresponding to the current number of P/E cycles. A neural network operation of the selected reliability-state CNN model is performed to identify a predicted reliability state. Corresponding reliability-state tags are identified and a corresponding RNN inference model is selected. A neural network operation of the selected RNN inference model is performed, using the reliability-state tags as input, to generate output indicating the shape of a threshold-voltage-shift read-error (TVS-RE) curve. Threshold Voltage Shift Offset (TVSO) values are identified corresponding to a minimum value of the TVS-RE curve and a read is performed using a threshold-voltage-shift read at the identified TVSO values. 1. A method for reading a flash memory device comprising:storing configuration files of a plurality of reliability-state classification neural network (CNN) models, configuration files of a plurality of regression neural network (RNN) inference models and a plurality of sets of reliability-state tags, each set of reliability-state tags associated with one of a plurality of reliability states and each of the reliability-state CNN models associated with a range of program and erase (P/E) cycles;monitoring the operation of the flash memory device to identify a current number of P/E cycles of the flash memory device;selecting one of the reliability-state CNN models associated with a range of P/E cycles corresponding to the current number of P/E cycles;performing a neural network operation of the selected reliability-state CNN model to identify a predicted reliability state;identifying the set of reliability-state tags ...

Relinking Scheme in Sub-Block Mode

Aspects of a storage device including a memory and a controller are provided which allow sub-blocks with different sub-block addresses to be linked across multiple planes to form metablocks. The memory includes multiple blocks in different planes, where each of the blocks includes multiple sub-blocks. The controller links a first sub-block in a first plane and a second sub-block in a second plane with different sub-block addresses to form the metablock. After forming the metablock, the controller programs different word lines in the first and second sub-blocks when writing data to the metablock. Thus, the controller may write data to linked or relinked metablocks with different sub-block addresses, thereby improving die yield and memory capacity of the storage device.

METHOD FOR OPERATING LOW-CURRENT EEPROM ARRAY

A method for operating a low-current EEPROM array is disclosed. The EEPROM array comprises bit line groups, word lines, common source lines, and sub-memory arrays. Each sub-memory array includes a first memory cell and a second memory cell. The first memory cell is connected with one bit line of a first bit line group, a first common source line, and a first word line. The second memory cell is connected with the other bit line of the first bit line group, the first common source line, and a second word line. The first and second memory cells are operation memory cells and symmetrically arranged at two sides of the first common source line. The method uses special biases to perform the bytes writing and erasing with low current, low voltage and low cost. 1. A method for operating a low-current electrically erasable programmable read only memory array , wherein said low-current electrically erasable programmable read only memory (EEPROM) array comprises a plurality of parallel bit lines; a plurality of parallel word lines; a plurality of parallel common source lines; and a plurality of sub-memory arrays , and wherein said bit lines are divided into a plurality of bit line groups including a first bit line group , and wherein said word lines are vertical to said bit lines and include a first word line and a second word line , and wherein said common source lines are parallel to said word lines and include a first common source line , and wherein each said sub-memory array is connected with one said bit line group , two said word lines and one said common source line , and wherein each said sub-memory array includes a first memory cell and a second memory cell , and wherein said first memory cell is connected with said first bit line group , said first common source line and said first word line , and wherein said second memory cell is connected with said first bit line group , said first common source line and said second word line , and wherein said first memory cell ...

USER DEVICE HAVING A HOST FLASH TRANSLATION LAYER (FTL), A METHOD FOR TRANSFERRING AN ERASE COUNT THEREOF, A METHOD FOR TRANSFERRING REPROGRAM INFORMATION THEREOF, AND A METHOD FOR TRANSFERRING A PAGE OFFSET OF AN OPEN BLOCK THEREOF

A user device includes a storage device including a flash memory; and a host connected to the storage device via an interface and adapted to transmit data to the storage device. The host provides the storage device with erase count information of the flash memory using a host flash translation layer (FTL), provides the storage device with reprogram information when the flash memory uses a reprogram method, or provides the storage device with page offset information of an open block of the flash memory. 1. A user device , comprising:a storage device including a flash memory; anda host connected to the storage device via an interface and adapted to transmit data to the storage device,wherein the host provides the storage device with erase count information of the flash memory using a host flash translation layer (FTL), provides the storage device with reprogram information When the flash memory uses a reprogram method, or provides the storage device with page offset information of an open block of the flash memory.2. The user device of claim 1 , wherein the flash memory includes a plurality of memory blocks claim 1 , andwherein the erase count information is a max erase count of erase counts of the memory blocks.3. The user device of claim 1 , wherein the host provides the storage device with the erase count information of the flash memory periodically or when the storage device is booted up.4. The user device of claim 1 , Wherein the storage device adjusts a read level of the flash memory using the erase count information.5. The user device of claim 1 , wherein the flash memory includes a plurality of block types claim 1 , and wherein the erase count information is a max erase count of each block type.6. The user device of claim 1 , wherein the host provides the storage device with the reprogram information using a program command field format.7. The user device of claim 6 , wherein the program command field format includes a storage address format claim 6 , and ...

NONVOLATILE MEMORY AND RELATED REPROGRAMMING METHOD

A method of reprogramming a nonvolatile memory device, comprising setting up bit lines of selected memory cells according to logic values of first and second latches of a page buffer connected to the bit lines, supplying a program pulse to the selected memory cells, performing a program verify operation on the selected memory cells using the first and second latches, and performing a predictive program operation on the selected memory cells according to a result of the program verify operation. In the predictive program operation, bit lines of the selected memory cells are setup according to a logic value of a third latch of the page buffer that corresponds to each of the selected memory cells. 1. A method of reprogramming a nonvolatile memory device , comprising:setting up bit lines of selected memory cells according to logic values of first and second latches of a page buffer connected to the bit lines;supplying a program pulse to the selected memory cells;performing a program verify operation on the selected memory cells using the first and second latches; andperforming a predictive program operation on the selected memory cells according to a result of the program verify operation,wherein in the predictive program operation, bit lines of the selected memory cells are setup according to a logic value of a third latch of the page buffer that corresponds to each of the selected memory cells.2. The method of claim 1 , wherein during performing the program verify operation claim 1 , verify voltages provided to wordlines of the selected memory cells are provided as three different levels.3. The method of claim 1 , wherein during the program verify operation claim 1 , verify voltages provided to wordlines of the selected memory cells are provided based on multiple groups that are identified by logic values stored in the first and second latches.4. The method of claim 1 , wherein the predictive program operation is performed after the selected memory cells are ...

Virtual otp pre-programming

Aspects of virtual one-time programmable (OTP) memory pre-programming are described. A device may include a logical sink destination, an OTP memory map, a virtual memory map, and a comparator. The OTP memory map may store one or more OTP logical values, and the virtual memory map may store one or more default virtual logical values. Generally, the virtual memory map may be predefined for various representative OTP scenarios including test and customer-specific values. Certain portions or outputs of the logical values stored in the OTP memory map and the virtual memory map may be compared by the comparator, and the logical result of the comparison may be output to the logical sink destination. In certain aspects, the portions or outputs of OTP and virtual memory maps that are compared may be determined based on various factors such as strap option settings, temperatures, voltages, or register values of the device.

MEMORY SYSTEM

A memory system according to an embodiment includes first to sixth word lines, a plurality of memory pillars and a control circuit. The control circuit performs an initial write operation in which a threshold voltage of a subject memory cell is increased from a first level to a second level, a first write operation after the initial write operation and a second write operation after the first write operation. The control circuit is configured to perform the initial write operation on the third memory cell and the fourth memory cells, the first write operation on the third memory cells, the first write operation on the fourth memory cells, the second write operation on the fifth memory cells, the second write operation on the sixth memory cells, and the initial write operation on the first memory cells and the second memory cells. 1. A memory system comprising:a first word line provided in a first layer;a second word line provided in the first layer and configured to be controlled independently from the first word line;a third word line provided in a second layer being adjacent to the first layer in a vertical direction;a fourth word line provided in the second layer and configured to be controlled independently from the third word line;a fifth word line provided in a third layer being adjacent to the second layer in the vertical direction;a sixth word line provided in the third layer and configured to be controlled independently from the fifth word line; [ sandwiched by the first word line and the second word line,', 'sandwiched by the third word line and the fourth word line,', 'sandwiched by the fifth word line and the sixth word line, and, 'each extending in the vertical direction to be'}, a first memory cell facing the first word line,', 'a second memory cell facing the second word line,', 'a third memory cell facing the third word line,', 'a fourth memory cell facing the fourth word line,', 'a fifth memory cell facing the fifth word line and', 'a sixth memory ...

STATIC RANDOM ACCESS MEMORY AND OPERATION METHOD THEREOF

A static random access memory including at least one memory cell is provided. The memory cell includes a first inverter, a second inverter, a first pass gate transistor, a second pass gate transistor, a first non-volatile memory, and a second non-volatile memory. The first inverter and the second inverter are coupled to each other. The first pass gate transistor is coupled between the first inverter and the first bit line. The second pass gate transistor is coupled between the second inverter and the second bit line. The first non-volatile memory is coupled between the first pass gate transistor and the first bit line. The second non-volatile memory is coupled between the second pass gate transistor and the second bit line. 1. A static random access memory , comprising at least one memory cell , wherein the memory cell comprises:a first inverter and a second inverter, wherein the first inverter and the second inverter are coupled to each other;a first pass gate transistor coupled between the first inverter and a first bit line;a second pass gate transistor coupled between the second inverter and a second bit line;a first non-volatile memory coupled between the first pass gate transistor and the first bit line; anda second non-volatile memory coupled between the second pass gate transistor and the second bit line.2. The static random access memory according to claim 1 , whereinthe first inverter comprises a first pull-up transistor and a first pull-down transistor coupled to each other, andthe second inverter comprises a second pull-up transistor and a second pull-down transistor coupled to each other.3. The static random access memory according to claim 1 , wherein each of the first non-volatile memory and the second non-volatile memory comprises a split gate flash memory.4. The static random access memory according to claim 3 , wherein each of the first non-volatile memory and the second non-volatile memory comprises:a first gate located on the substrate;a second ...

SEMICONDUCTOR STORAGE DEVICE

A semiconductor storage device includes a memory cell array includes a plurality of memory cell transistors, a plurality of word lines connected to gates of the memory cell transistors, a voltage generation circuit configured to generate a voltage applied to each of the word lines, and a control circuit configured to control an operation of the memory cell array. In a write operation for writing data to the memory cell array that includes multiple loops of a program operation and a verify operation, the control circuit controls an operation of the voltage generation circuit so that a rate of increase of a voltage applied to a non-selected word line at a beginning of the verify operation is different for at least two of the loops. 1. A semiconductor storage device comprising:a memory cell array including a plurality of memory cell transistors;a plurality of word lines connected to gates of the memory cell transistors;a voltage generation circuit configured to generate a voltage applied to each of the word lines; anda control circuit configured to control an operation of the memory cell array,wherein, in a write operation for writing data to the memory cell array that includes multiple loops of a program operation and a verify operation, the control circuit controls an operation of the voltage generation circuit so that a rate of increase of a voltage applied to a non-selected word line at a beginning of the verify operation is different for at least two of the loops.2. The semiconductor storage device according to claim 1 , wherein the rate of increase of the voltage applied to the non-selected word line at the beginning of the verify operation of a first loop is higher than the rate of increase of the voltage applied to the non-selected word line at the beginning of the verify operation of a second loop claim 1 , which is executed later than the first loop.3. The semiconductor storage device according to claim 2 , wherein the first loop is executed before all of the ...

Accessing a multi-level memory cell

Methods, systems, and devices for accessing a multi-level memory cell are described. The memory device may perform a read operation that includes pre-read portion and a read portion to access the multi-level memory cell. During the pre-read portion, the memory device may apply a plurality of voltages to a plurality of memory cells to identify a likely distribution of memory cells storing a first logic state. During the read portion, the memory device may apply a first read voltage to a memory cell based on performing the pre-read portion. The memory device may apply a second read voltage to the memory cell during the read portion that is based on the first read voltage. The memory device may determine the logic state stored by the memory cell based on applying the first read voltage and the second read voltage.

MEMORY CONTROLLER AND METHOD OF OPERATING THE MEMORY CONTROLLER

A memory controller that controls a memory device including a memory block includes an initial program controller configured to control the memory device to program at least one or more monitoring memory cells from among memory cells respectively connected to monitoring word lines from among a plurality of word lines connected to the memory block, a pre-read controller configured to generate a shifting information of a threshold voltage distribution of the monitoring memory cells based on a result of reading the monitoring memory cells before a read operation is performed on the memory block, and a pre-program controller configured to control the memory device to perform the read operation after applying a pre-program voltage having a voltage level determined according to the shifting information to the plurality of word lines. 1. A memory controller that controls a memory device including a memory block , the memory controller comprising:an initial program controller configured to control the memory device to program at least one or more monitoring memory cells from among memory cells respectively connected to monitoring word lines from among a plurality of word lines connected to the memory block;a pre-read controller configured to generate a shifting information of a threshold voltage distribution of the monitoring memory cells based on a result of reading the monitoring memory cells before a read operation is performed on the memory block; anda pre-program controller configured to control the memory device to perform the read operation after applying a pre-program voltage having a voltage level determined according to the shifting information to the plurality of word lines.2. The memory controller of claim 1 , wherein the monitoring word lines are most adjacent to a select line connected to the memory block.3. The memory controller of claim 1 , wherein the memory device further comprises:a voltage generator configured to generate a voltage to be applied to the ...

OPEN BLOCK-BASED READ OFFSET COMPENSATION IN READ OPERATION OF MEMORY DEVICE

Open block-based read offset compensation in read operation of memory device is disclosed. For example, a memory device includes an array of memory cells arranged in a plurality of blocks and a peripheral circuit coupled to the array of memory cells. The peripheral circuit is configured to, in response to a block of the plurality of blocks being an open block, perform a read operation on a memory cell of the array of memory cells in the block using a compensated read voltage. The compensated read voltage has an offset from a default read voltage of the block. 1. A memory device , comprising:an array of memory cells arranged in a plurality of blocks; anda peripheral circuit coupled to the array of memory cells and configured to, in response to a block of the plurality of blocks being an open block, perform a read operation on a memory cell of the array of memory cells in the block using a compensated read voltage, the compensated read voltage having an offset from a default read voltage of the block.2. The memory device of claim 1 , whereineach block of the plurality of blocks comprises a plurality of pages; andthe peripheral circuit is further configured to determine that the block is an open block if at least one page of the plurality of pages in the block is not programmed.3. The memory device of claim 2 , whereineach block of the plurality of blocks comprises a plurality of pages; andthe memory device further comprises a memory controller coupled to the peripheral circuit and configured to determine that the block is an open block if at least one page of the plurality of pages in the block is not programmed.4. The memory device of claim 2 , wherein the peripheral circuit comprises:a register configured to store open block information of one or more blocks of the plurality of blocks; andcontrol logic coupled to the register and configured to determine that the block is an open block based on the open block information stored in the register.5. The memory device of ...

SEMICONDUCTOR MEMORY DEVICE WITH WRITE DISTURB REDUCTION

A semiconductor memory device implements a write disturb reduction method to reduce write disturb on unselected memory cells by alternating the order of the write logical “1” step and write logical “0” step in the write operations of selected memory cells associated with the same group of bit lines. In one embodiment, a method in an array of memory cells includes performing write operation on the memory cells in one of the memory pages to store write data into the memory cells where the write operation includes a first write step of writing a data of a first logical state and a second write step of writing data of a second logical state; and performing the write operation for each row of memory cells by alternately performing the first write step followed by the second write step and performing the second write step followed by the first write step. 1. A method for reducing write disturb in an array of memory cells arranged in a plurality of memory pages , each memory page comprising memory cells arranged in rows and columns , the method comprising:selecting a row of memory cells in a first memory page for a write operation to store write data into the memory cells;determining a step order value indicative of a write step order of the write operation;in response to the step order value having a first logical state, performing the write operation by writing data of a first logical state in all the memory cells in the selected row followed by writing data of a second logical state in at least a subset of memory cells in the selected row in response to the write data; andin response to the step order value having a second logical state, performing the write operation by writing data of the second logical state in all the memory cells in the selected row followed by writing data of the first logical state in at least a subset of memory cells in the selected row in response to the write data.2. The method of claim 1 , further comprising:storing a step order value for ...

Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array having a plurality of memory cell transistors connected in series therein; a plurality of bit lines; and a control circuit for executing a read operation. The control circuit is configured capable of executing the read operation, the read operation charging the bit line and applying a read voltage to the control gate electrode of the memory cell transistor to determine whether the memory cell transistor is conductive and the bit line discharges or not. The control circuit is configured to, in the read operation, be capable of executing the read operation targeting the memory cell transistors connected to a portion of the plurality of bit lines, and not execute a charging operation in those other of the bit lines where the connected memory cell transistors are not targeted by the read operation.

SEMICONDUCTOR DEVICE, AND INFORMATION-PROCESSING DEVICE

According to one embodiment, a semiconductor device includes a non-volatile memory, a temperature measurement circuit that measures a temperature of the non-volatile memory, and a controller. The controller also writes information about the temperature which is measured by the temperature measurement circuit in the non-volatile memory together when writing data in the non-volatile memory. Further, the controller performs write-back processing of writing data, which is written at a temperature in a rewriting temperature range, back when the temperature measured by the temperature measurement circuit is not in the rewriting temperature range. 1. (canceled)2: A method of controlling a memory system including a non-volatile memory and a temperature measurement circuit , the method comprising:when writing data into the non-volatile memory, writing information about a temperature of the non-volatile memory which is measured by the temperature measurement circuit into the non-volatile memory along with the data; andin a case that the temperature at which the data has been written into the non-volatile memory is in a rewriting temperature range, performing write-back processing while a temperature measured by the temperature measurement circuit is not in the rewriting temperature range, the write-back processing being processing in which the data is re-written into the non-volatile memory.3: The method according to claim 2 , wherein the performing write-back processing includes:reading out the data written at a temperature in the rewriting temperature range; andwriting the read data into the non-volatile memory.4: The method according to claim 3 , whereinthe data includes a data body portion and a redundant portion, andin the writing the information, the information about the temperature which is measured at the time of the writing of the data in the redundant portion is stored when writing the data body portion.5: The method according to claim 2 , wherein the write-back ...

Memory system

A memory system has a memory cell array having a plurality of strings, the plurality of strings each having a plurality of memory cells connected in series, and a controller configured to perform control of transferring charges to be stored in the plurality of memory cells in the string or transferring charges according to stored data, between potential wells of channels in the plurality of memory cells.

SEMICONDUCTOR STORAGE DEVICE

A semiconductor storage device in an embodiment includes a plurality of planes each including a memory cell array, a voltage generation circuit configured to apply a first intermediate voltage to an adjacent word line adjacent to a selected word line in a former half of a program period and apply a second intermediate voltage higher than the first intermediate voltage to the adjacent word line in a latter half of the program period, a discharge circuit configured to feed a discharge current from the selected word line in a period corresponding to a period in which the second intermediate voltage is applied to the adjacent word line, and a control circuit configured to set a discharge characteristic of the discharge circuit according to a number of the planes. 1. A semiconductor storage device comprising:a plurality of planes each including a memory cell array configured by a plurality of memory cells, word lines connected to gates of the plurality of memory cells, and bit lines electrically connected to one ends of the plurality of memory cells via selection gate transistors respectively connected to the one ends of the plurality of memory cells;a voltage generation circuit capable of generating a voltage supplied to one or more of the memory cell arrays respectively included in the plurality of planes, the voltage generation circuit supplying a program voltage to a writing target selected word line in a program period and applying a first intermediate voltage to an adjacent word line adjacent to the selected word line in a former half of the program period and applying a second intermediate voltage higher than the first intermediate voltage to the adjacent word line in a latter half of the program period;a discharge circuit provided on a path between the voltage generation circuit and the selected word line and configured to feed a discharge current from the selected word line in a period corresponding to a period in which the second intermediate voltage is applied ...

MULTIPLE TIME PROGRAMMABLE MEMORY USING ONE TIME PROGRAMMABLE MEMORY AND ERROR CORRECTION CODES

The present invention relates to the field of digital memory, and in particular to a multiple-time programmable (MTP) memory employing error correction codes (ECC), the MTP memory being made up of one-time programmable (OTP) memory modules. Pointers to the memory address of currently in-use OTP memory blocks in use for each virtual MTP memory block are stored in OTP memory with an error correcting code. The pointers encode the memory addresses according to a scheme that ensure that only bit changes in a single direction are required in both the pointer data and the error correction code when the memory address is incremented. 1. Multiple-time programmable memory (MTP) comprising one-time programmable (OTP) memory and a plurality of virtual MTP memory blocks , the OTP memory comprising a plurality of OTP memory blocks , wherein:a plurality of the OTP memory blocks are reserved for each virtual MTP memory block;at any given time, each virtual MTP memory block is associated with one of the plurality of OTP memory blocks that are reserved for the virtual MTP memory block, wherein the current data of the virtual MTP memory block is stored in the associated OTP memory block;for each virtual MTP memory block, a pointer that identifies the OTP memory block that is associated with the virtual MTP memory block is stored elsewhere in the OTP memory; and programming a previously unprogrammed OTP memory block of the OTP memory blocks that are reserved for the first virtual MTP memory block with the new data; and', 'updating the pointer of the OTP memory block that is associated with the first virtual MTP memory block to identify the newly programmed OTP memory block;, 'the MTP memory is configured to program a first virtual MTP memory block of the plurality of virtual MTP memory blocks with new data bywherein the pointers of the OTP memory blocks that are associated with the virtual MTP memory blocks are stored with an error correcting code, and wherein the encoding scheme of ...

SEMICONDUCTOR STORAGE DEVICE

A semiconductor storage device includes a memory cell array including memory cell transistors connected in series between a bit line and a source line and word lines respectively connected to gates of the memory cell transistors. In the erasing operation to erase data stored in a selected memory cell transistor, while an erase voltage is applied to the bit line and the source line: a first voltage is applied to the word line connected to the gate of the selected memory cell transistor, a second voltage higher than the first voltage is applied to the word line connected to the gate of each memory cell transistor adjacent to the selected memory cell transistor, and a third voltage higher than the second voltage and lower than the erase voltage is applied to the word line connected to the gate of each memory cell transistor not adjacent to the selected memory cell transistor. 1. A semiconductor storage device comprising:a memory cell array including a plurality of memory cell transistors that are connected to each other in series between a bit line and a source line and a plurality of word lines respectively connected to gates of the memory cell transistors; anda control circuit configured to control an operation of the memory cell array, including an erasing operation, wherein a first voltage is applied to the word line connected to the gate of the selected memory cell transistor,', 'a second voltage higher than the first voltage is applied to the word line connected to the gate of the memory cell transistor adjacent to the selected memory cell transistor, and', 'a third voltage higher than the second voltage and lower than the erase voltage is applied to the word line connected to the gate of the memory cell transistor not adjacent to the selected memory cell transistor., 'in the erasing operation to erase data stored in a selected one of the memory cell transistors, an erase voltage is applied to the bit line and the source line, and while the erase voltage is ...

MANAGING ERROR-HANDLING FLOWS IN MEMORY DEVICES

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a block of the memory device, wherein the block is associated with a voltage offset bin, determining an order of a plurality of error-handling operations to be performed to recovery data associated with the read error, wherein the order is specified in a metadata table and is based on the voltage offset bin associated with the block, and performing at least one error-handling operation of the plurality of error-handling operations in the order specified by the metadata table. 1. A system comprising:a memory device; and detecting a read error with respect to data residing in a block of the memory device, wherein the block is associated with a voltage offset bin which defines a set of threshold voltage offsets to be applied to a base voltage read level during read operations;', 'determining an order of a plurality of error-handling operations to be performed to recovery data associated with the read error, wherein the order is specified in a metadata table and is based on the voltage offset bin associated with the block; and', 'performing at least one error-handling operation of the plurality of error-handling operations in the order specified by the metadata table., 'a processing device, operatively coupled to the memory device, to perform operations comprising2. The system of claim 1 , wherein the processing device is to perform further operations comprising:adjusting the order of the plurality of error-handling operations.3. The system of claim 1 , wherein the processing device is to perform further operations comprising:maintaining a record of read error rates for the voltage offset bin; andresponsive to detecting the read error rates satisfying a threshold criterion, adjusting a read voltage offset associated with at least one ...

SYSTEM AND METHOD FOR HANDLING MEMORY REPAIR DATA

In a system on chip (SOC) device, continuity of a memory repair signature chain, which is accessible by all enabled memory systems, is provided, even when certain memory systems are gated (off) for certain SOC configurations. A mechanism for converting between compressed and uncompressed memory repair data within the repair chain is provided so that memory systems that support either uncompressed memory repair data (such as ternary content addressable memories) or compressed memory repair data can be incorporated in the SOC. 1. An integrated circuit , comprising:first and second memory systems, wherein each memory system includes a memory module having an associated first repair register for receiving compressed memory repair data, and wherein the first repair registers are connected in series as a chain;a store for storing compressed memory repair data for the first and second memory modules; anda processor, operably coupled to the store, for fetching the compressed memory repair data from the store and shifting the fetched compressed memory repair data through the chain for reception by the first repair registers,wherein the first memory system includes a second repair register and a decoder, wherein the decoder is operably coupled between the second repair register and the first repair register of the first memory system, andwherein the first memory system shifts compressed memory repair data for its memory module from the first repair register through the decoder to the second repair register for storage therein as decompressed memory repair data.2. The integrated circuit of claim 1 , wherein the first memory system includes a state machine for shifting compressed memory repair data for its memory module from the first repair register through the decoder to the second repair register for storage therein.3. The integrated circuit of claim 1 , wherein the store is a one-time programmable read-only memory (OTPROM).4. The integrated circuit of claim 1 , wherein the ...

OPERATING METHOD OF STORAGE CONTROLLER USING COUNT VALUE OF DIRECT MEMORY ACCESS, STORAGE DEVICE INCLUDING STORAGE CONTROLLER, AND OPERATING METHOD OF STORAGE DEVICE

A method of operating a storage controller that communicates with a non-volatile memory device includes performing a first direct memory access (DMA) read operation on data stored in the non-volatile memory device, based on a first read voltage; updating a page count value of a DMA register, based on the first DMA read operation; determining whether data read by the first DMA read operation include an uncorrectable error; when it is determined that the data read by the first DMA read operation include the uncorrectable error, determining a second read voltage different from the first read voltage, based on the updated page count value of the DMA register, without an additional read operation on the data stored in the non-volatile memory device; and performing a second DMA read operation on the data stored in the non-volatile memory device, based on the second read voltage. 1. A method of operating a storage controller that communicates with a non-volatile memory device , the method comprising:performing a first direct memory access (DMA) read operation on data stored in the non-volatile memory device, based on a first read voltage;updating a page count value of a DMA register, based on the first DMA read operation;determining whether data read by the first DMA read operation include an uncorrectable error;when it is determined that the data read by the first DMA read operation include the uncorrectable error, determining a second read voltage different from the first read voltage, based on the updated page count value of the DMA register, without an additional read operation on the data stored in the non-volatile memory device; andperforming a second DMA read operation on the data stored in the non-volatile memory device, based on the second read voltage.2. The method as claimed in claim 1 , wherein the second read voltage is a read voltage optimized on a page corresponding to the first read voltage claim 1 , based on a difference between the updated page count ...

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device includes a semiconductor layer, a gate electrode, a gate insulating film disposed therebetween, first and second wirings connected to the semiconductor layer, and a third wiring connected to the gate electrode and is configured to execute a write operation, an erase operation, and a read operation. In the write operation, a write voltage of a first polarity is supplied between the third wiring and at least one of the first wiring or the second wiring. In the erase operation, an erase voltage of a second polarity is supplied between the third wiring and at least one of the first wiring or the second wiring. In the read operation, the write voltage or a voltage having a larger amplitude than that of the write voltage is supplied between the third wiring and at least one of the first wiring or the second wiring. 1. A semiconductor memory device comprising:a memory transistor; anda plurality of wirings connected to the memory transistor, wherein a semiconductor layer;', 'a gate electrode opposed to the semiconductor layer; and', 'a gate insulating film disposed between the semiconductor layer and the gate electrode, wherein, 'the memory transistor includes a first wiring connected to the semiconductor layer;', 'a second wiring connected to the semiconductor layer; and', 'a third wiring connected to the gate electrode, wherein, 'the plurality of wirings includethe gate insulating film includes oxygen (O) and hafnium (Hf) and has an orthorhombic crystalline structure, whereinthe semiconductor memory device is configured to execute a write operation, an erase operation, and a first read operation,in the write operation, a write voltage in a first polarity is supplied between the third wiring and at least one of the first wiring or the second wiring,in the erase operation, an erase voltage in a second polarity is supplied between the third wiring and at least one of the first wiring or the second wiring, the second polarity being different from ...

MEMORY DEVICE AND ASYNCHRONOUS MULTI-PLANE INDEPENDENT READ OPERATION THEREOF

In certain aspects, a method for operating a memory device is disclosed. The memory device includes memory planes and multiplexers (MUXs). Each MUX includes an output coupled to a respective one of the memory planes, a first input receiving a non-asynchronous multi-plane independent (AMPI) read control signal, and a second input receiving an AMPI read control signal. Whether an instruction is an AMPI read instruction or a non-AMPI read instruction is determined. In response to the instruction being an AMPI read instruction, an AMPI read control signal is generated based on the AMPI read instruction, and a corresponding MUX is controlled to enable outputting the AMPI read control signal from the second input to the corresponding memory plane. In response to the instruction being a non-AMPI read instruction, a non-AMPI read control signal is generated based on the non-AMPI read instruction, and each MUX is controlled to enable outputting the non-AMPI read control signal from the respective first input to the respective memory plane. 1. A memory device , comprising:N memory planes, where N is an integer greater than 1;N asynchronous multi-plane independent (AMPI) read units each configured to provide an AMPI read control signal for a respective memory plane of the N memory planes to control an AMPI read operation on the respective memory plane;a first microcontroller unit (MCU) configured to provide a non-AMPI read control signal for each memory plane of the N memory planes to control a non-AMPI read operation on each memory plane; anda multiplexing circuit coupled to the N memory planes, the first MCU, and the N AMPI read units and configured to, in a non-AMPI read operation, direct a non-AMPI read control signal to each memory plane from the first MCU, and in an AMPI read operation, direct each AMPI read control signal of N AMPI read control signals to the respective memory plane from the corresponding AMPI read unit of the N AMPI read units.2. The memory device of ...

CACHE PROCESSES WITH ADAPTIVE DYNAMIC START VOLTAGE CALCULATION FOR MEMORY DEVICES

A method, a memory chip controller of a flash memory device, and a flash memory device. The memory chip controller includes processing circuitry to receive data for a first page of N pages of data; and program cells of a memory location of the device to an nth threshold voltage level Ln, Ln corresponding to a program verify voltage level PVn, n being an integer from 0 to 2−1, and Ln being one of 2threshold voltage levels achievable using the N pages of data. Programming the cells includes: programming the cells based on the data for the first page while receiving data for subsequent pages of the N pages; and programming the cells based on the data for the subsequent pages, wherein programming the cells includes, for at least n=1, causing a respective dynamic start voltage (DSV) to be applied to the cells based on each respective page number p of the N pages for which data is received at the memory chip controller for the memory location to achieve PV 1. A memory chip controller of a flash memory device , the memory chip controller including processing circuitry to:receive data for a first page of N pages of data; and{'sup': N', 'N, 'claim-text': programming the cells based on the data for the first page while receiving data for subsequent pages of the N pages; and', {'b': '1', 'programming the cells based on the data for the subsequent pages, wherein programming the cells includes, for at least n=1, causing a respective dynamic start voltage (DSV) to be applied to the cells based on each respective page number p of the N pages for which data is received at the memory chip controller for the memory location to achieve PV.'}], 'program cells of a memory location of the device to an nth threshold voltage level Ln, Ln corresponding to a program verify voltage level PVn, n being an integer from 0 to 2−1, and Ln being one of 2threshold voltage levels achievable using the N pages of data, programming the cells including2. The memory chip controller of claim 1 , the ...

NEGATIVE GATE STRESS OPERATION IN MULTI-PASS PROGRAMMING AND MEMORY DEVICE THEREOF

A memory device is provided. The memory device includes an array of memory cells arranged, a plurality of word lines, and a peripheral circuit configured to perform multi-pass programming on a selected row of memory cells coupled to a selected word line. The multi-pass programming includes a plurality of programming passes. Each of the programming passes includes a programming operation and a verify operation. To perform the multi-pass programming, the peripheral circuit is configured to, in a non-last programming pass of memory cells, perform a negative gate stress (NGS) operation on a memory cell in the selected row of memory cells between the programming operation and the verify operation; and at a same time, perform a NGS operation on a memory cell in an unselected row of memory cells coupled to an unselected word line of the word lines. The unselected word line is adjacent to the selected word line. 1. A memory device , comprising:an array of memory cells arranged in a plurality of rows;a plurality of word lines respectively coupled to the plurality of rows of the memory cells; anda peripheral circuit coupled to the word lines and configured to perform multi-pass programming on a row of memory cells coupled to a word line of the plurality of word lines, the multi-pass programming comprising a plurality of programming passes, each of the programming passes comprising a programming operation and a verify operation, wherein, to perform the multi-pass programming, the peripheral circuit is configured to, in a non-last programming pass of memory cells,perform, during a first time period, a negative gate stress (NGS) operation on a memory cell in a first row of memory cells coupled to a first word line, between the programming operation and the verify operation, wherein the first word line is selected during the first time period; andduring the first time period, perform a NGS operation on a memory cell in a second row of memory cells coupled to a second word line of ...

TRIPLE MODULAR REDUNDANCY FOR FAULT-TOLERANT IN-MEMORY COMPUTING

Methods, systems, and devices related to 3D self-selecting-memory array of memory cells are described. The method relates to a solution for improving the fault-tolerant capability of memory devices, including: applying a triple-modular-redundancy calculation in a programming phase of the memory cells of a memory array, and adopting a sequence of two opposite dual polarity algorithms applied along a selected bit line and in parallel on the at least three selected word lines of the memory array. 1. A method for improving a fault-tolerant capability of memory devices , comprising:applying a triple-modular-redundancy calculation in a programming phase of the memory cells of a memory array; andadopting a sequence of two opposite dual polarity algorithms applied along a selected bit line and in parallel on at least three selected word lines of the memory array.2. The method of claim 1 , wherein a majority voting scheme is implemented by correcting wrong bits and rebuilding an integrity of copies of data used in the triple-modular-redundancy calculation during in-memory computing operations.3. The method of claim 1 , wherein the dual polarity algorithm comprises two pulses with respective polarities:a first pulse used for detecting a cell state; anda second pulse with a correct polarity for data programming.4. The method of claim 3 , wherein a snap detector circuit is activated during the first pulse of each dual polarity algorithm in the sequence to detect the cell state of the memory cell and in case skip the second pulse of the dual polarity algorithm.5. The method of claim 1 , wherein a current flowing through the selected bit line is checked by a current comparator circuit claim 1 , andif the current flowing through the selected bit line is less than a threshold reference current, then a second pulse of the dual polarity algorithm is applied;if the current flowing through the selected bit line is greater than or equal to the threshold reference current, then the ...

METHOD FOR RECOVERING EEPROM OF SLAVE DEVICE BY PLC COMMUNICATION MODULE

Disclosed is a method for automatically recovering data of an electronically erasable programmable read only memory (EEPROM) storing configuration information of a slave device by a programmable logic controller (PLC) communication module using an EtherCAT network when the data of the EEPROM is modified or incorrect. 1. A method for recovering data of an EEPROM storing configuration information of a slave device by a PLC communication module including the steps of:(A) analyzing original data of the EEPROM on a data section basis to compute a checksum of each data section, wherein the original data is stored in the PLC communication module;(B) analyzing EEPROM data read from the EEPROM on a data section basis to compute a checksum of each data section, wherein the EEPROM is attached to a an EtherCAT slave controller (ESC) of the slave device;(C) comparing each section-based checksum of the original data with each section-based checksum of the EEPROM data;(D) when at least one of section-based checksums mismatches between the original data and the EEPROM data, detecting at least one section having the at least one checksum having the mismatching, and indicating a flag value corresponding to the mismatching into the at least one section of the EEPROM data; and(E) informing a user of the at least one section of the EEPROM data having the flag value corresponding to the mismatching.2. The method of claim 1 , wherein the data sections of the EEPROM data include a critical information section claim 1 , a connection information section claim 1 , and a communication information section.3. The method of claim 1 , wherein the (D) includes:when all of section-based checksums mismatch between the original data and the EEPROM data, requesting reading-out of the configuration information from the EEPROM;when the reading-out is successful, checking whether the read-out configuration information is valid; andwhen the reading-out fails or when the read-out configuration information ...

PARTIALLY WRITTEN SUPERBLOCK TREATMENT

The present disclosure relates to partially written superblock treatment. An example apparatus includes a memory device operable as a multiplane memory resource including blocks organized as superblocks. The memory device is configured to maintain, internal to the memory device, included in a status of an open superblock, a page indicator corresponding to a last written page of the open superblock. The memory device is further configured, responsive to receipt, from a controller, of a read request to a page of the open superblock, determine from page map information maintained internal to the memory device and from the indicator of the last written page, which of a number of different read trim sets to use to read the page of the open superblock corresponding to the read request. 120-. (canceled)21. An apparatus , comprising:a memory device operable as a multiplane memory resource comprising blocks organized as superblocks; maintain, internal to the memory device, a status of a number of open superblocks in the memory device, the status comprising an indicator of a write operation initiated in the number of the open superblocks; and', 'responsive to receipt, by the controller, of a read request to a page of an open superblock, determine from page map information maintained internal to the memory device and from an indicator of a last written page of the open superblock, which of a number of different read trim sets to use to read the page of the open superblock corresponding to the read request., 'wherein the memory device includes instructions stored thereon that when executed by a controller, internal to the memory device, cause the controller to direct the memory device to22. The apparatus of claim 21 , wherein the controller further directs the memory device to maintain claim 21 , included in the status of the open superblock claim 21 , the indicator corresponding to the last written page of the open superblock.23. The apparatus of claim 21 , wherein:the read ...

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME

Provided herein may be a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a plurality of pages each including a plurality of memory cells, peripheral circuits configured to perform a program operation of a selected page among the plurality of pages and a control logic configured to control the peripheral circuits such that a main program operation is performed on the selected page and, when the main program operation is completed, a compensation program operation is performed on memory cells having lower threshold voltage retention characteristics compared to remaining memory cells, among the memory cells included in the selected page. 1. A semiconductor memory device comprising:a plurality of pages each comprising a plurality of memory cells;peripheral circuits configured to perform a program operation on a selected page among the plurality of pages; anda control logic configured to control the peripheral circuits such that a main program operation is performed on the selected page and, when the main program operation is completed, a compensation program operation is performed on memory cells having lower threshold voltage retention characteristics compared to remaining memory cells, among the memory cells included in the selected page.2. The semiconductor memory device according to claim 1 , wherein the peripheral circuits comprises:page buffers each including a plurality of latches configured to temporarily store data during the main program operation and the compensation program operation, under control of the control logic; anda voltage generation circuit configured to generate program voltages increasing in steps during the main program operation and a compensation program voltage during the compensation program operation, under the control of the control logic.3. The semiconductor memory device according to claim 2 , wherein the page buffers comprise:first latches configured to store data inputted ...

WRITING A NONVOLATILE MEMORY TO PROGRAMMED LEVELS

In some examples, a fluid dispensing device component includes an input to receive a control signal from the fluid dispensing system, the control signal for activating fluidic actuators during a fluidic operation mode. The fluid dispensing device component further includes a nonvolatile memory, and a controller to, during a memory write mode, write a first portion of the nonvolatile memory to a first programmed level responsive to application of a first programming voltage and activation of the control signal, and write a second portion of the nonvolatile memory to a second programmed level responsive to application of a second programming voltage different from the first programming voltage and activation of the control signal. 1. A fluid dispensing device component comprising:an input to receive a control signal from the fluid dispensing system, the control signal for activating fluidic actuators during a fluidic operation mode;a nonvolatile memory; and write a first portion of the nonvolatile memory to a first programmed level responsive to application of a first programming voltage and activation of the control signal, and', 'write a second portion of the nonvolatile memory to a second programmed level responsive to application of a second programming voltage different from the first programming voltage and activation of the control signal., 'a controller to, during a memory write mode2. The fluid dispensing device component of claim 1 , wherein the controller is to claim 1 , during the memory write mode claim 1 , write at least one further portion of the nonvolatile memory to at least one corresponding further programmed level responsive to application of a further programming voltage and activation of the control signal claim 1 , the at least one further programmed level being different from the first and second programmed levels claim 1 , and the at least one further programming voltage being different from the first and second programming voltages.3. The ...

RECOVERY FOR NON-VOLATILE MEMORY AFTER POWER LOSS

Non-volatile memory array can be recovered after a power loss. In one example, pages of a memory array are scanned to find a first free page after the power loss. The first free page is marked as available, and the page marked as available is written to with the next write cycle 1scanning pages of a memory array to find a first available page for writing by making a determination whether a header on a page contains a commit marker;based on a determination that the header on a page contains a commit marker, scanning a subsequent page; and. A method, comprising: Non-volatile memory devices provide a benefit of storing data without requiring any power to safely maintain the stored data. However, reading the stored data and initially writing the data does require power. In many non-volatile memory types, data is typically safe during read operations regardless of a power failure. However, if the power is interrupted or fails during a write process, not only does the writing stop, but some cells may have unstable values written to them. It may then become difficult, after power is restored, to determine where the writing should begin again.Moreover, checking the values already stored in memory may not reliably indicate where the writing should begin again. In flash memory, for example, the value in a memory cell is stored by setting a charge. The voltage on the charge element is compared to a threshold to determine whether the stored value is a zero or a one. If the stored value is near the threshold because the power went out before the intended charge was set, then it might read zero at some times and one at other times. Similarly, in a phase change memory cell the value is stored, by setting the resistance of a phase change material. The resistance is compared to a threshold and if the resistance is near the threshold, then the cell might read zero at some times and one at other times. Such unstable or inconsistent memory values can occur in any type of non-volatile ...

PROGRAMMABLE INTEGRATED CIRCUIT (IC) CONTAINING AN INTEGRATED OPTICAL TRANSDUCER FOR PROGRAMMING THE IC, AND A RELATED IC PROGRAMMING SYSTEM AND METHOD

A programmable integrated circuit (IC) comprising a single body of semiconductor is disclosed. The IC comprises at least one optical transducer as an integral part of the programmable integrated circuit on the same body of semiconductor, the optical transducer being operable to receive an optical input indicative of programming instructions and at least one storage element communicatively coupled to the optical transducer and being operable to store thereon the programming instructions or an adaptation thereof. The programming instructions received via the optical input are configured to direct the operation of the IC. 2. The IC as claimed in claim 1 , wherein the storage element in an integral part of the same body of semiconductor as the IC.3. The IC as claimed in claim 1 , wherein the storage element is external to the IC but connected thereto by a communication link or bus.4. The IC as claimed in claim 1 , wherein the optical transducer is an optical detector or photodetector.5. The IC as claimed in claim 4 , wherein the optical transducer additionally serves as an on-die light emitter.6. The IC as claimed in claim 5 , wherein the optical transducer provides bi-directional communication capabilities.7. The IC as claimed in claim 1 , wherein the body of semiconductor is predominantly silicon.8. The IC as claimed in claim 7 , wherein the body of semiconductor is crystalline silicon.9. The IC as claimed in claim 7 , which employs a CMOS claim 7 , BiCMOS claim 7 , or SOI process.10. The IC as claimed in claim 1 , wherein the optical transducer and associated electrical circuitry are operable to extract electrical power from at least a portion of the optical input claim 1 , thereby to power the electrical circuitry to support a programming event.11. The IC as claimed in claim 10 , wherein the electrical circuity includes an energy harvesting component operable to harvest energy from optical input claim 10 , rendering it unnecessary to supply the IC with additional ...

PROGRAMMABLE INPUT/OUTPUT CIRCUIT

A programmable input/output (I/O) circuit includes an output buffer coupled between an output signal and an I/O pad and an input comparator coupled between an input signal and the I/O pad. The input comparator includes a first input coupled to the I/O pad. A multiplexor receives a select signal for selecting a first reference voltage from the plurality of reference voltages at a first time and for dynamically selecting a second reference voltage from the plurality of reference voltages at a second time. 120-. (canceled)21. A programmable input/output (I/O) circuit comprising:an output buffer coupled between an output signal and an I/O pad;an input comparator coupled between an input signal and the I/O pad, the input comparator comprising a first input coupled to the I/O pad;a multiplexor coupled between a second input of the input comparator and a plurality of reference voltages, wherein the multiplexor receives a select signal for selecting a first reference voltage from the plurality of reference voltages at a first time and for dynamically selecting a second reference voltage from the plurality of reference voltages at a second time.22. The programmable I/O circuit of claim 21 , wherein the signal for dynamically selecting a second reference voltage from the plurality of reference voltages is provided without interrupting operation of circuits coupled to the programmable I/O circuit.23. The programmable I/O circuit of claim 21 , wherein the output buffer is a single input digital buffer coupled to an adjustable reference voltage.24. The programmable I/O circuit of claim 21 , wherein the input comparator is an operational amplifier in an open loop configuration.25. The programmable I/O circuit of claim 21 , wherein the plurality of reference voltages are provided from circuits disposed on the same silicon substrate as the programmable I/O circuit.26. The programmable I/O circuit of claim 21 , wherein at least one of the plurality of reference voltages are provided ...

SEMICONDUCTOR DEVICE AND ITS POWER SUPPLY CONTROL METHOD

The semiconductor device includes a semiconductor chip including a first nonvolatile memory including a first memory block and a second memory block, CPU controlling the first nonvolatile memory, a first switch electrically connected to the first memory block and controlling the supply of the first power supply voltage to the first memory block, a second switch electrically connected to the second memory block and controlling the supply of the first power supply voltage to the second memory block, and a second nonvolatile memory electrically connected to each of the first switch and the second switch and storing flag information for controlling the first switch and the second switch, wherein the control of each of the first switch and the second switch is performed based on flag information indicating whether program data executed by CPU is written in the first memory block and the second memory block. 1. A semiconductor device comprising:a semiconductor chip including;a first nonvolatile memory having a first memory block and a second memory block;CPU controlling the first nonvolatile memory;a first switch electrically connected to the first memory block and controlling the supply of a first power supply voltage to the first memory block;a second switch electrically connected to the second memory block and controlling the supply of the first power supply voltage to the second memory block; anda second nonvolatile memory electrically connected to each of the first switch and the second switch, and storing flag information for controlling the first switch and the second switch,wherein a control of each of the first switch and the second switch is performed based on the flag information indicating whether program data to be executed by CPU is written in the first memory block and the second memory block.2. The semiconductor device according to claim 1 ,wherein when the program data is written in the first memory block and the second memory block is blank, the first ...

Method and apparatus for performing data storage management to enhance data reliability with aid of repeated write command detection

A method and apparatus for performing data storage management to enhance data reliability are provided. The method includes: receiving a write command from a host system, wherein the write command indicates that writing a set of data into a non-volatile (NV) memory is required; determining whether a repeated writing condition is satisfied, wherein the repeated writing condition includes the write command being a repeated write command of a previous write command and corresponding to a same address and a same length as that of the previous write command; and in response to the repeated writing condition being satisfied, storing the set of data into at least one of a first type of blocks within the NV memory, for performing data storage enhancement processing, wherein bit count per memory cell of the first type of blocks is less than bit count per memory cell of a second type of blocks.

Memory system and method of controlling nonvolatile memory

According to one embodiment, a memory system includes a plurality of nonvolatile memory chips and a controller configured to control the nonvolatile memory chips through a channel. The controller detects a program command sequence and sets a second chip enable signal corresponding to a second nonvolatile memory chip of the nonvolatile memory chips to the enable state during a period of at least data input cycle in the detected program command sequence. The controller transmits, when it is indicated that a ready/busy signal input to the controller while the second chip enable signal is in the enable state, a command sequence to the second nonvolatile memory chip.

Method and Apparatus for Controlling a Non-Volatile Digital Information Memory

Embodiments are related to controlling a non-volatile digital information memory, such as a flash memory, by means of a memory controller. More specifically, embodiments are related to a method of controlling the information memory, a computer program being configured to perform the method, a memory controller for performing the method, and/or a memory system comprising such a memory controller. 1. A method of controlling a first information memory , the method comprising: perform an updating process where first assignment data being stored in the first information memory and representing an assignment between the logical memory addresses being addressable by a host through the memory controller circuit and physical memory addresses of the first information memory is updated such that the assignment represented by the first assignment data coincides with an assignment between the logical memory addresses and physical addresses of the first information memory that is currently actually used by the memory controller circuit for addressing the first information memory, and which is at least partly stored in a second information memory as respective second assignment data;', 'perform an examination process in which a determination is made, as to whether a pre-defined criterion is met that characterizes a potential loss of the second assignment data with regard to its occurrence and/or the degree of deviation of the assignment represented by the second assignment data from the assignment represented by the first assignment data; and', 'wherein the updating process is started upon determining that the criterion is met., 'using a memory controller circuit to2. The method of claim 1 , wherein the first information memory is a non-volatile memory (NVM) claim 1 , and wherein the second information memory is a volatile memory (VM).3. The method of claim 2 , wherein the examination process includes at least one process selected from a group consisting of: determining whether ...

STORAGE DEVICE AND OPERATING METHOD THEREOF

A memory device includes memory blocks, a read count storage, a cell counter, and a read reclaim processor. The read count storage stores read count information including read counts of the memory blocks. When a read count of a target block among the memory blocks exceeds at least one threshold count, the cell counter performs a read operation on at least one page among pages included in the target block by using a first read voltage, and calculates a first memory cell count as a number of memory cells read as first memory cells among memory cells included in the at least one page, based on a current sensed from the at least one page in the read operation. The read reclaim processor provides a memory controller with a status code based on the first memory cell count and a number of correctable error bits. 1. A memory device comprising:a plurality of memory blocks;a read count storage configured to store read count information including read counts of the plurality of memory blocks;a cell counter configured to, when a read count of a target block among the plurality of memory blocks exceeds at least one threshold count, perform a read operation on at least one page among a plurality of pages included in the target block by using a first read voltage, and calculate a first memory cell count as a number of memory cells read as first memory cells among memory cells included in the at least one page, based on a current sensed from the at least one page in the read operation; anda read reclaim processor configured to provide a memory controller with a status code representing a priority order of a read reclaim operation on the target block, based on the first memory cell count and a number of correctable error bits.2. The memory device of claim 1 , wherein the target block is a memory block on which a read operation is performed according to a read command received from the memory controller among the plurality of memory blocks.3. The memory device of claim 2 , wherein ...

Method and apparatus for configuring write performance for electrically writable memory devices

Methods and systems are provided that may include a nonvolatile memory to store information, where the nonvolatile memory is associated with a configuration register to indicate a write speed setting for at least one write operation to the nonvolatile memory. A circuit may supply current to achieve an indicated write speed setting for the at least one write operation to the nonvolatile memory.

APPARATUSES AND METHODS OF OPERATING FOR MEMORY ENDURANCE

Methods of operating an apparatus such as a computing system and/or memory device for memory endurance are provided. One example method can include receiving m digits of data having a first quantity of digits represented by a first data state that is more detrimental to memory cell wear than a second data state. The m digits of data are encoded into n digits of data having a second quantity of digits represented by the first data state. The value n is greater than the value m. The second quantity is less than or equal to the first quantity. The n digits of data are stored in an apparatus having memory cells. 120.-. (canceled)21. A method , comprising:encoding a quantity of data into a greater quantity of data,wherein the greater quantity of data includes a same number or fewer bits of a first data value than are included in the quantity of data, and wherein bits of the first data value are associated with more memory wear than bits of a second data value.22. The method of claim 21 , wherein the greater quantity of data includes fewer bits of a first data value than are included in the quantity of data claim 21 , and wherein bits of the first data value are associated with more memory wear than bits of a second data value.23. The method of claim 21 , wherein bits of the first data value are represented by storage in a memory cell of a greater amount of charge than an amount of charge that represents the second data value.24. The method of claim 21 , wherein the greater quantity of data includes at most a same number of bits of a first data value than are included in the quantity of data claim 21 , and wherein bits of the first data value are associated with more memory wear than bits of a second data value.25. The method of claim 21 , wherein the greater quantity of data includes more bits of a first data value than are included in the quantity of data claim 21 , and wherein bits of the first data value wear a memory cell less than bits of a second data value.26. A ...