УСТРОЙСТВО ПОЛУПРОВОДНИКОВОЙ ПАМЯТИ

... 1. Устройство полупроводниковой памяти, содержащее: ! матрицу памяти, к которой осуществляют доступ последовательно, начиная с верхнего адреса, и которая содержит перезаписываемую область, используемую для хранения перезаписываемых данных, и область, запрещенную для записи, которую используют для хранения данных только для чтения и которая следует за перезаписываемой областью, ! блок приема запроса на доступ, который принимает запросы на доступ для осуществления доступа к требуемому адресу в упомянутой матрице памяти, ! блок установки флага, который устанавливает флаг в положение ВКЛЮЧЕНО, когда был осуществлен доступ к области, запрещенной для записи, и ! контроллер памяти, который управляет доступом к упомянутой матрице памяти и не записывает данные в упомянутый требуемый адрес, если упомянутый требуемый адрес содержится в упомянутой перезаписываемой области, и упомянутый флаг установлен в положение ВКЛЮЧЕНО. ! 2. Устройство полупроводниковой памяти по п.1, в котором упомянутый контроллер ...

GEFILTERTES, SERIELLES EREIGNISGESTEUERTES BEFEHLSTOR FÜR "FLASH" SPEICHER

Halbleiterbauelement mit nichtflüchtigem Speicher

INTEGRIERTE SCHALTUNG MIT EINEM ALS NICHTFLUECHTIGER SCHREIB-LESE-SPEICHER AUSGESTALTETEN ANWENDUNGSSPEICHER

System und Verfahren zur Handhabung einer Unterbrechung der Versorgungsspannung in einem nichtflüchtigen Speicher

SCHREIBSCHUTZ DURCH VERWENDUNG EINES ZWEISIGNAL-STLEMENT MIT PARAMETERÄNDERUNGSFÄHIGKEIT, CHIPAUSWAHL UND WÄHLBARES SCHREIBEN IN NICHTFLÜCHTIGEM SPEICHER

A method and apparatus for hardware block locking in a nonvolatile memory

STORAGE OF DATA IN STORE

A method and apparatus for securing data contents of a non-volatile memory device

Semiconductor device and semiconductor device control method

Semiconductor device and semiconductor device control method

A portable data storage device.

A portable data storage device (10)includes a universal serial bus (usb)coupling device (1)and an interface device (2)is coupled to the usb coupling device (1). The portable data storage device (10)also includes a memory control device (3)and a non volatile solid-state memory device (4). The memory control device (3)is coupled betweem the interface device (2)and the memory device (4)to control the flow of data from the memory device (4)to the usb coupling device (1) ...

A portable data storage device

CONTROL UNIT

PROCEDURE AND ARRANGEMENT FOR THE ACCESS CONTROL ON EEPROMS AS WELL AS AN APPROPRIATE COMPUTER PROGRAMME PRODUCT AND AN APPROPRIATE COMPUTER-READABLE STORAGE MEDIUM

WRITING PROTECTION BY USE OF TWO-SIGNAL EXPENSIVE MINUTES FOR AN INTEGRATED CIRCUIT ELEMENT WITH ABILITY OF CHANGE OF PARAMETER, CHIP SELECTION AND SELECTABLE LETTER IN NON VOLATILE MEMORY

SWITCHING CONFIGURATION WITH NICHTFLUCHTIGEM MEMORY MODULE AND PROCEDURE FOR REGISTERING LIGHT ATTACKS AT THE NICHTFLUCHTIGEN MEMORY MODULE

DISK UNIT

PROTECTION CIRCUIT FOR PROGRAMMABLE LOGIC ARRAY.

FILTERED, SERIAL EVENT-CONTROLLED COMMAND GATE FOR '' FLASH '' MEMORY

Top/bottom symmetrical protection scheme for flash

PROM ERASE DETECTOR

MOBILE COMMUNICATION DEVICE HAVING INTEGRATED EMBEDDED FLASH AND SRAM MEMORY

The flash and SRAM memory (112, 113) are embedded within an application specific integrated circuit (ASIC) to provide improved access times and also reduce over all power consumption of a mobile telephone employing the ASIC. The flash memory system (112) includes a flash memory array (130) configured to provide a set of individual flash macros and a flash memory controller (132) for accessing the flash macros. The flash memory controller includes a read while writing unit (144, 146) for writing to one of the flash macros while simultaneously reading from another of the flash macros. The flash memory controller also includes programmable wait state registers (138) and a password register (140) providing a separate password for different portions of the flash memory array. A memory swap unit (149) is provided for swapping high and low memory subsequent to completion of operations performed by the boot loader. Method and apparatus implementations are disclosed.

SEMICONDUCTOR MEMORY CARD AND DATA READING APPARATUS

A semiconductor memory card comprising a control IC (302), a flash memory (303), and a ROM (304). The ROM (304) holds information such as a medium ID (341) unique to the semiconductor memory card. The flash memory (303) includes an authentication memory (332) and a non-authentication memory (331). The authentication memory (332) can be accessed only by external devices which have been affirmatively authenticated. The non-authentication memory 331 can be accessed by external devices whether the external devices have been affirmatively authenticated or not. The control IC (302) includes control units (325) and (326), an authentication unit (321) and the like. The control units (325) and (326) control accesses to the authentication memory (332) and the non-authentication memory (331), respectively. The authentication unit (321) executes a mutual authentication with an external device.

PUF VALUE GENERATION USING AN ANTI-FUSE MEMORY ARRAY

A method and system are used to generate random values for Physical Unclonable Function (PUF) for use in cryptographic applications. A PUF value generation apparatus comprises two dielectric breakdown based anti-fuses and at least one current limiting circuit connected between anti-fuses and power rails. Two anti-fuses are connected in parallel for value generation in programming by applying high voltage to both anti-fuses at the same time. Time for dielectric breakdown under high voltage stress is of random nature and therefore unique for each anti-fuse cell. Therefore the random time to breakdown causes one cell to break before another, causing high breakdown current through the broken cell. Once high breakdown current through one broken or programmed cell is established, a voltage drop across a current limiting circuit leads to decreased voltage across both cells, thereby slowing the time dependent breakdown process in the second cell and preventing it from breakage under programming ...

PROGRAMMABLE ACCESS PROTECTION IN A FLASH MEMORY DEVICE

A memory device (100) comprises a memory array (102) having corresponding first access control bits (202, 204) to control access thereto. A second set of access control bits (104) is provided to control write access to the first access control bits. The memory array is divided into memory blocks, each block having a corresponding access control bit. At least one such block (BLK0) is further subdivided into pages, each page having a corresponding control bit.

PORTABLE INFORMATION STORAGE DEVICE FOR STORING AND PROCESSING INFORMATION.

PROCEDURE FOR STORING DATA IN AN ELECTRICALLY ERASABLE MEMORY AND ELECTRICAL OF ERASABLE MEMORY FOR THE EXECUTION OF THE PROCEDURE.

Nonvolatile semiconductor memory device and its secret protection method

非易失半导体存储装置

... 本发明提供一种半导体存储装置，存储单元阵列具有第1、第2存储区域。上述第1存储区域具有由地址信号选择的多个存储元件，上述第2存储区域具有由控制信号选择的多个存储元件。控制电路具有第1熔丝元件。上述控制电路在上述第1熔丝元件被切断时，禁止对于上述第2存储区域的写入和擦除的至少其中之一。 ...

CIRCUIT INTEGRE DU TYPE CIRCUIT LOGIQUE COMPORTANT UNE MEMOIRE NON VOLATILE PROGRAMMABLE ELECTRIQUEMENT

LA PRESENTE INVENTION CONCERNE UN CIRCUIT INTEGRE DU TYPE CIRCUIT LOGIQUE COMPORTANT UNE MEMOIRE NON VOLATILE PROGRAMMABLE ELECTRIQUEMENT CONSTITUEE D'UNE MATRICE DE CELLULES-MEMOIRE DU TYPE A TRANSISTOR A GRILLE FLOTTANTE 1, DE CIRCUITS D'ECRITURE ET DE LECTURE R, 11, 12, 13, L ET DE MOYENS 6, 7, 8 GERANT L'INTERCONNEXION DE CES CIRCUITS AVEC LA MEMOIRE, LE CIRCUIT INTEGRE RECEVANT UNE TENSION D'ALIMENTATION GENERALE VCC, UNE TENSION DE PROGRAMMATION VPP ET UN SIGNAL-HORLOGE EXTERIEUR DIVISE D EN DEUX SIGNAUX-HORLOGE COMPLEMENTAIRES, LESDITS SIGNAUX-HORLOGE CLK1, CLK2 AGISSANT ENTRE AUTRES SUR LE FONCTIONNEMENT DES CIRCUITS D'ECRITURE. IL COMPORTE DE PLUS UN CIRCUIT P DE DETECTION DE PRESENCE DES SIGNAUX-HORLOGE INTERNES ENVOYANT UN SIGNAL INTERDISANT L'ECRITURE DANS LA MEMOIRE LORSQU'IL DETECTE L'ABSENCE D'UN DES SIGNAUX-HORLOGE INTERNES. APPLICATION NOTAMMENT AUX CARTES A MEMOIRE.

LOCKING DEVICE HAS NEVER A PROGRAMMABLE CELL HAVING A FLOATING GATE.

DISPOSITIF DE TEST D'UN CARACTERE TEMOIN INSCRIT DANS UNE MEMOIRE

Le dispositif comprend, une mémoire effaçable, un caractère témoin inscrit dans la mémoire, des circuits de commande de la mémoire autorisant la lecture du caractère témoin et interdisant l'écriture d'informations dans la zone de la mémoire qui lui est réservé, un comparateur pour vérifier la conformité du caractère témoin. La non-conformité du caractère témoin signifie que la mémoire a été exposée à des rayonnements ou à des perturbations électriques. Application: dispositifs d'enregistrement portables, système de traitement de l'information.

MEMORY INTEGRATED CIRCUIT HAVING A TAMPER-EVIDENT DEVICE

INTEGRATED CIRCUIT HAVING a DATA MEMORY PROTEGEE AGAINST OBLITERATION UV

L'invention concerne un procédé pour protéger contre un effacement global de données un circuit intégré (IC1) comprenant une mémoire de données programmable électriquement (MEM1) et une unité de contrôle (CTU) pour exécuter des commandes de lecture ou d'écriture de la mémoire. Le procédé comprend les étapes consistant à prévoir dans le circuit intégré des cellules mémoire témoin programmables électriquement (TZ), à la mise en service du circuit intégré, enregistrer dans les cellules mémoire témoin des bits de valeur déterminée formant une combinaison de bits autorisée et, pendant le fonctionnement du circuit intégré suivant sa mise en service, lire et évaluer les cellules mémoire témoin et bloquer le circuit intégré si les cellules mémoire témoin contiennent une combinaison de bits interdite différente de la combinaison autorisée.

INTEGRATED CIRCUIT OF THE LOGICAL CIRCUIT TYPE COMPRISING A PROGRAMMABLE NONVOLATILE MEMORY ELECTRICALLY

Integrated circuit one time programming memory having series placed transistor/polycrystalline silicon programming resistor forming memory element with programming resistor not destroyed during programming.

L'invention concerne une cellule mémoire à programmation unique comportant un transistor de programmation (MN) en série avec une résistance de programmation (Rp) en silicium polycristallin constituant l'élément de mémorisation, la programmation étant non destructrice de la résistance en silicium polycristallin.

MEMORY HAVING A CIRCUIT FOR DETECTING A GLITCH ON A LINE MEMORY

L'invention concerne une mémoire (MEM1) comprenant un circuit de commande (CCT, HC), un plan (MA1) de cellules mémoire (MC), chaque cellule mémoire étant couplée à une ligne de bits (BLn) et à au moins une ligne de mémoire (WLm), et un circuit de détection d'impulsion transitoire (DC) couplé à au moins une ligne de mémoire et configuré pour recevoir un signal de commande d'opération (OP) envoyé par le circuit de commande, le signal de commande d'opération indiquant si une opération est activée ou désactivée pour la ligne de mémoire, et pour fournir un signal de détection d'impulsion transitoire (DET, GLT) lorsqu'un signal sur la ligne de mémoire passe à une première valeur logique lorsque le signal d'opération est désactivé.

CELL MEMORY HAS NONDESTROYING SINGLE PROGRAMMING

L'invention concerne une cellule mémoire à programmation unique et son procédé de programmation, comportant un transistor de programmation (MN) en série avec une résistance de programmation (Rp) en silicium polycristallin constituant l'élément de mémorisation, la programmation étant non destructrice de la résistance en silicium polycristallin.

Method and device for secured writing of data in rewritable memory, for use in microelectronics and chip cards

On définit une mémoire comprenant un fichier cyclique possédant m enregistrements organisés en boucle, avec m entier allant de 1 à n+1, les enregistrements 1 à n étant accessibles tandis que l'enregistrement n+1, l'indicateur d'intégrité et le rang de chaque enregistrement étant cachés à l'utilisateur. On recherche l'enregistrement m = n+1, et on vérifie l'état de son indicateur d'intégrité. En cas d'indicateur d'intégrité mauvais, on écrit la donnée à inscrire dans l'enregistrement m = n+1, et en cas de succès, on incrémente d'une unité l'enregistrement m = n+1+1 = 1 qui devient caché, laissant accessibles les enregistrements 2 à n+1 tandis qu'en cas d'échec, on n'apporte aucune modification à l'enregistrement m = n+1 qui reste caché, les autres enregistrements 1 à n restant accessibles à l'utilisateur. En cas d'indicateur d'intégrité bon, on écrit la donnée à inscrire dans l'enregistrement m=n+1+1=1, et en cas de succès, on incrémente d'une unité le rang de l'enregistrement m = 1+1 = ...

Integrated circuit containing a protected memory and protected system using the aforementioned integrated circuit

Pour protéger efficacement en lecture des données mémorisées, le circuit intégré comporte une mémoire de type EEPROM et un verrou (L) protégeant une zone de la mémoire. La mémoire contient un mot de passe (PW) protégé en lecture et le circuit comporte des moyens pour libérer le verrou (L) si le circuit reçoit une commande d'écriture à l'adresse du mot de passe du même mot de passe (PW) encrypté. Application notamment aux systèmes et appareils électroniques à code confidentiel, tels que les auto-radios.

MEMORY CIRCUIT COMPRISING MEANS FOR DETECTING A FAULT INJECTION

L'invention concerne un circuit à mémoire (MEM1) comprenant un plan mémoire (MA) comportant des cellules mémoire (MC), et un décodeur d'adresse (RDEC) configuré pour appliquer au plan mémoire des signaux (V0-VI-1, Vsel) de sélection d'un groupe de cellules mémoire en fonction d'une adresse (AD1). Selon l'invention, le circuit à mémoire comprend des moyens (LCT) pour capturer des signaux (Vsel) de sélection de cellules mémoire apparaissant dans le plan mémoire, et des moyens (RCOD), pour reconstituer, à partir des signaux de sélection capturés, une adresse (AD2) d'un groupe de cellules mémoire sélectionné.

Dispositif de verrouillage à cellule à grille flottante jamais programmable.

On réalise des dispositifs de verrouillage en utilisant une cellule à grille flottante (1) rendue jamais programmable électriquement en mettant entre sa zone drain (3) et la masse et entre sa zone source (4) et la masse, un limiteur de tension (5 et 6). La cellule n'est plus jamais programmable par rayons ultra-violets à cause de l'interposition d'un pavé de métal (12) au-dessus de sa grille de commande 2. On réalise un limiteur de tension (5 et 6), en utilisant une diode Zener réalisée en joignant aux zones drain (3) et source (4) une zone de dopage opposé (7 et 8), placée à l'extérieur de la zone canal (9) et connectée à la masse.

DETECTION CIRCUIT Of WEAR

DETECTION CIRCUIT Of WEAR

DETECTION CIRCUIT Of WEAR

DETECTION CIRCUIT Of WEAR

DETECTION CIRCUIT Of WEAR

Semiconductor device with voltage generator

NON-VOLATILE SEMICONDUCTOR DEVICE HAVING LOCKABLE CELLS

PURPOSE: A semiconductor device is provided to easily remove lockable cells by electrically separating word lines in a memory cell array section and word lines in a lockable cell section. CONSTITUTION: A semiconductor device has a block structure in which control gates of lockable cell transistors(MLC1-MLC8) in a corresponding memory block are not directly connected to control gates of memory cell transistors(MC1-MC8) which are connected to word lines (WL1-WL8) in a page unit, respectively. The control gates of the lockable cell transistors(MLC1-MLC8) and the control gates of the memory cell transistors (MLC1-MLC8) are connected to external signals(S1-S8, LS1-LS8) via pass gates(13,14), respectively. In this memory block, in order to erase information in a selected lockable cell, a ground voltage(V) is applied to the control gate in a corresponding lockable cell transistor and an erase voltage(Vers) is applied to a bulk of the corresponding lockable cell transistor, while the control gates ...

NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME

MEMORY MODULE, OPRTATION METHOD OF MEMORY MODULE, MEMORY SYSTEM AND OPERATION METHOD OF MEMORY SYSTEM

NON-VOLATILE MEMORY SYSTEM AND METHOD OF PROGRAMMING THE SAME

WRITE PROTECTION METHOD OF SEQUENTIAL ACCESS SEMICONDUCTOR STORAGE DEVICE

In a semiconductor storage device (10), when the front address of a write inhibition area is exceeded, a passage flag is turned on. When the semiconductor storage device (10) receives a request of data write to a write restriction area (WRA), it is determined whether the passage flag has been turned on. If the passage flag has not been turned on, the data write to the write restriction area is executed. Otherwise, the data write to the write restriction area is not executed. © KIPO & WIPO 2008 ...

STORAGE DEVICE INCLUDING AN AUTHENTICATION DEVICE AND AN AUTHENTICATION DEVICE CONNECTION MEANS CAPABLE OF INCREASING SECURITY

PURPOSE: A storage device including an authentication device and an authentication device connection means are provided to prevent an illegal copy of contents stored in the storage device which an authentication function is not equipped. CONSTITUTION: A storage unit(306) stores authentication device identifying information. An interface unit(302) is connected to a host device(100) through a first interface. An authentication processing unit(304) receives an authentication request signal requesting authentication of a storage device connected to the host device through the interface unit from the host device and outputs an authentication response signal to the host device through the interface unit. The authentication response signal includes data about a performing result of an authentication process referring to the authentication device identifying information. COPYRIGHT KIPO 2013 [Reference numerals] (100) Host device; (110) Authentication device identifying module; (200) Storage unit ...

PORTABLE MEMORY DEVICE HAVING A CONTENTS PROTECTION FUNCTION CAPABLE OF PREVENTING ALTERNATION OF CONTENTS STORED IN A MEMORY, AND A MANUFACTURING METHOD THEREOF

PURPOSE: A portable memory device having a contents protection function and a manufacturing method thereof are provided to prevent altering contents stored in a memory and enable a user to store desired information to a portable storage device storing the contents by including a read-only memory area, a writable memory area, and a special memory area. CONSTITUTION: A read-only memory area(312) stores contents and permits only the read operation. A writable memory area(314) stores additional information related to the contents or the information to be stored by a user, and permits the read and write operations. A special memory area(316) stores the information needed for operating a portable memory device, and permits the read and/or write operations to an authorized program. A memory controller(320) controls the read/write operations for each memory area. The special memory area includes a program revocation list representing whether the program is a revoked program. The memory controller ...

Nonvolatile memory, memory system, computer system, and operating method of nonvolatile memory

CONTROLLED DATA ACCESS TO NON-VOLATILE MEMORY

A method of controlling data access to non-volatile memory is disclosed. The method includes storing a data file in a non-volatile memory. The non-volatile memory includes a memory array addressable by a plurality of address ranges one or more of which corresponding to a protected portion of the memory array and one or more of which corresponding to an unprotected portion of the memory array. The method also includes communicating to a host device an indication that a memory request with respect to the protected portion of the memory array is denied. The indication is communicated for instructing the host device to avoid a timeout.

MLC SELF-RAID FLASH DATA PROTECTION SCHEME

A two-dimensional self-RAID method of protecting page-based storage data in a MLC multiple-level-cell flash memory device. The protection scheme includes reserving one parity sector across each data page, reserving one parity page as the column parity, selecting a specific number of pages to form a parity group, writing into the parity page a group parity value for data stored in the pages of the parity group. The parity sector represents applying a RAID technique in a first dimension. The group parity represents applying a RAID technique in a second dimension. Data protection is achieved because a corrupted data sector can likely be recovered by the two dimensional RAID data.

ONE-TIME PROGRAMMABLE MEMORY CELL

The invention relates to a memory cell with a binary value consisting of two parallel branches. Each of said branches comprises: at least one polycrystalline silicon programming resistor (Rpl, Rp2), which is connected between a first supply terminal (1) and a point or terminal for the differential reading (4, 6) of the memory cell state; and at least one first switch (MNP1, MNP2) which, during programming, connects one of said read terminals to a second supply terminal (2).

CIRCUIT FOR FOCUSED ION BEAM (FIB) SENSOR

The circuit permits the capacitive control of the memory cell (delete, programme and read), using an additional capacitance (4), which isolates the antenna (3) from the control circuit (2) of the memory cell (1). If an attack occurs, the charge is collected in the antenna. The capacitance prevents the charge from being discharged in such a way that the generated voltage affects the memory cell, causing the charged condition of the latter to be modified and said modification is detected. The capacitance can be configured as any type of capacitor structure in the circuit and is produced by known methods.

NONVOLATILE MEMORY

A memory cell for storing 1-bit data is formed by using at least two memory elements in the OTP type nonvolatile memory using a memory element that have two states and can transit only in one direction. In the OTP type nonvolatile memory using a memory element that has two states of an H state (a first state) and an L ( a second state) state (hereinafter simply referred to as H and L) and can electrically transit only in one direction from L to H, a memory cell for storing 1-bit data is formed by using two or more memory elements.

SOLID-STATE MEMORY DEVICE

The invention relates to a solid-state memory device with a plurality of memory cells (3) arranged on a semiconductor substrate at crossing points of bit lines and word lines and controllable for programming with data contents using a word line control circuit (4) and a bit line control circuit (5). Enabling memory cells (12, 14) are arranged along an enabling bit line (9, 10, 13), can be controlled by a controllable enabling bit line control circuit (11) arranged to be separate and independent of the bit line control circuit (5) and are associated with the memory cells (3). Said enabling memory cells can be actuated by an enabling value to enable the memory cells (3) of a predetermined word line.

SYSTEMS AND METHODS INVOLVING HARDWARE-BASED RESET OF UNRESPONSIVE MEMORY DEVICES

Systems and methods of memory operation that provide a hardware-based reset of an unresponsive memory device are disclosed. In one embodiment, an exemplary system may comprise a semiconductor memory device having a memory array, a controller that may include a firmware component for controlling memory operations, and a reset circuit including power-up circuitry and timeout circuitry. The reset circuit may be configured to detect when the memory device is in a non-responsive state and reset the memory device without using any internal controller components potentially impacted/affected by the non-responsive state. 1. A memory device comprising:at least one memory array;input/output circuitry coupled to the at least one memory array and configured to read from and write to the at least one memory array;control circuitry coupled to the at least one memory array and the input/output circuitry and configured to control operation of the memory device, the control circuitry comprising an output providing a busy signal indicating that the memory device is busy; and a first time that a write protect signal is maintained active to perform the reset of an erase or program operation; or', 'a second time, determined for the memory device, that the busy signal is allowed to be active indicating a busy state before the memory device requires reset;, 'reset circuitry comprising timeout circuitry and logic, coupled to the control circuitry and configured to reset the memory device, wherein the reset circuitry is configured to generate a global reset signal in response to a determination that the timeout circuit has been activated for longer than a predetermined period, wherein the predetermined period is set as being greater than the longer ofwherein the timeout circuitry is configured to activate in response to the write protect signal and in response to the busy signal, the write protect signal configured to reset the erase or program operation of the memory device; andwherein the ...

Data storage device incorporating a two-dimensional code

A data storage device includes a data carrier having at least one planar surface. An array of detectable items is positioned on the planar surface and is detectable with a sensing device. The array is configured to represent a two-dimensional code that defines at least executable instructions and redundancy encoding to impart fault tolerant characteristics to the code. The executable instructions include image processing algorithms.

Semiconductor storage device, method for protecting predetermined memory element and portable electronic equipment

There is provided a semiconductor storage device and portable electronic equipment including a nonvolatile memory element that can easily be miniaturized. The semiconductor storage device includes a memory cell array 21 in which a plurality of memory elements 1 are arranged and a write state machine 32. The memory element 1 includes a gate electrode 104 formed on a semiconductor layer 102 via a gate insulator 103, a channel region arranged below the gate electrode 104, diffusion regions 107a, 107b that are located on both sides of the channel region and have a conductive type opposite to that of the channel region and memory function bodies 109 that are located on both sides of the gate electrode 104 and have a function to retain electric charge. The write state machine 32 can selectively prevent program and erase of data in the memory elements within a predetermined range.

Nonvolatile memory device including write protected region

The present invention relates to a nonvolatile memory device including a write protected region, comprising a program command processor, a write protected region setting unit and a write controller. The program command processor outputs a program command signal by decoding an external signal. The write protected region setting unit stores a region address corresponding to an inputted address when the program command signal is activated, and outputs a write protect signal when the program command signal is inactivated. The write controller controls a cell corresponding to the region address not to perform a write mode when the write protect signal is activated.

Memory card with erasure blocks and circuitry for selectively protecting the blocks from memory operations

A memory card includes a plurality of memories, each having an array that includes a first block and a second block. Control circuitry is coupled to the array for controlling memory operations of the array. A block write protect circuit is provided for storing block lock data to selectively lock control circuitry from accessing the array for the memory operations. The block write protect circuit locks the control circuit from accessing (1) the first block when the block write protect circuit stores a first datum of the data and (2) the second block when the block write protect circuit stores a second datum of the data. A control input is coupled to the block write protect circuit for applying a control signal to enable the block write protect circuit to lock the control circuitry in accordance with the data. The memory card further includes a register circuit coupled to the control input of each of the plurality of memories for storing a control datum to generate the control signal. When ...

Semiconductor memory device

An electrically erasable-programmable read-only memory device has memory cells formed on a semiconductive substrate. Each memory cell has source and drain layers, and a floating gate electrode and a control gate electrode insulatively provided above the substrate. First and second well regions having a polarity opposite to that of the substrate are formed therein so that each well region contains one or a plurality of memory cells therein. When information stored in the memory cell or memory cells in the first well region is to be rewritten with new information in a partial data rewrite mode, a potential of the first well region is independently controlled so as to inhibit reading and writing of information in the memory cells in the first well region. A potential of the second well region is separately controlled so as to allow writing of the new information in the memory cells in the second well region. The new information is written in the memory cell or memory cells in the second well ...

Protection after brown out in a synchronous memory

A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device can detect a brown-out of a supply voltage. The memory device comprises a voltage detection circuit to monitor a supply voltage and provide a signal if the supply voltage drops below a predetermined value. A latch is coupled to the voltage detection circuit and can be programmed to indicate if the supply voltage dropped below the predetermined value. An external controller can read a status of the latch. The memory, therefore, can provide an indication to an external controller that a reset, or initialization, operation is needed.

Tamper response system for integrated circuits

A tamper response system to protect intellectual property is provided. In one embodiment, the tamper response system includes at least one sensor adapted to sense tamper activity and a tamper circuit. The tamper circuit is coupled to receive tamper signals from the at least one sensor. Moreover, the tamper circuit is adapted to clear at least one field programmable gate array (FPGA) upon receipt of a tamper signal.

Nonvolatile semiconductor memory device having protection function for each memory block

A nonvolatile semiconductor memory device includes a memory cell array constituted by a plurality of memory blocks, an interface, a write circuit, and a read circuit. A protect flag is written in the memory block. The readout protect flag can be output to an external device through the interface. When a write command is input from the interface, the write circuit executes the write command when the protect flag in the selected memory block has a first value and does not execute the write command when the protect flag has a second value.

Write protection security for memory device

An erasable programmable memory device has a number of contiguous data storage cells forming the data memory of the device. The address of one of these data storage cells is stored to designate it as a cell which is to be write protected so that its contents may not thereafter be erased or overwritten. Information is also stored to identify the total number of contiguous data storage cells to be similarly write protected commencing with the cell whose address is stored to designate write protection. The contents of the designated and identified cells are then made permanent. Write protection of the designated and identified cells is accomplished by comparing each write operation address with the addresses of the data storage cells encompassed within the protected area, and if it is within that area, aborting the write operation.

Secure erase of non-volatile memory

In a non-volatile memory system, a fast bulk secure erase method for erasing data includes, in response to a secure erase command: applying charge to a portion of non-volatile memory in the non-volatile memory system, and performing an erase operation sufficient to remove charge from the portion of non-volatile memory to below an erase threshold. The applied charge is sufficient to program memory cells in the portion of non-volatile memory to above a pre-erase program threshold.

NONVOLATILE MEMORY APPARATUS AND METHOD OF OPERATING THE SAME

Nonvolatile memory apparatuses and methods of operating the same. A nonvolatile memory apparatus includes a nonvolatile memory cell array including a plurality of memory cells; an address decoder configured to receive computation data that indicates a computation from among a plurality of computations and an input data for computation, and the address decoder configured to output an address of the nonvolatile memory cell array corresponding to the indicated computation and input data, the nonvolatile memory cell array being configured to output result data stored at the output address, the result data corresponding to a previous computation performed before receipt of the computation data; and a reading unit configured to read the result data output from the nonvolatile memory cell array.

Solid State Drive Memory Device Comprising Secure Erase Function

A memory device such as a solid state memory device have a dual-hardware, secure erase feature. A memory controller operating in a memory controller domain provides general memory management and interface operons. Upon receipt of a trigger signal which may be received from a secure supervisor circuit, a separate processor element that is configured to directly access the raw memory cells in the device bypasses the memory controller domain and executes a separately provided secure erase operating system whereby the raw cell data may be erased and rewritten with a predetermined data pattern and whereby the erase operation at the raw cell level may be verified and reported to the user by the processor.

Non-volatile storage device with physical authentication

A non-volatile memory device uses physical authentication to enable the secure programming of a boot partition, when the boot partition is write protected. This physical authentication can also be used to enable other features/functions.

Methods and systems for programming secure data into programmable and irreversible cells

Methods and systems for programming secure data into programmable and irreversible memory cells included in electronic circuitry are provided. In general, the secure data is stored in one or more arrays integrated into or associated with an electronic device such as an IC. According to a disclosed method embodying the invention, a programmable and irreversible memory cell array has a control bit for indicating the program state of the array. The method includes reading the control bit of the array to identify a programmable state, loading and programming secure data, read-protecting and write-protecting the array. The control bit is programmed to indicate the non-programmable state of the programmed array. Aspects of the invention include monitoring for incorrectly programmed or unprotected secure data, and in the event such problems arise, programming all cells of the array in order to scuttle the programmed secure data and/or the device information specific to the IC to place the device ...

MEMORY SYSTEM

A memory system includes a nonvolatile memory having a plurality of data blocks each of which is a unit of data erase and has a plurality of pages, each of the pages being a unit of data write, and a controller which checks whether or not the nonvolatile memory has been affected by power interruption at power-on time and, if the nonvolatile memory has been affected by power interruption, writes data to that first page in a first data block which has not been affected by power interruption.

Noise reduction technique for transistors and small devices utilizing an episodic agitation

The present invention presents methods for reducing the amount of noise inherent in the reading of a non-volatile storage device by applying an episodic agitation (e.g. a time varying voltage) to some terminal(s) of the cell as part of the reading process. Various aspects of the present invention also extend to devices beyond non-volatile memories. According to one aspect of the present invention, in addition to the normal voltage levels applied to the cell as part of the reading process, a time varying voltage is applied to the cell. A set of exemplary embodiments apply a single or multiple set of alternating voltages to one or more terminals of a floating gate memory cell just prior to or during the signal integration time of a read process. In other embodiments, other reproducible external or internal agitations which are repeatable, and whose average effect (from one integration time to the next integration time) remains sufficiently constant so as to have a net noise reduction effect ...

Method and device for securing data when altering the storage contents of control units

Methods of securing the erasing and/or programming or reprogramming of data and/or programs in a memory of a computer, in particular a control unit in a motor vehicle, are described. In programming, either an identifier that identifies correct erasing and/or programming of memory is entered into an area of memory that is to be erased and/or programmed or it is selected from the data and/or programs already entered, in particular from a program identifier in the form of a section from it. In addition, the identifier is altered in memory before erasing and/or programming the data and/or programs, in particular by erasing and/or programming, so that the respective memory contents are not used in the event of an interruption in the programming operation and thus in the event of defective programming.

Method and arrangement for the verification of NV fuses as well as a corresponding computer program product and a corresponding computer-readable storage medium

The invention relates to a method and an arrangement for the verification of NV fuses as well as to a corresponding computer program product and to a corresponding computer-readable storage medium which can be used notably for the detection of attacks on the smart card security which modify EEPROM contents and hence also the contents of EEPROM fuses. During the reset phase the fuses are read from the EEPROM. The fuse values successively read out are then automatically verified. One possible implementation is, for example, to load the fuse values read out into a signature register, followed by comparison with a reference value. Appropriate security measures can be activated should the automatic verification indicate an error, for example, due to unauthorized modification of a fuse or attack on the boot operation.

Electronic memory component with protection against light attack

In order to further develop an electronic memory component ( 100 or 100' ), comprising at least one memory cell matrix ( 10 ) which is embedded in and/or let into at least one doped receiving substrate ( 20 ), in such a way that a light incidence taking the form of a so-called light attack is detected directly or sensed immediately without dead times (=contribution to chip development), it is proposed,-that the receiving substrate ( 20 ) be covered and/or surrounded at least partially and/or on at least one of its surfaces remote from the memory cell matrix ( 10 ) by at least one top/protective substrate ( 30 ) oppositely doped to the receiving substrate ( 20 ) and-that at least one of the substrates ( 20 or 30 ), for example the receiving substrate ( 20 ) and/or in particular the top/protective substrate ( 30 ), be in contact ( 12 a or 12 b) or connection ( 32 ) with at least one circuit arrangement ( 24 or 34 respectively) for the detection of voltages or currents caused by charge carriers ...

Migration of memory devices

A computing device that includes a plurality of memory devices and firmware to provide a migration data storage option that reserves a portion of a memory device to store, at least, encrypted metadata describing the physical layout information of the memory devices in preparation for migration of the memory devices.

Memory system with nonvolatile memory

A memory system includes a nonvolatile memory having a plurality of data blocks each of which is a unit of data erase and has a plurality of pages, each of the pages being a unit of data write, and a controller which checks whether or not the nonvolatile memory has been affected by power interruption at power-on time and, if the nonvolatile memory has been affected by power interruption, writes data to that first page in a first data block which has not been affected by power interruption.

Detecting radiation-based attacks

In a device having a plurality of circuits that can store at least a first value and a second value, a method can include configuring at least one circuit to persistently store the first value; determining whether the at least one circuit is storing the second value; and initiating a countermeasure if the at least one circuit is storing the second value. Determining whether the at least one circuit is storing the second value can include detecting whether the device has been attacked. Non-limiting examples of initiating a countermeasure can include resetting a portion of the device, powering down a portion of the device, activating an alarm circuit, causing protected data stored in the device to be erased, causing portions of the device to self-destruct, or causing the device to not respond to input applied to the interface.

PROGRAMMING TECHNIQUES FOR MEMORY DEVICES HAVING PARTIAL DRAIN-SIDE SELECT GATES

A method of operating a memory device. The method includes the step of preparing a memory device that includes a first group of the memory holes with full SGD transistors and a second group of the memory holes with partial SGD transistors. The second group includes both a set of selected partial SGD transistors and a set of unselected partial SGD transistors. The method proceeds with electrically floating a first unselected partial SGD transistor of the set of unselected partial SGD transistors. With the at least one first unselected partial SGD transistor electrically floating, the method continues with reducing a voltage applied to at least one transistor or memory cell adjacent the first unselected partial SGD transistor such that a voltage of the first unselected partial SGD transistor is decreased through a capacitance coupling effect.

MEMORY SYSTEM HAVING A NON-VOLATILE MEMORY AND A CONTROLLER CONFIGURED TO SWITCH A MODE FOR CONTROLLING AN ACCESS OPERATION TO THE NON-VOLATILE MEMORY

A memory system includes a non-volatile memory having a plurality of memory cells and a controller. The controller is configured to switch a mode for controlling an access operation to the non-volatile memory from a first mode to a second mode, in response to receiving from a host, a first command for instructing the controller to switch the mode from the first mode to the second mode. The access operation controlled according to the second mode improves data retention relative to the access operation controlled according to the first mode.

USE DETECTING CIRCUIT

Sector protection circuit and method for flash memory devices

An apparatus and a method for erasing data stored in a memory device

The present invention provides an apparatus and method for erasing data in a memory device comprising an array of memory cells, and configured to operate from a clock signal. The apparatus includes erase circuitry, responsive to receipt of an erase signal in an asserted state, to perform a forced write operation independently of the clock signal in respect of each memory cell within a predetermined erase region of said array. Further, erase signal generation circuitry is configured to receive a control signal and to maintain said erase signal in a deasserted state provided that the control signal takes the form of a pulse signal having at least a predetermined minimum frequency between pulses. The erase signal generation circuitry is further configured to issue said erase signal in said asserted state if the control signal does not take the form of said pulse signal. Such an approach enables the security of a memory device to be improved, and in particular prevents hackers from taking advantage ...

SOLID-STATE MEMORY DEVICE

SEMICONDUCTOR DEVICE WITH SECURE ACCESS KEY AND ASSOCIATED METHODS AND SYSTEMS

STORED INFORMATION PROTECTING CIRCUIT

PURPOSE: To inhibit the reading of any arbitrary bit and any arbitrary area in an EPROM with simple constitutive circuits by adding an EPROM cell for writing data for read inhibition to wiring. CONSTITUTION: When inhibiting the read of the EPROM at the time of a PROM mode, a read inhibit control signal 117 is previously written into an EPROM cell 101 as a prescribed high voltage. When write is performed by injecting electric charges to the floating gate of the EPROM cell 101 with FAMOS structure, since the threshold voltage is increased, the EPROM cell 101 keeps an OFF state even when the read inhibit control signal 117 is turned to a logical level H. Therefore, the voltage level of a drain 113 at the EPROM cell 101 is pulled up to a power supply level through a resistor 108 and turned to H. Since a gate input is turned to H, an (n) channel MOS transistor 103 is turned on, and the voltage of a drain 1 14 at the (n) channel MOS Tr 103 is turned to an L level. COPYRIGHT: (C)1995,JPO ...

Устройство хранения данных с системой синхронизируемого шифрования

Изобретение относится к устройствам хранения данных, в которых применяется шифрование. Задачей является обеспечение дополнительной защищенности данных от внешних воздействий при их хранении. Технический результат заключается в повышении защищенности сохраненных данных за счет синхронизируемого варьирования ключей шифрования и дешифрования в широких пределах, предназначенных для ограниченных временных интервалов (слот), в результате реализуется многократное перешифрование. Устройство содержит запоминающее устройство, генераторы ключей шифрования и дешифрования, шифрователь, дешифрователь, устройство управления, программатор слот, при этом первый выход которого соединен с входом генератора ключей шифрования, второй выход программатора слот подключен к входу устройства управления, третий выход программатора слот соединен с входом генератора ключей дешифрования, вместе с тем шифрователь формирует сигналы Х° для каждого слота. Устройство может быть построено на логических элементах и на программируемых ...

ELEKTRISCHE/ELEKTRONISCHE SCHALTUNGSANORDNUNG

Halbleiterspeicherkarte und Datenlesevorrichtung

Method of operating semiconductor memory device

According to one embodiment, a method of operating a semiconductor memory device is disclosed. The method can include storing read-only data in at least one selected from a memory cell of an uppermost layer and a memory cell of a lowermost layer of a plurality of memory cells connected in series via a channel body. The channel body extends upward from a substrate to intersect a plurality of electrode layers stacked on the substrate. The method can include prohibiting a data erase operation of the read-only memory cell having the read-only data stored in the read-only memory cell.

Destruction of data stored in phase change memory

A mechanism and means by which the data information pattern stored in Phase Change Memory PCM ( 21 ) can be quickly destroyed and made unreadable upon the receipt of a destruction stimuli( 11 ) by the application of a targeted thermal heat source generated by an internal integrated thermal heater ( 26 ), a heat source mounted under the PCM ( 28 ), on top of the PCM ( 29 ), within the PCB ( 30 ), or an externally generated heat source ( 27 ). Such an operation is non-destructive and while the stored data is rendered unreadable, the physical PCM device is unharmed and can be used again.

One-Die Flotox-Based Combo Non-Volatile Memory

A memory access apparatus that controls access to at least one memory array has an array of programmable comparison cells that retain a programmed pass code and compare it with an access pass code. When there is a match between the access pass code and the programmed pass code, the memory access apparatus generates a match signal for allowing access to the at least one memory array. If there is no match, the data within the at least one memory array may be corrupted or destroyed. Each nonvolatile comparison cell has a pair of series connected charge retaining transistors. The programmed pass code is stored in the charge retaining transistors. Primary and complementary query pass codes are applied to the charge retaining transistors and are logically compared with the stored pass code and based on the programmed threshold voltage levels determine if the query pass code is correct.

Flash Memory Device and Method for Handling Power Failure Thereof

A flash memory device. In one embodiment, the flash memory device comprises a flash memory, a diode, a controller, and a capacitor. The flash memory has a voltage source pin. The diode is coupled between a voltage source and the voltage source pin of the flash memory. The controller is coupled to the flash memory via a data bus. The capacitor is coupled between the voltage source pin of the flash memory and a ground, and supplies power to the flash memory to enable the flash memory to complete writing of at least one data page when the level of the voltage source is lowered.

Method for discharging a voltage from a capacitance in a memory device

In discharging a voltage from a circuit capacitance, a supply voltage to a memory device is monitored. The capacitance is discharged through a discharge circuit from a relatively high voltage to a relatively low voltage when the supply voltage decreases below a trip voltage. The trip voltage is set by an architecture of the discharge circuit.

Handheld imaging device with image processor provided with multiple parallel processing units

A handheld imaging device includes an image sensor for sensing an image; a micro-controller integrating therein a dedicated image processor for processing the sensed image, a bus interface, and an image sensor interface; and a plurality of processing units connected in parallel by a crossbar switch, the plurality of processing units provided within the micro-controller to form a multi-core processing unit for the processor. The image sensor interface provides communication between the micro-controller and the image sensor. The bus interface provides communication between the micro-controller and devices external to the micro-controller other than the image sensor.

Handheld imaging device with multi-core image processor integrating image sensor interface

A handheld imaging device includes an image sensor for sensing an image; a processor for processing the sensed image; a multi-core processing unit provided in the processor, the multi-core processing unit having a plurality of processing units connected in parallel by a crossbar switch; and an image sensor interface for converting signals from the image sensor to a format readable by the multi-core processing unit, the image sensor interface sharing a wafer substrate with the processor. A transfer of data from the image sensor interface to the plurality of processing units is conducted entirely on the shared wafer substrate.

Handheld imaging device with vliw image processor

A handheld imaging device includes an image sensor for sensing an image: a Very Long Instruction Word (VLIW) processor for processing the sensed image; a plurality of processing units provided in the VLIW processor, the plurality of processing units connected in parallel by a crossbar switch to form a multi-core processing unit for the VLIW processor; and an image sensor interface for receiving signals from the image sensor and converting the signals to a format readable by the VLIW processor, the image sensor interface sharing a wafer substrate with the VLIW processor. A transfer of data from the image sensor interface to the VLIW processor is conducted entirely on the shared wafer substrate.

Camera system with color display and processor for reed-solomon decoding

A camera system including: a substrate having a coding pattern printed thereon and a handheld digital camera device. The camera device includes: a digital camera unit having a first image sensor for capturing images and a color display for displaying captured images to a user; an integral processor configured for: controlling operation of the first image sensor and color display; decoding an imaged coding pattern printed on a substrate, the printed coding pattern employing Reed-Solomon encoding; and performing an action in the handheld digital camera device based on the decoded coding pattern. The decoding includes the steps of: detecting target structures defining the extent of the data area; determining the data area using the detected target structures; and Reed-Solomon decoding the coding pattern contained in the determined data area.

Non-volatile semiconductor memory device

A non-volatile semiconductor memory device includes: a power supply unit; a memory cell array powered on or off by the power supply unit; and a read unit for reading data recorded on the memory cell array, wherein the data recorded on the memory cell array is not read in response to a control signal, when the memory cell array is powered on or off.

Repair method and device for abnormal-erase memory block of non-volatile flash memory

A repair method for an abnormal-erase memory block of a non-volatile flash memory is provided. The method includes steps of: sequentially scanning bit data in a page of a block when reading data in a NAND flash; determining whether the page is an abnormal-erase page; setting logic “0” bit data in the page to logic “1” when the page is an abnormal-erase page; and re-erasing the block.

Device and Method for Protecting Data in Non-Volatile Memory

Disclosed is a non-volatile memory data protecting device and method. The non-volatile memory data protecting device that is used for protecting non-volatile memory data when a power is shut down in a system, may include a signal delay unit to delay a drop in voltage of an input/output line, a power shutdown sensor to sense power shutdown of a system, and a controller to control the signal delay unit in response to whether the system is shut down.

Storage device, host device, and storage system

A storage device includes a first storage area in which data can be read out and rewritten and file data is stored, a second storage area in which data can be read out and appended to an unwritten area and a first calculated value for detecting falsification which is calculated from the file data, and a controller that performs access control on the first storage area and the second storage area. The controller includes a frontend unit that receives a command from an external host device and accesses the first storage area and the second storage area, and a falsification detection notification unit that determines, without reading out the first calculated value to the host device, whether the first calculated value matches a second calculated value for detecting falsification which is calculated from the file data and notifies the host device of the determination result.

Semiconductor Memory Having Both Volatile and Non-Volatile Functionality and Method of Operating

Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

Nonvolatile memory device and program method thereof

Disclosed is a nonvolatile memory device which includes a nonvolatile memory including a plurality of LSB and MSB pages at a plurality of wordlines; and a controller controlling the nonvolatile memory. The controller controls the nonvolatile memory such that an LSB program operation on a first wordline (first LSB page) of the plurality of wordlines is programmed and then an LSB program operation on a second wordline of the plurality of wordlines (second LSB page) is programmed. When the LSB program operation on the second wordline (second LSB page) is performed, the nonvolatile memory stores information about LSB data programmed at the first wordline (first LSB page) at a spare area of the second wordline (second LSB page).

Semiconductor device capable of block protection

A semiconductor device includes: a memory cell array comprising a plurality of blocks each comprising a memory cell arranged at an intersection between a word line and a bit line; and a block state information storing unit configured to store state information of the respective blocks. The block state information storing unit stores lock state information to partially limit access to each of the blocks in response to a power-up signal.

Nonvolatile memory system and related method of preserving stored data during power interruption

A nonvolatile memory system comprises a temporary power supply that supplies power in the event of an unexpected power interruption. The temporary power supply provides power while metadata stored in one or more buffers is compressed and transferred to a nonvolatile memory device.

Nonvolatile memory, reading method of nonvolatile memory, and memory system including nonvolatile memory

A nonvolatile memory device includes a memory cell array and a read/write circuit connected to the memory cell array through bit lines. The read method of the nonvolatile memory device includes receiving a security read request, receiving security information, and executing a security read operation in response to the security read request. The security read operation includes reading of security data from the memory cell array using the read/write circuit, storing of the read security data in a register, performing security decoding on the read security data stored in the register using the received security information, resetting the read/write circuit, and outputting a result of the security decoding.

Memory system generating random number and method generating random number

In a memory of non-volatile memory cells, a random number is generated by programming non-volatile memory cells, reading the programmed non-volatile memory cells using a random number read voltage selected in accordance with a characteristic of the non-volatile memory cells to generate random read data, and generating the random number from the random read data.

Encrypted-transport solid-state disk controller

An encrypted transport SSD controller has an interface for receiving commands, storage addresses, and exchanging data with a host for storage of the data in a compressed (and optionally encrypted) form in Non-Volatile Memory (NVM), such as flash memory. Encrypted data received from the host is decrypted and compressed using lossless compression for advantageously reducing flash memory write amplification. The compressed data is re-encrypted and stored in the flash memory. The stored data is retrieved, decrypted, decompressed, and re-encrypted before delivery to the host. When implemented within a secure physical boundary, such as a single integrated circuit, the SSD controller protects the encrypted data, from receipt through storage within the flash memory, including delivery to the host. In specific embodiments, the controller exchanges session encryption/decryption keys with the host and/or uses a security protocol such as TCG Opal to determine encryption/decryption keys.

Method for dodging bad page and bad block caused by suddenly power off

A method for dodging bad page and bad block caused by suddenly power off is disclosed. This method is to avoid a new data from host program to potential hurt block or page caused by power off during NAND flash erasing or programming.

ENVELOPE WITH RECORDABLE AUDIO MEDIUM

An article carrier, such as an envelope for holding and presenting an article such as a gift card, includes an electronic device allowing for recording and re-recording of an audio stream or message to accompany the article. The electronic device includes a removable or breakable portion so that the recording may be locked to prevent re-recording. 1. An article carrier , comprising:a body having a foldably movable portion and adapted to receive an article therein, wherein the body comprises paper folded in the form of an envelope and wherein the foldably movable portion of the body is a flap of the envelope; and a power source for powering the electronic device,', 'a re-writeable storage medium for storing an input audio stream thereon as a recording provided by an end user,', 'a record actuator for recording the input audio stream to the re-writeable storage medium,', 'a movable component having a playback position for activating a playback of the recording provided by the end user and currently stored on the re-writeable storage medium, the movable component coupled with the body movable portion, and', 'a breakpoint for disconnecting the record actuator and preventing any further overwriting of the recording provided by the end user and now permanently stored on the re-writeable storage medium;, 'an electronic device positioned within the body, the electronic device including'}wherein the flap has a fully opened position, and the movable component playback position generally corresponds to the fully opened position.2. The article carrier of claim 1 , wherein the breakpoint is located on a circuit between the record actuator and the power source.3. The article carrier of claim 1 , wherein the storage medium is rewriteable memory chip.4. The article carrier of claim 1 , wherein the breakpoint is located on a circuit between the power source and the record actuator claim 1 , and the record actuator is located on the circuit between the storage medium and the ...

Flash Memory Device and Method for Handling Power Failure Thereof

A flash memory device. In one embodiment, the flash memory device includes a flash memory, a diode, a controller, and a capacitor. The flash memory has a voltage source pin. The diode is coupled between a voltage source and the voltage source pin of the flash memory. The controller is coupled to the flash memory via a data bus. The capacitor is coupled between the voltage source pin of the flash memory and a ground, and supplies power to the flash memory to enable the flash memory to complete writing of at least one data page when the level of the voltage source is lowered.

System and Method for Employing Secure Non-Volatile Storage Devices in Gaming Machines

A write-protection system and method for use with a gaming machine. The system having a non-volatile data storage device, an interface device and an electrically conductive connector. The storage device having electronic data storage and a write-protection controller providing a write-protected state and a write-permitting state, the electronic data storage being blocked from receiving electronic write commands in the write-protected state and being able to receive write commands in the write-permitting state. The interface device electrically connecting the data storage device to a power supply and control circuitry of the gaming machine. The interface device connected to the electronic data storage through the controller and the connector. 1. A write-protection system for use with a gaming machine , comprising:a non-volatile data storage device having electronic data storage operatively connected to a write-protection controller, the controller having a control element, associated circuitry and control logic stored on a computer-readable medium for activating a write-protected state and a write-permitting state, in the write-protected state electronic write commands being blocked from being received by the electronic data storage by the controller and in the write-permitting state electronic write commands being able to be received by the electronic data storage;an interface device electrically connecting the data storage device to a power supply and control circuitry of the gaming machine, the interface device connected to the electronic data storage through the controller, andan electrically conductive connector connecting the controller and the interface device, the connector carrying a voltage generated by the power supply.2. The system of where the interface is a serial advanced technology attachment interface.3. The system of where the interface device and storage device have separate connections for the transmission of data and power supplied to the storage ...

EMBEDDED MEMORY USING SOI STRUCTURES AND METHODS

An integrated circuit (IC) includes a semiconductor-on-insulator (SOI) substrate comprising a handle substrate, an insulator layer over the handle substrate, and a semiconductor device layer over the insulator layer. A logic device includes a logic gate arranged over the semiconductor device layer. The logic gate is arranged within a high κ dielectric layer. A memory cell includes a control gate and a select gate laterally adjacent to one another and arranged over the semiconductor device layer. A charge-trapping layer underlies the control gate. 1. An integrated circuit (IC) comprising:a semiconductor-on-insulator (SOI) substrate comprising a handle substrate, an insulator layer over the handle substrate, and a semiconductor device layer over the insulator layer;a logic device comprising a logic gate arranged over the semiconductor device layer, wherein the logic gate is arranged within a high κ dielectric layer; anda memory cell comprising a control gate and a select gate laterally adjacent to one another and arranged over the semiconductor device layer, wherein a charge-trapping layer underlies the control gate.2. The IC according to claim 1 , wherein the SOI substrate is a fully depleted SOI (FDSOI) substrate.3. The IC according to claim 1 , wherein the semiconductor device layer is a monocrystalline silicon layer having a thickness ranging from 5 nm to 40 nm claim 1 , the insulator layer is a silicon dioxide or sapphire layer having a thickness ranging from 10 nm to 60 nm.4. The IC according to claim 1 , wherein the semiconductor device layer has a thickness such that during operation of the memory cell or logic device claim 1 , a depletion region in a channel region of the memory cell or the logic device extends fully across the depths of the semiconductor device layer.5. The IC according to claim 1 , further comprising:an individual source/drain region disposed to a first side of the control gate;an intermediate source/drain region arranged laterally between ...

Switch and semiconductor device including the switch

A device for use with non-volatile memory, includes a first transistor of a first channel type coupled between first and second nodes, including a control gate supplied with a first control signal having a first phase, a second transistor of a second channel type different from the first channel type including a first terminal coupled to the first node, a second terminal coupled to a third node, a back gate coupled to the first terminal thereof, and a control gate supplied with a second control signal having a second phase substantially opposite to the first phase, a third transistor of the second channel type including a first terminal coupled to the second node, a second terminal coupled to the third node, a back gate coupled to the first terminal thereof, and a control gate supplied with the second control signal, and a protection circuit coupled between the first and second node.

Data Storage Device and Method for Operating Data Storage Device

A non-volatile memory operated through multiple channels. The non-volatile memory includes a plurality of chip-enable-signal controlled areas, each containing a plurality of dies. Simultaneous operations on the different dies of at least one target chip-enable-signal controlled space corresponding to a target channel are allowed. The control unit scans the non-volatile memory to check the health status of the dies of the target chip-enable-signal controlled space to assign a plurality of logical enable signals of the target channel to correspond to the dies of the target chip-enable-signal controlled space.

MEMORY CONTROL CIRCUIT UNIT, MEMORY STORAGE DEVICE AND CONTROL METHOD THEREOF

A control method of a memory storage device is provided and includes: detecting a first signal stream controlled by a host system; executing a boot code according to the first signal stream and entering a boot code mode; and receiving a command from the host system in the boot code mode and not executing a firmware code stored in a rewritable non-volatile memory module in the memory storage device. According, operational flexibility of the memory storage device may be enhanced. 1. A memory control circuit unit configured to control a memory storage device , the memory control circuit unit comprising:a host interface, configured to be coupled to a host system;a memory interface, configured to be coupled to a rewritable non-volatile memory module of the memory storage device;a signal detection circuit; anda memory management circuit, coupled to the host interface, the memory interface, and the signal detection circuit,wherein the signal detection circuit is configured to detect a first signal stream controlled by the host system,wherein the memory management circuit is configured to execute a boot code according to the first signal stream and enter a boot code mode,wherein the memory management circuit is further configured to receive a command from the host system in the boot code mode and not to execute a firmware code stored in the rewritable non-volatile memory module after entering the boot code mode.2. The memory control circuit unit as claimed in claim 1 , wherein the memory management circuit is further configured to establish a connection with the host system in the boot code mode after entering the boot code mode.3. The memory control circuit unit as claimed in claim 1 , wherein the memory management circuit is further configured to load the firmware code from the rewritable non-volatile memory module and attempt to establish a connection with the host system based on an execution of the firmware code before the signal detection circuit detects the first ...

SECURITY DEVICE FOR PREVENTING LEAKAGE OF DATA INFORMATION IN SOLID-STATE DRIVE

Disclosed is a security device for preventing leakage of data information in solid-state drive. The present invention provides the security device for preventing leakage of data information in solid-state drive (SSD), the device enabling a user to electrically destroy flash memory personally to prevent leakage of data stored in the SSD, which is used and is to be waste-processed. 1. A security device for preventing leakage of data information in solid-state drive including: a flash memory for storing data; an data interface for data communication with a host; a device controller controlling data exchange operation between the flash memory and the host via the data interface; and a buffer memory temporarily storing data read out from the flash memory by the device controller and data to be recorded in the flash memory ,wherein the solid-state drive is provided with a high-voltage pulse generator generating and outputting a control gate breakdown voltage (a high-voltage pulse ranging DC 60 V to 240 V) capable of destroying a dielectric layer of a control gate of a flash memory cell when a user operates a switch separately from the device controller;a memory controller of the flash memory provides a voltage selector capable of selecting and inputting the high-voltage pulse from the high-voltage pulse generator to a word line of a flash memory cell array; andwhen the user turns on the switch, the memory controller executes addressing on all word lines and bit lines in sequence and applies the control gate breakdown voltage to the word line of the flash memory cell array.2. The data information leakage prevention security device of claim 1 , wherein the high-voltage pulse generator includes:a DC-DC converter electrically connected to an output side of a power supply of a computer to increase a voltage by receiving a DC power from the power supply;a resistor electrically connected to an output side of the DC-DC converter to adjust an output current from the DC-DC ...

Password-based access control for programmable logic devices

A technique includes an access controller of a programmable logic device providing password protection-based access to a memory of the programmable logic device. The programmable logic device initiates programming of the access controller with a password; and in response to the programmable logic device detecting a predetermined stimulus, the programmable logic device initiates communication of the password to the access controller to unlock access to the memory.

PROTECTION CIRCUIT OF MEMORY IN DISPLAY PANEL AND DISPLAY APPARATUS

Disclosed is a protection circuit of a memory in a display panel. The circuit includes: a timing controller (), for outputting a first control signal; a memory (), for storing software data of the timing controller (); a power supply circuit (), for outputting a power signal; and a monitor circuit (), having three input ends and a signal output end, two input ends being respectively connected to the power supply circuit () and a control signal output end, and the other one input end being input with a write control signal; the monitor circuit () controls the memory () to be in a write protection state when in a normal state, and controls the memory () to be in a write enable state when a level state collection of the power signal, the first control signal, and the write control signal satisfies a preset level state collection. 1. A protection circuit of a memory in a display panel , comprising:a timing controller, having a signal transmission end and a control signal output end, the timing controller being configured to output a first control signal of high/low level;a memory, having a signal transmission end and a write protection control end, the signal transmission end of the memory being connected to the signal transmission end of the timing controller; the memory being configured to store software data of the timing controller;a power supply circuit, being configured to output a power signal; anda monitor circuit, having a first input end, a second input end, a third input end, and a signal output end, the first input end being connected to the power supply circuit, the second input end being connected to the control signal output end, the third input end being configured to be input with a write control signal, and the signal output end being connected to the write protection control end;wherein the monitor circuit is configured to:output a write protection signal when in a normal state, to control the memory to be in a write protection state; andoutput a ...

Memory structure for self-erasing secret storage

In one embodiment, memory cell includes a control gate, a floating gate, a substrate comprising a source region and a drain region, a first isolator between the control gate and floating gate, and a second isolator between the floating gate and the substrate. The memory cell is configured to have a retention time that is within a statistical window around a selected lifespan. The selected lifespan may be less than ten years, such as, for example, less than one year, less than one month, or less than one week.

Power supply device, power supply control method, and storage device

According to one embodiment, a power supply device includes a power supply circuit including circuit blocks and configured to generate power supply voltages based on an external power supply, detectors that detect failures of the circuit blocks, a nonvolatile memory, and a controller that stops an operation of the power supply circuit when any of the detectors detects the failure of any of the circuit blocks, and writes failure information of the power supply circuit into the nonvolatile memory. The failure information includes information indicating a type of the failure which has occurred and a circuit block among the circuit blocks in which the failure has occurred.

FLASH MEMORY SYSTEM AND METHOD OF GENERATING QUANTIZED SIGNAL THEREOF

The flash memory system according to the embodiment of the present invention is characterized by programming a selected page in a quantization signal generating operation, providing a reference read voltage to a selected word line connected to the selected page, A flash memory for generating a flash memory; And a memory controller for receiving a quantized signal from the flash memory and generating a response using the quantized signal, wherein the memory controller receives an challenge from a host and the flash memory performs the quantized signal generation. 2. The flash memory system of claim 1 ,wherein the selected page is programmed without a program verify operation.3. The flash memory system of claim 2 ,wherein the selected page is programmed with one program voltage or an increasing program voltage.4. The flash memory system of claim 1 ,wherein a plurality of reference read voltages are provided on the selected word line to separate into a plurality of quantization intervals.5. The flash memory system of claim 4 ,wherein the number of quantization intervals is greater than the number of program states.6. The flash memory system of claim 1 ,wherein the flash memory stores data for the quantized signal in some of the memory cells of the selected page.7. The flash memory system of claim 6 ,Wherein the challenge includes combination order information for some of the memory cells.8. The flash memory system of claim 7 ,wherein the memory controller manages the combination order information for some memory cells using a map table of a flash translation layer.9. The flash memory system of claim 1 ,wherein the memory controller manages data information matched to a threshold voltage distribution state of the flash memory using a map table of a flash translation layer.10. The flash memory system of claim 1 ,wherein the memory controller receives the quantized signal from the flash memory and generates a quantized key.11. A flash memory system comprising:a flash ...

APPARATUSES AND METHODS FOR TRANSISTOR PROTECTION BY CHARGE SHARING

Apparatuses and methods for protecting transistors through charge sharing are disclosed herein. An example apparatus includes a transistor comprising a gate node and a bulk node, a charge sharing circuit coupled between the gate and bulk nodes, and logic. The charge sharing circuit is configure to equalize charge differences between the gate and bulk nodes, and the logic is configured to enable the charge sharing circuit based at least in part on a combination of first and second signals, which indicate the presence of a condition. 1. A method , comprising:providing, by a first voltage source, a high negative voltage to a gate node of a transistor during a first operational mode of a memory;providing, by a second voltage source, a high positive voltage to a bulk node of the transistor during the first operational mode of the memory; andenabling a charge sharing circuit coupled between the gate and bulk nodes of the transistor responsive to a control signal, the control signal based at least in part on an occurrence of a condition.2. The method of claim 1 , further comprising:obtaining, by control circuit, a first signal indicative of the first operational mode;obtaining, by the control circuit, a second signal indicative of a power loss;providing, by the control circuit, the control signal to the charge sharing circuit based at least on the loss of power while the memory is in the first operational mode.3. The method of claim 2 , further comprisescombining, by the control circuit, the first signal indicative of the first operational mode and the second signal indicative of the power loss to provide an output signal; andcombining, by the control circuit, the output signal with a charge share circuit enable signal to generate the control signal based at least in part on the occurrence of the condition, wherein the occurrence of the condition comprises the power loss.4. The method of claim 1 , further comprising:disconnecting the first voltage source from the gate node ...

Semiconductor Memory Having Both Volatile and Non-Volatile Functionality and Method of Operating

Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

PHYSICAL UNCLONABLE FUNCTION FOR NON-VOLATILE MEMORY

A system and method for utilizing a security key stored in non-volatile memory, and for generating a PUF-based data set on an integrated circuit including non-volatile memory cells, such as flash memory cells, are described. The method includes storing a security key in a particular block in a plurality of blocks of the non-volatile memory array; utilizing, in a security logic circuit coupled to the non-volatile memory array, the security key stored in the particular block in a protocol to enable access via a port by external devices or communication networks to data stored in blocks in the plurality of blocks; and enabling read-only access to the particular block by the security logic for use in the protocol, and preventing access to the particular block via the port. 1. A method for generating a data set for storage on a memory , comprising:generating, by a first circuit, first level security information having N bits of data, N being an integer greater than 1;generating, by a second circuit, second level security information having M bits of data, the second level security information being generated as a function of the N bits of data of the first level security information, M being an integer that is less than N; andstoring the second level security information in the memory as the data set.2. The method of claim 1 , wherein the first circuit is a random number generator and the N bits of data of the first level security information are obtained from a randomly generated number.3. The method of claim 2 , wherein the random number generator is a physical unclonable function (PUF) circuit and the N bits of data of the first level security information are obtained using the randomly generated number and programmable memory cells of the PUF circuit.4. The method of claim 1 , wherein the function used to generate the second level security information is a hash function.5. The method of claim 4 , wherein the second circuit applies the hash function to the first level ...

STATE-DEPENDENT READ VOLTAGE THRESHOLD ADAPTATION FOR NONVOLATILE MEMORY

A controller adapts the read voltage thresholds of a memory unit in a non-volatile memory. In one embodiment, the controller determines, based on statistics for a memory unit of the non-volatile memory, an operating state of the memory unit from among a plurality of possible operating states and adapts at least one read voltage threshold for a memory cell in the memory unit based on the determined operating state. 1. A method of adapting read voltage thresholds in a non-volatile memory , the method comprising:a controller determining, for a memory unit of the non-volatile memory, an operating state of the memory unit from among a plurality of possible operating states, wherein the plurality of operating states includes at least first and second operating states; andthe controller adapting at least one read voltage threshold for a memory cell in the memory unit based on the determined operating state, wherein the adapting includes updating the at least one read voltage threshold utilizing a large negative voltage offset in response to detecting a transition of the memory unit from the first operating state to the second operating state.2. The method of claim 1 , wherein the adapting includes the controller selecting at least a number of candidate read voltage thresholds to test.3. The method of claim 2 , wherein the selecting includes dynamically selecting the number of candidate read voltage thresholds to test based on a bit error rate obtained by reading the memory unit utilizing at least one candidate read voltage threshold.4. The method of claim 1 , wherein the adapting includes the controller selecting a range of candidate read voltage thresholds to test.5. The method of claim 1 , wherein the adapting includes adapting the at least one read voltage threshold based on static memory characterization data.6. (canceled)7. The method of claim 1 , wherein the plurality of possible operating states includes a cycling operating state in which the memory unit is ...

DATA STORAGE DEVICE WITH OPERATION BASED ON TEMPERATURE DIFFERENCE

Embodiments of the present disclosure may relate to a memory controller that may include a memory interface and a logic circuitry component coupled with the memory interface. In some embodiments, the logic circuitry component is to program one or more NAND cells of a multi-level NAND memory array via the memory interface with a first set of data in a first pass, determine a first temperature of the multi-level NAND memory array in association with the first pass, determine a second temperature of the multi-level NAND memory array, determine a temperature difference between the second temperature and the first temperature, and perform one or more operations based at least in part on a result of the determination of the temperature difference. Other embodiments may be described and/or claimed. 1. A memory controller comprising:a memory interface; and program one or more NAND cells of a multi-level NAND memory array via the memory interface with a first set of data in a first pass;', 'determine a first temperature of the multi-level NAND memory array in association with the first pass;', 'determine a second temperature of the multi-level NAND memory array;', 'determine a temperature difference between the second temperature and the first temperature; and', 'perform one or more operations based at least in part on a result of the determination of the temperature difference, wherein the one or more operations include one or more of: program the one or more NAND cells with a second set of data in a second pass, in response to the temperature difference being less than or equal to a predefined threshold value; and send a flag indicating that the temperature difference exceeded the predefined threshold value to a host controller, to facilitate an external data read of the one or more NAND cells, data correction associated with the one or more NAND cells, or recovery of data encoded by the one or more NAND cells, in response to the temperature difference being greater than ...

Semiconductor Memory Having Both Volatile and Non-Volatile Functionality and Method of Operating

Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted. 122-. (canceled)23. A semiconductor memory device comprising a string of memory cells connected in series , each said memory cell having:a floating body region configured to be charged to a level indicative of a state of said memory cell to store the state as volatile memory;a first region in electrical contact with said floating body region;a second region in electrical contact with said floating body region and spaced apart from said first region;a floating gate or trapping layer positioned between said first and second regions and configured to receive transfer of data stored as said volatile memory and store said data as non-volatile memory indicative of said state of the memory cell; anda control gate positioned above said floating gate or trapping layer;wherein said charge stored in said floating body region determines a charge stored in said floating gate or trapping layer upon interruption of power to said semiconductor memory device; andwherein said transfer of data to said floating gate or trapping layer occurs to at least two of said memory cells.24. The semiconductor memory device of claim 23 , wherein said floating body region has a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;said first region has a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type; andsaid second ...

SYSTEMS AND METHODS INVOLVING HARDWARE-BASED RESET OF UNRESPONSIVE MEMORY DEVICES

Systems and methods of memory operation that provide a hardware-based reset of an unresponsive memory device are disclosed. In one embodiment, an exemplary system may comprise a semiconductor memory device having a memory array, a controller that may include a firmware component for controlling memory operations, and a reset circuit including power-up circuitry and timeout circuitry. The reset circuit may be configured to detect when the memory device is in a non-responsive state and reset the memory device without using any internal controller components potentially impacted/affected by the non-responsive state. 1. A memory device comprising:at least one memory array;input/output circuitry coupled to the at least one memory array and configured to read from and write to the at least one memory array; an output providing a busy signal indicating that the memory device is busy;', 'memory control components including nodes having electrical connections that render the nodes inoperative when the memory device is busy;, 'control circuitry coupled to the at least one memory array and the input/output circuitry and configured to control operation of the memory device, the control circuitry comprising a first time that the write protect signal is maintained active to perform the reset of the erase or program operation; and', 'a second time, determined for the memory device, that the busy signal is allowed to be active indicating a busy state before the memory device requires reset;, 'reset circuitry coupled to the control circuitry and configured to reset the memory device, the reset circuitry comprising timeout circuitry and logic, wherein the reset circuitry is configured to generate a global reset signal in response to a determination that the timeout circuit has been activated for longer than a predetermined period, wherein the predetermined period is set as being greater than the longer ofwherein the timeout circuitry is configured to activate in response to a write ...

ERASURE CODES TO PREVENT LOWER PAGE CORRUPTION IN FLASH MEMORY

Methods and structure for preventing lower page corruption in flash memory. One embodiment is a flash storage device that includes Multi-Level Cell (MLC) flash memory, Single-Level Cell (SLC) flash memory, and a controller coupled to the MLC flash memory and the SLC flash memory. The controller is configured to program host data to a lower page of the MLC flash memory, to generate an erasure code for the host data, and to store the erasure code in the SLC flash memory. The controller is also configured to detect an interrupted write operation to an upper page linked to the lower page, to retrieve the erasure code from the SLC flash memory, and to correct the host data of the lower page of the MLC flash memory using the erasure code. 1. A flash storage device comprising:Multi-Level Cell (MLC) flash memory;Single-Level Cell (SLC) flash memory; anda controller coupled to the MLC flash memory and the SLC flash memory, the controller configured to program host data to a lower page of the MLC flash memory, to generate an erasure code for the host data, and to store the erasure code in the SLC flash memory;the controller further configured to detect an interrupted write operation to an upper page linked to the lower page, to retrieve the erasure code from the SLC flash memory, and to correct the host data of the lower page of the MLC flash memory using the erasure code.2. The flash storage controller of claim 1 , wherein:the MLC flash memory is configured to store host write operations;the SLC flash memory is configured to store checkpoint data; andthe controller is further configured to generate the erasure code to cover a plurality of lower pages in the MLC flash memory.3. The flash storage controller of claim 2 , wherein:the controller is further configured to manage a hot data band that stores the host write operations in the MLC flash memory, and to manage a checkpoint band that stores the checkpoint data and the erasure code in the SLC flash memory.4. The flash ...

DATA STORAGE DEVICE AND METHOD FOR REWRITING PARAMETERS THEREOF

A data storage device is provided. The data storage device includes a flash memory and a controller. The flash memory stores a firmware that includes a plurality of mode page settings, and each mode page setting includes a plurality of mode parameters. The controller receives a mode selection command and a data out message arranged to rewrite a first mode page setting among the plurality of mode page settings from a host. The controller determines whether the data out message will change the mode parameters which cannot be rewritten in the first mode page setting by performing bitwise logic operations on a new mode page setting in the data out message, preset values of the plurality of mode parameters of the first mode page setting, and a rewriteable setting for each bit of the first mode page setting. 1. A data storage device comprising:a flash memory storing a firmware, wherein the firmware comprises a plurality of mode page settings, and each mode page setting comprises a plurality of mode parameters; anda controller receiving a mode selection command and a data out message from a host, wherein the data out message is arranged to rewrite a first mode page setting among the plurality of mode page settings, and further determining whether the data out message will change mode parameters which cannot be rewritten in the first mode page setting according to the data out message and the first mode page setting by performing bitwise logic operations on a new mode page setting in the data out message, preset values of the plurality of mode parameters of the first mode page setting, and a rewriteable setting for each bit of the first mode page setting,wherein in response to each bit of results of the bitwise logic operations being a zero value, the controller determines that the data out message will not change the mode parameters which cannot be rewritten in the first mode page setting, and determines whether a plurality of new mode parameters are kept in the flash ...

DETECTING FAILURE OF A THERMAL SENSOR IN A MEMORY DEVICE

A program operation on a subset of a plurality of memory cells is performed. A sense operation on the subset of the plurality of memory cells is performed to determine respective values stored in the subset of the plurality of memory cells. One or more patterns of pre-programmed memory cells of the memory device are identified. The one or more patterns comprise representations of values of the pre-programmed memory cells when at least one of a first temperature criterion or a second temperature criterion is satisfied. The respective values of the subset of the plurality of memory cells are compared to the values of the pre-programmed memory cells in the one or more patterns. Based on the comparison, a reading from a thermal sensor coupled to the memory device is determined to satisfy an accuracy criterion. 1. A system comprising:a memory device comprising a plurality of memory cells; and performing a program operation on a subset of the plurality of memory cells;', 'performing a sense operation on the subset of the plurality of memory cells to determine respective values stored in the subset of the plurality of memory cells;', 'identifying one or more patterns of pre-programmed memory cells of the memory device, wherein the one or more patterns comprise representations of values of the pre-programmed memory cells when at least one of a first temperature criterion or a second temperature criterion is satisfied;', 'comparing the respective values of the subset of the plurality of memory cells to the values of the pre-programmed memory cells in the one or more patterns; and', 'determining, based on the comparing, whether a reading from a thermal sensor coupled to the memory device satisfies an accuracy criterion., 'a processing device, operatively coupled with the memory device, to perform operations comprising2. The system of claim 1 , wherein performing the program operation on the subset of the plurality of memory cells comprises programming the subset of the ...

Non-volatile Memory Device With Secure Read

Technology that provides security for a requestor of data stored in a non-volatile memory device is disclosed. In one aspect, the non-volatile memory device provides data on a host interface only if a digest for the data matches an expected digest for the data. The non-volatile memory device may store expected digests for data for various logical addresses. Upon receiving a request on the host interface to read data for a logical address, the non-volatile memory device may access the data for the logical address, compute a digest for the accessed data, and compare the computed digest with the expected digest. The non-volatile memory device provides the accessed data on the host interface only if the computed digest matches the expected digest, in one aspect. The non-volatile memory device may be used to provide a secure boot of a host. 1. An apparatus , comprising:non-volatile memory;a host interface; and access data stored in the non-volatile memory in response to a request on the host interface for data for a logical address;', 'compute a digest of the accessed data; and', 'provide the accessed data on the host interface only if the computed digest matches an expected digest for data for the logical address., 'a control circuit in communication with the non-volatile memory and the host interface, the control circuit configured to2. The apparatus of claim 1 , wherein the control circuit is further configured to:verify integrity of the accessed data based on whether the computed digest matches the expected digest; andprovide the accessed data on the host interface only if the integrity of the accessed data is verified.3. The apparatus of claim 2 , wherein the control circuit is further configured to:verify authenticity of the accessed data based on whether the computed digest matches the expected digest; andprovide the accessed data on the host interface only if the authenticity of the accessed data is verified.4. The apparatus of claim 1 , wherein the control ...

NON-VOLATILE MEMORY WITH READ DISTURB DETECTION FOR OPEN BLOCKS

A non-volatile memory system includes technology for detecting read disturb in open blocks. In one embodiment, the system determines whether a particular block of non-volatile memory cells has been subjected to a minimum number of open block read operations and performs sensing operations for memory cells connected to an open word line of the particular block. The number of errors in the sensed data is determined. If the number of errors is greater than a limit, then the system takes an action to mitigate the read disturb. 1. A non-volatile storage apparatus , comprising:a plurality of non-volatile memory cells; andone or more control circuits in communication with the memory cells, the one or more control circuits are configured to determine whether a particular block of non-volatile memory cells has been subjected to a minimum number of open block read operations, the one or more control circuits are configured to cause sensing of information for memory cells connected to an open word line of the particular block and determine a number of errors based on the sensing if the particular block has been subjected to a minimum number of open block read operations, the one or more control circuits are configured to protect data of the particular block if the number of errors is greater than a limit.2. A non-volatile storage apparatus according to claim 1 , wherein:the one or more control circuits are configured to protect data of the particular block by copying all data of the particular block to a new block.3. A non-volatile storage apparatus according to claim 1 , wherein:the one or more control circuits are configured to protect data of the particular block by subjecting data of the particular block to an error correction process.4. A non-volatile storage apparatus according to claim 1 , wherein:the one or more control circuits are configured to protect data of the particular block by adjusting threshold voltages of memory cells in the particular block.5. A non- ...

NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING

A method of operating a non-volatile memory includes; during power-on, reading control information from an information block and lock information from an additional information block, then upon determining that a secure block should be locked, generating a lock enable signal that inhibits access to data stored in the secure block, and a read-only enable signal that prevents change in the data stored in the additional information block. 1. A method of operating a non-volatile memory device , the method comprising:upon initiating operation of the non-volatile memory device, reading control information from an information block in the non-volatile memory device, and reading lock information from an additional information block in the non-volatile memory device;determining whether a secure block of the non-volatile memory device will be locked in response to the lock information;upon determining that the secure block will be locked, generating a lock enable signal associated with the secure block that inhibits access to data stored in the secure block, and also activating a read-only enable signal associated with the additional information block that prevents change in the data stored in the additional information block.2. The method according to claim 1 , further comprising:upon determining that the secure block will not be locked, performing at least one of a read operation, a program operation, and an erase operation on the secure block.3. The method according to claim 1 , wherein the information block and the additional information block are separate and distinctly addressable regions within a memory cell array of the non-volatile memory device.4. The method of claim 1 , wherein the non-volatile memory comprises a row decoder that receives an address claim 1 , and the method further comprises:applying the lock enable signal to the row decoder to prevent selection of any word line in the secure block during any data access operation.5. The method of claim 4 , further ...

Memory Controllers and User Systems Including the Same

A user system is provided including a plurality of flash memory devices and a memory controller connected to the flash memory devices through a plurality of channels. The memory controller includes a voltage regulator configured to supply a power of the flash memory devices and a compensation unit configured to supply an additional power to the flash memory devices when a power required by the flash memory devices exceeds a predetermined level. The compensation unit includes a resistor unit connected to an output terminal of the voltage regulator and input terminals of the flash memory devices and a charging unit connected to input terminals of the flash memory devices. The charging unit is configured to supply an additional power to the flash memory devices according to voltages of input terminals of the flash memory devices.

Ephemeral Peripheral Device

An ephemeral peripheral system includes an ephemeral memory system and controller circuit for securing user data for a smartphone application. Different secure operating modes are provided for customizing user security requirements across end-to-end communications links, including in exchanges of electronic data between smartphone devices. 1. A portable peripheral computing device adapted to secure data for an application executing on a separate mobile device comprising:an interface on the portable peripheral computing device which is adapted to communicate data between the portable peripheral computing device and a high speed port on the separate mobile device;an ephemeral memory on the portable peripheral computing device which is adapted to store ephemeral data based on a security designation provided by the separate mobile device;an ephemeral memory controller circuit on the portable computing device adapted to write and read said ephemeral data to and from the ephemeral memory based on security parameters provided by the separate mobile device application;the ephemeral memory controller on the portable peripheral computing device being adapted to effectuate at least two (2) separate data erase modes, including:1) a first erase mode in which first ephemeral data in the ephemeral memory is deleted on a bulk basis based on a dedicated erase operation;2) a second erase mode in which second ephemeral data in the ephemeral memory is automatically deleted on a byte or bit basis as part of a read access operation made to such ephemeral data;wherein said second erase mode alters an original physical charge state of cells storing such second ephemeral data, and such that an original value of said second ephemeral data is unreadable.2. The device of wherein the separate mobile device is a smartphone.3. The device of wherein the device is adapted to support a mobile smartphone application implementing a secure communications channel in which no received data from a second ...

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device according to an embodiment comprises: a memory cell array, the memory cell array including a memory block, the memory block including a memory cell, the memory cell including a semiconductor layer, a conductive layer, and a charge accumulation layer, the charge accumulation layer being disposed between the semiconductor layer and the conductive layer; and a control circuit that executes an access operation on the memory cell, the control circuit, triggered by the access operation, detecting a leak current of the conductive layer, and when the leak current is a certain value or more, executing a faulty memory block processing that registers as an access-prohibited region the memory block including the conductive layer. 1. A semiconductor memory device , comprising:a memory cell array, the memory cell array including a memory block, the memory block including a memory cell, the memory cell including a semiconductor layer, a conductive layer, and a charge accumulation layer, the charge accumulation layer being disposed between the semiconductor layer and the conductive layer; anda control circuit that executes an access operation on the memory cell,the control circuit, triggered by the access operation, detecting a leak current of the conductive layer, and when the leak current is a certain value or more, executing a faulty memory block processing that registers as an access-prohibited region the memory block including the conductive layer, andexecuting the faulty memory block processing based on the number of times of executions of the access operation.2. The semiconductor memory device according to claim 1 , whereinthe access operation is a read operation, a write operation, or an erase operation on the memory cell.3. (canceled)4. The semiconductor memory device according to claim 2 , whereinthe control circuit confirms a fail bit number of data read from the memory cell during the read operation, and when the fail bit number is a ...

Fast Secure Erasure Schemes for Non-Volatile Memory

A method includes, in a memory with multiple analog memory cells, storing one or more data pages in respective groups of the memory cells using a first programming configuration having a first storage speed. Upon receiving a request to securely erase a data page from the memory, one or more of the memory cells in a group that stores the data page are re-programmed using a second programming configuration having a second storage speed that is faster than the first storage speed.

SEMICONDUCTOR MEMORY DEVICE FOR PSEUDO-RANDOM NUMBER GENERATION

According to one embodiment, a semiconductor memory device includes a memory cell array including a plurality of memory cells, a random number generation circuit configured to generate a random number, and a controller configured to control the memory cell array and the random number generation circuit. The random number generation circuit includes a random number control circuit configured to generate a random number parameter based on data which is read out from the memory cell by a generated control parameter, and a pseudo-random number generation circuit configured to generate the random number by using the random number parameter as a seed value. 1. A semiconductor memory device comprising:a memory cell array including a plurality of memory cells;a random number generation circuit configured to generate a random number; anda controller configured to control the memory cell array and the random number generation circuit,wherein the random number generation circuit includes:a random number control circuit configured to generate a random number parameter based on data which is read out from the memory cell by a generated control parameter; anda pseudo-random number generation circuit configured to generate the random number by using the random number parameter as a seed value.2. The device of claim 1 , wherein the random number control circuit includes:a control parameter generation circuit configured to generate the control parameter; andan accumulation circuit configured to generate the seed value by executing an accumulation process on read-out data of the memory cell, which is input.3. The device of claim 2 , wherein the control parameter generation circuit includes:an address setting circuit configured to receive a random number generation trigger signal from the controller, and to generate a control parameter of an address at a time of reading out data from the memory cell array, by using an output value of the pseudo-random number generation circuit; anda ...

MEMORY CONTROLLER, MEMORY SYSTEM HAVING THE MEMORY CONTROLLER, AND OPERATING METHOD OF THE MEMORY CONTROLLER

A memory system includes a memory controller. The memory controller includes a program history manager for managing a program history of a first memory unit including a plurality of sub-units of which write protection mode is set; and a memory unit manager for selecting, based on the program history, at least one sub-unit on which a program operation is not performed during a set period among the plurality of sub-units, and releasing the write protection mode of the at least one selected sub-unit. 1. A memory controller comprising:a program history manager configured to manage a program history of a first memory unit including a plurality of sub-units of which write protection mode is set; anda memory unit manager configured to select, based on the program history, at least one sub-unit on which a program operation is not performed during a set period among the plurality of sub-units, and release the write protection mode of the at least one selected sub-unit.2. The memory controller of claim 1 , wherein the memory unit manager selects the at least one sub-unit such that a rate of free units in which data is not stored among sub-units except the at least one sub-unit among the plurality of sub-units is greater than or equal to a threshold value.3. The memory controller of claim 2 , wherein claim 2 , when the rate of free units decreases claim 2 , the memory unit manager resets the write protection mode for a portion of the at least one sub-unit of which write protection mode is released.4. The memory controller of claim 3 , wherein the memory unit manager resets the write protection mode for the portion of the at least one sub-unit of which write protection mode is released such that the rate of free units is greater than or equal to the threshold value.5. The memory controller of claim 3 , wherein claim 3 , when data is programmed in the at least one sub-unit of which write protection mode is released claim 3 , the memory unit manager copies the programmed data to ...

Storage device and method of operating the same

Provided herein may be a storage device and a method of operating the same. A storage device for protecting the storage device from physic& movement may include a nonvolatile memory device, a sensor unit configured to collect information about physical movement of the storage device, and a memory controller configured to perform a device lock operation of protecting data in the nonvolatile memory device, based on a sensor value acquired from the sensor unit.

NAND TEMPERATURE DATA MANAGEMENT

Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion. 1. A NAND device for NAND temperature data management , the NAND device comprising:a NAND component; and receiving a command to write data to the NAND component;', 'obtaining a temperature corresponding to the NAND component in response to receiving the command; and', 'executing the command to write data to the NAND component and to write a representation of the temperature, the data written to a user portion and the representation of the temperature written to a management portion that is accessible only to the NAND controller and segregated from the user portion, wherein the representation of the temperature is a quantization of the temperature at a lower resolution than the obtained temperature., 'a NAND controller to perform operations comprising2. The NAND device of claim 1 , wherein the management portion is on the NAND component.3. The NAND device of claim 2 , wherein the NAND component is a page.4. The NAND device of claim 3 , wherein the management portion is auxiliary bytes of the page.5. (canceled)6. The NAND device of claim 1 , wherein claim 1 , to obtain the temperature claim 1 , the NAND controller obtains the temperature from a thermometer in response to receiving the command.7. The NAND device of claim 1 , wherein the NAND controller is further to read the data from the NAND component and reading the representation of the temperature.8. The NAND device ...

MICROCONTROLLER, MEMORY SYSTEM HAVING THE SAME, AND METHOD FOR OPERATING THE SAME

There are provided a microcontroller, a memory system having the same, and a method for operating the same. A memory system includes: a semiconductor memory performing a scanning operation on ROM data stored in a microcontroller in a test operation and outputting a result of the scanning operation as a status output signal; and a controller for determining whether an error exists in the ROM data, using the status output signal. 1. A memory system comprising:a semiconductor memory device performing a scanning operation on ROM data stored in a microcontroller in a test operation and outputting a result of the scanning operation as a status output signal; anda controller configured to determine whether an error exists in the ROM data, using the status output signal.2. The memory system of claim 1 , wherein the scanning operation checks whether an error exists in the ROM data to detect the error claim 1 , using a cyclic redundancy check (CRC) method.3. The memory system of claim 1 , wherein the microcontroller includes:a control logic configured to store the ROM data, output control signals for controlling a peripheral circuit in response to a command input from the outside, and read and output the ROM data in response to a test mode enable signal in the test operation;a ROM data divider configured to divide and store the ROM data with a set data size, and sequentially output the stored divided data as main data and sub-data;a ROM data scanner configured to output a ROM data scanning signal by performing the scanning operation on the main data or the sub-data in response to a scan clock; andan output circuit configured to poll the ROM data scanning signal in an internal status output signal and output the polled signal as the status output signal.4. The memory system of claim 3 , wherein the microcontroller further includes:a test mode enabler configured to generate the test mode enable signal for enabling a test mode after a power-on reset operation, after a reset ...

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device includes a first transistor including a first end connected to a first pad and a second end connected to a first node, a second transistor including a first end connected to a second pad and a second end connected to the first node, a third transistor including a first end connected to the second pad, a second end connected to the first node, and a gate connected to a second node and having a size different from that of the second transistor, a fourth transistor including a first end connected to the first pad, a second end connected to the second node, and a gate connected to the first node, and a fifth transistor including a first end connected to the second pad, a second end connected to the second node, and a gate connected to the first node. 1. A semiconductor memory device , comprising:a first pad to which a first voltage is supplied;a second pad to which a second voltage different from the first voltage is supplied; and a first transistor including a first end electrically connected to the first pad and a second end electrically connected to a first node,', 'a second transistor including a first end electrically connected to the second pad and a second end electrically connected to the first node,', 'a third transistor including a first end electrically connected to the second pad, a second end electrically connected to the first node, and a gate electrically connected to a second node, and having a size different from that of the second transistor,', 'a fourth transistor including a first end electrically connected to the first pad, a second end electrically connected to the second node, and a gate electrically connected to the first node, and', 'a fifth transistor including a first end electrically connected to the second pad, a second end electrically connected to the second node, and a gate electrically connected to the first node., 'a power supply protection circuit including2. The semiconductor memory device according to ...

MEMORY CONTROL DEVICE, CONTROL METHOD OF FLASH MEMORY, AND METHOD FOR GENERATING SECURITY FEATURE OF FLASH MEMORY

A method for generating a security feature of a flash memory includes determining a memory block from a plurality of memory blocks in the flash memory; erasing data of the determined memory block of the flash memory; providing a predetermined voltage to the determined memory block to obtain a plurality of corresponding threshold voltages of a plurality of cells in the determined memory block, wherein each of the corresponding threshold voltages corresponds to a characteristic of each cell in the determined memory block; and establishing a security feature based on the plurality of corresponding threshold voltages. 1. A method for generating a security feature of a flash memory , comprising:determining a memory block from a plurality of memory blocks in the flash memory;erasing data of the determined memory block of the flash memory;providing a predetermined voltage to the determined memory block to obtain a plurality of corresponding threshold voltages of a plurality of cells in the determined memory block, wherein each of the corresponding threshold voltages corresponds to a characteristic of each cell in the determined memory block; andestablishing a security feature based on the plurality of corresponding threshold voltages of the cells.2. The method according to claim 1 , wherein the step of erasing data of the determined memory block comprises:erasing data in the determined memory block of the flash memory;writing a predetermined data to the determined memory block; anderasing the predetermined data in the written memory block.31. The method according to claim 1 , wherein the predetermined data is zero.41. The method according to claim 1 , wherein the step of providing the predetermined voltage to the memory block is different from a step of writing data to the memory block.51. The method according to claim 1 , wherein the security feature is produced according to at least one of at least part of the plurality of corresponding threshold voltages of the ...

Solving MLC NAND paired page program using reduced spatial redundancy

Reduced spatial redundancy of lower bits data can provide data protection for a flash memory having MLC NAND devices operated in page mode. An interrupted write operation of most significant bit pages can corrupt previously written data in lower bit pages. The lower bits redundant memory can assist in restoring the data, using less than a full back up storage. 1. A method of managing a memory , the method comprising wherein the first memory comprises a plurality of multi-level cell (MLC) memory cells,', 'wherein each MLC memory cell comprises at least a least significant bit (LSB) and a most significant bit (MSB);, 'configuring a first memory and a second memory,'} 'wherein the first data comprise at least LSBs except MSBs of the MLC memory cells;', 'copying first data from the first memory to the second memory,'}writing second data to the MSBs of the MLC memory cells.2. A method as in wherein the first memory is configured from a fabricated memory having a repair portion claim 1 , and wherein the second memory is formed from the repair portion.3. A method as in wherein the first memory comprises a portion of a memory claim 1 , and wherein the second memory comprises a remaining portion of the memory.4. A method as in further comprisingprotecting data in the second memory to prevent from being changed when performing the writing operation to the first memory.5. A method as in further comprisingstoring a write status of the writing operation to the first memory.6. A method as in further comprisingrestoring data from the second memory to the at least the LSBs except the MSBs of the MLC memory cells of the first memory,wherein the restoring operation is performed during a power up of the data storage module when an interrupted writing operation is detected.7. A data storage system comprising wherein the first memory comprises a plurality of multi-level cell (MLC) memory cells,', 'wherein each MLC memory cell comprises at least a least significant bit (LSB) and a most ...

Data Storage Device and Voltage Protection Method Thereof

A data storage device includes a flash memory, a voltage detection device, and a controller. The flash memory is arranged to store data. The voltage detection device is arranged to detect a supply voltage received by the data storage device. The controller is configured to receive write commands from a host, and perform a prohibition mode when the supply voltage is outside a predetermined range, wherein the write command is arranged to enable the controller to write the flash memory, and the controller is further configured to disable all of the write commands received from the host in the prohibition mode. 1. A data storage device , comprising:a flash memory, arranged to store data;a voltage detection device, arranged to detect a supply voltage received by the data storage device; anda controller, configured to receive read commands from a host, and operate in a prohibition mode when the supply voltage is outside a predetermined range, wherein the read command is arranged to enable the controller to retrieve data from the flash memory, and the controller is configured to ignore all of the read commands received from the host while in the prohibition mode.2. The data storage device as claimed in claim 1 , wherein the controller is further configured to receive write commands from the host claim 1 , and ignore all of the write commands received from the host in the prohibition mode claim 1 , wherein the write command is arranged to enable the controller to write data into the flash memory.3. The data storage device as claimed in claim 1 , wherein the controller is further configured to produce a warning signal for noticing the prohibition of reading and writing when the supply voltage is outside the predetermined range.4. The data storage device as claimed in claim 1 , wherein the controller is further configured to read the voltage detection device at a predetermined time interval to obtain a value of the current supply voltage.5. The data storage device as claimed ...

Information processing apparatus, control method thereof, and storage medium

The present information processing apparatus is provided with a flash memory divided into a plurality of areas based on characteristics of information to be stored therein. The present information processing apparatus detects a problem in data stored in each area using a different method for each area, and repairs the detected problem using a different method for each area.

SHUT-OFF MECHANISM IN AN INTEGRATED CIRCUIT DEVICE

Described herein are technologies related to self-disabling feature of a integrated circuit device to avoid unauthorized access to stored data information 1. An integrated circuit (IC) device comprising:a sensor configured to measure a signal;a control unit configured to process the measured signal and provide a triggering signal based upon the measured signal;a high-surge voltage component coupled to the control unit, the high-surge voltage component configured to provide a voltage based upon the triggering signal, wherein the provide voltage is greater than a voltage threshold of a storage component in the IC device, the voltage threshold includes a maximum voltage of operation of the storage component;2. The IC device as recited in claim 1 , wherein the sensor is a dosimeter that is configured to measure amount of radiation exposure of the IC device.3. The IC device as recited in claim 1 , wherein the sensor is an ohm meter that is configured to measure total resistance in a circuitry of the IC device.4. The IC device as recited in claim 1 , wherein the measured signal includes measured biometric identification signals.5. The IC device as recited in claim 1 , wherein the control unit is configured to generate one or more of a remote triggering signal claim 1 , a local software triggering signal claim 1 , or a local hardware triggering signal.6. The IC device as recited in claim 1 , wherein the high-surge voltage component includes one or more of a charged capacitor or a voltage supply that is configured to generate the supplied voltage that is above the threshold voltage of the storage component.7. The IC device as recited in claim 1 , wherein the high-surge voltage component includes a charged capacitor that is configured to generate the supplied voltage when a wireless device is powered OFF.8. A wireless device comprising: The IC device as recited in .9. The IC device as recited in further comprising a micro electro mechanical system (MEMS) coupled to the ...

Nonvolatile memory device for invalidating data stored therein, memory system including the same, and operating method thereof

A memory device includes a plurality of word lines and a plurality of bit lines intersecting the word lines, a memory cell array comprising a plurality of memory cells coupled between the word lines and the bit lines at intersections between the word lines and the bit lines, respectively, an address decoder suitable for decoding an address to access a memory cell selected among the memory cells, and a controller suitable for writing and reading data to and from the selected memory cell by applying voltages to the word lines and bit lines, wherein the controller invalidates data stored in memory cells coupled to a target word line among the word lines by applying an invalidation voltage to the target word line for a set time.

Data Storage Device and Voltage Protection Method Thereof

A data storage device includes a flash memory, a voltage detection device, and a controller. The flash memory is arranged to store data. The voltage detection device is arranged to detect a supply voltage received by the data storage device. The controller is configured to receive write commands from a host, and perform a prohibition mode when the supply voltage is outside a predetermined range, wherein the write command is arranged to enable the controller to write the flash memory, and the controller is further configured to disable all of the write commands received from the host in the prohibition mode. 1. A data storage device , comprising:a flash memory, arranged to store data;a voltage detection device, arranged to detect a supply voltage received by the data storage device; anda controller, configured to receive write commands from a host, and operate ina prohibition mode when the supply voltage is outside a predetermined range, wherein the write command is arranged to enable the controller to write data into the flash memory, and the controller is configured to ignore all of the write commands received from the host while in the prohibition mode.2. The data storage device as claimed in claim 1 , wherein the controller is further configured to receive read commands from the host claim 1 , and ignore all of the read commands received from the host in the prohibition mode claim 1 , wherein the read command is arranged to enable the controller to retrieve data from the flash memory.3. The data storage device as claimed in claim 1 , wherein the controller is further configured to produce a warning signal for noticing the prohibition of reading and writing when the supply voltage is outside the predetermined range.4. The data storage device as claimed in claim 1 , wherein the controller is further configured to read the voltage detection device at a predetermined time interval to obtain a value of the current supply voltage.5. The data storage device as claimed ...

Non-volatile memory devices and systems with read-only memory features and methods for operating the same

Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as read-only memory by not implementing erase or write commands. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to compare an address of a received command to the one or more addresses, and at least in part based on the comparison, determine not to implement the received command. The circuitry can be further configured to return an error message after determining not to implement the received command.

Protection against side-channel attacks on non-volatile memory

A non-volatile memory (NVM) device includes an NVM array, which is configured to store data, and control logic. The control logic is configured to receive data values for storage in the NVM array, and to write at least some of the received data values to the NVM array and simultaneously to write complements of the at least some of the received data values.

Read-only operation of non-volatile memory module

A non-volatile memory module and a read-only operation of the non-volatile memory module are disclosed. A non-volatile memory module such as a non-volatile dual in-line memory module (NVDIMM) may, in response to a command from a host, set a particular memory range of the memory module as a read-only state by storing an address of the memory range with a secret associated with the memory range in an internal database of the memory module. The memory module may then reject a write command to the memory range in the read-only state. The internal database is stored within the memory module and the write protection is implemented inside the memory module so that no external entity may change the protected memory region. 1. A memory module having a capability of read-only operation , comprising:a non-volatile memory; anda controller configured to, in response to a first command from a host, set a memory range of the memory module as a read-only state by storing an address of the memory range with a secret associated with the memory range in an internal database of the memory module, and reject a write command to the memory range in the read-only state,wherein the controller is further configured to indicate to the host, in response to a second command from the host, whether a secret provided with the second command matches the secret stored in the internal database.2. The memory module of claim 1 , wherein the controller is further configured to claim 1 , in response to a third command from the host claim 1 , set the memory range to a read/write state on a condition that a secret provided with the third command matches the secret stored in the internal database.3. The memory module of claim 2 , wherein the memory module is a non-volatile dual in-line memory module (NVDIMM).4. The memory module of claim 1 , wherein the internal database is stored either in the non-volatile memory claim 1 , in an electrically erasable programmable read only memory (EEPROM) in the memory ...

Memory disablement for data security

Apparatuses and methods related to memory disablement for memory security. Disabling the memory for memory security can include, responsive to receiving a trigger signal, provide a voltage, which may be in excess of an operating or nominal voltage, to the access circuitry. The voltage may thus be sufficient to render the access circuitry inoperable for accessing data stored in the memory array.

Solid state storage device and data writing method thereof

A data writing method for a solid state storage device includes following steps. A step (a) is performed to judge whether a shutdown command is issued from a host. In a step (b), if the solid state storage device confirms that the shutdown command is not issued from the host, plural program procedures are performed. Consequently, plural write data in a buffer are stored to a triple-level cell flash memory according to a program order. In a step (c), if the solid state storage device confirms that the shutdown command is issued from the host, plural redundant data are added to the plural write data, the write data are stored into the buffer, and the plural program procedures are performed. Consequently, the plural write data in the buffer are stored to the triple-level cell flash memory according to the program order.

Circuit and method for storing information in non-volatile memory during a loss of power event

A data storage circuit for storing data from volatile memory in response to a power loss, the data storage circuit including an input for receiving a power loss signal in response to a power loss from at least one power source, an input configured to receive data from a volatile memory, a single block of non-volatile matrix of memory cells and a driver circuit coupled to said single row of non-volatile matrix of memory cells. The driver circuit is configured to write data to and read data from said single block of non-volatile matrix of memory cells. The single block of non-volatile matrix of memory cells can be provided as a single row electrically erasable programmable read only memory (EEPROM).

Data storing system and operating method thereof

A method of operating a data storing system includes performing a first copy operation of copying data stored in memory cells of first to n th word lines (n>1, and n is an integer) of a first memory block to first to n th pages of a word line of a second memory block; if a power is turned off, searching for a first erase page, which is recognized to be in an erase state, among the pages of the second memory block when the power comes back on; performing a first map-update on copied pages of the second memory block except for a set number of pages copied right before the first erase page; and performing a second copy operation from the first erase page.

APPARATUSES AND METHODS FOR TRANSISTOR PROTECTION BY CHARGE SHARING

Apparatuses and methods for protecting transistors through charge sharing are disclosed herein. An example apparatus includes a transistor comprising a gate node and a bulk node, a charge sharing circuit coupled between the gate and bulk nodes, and logic. The charge sharing circuit is configure to equalize charge differences between the gate and bulk nodes, and the logic is configured to enable the charge sharing circuit based at least in part on a combination of first and second signals, which indicate the presence of a condition. 1. A method , comprising:monitoring, by logic, for occurrence of a condition; andbased on the occurrence of the condition, coupling a gate node and a bulk node of a transistor and de-coupling the gate node and the bulk node from first and second voltages, respectively.2. The method of claim 1 , wherein the condition is the loss of power during an erase operation.3. The method of claim 1 , wherein the transistor is one or more memory array transistors of a FLASH memory.4. The method of claim 1 , further comprising generating a control signal responsive to occurrence of the condition claim 1 , and wherein coupling the gate node and the bulk node of the transistor comprises enabling a charge sharing circuit coupled between the gate node and the bulk node of the transistor based on the control signal.5. The method of claim 1 , wherein monitoring claim 1 , by logic claim 1 , for occurrence of a condition comprises:receiving, by the logic, a power down signal and an erase operation signal;combining, by the logic, the power down signal and the erase operation signal to provide an output signal; andcombining, by the logic, the output signal with a charge share circuit enable signal to provide the control signal.6. The method of claim 5 , further comprising:combining, by the logic, the output signal with an access line disconnect signal to provide a second control signal; andproviding, by the logic, the second control signal to a switch to ...

NONVOLATILE MEMORY DEVICES AND SOLID STATE DRIVES INCLUDING THE SAME

A nonvolatile memory device includes a memory cell array, a voltage generator, and a control circuit. The voltage generator generates word-line voltages to be applied to the memory cell array. The control circuit generates control signals that control the voltage generator in response to a command and an address. The control circuit includes a hacking detection circuit. The hacking detection circuit disables an operation of the nonvolatile memory device when a hacking is detected, wherein the hacking is detected when an access sequence of the command and the address does not match a standard sequence of the nonvolatile memory device a consecutive number of times. 1. A nonvolatile memory device , comprising:a memory cell array;a voltage generator configured to generate word-line voltages to be applied to the memory cell array; anda control circuit configured to generate control signals that control the voltage generator in response to a command and an address,wherein the control circuit includes a hacking detection circuit configured to disable an operation of the nonvolatile memory device when a hacking is detected, wherein the hacking is detected when an access sequence of the command and the address does not match a standard sequence of the nonvolatile memory device a consecutive number of times.2. The nonvolatile memory device of claim 1 , wherein the hacking detection circuit comprises:an access sequence analyzer configured to analyze the access sequence and to output a decision signal that is enabled when the access sequence does not match the standard sequence;a counter configured to count the decision signal that is enabled and to output a counting signal; anda hacking detection signal generator configured to receive the counting signal and to output a hacking detection signal that is enabled when the counting signal exceeds a reference value.3. The nonvolatile memory device of claim 2 , wherein the access sequence analyzer is configured to output the ...

DETECTING FAILURE OF A THERMAL SENSOR IN A MEMORY DEVICE

Respective values of a subset of the plurality of memory cells of a memory device are compared to a pattern of pre-programmed memory cells. The pattern pre-programmed memory cells comprise representations of values of the pattern of pre-programmed memory cells when a temperature criterion is satisfied. Responsive to determining that at least a threshold number of the respective values of the subset matches the pattern of pre-programmed memory cells, a temperature reading from a thermal sensor coupled to the memory device is identified. Responsive to determining that the temperature reading does not correspond to a temperature criterion, determining that the thermal sensor has failed. 1. A system comprising:a memory device comprising a plurality of memory cells; and comparing respective values of a subset of the plurality of memory cells to a pattern of pre-programmed memory cells on the memory device, wherein the pattern of pre-programmed memory cells comprises representations of values of the pattern of pre-programmed memory cells when a temperature criterion is satisfied;', 'responsive to determining that at least a threshold number of the respective values of the subset matches the pattern of pre-programmed memory cells, identifying a temperature reading from a thermal sensor coupled to the memory device; and', 'responsive to determining that the temperature reading does not correspond to the temperature criterion, determining that the thermal sensor has failed., 'a processing device, operatively coupled with the memory device, to perform operations comprising2. The system of claim 1 , wherein the processing device is to perform operations further comprising:programming the subset of the plurality of memory cells to voltages between valid states of the memory cells.3. The system of claim 1 , wherein the processing device is to perform operations further comprising:responsive to determining that the thermal sensor has failed, sending a notification to a host ...

Semiconductor device with secure access key and associated methods and systems

Memory devices, systems including memory devices, and methods of operating memory devices are described, in which security measures may be implemented to control access to a fuse array (or other secure features) of the memory devices based on a secure access key. In some cases, a customer may define and store a user-defined access key in the fuse array. In other cases, a manufacturer of the memory device may define a manufacturer-defined access key (e.g., an access key based on fuse identification (FID), a secret access key), where a host device coupled with the memory device may obtain the manufacturer-defined access key according to certain protocols. The memory device may compare an access key included in a command directed to the memory device with either the user-defined access key or the manufacturer-defined access key to determine whether to permit or prohibit execution of the command based on the comparison.

METHOD AND DEVICE FOR PROTECTING DATA OF FLASH MEMORY

A method of protecting data of a flash memory is provided. The method includes detecting primary power applied to the flash memory, and applying secondary power converted from the primary power to the flash memory. The primary power is compared to first and second values, and a writing-protection pin of the flash memory is enabled when the detected primary power reaches a predetermined value. 1. A method of protecting data of a flash memory , the method comprising:detecting a primary power applied to the flash memory;applying a secondary power converted from the primary power to the flash memory; andenabling a writing-protection pin of the flash memory in response to the detected primary power reaching a predetermined value.2. The method according to claim 1 , wherein the writing-protection pin is enabled in response to the primary power increasing.3. The method according to claim 1 , wherein the writing-protection pin is enabled before the secondary power is applied to the flash memory.4. The method according to claim 1 , wherein the writing-protection pin is enabled in response to the primary power decreasing.5. The method according to claim 1 , wherein the writing-protection pin is enabled before the secondary power applied to the flash memory decreases.6. A device for protecting data of a flash memory claim 1 , the device comprising:a power supply configured to supply a primary power to the flash memory;a converter configured to apply a secondary power converted from the primary power to the flash memory; anda writing-protection pin enabler configured to enable a writing-protection pin of the flash memory when the primary power reaches a predetermined value.7. The device according to claim 6 , wherein the writing-protection pin is enabled when the primary power increases.8. The device according to claim 6 , wherein the writing-protection pin is enabled before the secondary power is applied to the flash memory.9. The device according to claim 6 , wherein the ...

Management of memory array with magnetic random access memory (mram)

The present invention is directed to a storage device including a storage media and a controller coupled thereto through a high speed interface. The storage media includes one or more byte-addressable persistent memory devices, one or more block-addressable persistent memory devices, a hybrid reserved area spanning at least a portion of the one or more byte-addressable persistent memory devices, and a hybrid user area spanning at least a portion of the one or more block-addressable persistent memory devices. The controller uses the hybrid reserved area to store private data. Each of the one or more byte-addressable persistent memory devices may include one or more magnetic random access memory (MRAM) arrays. Each of the one or more block-addressable persistent memory devices may include one or more NAND flash memory arrays. The high speed interface may be a universal flash storage (UFS) interface that operates in the full-duplex mode.

AUTHENTICATED SIGNALS FOR WRITE PROTECTION

An electronic device comprises circuitry to generate and authenticate a first write protect (WP) signal; a controller to write data to a memory, the controller to generate a second WP signal; and a logic gate coupled to the circuitry and the controller. The logic gate is to receive the first and second WP signals; generate a third WP signal based on the first and second WP signals; and assert the third WP signal to the memory to control a write enable state of the memory. 1. An electronic device , comprising:circuitry to generate and authenticate a first write protect (WP) signal;a controller to write data to a memory, the controller to generate a second WP signal; and receive the first and second WP signals;', 'generate a third WP signal based on the first and second WP signals; and', 'assert the third WP signal to the memory to control a write enable state of the memory., 'a logic gate coupled to the circuitry and the controller, the logic gate to2. The electronic device of claim 1 , wherein the memory comprises an electrically erasable programmable read-only memory (EEPROM).3. The electronic device of claim 1 , wherein the logic gate comprises an AND gate.4. The electronic device of claim 1 , wherein the logic gate comprises a NAND gate claim 1 , an OR gate claim 1 , or a combination thereof.5. The electronic device of claim 1 , wherein the electronic device comprises a first circuit board on which the circuitry is located claim 1 , and wherein the electronic device comprises a second circuit board on which the controller and the logic gate are located.6. The electronic device of claim 1 , comprising a display coupled to the controller claim 1 , the controller to drive the display using data stored in the memory.7. The electronic device of claim 1 , wherein the circuitry includes a second controller and an authentication engine claim 1 , the second controller and the authentication engine to authenticate the first WP signal.8. The electronic device of claim 1 , ...

ADAPTIVE READ THRESHOLD VOLTAGE TRACKING WITH CHARGE LEAKAGE MITIGATION USING CHARGE LEAKAGE SETTLING TIME

Adaptive read reference voltage tracking techniques are provided that employ charge leakage mitigation. An exemplary device for use with multi-level memory cells, comprises a controller configured to: after a predefined time interval that approximates a settling time after a programming of the multi-level memory cells until a charge leakage of one or more of the multi-level memory cells has settled, determine a plurality of read reference voltages for the multi-level memory cells using a post-programming adaptive tracking algorithm; and employ the plurality of read reference voltages to read data from the multi-level memory cells. The reference voltage offsets are optionally determined based on a shift in the read reference voltages after the predefined time interval since the programming of the multi-level memory cells. 1. A device for use with multi-level memory cells , comprising:a controller configured to perform the following steps:after a predefined time interval that is based on a settling time after a programming of the multi-level memory cells until a charge leakage of one or more of the multi-level memory cells has settled, determining a plurality of read reference voltages for the multi-level memory cells using a post-programming adaptive tracking algorithm; andemploying the plurality of read reference voltages to read data from the multi-level memory cells.2. The device of claim 1 , further comprising the step of employing the plurality of read reference voltages shifted by at least one reference voltage offset to read data from the multi-level memory cells during the predefined time interval.3. The device of claim 2 , wherein the shifting is performed until the charge leakage of the multi-level memory cells has settled.4. The device of claim 2 , wherein the at least one reference voltage offset is determined based on a shift in one or more of the read reference voltages after the predefined time interval since the programming of the multi-level memory ...

INCREASED NAND PERFORMANCE UNDER HIGH THERMAL CONDITIONS

Devices and techniques for increased NAND performance under high thermal conditions are disclosed herein. An indicator of a high-temperature thermal condition for a NAND device may be obtained. A workload of the NAND device may be measured in response to the high-temperature thermal condition. Operation of the NAND device may then be modified based on the workload and the high-temperature thermal condition. 1. A non-transitory machine readable medium including instructions to increase burst write performance in a NAND device , the instructions , when executed by processing circuitry , cause the processing circuitry to perform operations comprising:operating a NAND device in accordance with high-temperature policy in response to a high-temperature thermal condition of the NAND device;measuring a command queue of the NAND device to determine that a current workload exhibits a bursty workload profile, the bursty workload profile being a temporary rather than sustained increased change in activity for the NAND device;suspending the high-temperature policy with respect to the current workload;processing the current workload while the high-temperature policy is suspended; andre-implementing the high-temperature policy for the NAND device in response to completing the current workload.2. The machine readable medium of claim 1 , wherein the high-temperature thermal condition is one of an ordered set of thermal conditions for the NAND device claim 1 , members of the set of thermal conditions having respective operating policies for the NAND device.3. The machine readable medium of claim 2 , wherein the respective operating policies include throttling a resource of the NAND device claim 2 , wherein a higher order in the set of thermal conditions corresponds to a greater degree of throttling.4. The machine readable medium of claim 3 , wherein throttling the resource includes powering-off a component of the NAND device claim 3 , a greater degree of throttling corresponding to ...

UNCHANGEABLE PHYSICAL UNCLONABLE FUNCTION IN NON-VOLATILE MEMORY

A device which can be implemented on a single packaged integrated circuit or a multichip module comprises a plurality of non-volatile memory cells, and logic to use a physical unclonable function to produce a key and to store the key in a set of non-volatile memory cells in the plurality of non-volatile memory cells. The physical unclonable function can use entropy derived from non-volatile memory cells in the plurality of non-volatile memory cells to produce a key. Logic is described to disable changes to data in the set of non-volatile memory cells, and thereby freeze the key after it is stored in the set. 1. A circuit configured for maintaining PUF keys in unchangeable form when needed , comprising:a plurality of non-volatile memory cells, wherein the plurality of non-volatile memory cells includes an array of memory cells with peripheral circuits for access to the array;logic to use a physical unclonable function to produce a key, and to store the key in a set of non-volatile memory cells in the plurality of non-volatile memory cells; andlogic to disable changes to data in the set of non-volatile memory cells after the key is stored in the set, wherein the peripheral circuits have a first state in which access to the set of non-volatile memory cells to write the key is enabled, and a second state in which access to the set of non-volatile memory cells to write is disabled while access to other non-volatile memory cells in the array to write is enabled, and wherein the logic to disable changes to data in the set of non-volatile memory cells includes an indicator to set the first state or the second state.2. The circuit of claim 1 , wherein the physical unclonable function utilizes entropy generated using non-volatile memory cells in the plurality of non-volatile memory cells to produce the key.3. The circuit of claim 1 , wherein the logic to disable changes to data in the set of non-volatile memory cells further includes logic that disables use of the physical ...

Recording apparatus, method of controlling recording apparatus, and storage medium

A recording apparatus configured to access a recording medium includes a controller that sets a temperature threshold value for execution of function limitation on the recording medium to the recording medium, wherein, based on an operation state of the recording apparatus, the controller selects whether to execute a first setting to set the temperature threshold value to a specific value or a second setting to set the temperature threshold value to a value greater than the specific value.

APPARATUSES AND METHODS FOR TRANSISTOR PROTECTION BY CHARGE SHARING

Apparatuses and methods for protecting transistors through charge sharing are disclosed herein. An example apparatus includes a transistor comprising a gate node and a bulk node, a charge sharing circuit coupled between the gate and bulk nodes, and logic. The charge sharing circuit is configure to equalize charge differences between the gate and bulk nodes, and the logic is configured to enable the charge sharing circuit based at least in part on a combination of first and second signals, which indicate the presence of a condition. 1. An apparatus , comprising:a transistor comprising a gate node and a bulk node;a charge sharing circuit coupled between the gate node and the bulk node of the transistor, wherein the charge sharing circuit is configured to equalize charge differences between the gate node and the bulk node; andlogic configured to enable the charge sharing circuit based at least in part on a combination of first and second signals, the first and second signals indicative of a condition.2. The apparatus of claim 1 , wherein the transistor further comprises a source node claim 1 , a p-well node claim 1 , and a drain node claim 1 , and wherein the source claim 1 , p-well claim 1 , bulk claim 1 , and drain nodes are coupled together.3. The apparatus of claim 1 , wherein the charge sharing circuit further comprises a switch configured to enable the charge sharing circuit based at least in part on a control signal provided by the logic.4. The apparatus of claim 3 , wherein the charge sharing circuit further comprises a transistor configured to conduct based at least in part on the control signal provided by the logic.5. The apparatus of claim 1 , wherein the logic is further configured to disconnect the gate node from a first voltage source and further configured to disconnect the bulk node from a second voltage source.6. The apparatus of claim 1 , wherein the logic provides three control signals configured to enable the discharge circuit and disconnect the ...

SEMICONDUCTOR DEVICE AND SECURITY SYSTEM

A semiconductor device is provided. The semiconductor device includes a unique-information generation portion, a detection portion, a memory portion, and a readout portion. The unique-information generation portion operates in a plurality of operation environments to generate unique information. The unique information includes stable information and unstable information. The stable information is constant in the plurality of operation environments, and the unstable information is different in at least two of the plurality of operation environments. The detection portion detects the unstable information. The memory portion stores the unique information and identification information for identifying the unstable information. The readout portion reads out the unique information and the identification information and outputs the unique information and the identification information to an external portion. 1. A security system comprising: a unique-information generation circuit configured to operate in a plurality of operation environments to generate unique information, wherein the unique information comprises stable information and unstable information, the stable information is a constant in the plurality of operation environments, and the unstable information is different in at least two of the plurality of operation environments;', 'a controlling logic configured to detect the unstable information; and', 'a memory portion storing the unique information and identification information for identifying the unstable information, wherein the controlling logic reads out the unique information and the identification information stored in the memory portion and outputs the unique information and the identification information; and, 'a semiconductor device comprising a storage portion storing the unique information and the identification information received from the memory portion of the semiconductor device;', 'an information receiving portion receiving the unique ...

SEMICONDUCTOR DEVICE AND SECURITY SYSTEM

A semiconductor device is provided. The semiconductor device includes a unique-information generation portion, a detection portion, a memory portion, and a readout portion. The unique-information generation portion operates in a plurality of operation environments to generate unique information. The unique information includes stable information and unstable information. The stable information is constant in the plurality of operation environments, and the unstable information is different in at least two of the plurality of operation environments. The detection portion detects the unstable information. The memory portion stores the unique information and identification information for identifying the unstable information. The readout portion reads out the unique information and the identification information and outputs the unique information and the identification information to an external portion. 1. A semiconductor device comprising:a unique-information generation circuit configured to operate in a plurality of operation environments to generate unique information, wherein the unique information comprises stable information and unstable information, the stable information is a constant in the plurality of operation environments, and the unstable information is different in at least two of the plurality of operation environments;a controlling logic configured to detect the unstable information and generate code information based on the detected unstable information, wherein the code information comprises a code sequence formed by the stable information and the unstable information and identification information used to identify the unstable information of the code sequence; anda memory portion storing the code information,wherein the controlling logic reads out the code information from the memory portion and outputs the code information to a host device, and,wherein the controlling logic is further configured to delete the code information and the ...

METHODS OF OPERATING NONVOLATILE MEMORY DEVICES

In a method of operating a nonvolatile memory device, a first sub-block to be erased is selected in a first memory block including the first sub-block and a second sub-block adjacent to the first sub-block, in response to a erase command and an address. The first sub-block includes memory cells connected to a plurality of word-lines including at least one boundary word-line adjacent to the second sub-block and internal word-lines other than the at least one boundary word-line. An erase voltage is applied to a substrate in which the first memory block is formed. Based on a voltage level of the erase voltage applied to the substrate, applying, a first erase bias condition to the at least one boundary word-line and a second erase bias condition different from the first erase bias condition to the internal word-lines during an erase operation being performed on the first sub-block. 1. A method of operating a nonvolatile memory device , the method comprising:selecting a first sub-block to be erased in a first memory block including the first sub-block and a second sub-block, adjacent to the first sub-block, in response to a erase command and an address, wherein the first sub-block includes memory cells connected to a plurality of word-lines including at least one boundary word-line adjacent to the second sub-block and internal word-lines other than the at least one boundary word-line;applying an erase voltage to a substrate in which the first memory block is formed; andbased on a voltage level of the erase voltage applied to the substrate, applying a first erase bias condition to the at least one boundary word-line and a second erase bias condition different from the first erase bias condition to the internal word-lines during an erase operation being performed on the first sub-block.2. The method of claim 1 , wherein the voltage level of the erase voltage applied to the substrate increases with a constant slope during a first interval and the voltage level of the erase ...

Method for controlling operations of memory device, associated memory device and controller thereof, and associated electronic device

A method for controlling operations of a memory device, the memory device and the controller thereof, and the associated electronic device are provided. The method can comprise: before a voltage-drop event regarding a driving voltage occurs, mapping a rising reference voltage and a falling reference voltage to a first reference voltage and a second reference voltage, respectively; when the voltage-drop event occurs, pausing at least one access operations to a non-volatile (NV) memory, and mapping the rising reference voltage and the falling reference voltage to another first reference voltage and another second reference voltage, respectively; and when the voltage-drop event ends, mapping the rising reference voltage and the falling reference voltage to the first reference voltage and the second reference voltage, respectively.

Migration of memory devices

A computing device that includes a plurality of memory devices and firmware to provide a migration data storage option that reserves a portion of a memory device to store, at least, encrypted metadata describing the physical layout information of the memory devices in preparation for migration of the memory devices.

RESPONDING TO POWER LOSS

Methods of operating apparatus, as well as apparatus configured to perform such methods, include checking whether power loss to the apparatus during programming of user data to a grouping of memory cells of the apparatus is indicated, and, when power loss is indicated, checking feature settings of the apparatus to determine a location of the apparatus containing an address of the grouping of memory cells, and recovering the address of the grouping of memory cells from the determined location. 1. A method of operating an apparatus , comprising:checking whether power loss to the apparatus during programming of user data to a grouping of memory cells of the apparatus is indicated; checking feature settings of the apparatus to determine a location of the apparatus containing an address of the grouping of memory cells; and', 'recovering the address of the grouping of memory cells from the determined location., 'when power loss is indicated2. The method of claim 1 , further comprising recovering the user data from the determined location.3. The method of claim 2 , further comprising erasing the determined location after recovering the user data and the address of the grouping of memory cells.4. The method of claim 2 , further comprising recovering overhead data associated with the user data from the determined location.5. The method of claim 4 , wherein the overhead data comprises error correction code associated with the user data claim 4 , and further comprising using the error correction code to recover a portion of the user data overwritten by a portion of the address of the grouping of memory cells.6. The method of claim 1 , further comprising checking the feature settings of the apparatus to determine a location of the apparatus containing the user data claim 1 , wherein the determined location of the apparatus containing the user data is different than the determined location of the apparatus containing the address of the grouping of memory cells.7. The method of ...

Memory device and memory system having the same

A memory system includes a plurality of memory cells at intersections between a plurality of word lines and a plurality of bit lines, and a plurality of bit line sense amplifiers connected to the plurality of bit lines, the plurality of bit line sense amplifiers configured to write data to or read data from the plurality of memory cells through the plurality of bit lines, a redundancy bit line sense amplifier among the plurality of bit line sense amplifiers configured to generate a physically unclonable function (PUF) key including a unique random digital value.

METHOD FOR DETECTING A THINNING OF THE SEMICONDUCTOR SUBSTRATE OF AN INTEGRATED CIRCUIT FROM ITS BACK FACE AND CORRESPONDING INTEGRATED CIRCUIT

The thinning of a semiconductor substrate of an integrated circuit from a back face is detected using the measurement of a physical quantity representative of the resistance between the ends of two electrically-conducting contacts situated at an interface between an insulating region and an underlying substrate region. The two electrically-conducting contacts extend through the insulating region to reach the underlying substrate region. 1. A method for detecting a thinning of an integrated circuit semiconductor substrate from its back face , wherein the integrated circuit semiconductor substrate includes a resistance extending between a first end of a first electrically-conducting contact and a second end of a second electrically-conducting contact , comprising:measuring a physical quantity representative of said resistance;comparing said physical quantity to a reference; andindicating that thinning has occurred if the measured physical quantity differs from the reference.2. The method of claim 1 , wherein the physical quantity is a voltage.3. The method of claim 1 , wherein the first and second ends of the first and second electrically-conducting contacts claim 1 , respectively claim 1 , are situated at an interface between an insulating region and an underlying substrate region providing said resistance.4. The method of claim 3 , wherein the first and second electrically-conducting contacts extend through the insulating region.5. The method of claim 1 , further comprising forming a resistive channel buried in the integrated circuit semiconductor substrate claim 1 , wherein the resistance of the resistive channel is dependent on a thickness of the resistive channel.6. The method of claim 5 , wherein the resistive channel is a semiconductor well region within the integrated circuit semiconductor substrate claim 5 , said semiconductor well and integrated circuit semiconductor substrate being doped with opposite conductivity types.7. The method of claim 1 , wherein ...

MULTI-CHIP PACKAGE CAPABLE OF TESTING INTERNAL SIGNAL LINES

A multi-chip package capable of testing internal signal lines including a printed circuit board, a first semiconductor chip mounted on the printed circuit board and including a test circuit, and second semiconductor chips mounted on the printed circuit board and electrically connected to the first semiconductor chip via a plurality of internal signal lines may be provided. The test circuit may be configured to enable circuits of the first semiconductor chip connected to pads contacting the plurality of internal signal lines, transmit complementary data to at least two pads from among the pads, and form a current path in the circuits connected to the at least two pads, thereby detecting a short-circuit between the internal bonding wires. 1. A multi-chip package comprising:a printed circuit board;a first semiconductor chip on the printed circuit board, the first semiconductor chip including a test circuit; andsecond semiconductor chips on the printed circuit board, the second semiconductor chips electrically connected to the first semiconductor chip via a plurality of internal signal lines,wherein the test circuit is configured to enable circuits of the first semiconductor chip connected to pads contacting the plurality of internal signal lines, transmit complementary data to at least two pads from among the pads, and form a current path in the circuits connected to the at least two pads.2. The multi-chip package of claim 1 , whereinthe plurality of internal signal lines comprise bonding wires, andthe pads contacting the plurality of internal signal lines comprise bonding pads.3. The multi-chip package of claim 1 , wherein the circuits connected to the at least two pads comprise output drivers configured to transmit data to the second semiconductor chips via the plurality of internal signal lines.4. The multi-chip package of claim 3 , wherein the test circuit comprises:a path selection circuit configured to enable the output drivers; anda pattern generator configured ...

Memory system having a semiconductor memory device with protected blocks

A memory system includes a semiconductor memory device including a plurality of blocks, and a controller configured to register a block designated in a protection command as a protected block in a storage region. When the control circuit receives from a host a command to erase the protected block or write to the protected block, the control circuit does not issue a corresponding erase or write command to the semiconductor memory device and notifies the host of the failure to execute the command.

Semiconductor memory device and method of operating the same

A semiconductor memory device may include a memory cell array, a peripheral circuit and a control logic. The memory cell array may include a plurality of memory blocks. The peripheral circuit may perform a program operation on a selected memory block among the memory blocks. The control logic may control the program operation of the peripheral circuit. The selected memory block may be coupled with a plurality of bit lines, and the bit lines may be grouped into a first bit line group and a second bit line group based on programing speeds of memory cells coupled to the bit lines that are grouped into the first and second bit line groups. During a blind program operation of the selected memory block, the control logic may control the peripheral circuit to apply different program permission voltages to bit lines of at least two bit line groups.

EMBEDDED MEMORY USING SOI STRUCTURES AND METHODS

An integrated circuit (IC) includes a semiconductor-on-insulator (SOI) substrate comprising a handle substrate, an insulator layer over the handle substrate, and a semiconductor device layer over the insulator layer. A logic device includes a logic gate arranged over the semiconductor device layer. The logic gate is arranged within a high κ dielectric layer. A memory cell includes a control gate and a select gate laterally adjacent to one another and arranged over the semiconductor device layer. A charge-trapping layer underlies the control gate. 1. An integrated circuit (IC) comprising:a semiconductor-on-insulator (SOI) substrate comprising a handle substrate, an insulator layer over the handle substrate, and a semiconductor device layer over the insulator layer;a logic device comprising a logic gate arranged over the semiconductor device layer, wherein the logic gate is arranged within a highκ dielectric layer; anda memory cell comprising a control gate and a select gate laterally adjacent to one another and arranged over the semiconductor device layer, wherein a charge-trapping layer underlies the control gate.2. The IC according to claim 1 , wherein the SOI substrate is a fully depleted SOI (FDSOI) substrate.3. The IC according to claim 1 , wherein the semiconductor device layer is a monocrystalline silicon layer having a thickness ranging from 5 nm to 40 nm claim 1 , the insulator layer is a silicon dioxide or sapphire layer having a thickness ranging from 10 nm to 60 nm.4. The IC according to claim 1 , wherein the semiconductor device layer has a thickness such that during operation of the memory cell or logic device claim 1 , a depletion region in a channel region of the memory cell or the logic device extends fully across the depths of the semiconductor device layer.5. The IC according to claim 1 , further comprising:an individual source/drain region disposed to a first side of the control gate;an intermediate source/drain region arranged laterally between a ...

Electronic apparatus

An electronic apparatus includes a first voltage detection circuit which detects when a voltage, becomes higher than a first level after the voltage starts to be supplied to a peripheral circuit, and detects when the voltage becomes lower than a second level after a supply of the voltage to the peripheral circuit starts to be interrupted, and a second voltage detection circuit which detects when the voltage becomes lower than a reference level while the peripheral circuit operates. The second level is lower than the reference level.

Write Sequence Providing Write Abort Protection

In a multi-level cell (MLC) nonvolatile memory array, data is assigned sequentially to the lower and upper page of a word line, then both lower and upper pages are programmed together before programming a subsequent word line. Word lines of multiple planes are programmed together using latches to hold data until all data is transferred. Tail-ends of data of write commands are stored separately.

Secure Device State Apparatus and Method and Lifecycle Management

A semiconductor chip device include device state fuses that may be used to configure various device states and corresponding security levels for the semiconductor chip as it transitions from wafer manufacturing to provisioned device. The device states and security levels prevent the semiconductor chip from being accessed and exploited, for example, during manufacturing testing. A secure boot flow process for a semiconductor chip over its lifecycle is also disclosed. The secure boot flow may start at the wafer manufacturing stage and continue on through the insertion of keys and firmware. 1. A method of provisioning a semiconductor chip device , the method comprising:determining that the semiconductor chip device is ready for provisioning based on a bit pattern stored in device fuses within the semiconductor chip device;writing boot processing code to non-volatile memory of the semiconductor chip device;verifying an authenticity of the boot processing code;creating a device initialization key using a certificate;disabling the certificate;deriving a plurality of provisioning keys using the device initialization key and the boot processing code;proving identity by providing a device ID and one of the provisioning keys;decrypting provisioning data using another of the provisioning keys; andverifying that the provisioning data is valid.2. The method of claim 1 , wherein the non-volatile memory is flash memory.3. The method of claim 1 , wherein the device initialization key is stored in a firmware readable register.4. The method of claim 1 , wherein the provisioning data includes application-specific flash firmware; andwherein the method further comprises allowing, by the boot processing code, storage of the application-specific flash firmware in the non-volatile memory.5. The method of claim 1 , wherein the certificate is disabled by permanently burning a plurality of the device fuses.6. The method of claim 1 , wherein the certificate is contained within the boot ...

Methods of operating storage devices

In a method of operating a storage device including at least one nonvolatile memory device and a memory controller configured to control the at least one nonvolatile memory device, a boundary page of a first memory block among a plurality of memory blocks included in the at least one nonvolatile memory device is searched for, at least one clean page, in which data is not written, of the first memory block is searched for, a dummy program operation is performed on a portion of the boundary page and the at least one clean page, and an erase operation is performed on the first memory block.