Semiconductor device with voltage generator
The present invention refers to semiconductor device relates to, in particular electrical characteristics for preventing degradation voltage generator of semiconductor device is relates to. Semiconductor device from the outside external voltage transformers, internal circuit through the internal voltage supplied to the level of external voltage and high voltage for, which are used. For example, external voltage applied to the semiconductor device using external voltage in internal circuit when the reference voltage is generated and, generating voltage with a reference voltage clock signal is occurs. Clock signal is applied to the pump section and also as the pump generates a predetermined reference clock signal according to level of external voltage and supplied to the high voltage for. High voltage program operation of a semiconductor device, erase operation and an readout operation is carried out by using an acidulous. In particular, program operation use high voltage to a program voltage, memory cells portion of the program voltage. For example, threshold voltage the program voltage is applied differ depending on the changes of the level of the time or can be. Also according to the prior art Figure 2 shows a and 1 to explain the problem is surface. Also 1 with a, semiconductor device a memory cell included in array is even with times shown in the portion of. Memory cell array different string (string) is connected to the second node includes the memory cells. Different string memory cells are connected to word lines are connected from the control unit via the (WLn-1-WLn+1). Program operation, program voltage (WLn-1-WLn+1) word lines on each of the memory cells can be delivered through, the program voltages applied if having a non-constant delivery times of the memory cell to be programmed (Sel. Cell) sufficient program of the software can be of the wafer is not performed. For example, semiconductor device a resistors resistance value is desired value above the, high voltage occurrence time of the performance event can be is delayed is. Thereby, in a selected memory cell (Sel. Cell) (WLn) word line or more signal selectors coupled to the pass voltage program through the first (Vpass), program pass voltage (VpasS) is applied can be time. Furthermore, memory cell (Sel. Cell) or more signal selectors coupled to the word line (WLn) (Vpgm) program voltage through program voltage even when is applied (Vpgm) is applied can be time. Also refers to surface 2, in a selected memory cell (of Figure 1 Sel. Cell) program pass voltage (of Figure 1 Vpass) or program voltage (of Figure 1 Vpgm) when applied to the semiconductor device having a non-constant threshold voltage of. may be diverted. For example, distribution of threshold voltage can be, giving a wide. As described above, semiconductor device in one embodiment this is done for high voltage level variation semiconductor device can result in surface of each trench. High voltage level of a store instrument preserves change at which may be several, the engine thereby for reducing fuel consumption semiconductor device provided according to resistance value of a resistance (resistor) a unidirected relative to instances in a to account for. Semiconductor device substrate structure in a semiconductor fabrication process, different wafer (wafer) to a manufacturing process embodiment as to correctly ALIGN the condition it is difficult in order to form a. Different memory cell resistance and is formed long by an extrusion forming process may embodiment, this case is mounted on the upper plate of the film solution and drying. The, simultaneously form the second memory cell forming, different wafer by removing the removal process the resistance of one another when a difference occurs in a wafer having a different than θ1. values are also formed of a resistor. Furthermore, semiconductor device plurality of resistance is changed gate of which are included in high frequency noise and samples the first memories, occurrence time of the performance event high voltage due to clock signal can be is changed. Chip selection signal is enabled, resistance based on variations in since is degradable has a superior electric characteristic, reliability of semiconductor device. can be lowered. Is the problem of the present invention, plurality of distributing an voltage using resistance, according to the voltage distributed, thereby generates a reference voltage of an occurrence time of the performance event. Thereby, program operation can be case that the error. In the embodiment according to one of the present invention semiconductor voltage and a control signal a device, formed of plurality of voltage distribution line, each voltage distribution line different resistance value so as to have at least one resistance includes distribution circuit for distributing a including. Distribution circuit a constant voltage and the voltage outputted from the plurality of compared to step-control signals includes a voltage comparing circuit. A respective control signal generates a reference voltage according to a reference voltage signal including voltage generating with the approach of the invention, voltage comparator circuit a, voltage divider output node and lines respectively extending from the signal non-comparators including voltage generation part generates made of a semiconductor device. Other of the present invention semiconductor device in the embodiment according to voltage and a control signal a, formed of plurality of voltage distribution line, each voltage distribution line different resistance value so as to have at least one resistance includes distribution circuit for distributing a including. A constant voltage and the voltage outputted from the distribution circuit compared to step-plurality of control signals includes a voltage comparing circuit. According to a respective control signal generates a reference voltage includes a reference voltage generating part. Reference voltage according to clock signal clock generator part. Clock signals according to the generate a high voltage, so that a pump does not including voltage and a control signal a made of a semiconductor device. A distribution circuit, voltage distribution line are connected in series each includes a plurality of resistors, voltage distribution line is connected to each of the sidewalls including enable switch. Power source voltage and between two adjacent grooves of the distribution line voltage and a terminal is commonly connected to the, other side voltage comparator circuit, respectively are connected. Voltage is applied to the power resistors are within and adjacent a terminal and, enable switches are between voltage comparator circuit with resistance is connected to. Enable switch is embodied in the transistor NMOS. As data output line voltage distribution enable switches voltage is applied to the node and ground are connected between the terminals. Voltage comparator circuit a, voltage divider output node and lines respectively extending from the signal non-comparator including. [...] voltage (band gap) bandgap a constant voltage. Comparators distribution circuit the voltage outputted from the high than a constant voltage level of 'high' level of the control signal outputs, the voltage outputted from the distribution circuit otherwise a constant voltage level of 'low' level of the control signal 10, and outputs it as a. Voltage generator generates an inner power voltage, power voltage is applied to the terminal and ground voltage is applied to the terminal in series between including two tri-state resistors includes line resistance. Resistors during, both resistive the upper substrate in correspondence to the ground voltage is connected to the nodes between includes a reference output line. Resistors between each node and said reference output between the two tri-state switch including. Switches are control signals according the reference output line transmits it reference voltage. Clock signal generating unit generates the switch signal, number 1 input signal to the selected pixels controls an input signal number 1 output signals and voltage generation part generates master clock to the clock points, reference voltage inverse to that of the first back comparing the signals includes a clock for correcting voltage, clock for correcting voltage according to signal from outputting a clock signal clock output part. Clock voltage generator generates an inner power voltage, inverted inverted transformers 200,300 input number 1 number 1 input signal inverted at the output a number 1. including an inverter. Number 1 input signal transformers a inverted at the output input signal number 1 number 2. including an inverter. Clock voltage correction part corrects the, a signal output from inverter number 1 after comparing the sensing voltage from the and a reference voltage 'high' or 'low' level signal a number 1 and includes a comparator, a signal output from inverter number 2 and a reference voltage level by comparing the 'low' or 'high' level signal a number 2. includes a comparator. The clock output a the input signal generated from the number 2 number 1 NAND-gate, the input signal generated from the number 2 inverted includes decoded address signal to a MOS a number 2, number 1 number 1 nAND gate the signals produced in comparator number 2 to the selected pixels according to input signal and outputs an input signal number 2, number 2 number 2 comparator nAND gate in the generated signal is inverted in response to an input signal number 2 and number 2 outputs the input signal. The present invention refers to resistance plurality of distributing an voltage using, distribution mode is set to be a reference voltage difference resistance by generating an according to program operation can be prevent a change of time. The, semiconductor device different resistance value is between program same kind as described above, has operating time for improving reliability of semiconductor device can be. Hereinafter, reference to drawing with an account 1/10 time as large as that of of the present invention preferred embodiment. However, in the embodiment in the present invention refers to hereinafter a disclosure is supported by the upper case and limited to different in various forms can be implemented, and, in the embodiment the present only to a of the present invention disclosure is completely of the invention executable commands for transmitting the clock radio receives 155.520 MB/s data scrambled to completely intenna is to be provided for. Also the present invention according to Figure 3 shows a semiconductor voltage and a control signal is coarse for account device. Semiconductor device the voltage generating unit (300), the branch section (310a, 310b), the pump section and also as the (320), high voltage switch section (330), gradation voltage selecting and inverting part (340), voltage transmission part (350) and a memory cell array (360) includes. Voltage generator generates (300) a power supply voltage (VDD) transformers (PMCK) 10, and outputs it as a corrected clock signal. The branch section (310a and 310b) (PMCK) clock signals, controls data by the driving of a pump signal number 1 and number 2 (CLK1 and CLK2) number 1 for generating a branch section (310a) and a number 3 and number 4 pump signal (CLK3 and CLK4) for generating a number 2 the branch section (310b) includes. Rotary shaft of the pump section and (320) a plurality of pump unit machine comprising such a tool and, number 1 to number 4 (CLK1-CLK4) pump signal according to the source voltage (VDD) raising the voltage level of the (VPP) for the high voltage. High voltage switch section (330) a high voltage (VPP) d (VPPEN) enable high voltage according to. Specifically, high voltage switch section (330) a high voltage (VPP) (Vss) and a ground voltage line is applied between the control terminal and the load is applied connected in series resistance distribution number 1 (331), number 1 device (333), resistance distribution number 2 (332) includes. Furthermore, high voltage switch section (330) a high voltage (VPP) (Vss) and a ground voltage line is applied between serially connected to the number 2 device (334), resistance distribution number 3 (336) and number 4 distribution resistance (337) includes. Furthermore, distribution reference voltage (Ref) and a dispensing delivery voltage generates a synchronous (VR) number 1 device (333) which occur outgoing signals to gate of comparator (335) includes. Number 2 device (334) the number 1 distribution resistance (331) and number 1 device (333) according by means of a voltage applied to nodes between and operates. Furthermore, comparator (335) (VR) voltage delivery distribution applied to the number 3 and number 4 distribution resistance (336 and 337) is supplies the. Gradation voltage selecting and inverting part (340) a high voltage enable global drain select line (GDSL) according to (VPPEN), (GWL0-GWLn) and global source select line global word line operating voltage in (GSSL) transmits it. Voltage transmission part (350) voltage generator generates of operation in which (340) generated from operating voltage characteristics are in a selected memory cell block drain select line (DSL), word line (WL0-WLn) and source select line (SSL). delivering. Memory cell array (360) a series drain select transistor (DST), memory cells (F0-Fn) and source select transistor includes (Samoa Standard Time). Each drain select transistor (DST), memory cells (F0-Fn) and source select transistor a voltage transmission part (Samoa Standard Time) (350) delivered from and operates according drive voltage. Is selected from them, voltage generator generates (300) specifically. off at the first and the second. To illustrate the voltage generation part generates also Figure 4 shows a coarse is for. Voltage generator generates (300) a voltage dispensing portion (400), reference voltage generating part (500) and clock signal generation part (600) includes. Voltage dispensing portion (400) a power supply voltage (VDD) distributed according to one of the first resistance Control signals (SW1-SWk) for. Reference voltage generating part (500) according to the control signals (SW1-SWk) (VREF) for reference voltage. Clock signal generation part (600) generates a reference voltage (VREF) according to d (PMCK) clock signal. Specifically. off at the first and the second. Figure 5 shows a voltage for account dispensing portion is circuit diagram of Figure 4. Voltage dispensing portion (400) the dispense circuit (410) and voltage comparator circuit (420) includes. Distribution circuit (410) the plurality consisting of lines voltage divider. Each voltage distribution line of input terminals are coupled power supply voltage (VDD) is commonly connected to the a node where is applied, different output stage is connected to the nodes. Each voltage distribution line are resistors (R1-Rk) includes (NS) switch generators in each group are operated. Resistors are different distribution line the different voltages are connected in series each number. In distribution line voltage resistors (R1-Rk) voltage distribution line is connected to the adjacent to input stage of, the dispense (NS) enable switches adjacent to output stage and line are connected. A voltage distribution line (NS) enable switches output of and a ground voltage (VSS) is applied is connected between terminal, and operates according to enable signal (en). Voltage divider lines are connected with resistors (R1-Rk) to specifically. off at the first and the second. Each voltage distribution line different number of resistors (R1-Rk) includes. For example, number 1 voltage divider line one resistor (R1) is connected with a, number 2 voltage distribution line is two resistors (R1, R2) are connected. And, number k k line voltage divider of resistors (R1-Rk) is are connected. Chip selection signal is enabled, each voltage distribution line number of resistance which are connected to (NS) of if the enable switches connected the drain only this than θ1. resale applying the current, the current node. The, enable switches (turn off) (NS) is turned off and a (NS) enable switches and, if contained, a voltage level node connected the drain only this of each voltage distribution line. in. However, enable switches (turn on) when (NS) is turned on, each voltage distribution line (NS) enable switches included in the distributed voltage node connected the drain only this of level of than θ1. each other. For example, the number of resistance a farther module and to a small voltage distribution line, the level of the distributed voltage generated, resulting low. Voltage comparator circuit (420) (C1-Ck) comparators the plurality includes. Each non-comparators (C1-Ck) distributed voltage generated in the comparing circuit, (band gap) band gap and thus (vbg) voltage level of control signals (SW1-SWk) for. In particular, different wafer power supply voltage (VDD) and band gap voltage (vbg) in the vertical direction is the same level of, distribution circuit (410) with a distribution generated control signal according to the voltage level it is allowed to develop into at different levels are also (SW1-SWk).. Specifically. off at the first and the second. Each non-comparators (C1-Ck) between the first and the second distribution line level of distributed voltage generated from voltage bandgap, high high than level of (vbg) (high) level of the control signal d (SW1-SWk). The, power supply voltage (VDD) and in a band gap voltage having a uniform level the (vbg). assuming that. Each non-comparators (C1-Ck) level of distributed voltage different level of (vbg) voltage bandgap, otherwise low (high) level of the control signal d (SW1-SWk). Number 3 number 3 control signal generated in the comparator (C3) (SW3) is' high 'level outputs, number 2 number 2 control signal generated in the comparator (C2) (SW2) is' low' brake only the second output terminal outputs to account for the for example. Number 3 (C3) level of distributed voltage applied to comparator bandgap, voltage (vbg) formed on the, number 3 (SW3) control signal outputted from the 'high' level. The, distributed voltage applied to comparator number 3 (C3) distribution of a level higher than a level of voltage is applied to the picture is predicted from another non comparators' high ' (C4-Ck) also outputs a (SW4-SWk) levels of control signals. Furthermore, distributed voltage applied to comparator number 2 (C2) level of voltage bandgap, since the smaller than that of (vbg), number 2 (SW2) control signal outputted from the 'low' level. The, number 2 comparator (C2) distributed voltage applied to voltage is applied to the distribution of a level less than is predicted from another non comparator (C1) also 'low' level of the control signal (SW1) 10, and outputs it as a. I.e., semiconductor device if the voltage dispensing portion are each other (400) from an output in an control signals (SW1-SWk) is output other is also advanced or delayed, respectively. Figure 6 shows a reference voltage generating part account for is circuit diagram of Figure 4. Reference voltage generating part (500) a power supply voltage (VDD) (VSS) voltage and ground terminal is applied between the control terminal and the load is applied (RG1-RGk+2) number 1 to number k+2 distribution resistance connected in series are includes line resistance. Reference voltage generating part (500) the number k+2 distribution resistance (RGk+2) (RGk+1) resistance distribution number k+1 and is connected to the nodes between includes a reference output line. Furthermore, reference voltage generating part (500) the number 1 to number k+2 distribution resistances (RG1-RGk+2) between each node and a reference node, coupled between the at least one output line number 1 to number k includes (NG 1-NGk) switches. Number 1 to number k the NMOS transistor (NG 1-NGk) switches-changed signal is shifted down. Specifically, the (drain) drain (NG 1) switch number 1 (RG1) resistance distribution number 1 (RG2) resistance distribution number 2 and the source connected to the nodes between (source) generates a reference output lines and is coupled, and operates according to control signal number 1 (SW1). The (drain) drain (NGk) switch number k (RGk) resistance distribution number k (RGk+1) resistance distribution number k+1 and the source connected to the nodes between (source) generates a reference output lines and is coupled, and operates according to number k control signal (SWk). The, invention as described above wherein in Figure 5, voltage dispensing portion (400) from an output in an number 1 to number k control signal (SW1-SWk) according to is (turn off) is turned off and a (NGk-2) switch number k-2 number k-1 switch (NGk-1) is turned on (turn on), and if the data, number 1 to number k-2 (NG 1-NGk -2) switch number k to number k-1 turned off and a both the (NGk-1-NGk) switch is turned on. As described above, number 1 to number k-2 switch (NG 1-NGk -2) is turned off and a is (turn off) (NGk-1-NGk) switch number k to number k-1 of the antenna in case that the (turn on) is turned on, power supply voltage (VDD) (RG1-RGk -1) beyond the number 1 to number k-1 distribution resistance (NGk-1) switch number k-1 can be delivered via a reference output line, reference output line voltage passes through an inside wall of a reference voltage (Vref) is. The, , the level of the reference voltage (Vref) number 1 to number k than θ1. are subjected to the action of (NG 1-NGk) switch. Chip selection signal is enabled, voltage dispensing portion (400) variety of voltage changed according to a resistance value and outputs a control signals (SW1-SWk), using the same reference voltage generating part (500) in a constant level (Vref) reference voltage generator includes a divider is formed on according to difference position, placed on the reference voltage (Vref) can be to suppress change of. Figure 7 shows a clock signal generating section to illustrate the circuit diagram of Figure 4 is for. Clock signal generation part (600) receives the clock voltage generator generates (610), clock voltage correction unit (620) and clock output (630) includes. Clock voltage generator generates (610) two inverters numbers which are different from each other (Q1) input signal number 1 to number 1 to the selected pixels respectively applied input signal (/ Q1) number 2 and number 4 node (D2 and D4) reversed through the signal is outputted at the VCR. Specifically, inverted number 1 input signal (/ Q1) is applied to the surface of glass inverter, power supply voltage (VDD) is applied voltage and ground terminal (VSS) is applied between the terminals the switch elements (611 and 612) serially-are connected. Power supply voltage (VDD) switch element and an adjacent terminal is applied (611) is embodied as a the PMOS transistor, ground voltage (VSS) is applied terminal and an adjacent switch element (612) the NMOS transistor is embodied in the. The switch elements (611 and 612) a connected to the gate of a number 1 input signal is reverted to (D1) node number 1 (/ Q1) is applied. The switch elements (611 and 612) between node number 2 (D2) and ground voltage (VSS) is applied between the terminal capacitor (613) is connected. Number 1 input signal (Q1) is applied to the surface of glass inverter, power supply voltage (VDD) is applied voltage and ground terminal (VSS) is applied between the terminals the switch elements (614 and 615) serially-are connected. Power supply voltage (VDD) switch element and an adjacent terminal is applied (614) is embodied as a the PMOS transistor, ground voltage (VSS) is applied terminal and an adjacent switch element (615) the NMOS transistor is embodied in the. The switch elements (614 and 615) (D3) node a connected to the gate of number 1 to number 3 input signal (Q1) is applied. The switch elements (614 and 615) between node number 4 (D4) and ground voltage (VSS) is applied between the terminal capacitor (616) is connected. Clock voltage correction unit (620) the number 1 and number 2 comparator (621 and 623) and a number 1 and number 2 inverter (624 and 622) includes. Non-contact resistance, comparator number 1 (621) the number 2 (D2) (Vref) voltage and the reference voltage applied to node generates a synchronous, reference voltage (Vref) of 'low' if level is higher (low) level of voltage reference voltage (Vref) otherwise further level of 'high' (high) level of voltage for. Number 2 comparator (623) the number 4 (D4) (Vref) voltage and the reference voltage applied to node generates a synchronous, reference voltage (Vref) of 'low' if level is higher (low) level of voltage reference voltage (Vref) otherwise further level of 'high' (high) level of voltage for. The, reference voltage (Vref) the reference voltage generating part (500) is outputted from reference voltage (Vref). In particular, reference voltage (Vref) resistance according to manufacturing process the difference between a constant level by maintaining the number 1 and number 2 comparator (621 and 623) from in addition voltage that is generated can be kept constant. Number 1 inverter (622) the number 1 comparator (621) the voltage generated from a is inverted at the output. Number 2 inverter (624) the number 2 comparator (623) is inverted at the output the voltage generated from a. Clock output part (630) the number 1 and number 2 NAND gate (631 and 632), an inverter (633) includes. Number 1 NAND gate (631) receives the clock voltage correction unit (620) of inverter number 1 (622) number 2 and a signal output from NAND gate (632) according to signals evoked from the number 2 input signal d (Q2). Number 2 NAND gate (632) receives the clock voltage correction unit (620) of inverter number 2 (624) (Q2) and a signal output from number 2 number 2 inverted input signal according to input signal (/ Q2) d. Inverter (633) the inverted the number 2 input signal (Q2) (PMCK) 10, and outputs it as a clock signal. Figure 8 shows a also account for clock signal the present invention according to. plane from the. Also 3 and 8 with a, as described above, in a manufacturing process of the resistance value difference between reference voltage (Vref) of gasket is installed on level is changed, (PMCK) clock signal period of. allow for the modification of. By changing the period of clock signal (PMCK), high voltage (VPP) reach a specific level of a desired level can be adjusting the time during which. The, high voltage switch section (VPPEN) enable high voltage generated in (of Figure 3330) occurrence time of the performance event part of the horizontal frame, in particular word lines (WL0-WLn) delivered to a time of arrival of program voltage can be control. For example, semiconductor device a resistors desired value if the reacquisition time is greater than resistance value is, high voltage (VPP) that a receiving call is generated rapidly word line to be delivered to the time of arrival of driving voltage and prevent it from late can be. Or, resistors semiconductor device is a network monitor measures a transmission resistance value is desired value, high voltage (VPP) on the membrane and therefore slow the time is the word line to be delivered to the driving voltage of arrival of time is shortened, and the can be and prevent it from. I.e., word line driving voltage to be delivered to the time of arrival of since can be made to be even among, and electrical reliability of semiconductor device characteristics are prevented from deteriorating because. Figure 9 shows a also the present invention according to. plane from the account for effect. Also refers to surface 3 and 9, number 1 to number 4 in Figure 8 invention as described above wherein (CLK1-CLK4) pump signal constant period is the ground, the pump section and also as the (320) level of high voltage generated in (VPP) can be, and to maintain in addition. High voltage (VPP) constant level of the ground and to finally word lines which is applied on voltage to be constant purpose: an instrument for an endoscope. Program operation, for example, .off at the first and the second. Program operation, a word line connected to the with a selected memory cell (Sel. Cell) the second resistor is connected between (Vpass) pass voltage programmed, then program voltage (Vpgm) is applied. The, high voltage (VPP) the multiplexer provides a path for applying constant level of applied through the word line program pass voltage (Vpass) and the program voltage (Vpgm) level of or applied without any delay of time between working can be. As described above, whenever a difference occurs in comparison resistance on the second pad when, reference voltage (Vref) level of part of the horizontal frame, clock signal (PMCK) can be control period of. The, high voltage (VPP) occurrence time of the performance event and to adjust the CDMA timing to memory cell via a word line carries a driving voltage that is delivery times of the can be keeping constant an. The technical idea of the present invention taught said preferred embodiment but described in time and embodied in, said for instructing a the in the embodiment the restriction which is for the. attention not. Furthermore, if expert conventional art the present invention refers to of the present invention of the present invention technical idea within the range of a minimum in the embodiment unit is 2000 database for each consumer. Also according to the prior art Figure 2 shows a and 1 to explain the problem is surface. Also the present invention according to Figure 3 shows a semiconductor voltage and a control signal is coarse for account device. To illustrate the voltage generation part generates also Figure 4 shows a coarse is for. Figure 5 shows a voltage for account dispensing portion is circuit diagram of Figure 4. Figure 6 shows a reference voltage generating part account for is circuit diagram of Figure 4. Figure 7 shows a clock signal generating section to illustrate the circuit diagram of Figure 4 is for. Figure 8 shows a also account for clock signal the present invention according to. plane from the. Figure 9 shows a also the present invention according to. plane from the account for effect. < 도면의 주요 부분에 대한 부호의 설명 > 300: voltage generator generates 310a, 310b: the branch section 320:330 rotary shaft of the pump section and: high voltage switch section 340: gradation voltage selecting and inverting part 350: voltage transmission part 360 : GWL0-GWLn memory cell array: global word line WL0-WLn: word line GDSL: global drain select line DSL: drain select line GSSL: global source select line SSL: source select line F0-Fn: memory cell 400: voltage dispensing portion 410: distribution circuit 420: voltage comparator circuit 500: reference voltage generating part 600: clock signal generation unit 610: voltage generator generates clock 611, 612, 614, 615: switch element 613, 616: capacitor 620: clock voltage correction unit 621, 623: comparator 622, 624, 633: inverter 630: clock output part 631, 632: NAND-gate A semiconductor device includes a voltage generator. The voltage generator includes a detection circuit having a number of voltage detection units, each detection unit including a different number of resistors compared to other detection units and each detection unit outputting a respective voltage, a voltage comparison circuit configured to compare a constant voltage to each respective divided voltage outputted from detection units of the detection circuit and to output a number of control signals in response to the comparison, and a reference voltage generator configured to generate a reference voltage in response to the control signals. Formed of plurality of voltage distribution line, each voltage distribution line different resistance value so as to have at least one resistance distribution circuit including; Said distribution circuit and the voltage outputted from the constant voltage step-control signals plurality of compared to a voltage comparing circuit; and Said a respective control signal generates a reference voltage according to a reference voltage signal including voltage generating with the approach of the invention, Said voltage comparator circuit a, said voltage divider output node and lines respectively extending from the signal non-comparators semiconductor device including voltage generation part generates. Formed of plurality of voltage distribution line, each voltage distribution line different resistance value so as to have at least one resistance distribution circuit including; Said distribution circuit and a constant voltage step-the voltage outputted from the plurality of control signals compared to a voltage comparing circuit; Said a respective control signal according to a reference voltage generating part generates a reference voltage; According to said reference voltage generating an intermediate clock signal a clock signal generating section; and Said clock signals according to the a, so that a pump does not generate a high voltage semiconductor device including voltage and a control signal. According to Claim 1 or Claim 2, said distribution circuit a, Said voltage distribution line are connected in series each of a plurality of resistors; and Said voltage distribution line is connected to each of the sidewalls enable switches semiconductor device including voltage and a control signal. According to Claim 3, Said power source voltage and between two adjacent grooves of the distribution line voltage and a terminal is commonly connected to the, other side said voltage comparator circuit and first valve is disposed semiconductor voltage and a control signal device. According to Claim 4, Said resistors are said fast within and adjacent a terminal and voltage is applied to the power, said resistance with said enable switches are said voltage comparator circuit coupled between the device semiconductor voltage and a control signal. According to Claim 3, Said enable switch which are implemented with NMOS transistor semiconductor voltage and a control signal device. According to Claim 3, Said enable switch said voltage distribution line voltage is applied to the node and ground as data output coupled between the terminal semiconductor voltage and a control signal device. According to Claim 2, said voltage comparator circuit a, Said voltage divider output node and lines respectively extending from the signal non-comparators semiconductor device including voltage and a control signal. According to Claim 1 or Claim 2, Said constant voltage bandgap (band gap) voltage can be acquired by back device semiconductor voltage and a control signal. According to Claim 8, Said comparators said distribution circuit the voltage outputted from the level of said constant voltage than high 'high' level of said control signal outputs, said distribution circuit the voltage outputted from the level of said constant voltage otherwise 'low' level of said signal voltage and a control signal semiconductor device. According to Claim 1 or Claim 2, said voltage generator generates an inner power voltage, Power voltage is applied to the terminal and ground voltage is applied to the terminal in series between two tri-state resistors resistance including a; Said resistors during, said both resistive the upper substrate in correspondence to the ground voltage is connected to the nodes between a reference output line; and Said resistors between each node and said reference output between the two tri-state switches semiconductor device including voltage and a control signal. According to Claim 11, Said switches are said control signals according the reference output line reference said carrying voltages above semiconductor voltage and a control signal device. According to Claim 2, said clock signal generating unit generates the switch signal, Number 1 input signal to the selected pixels controls an input signal number 1 of outputting the signal voltage generator generates clock; Said reference voltage and said inverted comparing the signals a clock voltage correction unit; and Signal from said clock for correcting voltage outputting a clock signal according to a clock output semiconductor device including voltage and a control signal. According to Claim 13, said clock voltage generator generates an inner power voltage, Said inverted inverted said transformers 200,300 input number 1 number 1 input signal inverter number 1 a inverted at the output; and Said number 1 input signal transformers said number 1 number 2 a inverted at the output input signal inverter semiconductor device including voltage and a control signal. According to Claim 14, said clock voltage correction part corrects the, Said and a signal output from inverter said number 1 generates a synchronous reference voltage 'high' or 'low' level signal a number 1 comparator; and Inverter said number 2 and a signal output from said reference voltage by comparing the level of 'low' or 'high' level signal comparator a number 2 semiconductor device including voltage and a control signal. According to Claim 15, The clock output said said number 2 a the input signal generated from the number 1 NAND-gate, the input signal generated from the number 2 inverted includes decoded address signal to a MOS a number 2, The signals produced in comparator said number 1 nAND gate said number 1 and number 2 inverted said said number 2 in response to an input signal and outputs an input signal, In comparator said number 2 nAND gate said number 2 and the generated signal is said input signal according to said number 2 number 2 inverted outputs an input signal voltage and a control signal semiconductor device.