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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 3530. Отображено 100.
28-06-2012 дата публикации

Single check memory devices and methods

Номер: US20120163076A1
Автор: Aaron Yip, Tomoharu Tanaka, Vishal Sarin
Принадлежит: Individual

Memory devices and methods of operating memory devices are shown. Configurations described include circuits to perform a single check between programming pulses to determine a threshold voltage with respect to desired benchmark voltages. In one example, the benchmark voltages are used to change a programming speed of selected memory cells.

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Номер записи: 1
28-06-2012 дата публикации

Data management in flash memory using probability of charge disturbances

Номер: US20120166897A1
Автор: Luiz M. Franca-Neto, Richard Leo Galbraith, Travis Roger Oenning
Принадлежит: Individual

A Flash memory system and a method for data management using the system's sensitivity to charge-disturbing operations and the history of charge-disturbing operations executed by the system are described. In an embodiment of the invention, the sensitivity to charge-disturbing operations is embodied in a disturb-strength matrix in which selected operations have an associated numerical value that is an estimate of the relative strength of that operation to cause disturbances in charge that result in data errors. The disturb-strength matrix can also include the direction of the error which indicates either a gain or loss of charge. The disturb-strength matrix can be determined by the device conducting a self-test in which charge-disturb errors are provoked by executing a selected operation until a detectable error occurs. In alternative embodiments the disturb-strength matrix is determined by testing selected units from a homogeneous population.

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Номер записи: 2
30-08-2012 дата публикации

Test circuit, semiconductor memory apparatus using the same, and test method of the semiconductor memory apparatus

Номер: US20120218846A1
Автор: Yong Gu Kang
Принадлежит: SK hynix Inc

A test circuit of a semiconductor memory apparatus includes: a test control signal generating unit configured to enable a control signal if an active signal is enabled after a test signal is enabled, and substantially maintain the control signal in an enable state until a precharge timing signal is enabled; and a precharge control unit configured to invert the control signal to output the inverted signal as a bit line precharge signal when a preliminary bit line precharge signal is in a disable state.

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Номер записи: 3
10-01-2013 дата публикации

Method of Detecting Connection Defects of Memory and Memory Capable of Detecting Connection Defects thereof

Номер: US20130010558A1
Автор: Lien-Sheng Yang, Min-Chih Chang, Shih-Hsing Wang, Te-Yi Yu
Принадлежит: Individual

By inputting voltages to global word lines of a memory, and by detecting currents of corresponding global word lines, a relation function between the currents and the voltages can be generated, and connection defects on the global word lines can be determined according to various types of deviation of a relation curve corresponding to the relation function between the currents and voltages.

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Номер записи: 4
04-07-2013 дата публикации

Electronic device and method for testing endurance of memory

Номер: US20130170307A1
Автор: Min Tan
Принадлежит: Hon Hai Precision Industry Co Ltd, Hongfujin Precision Industry Shenzhen Co Ltd

An electronic device for endurance test of a memory includes an interface, a storage unit, an obtaining unit, and a control unit. The interface is for connecting the memory to the electronic device. The storage unit stores a variety of test packages for different storage capacities of memories and at least one test option associated with each test package. The test option defines a predetermined capacity of the associated memory to be tested. The obtaining unit obtains a storage capacity of the memory connected to the electronic device. The control unit selects one of the at least one test option associated with one of the test packages corresponding to the obtained storage capacity, selects a plurality of blocks according to the predetermined capacity of the selected test option, assigns corresponding logical addresses to the selected blocks, and then tests the endurance of the selected blocks.

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Номер записи: 5
22-08-2013 дата публикации

Spin-transfer torque memory self-reference read method

Номер: US20130215674A1
Автор: Dimitar V. Dimitrov, Hai Li, Henry F. Huang, Hongyue Liu, Kang Yong Kim, Yiran Chen
Принадлежит: SEAGATE TECHNOLOGY LLC

A spin-transfer torque memory apparatus and self-reference read schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage. Then applying a low resistance state polarized write current through the magnetic tunnel junction data cell, forming a low second resistance state magnetic tunnel junction data cell. A second read current is applied through the low second resistance state magnetic tunnel junction data cell to forming a second bit line read voltage. The method also includes comparing the first bit line read voltage with the second bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state.

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Номер записи: 6
22-08-2013 дата публикации

Tracking capacitive loads

Номер: US20130215693A1
Автор: Annie-Li-Keow Lum, Bing Wang, Derek C. Tao, Kuoyuan (Peter) Hsu, Young Seog Kim
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A time delay is determined to cover a timing of a memory cell in a memory macro having a tracking circuit. Based on the time delay, a capacitance corresponding to the time delay is determined. A capacitor having the determined capacitance is utilized. The capacitor is coupled to a first data line of a tracking cell of the tracking circuit. A first transition of the first data line causes a first transition of a second data line of the memory cell.

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Номер записи: 7
22-08-2013 дата публикации

Semiconductor memory device changing refresh interval depending on temperature

Номер: US20130215700A1
Автор: Akinobu Shirota, Kuninori Kawabata
Принадлежит: Fujitsu Semiconductor Ltd

A semiconductor memory device includes a memory core circuit having memory cells for storing data, a circuit configured to refresh the memory core circuit at a refresh interval, a temperature detecting unit configured to detect temperature, and a control circuit configured to shorten the refresh interval immediately in response to detection of a predetermined temperature rise by the temperature detecting unit and to elongate the refresh interval after refreshing every one of the memory cells at least once in response to detection of a temperature drop by the temperature detecting unit.

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Номер записи: 8
29-08-2013 дата публикации

Oscillator based on a 6T SRAM for measuring the Bias Temperature Instability

Номер: US20130222071A1
Автор: Ching-Te Chuang, Hao-I Yang, Kuen-Di Lee, Ming-Chien Tsai, Ming-Hsien Tu, Nan-Chun Lien, Shyh-Jye Jou, Wei Hwang, Wei-Chiang Shih, Yi-Wei Lin
Принадлежит: National Chiao Tung University NCTU

The present invention provides an oscillator which is based on a 6T SRAM for measuring the Bias Temperature Instability. The oscillator includes a first control unit, a first inverter, a second control unit, and a second inverter. The first control unit is coupled with the first inverter. The second control unit is coupled with the second inverter. The first control unit and the second control unit is used to control the first inverter and the second inverter being selected, biased, and connected respectively, so that the NBTI and the PBTI of the SRAM can be measured separately, and the real time stability of the SRAM can be monitored immediately.

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Номер записи: 9
13-03-2014 дата публикации

Technique for Determining Performance Characteristics Of Electronic Devices And Systems

Номер: US20140070819A1
Автор: Haw-Jyh Liaw, Mark A. Horowitz, Xingchao Yuan
Принадлежит: RAMBUS INC

A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.

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Номер записи: 10
27-03-2014 дата публикации

Serial advanced technology attachment dual in-line memory module device having testing circuit for capacitor

Номер: US20140089739A1
Автор: Guo-Yi Chen, Xiao-Gang Yin
Принадлежит: Individual

A serial advanced technology attachment dual in-line memory module device includes a capacitor to be tested, a control chip, a display device, a testing chip, and a selecting chip. Voltage pins of the testing chip and the selecting chip are connected to a power source. A testing pin of the testing chip is connected to the capacitor. A first input output (I/O) pin of the selecting chip is connected to a first I/O pin of the testing chip. A second I/O pin of the selecting chip is connected to a second I/O pin of the testing chip. A third I/O pin of the selecting chip is connected to an input pin of the control chip. A fourth I/O pin of the selecting chip is connected to an output pin of the control chip. A fifth I/O pin of the selecting chip is connected to the display device.

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Номер записи: 11
10-04-2014 дата публикации

Apparatuses and methods for sensing fuse states

Номер: US20140098623A1
Автор: Marco Sforzin
Принадлежит: Micron Technology Inc

Apparatuses and methods for sensing fuse states are disclosed herein. An apparatus may include an array having a plurality of sense lines. A plurality of cells may be coupled to a sense line of the plurality of sense lines. A fuse sense circuit may coupled to the sense line of the plurality of sense lines and configured to receive a sense voltage from a cell of the plurality of cells. The sense voltage may be based, at least in part, on a state of a fuse corresponding to the cell of the plurality of cells. The fuse sense circuit may further be configured to compare the sense voltage to a reference voltage to provide a fuse state control signal indicative of the state of the fuse.

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Номер записи: 12
04-01-2018 дата публикации

ERROR CORRECTION CODE EVENT DETECTION

Номер: US20180004596A1
Автор: Kreifels Gerard A., Lei Jianfei, Mangalindan Paolo E., Proescholdt Andrew D., Zhang Yihua
Принадлежит:

Methods, systems, and devices for operating a memory cell or cells are described. An error in stored data may be detected by an error correction code (ECC) operation during sensing of the memory cells used to store the data. The error may be indicated in hardware by generating a measurable signal on an output node. For example, the voltage at the output node may be changed from a first value to a second value. A device monitoring the output node may determine an error has occurred for a set of data based at least in part on the change in the signal at the output node. 1. A method of operating an electronic memory apparatus , comprising:identifying a codeword from a read operation of the electronic memory apparatus;detecting an error in the codeword based at least in part on an error correction code (ECC) operation associated with the codeword; andtransmitting a signal indicative of the error detection to a node of the electronic memory apparatus.2. The method of claim 1 , wherein the error comprises a one bit error or a two bit error.3. The method of claim 1 , further comprising:selecting a type of error to be detected in response to a user input.4. The method of claim 3 , wherein the type of error comprises a one bit error or a two bit error claim 3 , or both.5. The method of claim 1 , further comprising:enabling an error detection mode, wherein the error in the codeword is detected based at least in part on enabling the error detection mode.6. The method of claim 1 , wherein the read operation comprises:applying a first voltage to a set of memory cells associated with the codeword; anddetermining a voltage or current corresponding to each memory cell of the set of memory cells based at least in part on the application of the first voltage, wherein the codeword is identified based at least in part on the determination of the voltages or currents corresponding to each memory cell.7. The method of claim 1 , further comprising:storing an indication of the detected ...

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Номер записи: 13
05-01-2017 дата публикации

STRUCTURE AND METHOD FOR ADJUSTING THRESHOLD VOLTAGE OF THE ARRAY OF TRANSISTORS

Номер: US20170004873A1
Автор: Cai Jin, Cheng Kangguo, Dennard Robert H., Khakifirooz Ali, Ning Tak H.
Принадлежит:

A semiconductor device including a charge storage element present in a buried dielectric layer of the substrate on which the semiconductor device is formed. Charge injection may be used to introduce charge to the charge storage element of the buried dielectric layer that is present within the substrate. The charge that is injected to the charge storage element may be used to adjust the threshold voltage (Vt) of each of the semiconductor devices within an array of semiconductor devices that are present on the substrate. 1. A method of adjusting threshold voltage in a memory device comprising:providing a static random access memory (SRAM) device comprising at least two p-type pull up transistors, at least two n-type pull down transistors, a first pass gate transistor and a second pass gate transistor on a substrate, wherein the at least two p-type pull up transistors and the at least two n-type pull down transistors provide a storage cell, and the first and the second pass gate transistors provide an access to the storage cell, and wherein the at least two p-type pull up transistors and the at least two n-type pull down transistors overlie a charge storage element present in a dielectric layer of the substrate;measuring a test electrical property of at least one of the at least two p-type pull up transistors and the at least two n-type pull down transistors; andapplying at least one of a voltage to a bit line (BL) that is electrically connected to source/drain regions of the first pass gate transistor, a voltage to a bit line complement (BLC) that is electrically connected to source/drain regions of the second pass gate transistor, a voltage to a word line (WL) that is electrically connected to gate structures of the first and the second pass gate transistors, a positive supply voltage to at least one of the at least two p-type pull up transistors and a negative supply voltage to at least one of the at least two n-type pull down transistors, and a voltage to the ...

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Номер записи: 14
03-01-2019 дата публикации

Memory system

Номер: US20190004706A1
Автор: Shinken Okamoto
Принадлежит: Toshiba Memory Corp

According to the embodiments, a memory system includes a nonvolatile semiconductor memory and a writing-loop-count monitoring unit that monitors a loop count of an applied voltage to the nonvolatile semiconductor memory required for data writing of the nonvolatile semiconductor memory as a writing loop count. Moreover, the memory system includes a management table for managing the writing loop count in block unit that is a unit of data erasing and a life managing unit that determines a degraded state of the nonvolatile semiconductor memory based on the management table.

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Номер записи: 15
07-01-2016 дата публикации

E-FUSE TEST DEVICE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

Номер: US20160005494A1
Автор: CHOI Hyun-min, PARK In-gyu, SONG Jung-Hak
Принадлежит:

An e-fuse test device is provided. The e-fuse test device may include a first transistor, and a fuse array connected to a source/drain terminal of the first transistor. The fuse array may include n fuse groups, each of the fuse groups may include one end, the other end, and m first fuse elements connected in series to each other between the one end and the other end, the one end of each of the fuse groups may be connected to each other, and the other end of each of the fuse groups may be connected to the source/drain terminal of the first transistor, and the n and m are natural numbers that are equal to or larger than two. 1. An e-fuse test device comprising:a first transistor including a first gate terminal configured to receive a first gate voltage, a first source/drain terminal, and a second source/drain terminal, wherein the e-fuse test device is configured to detect a current passing through the first transistor; anda fuse array including n sets of fuses, each set arranged between a first end line and a second end line,wherein each respective set of fuses of the n sets of fuses includes a first end, a second end, and m first fuse elements connected in series to each other between the first end and the second end,wherein the first ends of the respective sets of fuses of the n sets of fuses are connected to the first end line, and the second ends of the respective sets of fuses of the n sets of fuses are connected to the second end line and the first source/drain terminal of the first transistor,wherein the first end line is configured to receive a first source voltage, andwherein the n and m are natural numbers that are equal to or larger than 2.2. The e-fuse test device of claim 1 , wherein each respective set of fuses of the n sets of fuses comprises (m−1) connection terminals that connect the adjacent first fuse elements to each other claim 1 ,wherein the (m−1) connection terminals of each respective set of fuses of the n sets of fuses includes an 1-th ...

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Номер записи: 16
07-01-2016 дата публикации

REDUCING DISTURBANCES IN MEMORY CELLS

Номер: US20160005495A1
Автор: LASSER MENAHEM
Принадлежит:

Methods for reducing program disturb in non-volatile memories are described. In some embodiments, a non-volatile storage system may acquire a first set of intermediate data to be written to a plurality of memory cells, determine a current set of intermediate data written in the plurality of memory cells, determine whether to invert the first set of intermediate data based on the current set of intermediate data, invert the first set of intermediate data, and write the inverted first set of intermediate data to the plurality of memory cells. The memory cells that are already at the correct state may be skipped over and not programmed, thereby improving programming speed and reducing the cumulative voltage stress applied to unselected memory cells. 1. A method for operating a non-volatile storage system , comprising:acquiring a set of user-level data to be stored in a plurality of memory cells;determining a mapping between physical states of a memory cell and data values represented by the physical states based on a number of memory cells that will change state if the set of user-level data was stored in the plurality of memory cells according to the mapping; andstoring the set of user-level data in the plurality of memory cells according to the mapping.2. The method of claim 1 , wherein:the determining a mapping includes acquiring a first set of intermediate data derived from the set of user-level data and determining the number of memory cells that will change state if the first set of intermediate data was written to the plurality of memory cells.3. The method of claim 2 , wherein:the determining the number of memory cells that will change state if the first set of intermediate data was written to the plurality of memory cells includes reading a current set of intermediate data written in the plurality of memory cells and comparing the current set of intermediate data with the first set of intermediate data.4. The method of claim 2 , wherein:the storing the set of ...

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Номер записи: 17
04-01-2018 дата публикации

High Speed And Low Power Sense Amplifier

Номер: US20180005701A1
Автор: PI XIAO YAN, Qian Xiaozhou, Yue Kai Man, ZHOU Yao, Zhu Yaohua
Принадлежит:

An improved sensing circuit is disclosed that utilizes a bit line in an unused memory array to provide reference values to compare against selected cells in another memory array. A circuit that can perform a self-test for identifying bit lines with leakage currents about an acceptable threshold also is disclosed. 1. A system for detecting leakage current associated with a bit line in a memory system , comprisinga first circuit for generating a reference current;a second circuit that generates leakage current associated with the bit line;a first node coupled to the first circuit and second circuit;a second node that exhibits a constant voltage;a comparator that comprises the first node as an input and the second node as an input, wherein an output of the comparator indicates if the leakage current exceeds the reference current.2. The system of claim 1 , wherein the reference current is a level of acceptable leakage current for the bit line.3. The system of claim 1 , further comprising a controller.4. The system of claim 3 , wherein the controller is configured to store an identifier of the bit line.5. A method of detecting leakage current associated with a bit line in a memory system claim 3 , comprising:generating a reference current at a first node;generating a leakage current associated with the bit line at the first node;generating a constant voltage at a second node;comparing a voltage of the first node and a voltage of the second node and generating an output voltage that indicates if the leakage current exceeds the reference current.6. The method of claim 5 , wherein the reference current is a level of acceptable leakage current for the bit line.7. The method of claim 6 , further comprising:generating an identifier for the bit line.8. The method of claim 7 , further comprising:storing in a controller an identifier of the bit line.9. The method of claim 7 , further comprising:substituting a second bit line for the bit line during operation of the memory system. ...

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Номер записи: 18
04-01-2018 дата публикации

Logic Timing and Reliability Repair for Nanowire Circuits

Номер: US20180005707A1
Автор: Kawa Jamil, Moroz Victor
Принадлежит: Synopsys, Inc.

A method for improving an integrated circuit design having transistors with nanowire channels comprises identifying a particular device having a particular transistor with a nanowire channel; and adding to the integrated circuit design a controller which, when activated, repairs the particular transistor by self-heating. A critical path in logic circuitry in the design can be determined including a particular device having a transistor with a nanowire channel. A repair circuit can be added to the design connected to the particular device, the repair circuit when activated applying a self-heating stress to the particular device. The repair circuit can include a selection block selecting among a plurality of signals as an input signal to the particular device. The plurality of signals include a repair signal and an operational logic signal, the repair signal being such as to apply the self-heating stress to the nanowire channel of the particular device when activated. 1. A method for improving an integrated circuit design which has transistors with nanowire channels , comprising:identifying a particular device having a particular transistor with a nanowire channel; andadding to the integrated circuit design a controller which, when activated, repairs the particular transistor by self-heating.2. A method for improving an integrated circuit design including logic circuitry with devices having transistors with nanowire channels , comprising:determining a critical path in the logic circuitry, the critical path including a particular device having a transistor with a nanowire channel; andadding a repair circuit to the integrated circuit design connected to the particular device in the critical path, the repair circuit when activated applying a self-heating stress to the particular device in the critical path.3. The method of claim 2 , the repair circuit including a selection block selecting among a plurality of signals as an input signal to the particular device claim 2 , ...

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Номер записи: 19
04-01-2018 дата публикации

Enhancing Memory Yield and Performance Through Utilizing Nanowire Self-Heating

Номер: US20180005708A1
Автор: Kawa Jamil, Moroz Victor
Принадлежит: Synopsys, Inc.

A method for improving an integrated circuit design which has transistors with nanowire channels comprises identifying a particular device having a particular transistor with a nanowire channel; and adding to the integrated circuit design circuitry which, when activated, repairs the particular transistor by self-heating. The method can comprise determining a memory cell that has a read current below a passing criteria, the memory cell having a transistor with a nanowire channel on a current path through which the read current flows; and applying a stress on the memory cell to repair the nanowire channel of the transistor in the memory cell on the current path. The determining step can include sensing read currents of memory cells in an array of memory cells; and determining one or more memory cells in the array of memory cells having read currents below the passing criteria, using the read currents sensed. 1. A method for improving an integrated circuit design which has transistors with nanowire channels , comprising:identifying a particular device having a particular transistor with a nanowire channel; andadding to the integrated circuit design circuitry which, when activated, repairs the particular transistor by self-heating.2. A method for repairing memory cells having transistors with nanowire channels on an integrated circuit , comprising:determining a memory cell that has a read current below a passing criteria, the memory cell having a transistor with a nanowire channel on a current path through which the read current flows; andapplying a stress on the memory cell to repair the nanowire channel of the transistor in the memory cell on the current path.3. The method of claim 2 , wherein said determining comprises:sensing read currents of memory cells in an array of memory cells, the memory cells having transistors with nanowire channels on current paths through which the read currents flow; anddetermining one or more memory cells in the array of memory cells ...

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Номер записи: 20
02-01-2020 дата публикации

SEMICONDUCTOR MEMORY DEVICE, OPERATING METHOD THEREOF, AND MEMORY SYSTEM

Номер: US20200005886A1
Автор: LEE Jae Ho
Принадлежит:

A semiconductor memory device includes a switching controller, a voltage generator and control logic. The switching controller is connected to a local word line. The voltage generator, connected to the switching controller, is configured to generate an operating voltage according to an input clock signal and transfer the operating voltage to the switching controller. The control logic is configured to control operations of the voltage generator and the switching controller. The control logic is configured to detect an amount of leakage current of the local word line by counting a number of pulses of the input clock signal. 1. A semiconductor memory device comprising:a switching controller connected to a local word line;a voltage generator, connected to the switching controller, configured to generate an operating voltage according to an input clock signal and transfer the operating voltage to the switching controller; andcontrol logic configured to control operations of the voltage generator and the switching controller,wherein the control logic is configured to detect an amount of leakage current of the local word line by counting a number of pulses of the input clock signal.2. The semiconductor memory device of claim 1 , wherein the voltage generator includes:a charge pump configured to receive the input clock signal to generate an output voltage;a voltage comparator configured to generate an enable signal by comparing the output voltage of the charge pump with a reference voltage;a clock input driver configured to generate the input clock signal, applied to the charge pump, based on the enable signal;a voltage regulator configured to regulate the output voltage of the charge pump; anda reference current source connected to an output terminal of the voltage regulator.3. The semiconductor memory device of claim 2 ,wherein the voltage comparator is configured to receive the output voltage of the charge pump and the reference voltage, to output the enable signal when ...

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Номер записи: 21
03-01-2019 дата публикации

WORD LINE LEAKAGE DETECTION USING SOURCE AND SINK CURRENTS

Номер: US20190006019A1
Автор: Huynh Jonathan, Wang Sung-En
Принадлежит: SanDisk Technologies LLC

A leakage detection circuit is configured to generate a regulated voltage at a node and supply the regulated voltage to one or more word lines. The leakage detection circuit may adjust a source current used to regulate the voltage in response to leakage current sourced to the node. The leakage detection circuit may control an adjustable current sink connected to the node in order to maintain the source current within a target range. The leakage detection circuit may measure the amount of the leakage current by determining how much it had to adjust the leakage current amount to keep the source current within the target range. 1. A circuit comprising: 'generate a voltage supplied to a word line of a memory array via a voltage supply path; and', 'a voltage generation circuit configured to measure an amount of leakage current sourced to a node connected to the voltage supply path during supply of the voltage to the word line; and', 'control an adjustable current sink to sink, from the node, an amount of sink current corresponding to the measured amount of the leakage current in discrete steps; and', 'keep track of the adjustments to measure the amount of the leakage current., 'a measurement circuit configured to2. The circuit of claim 1 , wherein the voltage generation circuit is further configured to:supply a source current to the node; andregulate the voltage through adjustment of the level of the source current.3. The circuit of claim 1 , wherein the measurement circuit is configured to:control the adjustable current sink to maintain a level of the source current in a target current range; anddetermine how much the adjustable current sink adjusted the sink current to keep the source current in the target current range in order to measure the amount of leakage current.4. The circuit of claim 1 , further comprising: sense an amount of the leakage current; and', 'generate at least one sense current indicative of the amount of the leakage current,, 'a sense circuit ...

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Номер записи: 22
03-01-2019 дата публикации

APPARATUS FOR MEMORY DEVICE TESTING AND FIELD APPLICATIONS

Номер: US20190006022A1
Автор: NIU Baohua, YING Ji-Feng
Принадлежит: Taiwan Semiconductor Manufacturing Co, Ltd.

A memory test system is disclosed that includes a memory integrated circuit (IC) and a memory functional tester. The memory IC includes a plurality of memory banks, where each memory bank includes a plurality of memory cells. The memory functional tester includes an adjustable voltage generator circuit, a read current measurement circuit, and a controller. The memory functional tester performs a write/read functional test on the memory bank over a number of write control voltages to determine a preferred write control voltage, where the preferred write control voltage is designated for use during subsequent write operations to the memory bank during an operational mode. 1. A memory functional tester to perform a write/read functional test on a plurality of memory cells , the memory functional tester , comprising:an adjustable voltage generator circuit configured to generate each write control voltage of a plurality of write control voltages to store first and second logic states in the plurality of memory cells during respective first and second write cycles of the write/read functional test; 'measure first and second sets of read currents that define first and second sets of read current distributions associated with the each write control voltage of the plurality of write control voltages, wherein the first read current distribution represents the first logic state stored in the plurality of memory cells during the first write cycle, and the second read current distribution represents the second logic state stored in the plurality of memory cells during the second write cycle;', 'a read current measurement circuit configured to determine a number error currents that fall outside the first and second read current distributions associated with the each write control voltage of the plurality of write control voltages;', 'determine an error rate associated with the each write control voltage based on the corresponding number of error currents associated with the each ...

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Номер записи: 23
27-01-2022 дата публикации

Retention Voltage Management for a Volatile Memory

Номер: US20220028479A1
Автор: Abu-Rahma Mohamed H., Barn Amrinder S., Nazar Shahzad
Принадлежит:

An apparatus includes a memory circuit that includes a plurality of sub-arrays. The memory circuit is configured to implement a retention mode according to test information indicating voltage sensitivities for the plurality of sub-arrays. The apparatus also includes a voltage control circuit coupled to a power supply node. The voltage control circuit is configured, in response to activation of the retention mode for the plurality of sub-arrays, to generate, based on the test information, at least two different retention voltage levels for different ones of the plurality of sub-arrays. The at least two different retention voltage levels are lower than a power supply voltage level of the power supply node. 120-. (canceled)21. An apparatus , comprising:a memory circuit including a plurality of sub-arrays, wherein the memory circuit is configured to implement a retention mode according to stored information indicating voltage sensitivities for the plurality of sub-arrays; and generate, based on the stored information, a first retention voltage level for a first subset of the plurality of sub-arrays; and', 'generate, based on the stored information, a second retention voltage level, higher than the first retention voltage level, for a second subset of the plurality of sub-arrays; and', 'wherein the first and second retention voltage levels are lower than a power supply voltage level of the power supply node, and wherein the second subset includes one or more voltage sensitive data storage cells that fail to retain data at the first retention voltage level., 'a voltage control circuit coupled to a power supply node, wherein during the retention mode for the plurality of sub-arrays, the voltage control circuit is configured to22. The apparatus of claim 21 , wherein the stored information includes test information generated from a test procedure that indicates that one or more voltage sensitive data storage cells are included in the second subset of the plurality of sub- ...

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Номер записи: 24
14-01-2016 дата публикации

MEMORY CONTROLLER, STORAGE DEVICE AND MEMORY CONTROL METHOD

Номер: US20160011970A1
Автор: SAKURADA Kenji
Принадлежит: KABUSHIKI KAISHA TOSHIBA

According to one embodiment, a memory controller controlling a nonvolatile memory which stores a code word includes a read control unit which controls reading from the nonvolatile memory and a decoding unit which obtains likelihood information of each memory cells based on a reading result from the nonvolatile memory and decodes the code word by using the likelihood information, wherein the decoding unit obtains the likelihood information of a first memory cell based on the reading result of the first memory cell and the reading results of second memory cells which are one or more of the memory cells adjacent to the first memory cell. 1. A memory controller controlling a nonvolatile memory configured to include a plurality of bit lines , a plurality of word lines , and a plurality of memory cells to store a code word , each of the plurality of memory cells connected to the bit line and the word line , comprising:a read control unit configured to control the nonvolatile memory to perform reading; anda decoding unit configured to obtain likelihood information of each of the plurality of memory cells based on a reading result output from the nonvolatile memory and decodes the code word by using the likelihood information corresponding to the code word,wherein the decoding unit obtains the likelihood information of a first memory cell which is one of the plurality of memory cells based on the reading result of the first memory cell and the reading results of second memory cells which are one or more of the plurality of memory cells adjacent to the first memory cell.2. The memory controller according to claim 1 ,wherein the likelihood information is defined as an LLR, andwherein the decoding unit retains a first LLR table and a second LLR table representing correspondence between the reading results from the memory cells and LLRs, and in the second LLR table, the LLRs are set so that influence of interference from the adjacent memory cells are canceled, andwherein the ...

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Номер записи: 25
14-01-2016 дата публикации

MEMORY COMPRISING A CIRCUIT FOR DETECTING A GLITCH ON A LINE OF THE MEMORY

Номер: US20160012919A1
Автор: BOUZEKRI ALAMI Salwa
Принадлежит: INSIDE SECURE

A memory including at least one line to which memory cells are coupled. A control circuit is configured to emit an end-of-operation signal at the end of the execution of an operation on at least one memory cell, and a glitch detection circuit coupled to the memory line is configured to supply a glitch detection signal when a falling edge of the amplitude of a voltage signal appears on the memory line in the absence of the end-of-operation signal. 1. A memory comprising:a control circuit for executing operations on memory cells, andat least one line to which memory cells are coupled,wherein the control circuit is configured to emit an end-of-operation signal at the end of the execution of an operation on at least one memory cell,and in that it comprises at least one glitch detection circuit coupled to the memory line and configured to supply a glitch detection signal when a falling edge of the amplitude of a voltage signal appears on the memory line in the absence of the end-of-operation signal.2. Memory according to claim 1 , wherein the control circuit is configured to:during the execution of the operation on the memory cell, apply a voltage signal on the memory line,once the operation is over, emit the end-of-operation signal before ceasing to apply the voltage signal to the memory line, then cease to emit the end-of-operation signal after ceasing to apply the voltage signal to the memory line.3. Memory according to claim 1 , wherein the control circuit is configured to claim 1 , once the operation is over claim 1 , emit the end-of-operation signal for less than 20 nanoseconds.4. Memory according to claim 1 , wherein the glitch detection circuit comprises:detection means configured to transform a voltage signal present on the memory line into a logic signal having a first logic value when the amplitude of the voltage signal is below a threshold and a second logic value when the amplitude of the voltage signal is above the threshold,storing means for storing a ...

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Номер записи: 26
14-01-2021 дата публикации

SELF-ADAPTIVE READ VOLTAGE ADJUSTMENT USING DIRECTIONAL ERROR STATISTICS FOR MEMORIES WITH TIME-VARYING ERROR RATES

Номер: US20210012856A1
Автор: Chen Zhengang, Xie Tingjun
Принадлежит:

A processing device in a memory system identifies a first range of a plurality of write-to-read delay ranges for the memory component, wherein the first range represents a plurality of write-to-read delay times and has an associated read voltage level used to perform a read operation on a segment of the memory component having a write-to-read delay time that falls within the first range. The processing device further identifies a first set of the plurality of write-to-read delay times at a first end of the first range and determines a first directional error rate for the memory component corresponding to the first set of the plurality of write-to-read delay times and a second directional error rate for the memory component corresponding to the first set of the plurality of write-to-read delay times. The processing device determines whether a correspondence between the first directional error rate and the second directional error rate satisfies a first threshold criterion and, responsive to the correspondence between the first directional error rate and the second directional error rate not satisfying the first threshold criterion, modifies the read voltage level associated with the first range. 1. A system comprising:a memory component; and identify a first range of a plurality of write-to-read delay ranges for the memory component, wherein the first range represents a plurality of write-to-read delay times and has an associated read voltage level used to perform a read operation on a segment of the memory component having a write-to-read delay time that falls within the first range;', 'identify a first set of the plurality of write-to-read delay times at a first end of the first range;', 'determine a first directional error rate for the memory component corresponding to the first set of the plurality of write-to-read delay times and a second directional error rate for the memory component corresponding to the first set of the plurality of write-to-read delay times ...

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Номер записи: 27
14-01-2021 дата публикации

Self-adaptive read voltage adjustment using boundary error statistics for memories with time-varying error rates

Номер: US20210012857A1
Автор: Tingjun Xie, Zhengang Chen
Принадлежит: Micron Technology Inc

A processing device in a memory system identifies a first range of a plurality of write-to-read delay ranges for the memory component, wherein the first range represents a plurality of write-to-read delay times and has an associated read voltage level used to perform a read operation on a segment of the memory component having a write-to-read delay time that falls within the first range. The processing device further identifies a first set of the plurality of write-to-read delay times at a first end of the first range and a second set of the plurality of write-to-read delay times at a second end of the first range, and determines a first error rate for the memory component corresponding to the first set of the plurality of write-to-read delay times and a second error rate for the memory component corresponding to the second set of the plurality of write-to-read delay times. The processing device determines whether a correspondence between the first error rate and the second error rate satisfies a first threshold criterion, and, responsive to the correspondence between the first error rate and the second error rate not satisfying the first threshold criterion, modifies the read voltage level associated with the first range.

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Номер записи: 28
09-01-2020 дата публикации

ARRAY PLATE SHORT REPAIR

Номер: US20200013478A1
Автор: Fackenthal Richard E., Lovett Simon J.
Принадлежит:

Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. Groups of cells may be operated in different ways depending, for example, on a relationship between cell plates of the group of cells, pages of cells, and/or sections of cells. Cells may be selected in pairs or in larger multiples in order to accommodate an electric current relationship (such as a short) between two or more cells within a group, a page, and/or a section. When performing an access based on a smaller page size, a larger page size of cells may be selected to accommodate a short between plates within the smaller page, the larger page, and/or a section of memory that includes the smaller page or the larger page. 1. (canceled)2. A method , comprising:identifying a first page of memory cells based at least in part on an access command;identifying that there is a defect associated with at least one memory cell of a second page of memory cells, the second page of memory cells that includes the first page of memory cells; andactivating the second page of memory cells based at least in part on the defect associated with the at least one memory cell.3. The method of claim 2 , wherein identifying that there is the defect comprises:identifying that a first plate associated with the at least one memory cell of the second page is shorted with a second plate associated with at least a second memory cell of the second page.4. The method of claim 3 , wherein the at least one memory cell is included in the first page and the at least the second memory cell is not included in the first page.5. The method of claim 3 , wherein the at least one memory cell is not included in the first page and the at least the second memory cell is not included in the first page.6. The method of claim 2 , further comprising:activating, based at least in part on the defect, a first access line associated with the first page of memory cells and a second access line associated with a ...

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Номер записи: 29
21-01-2016 дата публикации

LEAKAGE CURRENT DETECTION DEVICE AND NONVOLATILE MEMORY DEVICE HAVING THE SAME

Номер: US20160018453A1
Автор: JEON Byung-gil, KIM DOO-GON
Принадлежит:

A leakage current detection device includes a test detection circuit, a reference detection circuit, a comparator, and a latch circuit. The test detection circuit is coupled between a test node and a test line, provides a voltage to the test node to charge the test line, floats the test node and the test line, and decreases a voltage of the test node based on leakage current of the test line. The reference detection circuit is coupled between a reference node and a reference line, provides the voltage to the reference node to charge the reference line, floats the reference node and the reference line, and decreases a voltage of the reference node based on self-discharge of the reference line. The comparator outputs a comparison signal by comparing voltages of the test node and the reference node. The latch circuit latches the comparison signal to output a test result signal.

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Номер записи: 30
03-02-2022 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20220036961A1
Автор: ISHII Yuichiro, Tanaka Shinji, YABUUCHI Makoto
Принадлежит:

A semiconductor device including an SRAM capable of sensing a defective memory cell that does not satisfy desired characteristics is provided. The semiconductor device includes a memory cell, a bit line pair being coupled to the memory cell and having a voltage changed towards a power-supply voltage and a ground voltage in accordance with data of the memory cell in a read mode, and a specifying circuit for specifying a bit line out of the bit line pair. In the semiconductor device, a wiring capacitance is coupled to the bit line specified by the specifying circuit and a voltage of the specified bit line is set to a voltage between a power voltage and a ground voltage in a test mode. 1. A semiconductor device comprising:a memory cell;a bit line pair on which a voltage is changed towards a first voltage and a second voltage that is different from the first voltage in a read mode in accordance with data of the memory cell, the bit lines being coupled to the memory cell; anda specifying circuit for specifying a bit line out of the bit line pair,wherein a capacitative element is coupled to the bit line specified by the specifying circuit and a voltage of the specified bit line is set to a voltage between the first voltage and the second voltage in a test mode.2. The semiconductor chip according to claim 1 ,wherein the capacitative element has a wiring capacitance that is determined depending on a length of the bit line pair.3. The semiconductor device according to claim 2 , further comprisinga write circuit for supplying a potential in accordance with data to be written to the bit line pair in a write mode,wherein the write circuit includes a specifying circuit and supplies a third voltage that is different from the first voltage and the second voltage to the bit line specified by the specifying circuit in the write mode.4. The semiconductor device according to claim 3 ,wherein the specifying circuit specifies a bit line out of the bit line pair in accordance with the ...

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Номер записи: 31
21-01-2021 дата публикации

CHIP TESTING METHOD

Номер: US20210018558A1
Автор: ROSENTHAL GENE, TSAI CHEN-LUNG
Принадлежит:

A chip testing method for being implemented by a chip testing system includes: a chip mounting step implemented by using a chip mounting apparatus to respectively dispose a plurality of chips onto electrical connection sockets of a chip testing device; a moving-in step implemented by transferring the chip testing device carrying the chips into one of accommodating chambers of an environment control apparatus; a temperature adjusting step implemented by controlling a temperature adjusting device of the one of the accommodating chambers so that the chips are in an environment having a predetermined temperature; and a testing step implemented by providing electricity to the chip testing device, so that each testing module of the chip testing device performs a predetermined testing process on the chips on the corresponding electrical connection sockets connected thereto. 1. A chip testing method for being implemented by a chip testing system that includes a chip mounting apparatus , at least one chip testing device , at least one environment control apparatus , and a classification apparatus , wherein the at least one chip testing device includes a circuit board , a plurality of electrical connection sockets disposed on the circuit board , a plurality of testing modules disposed on the circuit board and connected to the electrical connection sockets , and at least one power supply member connected to the circuit board , wherein each of the electrical connection socket is configured to carry a chip , and the at least one power supply member is configured to convert electricity provided from an external power supply apparatus to the testing modules , and wherein the at least one environment control apparatus includes a plurality of accommodating chambers each receiving a temperature adjusting device , the chip testing method comprising:a chip mounting step implemented by using the chip mounting apparatus to respectively dispose a plurality of chips onto the electrical ...

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Номер записи: 32
17-01-2019 дата публикации

DEVICE AND METHOD FOR DATA-WRITING

Номер: US20190019541A1
Автор: LEE Po-Hao, Shih Yi-Chun
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A device includes a circuit cell, a voltage regulator, a first switching unit, a second switching unit, and a third switching unit. The voltage regulator is configured to output a write voltage. The first switching unit is configured to generate, in response to a control voltage, a current represented by an auxiliary signal. The second switching unit is configured to receive the auxiliary signal, and to turn on to transmit the auxiliary signal to the circuit cell. The third switching unit is configured to receive the write voltage, and to turn on to transmit the write voltage to the circuit cell. 1. A device , comprising:a circuit cell;a voltage regulator configured to output a write voltage;a first switching unit configured to generate, in response to a control voltage, a current represented by an auxiliary signal;a second switching unit configured to receive the auxiliary signal, and to turn on to transmit the auxiliary signal to the circuit cell; anda third switching unit configured to receive the write voltage, and to turn on to transmit the write voltage to the circuit cell.2. The device of claim 1 , wherein the second switching unit is configured to turn on in response to a first select signal of a plurality of select signals claim 1 , and the third switching unit is configured to turn on in response to a second select signal of the plurality of select signals.3. The device of claim 2 , wherein the second switching unit and the third switching unit are connected in parallel.4. The device of claim 2 , wherein the second switching unit and the third switching unit are connected in series claim 2 , and the third switching unit is coupled between the second switching unit and the circuit cell.5. The device of claim 1 , further comprising:a feedback circuit configured to generate the control voltage according to a reference voltage and a reference current.6. The device of claim 5 , wherein the feedback circuit comprises:an amplifier configured to generate the ...

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Номер записи: 33
22-01-2015 дата публикации

APPARATUSES AND METHODS FOR SENSING FUSE STATES

Номер: US20150023088A1
Автор: Sforzin Marco
Принадлежит:

Apparatuses and methods for sensing fuse states are disclosed herein. An apparatus may include an array having a plurality of sense lines. A plurality of cells may be coupled to a sense line of the plurality of sense lines. A fuse sense circuit may coupled to the sense line of the plurality of sense lines and configured to receive a sense voltage from a cell of the plurality of cells. The sense voltage may be based, at least in part, on a state of a fuse corresponding to the cell of the plurality of cells. The fuse sense circuit may further be configured to compare the sense voltage to a reference voltage to provide a fuse state control signal indicative of the state of the fuse. 1. An apparatus , comprising:a fuse sense circuit coupled to a sense line and configured to receive a sense voltage from a cell associated with the sense line, the sense voltage based on a state of a fuse corresponding to the cell,wherein the fuse sense circuit is further configured to determine whether the sense voltage exceeds a reference voltage using a plurality of unblown fuses.2. The apparatus of claim 1 , wherein the fuse sense circuit is configured to receive the sense voltage associated with the sense line responsive to a switch of a memory cell being enabled claim 1 , the memory cell coupled to the sense line.3. The apparatus of claim 1 , wherein the plurality of unblown fuses includes a first unblown fuse coupled in parallel with a second unblown fuse and coupled in series with a third unblown fuse.4. The apparatus of claim 1 , wherein the fuse sense circuit includes a voltage divider including a plurality of resistive elements.5. The apparatus of claim 4 , wherein a first resistive element of the plurality of resistive elements includes a first plurality of resistive devices and wherein a second resistive element of the plurality of resistive elements includes a second plurality of resistive devices.6. The apparatus of claim 1 , wherein the fuse sense circuit comprises a ...

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Номер записи: 34
21-01-2021 дата публикации

Memory structure for self-erasing secret storage

Номер: US20210020775A1
Автор: Elad Peer, Elena Sidorov, Rami Sudai, Reuven Elbaum, Steve J. Brown, Uri Bear
Принадлежит: Intel Corp

In one embodiment, memory cell includes a control gate, a floating gate, a substrate comprising a source region and a drain region, a first isolator between the control gate and floating gate, and a second isolator between the floating gate and the substrate. The memory cell is configured to have a retention time that is within a statistical window around a selected lifespan. The selected lifespan may be less than ten years, such as, for example, less than one year, less than one month, or less than one week.

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Номер записи: 35
10-02-2022 дата публикации

Determine Optimized Read Voltage via Identification of Distribution Shape of Signal and Noise Characteristics

Номер: US20220044736A1
Автор: Alhussien AbdelHakim S., Fitzpatrick James, Khayat Patrick Robert, Parthasarathy Sivagnanam
Принадлежит:

A memory device to determine a voltage optimized to read a group of memory cells. In response to a command, the memory device reads the group of memory cells at a plurality of test voltages to determine a set of signal and noise characteristics of the group of memory cells. The memory device determines or recognizes a shape of a distribution of the signal and noise characteristics over the plurality of test voltages. Based on the shape, the memory device selects an operation in determining an optimized read voltage of the group of memory cells. 1. A memory device , comprising:an integrated circuit package enclosing the memory device; anda plurality of groups of memory cells formed on at least one integrated circuit die; determine a set of signal and noise characteristics of the group of memory cells from a result of reading the group of memory cells at the plurality of test voltages;', 'recognize a shape of a distribution of the signal and noise characteristics over the plurality of test voltages;', 'select, based on the shape, an operation to determine an optimized read voltage of the group of memory cells; and', 'perform the operation in determination of the optimized read voltage., 'wherein in response to a command identifying a group of memory cells within the plurality of groups, the memory device is configured to, read the group of memory cells at a plurality of test voltages;'}2. The memory device of claim 1 , wherein the set of signal and noise characteristics identifies a distribution of count difference over the plurality of test voltages according to bit counts on the test voltages respectively; wherein each respective bit count at a test voltage identifies a number of memory cells in the group that claim 1 , when read at the test voltage claim 1 , provide a predetermined bit value; and wherein each respective count difference between two adjacent test voltages represents a difference between bit counts at the adjacent test voltages respectively.3. The ...

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Номер записи: 36
10-02-2022 дата публикации

Iterative Read Calibration Enhanced according to Patterns of Shifts in Read Voltages

Номер: US20220044739A1
Автор: Alhussien AbdelHakim S., Fitzpatrick James, Khayat Patrick Robert, Parthasarathy Sivagnanam
Принадлежит:

A memory sub-system configured to use first values of a plurality of optimized read voltages to perform a first read calibration, which determines second values of the plurality of optimized read voltages. A plurality of shifts, from the first values to the second values respectively, can be computed for the plurality of optimized read voltages respectively. After recognizing a pattern in the plurality of shifts that are computed for the plurality of voltages respectively, the memory sub-system can control and/or initiate a second read calibration based on the recognized pattern in the shifts. 1. A device , comprising:a plurality of memory cells programmable to have threshold voltages in a plurality of voltage regions to represent data stored in the plurality of memory cells;a calibration circuit configured to apply a test voltage to the plurality of memory cells and detect whether each memory cell, among the plurality of memory cells, has a threshold voltage below the test voltage; and determine, based on first test voltages applied in a first voltage region among the plurality of voltage regions, a first shift of a threshold voltage of the plurality of memory cells in the first voltage region;', 'predict, based on the first shift, a second shift of a threshold voltage of the plurality of memory cells in a second voltage region among the plurality of voltage regions; and', 'instruct, based on the second shift, the calibration circuit to apply second test voltages in the second voltage region., 'a logic circuit configured to2. The device of claim 1 , wherein the logic circuit is further configured to:determine, based on test voltages applied to the plurality of memory cells, a plurality of shifts of threshold voltages within a portion of the plurality of voltage regions, the plurality of shifts including the first shift; andidentify a pattern in the plurality of shifts, wherein the second shift is predicted based on the pattern.3. The device of claim 2 , wherein the ...

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Номер записи: 37
10-02-2022 дата публикации

MEMORY SYSTEM INCLUDING A NONVOLATILE MEMORY DEVICE, AND AN ERASING METHOD THEREOF

Номер: US20220044758A1
Автор: JUNG Wontaeck, NAM Buil, SON Myoungho
Принадлежит:

A fail detecting method of a memory system including a nonvolatile memory device and a memory controller, the fail detecting method including: counting, by the memory controller, the number of erases of a word line connected to a pass transistor; issuing a first erase command, by the memory controller, when the number of erases reaches a reference value; applying a first voltage, by the nonvolatile memory device, in response to the first erase command, that causes a gate-source potential difference of the pass transistor to have a first value; detecting, by the memory controller, a leakage current in a word line, after the applying of the first voltage; and determining, by the memory controller, the word line as a fail when a leakage voltage caused by the leakage current is greater than a first threshold value. 1. A fail detecting method of a memory system comprising a nonvolatile memory device and a memory controller , the fail detecting method comprising:counting, by the memory controller, the number of erases of a word line connected to a pass transistor;issuing a first erase command, by the memory controller, when the number of erases reaches a reference value;applying a first voltage, by the nonvolatile memory device, in response to the first erase command, that causes a gate-source potential difference of the pass transistor to have a first value;detecting, by the memory controller, a leakage current in a word line, after the applying of the first voltage; anddetermining, by the memory controller, the word line as a fail when a leakage voltage caused by the leakage current is greater than a first threshold value.2. The fail detecting method of claim 1 , wherein the applying of the first voltage comprises increasing a source terminal voltage of the pass transistor.3. The fail detecting method of claim 1 , wherein the applying of the first voltage comprises decreasing a gate terminal voltage of the pass transistor.4. The fail detecting method of claim 1 , ...

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Номер записи: 38
10-02-2022 дата публикации

IMPRINT MANAGEMENT FOR MEMORY

Номер: US20220044759A1
Автор: Bangalore Lakshman Shashank, Basuta Sukneet Singh, Harms Jonathan D., Strand Jonathan J.
Принадлежит:

Methods, systems, and devices for imprint recovery management for memory systems are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting. 1. (canceled)2. A method , comprising:writing a first set of logic states to a subset of memory cells of a memory array;reading, using a first reference voltage, the subset of memory cells to obtain a second set of logic states that are based at least in part on the first set of logic states;reading, using a second reference voltage, the subset of memory cells to obtain a third set of logic states that are based at least in part on the first set of logic states;determining a first quantity of errors associated with the second set of logic states and a second quantity of errors associated with the third set of logic states; andperforming a recovery operation on the memory array based at least in part on a difference between the first quantity of errors and the second quantity of errors.3. The method of claim 2 , further comprising:calculating a gradient based at least in part on the first quantity of errors and the second quantity of errors; andcomparing the calculated gradient to an expected gradient, wherein performing the recovery operation is based at least in ...

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Номер записи: 39
23-01-2020 дата публикации

TESTING METHOD FOR SEMICONDUCTOR MEMORY

Номер: US20200027523A1
Автор: OKADA Toshiharu
Принадлежит: LAPIS SEMICONDUCTOR CO., LTD.

A testing method for a semiconductor memory includes determining which memory blocks are defective based on the number of defective cells in the block. The method includes determining whether the number of defective blocks exceeds a first threshold value and judging the semiconductor memory to be defective if the number of defective blocks is equal to or greater than the first threshold value. The method also includes comparing the number of defective blocks with a second threshold value equal to or less than the first threshold value and repeating the process of measuring and judging of the memory cells and memory blocks until the number of defective blocks is at least equal to the second threshold value, and then managing access to the defective blocks in a different manner from accesses to other blocks. 1. A testing method for semiconductor memory having a plurality of memory blocks that each includes a plurality of memory cells , the method comprising:measuring an electrical characteristic of each of the plurality of memory cells of the plurality of memory blocks;identifying a defective cell among the plurality of memory cells by determining whether a measured value of the electrical characteristic of a memory cell satisfies a standard value, and determining that the memory cell is the defective cell based on determining that the measured value of the electrical characteristic of the memory cell does not satisfy the standard value;judging a memory block among the plurality of memory blocks to be a defective block if the memory block includes at least a prescribed number of defective cells;determining whether a number of defective blocks exceeds a first threshold value;recognizing the semiconductor memory as defective if the number of defective blocks exceeds the first threshold value;comparing the number of defective blocks with a second threshold value that equal to or less than the first threshold value;based on determining that the number of defective blocks ...

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Номер записи: 40
28-01-2021 дата публикации

Memory device test circuit and memory device test method

Номер: US20210027854A1
Автор: Sheng-Lin Lin, Shih-Chieh Lin
Принадлежит: Realtek Semiconductor Corp

A memory device test circuit and a memory device test method are provided. The memory device test circuit is configured to test a memory device and includes a storage circuit, a comparison circuit and a control circuit. The storage circuit stores a test data. The comparison circuit is coupled to the storage circuit. The control circuit is coupled to the storage circuit, the comparison circuit, and the memory device and performs the following steps to test the memory device: writing the test data to the memory device; controlling the memory device to enter a power mode; controlling the memory device to enter a function mode; and controlling the comparison circuit to compare an output data of the memory device with the test data.

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Номер записи: 41
04-02-2016 дата публикации

OPERATIONAL VIBRATION COMPENSATION THROUGH MEDIA CACHE MANAGEMENT

Номер: US20160034342A1
Автор: Feldman Timothy Richard, Liu Xiong, Moller Gregory Paul, Toh Michael JC, Wiggins Paul Michael, XIE WENXIANG
Принадлежит:

Apparatus and method for managing a media cache through the monitoring of operational vibration of a data storage device. In some embodiments, a non-volatile media cache of the data storage device is partitioned into at least first and second zones having different data recording characteristics. Input data are received for storage in a non-volatile main memory of the data storage device. An amount of operational vibration associated with the data storage device is measured. The input data are stored in a selected one of the first or second zones of the media cache prior to transfer to the main memory responsive to a comparison of the measured amount of operational vibration to a predetermined operational vibration threshold. 1. A method comprising:partitioning a non-volatile media cache of a data storage device into at least first and second zones having different data recording characteristics;receiving input data to be stored in a non-volatile main memory of the data storage device;measuring an amount of operational vibration associated with the data storage device; andstoring the input data in a selected one of the first or second zones of the media cache prior to transfer to the main memory responsive to a comparison of the measured amount of operational vibration to a predetermined operational vibration threshold.2. The method of claim 1 , wherein the first zone is configured to have a lower susceptibility to operational vibration and the second zone is configured to have a higher susceptibility to operational vibration.3. The method of claim 2 , wherein the data are stored in the first zone responsive to the measured amount of operational vibration falling below the predetermined operational vibration threshold claim 2 , and wherein the data are stored in the second zone responsive to the measured amount of operational vibration exceeding the predetermined operational threshold.4. The method of claim 1 , wherein the first zone is formed from a rotatable data ...

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Номер записи: 42
01-02-2018 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME

Номер: US20180033494A1
Автор: Kim Tae Hoon
Принадлежит:

A semiconductor memory device includes memory cells coupled to a word line; and a peripheral circuit configured to read first to kth page data from the memory cells by sequentially applying first to kth test voltages to the word line, where k is a natural number greater than 3, wherein the peripheral circuit is configured to gradually reduce times during which the first to kth test voltages are applied to the word line. 1. A method of operating a semiconductor memory device , the method comprising:reading first to kth page data from memory cells coupled to a word line by sequentially applying first to kth test voltages to the word line,wherein a read voltage applied to the word line during a read operation is determined by comparing a number of data bits changed between (k−2)th page data and (k−1)th page data with a number of data bits changed between the (k−1)th page data and the kth page data, andtimes during which data sensed by the first to kth test voltages are evaluated are gradually reduced.2. The method of claim 1 , where the times during which the data sensed by the first to kth test voltages are evaluated are times during which data transferred to latches of page buffers through bit lines coupled to the memory cells are determined.3. The method of claim 1 , wherein times during which the first to kth test voltages are applied are gradually reduced.4. The method of claim 3 , wherein the first to kth test voltages are gradually increased.5. The method of claim 3 , further comprising precharging bit lines coupled to the memory cells once before applying the first to kth test voltages to the word line. This application is a division of the U.S. patent application Ser. No. 15/211,779 filed on Jul. 15, 2016, titled “SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME”, which is a Continuation in Part of U.S. patent application Ser. No. 14/292,299 filed on May 30, 2014, and now U.S. Pat. No. 9,406,402 issued on Aug. 2, 2016, which claims priority to ...

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Номер записи: 43
17-02-2022 дата публикации

PROGRAM AND OPERATING METHODS OF NONVOLATILE MEMORY DEVICE

Номер: US20220051747A1
Автор: KIM Boh-Chang
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A program method of a nonvolatile memory device including a plurality of memory cells, each storing at least two bits of data, includes performing a first program operation based on a plurality of program voltages having a first pulse width to program first page data into selected memory cells connected to a selected word line among the plurality of memory cells; and performing a second program operation based on a plurality of program voltages having a second pulse width different from the first pulse width to program second page data into the selected memory cells in which the first page data is programmed. 1. A method comprising:receiving a first program command to write first data to a memory device;programming the first data in a plurality of memory cells in the memory device using a first voltage level available in the plurality of memory cells;receiving a second program command to write second data to the memory device; andprogramming the second data in the plurality of memory cells programmed with the first data, using a second voltage level available in the plurality of memory cells,wherein each of the plurality of memory cells is programmed with two bits of data from the first data, and each of the plurality of memory cells is programmed with two bits of data from the second data, andthe second voltage level is different from the first voltage level.2. The method of claim 1 , further comprising writing a flag bit indicating completion of a first program operation into the plurality of memory cells.3. The method of claim 1 , wherein a threshold voltage associated with the first voltage level is less than a threshold voltage associated with the second voltage level.4. The method of claim 1 , wherein the memory device is a three-dimensional (3D) NAND flash memory device.5. The method of claim 1 , wherein the first voltage level has a first pulse width claim 1 , and the second voltage level has a second pulse width that is different from the first pulse width. ...

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Номер записи: 44
12-02-2015 дата публикации

Addressable test circuit and test method for key parameters of transistors

Номер: US20150042372A1
Автор: Weiwei Pan, Yongjun Zheng
Принадлежит: Semitronix Corp

Methods of testing key parameters of transistors can be achieved using an addressable test circuit. Saturation current and leakage current of transistor are measured through different test signal lines. The addressable test circuit can be applied to a plurality of MOS transistors, each MOS transistor has a gate end G, a drain end D, a source end S, and a substrate B, wherein the S end and D end of each MOS transistor are respectively connected to different test signal lines. The test circuit can have a high area utilization rate such that it has the capacity to put a lot of transistors within one small wafer area. In addition, each transistor's I dsat , I off can be measured accurately.

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Номер записи: 45
08-02-2018 дата публикации

METHOD AND APPARATUS FOR REAL-TIME BLANK PAGE DETECTION IN DATA TRANSMISSION

Номер: US20180039432A9
Автор: FAN CHONGBIN, Wang Yong, Xie Jun
Принадлежит:

A device for reading data from a first memory to a second memory based on real-time blank page detection includes a memory controller for reading a page of data from the first memory, a buffer for buffering a portion of the page data, a blank page pre-detection unit for generating a pre-detection result that indicates whether the page is a blank page based on a pre-determined part of the page data, a data processing unit for processing all of the page data to identify a page type, and a control unit for signaling the memory controller to read the page of data from the first memory and enabling the data processing unit based on the pre-detection result. 1. A device for reading data from a first memory to a second memory , the device comprising:a memory controller for reading at least one page of data from the first memory;a buffer connected to the memory controller for buffering a portion of the at least one page of data read from the first memory;a blank page pre-detection unit, connected to the buffer, for generating a pre-detection result that indicates whether the at least one page is a blank page based on a pre-determined part of the data in the at least one page;a data processing unit, connected to the buffer and the blank page pre-detection unit, for processing all of the data in the at least one page to identify a type of the page; anda control unit, connected to the memory controller, the blank page pre-detection unit, and the data processing unit, for signaling the memory controller to read the at least one page of data from the first memory and enabling the data processing unit based on the pre-detection result.2. The device of claim 1 , wherein the pre-determined part is a metadata block of the at least one page claim 1 , wherein the metadata block includes an occupied part for storing information of the at least one page claim 1 , and a non-occupied part.3. The device of claim 2 , wherein the blank page pre-detection unit generates the pre-detection ...

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Номер записи: 46
18-02-2016 дата публикации

THRESHOLD VOLTAGE EXPANSION

Номер: US20160049209A1
Автор: Belgal Hanmant P., Damle Prashant S., KRIPANIDHI Arjun, LY-GAGNON Dany-Sebastien, PANDEY Abhinav, Pangal Kiran, Rangan Sanjay, URIBE Sebastian T.
Принадлежит:

Embodiments including systems, methods, and apparatuses associated with expanding a threshold voltage window of memory cells are described herein. Specifically, in some embodiments memory cells may be configured to store data by being set to a set state or a reset state. In some embodiments, a dummy-read process may be performed on memory cells in the set state prior to a read process. In some embodiments, a modified reset algorithm may be performed on memory cells in the reset state. Other embodiments may be described or claimed. 1. An apparatus comprising:a plurality of memory cells, wherein individual memory cells of the plurality of memory cells are configured to store one or more bits of data; identify, based on a current detected in response to application of a read voltage, a state of a bit of data in a memory cell of the individual memory cells; and', 'apply, prior to the application of the read voltage, a dummy-read voltage to the memory cell., 'a bias logic coupled with the individual memory cells, the bias logic to2. The apparatus of claim 1 , wherein the individual memory cells are in a set state or a reset state claim 1 , and the bias logic is further configured to apply a voltage bias pulse to a memory cell in the reset state.3. The apparatus of claim 2 , wherein the bias logic is further configured to apply the voltage bias pulse to the memory cell immediately following performance of a memory reset operation on the memory cell.4. The apparatus of claim 2 , wherein the state of the bit of data in the memory cell is based on whether the read voltage is above or below a threshold voltage of the memory cell.5. The apparatus of claim 2 , wherein a time parameter or an amplitude parameter of the voltage bias pulse is based on a desired threshold voltage of the memory cell in the reset state.6. The apparatus of claim 2 , wherein the set state corresponds to a value of the bit of data equal to a first logical value claim 2 , and the reset state corresponds ...

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Номер записи: 47
15-02-2018 дата публикации

MEMORY SYSTEM WITH A WEIGHTED READ RETRY TABLE

Номер: US20180046527A1
Автор: Guo Zelei, RAGHU DEEPAK, Reusswig Philip, Yip Chris Nga Yee
Принадлежит: SanDisk Technologies LLC

A storage device with a memory may utilize an optimized read retry operation. A read retry table includes a number of read retry cases with updated read thresholds. The read thresholds in the read retry table may be used to avoid errors caused by shifting of charge levels. The optimization of read retry includes weighting or reordering of the read retry cases in the read retry table. The selection of a read retry case (and corresponding read thresholds) are determined based on the weighting or reordering. 1. A storage device comprising:a read retry table comprising a plurality of read retry cases, wherein each read retry case comprises a set of read thresholds; selecting one of the read retry cases from the read retry table based on a weight associated with each of the read retry cases, wherein the weight is based on one or more weighting factors;', 'shifting read thresholds according to the selected read retry case; and', 'updating the read retry table depending on whether the shifted read thresholds are correct., 'read retry circuitry configured to initiate a read retry operation comprising2. The storage device of wherein the weighting factors comprise a frequency of decode success claim 1 , a bit error rate (BER) claim 1 , or a reliability mechanism.3. The storage device of wherein the frequency of decode success comprises a frequency that a particular read retry case and its shifted read thresholds correct an error.4. The storage device of further comprising:a memory comprising memory blocks; anda controller coupled with the memory that is configured to access the read retry circuitry and initiate the read retry operation.5. The storage device of wherein the updating the read retry table comprises reordering the read retry cases according to priority.6. The storage device of wherein the priority corresponds to the weight for each of the read retry cases.7. The storage device of wherein the read thresholds comprise a voltage at which charge distributions are ...

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Номер записи: 48
03-03-2022 дата публикации

Semiconductor device and method for operating the same

Номер: US20220068352A1
Автор: Yun Gi Hong
Принадлежит: SK hynix Inc

According to an embodiment, a semiconductor device includes a transmission circuit including first and second transistors coupled in series between a first voltage terminal and a second voltage terminal, and a first common node coupled between the first and second transistors and coupled to a through line, the transmission circuit outputting a signal transferred from an internal circuit to the first common node according to an output control signal; a reception circuit including third and fourth transistors coupled in series between the first voltage terminal and the second voltage terminal, and a second common node coupled between the third and fourth transistors and coupled to the internal circuit, the reception circuit transferring a signal transferred through the through line to the internal circuit according to a first input control signal; and a deterioration acceleration circuit for applying stress to the first and third transistors according to a test signal.

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Номер записи: 49
25-02-2016 дата публикации

Semiconductor device including temperature ranges having temperature thresholds and method of determining therefor

Номер: US20160054374A1
Автор: Darryl G. Walker
Принадлежит: Darryl G. Walker

A method of determining temperature ranges and setting performance parameters in a semiconductor device that may include at least one temperature sensing circuit is disclosed. The temperature sensing circuits may be used to control various operating parameters to improve the operation of the semiconductor device over a wide temperature range. The performance parameters may be set to improve speed parameters and/or decrease current consumption over a wide range of temperature ranges.

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Номер записи: 50
25-02-2016 дата публикации

Testing and setting performance parameters in a semiconductor device and method therefor

Номер: US20160054379A1
Автор: Darryl G. Walker
Принадлежит: Darryl G. Walker

A method of determining temperature ranges and setting performance parameters in a semiconductor device that may include at least one temperature sensing circuit is disclosed. The temperature sensing circuits may be used to control various operating parameters to improve the operation of the semiconductor device over a wide temperature range. The performance parameters may be set to improve speed parameters and/or decrease current consumption over a wide range of temperature ranges.

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Номер записи: 51
14-02-2019 дата публикации

NONVOLATILE MEMORY DEVICE AND OPERATING METHOD OF NONVOLATILE MEMORY DEVICE

Номер: US20190051351A1
Автор: Jung Hyuntaek, PYO SUK-SOO, SONG TAEJOONG
Принадлежит:

A nonvolatile memory device includes a memory cell including memory cells and dummy cells, a row decoder connected to the memory cells through word lines, a dummy word line bias circuit connected to the dummy cells through dummy word lines, a write driver and sense amplifier connected to the memory cells through bit lines, and a dummy bit line bias circuit connected to the dummy cells through a dummy bit line. The dummy word line bias circuit is configured to apply a same or a different voltage to respective ones of the dummy word lines to turn off selected dummy cells and adjust a leakage current flowing through the dummy cells; and a leakage current in the memory cells is maintained at a substantially uniform level through adjustment of the leakage current in the dummy cells. 1. A nonvolatile memory device comprising:a memory cell array including a plurality of memory cells and dummy cells formed on a body;a row decoder connected to the memory cells through word lines;a dummy bit line bias circuit connected to the dummy cells through a dummy bit line;a dummy word line bias circuit connected to the dummy cells through a plurality of dummy word lines; anda write driver and sense amplifier connected to the memory cells through bit lines.2. The nonvolatile memory device of claim 1 , wherein the memory cells and the dummy cells have the same structure.3. The nonvolatile memory device of claim 1 , wherein one or more of the dummy cells include selection transistors respectively controlled by the dummy word lines and variable resistance elements claim 1 , andwherein, during a read operation associated with the memory cells, the dummy word line bias circuit applies voltages for turning off the selection transistors of the dummy cells to the dummy word lines.4. The nonvolatile memory device of claim 1 , further comprising:a source line driver connected to the memory cells through a plurality of source lines; anda leakage detector connected to the dummy cells through a ...

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Номер записи: 52
23-02-2017 дата публикации

READ VOLTAGE OFFSET

Номер: US20170053714A1
Автор: Guy Adam C., Muchherla Kishore K., Ratnam Sampath K.
Принадлежит:

Apparatuses, methods, and data structures that can be utilized to provide a read voltage offset are described. One or more apparatuses can include a memory device and a controller coupled to the memory device and configured to: access a data structure comprising write temperature data corresponding to a number of data segments stored in the memory device; read a particular data segment using a read voltage offset determined based on: the write temperature data from the data structure and corresponding to the particular data segment; and read temperature data corresponding to the particular data segment. 1. An apparatus , comprising:a memory device; and access a data structure comprising write temperature data corresponding to a number of data segments stored in the memory device;', 'read a particular data segment using a read voltage offset determined based on:', 'the write temperature data from the data structure and corresponding to the particular data segment; and', 'read temperature data corresponding to the particular data segment., 'a controller coupled to the memory device and configured to2. The apparatus of claim 1 , wherein a memory device storing the data structure is volatile memory.3. The apparatus of claim 1 , wherein the memory device storing the data structure is non-volatile memory.4. The apparatus of claim 3 , wherein the non-volatile memory includes the write temperature data programmed as metadata.5. The apparatus of claim 1 , wherein the write temperature data corresponds to a range of temperatures.6. The apparatus of claim 1 , wherein the data structure is configured to include additional write temperature data respectively corresponding to additional data segments.7. The apparatus of claim 1 , wherein the write temperature data comprises from two to eight bits.8. The apparatus of claim 1 , wherein the controller is further configured to access a temperature indicator.9. A method for providing a read voltage offset claim 1 , comprising: ...

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Номер записи: 53
13-02-2020 дата публикации

DEVICE AND METHOD FOR DATA-WRITING

Номер: US20200051598A1
Автор: LEE Po-Hao, Shih Yi-Chun
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A device includes a circuit cell, a first switching unit, and a second switching unit. The first switching unit is configured to output an auxiliary signal. The second switching unit is coupled between the first switching unit and the circuit cell, and configured to transmit a write voltage and an auxiliary signal to the circuit cell. 1. A device , comprising:a circuit cell;a first switching unit configured to output an auxiliary signal; anda second switching unit coupled between the first switching unit and the circuit cell, and configured to transmit a write voltage and the auxiliary signal to the circuit cell.2. The device of claim 1 , further comprising:a third switching unit configured to generate a current represented by the auxiliary signal, in response to a control voltage.3. The device of claim 1 , further comprising:a voltage regulator configured to output the write voltage; anda control signal generator configured to generate a control voltage according to a reference voltage and a reference current,wherein the first switching unit is configured to output the auxiliary signal according to the control voltage.4. The device of claim 3 , wherein the control signal generator comprises:an amplifier configured to generate the control voltage according to the reference voltage and a sensing voltage; anda fourth switching unit configured to generate the sensing voltage according to the control voltage.5. The device of claim 1 , wherein the circuit cell comprises a memory claim 1 , and the memory is programmed according to the write voltage and the auxiliary signal.6. The device of claim 1 , wherein the first switching unit is configured to be turned on in response to a first select signal of a plurality of select signals claim 1 , and the second switching unit is configured to be turned on in response to a second select signal of the plurality of select signals.7. The device of claim 1 , further comprising: a comparator configured to output an adjust signal ...

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Номер записи: 54
10-03-2022 дата публикации

TEST CIRCUIT AND SEMICONDUCTOR MEMORY SYSTEM INCLUDING THE TEST CIRCUIT

Номер: US20220076775A1
Автор: CHOI Sung Won, JUNG Jong Seok
Принадлежит: SK HYNIX INC.

A test circuit includes a control circuit and a counting circuit. The control circuit is configured to control a charging operation and a discharging operation on a test node. The counting circuit is configured to generate counting information by performing a counting operation during a unit measurement interval. 1. A test circuit comprising:a control circuit configured to control a charging operation and a discharging operation on a test node of a test target circuit; anda counting circuit configured to generate counting information corresponding to a defect of the test node by counting a counting dock signal during a unit measurement interval from a point of time that the charging operation on the test node is completed to a point of time that the discharging operation on the test node is completed.2. The test circuit according to claim 1 , wherein the unit measurement interval comprises a first unit measurement interval and a second unit measurement interval claim 1 , wherein the first unit measurement interval comprises an interval from a point of time that the charging operation on the test node is completed to a point of time that the discharging operation on the test node is completed claim 1 , and the second unit measurement interval comprises an interval from a point of time that the discharging operation on the test node is completed to a point of time that the charging operation on the test node is completed.3. The test circuit according to claim 1 , wherein the control circuit charges the test node to a preset charging voltage level through the charging operation claim 1 , and discharges the test node to a preset discharging voltage level through the discharging operation.4. The test circuit according to claim 3 , wherein the control circuit comprises:a charging circuit configured to charge the test node based on a charging control signal;a discharging circuit configured to discharge the test node based on a discharging control signal;a first comparison ...

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Номер записи: 55
21-02-2019 дата публикации

STRUCTURE AND METHOD FOR TESTING THREE-DIMENSIONAL MEMORY DEVICE

Номер: US20190057756A1
Автор: Kim Jong Jun, Kim Youn Cheul, Lee Jong Seuk, Li Yongna, Lu Zhenyu, Pan Feng, Song Lidong, YANG Simon Shi-Ning, YANG Steve Weiyi
Принадлежит: Yangtze Memory Technologies Co., Ltd.

Embodiments of structures and methods for testing three-dimensional (3D) memory devices are disclosed. In one example, a 3D memory device includes a memory array structure, a peripheral device structure, and an interconnect layer in contact with a front side of the memory array structure and a front side of the peripheral device structure, and a conductive pad at a back side of the memory array structure and that overlaps the memory array structure. The memory array structure includes a memory array stack, a through array contact (TAC) extending vertically through at least part of the memory array stack, and a memory array contact. The peripheral device structure includes a test circuit. The interconnect layer includes an interconnect structure. The conductive pad, the TAC, the interconnect structure, and at least one of the test circuit and the memory array contact are electrically connected. 1. A memory device , comprising: a memory array stack;', 'a through array contact (TAC) extending vertically through at least part of the memory array stack; and', 'one or more memory array contacts;, 'a memory array structure comprisinga first dielectric layer at a front side of the memory array structure;a plurality of first contacts in the first dielectric layer;a plurality of conductive pads at a backside of the memory array structure;a complementary metal-oxide-semiconductor (CMOS) structure;a metal layer at a front side of the CMOS structure, the metal layer comprising a plurality of metal patterns;a second dielectric layer on the metal layer; anda plurality of second contacts in the second dielectric layer,wherein the first dielectric layer and the second dielectric layer are joined face to face, such that the memory array structure is above the CMOS structure, and one or more electrical connections are formed by at least the plurality of conductive pads, the TAC, the plurality of first contacts, the plurality of second contacts, the plurality of metal patterns in the ...

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Номер записи: 56
01-03-2018 дата публикации

DATA STORAGE DEVICE AND OPERATING METHOD THEREOF

Номер: US20180061510A1
Автор: HAN Ju Hyeon, Park Jong Won, YANG Chan Woo
Принадлежит:

A data storage device includes a nonvolatile memory device; and a control unit suitable for controlling a program operation for memory cells of a page of the nonvolatile memory device, and processing a program fail in the case where the program operation fails, wherein the control unit adjusts a read voltage for discriminating an erase state and a program state having a threshold voltage most adjacent to the erase state, reads out data by applying the adjusted read voltage to the memory cells of the page, and performs an error handling operation to data stored in the memory cells of the page according to a result of comparing a reference value and a number of flipped bits of the data read out by applying the varied read voltage. 1. A data storage device comprising:a nonvolatile memory device; anda control unit suitable for controlling a program operation for memory cells of a page of the nonvolatile memory device, and processing a program fail in the case where the program operation fails,wherein the control unit adjusts a read voltage for discriminating an erase state and a program state having a threshold voltage most adjacent to the erase state, reads out data by applying the adjusted read voltage to the memory cells of the page, and performs an error handling operation to data stored in the memory cells of the page according to a result of comparing a reference value and a number of flipped bits of the data read out by applying the varied read voltage.2. The data storage device according to claim 1 , wherein the control unit performs the error handling operation in the case where the number of flipped bits is equal to or larger than the reference value.3. The data storage device according to claim 2 , wherein the control unit determines the number of flipped bits by comparing the data read out by applying the adjusted read voltage and original data of the program-failed page.4. The data storage device according to claim 1 , further comprising an error correction ...

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Номер записи: 57
22-05-2014 дата публикации

Read margin measurement in a read-only memory

Номер: US20140140141A1
Автор: David Alexander Grant
Принадлежит: Texas Instruments Inc

Read margin measurement circuitry for measuring the read margin of floating-gate programmable non-volatile memory cells. In some embodiments, the read margin of a cell with a floating-gate transistor in a non-conductive state is measured by periodically clocking a counter following initiation of a read cycle; a latch stores the counter contents upon the cell under test making a transition due to leakage of the floating-gate transistor. Logic for testing a group of cells in parallel is disclosed. In some embodiments, the read margin of a cell in which the floating-gate transistor is set to a conductive state is measured by repeatedly reading the cell, with the output developing a voltage corresponding to the duty cycle of the output of the read circuit.

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Номер записи: 58
02-03-2017 дата публикации

MEMORY DEVICE THAT SUPPORTS MULTIPLE MEMORY CONFIGURATIONS

Номер: US20170062039A1
Автор: Lao Tim, Na Byeong Cheol, Ong Adrian E.
Принадлежит:

A memory device comprises: a plurality of memory configuration modes; an option selection logic for selecting one of the plurality of memory configuration modes to operate the memory device; and bonding pads. The bonding pads are connected to inputs of the option selection logic. The bonding pads are configurable to allow for a default mode selection for the selected one of the plurality of memory configuration modes to operate the memory device. 1. A memory device , comprising:a plurality of memory configuration modes;an option selection logic for selecting one of the plurality of memory configuration modes to operate the memory device;test mode registers, wherein the test mode registers provide storage to receive a certain test mode register command; andbonding pads for selecting a default memory configuration mode,wherein the bonding pads are connected to inputs of the option selection logic, andwherein the selected one of the plurality of memory configuration modes is selected as a function of the certain test mode register command and the default memory configuration mode.2. The memory device of wherein the bonding pads are configurable claim 1 , and wherein the selected one of the plurality of memory configuration modes is further selected as a function of the configured bonding pads.3. (canceled)4. The memory device of wherein the certain test mode register command is inputted to the option selection logic claim 1 , and wherein the default memory configuration mode is overwritten by another one of the plurality of memory configuration modes based on the certain test mode register command.5. The memory device of wherein the plurality of memory configuration modes comprises low power double data rate 2 (“LPDDR2”) claim 1 , low power double data rate 3 (“LPDDR3”) claim 1 , and low power double data rate 4 (“LPDDR4”) claim 1 , wherein the plurality of memory configuration modes have a R+ mode claim 1 , and wherein the plurality of memory configuration modes have ...

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Номер записи: 59
04-03-2021 дата публикации

Voltage and Temperature Adaptive Memory Leakage Reduction Bias Circuit

Номер: US20210065821A1
Автор: Lam Kwan Him
Принадлежит:

This application discloses a memory device to retain stored data when receiving a voltage supply having at least a retention voltage level. The retention voltage level varies based on a supply voltage and a temperature of an environment around the memory device. A sensitive circuit can adjust the voltage supply received by the memory device based on the supply voltage and the temperature. The sensitive circuit can alter a memory bias supply voltage for the memory device to adjust the voltage supply towards the retention voltage level. The sensitive circuit can include a temperature dependent circuit to generate a bias voltage based on the supply voltage and the temperature, and an adjustment circuit to alter the memory bias supply voltage based on the bias voltage. The adjustment circuit also can include high temperature circuitry to adjust the memory bias supply voltage based on a leakage current from the memory device. 1. A system comprising:a memory device configured to retain stored data when receiving a voltage supply having at least a retention voltage level that varies based on a memory supply voltage and a temperature of an environment around the memory device; anda sensitive circuit configured to adjust the voltage supply received by the memory device based on the memory supply voltage and the temperature of the environment.2. The system of claim 1 , wherein the voltage supply corresponds to a difference between the memory supply voltage and a memory bias supply voltage associated with the memory device claim 1 , and wherein the sensitive circuit is configured to alter the memory bias supply voltage to adjust a voltage level of the voltage supply towards the retention voltage level.3. The system of claim 2 , wherein the sensitive circuit further comprising:a temperature dependent circuit configured to generate a bias voltage based, at least in part, on the temperature of the environment; andan adjustment circuit configured to alter the memory bias supply ...

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Номер записи: 60
04-03-2021 дата публикации

ADJUSTMENT OF READ AND WRITE VOLTAGES USING A SPACE BETWEEN THRESHOLD VOLTAGE DISTRIBUTIONS

Номер: US20210065824A1
Автор: Lang Murong, Zhou Zhenming
Принадлежит:

A current demarcation voltage is determined, where the current demarcation voltage is to be applied to a memory cell for reading a state of the memory cell. Based on the current demarcation voltage and a space between a first threshold voltage distribution corresponding to a first state of the memory cell and a second threshold voltage distribution corresponding to a second state of the memory cell, a test demarcation voltage having a low error rate of reading the state of the memory cell is selected. The current demarcation voltage is set to correspond to the selected test demarcation voltage. 1. A system comprising:a memory component including one or more memory cells; and determining a current demarcation voltage that is to be applied to a memory cell for reading a state of the memory cell;', 'selecting, based on the current demarcation voltage and a space between a first threshold voltage distribution corresponding to a first state of the memory cell and a second threshold voltage distribution corresponding to a second state of the memory cell, a test demarcation voltage having a low error rate of reading the state of the memory cell; and', 'setting the current demarcation voltage to correspond to the selected test demarcation voltage., 'a processing device, operatively coupled with the memory component, the processing device configured to perform operations comprising2. The system of claim 1 , wherein the operations further comprise:determining a plurality of spaces between the first threshold voltage distribution and the second threshold voltage distribution of the memory cell, each space associated with the memory cell under different operation conditions; anddetermining a plurality of test demarcation voltages spanning a voltage range that corresponds to a difference in the plurality of spaces and that includes the current demarcation voltage, wherein the selected test demarcation voltage is one of the plurality of test demarcation voltages.3. The system of ...

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Номер записи: 61
17-03-2022 дата публикации

Current test circuit, device and method, and storage medium

Номер: US20220082619A1
Автор: Maosong MA, Xinwang CHEN, Zhangqin ZHOU
Принадлежит: Changxin Memory Technologies Inc

A current test circuit can include a sampling resister array with a control end connected with a main control component, a first end is connected with a power conversion circuit, and a second end configured to be connected with a component to be tested. The sampling resistor array includes at least two sampling branches, each having an analog switch and a sampling resistor connected serially. In the test, the main control component can generate a control signal according to the operating state of the component and gate at least one sampling branch of the sampling resistor array through the control signal, obtain voltage values at two ends of the sampling resistor array through a voltage test assembly, and determine the current of the component according to the voltage values at two ends of the sampling resistor array and resistance values of the sampling resistor array.

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Номер записи: 62
08-03-2018 дата публикации

Raid data loss prevention

Номер: US20180067809A1
Автор: Brian A. Rinaldi, Clint A. Hardy, Karl A. Nielsen, Lokesh M. Gupta, Matthew G. Borlick
Принадлежит: International Business Machines Corp

A method for preventing data loss in a RAID includes monitoring storage drives making up a RAID. The method individually tests a storage drive of the RAID by subjecting the storage drive to a stress workload test. This stress workload test may be designed to place additional stress on the storage drive while refraining from adding stress to other storage drives in the RAID. In the event the storage drive fails the stress workload test (e.g., the storage drive cannot adequately handle the additional workload or generates errors in response to the additional workload), the method replaces the storage drive with a spare storage drive and rebuilds the RAID. In certain embodiments, the method tests the storage drive with greater frequency as the age of the storage drive increases. A corresponding system and computer program product are also disclosed.

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Номер записи: 63
10-03-2016 дата публикации

VOLTAGE COMPARATOR CIRCUIT AND USAGE THEREOF

Номер: US20160071551A1
Автор: Binyamini Lior, Herooti Lidar, Jungmann Noam, Kachir Elazar, Plass Donald W., Shalom Hezi, Wagner Israel
Принадлежит:

A circuit comprising a first power supply having a first voltage and a second power supplying having a second voltage, wherein said first and second voltages are different at least in some cycles of said circuit, a memory element, wherein said first and second power supplies are driven into said memory element, a voltage comparator having connected thereto said first and second power supplies, wherein said voltage comparator is an analog to digital converter configured to provide digital output indicting of a voltage difference over a predetermined threshold between said first and second power supplies, and a supply selector element, wherein said supply selector element is configured to disconnect said second power supply from said memory element in response to the digital output of said voltage comparator. 1. A circuit comprising:a first power supply having a first voltage and a second power supplying having a second voltage, wherein said first and second voltages are different at least in some cycles of said circuit;a memory element, wherein said first and second power supplies are driven into said memory element;a voltage comparator having connected thereto said first and second power supplies, wherein said voltage comparator is an analog to digital converter configured to provide digital output indicting of a voltage difference over a predetermined threshold between said first and second power supplies; anda supply selector element, wherein said supply selector element is configured to disconnect said second power supply from said memory element in response to the digital output of said voltage comparator.2. The circuit of claim 1 , wherein said memory element is a Static Random-Access Memory (SRAM) element claim 1 , wherein said first power supply is a cell power supply and said second power supply is a peripheral power supply.3. The circuit of claim 2 , wherein said memory element comprises an array of bit lines that are used to write to and read from cells of ...

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Номер записи: 64
10-03-2016 дата публикации

VOLTAGE COMPARATOR CIRCUIT AND USAGE THEREOF

Номер: US20160071617A1
Автор: Binyamini Lior, Herooti Lidar, Jungmann Noam, Kachir Elazar, Plass Donald W., Shalom Hezi, Wagner Israel
Принадлежит:

A method for testing a circuit comprising a memory element, a voltage comparator and a supply selector, the circuit is configured to be connected to two power supplies, the voltage comparator is configured to provide an output indicative of a voltage difference between the two power supplies above a predetermined threshold, the supply selector is configured to select a power supply to feed power to the memory element in response to the output from the voltage comparator. The method comprises connecting the two power supplies to the circuit, wherein said connecting comprises causing the two power supplies to drive power to the memory element and to another element of the circuit, wherein the voltage different between the two power supplies is above the predetermined threshold. The method further comprises that in response to said connecting, the supply selector of the circuit is invoked and disconnects one power supply from the memory element; whereby stress testing the circuit, the stress testing tests the memory element without a voltage difference condition, the stress testing tests the another element with the voltage difference condition. 1. A method for testing a circuit comprising a memory element , a voltage comparator and a supply selector , the circuit is configured to be connected to two power supplies , the voltage comparator is configured to provide an output indicative of a voltage difference between the two power supplies above a predetermined threshold , the supply selector is configured to select a power supply to feed power to the memory element in response to the output from the voltage comparator , the method comprising:connecting the two power supplies to the circuit, wherein said connecting comprises causing the two power supplies to drive power to the memory element and to another element of the circuit, wherein the voltage different between the two power supplies is above the predetermined threshold; andin response to said connecting, the ...

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Номер записи: 65
08-03-2018 дата публикации

Array Power Supply-Based Screening of Static Random Access Memory Cells for Bias Temperature Instability

Номер: US20180068713A1
Автор: Deng Xiaowei, Loh Wah Kit
Принадлежит:

A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both). Asymmetric bias voltages applied to the transistors in this manner will reduce the transistor drive current, and can thus mimic the effects of bias temperature instability (BTI). Cells that are vulnerable to threshold voltage shift over time can thus be identified. 1. A method of testing an integrated circuit , the integrated circuit including a microprocessor and a memory array , the memory array including memory cells arranged in rows and columns , each memory cell comprising first and second cross-coupled inverters and a first pass transistor , each column of memory cells associated with a first bit line coupled to the first pass transistor of each memory cell in the column , each row of memory cells associated with a word line coupled to gates of the pass transistors of the memory cells in the row;wherein, in operation, the first and second inverters are each biased from first and second array bias nodes;the method comprising:writing a first data state to a selected memory cell under normal bias conditions;applying a reduced bias at the first array bias node of the first inverter of the selected memory cell relative to a bias applied at the first array bias node of the second inverter of the selected memory cell, during the applying step the selected memory cell is accessed;determining whether the selected memory cell has passed the test method; andpackaging the integrated circuit if fewer than a limit of memory cells has passed the test ...

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Номер записи: 66
28-02-2019 дата публикации

METAL ISOLATION TESTING IN THE CONTEXT OF MEMORY CELLS

Номер: US20190067300A1
Автор: Chiu Te-Hsin, Lin Meng-Han, Wu Wei Cheng
Принадлежит:

In the present disclosure, it has been appreciated that memory structures, such as static random access memory (SRAM) structures, have feature densities that are extremely high. While this is beneficial in allowing the memory structures to store large amounts of data in a small chip footprint, it is potentially detrimental in that it makes the memory structures more susceptible to leakage current than the other areas of the chip. Accordingly, the present disclosure provides pseudo memory structures which are similar in terms of layout spacing to actual memory structures. However, rather than being used as actual memory structures that store data during operation, these pseudo memory structures are used to characterize leakage current in the design of the IC and/or to characterize the fabrication process used to manufacture the IC. 1. A method comprising:receiving a metal isolation test circuit comprising a pseudo static random access memory (SRAM) cell disposed on a semiconductor substrate, wherein the pseudo SRAM cell includes a plurality of transistors and an interconnect structure disposed over the plurality of transistors, the interconnect structure including a plurality of pins that are coupled to a plurality of nodes in the pseudo SRAM cell;applying a first voltage bias across first and second pins of the plurality of pins, and measuring a first leakage current while the first voltage bias is applied;applying a second voltage bias across third and fourth pins, and measuring a second leakage current while the second voltage bias is applied; andcharacterizing a process or a design rule by which the pseudo SRAM cell is made based on the first leakage current and the second leakage current.2. The method of claim 1 , further comprising:modifying the process, the design rule, or an actual SRAM cell design based on the characterization of the process or the design rule.3. The method of claim 2 , wherein the pseudo SRAM cell and the actual SRAM cell design have the ...

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Номер записи: 67
27-02-2020 дата публикации

Apparatus for memory control

Номер: US20200066322A1
Автор: Kazuko HIGURASHI, Masazumi Maeda
Принадлежит: Fujitsu Ltd

An apparatus for memory control includes a data storage area configured to store data indicative of a distribution of total current consumption required for a write operation as measured with respect to one or more nonvolatile memory devices of a first type, and a control apparatus configured to evaluate, based on the data indicative of the distribution, a degree to which a total amount of current consumption required for a write operation with respect to a memory area in a nonvolatile memory device of the same first type, regarding a current flowing from a power supply to the nonvolatile memory device during the write operation, is deviated toward larger total current consumptions in the distribution, thereby determining whether the memory area is satisfactory.

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Номер записи: 68
17-03-2016 дата публикации

Power Loss Test Device And Method For Nonvolatile Memory Device

Номер: US20160078967A1
Автор: LEE Sung-woo
Принадлежит: Elixir Flash Technology Co., Ltd.

A power loss test apparatus for a non-volatile memory device includes a test-board including at least one socket into which at least one test target non-volatile memory device is inserted, a micro controller that determines whether to supply power to the test target non-volatile memory device based on current consumption information or operating state information of the test target non-volatile memory device, and a tester that performs a power loss test for the test target non-volatile memory device based on whether the power is supplied to the test target non-volatile memory device. 1. A power loss test apparatus for a non-volatile memory device comprising:a test-board including at least one socket into which at least one test target non-volatile memory device is inserted;a micro controller configured to determine whether to supply power to the test target non-volatile memory device based on current consumption information or operating state information of the test target non-volatile memory device; anda tester configured to perform a power loss test for the test target non-volatile memory device based on whether the power is supplied to the test target non-volatile memory device.2. The apparatus of claim 1 , wherein the test target non-volatile memory device constitutes an embedded multi media card.3. The apparatus of claim 1 , wherein the micro controller is included in the test-board or in the tester.4. The apparatus of claim 1 , wherein the test-board includes:a current monitoring module configured to monitor current consumption of the test target non-volatile memory device to generate the current consumption information; anda power control module configured to supply the power to the test target non-volatile memory device through the socket when the micro controller determines to supply the power to the test target non-volatile memory device and configured to cut off the power from the test target non-volatile memory device through the socket when the micro ...

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Номер записи: 69
15-03-2018 дата публикации

Efficient calibration of memory devices

Номер: US20180075887A1
Автор: David D. Cadigan, Gary A. Van Huben, John S. Bialas, Jr., Stephen P. Glancy, Warren E. Maule
Принадлежит: International Business Machines Corp

A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A temporal calibration mechanism reduces the time and resources for calibration by reducing the number tests needed to sufficiently determine the boundaries of the data eye of the memory device. For one or more values of the voltage reference, the temporal calibration mechanism performs a minimal number of tests to find the edges of the data eye for the hold and setup times.

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Номер записи: 70
24-03-2022 дата публикации

NONVOLATILE MEMORY DEVICE AND STORAGE DEVICE INCLUDING NONVOLATILE MEMORY DEVICE

Номер: US20220093206A1
Автор: Im Jaewoo, JOO Sang-Hyun, JUNG Won-Taeck, Kim Hyungsoo, PARK TAE-MIN
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

Disclosed is a nonvolatile memory device, which includes a memory cell array including cell strings, a row decoder connected with a ground selection transistor of each of the cell strings through a ground selection line, connected with memory cells of each of the cell strings through word lines, and connected with a string selection transistor of each of the cell strings through a string selection line, and a page buffer connected with the cell strings through bit lines. In a first period of a check operation, the page buffer applies a first bias voltage to the bit lines, and the row decoder applies a turn-off voltage to the ground selection line, a turn-on voltage to the string selection line, and a first check voltage to the word lines. In a second period of the check operation, the page buffer senses first changes of voltages of the bit lines. 1. A nonvolatile memory device comprising:a memory cell array including cell strings, wherein each of the cell strings includes a ground selection transistor, memory cells, and a string selection transistor stacked in a direction perpendicular to a substrate;a row decoder connected with the ground selection transistor of each of the cell strings through a ground selection line, connected with the memory cells of each of the cell strings through word lines, and connected with the string selection transistor of each of the cell strings through a string selection line; anda page buffer connected with the cell strings through bit lines,wherein, in a first period of a check operation, the page buffer is configured to apply a first bias voltage to the bit lines,wherein, in the first period of the check operation, the row decoder is configured to apply a turn-off voltage to the ground selection line, to apply a turn-on voltage to the string selection line, and to apply a first check voltage to the word lines,wherein, in a second period of the check operation, the page buffer is configured to sense first changes of voltages of the ...

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Номер записи: 71
05-03-2020 дата публикации

Systems And Methods For Creating And/Or Modifying Memory Configuration Settings

Номер: US20200073568A1
Автор: Craig Chaiken, Michael Arms, Stephen Cooper, Vinod Makhija
Принадлежит: Dell Products LP

Systems and methods are provided for creating and/or modifying memory configuration settings (e.g., such as memory timing and memory drive voltage) for use at selected and/or varying memory temperature/s. The disclosed systems and methods may be implemented to create a relationship between optimized memory configuration settings for different memory temperatures during burn-in testing and/or on an ad-hoc basis.

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Номер записи: 72
05-03-2020 дата публикации

ERROR CORRECTION CODE EVENT DETECTION

Номер: US20200073754A1
Автор: Kreifels Gerard A., Lei Jianfei, Mangalindan Paolo E., Proescholdt Andrew D., Zhang Yihua
Принадлежит:

Methods, systems, and devices for operating a memory cell or cells are described. An error in stored data may be detected by an error correction code (ECC) operation during sensing of the memory cells used to store the data. The error may be indicated in hardware by generating a measurable signal on an output node. For example, the voltage at the output node may be changed from a first value to a second value. A device monitoring the output node may determine an error has occurred for a set of data based at least in part on the change in the signal at the output node. 1. (canceled)2. A method of operating an electronic memory apparatus , comprising:performing a read operation on a set of memory cells;detecting an error in data read from the set of memory cells based at least in part on an error correction code (ECC) operation performed on the data;changing a voltage of an output pin of the electronic memory apparatus from a first level to a second level based at least in part on detecting the error, the second level indicating the error; andchanging the voltage of the output pin from the second level to the first level based at least in part on determining that a threshold amount of time has elapsed since the error was detected.3. The method of claim 1 , further comprising:incrementing a counter that represents a quantity of detected errors, wherein the counter is incremented based at least in part on the voltage of the output pin changing from the first level to the second level; andperforming a refresh operation based at least in part on the counter exceeding a threshold value.4. The method of claim 1 , further comprising:detecting a second error in data read from a second set of memory cells; andmaintaining the voltage of the output pin at the second level irrespective of the detection of the second error.5. The method of claim 1 , further comprising:selecting a second set of memory cells for a read operation; andmaintaining the voltage of the output pin at the ...

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Номер записи: 73
22-03-2018 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF DIAGNOSING SEMICONDUCTOR DEVICE

Номер: US20180080976A1
Автор: ASAI Mikio, FUKUSHIMA Yasuhiko, KOBASHI Hisao
Принадлежит:

A semiconductor device includes a logic circuit, a memory circuit having a plurality of first static memory cells formed by a transistor on the semiconductor substrate, a monitor circuit having a second static memory cell formed by a transistor on the semiconductor substrate, the monitor circuit being configured to apply stress to the second static memory cell during a period in which the semiconductor device operates so that a state of the second static memory cell can be notified, and a bus coupled with the logic circuit, the memory circuit and the monitor circuit, wherein a size of the transistor of one cell of the first static memory cells is substantively the same as that of the transistor of the second static memory cell. 1. A semiconductor device comprising:a logic circuit;a memory circuit including a plurality of first static memory cells formed by a transistor on the semiconductor substrate;a monitor circuit including a second static memory cell formed by a transistor on the semiconductor substrate, the monitor circuit being configured to apply stress to the second static memory cell during a period in which the semiconductor device operates so that a state of the second static memory cell can be notified; anda bus coupled with the logic circuit, the memory circuit and the monitor circuit,wherein a size of the transistor of one cell of the first static memory cells is substantively the same as that of the transistor of the second static memory cell.2. The semiconductor device according to claim 1 ,wherein each of the plurality of first static memory cells includes a pair of inverter circuits which are connected between a first voltage node and a reference voltage node, and whose inputs and outputs are cross-connected to each other, andthe second static memory cell includes a pair of inverter circuits which are connected between a second voltage node and a reference voltage node, and whose inputs and outputs are cross-connected to each other.3. The ...

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Номер записи: 74
14-03-2019 дата публикации

CONTROL METHOD FOR MEMORY DEVICE

Номер: US20190080727A1
Автор: IZUMI Tatsuo, Suzuki Ryota
Принадлежит:

According to one embodiment, a method of controlling a memory device includes supplying a second potential having a first value to a second electrode and simultaneously, or thereafter, supplying a third potential to a third electrode, and thereafter stopping supply of the third potential such that the potential of the third electrode decays while reducing the potential of the second electrode, and thereafter supplying a first potential to the first electrode. 1. A method of operating a memory device that comprises a plurality of electrodes , the method comprising:supplying a second potential having a first value to a second electrode and simultaneously, or thereafter, supplying a third potential to a third electrode;stopping supply of the third potential such that the potential of the third electrode decays while reducing the potential of the second electrode; andsupplying a first potential to the first electrode after stopping supply of the third potential.2. The method of operating a memory device according to claim 1 , further comprising:reducing the potential of the second electrode by allowing the second potential to decay to a value less than the first value; andsupplying the second potential to the second electrode at a second level less than the first value but greater than the value to which the second electrode decayed.3. The method of operating a memory device according to claim 2 , further comprising supplying the second potential to the second electrode at the second level simultaneously with the supplying of the first potential to the first electrode.4. The method of operating a memory device according to claim 2 , further comprising:supplying the second potential to the second electrode at the second level before supplying of the first potential to the first electrode.5. The method of operating a memory device according to claim 1 , further comprising:supplying a fourth potential to a fourth electrode before supplying any of the first, second, and ...

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Номер записи: 75
14-03-2019 дата публикации

APPARATUSES AND METHODS FOR CURRENT LIMITATION IN THRESHOLD SWITCHING MEMORIES

Номер: US20190080756A1
Автор: Cui Mingdong, Giduturi Hari, Pellizzer Fabio
Принадлежит: MICRON TECHNOLOGY, INC.

Apparatuses and methods for limiting current in threshold switching memories are disclosed. All example apparatus, may include a plurality of first decoder circuits, a plurality of second decoder circuits, an array of memory cells, and a control circuit. Each memory cell of the array of memory cells may be cells coupled to a pair of first decoder circuits of the plurality of first decoder circuits, and further coupled to a pair of second decoder circuits of the plurality of second decoder circuits. The control circuit may be coupled to the plurality of first decoder circuits and the plurality of second decoder circuits, and the control circuit may be configured to activate a first one of the pair of first decoder circuits coupled to a memory cell of the array of memory cells before a second one of the pair of first decoder circuits, and further configured to activate a first one of the pair of second decoder circuits coupled to the memory cell of the array of memory cells before a second one of the pair of second decoder circuits to access the a memory cell. 1. An apparatus , comprising:a first memory cell coupled to a first pair of decoder circuits via a first access line and a second access line;a second memory cell coupled to one of the first pair of decoder circuits via the first access line and coupled to one of a second pair of decoder circuits; anda control circuit coupled to the first pair of decoder circuits and the second pair of decoder circuits, and wherein the control circuit is configured to sequentially activate the first pair of decoder circuits, wherein a first one of the first pair of decoder circuits associated with a first parasitic load is activated before a second one of the first pair of decoder circuits associated with a second parasitic load.2. The apparatus of claim 1 , wherein the first memory cell comprises a memory material and a chalcogenide switching device.3. The apparatus of claim 2 , wherein the memory material includes a memory ...

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Номер записи: 76
14-03-2019 дата публикации

Ferroelectric memory cell recovery

Номер: US20190080782A1
Автор: Andrea Locatelli, Giorgio Servalli, Marcello Mariani
Принадлежит: Micron Technology Inc

Methods, systems, and devices for recovering fatigued ferroelectric memory cells are described. Recovery voltages may be applied to a ferroelectric memory cell that is fatigued due to repeated access (read or write) operations. The recovery voltage may have a greater amplitude than the access voltage and may include multiple voltage pulses or a constant voltage. The recovery operation may be performed in the background as the memory array operates, or it may be performed when a host device is not actively using the memory array. The recovery operations may be performed periodically or may include discrete series of pulses distributed among several instances.

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Номер записи: 77
24-03-2016 дата публикации

Method and system for improving the radiation tolerance of floating gate memories

Номер: US20160086676A1
Автор: Adam Duncan, Andrew Howard, James David Ingalls, Matthew Gadlage, Matthew Kay
Принадлежит: US Department of Navy

A method of improving radiation tolerance of floating gate memories is provided herein. Floating gate memories can include a floating gate transistor or a block of floating gate transistors. A floating gate transistor can include a semiconductor region, a source region, a drain region, a floating gate region, a tunnel oxide region, an oxide-nitride-oxide region, and a control gate region. A floating gate transistor or block of floating gate transistors can be written to multiple times in order to accumulate charge on one or more floating gate regions in accordance with an embodiment of the invention. When exposed to radiation, a floating gate region can retain its charge above a certain voltage threshold. A block of floating gate transistors can communicate with an external device where the external device can read a state of the block of floating gate transistors in accordance with an embodiment of the invention.

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Номер записи: 78
24-03-2016 дата публикации

SEMICONDUCTOR DEVICE FOR TESTING LARGE NUMBER OF DEVICES AND COMPOSING METHOD AND TEST METHOD THEREOF

Номер: US20160086863A1
Автор: HYUN DaiJoon, Jeong Kwangok, WON Hyosig
Принадлежит:

Provided is a method for testing a plurality of transistors of a semiconductor device. The method includes forming a plurality of elements or a plurality of logic using a Front End Of Line (FEOL) process, forming a selection logic using at least one of the plurality of elements or the plurality of logic cells, connecting the selection logic and the plurality of transistors, forming a pad for connecting an input terminal of the selection logic and drain or source terminals of the plurality of transistors, and sequentially selecting the plurality of transistors using the selection logic and measuring an electrical characteristic of selected transistors among the plurality of transistors. 1. A method for testing a plurality of transistors of a semiconductor device , comprising:forming a plurality of elements or a plurality of logic cells using a Front End Of Line (FEOL) process;forming a selection logic using at least one of to the plurality of elements or the plurality of logic cells;connecting the selection logic and the plurality of transistors;forming a pad for connecting an input terminal of the selection logic and drain or source terminals of the plurality of transistors; andsequentially selecting the plurality of transistors using the selection logic and measuring an electrical characteristic of selected transistor among the plurality of transistors.2. The method of claim 1 , wherein the plurality of elements are elements placed at a specific chip area of the semiconductor device.3. The method of claim 1 , wherein the plurality of logic cells are standard logic cells at the semiconductor device.4. The method of claim 1 , whereinthe plurality of logic cells include logic filler cells that are cells assigned to filler cells at a design level of the semiconductor device, andthe logic filler cells are formed to have the same function of a standard logic cell.5. The method of claim 4 , whereinthe logic filler cells and the standard logic cells each include input and ...

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Номер записи: 79
25-03-2021 дата публикации

IMPRINT RECOVERY FOR MEMORY ARRAYS

Номер: US20210090641A1
Автор: Bangalore Lakshman Shashank, Basuta Sukneet Singh, Harms Jonathan D., Strand Jonathan J.
Принадлежит:

Methods, systems, and devices for imprint recovery for memory arrays are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting. 1. A method , comprising:determining that a set of memory cells are imprinted in respective first logic states;restricting access to the set of memory cells based at least in part on determining that the set of memory cells are imprinted in the respective first logic states;performing an imprint recovery procedure on the set of memory cells while access to the set of memory cells is restricted, the imprint recovery procedure to increase an ability of the set of memory cells to switch between storing the respective first logic states and storing respective second logic states; andpermitting access to the set of memory cells after performing the imprint recovery procedure.2. The method of claim 1 , further comprising:determining, after performing the imprint recovery procedure, whether the imprint recovery procedure was successful.3. The method of claim 2 , further comprising:performing a second imprint recovery procedure on the set of memory cells based at least in part on determining that the imprint recovery procedure was not successful.4. The method of claim 2 , further ...

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Номер записи: 80
25-03-2021 дата публикации

DEVICE INCLUDING MEMORY CONTROLLER, MEMORY DEVICE, AND POWER MANAGEMENT CIRCUIT, AND METHOD OF OPERATING THE SAME

Номер: US20210090673A1
Автор: AN Joong Hyun, Jin Yong, Kim Yoon Jin
Принадлежит:

The present technology includes a memory controller that controls auxiliary power cells of which the charge counts is small to be preferentially charged, based on charge count information of each of a plurality of auxiliary power cells included in an auxiliary power device that supplies power to a memory device and a memory controller. 1. A memory controller that controls an operation of a memory device , the memory controller comprising:an auxiliary power cell information storage including charge count information of each of a plurality of auxiliary power cells included in an auxiliary power device that supplies auxiliary power as a substitute for main power to the memory device and the memory controller; andan auxiliary power cell controller configured to control the charging of the plurality of auxiliary power cells based on the charge count information so that the differences between respective charge counts of the plurality of auxiliary power cells are minimized.2. The memory controller of claim 1 , wherein the auxiliary power cell controller comprises:a selected auxiliary power cell determiner configured to generate, according to the charge count information, auxiliary power cell selection information including information on selected auxiliary power cells that are auxiliary power cells to be charged; andan auxiliary power cell charge signal generator configured to generate cell selection signals for selecting the selected auxiliary power cells according to the auxiliary power cell selection information.3. The memory controller of claim 2 , wherein the selected auxiliary power cell determiner selects a predetermined number of the plurality of auxiliary power cells having a relatively small charge counts as the selected auxiliary power cells.4. The memory controller of claim 3 , wherein the predetermined number is the number smaller than the number of the plurality of auxiliary power cells.5. The memory controller of claim 2 , wherein the charge count ...

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Номер записи: 81
25-03-2021 дата публикации

Measurement of mtj in a compact memory array

Номер: US20210090679A1
Автор: Minh Quang Tran
Принадлежит: Spin Memory Inc

A system and method for testing a magnetic memory cell in a bit cell array to determine whether the electrical resistance values of the memory cell are within acceptable parameters. The system and method allows for the determination of the electrical resistance of the memory cell without parasitic resistance associated with that memory cell in order to accurately determine the electrical resistance of the memory cell.

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Номер записи: 82
25-03-2021 дата публикации

IMPRINT MANAGEMENT FOR MEMORY

Номер: US20210090680A1
Автор: Bangalore Lakshman Shashank, Basuta Sukneet Singh, Harms Jonathan D., Strand Jonathan J.
Принадлежит:

Methods, systems, and devices for imprint recovery management for memory systems are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting. 1. A method , comprising:writing a first set of logic states to a subset of memory cells of a memory array;reading, using a first reference voltage, the subset of memory cells to obtain a second set of logic states that are based at least in part on the first set of logic states;reading, using a second reference voltage, the subset of memory cells to a obtain a third set of logic states that are based at least in part on the first set of logic states;determining a first quantity of errors associated with the second set of logic states and a second quantity of errors associated with the third set of logic states; andperforming a recovery operation on the memory array based at least in part on a difference between the first quantity of errors and the second quantity of errors.2. The method of claim 1 , further comprising:calculating a gradient based at least in part on the first quantity of errors and the second quantity of errors; andcomparing the calculated gradient to an expected gradient, wherein performing the recovery operation is based at least in part on ...

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Номер записи: 83
25-03-2021 дата публикации

IMPRINT RECOVERY FOR MEMORY CELLS

Номер: US20210090681A1
Автор: Bangalore Lakshman Shashank, Basuta Sukneet Singh, Harms Jonathan D., Strand Jonathan J.
Принадлежит:

Methods, systems, and devices for imprint recovery for memory cells are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting. 1. A method , comprising:determining to perform an imprint recovery procedure on a memory cell configured to store one of a set of logic states based at least in part on detecting, for a set of memory cells comprising the memory cell, a quantity of mismatched logic states that satisfies a threshold quantity of mismatched logic states, wherein the imprint recovery procedure is to increase an ability of the memory cell to switch between storing a first logic state of the set of logic states and storing a second logic state of the set of logic states; andapplying to the memory cell, based at least in part on determining to perform the imprint recovery procedure, a set of one or more voltage pulses each having a polarity associated with the second logic state.2. The method of claim 1 , further comprising:applying to the memory cell a second set of one or more voltage pulses each having a second polarity associated with the first logic state.3. The method of claim 2 , wherein:the set of one or more voltage pulses each have a first duration; andthe second set of one or more voltage ...

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Номер записи: 84
25-03-2021 дата публикации

SELF-ADAPTIVE READ VOLTAGE ADJUSTMENT USING DIRECTIONAL ERROR STATISTICS FOR MEMORIES WITH TIME-VARYING ERROR RATES

Номер: US20210090683A1
Автор: Chen Zhengang, Xie Tingjun
Принадлежит:

A processing device in a memory system determines a first error rate associated with a first number of bits written to the memory device as a first logical value and erroneously read as a second logical value and corresponding to a first range of a plurality of write-to-read delay times and a second error rate associated with a second number of bits written to the memory device as the second logical value and erroneously read as the first logical value and corresponding to the first range of the plurality of write-to-read delay times. The processing device further determines whether a ratio of the first error rate to the second error rate satisfies a first threshold criterion, and responsive to the ratio of the first error rate to the second error rate not satisfying the first threshold criterion, adjusts a read voltage level associated with the first range. 1. A system comprising:a memory device; and determining a first error rate associated with a first number of bits written to the memory device as a first logical value and erroneously read as a second logical value and corresponding to a first range of a plurality of write-to-read delay times and a second error rate associated with a second number of bits written to the memory device as the second logical value and erroneously read as the first logical value and corresponding to the first range of the plurality of write-to-read delay times;', 'determining whether a ratio of the first error rate to the second error rate satisfies a first threshold criterion; and', 'responsive to the ratio of the first error rate to the second error rate not satisfying the first threshold criterion, adjusting a read voltage level associated with the first range., 'a processing device, operatively coupled with the memory device, to perform operations comprising2. The system of claim 1 , wherein determining the first error rate comprises:monitoring read operations performed on segments of the memory device having write-to-read delay ...

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Номер записи: 85
29-03-2018 дата публикации

APPARATUSES AND METHODS FOR CURRENT LIMITATION IN THRESHOLD SWITCHING MEMORIES

Номер: US20180090204A1
Автор: Cui Mingdong, Giduturi Hari, Pellizzer Fabio
Принадлежит: MICRON TECHNOLOGY, INC.

Apparatuses and methods for limiting current in threshold switching memories are disclosed. An example apparatus may include a plurality of first decoder circuits, a plurality of second decoder circuits, an array of memory cells, and a control circuit. Each memory cell of the array of memory cells may be cells coupled to a pair of first decoder circuits of the plurality of first decoder circuits, and further coupled to a pair of second decoder circuits of the plurality of second decoder circuits. The control circuit may be coupled to the plurality of first decoder circuits and the plurality of second decoder circuits, and the control circuit may be configured to activate a first one of the pair of first decoder circuits coupled to a memory cell of the array of memory cells before a second one of the pair of first decoder circuits, and further configured to activate a first one of the pair of second decoder circuits coupled to the memory cell of the array of memory cells before a second one of the pair of second decoder circuits to access the a memory cell. 1. An apparatus , comprising:a plurality of decoder circuits including a pair of decoder circuits; anda control circuit coupled to the plurality of decoder circuits, the control circuit configured to activate a first one of the pair of decoder circuits based on a first parasitic load before a second one of the pair of decoder circuits based on a second parasitic load.2. The apparatus of claim 1 , wherein the control circuit is configured to activate a target memory cell based on a memory address of the pair of decoder circuits.3. The apparatus of claim 1 , wherein the control circuit is configured to sequentially activate the first one of the pair of decoder circuits before the second one of the pair of first decoder circuits based claim 1 , at least in part claim 1 , on the first parasitic load being larger than the second parasitic load.4. The apparatus of claim 3 , wherein the first one of the pair of decoder ...

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Номер записи: 86
05-05-2022 дата публикации

MEMORY DEVICE CAPABLE OF OUTPUTTING FAIL DATA IN PARALLEL BIT TEST AND MEMORY SYSTEM INCLUDING THE MEMORY DEVICE

Номер: US20220139485A1
Автор: Choi Insu, KIM DAEJEONG, KIM Dohan, KIM NAMHYUNG, SEO DEOKHO, SHIN WONJAE
Принадлежит:

A memory device includes a memory cell array and a test controller. The memory cell array includes a plurality of memory cells, where the memory cell array is divided into multiple regions. The test controller is configured to perform a parallel bit test (PBT) on the plurality of memory cells, where the test controller selects fail data including a fail data bit among internal data output from the multiple regions during the PBT, and outputs the fail data via a data input/output signal line to the outside of the memory device.

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Номер записи: 87
19-03-2020 дата публикации

Semiconductor device

Номер: US20200091239A1
Автор: Takayuki Miyazaki
Принадлежит: Kioxia Corp

A semiconductor device includes a plurality of first conductive lines in a first wiring layer, a plurality of second conductive lines in a second wiring layer, and a plurality of memory cells between the first and second conductive lines in a first direction in a first region. A plurality of third conductive lines in the first wiring layer, a plurality of fourth conductive lines in the second wiring, and a plurality of first memory lines are in a second region. The third conductive lines extends in a second direction and are spaced from each other in a third direction. The fourth conductive lines extend in the second direction and are spaced in the third direction. The first memory lines are between the third conductive lines and the fourth conductive lines in the first direction. The first memory lines comprise the same materials as the memory cells.

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Номер записи: 88
16-04-2015 дата публикации

MEMORY DEVICE RETENTION MODE BASED ON ERROR INFORMATION

Номер: US20150106671A1
Автор: Guo Ziyu, KONG Xiangming, Zhang Shayan
Принадлежит: Freescale Semiconductor, Inc.

A controller for a memory device has a power control section to control power to a memory element in an operation mode and in a retention mode. A monitoring section receives and monitors error information and a storage section stores a retention parameter. In the operation mode, the power control section causes an operation voltage to be applied to the memory element, and in the retention mode, the power control section causes a time-varying voltage to be applied to the memory. The power control section also causes the voltage across the memory element to change in the retention mode between a first retention voltage and a second retention voltage based on the retention parameter. 1. A controller for a memory device , comprising:a power control section to control power to a memory element of the memory device in an operation mode and in a retention mode;a monitoring section for receiving and monitoring error information indicative of an error in the memory device; and the power control section causes an operation voltage to be applied to the memory element in the operation mode, and causes a time-varying voltage to be applied to the memory element in the retention mode,', 'the time-varying voltage changes between a first retention voltage and a second retention voltage, the second retention voltage being less than the first retention voltage, and the first retention voltage being less than the operation voltage,', 'the power control section controls the second retention voltage based on the retention parameter, and', 'the retention parameter is set based on the error information., 'a storage section for storing a retention parameter, wherein,'}2. The controller of claim 1 , wherein the error information is based on an error correction code.3. The controller of claim 1 , wherein the error information is determined based on a result of reading the memory in the operation mode.4. The controller of claim 1 , wherein the memory element is a reference memory element ...

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Номер записи: 89
12-04-2018 дата публикации

Screening for Data Retention Loss in Ferroelectric Memories

Номер: US20180102184A1
Автор: Carl Z. Zhou, John A. Rodriguez, Richard A. Bailey
Принадлежит: Texas Instruments Inc

A data retention reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays. Sampled groups of cells in the FRAM array are tested at various reference voltage levels, after programming to a high polarization capacitance data state and a relaxation time at an elevated temperature. Fail bit counts of the sample groups at the various reference voltage levels are used to derive a test reference voltage, against which all of the FRAM cells in the integrated circuit are then tested after preconditioning (i.e., programming) and another relaxation interval at the elevated temperature, to determine those cells in the integrated circuit that are vulnerable to long-term data retention failure.

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Номер записи: 90
23-04-2015 дата публикации

Efficient Reduction of Read Disturb Errors

Номер: US20150113341A1
Автор: Camp Charles J., FISHER TIMOTHY J., Frost Holloway H., Fuxa James A., SHELTON Lance W.
Принадлежит:

Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block. 1. A method of reducing read-disturb errors in a memory system comprising a nonvolatile memory space organized into a plurality of blocks , each block comprising a plurality of pages , and each page defining an individually addressable physical memory location , the method comprising the steps of:accumulating a Block READ Count corresponding to the number of times any of the pages in a first block have been read;determining whether the Block READ Count for the first block has reached a predetermined number;maintaining a list of pages to be moved, the list including a plurality of entries representing pages to be moved; andafter the Block READ Count for the first block has reached a predetermined number:if the list of pages to be moved is not full, responding to a first READ request directed to a first target page within the first block by moving data stored within the first target page to a second block that is different from the first block and designating data that remains stored within the first target page as invalid data while retaining within the first block ...

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Номер записи: 91
11-04-2019 дата публикации

MARGIN TEST FOR MULTIPLE-TIME PROGRAMMABLE MEMORY (MTPM) WITH SPLIT WORDLINES

Номер: US20190108894A1
Автор: ANAND Darren L., FIFIELD John A., Hunt-Schroeder Eric D.
Принадлежит:

The present disclosure relates to a structure which includes a twin-cell memory which includes a first device and a second device and which is configured to store data which corresponds to a threshold voltage difference between the first device controlled by a first wordline and the second device controlled by a second wordline. 1. A structure comprising a twin-cell memory which includes a first device and a second device and which is configured to store data which corresponds to a threshold voltage difference between the first device controlled by a first wordline and the second device controlled by a second wordlinewherein the first wordline is connected to a gate of the first device, the second wordline is connected to a gate of the second device, and the first wordline is a different wordline than the second wordline.2. The structure of claim 1 , wherein the first device and the second device are field effect transistors (FETs) of the twin-cell memory and the structure is a multiple time programmable memory (MTPM) array.3. The structure of claim 2 , wherein the first device and the second device are NFETs.4. The structure of claim 2 , wherein the first device and the second device are PFETs.5. The structure of claim 1 , wherein the first wordline is enabled with a different voltage potential than the second wordline during a signal margin test operation.6. The structure of claim 5 , wherein the first wordline has a higher voltage potential than the second wordline during a true data type test of the signal margin test operation.7. The structure of claim 5 , wherein the first wordline has a lower voltage potential than the second wordline during a complement data type test of the signal margin test operation.8. The structure of claim 1 , wherein the first wordline is enabled with a same voltage potential as the second wordline during a non-signal margin test read operation.9. The structure of claim 8 , wherein the same voltage potential is a threshold voltage of ...

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Номер записи: 92
11-04-2019 дата публикации

MARGIN TEST FOR ONE-TIME PROGRAMMABLE MEMORY (OTPM) ARRAY WITH COMMON MODE CURRENT SOURCE

Номер: US20190108895A1
Автор: FIFIELD John A.
Принадлежит:

The present disclosure relates to a structure which includes a current-mirror control node which is configured to adjust a current margin and provide the adjusted current margin to at least one one-time programmable memory (OTPM) cell. 1. A structure comprising:a current-mirror control node which is configured to adjust a current margin and provide the adjusted current margin to at least one one-time programmable memory (OTPM) cell; anda twin-cell memory in the OTPM cell which is configured to be programmable using a plurality of write operations based on the adjusted current margin,wherein the twin-cell memory comprises a pair of NFET devices with different threshold voltages,the pair of NFET devices comprises a true NFET transistor and a complement NFET transistor, anda word line is connected to a gate of the true NFET transistor and a gate of the complement NFET transistor.2. The structure of claim 1 , further comprising:a current sense amplifier which is connected to the twin-cell memory and is configured to sense a current differential of the twin-cell memory and latch a differential voltage based on the current differential.3. The structure of claim 2 , wherein the current sense amplifier comprises a plurality of PFET devices and each of the PFET devices has a gate which is commonly connected to the current-mirror control node.4. The structure of claim 3 , wherein the plurality of PFET devices are configured to adjust the current margin to a true bit line (BLT) and a complement bit line (BLC) of the current sense amplifier to create the differential voltage.5. The structure of claim 2 , wherein the current sense amplifier comprises a latch which is configured to store the differential voltage.6. (canceled)7. The structure of claim 2 , wherein the current sense amplifier is connected to the twin-cell memory array through a true bit line (BLT) and a complement bit line (BLC).8. The structure of claim 1 , further comprising a margin adjustment circuit which ...

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Номер записи: 93
11-04-2019 дата публикации

APPARATUS AND METHODS FOR THROUGH SUBSTRATE VIA TEST

Номер: US20190109057A1
Автор: Bunker Layne, Dimitriu Dragos, Hargan Ebrahim H., King Gregory A.
Принадлежит:

A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side of another IC. Electrical signals may be transferred from the back side of one IC to the front side of the same IC by means of through substrate vias (TSVs), which may include through silicon vias. Electronic apparatus, systems, and methods may operate to test and/or replace defective TSVs. Additional apparatus, systems and methods are disclosed. 1. (canceled)2. A method of testing a memory structure , comprising:in response to initiation of a test process, applying test signal to a first through substrate via (TSV) stack extending vertically though multiple memory die, the multiple memory die vertically stacked with one another, and each of the multiple memory die comprising multiple TSVs respectively aligned with corresponding TSVs of other memory die to form respective TSV stacks of serially connected TSVs extending through multiple memory die;measuring a property of the TSV stack in response to the test signal.3. The method of claim 2 , wherein applying the test signal comprises flowing at a current claim 2 , and wherein measuring the property comprises measuring resistance of the first TSV stack in response to the current flow through the TSV stack.4. The method of claim 3 , wherein applying the test signal comprises applying incremental steps of current to the first TSV stack.5. The method of claim 3 , wherein measuring resistance of the first TSV stack in response to current flow through the first TSV stack is performed through use of at least one sense amp on one of the vertically stacked memory die.6. The method of claim 5 , wherein a current flow through a reference resistance is coupled to the at least one sense amp.7. The method of claim 2 , wherein applying the test signal comprises an oscillating signal claim 2 , and wherein measuring the property comprises measuring the resistance-capacitance ( ...

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Номер записи: 94
02-04-2020 дата публикации

METHOD OF TRAINING ARTIFICIAL INTELLIGENCE TO ESTIMATE SENSING VOLTAGES FOR STORAGE DEVICE

Номер: US20200105361A1
Автор: PENG HSIANG-EN, Wu Sheng-Han
Принадлежит:

A method of training artificial intelligence to estimate sensing voltages for a storage device is provided, which includes steps of: supplying initial sensing voltages to memory units; defining various storing states; comparing threshold voltages of the memory units with the initial sensing voltages to classify the memory units; calculating a ratio of the number of the memory units in a strong correct region to the number of in the strong correct region and a weak correct region; calculating a ratio of the number of the memory units in a strong error region to the number of in the strong error region and a weak error region; calculating the number of the memory units in the weak correct and error regions to obtain a histogram parameter; inputting the ratios and parameter to an artificial intelligence neural network; and using machine learning to analyze practical sensing voltages. 1. A method of training artificial intelligence to estimate sensing voltages for a storage device including a plurality of memory units each storing one or more bit values , the method comprising the following steps:(a) supplying a plurality of initial sensing voltages having different voltage values to each of the memory units;(b) defining a plurality of storing states including a strong correct region, a weak correct region, a strong error region and a weak error region;(c) comparing the initial sensing voltages with the threshold voltage of each of the memory units, and accordingly classifying each of the memory units into the strong correct region, the weak correct region, the strong error region or the weak error region;(d) calculating a strong correct ratio of the number of the memory units classified in the strong correct region to the number of the memory units classified in the strong correct region and the weak correct region;(e) calculating a strong error ratio of the number of the memory units classified in the strong error region to the number of the memory units classified in ...

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Номер записи: 95
26-04-2018 дата публикации

HIGH SPEED AND HIGH PRECISION CHARACTERIZATION OF VTSAT AND VTLIN OF FET ARRAYS

Номер: US20180113166A1
Автор: Baer Matthias, Boldt Juergen, Eckhardt Uwe, Fimmel Dirk, Sandig Karl-Heinz
Принадлежит:

The present disclosure relates to circuit structures and, more particularly, to circuit structures which detect high speed and high precision characterization of VTsat and VTlin of FET arrays and methods of manufacture and use. The circuit includes a control loop comprised of a differential amplifier, a plurality of FET arrays, and at least one analog switch enabling selection between a calibration mode and an operation mode. 1. A circuit comprising a control loop comprised of a differential amplifier , a plurality of FET arrays , and at least one analog switch enabling selection between a calibration mode and an operation mode.2. The circuit of claim 1 , further comprising dedicated analog switches and muxes for selection of the plurality of FET arrays and FETs within the plurality of FET arrays.3. The circuit of claim 2 , wherein the plurality of FET arrays are NFET arrays or PFET arrays.4. The circuit of claim 2 , wherein an input to the differential amplifier includes a target voltage VDS and an output voltage VDI of a selected one of the plurality of FET arrays.5. The circuit of claim 4 , wherein the output voltage VDI of the selected one of the plurality of FET arrays is provided as the input to the differential amplifier by operation of an analog switch of the at least one analog switch claim 4 , resulting in a loop system.6. The circuit of claim 5 , wherein an output voltage VGSI of the differential amplifier is supplied as an input voltage to each selected one of the plurality of FET arrays claim 5 , as selected by a control circuit.7. The circuit of claim 6 , wherein the output voltage VGSI is controlled by the target voltage VDS and the output voltage VDI to converge to “0”.8. The circuit of claim 1 , further comprising a current mirror to force a well defined drain current (IDI) to each selected FET of each selected FET array of the plurality of FET arrays.9. The circuit of claim 1 , further comprising an output buffer to drive measured voltage towards ...

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Номер записи: 96
28-04-2016 дата публикации

Memory Programming Methods and Memory Systems

Номер: US20160118119A1
Автор: Adam Johnson, Durai Vishak Nirmal Ramaswamy, Jonathan Strand, Xiaonan Chen
Принадлежит: Micron Technology Inc

Memory programming methods and memory systems are described. One example memory programming method includes first applying a first signal to a memory cell to attempt to program the memory cell to a desired state, wherein the first signal corresponds to the desired state, after the first applying, determining that the memory cell failed to place in the desired state, after the determining, second applying a second signal to the memory cell, wherein the second signal corresponds to another state which is different than the desired state, and after the second applying, third applying a third signal to the memory cell to program the memory cell to the desired state, wherein the third signal corresponds to the desired state. Additional method and apparatus are described.

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Номер записи: 97
18-04-2019 дата публикации

Dram and method for determining binary logic using a test voltage level

Номер: US20190115067A1
Автор: Chung-Hsun Lee, Hsien-Wen Liu
Принадлежит: Nanya Technology Corp

A dynamic random access memory (DRAM) includes a memory array and a control device. The memory array includes a refresh unit. The refresh unit includes a first cell and a second cell. The first cell is configured to store data, and have a programmed voltage level by being programmed. The second cell is configured to have a test voltage level by being programmed in conjunction with the first cell, wherein the first cell and the second cell are controllable by a same row of the memory array. The control device is configured to increase a voltage difference between the programmed voltage level and a standard voltage level for determining binary logic when the test voltage level becomes lower than a threshold voltage level, wherein the threshold voltage level is higher than the standard voltage level.

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Номер записи: 98
18-04-2019 дата публикации

DRAM AND METHOD FOR DETERMINING BINARY LOGIC USING A TEST VOLTAGE LEVEL

Номер: US20190115068A1
Автор: LEE CHUNG-HSUN, Liu Hsien-Wen
Принадлежит:

A dynamic random access memory (DRAM) includes a memory array and a control device. The memory array includes a refresh unit. The refresh unit includes a first cell and a second cell. The first cell is configured to store data, and have a programmed voltage level by being programmed. The second cell is configured to have a test voltage level by being programmed in conjunction with the first cell, wherein the first cell and the second cell are controllable by a same row of the memory array. The control device is configured to increase a voltage difference between the programmed voltage level and a standard voltage level for determining binary logic when the test voltage level becomes lower than a threshold voltage level, wherein the threshold voltage level is higher than the standard voltage level. 1. A dynamic random access memory (DRAM) , comprising: a first cell configured to store data, and have a programmed voltage level by being programmed; and', 'a second cell configured to have a test voltage level by being programmed in conjunction with the first cell,', 'wherein the first cell and the second cell are controllable by a same row of the memory array; and, 'a refresh unit including, 'a memory array includinga control device configured to increase a voltage difference between the programmed voltage level and a standard voltage level for determining binary logic when the test voltage level becomes lower than a threshold voltage level, wherein the threshold voltage level is higher than the standard voltage level;wherein the control device is configured to increase the programmed voltage level by increasing a program voltage for programming the first cell and the second cell when the test voltage level becomes lower than the threshold voltage level.2. The DRAM of claim 1 , wherein the threshold voltage level is a first threshold voltage level claim 1 ,wherein the control device is configured to increase the program voltage to a first program voltage when the test ...

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Номер записи: 99
13-05-2021 дата публикации

ARRAY PLATE SHORT REPAIR

Номер: US20210142862A1
Автор: Fackenthal Richard E., Lovett Simon J.
Принадлежит:

Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. Groups of cells may be operated in different ways depending, for example, on a relationship between cell plates of the group of cells, pages of cells, and/or sections of cells. Cells may be selected in pairs or in larger multiples in order to accommodate an electric current relationship (such as a short) between two or more cells within a group, a page, and/or a section. When performing an access based on a smaller page size, a larger page size of cells may be selected to accommodate a short between plates within the smaller page, the larger page, and/or a section of memory that includes the smaller page or the larger page. 1. (canceled)2. A method , comprising:identifying a short between a first cell plate and a second cell plate that is adjacent to the first cell plate, the first cell plate included in a first cell plate group comprising a first plurality of cell plates and the second cell plate included in a second cell plate group comprising a second plurality of cell plates; andactivating, concurrently, a first access line coupled with a first set of ferroelectric memory cells associated with the first cell plate and a second access line coupled with a second set of ferroelectric memory cells associated with the second cell plate based at least in part on identifying the short between the first cell plate and the second cell plate.3. The method of claim 2 , further comprising:identifying that the first cell plate is in a last position in the first cell plate group.4. The method of claim 3 , further comprising:identifying that the second cell plate is in a first position in the second cell plate group.5. The method of claim 2 , wherein the first plurality of cell plates are adjacent and the second plurality of cell plates are adjacent.6. The method of claim 2 , further comprising:identifying a third cell plate included in a third cell plate group; ...

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Номер записи: 100