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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 7629. Отображено 100.
05-01-2012 дата публикации

Output enable signal generation circuit of semiconductor memory

Номер: US20120002493A1
Автор: Hee Jin Byun
Принадлежит: Hynix Semiconductor Inc

An output enable signal generation circuit of a semiconductor memory includes: a latency signal generation unit configured to generate a latency signal for designating activation timing of a data output enable signal in response to a read signal and a CAS latency signal; and a data output enable signal generation unit configured to control the activation timing and deactivation timing of the data output enable signal in response to the latency signal and a signal generated by shifting the latency signal based on a burst length (BL).

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Номер записи: 1
12-01-2012 дата публикации

Semiconductor memory device

Номер: US20120008433A1
Автор: Hyun-Su Yoon, Jong-Chern Lee, Seung-joon Ahn
Принадлежит: Hynix Semiconductor Inc

A semiconductor memory device includes an open-loop-type delay locked loop (DLL) configured to generate a clock signal locked by reflecting a first delay amount which actually occurs in a data path and a second delay amount which is required for locking the clock signal, a latency control unit configured to shift an inputted command according to a latency code value corresponding to the first delay amount and latency information, and output the shifted command, and an additional delay line configured to delay the shifted command according to a delay code value corresponding to the second delay amount, and output the command of which operation timing is controlled.

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Номер записи: 2
26-01-2012 дата публикации

Dynamic impedance control for input/output buffers

Номер: US20120019282A1
Автор: Bruce Millar
Принадлежит: Mosaid Technologies Inc

A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an “on” output is to be generated, and the pull-up network is configured to produce a calibrated drive impedance when an “off” output is to be generated. In termination mode, the pull-up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance respectively such that together, they form a split termination.

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Номер записи: 3
26-01-2012 дата публикации

Memory system with delay locked loop (dll) bypass control

Номер: US20120020171A1
Автор: Kevin C. Gower, Kyu-Hyoun Kim, Lisa C. Gower, Warren E. Maule
Принадлежит: International Business Machines Corp

A memory system with delay locked loop (DLL) bypass control including a method for accessing memory that includes receiving a memory read command at a memory device. The memory device is configured to operate in a DLL off-mode to bypass a DLL clock as input to generating a read clock. A DLL power-on command is received at the memory device and in response to receiving the DLL power-on command a DLL initialization process is performed at the memory device. The memory read command is serviced at the memory device operating in the DLL off-mode, the servicing overlapping in time with performing the DLL initialization process. The memory device is configured to operate in a DLL on-mode to utilize the DLL clock as input to generating the read clock in response to a specified period of time elapsing. The specified period of time is relative to receiving the DLL power-on command.

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Номер записи: 4
16-02-2012 дата публикации

Memory systems and memory modules

Номер: US20120042204A1
Автор: Michael John Sebastian Smith, Suresh Natarajan Rajan
Принадлежит: Google LLC

One embodiment of the present invention sets forth a memory module that includes at least one memory chip, and an intelligent chip coupled to the at least one memory chip and a memory controller, where the intelligent chip is configured to implement at least a part of a RAS feature. The disclosed architecture allows one or more RAS features to be implemented locally to the memory module using one or more intelligent register chips, one or more intelligent buffer chips, or some combination thereof. Such an approach not only increases the effectiveness of certain RAS features that were available in prior art systems, but also enables the implementation of certain RAS features that were not available in prior art systems.

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Номер записи: 5
15-03-2012 дата публикации

Semiconductor memory device

Номер: US20120063206A1
Автор: Kazuma Furutani, Yutaka Shionoiri
Принадлежит: Semiconductor Energy Laboratory Co Ltd

An object is to provide a semiconductor memory device capable of copying memory data without using an external circuit. The semiconductor memory device includes a bit line to which first terminals of a plurality of memory cells are connected in common; a pre-charge circuit which is connected to the bit line and pre-charges the bit line with a specific potential in data reading; a data holding circuit comprising a capacitor which temporarily holds data read out from the memory cell or data which is written to the memory cell; and an inverted data output circuit which outputs inverted data of data held in the data holding circuit to the bit line. The inverted data output circuit includes a means for controlling output of inverted data of data held in the data holding circuit.

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Номер записи: 6
15-03-2012 дата публикации

System and method of page buffer operation for memory devices

Номер: US20120066442A1
Автор: Hakjune Oh, Hong Beom Pyeon, Jin-Ki Kim
Принадлежит: Mosaid Technologies Inc

Systems and methods are provided for using page buffers of memory devices connected to a memory controller through a common bus. A page buffer of a memory device is used as a temporary cache for data which is written to the memory cells of the memory device. This can allow the memory controller to use memory devices as temporary caches so that the memory controller can free up space in its own memory.

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Номер записи: 7
26-04-2012 дата публикации

Data output buffer and memory device

Номер: US20120099383A1
Автор: Jin-Il Lee, Kwang-Il Park, Seung-Jun Bae, Si-Hong Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A data output buffer includes a driving unit and a control unit. The driving unit selectively performs a termination operation that provides a termination impedance to a transmission line coupled to an external pin, and a driving operation that provides a drive impedance to the transmission line while outputting read data. The control unit adjusts a value of the termination impedance and a value of the drive impedance based on an output voltage at the external pin during a termination mode, and controls the driving unit to selectively perform one of the termination operation and the driving operation during a driving mode.

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Номер записи: 8
17-05-2012 дата публикации

Semiconductor memory device and method of controlling the same

Номер: US20120120739A1
Автор: Koichi Nishimura, Kotoku Sato, Shinya Fujioka, Tomohiro Kawakubo
Принадлежит: Fujitsu Semiconductor Ltd

An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

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Номер записи: 9
12-07-2012 дата публикации

Column address strobe write latency (cwl) calibration in a memory system

Номер: US20120176850A1
Автор: Lydia M. Do, William M. Zevin
Принадлежит: International Business Machines Corp

Column address strobe write latency (CWL) calibration including a method for calibrating a memory system. The method includes entering a test mode at a memory device and measuring a CWL at the memory device. A difference between the measured CWL and a programmed CWL is calculated. The calculated difference is transmitted to a memory controller that uses the calculated difference for adjusting a timing delay to match the measured CWL.

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Номер записи: 10
30-08-2012 дата публикации

Utilizing two algorithms to determine a delay value for training ddr3 memory

Номер: US20120218841A1
Автор: Brandon L. Hunt
Принадлежит: LSI Corp

A method for training an electronic memory may include receiving a first delay value and a second delay value. The first delay value and the second delay value may be associated with a first data strobe indicating when to sample data on a first memory lane of the electronic memory. The method may also include determining a difference between the first delay value and the second delay value. The method may further include receiving a third delay value associated with a second data strobe indicating when to sample data on a second memory lane of the electronic memory. The method may also include determining a fourth delay value for the second memory lane of the electronic memory utilizing the third delay value and the determined difference between the first delay value and the second delay value.

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Номер записи: 11
13-09-2012 дата публикации

Semiconductor memory device and methods thereof

Номер: US20120230125A1
Автор: Nak-Won Heo
Принадлежит: SAMSUNG ELECTRONICS CO LTD

According to example embodiments, a semiconductor memory device includes a memory cell array, a multi-purpose register, a data output circuit, and a mode register. The memory cell array is configured to store data. The multi-purpose register is configured to store a data pattern. The data output circuit is configured to output the stored data during a first output mode and output the stored data pattern during a second output mode. The mode register is configured to set the first or second output mode according to a logic level of a portion of a content of the mode register.

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Номер записи: 12
04-10-2012 дата публикации

Semiconductor memory and semiconductor memory control method

Номер: US20120250425A1
Автор: Katsumi Abe, Masahiro Yoshihara
Принадлежит: Individual

According to one embodiment, the semiconductor memory includes a memory cell array which includes memory cells to store data, a buffer circuit which includes latches, each of the latches including transistors as control elements and a flip-flop, and a control circuit which turns off the transistors to deactivate one or more of the latches.

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Номер записи: 13
22-11-2012 дата публикации

Compensating for jitter during ddr3 memory delay line training

Номер: US20120296598A1
Автор: Carl E. Gygi, Craig R. Chafin, William J. Schmitz
Принадлежит: LSI Corp

A method for compensating for jitter during DDR3 delay line training may include using a computer or processor to perform the steps of executing a plurality of tests for each one of a plurality of delay values for an interconnect delay between a Double-Data-Rate Three (DDR3) memory controller and a DDR3 Synchronous Dynamic Random Access Memory (SDRAM); accumulating a plurality of test results for each plurality of tests for each one of the plurality of delay values; determining a plurality of final test results, where each final test result is associated with an accumulated plurality of test results; and determining a working window edge for the interconnect delay between the DDR3 memory controller and the DDR3 SDRAM utilizing the plurality of final test results.

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Номер записи: 14
29-11-2012 дата публикации

Advanced memory device having improved performance, reduced power and increased reliability

Номер: US20120300563A1
Автор: Charles A. Kilmer, Daniel M. Dreps, George L. Chiu, Hillery C. Hunter, Kevin C. Gower, Kyu-Hyoun Kim, Paul W. Coteus, Warren E. Maule
Принадлежит: International Business Machines Corp

An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

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Номер записи: 15
13-12-2012 дата публикации

Semiconductor memory device and method of driving semiconductor memory device

Номер: US20120314513A1
Автор: Yoshiyuki Kurokawa
Принадлежит: Semiconductor Energy Laboratory Co Ltd

A semiconductor memory device includes a memory portion that includes i (i is a natural number) sets each including j (j is a natural number of 2 or larger) arrays each including k (k is a natural number of 2 or larger) lines to each of which a first bit column of an address is assigned in advance; a comparison circuit; and a control circuit. The i×j lines to each of which a first bit column of an objective address is assigned in advance are searched more than once and less than or equal to j times with the use of the control circuit and a cache hit signal or a cache miss signal output from the selection circuit. In such a manner, the line storing the objective data is specified.

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Номер записи: 16
20-12-2012 дата публикации

Low voltage sensing scheme having reduced active power down standby current

Номер: US20120320687A1
Автор: Tae Kim
Принадлежит: Individual

A low voltage sensing scheme reduces active power down standby leakage current in a memory device. A clamping device or diode is used between a Psense amplifier control line (e.g. ACT) and Vcc and/or between an Nsense amplifier control line (e.g. RNL*) and Vss (ground potential). The clamping diode is not enabled during normal memory operations, but is turned on during active power down mode to reduce leakage current through ACT and/or RNL* nodes. The clamping device connected to the ACT node may reduce the voltage on the ACT line during power down mode, whereas the clamping device connected to the RNL* node may increase the voltage on the RNL* line during power down mode to reduce sense amplifier leakage current through these nodes. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

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Номер записи: 17
10-01-2013 дата публикации

Semiconductor device, adjustment method thereof and data processing system

Номер: US20130010515A1
Автор: Chikara Kondo, Naohisa Nishioka
Принадлежит: Elpida Memory Inc

A method includes preparing a chip-stack structure in which a first memory chip is stacked over a first main surface of a second memory chip, data electrodes of the first and second memory chips being electrically connected and a data signal outputted from the data electrode of the first memory chip being conveyed on a side of the second main surface of the second memory chip, accessing the first memory chip so that the data signal is outputted from the first memory chip and appears on the side of the second main surface of the second memory chip in first access time, accessing the second memory chip so that a data signal is outputted and appears on the side of the second main surface of the second memory chip in second access time, and setting output timing adjustment information into at least one of the first and second memory chips.

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Номер записи: 18
10-01-2013 дата публикации

Memory circuit and word line control circuit

Номер: US20130010531A1
Автор: Shih-Huang Huang
Принадлежит: MediaTek Inc

The invention provides a memory circuit. In one embodiment, the memory circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a memory cell array. The first PMOS transistor is coupled between a first voltage terminal and a first node. The second PMOS transistor is coupled between the first voltage terminal and a second node. The first NMOS transistor is coupled between a third node and a second voltage terminal. The second NMOS transistor is coupled between a fourth node and the second voltage terminal. The memory cell array comprises a plurality of memory cells, at least one comprising a first inverter and a second inverter. A positive power terminal of the first inverter is coupled to the first node, a negative power terminal of the first inverter is coupled to the third node, a positive power terminal of the second inverter is coupled to the second node, and a negative power terminal of the second inverter is coupled to the fourth node.

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Номер записи: 19
21-02-2013 дата публикации

Processor with memory delayed bit line precharging

Номер: US20130044555A1
Автор: Hong-Yi Chen, Jason Sheu, Jason T. Su, Jensen Tjeng, Sehat Sutardja
Принадлежит: MARVELL WORLD TRADE LTD

A processor includes an array of memory cells, a control module, a precharge circuit, and an amplifier module. The control module generates a clock signal at a first rate, reduces the first rate to a second rate for a predetermined period, and adjusts the second rate back to the first rate at an end of the predetermined period. The precharge circuit: based on the first rate, precharges first bit lines connected to memory cells in a first row of the array of memory cells; based on the second rate, refrains from precharging the first bit lines; and precharges the first bit lines subsequent to the end of the predetermined period. The amplifier module: based on the first rate, access first instructions stored in the first row; and based on the second rate, accesses second instructions stored in the first row or a second row of the array.

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Номер записи: 20
28-02-2013 дата публикации

High speed multiple memory interface i/o cell

Номер: US20130049799A1
Автор: Cheng-Gang Kong, Dharmesh Bhakta, Hong-Him Lim, Todd Randazzo
Принадлежит: LSI Corp

A calibration circuit includes an amplifier, a current steering digital-to-analog converter (DAC), a comparator, a slew calibration network, and an on-die termination (ODT) network. The amplifier generally has a first input, a second input, and an output. The first input generally receives a reference signal. The current steering digital-to-analog converter (DAC) generally has a first input coupled to the output of the amplifier, a first output coupled to the second input of the amplifier, and a second output coupled to a circuit node. The comparator generally has a first input receiving the reference signal, a second input coupled to the circuit node, and an output at which an output of the calibration circuit may be presented. The slew calibration network is generally coupled to the circuit node and configured to adjust a slew rate of the calibration circuit. The on-die termination (ODT) network is generally coupled to the circuit node.

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Номер записи: 21
02-05-2013 дата публикации

Semiconductor system including semiconductor device

Номер: US20130107641A1
Автор: Jeong Hun Lee
Принадлежит: Hynix Semiconductor Inc

A semiconductor system includes a controller configured to apply code signals for setting levels of a reference voltage and data, and to receive output data. The semiconductor system also includes a semiconductor device configured to receive the data for the respective levels of the reference voltage set according to the code signals, to compare the reference voltages with the data to generate new data, to store the new data as internal data, and to process the stored internal data to output as the output data.

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Номер записи: 22
02-05-2013 дата публикации

Semiconductor memory device and operating method thereof

Номер: US20130111101A1
Автор: Seok-Cheol Yoon
Принадлежит: Hynix Semiconductor Inc

A semiconductor memory device includes a path control unit configured to activate an address transmission path corresponding to a bank address, an address providing unit configured to provide a memory address to the path control unit in response to an active signal, and a plurality of memory banks each configured to receive the memory address provided through the corresponding address transmission path of the path control unit, wherein the bank address corresponds to a memory bank of the plurality of memory banks.

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Номер записи: 23
18-07-2013 дата публикации

Memory system capable of calibrating output voltage level of semiconductor memory device and method of calibrating output voltage level of semiconductor memory device

Номер: US20130182513A1
Автор: Yong-Cheol Bae, Yoon-Joo EOM, Young-Chul Cho, Young-Jin Jeon
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Provided are a semiconductor memory device and a memory system including the same, which may calibrate a level of an output voltage in consideration of channel environment and a mismatch in on-die termination (ODT) resistance of a memory controller. The memory system includes a memory controller and a semiconductor memory device. The semiconductor memory device is configured to generate a reference voltage based on driving information of the memory controller, and calibrate an output voltage level based on a reference voltage when the semiconductor memory device is electrically connected to the memory controller.

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Номер записи: 24
29-08-2013 дата публикации

Refresh request queuing circuitry

Номер: US20130227212A1
Автор: Robert J. Proebsting
Принадлежит: Intellectual Ventures I LLC

An apparatus and system associated with memory are disclosed herein. In various embodiments, an apparatus may include first circuitry to determine a number of queued pending refresh requests for a memory bank based on a comparison of a count from a refresh-request counter to a count from a refresh-address counter; and second circuitry to set a refresh flag in response to a determination that the number of queued pending refresh requests exceeds a predetermined number. Other embodiments may be disclosed and/or claimed.

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Номер записи: 25
12-09-2013 дата публикации

Data write training method

Номер: US20130235683A1
Автор: Kwang-Il Park, Seung-Jun Bae, Tae-Young Oh, Young-Soo Sohn
Принадлежит: Individual

Embodiments may be directed to a method of operating a semiconductor device, the method including receiving a first write training command, receiving a first write data responsive to the first write training command through a first data line, and transmitting the first write data through a second data line. Transmitting the first write data is performed without an additional training command.

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Номер записи: 26
19-09-2013 дата публикации

Signal tracking in write operations of memory cells

Номер: US20130242678A1
Автор: Bing Wang, Kuoyuan (Peter) Hsu, Young Suk Kim
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

In a method, a first edge of a first tracking signal in a first direction of a memory array is generated. A first edge of a second tracking signal in a second direction of the memory array is generated. A first edge of a write-timing control signal is generated based on a slower edge of the first edge the first tracking signal and of the first edge of the second tracking signal. The first edge of the write-timing control signal is used to generate a second edge of the second tracking signal.

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Номер записи: 27
05-12-2013 дата публикации

Semiconductor memory device, and method of controlling the same

Номер: US20130326247A1
Автор: Koichi Nishimura, Kotoku Sato, Shinya Fujioka, Tomohiro Kawakubo
Принадлежит: Fujitsu Semiconductor Ltd

A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.

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Номер записи: 28
09-01-2014 дата публикации

Apparatuses and methods for adjusting a path delay of a command path

Номер: US20140010025A1
Автор: Venkat Bringivijayaraghavan
Принадлежит: Micron Technology Inc

Apparatuses and method for adjusting a path delay of a command path are disclosed. In an example apparatus, a command path configured to provide a command from an input to an output includes an adjustable delay. The adjustable delay is configured to add delay to the command path delay, wherein the delay of the adjustable delay is based at least in part on a phase relationship between a feedback signal responsive to the command propagating through the command path and a clock signal. An example method includes configuring a command path to add delay to a command path delay to provide an internal write command signal to perform a write operation on write data corresponding to the internal write command, and propagating the write data corresponding to the internal write command through a data path without further delaying the write data to match the command path delay.

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Номер записи: 29
09-01-2014 дата публикации

Dynamic memory performance throttling

Номер: US20140013070A1
Автор: Brian Toronyi, Kenneth Shoemaker
Принадлежит: Intel Corp

Dynamic memory performance throttling. An embodiment of a memory device includes a memory stack including coupled memory elements; the memory elements including multiple ranks, the plurality of ranks including a first rank and a second rank, and a logic device including a memory controller. The memory controller is to determine an amount of misalignment between data signals relating to a read request for the first rank and a read request for the second rank, and, upon determining that misaligment between the first rank and the second rank is greater than a threshold, the memory controller is to insert a time shift between a data signal for the first rank and a data signal for the second rank.

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Номер записи: 30
30-01-2014 дата публикации

Memory Component with Pattern Register Circuitry to Provide Data Patterns for Calibration

Номер: US20140032830A1
Автор: Craig E. Hampel, Ely K. Tsern, Frederick A. Ware, Richard S. Perego, Stefanos Sidiropoulos
Принадлежит: RAMBUS INC

A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration.

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Номер записи: 31
20-02-2014 дата публикации

Cas latency setting circuit and semiconductor memory apparatus including the same

Номер: US20140050034A1
Автор: Seong Jun Lee
Принадлежит: SK hynix Inc

A semiconductor memory apparatus includes a CAS latency setting circuit configured to change an initially-set CAS latency value in response to control signal pulses which are sequentially applied, during a test mode without changing settings of a mode register set during each test.

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Номер записи: 32
20-02-2014 дата публикации

Memory device with a logical-to-physical bank mapping cache

Номер: US20140052912A1
Автор: Chien-Hsien Wu, Mohammad Issa, Weihuang Wang
Принадлежит: Broadcom Corp

A memory device with a logical-to-physical (LTP) bank mapping cache that supports multiple read and write accesses is described herein. The memory device allows for at least one read operation and one write operation to be received during the same clock cycle. In the event that the incoming write operation is not blocked by the at least one read operation, data for that incoming write operation may be stored in the physical memory bank corresponding to a logical memory bank that is associated with the incoming write operation. In the event that the incoming write operation is blocked by the at least one read operation, then data for that incoming write operation may be stored in an unmapped physical bank that is not associated with any logical memory bank.

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Номер записи: 33
20-02-2014 дата публикации

Multi-ported memory with multiple access support

Номер: US20140052913A1
Автор: Chien-Hsien Wu, Weihuang Wang
Принадлежит: Broadcom Corp

A multi-ported memory that supports multiple read and write accesses is described herein. The multi-ported memory may include a number of read/write ports that is greater than the number of read/write ports of each memory bank of the multi-ported memory. The multi-ported memory allows for at least one read operation and at least one write operation to be received during the same clock cycle. In the event that an incoming write operation is blocked by the at least one read operation, data for that incoming write operation may be stored in a cache included in the multi-port memory. That cache is accessible to both write operations and read operations. In the event than the incoming write operation is not blocked by the at least one read operation, data for that incoming write operation is stored in the memory bank targeted by that incoming write operation.

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Номер записи: 34
06-03-2014 дата публикации

Integrated circuit

Номер: US20140064013A1
Автор: Jae-Bum Ko, Sang-Jin Byeon
Принадлежит: SK hynix Inc

An integrated circuit includes a plurality of mode register set (MRS) setting blocks configured to generate a plurality of additive latency (AL) codes in response to an MRS signal, and a decoding unit configured to decoding the plurality of AL codes in response to a stack information signal to generate a plurality of AL setting signals.

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Номер записи: 35
02-01-2020 дата публикации

One-die trermination control for memory systems

Номер: US20200004436A1
Автор: Gang Yan, Leechung Yiu, Lizhi Jin, Robert Xi Jin, Yibo Jiang
Принадлежит: Montage Technology Shanghai Co Ltd

A memory system, comprising: a first plurality of memory ranks each having multiple memory cells; a second plurality of local controllers each coupled between one or more of the first plurality of memory ranks and a memory controller, the memory controller being configured to provide to a target local controller of the second plurality of local controllers, out of a first plurality of chip select (CS) signals, a target access CS signal enabling target access to a target memory rank of the first plurality of memory ranks coupled to the target local controller, and provide to the second plurality of local controllers, later than the target access CS signal, a command and address (CA) signal for addressing and accessing the multiple memory cells of the target memory rank; and wherein the target local controller is configured to generate, in response to receiving the target access CS signal, a target CA on-die termination (ODT) instruction switching on target CA ODT at its CA input at least for a period when the CA signal is being received from the memory controller.

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Номер записи: 36
02-01-2020 дата публикации

MEMORY DEVICE WITH DYNAMIC PROGRAM-VERIFY VOLTAGE CALIBRATION

Номер: US20200004440A1
Автор: Koudele Larry J., Liikanen Bruce A.
Принадлежит:

A memory system includes a memory array including a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: determine a target profile including distribution targets, wherein each of the distribution targets represent a program-verify target corresponding to a logic value for the memory cells, determine a feedback measure based on implementing a processing level for processing data, and dynamically adjust the program-verify target according to the feedback measure. 1. A memory device , comprising:a memory array including a plurality of memory cells; and determine a target profile including distribution targets, wherein each of the distribution targets represents a program-verify target corresponding to a desired pattern of processing levels for a logic value for the memory cells,', 'determine a feedback measure based on implementing a processing level for processing data, and', 'dynamically adjust the program-verify target according to the feedback measure., 'a controller coupled to the memory array, the controller configured to2. The memory device of wherein the controller is further configured to determine the feedback measure based on an error count associated with a read level voltage.3. The memory device of wherein the controller is further configured to dynamically adjust the program-verify target based on adjusting separations between adjacent program-verify targets.4. The memory device of wherein the controller is further configured to dynamically adjust the program-verify target balancing an error measure across multiple page types for the memory cells.5. The memory device of wherein the controller is further configured to dynamically adjust the program-verify target based on a net-zero change for the target profile and across the program-verify target.6. The memory device of wherein:the program-verify target controls resulting distribution of actual processing levels associated with the logic value for the ...

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Номер записи: 37
07-01-2016 дата публикации

Independently addressable memory array address spaces

Номер: US20160005447A1
Автор: Troy A. Manning
Принадлежит: Micron Technology Inc

Examples of the present disclosure provide devices and methods for accessing a memory array address space. An example memory array comprising a first address space comprising memory cells coupled to a first number of select lines and to a number of sense lines and a second address space comprising memory cells coupled to a second number of select lines and to the number of sense lines. The first address space is independently addressable relative to the second address space.

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Номер записи: 38
03-01-2019 дата публикации

Processors, methods, and systems for a configurable spatial accelerator with transactional and replay features

Номер: US20190004945A1
Автор: Kent D. GLOSSOP, Kermin FLEMING, Samantika S. Sury, Simon C. Steely, Jr.
Принадлежит: Intel Corp

Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In an embodiment, a processor includes a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements are to perform an atomic operation when an incoming operand set arrives at the plurality of processing elements.

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Номер записи: 39
07-01-2021 дата публикации

Periodic calibrations during memory device self refresh

Номер: US20210005245A1
Автор: Bill Nale, Christopher E. Cox
Принадлежит: Intel Corp

A memory device is described. The memory device includes logic circuitry to perform calibrations of resistive network terminations and data drivers of the memory device while the memory device is within a self refresh mode.

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Номер записи: 40
04-01-2018 дата публикации

Method of programming semiconductor memory device

Номер: US20180005696A1
Автор: Eun Mee KWON, Ji Seon Kim, Sang Tae Ahn
Принадлежит: SK hynix Inc

In a method of programming a semiconductor memory device, during a standby period, a standby voltage is applied to word lines coupled to a plurality of memory cells included in a selected memory cell string, and, during a first program period, a first pre-bias voltage is applied to a word line coupled to at least one of programmed memory cells of the selected memory cell string. The first pre-bias voltage is greater than the standby voltage.

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Номер записи: 41
02-01-2020 дата публикации

DATA STROBE CALIBRATION

Номер: US20200005840A1
Автор: "DAlessandro Ferdinando", Castaldo Andrea, Castellano Cristiano, Di Martino Erminio, Giaccio Claudio, Mastrangelo Raffaele, Pascale Ferdinando
Принадлежит:

Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit. 1. A system comprising:a host device configured to receive read data from an embedded MultiMediaCard (eMMC) device over data lines of a communication interface and a data strobe signal from the eMMC device over a data strobe line of the communication interface,wherein the host device is configured to determine a timing relationship between the data strobe signal and an internal clock signal in a calibration mode to align the read data for sampling, andwherein the host device is configured to receive read data from the eMMC device over the data strobe line in a data mode separate from calibration mode.2. (canceled)3. The system of claim 1 , wherein the host device includes:data pins configured to receive read data from the eMMC device over the data lines of the communication interface; anda data strobe pin configured to receive the data strobe signal from the eMMC device over a data strobe line of the communication interface,wherein the host device is configured to receive read data from the eMMC device over at the data pins in both the calibration mode and the data mode.4. The system of claim 3 , wherein the host device is configured to provide a command to the eMMC device to provide read data over the data strobe line of the communication interface in the data mode.5. The system of claim 3 , wherein the data pins consist of a number (N) of data pins claim 3 , and wherein the host is configured to receive read data from the eMMC device using the N data pins and the data strobe pin claim 3 , collectively N+1 pins claim 3 , in the data mode.6. The system of ...

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Номер записи: 42
02-01-2020 дата публикации

MEMORY SYSTEM AND OPERATING METHOD THEREOF

Номер: US20200005888A1
Автор: KIM Hyungsup, WON Hyung-Sik
Принадлежит:

A memory system includes a memory device and a controller. The memory device includes a memory cell array including a normal memory cell area and a redundancy memory cell area, the redundancy memory cell area having a replacement memory cell region and a reserved memory cell region; a register suitable for generating a first signal indicating existence of the reserved memory cell region; and a fuse unit suitable for activating the reserved memory cell region based on the first signal. The controller assigns an address for accessing a reserved memory cell of the reserved memory cell region based on the first signal. A replacement memory cell in the replacement memory cell region replaces a failed memory cell in the normal memory cell region, and the reserved memory cell in the reserved memory cell region remains without replacing any failed memory cell in the normal memory cell region. 1. A memory system comprising:a plurality of memory devices including first and second memory devices, the first memory device having a memory cell array and a device controller, the memory cell array including a normal memory cell area and a redundancy memory cell area, the device controller being configured to generate a first signal associated with the redundancy memory cell area; anda memory controller provided external to the first memory device and configured to enable accessing of a redundancy memory cell of the redundancy memory cell area of the first memory device based on the first signal.2. The memory system of claim 1 , wherein the memory controller is configured to assign a first address for accessing the redundancy memory cell and control the first memory device to activate the redundancy memory cell based on the first address.3. The memory system of claim 2 , wherein the first memory device further comprises a fuse unit configured to activate the redundancy memory cell based on the first address.4. The memory system of claim 3 , wherein the first signal is provided to ...

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Номер записи: 43
03-01-2019 дата публикации

SEMICONDUCTOR STORAGE DEVICE

Номер: US20190005998A1
Автор: MATSUOKA Fumiyoshi
Принадлежит: Toshiba Memory Corporation

A semiconductor storage device includes a first bank that includes a first memory cell group and writes data into the first memory cell group upon receipt of a first command, a second bank that includes a second memory cell group and writes data into the second memory cell group upon receipt of the first command, and a delay controller that issues the first command for the first bank upon receipt of a second command, and issues the first command for the second bank after an interval of at least a first period. 1a first bank that includes a first memory cell group and writes data into the first memory cell group upon receipt of a first command;a second bank that includes a second memory cell group and writes data into the second memory cell group upon receipt of the first command; anda delay controller that issues the first command for the first bank upon receipt of a second command, and issues the first command for the second bank after an interval of at least a first period.. A semiconductor storage device comprising: This application is a Continuation application of U.S. application Ser. No. 15/264,545, filed Sep. 13, 2016, which claims the benefit of U.S. Provisional Application No. 62/309,837, filed Mar. 17, 2016. The entire contents of both the above-identified applications are incorporated herein by reference.Embodiments described herein relate generally to a semiconductor storage device.A magnetic random access memory (MRAM) is a memory device employing a magnetic element having a magnetoresistive effect as a memory cell for storing information, and is receiving attention as a next-generation memory device characterized by its high-speed operation, large storage capacity, and non-volatility. Research and development have been advanced to use the MRAM as a replacement for a volatile memory, such as a dynamic random access memory (DRAM) or a static random access memory (SRAM). In order to lower the development cost and enable smooth replacement, it is desirable ...

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Номер записи: 44
20-01-2022 дата публикации

Write broadcast operations associated with a memory device

Номер: US20220020424A1
Автор: Dmitri A. Yudanov, Shanky Kumar Jain
Принадлежит: Micron Technology Inc

Methods, systems, and devices related to write broadcast operations associated with a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may enable write broadcast operations. A write broadcast may occur from one or more signal development components or from one or more multiplexers to multiple locations of the memory array.

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Номер записи: 45
11-01-2018 дата публикации

Memory controller that uses a specific timing reference signal in connection with a data brust following a specified idle period

Номер: US20180011805A1
Автор: Giovannini Thomas J., Shaeffer Ian
Принадлежит:

Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read command which specifies that a memory device output data accessed from a memory core. This read command contains information which specifies whether the memory device is to commence outputting of a timing reference signal prior to commencing outputting of the data. The memory controller receives the timing reference signal if the information specified that the memory device output the timing reference signal. The memory controller subsequently samples the data output from the memory device based on information provided by the timing reference signal output from the memory device. 1. A method of operation in a memory controller , the method comprising:transmitting a read command which specifies that a memory device output data accessed from a memory core via a data bus, the data to be output by the memory device as a burst of data words;provided that the burst of data words follows a period of specified duration during which the memory device was not exchanging data with the memory controller, transmitting information to the memory device which specifies whether the memory device is to commence outputting of a specified timing reference signal prior to commencing outputting of the burst of data words; andreceiving the timing reference signal if the information specified that the memory device output the timing reference signal.2. The method of claim 1 , wherein transmitting the information to the memory device comprises programming a register of the memory device to cause the outputting of the specified timing reference signal prior to commencing outputting of the burst of data words.3. The method of claim 1 , wherein the timing reference signal comprises a toggling pattern having at least four bits.4. The method of claim 3 , wherein the method further comprises receiving the toggling pattern at the memory ...

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Номер записи: 46
10-01-2019 дата публикации

INJECT DELAY TO SIMULATE LATENCY

Номер: US20190012095A1
Автор: Cherkasova Ludmila, MagaIhaes Guilherme de Campos, Volos Haris
Принадлежит:

Techniques for injecting a delay to simulate latency are provided. In one aspect, it may be determined that a current epoch should end. A delay may be injected. The delay may simulate the latency of non-volatile memory access during the current epoch. The current epoch may then end. A new epoch may then begin. 1. A non-transitory processor readable medium containing instructions thereon which when executed by a processor cause the processor to:determine that a current epoch should end;inject a delay, the delay simulating latency of non-volatile memory access during the current epoch;end the current epoch; andbegin a new epoch.2. The medium of claim 1 , wherein determining that the current epoch should end further comprises instructions to:periodically determine how long the current epoch has lasted; anddetermine the current epoch should end when the current epoch has exceeded a maximum epoch length threshold.3. The medium of claim 1 , wherein determining that the current epoch should end further comprises instructions to;determine that a synchronization primitive has been invoked; andinjecting the delay prior to completion of the synchronization primitive.4. The medium of claim 3 , wherein determining that the current epoch should end further comprises instructions to:determine that a synchronization primitive has been invoked;determine if the current epoch has exceeded a minimum epoch length threshold; andinjecting the delay prior to completion of the synchronization primitive when the minimum epoch length threshold has been exceeded.5. The medium of claim 1 , wherein injecting a delay further comprises instructions to;determine a number of processor stall cycles attributable to memory access; andcompute the delay based on the number of processor stall cycles and the latency of the simulated non-volatile memory.6. The medium of wherein determining the number of processor stall cycles comprises instructions to:retrieve at least one processor performance counter ...

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Номер записи: 47
10-01-2019 дата публикации

APPARATUSES AND METHODS FOR MEMORY OPERATIONS HAVING VARIABLE LATENCIES

Номер: US20190012173A1
Автор: Kindworth Andre, Lemarie Sebastien, Mirichigni Graziano, Porzio Luca, Tan Chee Weng, Villa Corrado
Принадлежит: MICRON TECHNOLOGY, INC.

Apparatuses and methods for performing memory operations are described. An example apparatus includes a memory operation controller. The memory operation controller is configured to receive memory instructions and decode the same to provide internal signals for performing memory operations for the memory instructions. The memory operation controller is further configured to provide information indicative of a time for a variable latency period of a memory instruction during the variable latency period. In an example method, a write instruction and an address to which write data is to be written is received at a memory and an acknowledgement indicative of an end of a variable latency period for the write instruction is provided. After waiting a variable bus turnaround after the acknowledgement, write data for the write instruction is received. 1. An apparatus comprising: providing information indicative of a duration of a variable latency period; and', 'waiting a programmable bus turnaround time after the duration of the variable latency period, wherein the programmable bus turnaround time is programmed in the memory., 'a memory configured to receive a memory instruction from a memory controller and perform a memory operation responsive thereto, wherein performing the memory operation comprises the memory2. The apparatus of claim 1 , wherein the memory is configured to provide information indicative of the duration of the variable latency period on one or more input/output signal lines.3. The apparatus of claim 1 , wherein the memory is configured to provide an acknowledgment on an input/output signal line indicative of an end of the variable latency period represented by a change in logic level from a first logic level to a second logic level.4. The apparatus of claim 1 , wherein the memory is configured to provide information indicative of the duration of the variable latency period including a wait state.5. The apparatus of claim 4 , wherein the memory is ...

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Номер записи: 48
09-01-2020 дата публикации

MEMORY CONTROLLER WITH TRANSACTION-QUEUE-DEPENDENT POWER MODES

Номер: US20200012332A1
Автор: Fuller Andrew M., Palmer Robert E., Poulton John W., Ware Frederick A.
Принадлежит:

A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices. 120-. (canceled)21. A memory controller component comprising:a clock transmitter to transmit a first clock signal to a dynamic random access memory device (DRAM), the DRAM having (i) command/address receive circuitry to receive read commands and write commands, (ii) read-data transmit circuitry to transmit, in response to the read commands, read data using the first clock signal, and (iii) write-data receive circuitry to sample, in response to the write commands, write data using the first clock signal;a command/address transmitter to transmit the read commands and the write commands to the DRAM in response to a second clock signal;a write-data transmitter to transmit the write data to the DRAM in response to a third clock signal;a read-data receiver to sample the read data transmitted by the DRAM in response to a fourth clock signal; and phase control circuitry to independently offset phases of the third and fourth clock signals relative to the first clock signal and', 'circuitry to generate the second clock signal at a lower frequency than the third and fourth clock signals; and', 'clock-pause circuitry to halt transmission of the first clock signal to the DRAM during a first interval to conserve power and to re- ...

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Номер записи: 49
11-01-2018 дата публикации

MEMORY DEVICE HAVING COMMAND WINDOW GENERATOR

Номер: US20180012638A1
Автор: CHOI Hun-Dae, KANG SUKYONG
Принадлежит:

A memory device including a command window generator is provided. The command window generator is configured to generate a delay signal by converting a delay time between a clock signal input to a write path circuit and a clock signal output to a write path replica circuit into a number of cycles of an internal clock signal, by using the write path circuit and the write path replica circuit, and generate a command window to correspond to a data window using the delay signal. The delay window may correspond to a burst length of write data. 1. A command window generator configured to generate a command window for processing data associated with a command after a certain latency from receipt of the command , the command window generator comprising:a clock freezer circuit configured to receive a first clock signal divided from an input clock signal and generate a second clock signal from the first clock signal, where the second clock signal has a freezing section corresponding to a logic low section of a clock freezing signal;a first circuit configured to receive the second clock signal as an input, and output the second clock signal after a first delay time;a second circuit having the same structure as the first circuit and configured to receive an output of the first circuit as an input, and output a third clock signal after the first delay time; anda delay measure circuit configured to receive the second clock signal and the third clock signal as inputs, generate a delay signal by converting a delay time between the second clock signal and the third clock signal into a number of cycles of the input clock signal, and generate the command window to correspond to a data window of the data using the delay signal.2. The command window generator of claim 1 , wherein the delay measure circuit generates a latency control signal generated at a point in which the delay signal is subtracted from the latency claim 1 , andthe first circuit receives the latency control signal as ...

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Номер записи: 50
11-01-2018 дата публикации

MEMORY COMPONENT WITH PATTERN REGISTER CIRCUITRY TO PROVIDE DATA PATTERNS FOR CALIBRATION

Номер: US20180012643A1
Автор: Hampel Craig E., Perego Richard E., Sidiropoulos Stefanos, Tsern Ely K., Ware Frederick A.
Принадлежит:

A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration. 1. (canceled)2. A controller to control operations of a memory component , the controller comprising: a first command that specifies a first data pattern to be stored in a first register of the memory component;', 'a second command that specifies a second data pattern to be stored in a second register of the memory component; and,', 'a third command to select one of the first data pattern or the second data pattern to be output by the memory component;, 'a first circuit to transmit commands to the memory component, the commands includinga second circuit to receive, from the memory component as a received data pattern, the one of the first data pattern or the second data pattern output by the memory component, as selected by the third command; and,calibration circuitry to based on the received data pattern, adjust a timing of a timing reference signal for sampling data at the second circuit.3. The controller of claim 2 , wherein the commands transmitted by the first circuit include a fourth command that specifies data to be accessed from a memory core of the memory component claim 2 , ...

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Номер записи: 51
10-01-2019 дата публикации

Apparatuses and methods for data movement

Номер: US20190013061A1
Автор: Glen E. Hush
Принадлежит: Micron Technology Inc

The present disclosure includes apparatuses and methods for data movement. An example apparatus includes a memory device that includes a plurality of subarrays of memory cells and sensing circuitry coupled to the plurality of subarrays. The sensing circuitry includes a sense amplifier and a compute component. The memory device includes a latch selectably coupled to a column of the memory cells and configured to store a data value moved from the sensing circuitry. The memory device includes a controller configured to direct movement of the data value from the sensing circuitry to the latch.

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Номер записи: 52
03-02-2022 дата публикации

Electronic device configured to perform an auto-precharge operation

Номер: US20220036930A1
Автор: Woongrae Kim
Принадлежит: SK hynix Inc

An electronic device may include: an input/output control signal generation circuit configured to generate an input control signal and a first output control signal during a write operation, and generate a second output control signal during a write operation with an auto-precharge operation; and a bank address output circuit configured to latch a bank address based on the input control signal, and output the latched bank address as a write bank address for the write operation or a precharge bank address for the auto-precharge operation, based on the first output control signal and the second output control signal.

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Номер записи: 53
03-02-2022 дата публикации

Monitoring and adjusting access operations at a memory device

Номер: US20220036960A1
Автор: Aaron P. Boehm, Mark D. INGRAM, Scott D. VAN DE GRAAFF, Scott E. Schaefer, Todd Jackson Plum
Принадлежит: Micron Technology Inc

Methods, systems, and devices for monitoring and adjusting access operations at a memory device are described to support integrating monitors or sensors for detecting memory device health issues, such as those resulting from device access or wear. The monitoring may include traffic monitoring of access operations performed at various components of the memory device, or may include sensors that may measure parameters of components of the memory device to detect wear. The traffic monitoring or the parameters measured by the sensors may be represented by a metric related to access operations for the memory device. The memory device may use the metric (e.g., along with a threshold) to determine whether to adjust a parameter associated with performing access operations received by the memory device, in order to implement a corrective action.

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Номер записи: 54
21-01-2021 дата публикации

APPARATUSES AND METHODS FOR SIMULTANEOUS IN DATA PATH COMPUTE OPERATIONS

Номер: US20210019048A1
Автор: Hush Glen E., Lea Perry V.
Принадлежит:

The present disclosure includes apparatuses and methods for simultaneous in data path compute operations. An apparatus can include a memory device having an array of memory cells and sensing circuitry selectably coupled to the array. A plurality of shared I/O lines can be configured to move data from the array of memory cells to a first portion of logic stripes and a second portion of logic stripes for in data path compute operations associated with the array. The first portion of logic stripes can perform a first number of operations on a first portion of data moved from the array of memory cells to the first portion of logic stripes while the second portion of logic stripes perform a second number of operations on a second portion of data moved from the array of memory cells to the second portion of logic stripes during a first time period. 2. The system of claim 1 , wherein the controller is further configured to:direct movement of the result of the first operation from the first logic stripe to the second logic stripe of the first portion of logic stripes in response to completion of the first operation.3. The system of claim 1 , wherein the controller is further configured to direct performance of a second operation on the result of the first operation using a second logic stripe of the first portion of logic stripes.4. The system of claim 3 , wherein the controller is further configured tointerrupt performance of the second operation on the second logic stripe of the first portion of logic stripes and direct the result of the first operation to a third logic stripe of the first portion of logic stripes.5. The system of claim 1 , wherein the controller is further configured to:direct movement of a second portion of data from the array to a first logic stripe of a second portion of logic stripes in the data path via the plurality of I/O lines during the first time period.6. The system of claim 5 , wherein the controller is further configured to:direct ...

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Номер записи: 55
16-01-2020 дата публикации

Memory power management

Номер: US20200020361A1
Автор: Jaspal Singh Shah, Sanjeev Kumar Jain
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A memory device includes an array of memory cells, such as SRAM cells, and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit is configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells.

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Номер записи: 56
16-01-2020 дата публикации

Semiconductor storage device

Номер: US20200020379A1
Автор: Fumiyoshi Matsuoka
Принадлежит: Toshiba Memory Corp

A semiconductor storage device includes a first bank that includes a first memory cell group and writes data into the first memory cell group upon receipt of a first command, a second bank that includes a second memory cell group and writes data into the second memory cell group upon receipt of the first command, and a delay controller that issues the first command for the first bank upon receipt of a second command, and issues the first command for the second bank after an interval of at least a first period.

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Номер записи: 57
21-01-2021 дата публикации

Non-volatile memory devices and program methods thereof

Номер: US20210020254A1
Автор: Jinwoo Park, Sang-Wan Nam, Seongjin Kim, Wandong Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A program method of a non-volatile memory device, the non-volatile memory device including a cell string having memory cells stacked perpendicular to a surface of a substrate, the method includes performing a first program phase including programming a first memory cell connected to a first word line and applying a first pass voltage to other word lines above or below the first word line, and performing a second program phase including programming a second memory cell after the first memory cell is completely programmed, the second memory cell being connected to a second word line closer to the substrate than the first word line, applying a second pass voltage to a first word line group below the second word line and applying a third pass voltage to a second word line group above the second word line, the second pass voltage being lower than the third pass voltage.

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Номер записи: 58
22-01-2015 дата публикации

MOBILE DEVICE AND A METHOD OF CONTROLLING THE MOBILE DEVICE

Номер: US20150026398A1
Автор: Kim Ho-Sung
Принадлежит:

A mobile device including: a storage device; a system-on-chip (SOC) including a central processing unit (CPU) and a memory interface configured to access the storage device in response to a request of the CPU; and a working memory including an input/output (I/O) scheduler and a device driver, the I/O scheduler configured to detect real time processing requests and store the real time processing requests in a sync queue, and detect non-real time processing requests and store the non-real time processing requests in an async queue, the device driver configured to adjust the performance of the mobile device based on the number of requests in the sync queue. 1. A mobile device , comprising:a storage device;a system-on-chip (SOC) including a central processing unit (CPU) and a memory interface configured to access the storage device in response to a request of the CPU; anda working memory including an input/output (I/O) scheduler and a device driver,the I/O scheduler configured to detect real time processing requests and store the real time processing requests in a sync queue, and detect non-real time processing requests and store the non-real time processing requests in an async queue,the device driver configured to adjust the performance of the mobile device based on the number of requests in the sync queue.2. The mobile device of claim 1 , wherein when the sync queue and the async queue are empty a low power mode of the mobile device is entered.3. The mobile device of claim 1 , wherein the CPU is a heterogeneous multi-core CPU.4. The mobile device of claim 1 , wherein the working memory includes a dynamic random access memory (DRAM).5. The mobile device of claim 1 , wherein the storage device includes a nonvolatile memory device.6. The mobile device of claim 1 , wherein the synch queue includes a plurality of read requests.7. The mobile device of claim 1 , wherein the async queue includes a plurality of write requests.8. The mobile device of claim 1 , wherein the ...

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Номер записи: 59
25-01-2018 дата публикации

Apparatuses and methods for reducing off state leakage currents

Номер: US20180026622A1
Автор: Pierguido Garofalo
Принадлежит: Micron Technology Inc

Apparatuses and methods for reducing leakage currents during an off state for transistors are described herein. An example apparatus includes a switch having an input node and an output node. The switch is configured to couple a signal on the input to the output node when the switch is in an on state and is further configured to decouple the input and output nodes when the switch is in an off state. The switch includes first and second transistors, and further includes third and fourth transistors. A drain electrode of the first transistor is coupled to a source electrode of the third transistor, a drain electrode of the second transistor is coupled to a source electrode of the fourth transistor, and the drain electrodes of the third and fourth transistors are coupled together to the output node.

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Номер записи: 60
10-02-2022 дата публикации

BIT LINE EQUALIZATION DRIVER CIRCUITS AND RELATED APPARATUSES, METHODS, AND COMPUTING SYSTEMS

Номер: US20220044721A1
Автор: He Yuan, Park Sang-Kyun
Принадлежит:

Bit line equalization driver circuits and related apparatuses, methods, and computing systems are disclosed. An apparatus includes an output inverter including a pull-up transistor and a pull-down transistor electrically connected in series between a pull-up node and a pull-down node. An output node is electrically connected between the pull-up transistor and the pull-down transistor. The pull-down transistor includes a short length transistor having a degradation voltage potential across the pull-down transistor below which the pull-down transistor is configured to operate to avoid degradation of the pull-down transistor. The apparatus also includes biasing circuitry configured to control voltage potentials at the pull-up node and the pull-down node to enable the output inverter to assert, at the output node, an output voltage potential that is greater than the degradation voltage potential higher than a low power supply voltage potential at the low power supply node. 1. An apparatus , comprising:a pull-up node;a pull-down node;an output node;a low power supply node;an output inverter including a pull-up transistor and a pull-down transistor electrically connected in series between the pull-up node and the pull-down node, the output node electrically connected between the pull-up transistor and the pull-down transistor, the pull-down transistor having a degradation voltage potential across the pull-down transistor below which the pull-down transistor is configured to operate to avoid degradation of the pull-down transistor; andbiasing circuitry configured to control voltage potentials at the pull-up node and the pull-down node to enable the output inverter to assert, at the output node, an output voltage potential that is greater than the degradation voltage potential higher than a low power supply voltage potential at the low power supply node.2. The apparatus of claim 1 , wherein:the biasing circuitry is configured to provide, to the pull-up node, an isolation ...

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Номер записи: 61
10-02-2022 дата публикации

Signal development caching in a memory device

Номер: US20220044723A1
Автор: Dmitri A. Yudanov, Shanky Kumar Jain
Принадлежит: Micron Technology Inc

Methods, systems, and devices related to signal development caching in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). In various examples, accessing the memory device may include accessing information from the signal development cache, or the memory array, or both, based on various mappings or operations of the memory device.

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Номер записи: 62
10-02-2022 дата публикации

Read Model of Memory Cells using Information Generated during Read Operations

Номер: US20220044756A1
Автор: Alhussien AbdelHakim S., Fitzpatrick James, Khayat Patrick Robert, Parthasarathy Sivagnanam
Принадлежит:

A memory sub-system configured to generate or update a model for reading memory cells in a memory device. For example, in response to a processing device of a memory sub-system transmitting to a memory device read commands that are configured to instruct the memory device to retrieve data from a group of memory cells formed on an integrated circuit die in the memory device, the memory device may measure signal and noise characteristics of the group of memory cells during execution of the read commands. Based on the signal and noise characteristics the memory sub-system can generate or update, measured during the execution of the read commands a model of changes relevant to reading data from the group of memory cells. The changes can be a result of damage, charge loss, read disturb, cross-temperature effect, etc. 1. A device , comprising:an integrated circuit die;memory cells formed on the integrated circuit die; and measure signal and noise characteristics of a memory cell group, among the memory cells, to calibrate read voltages of the memory cell group; and', 'generate, based at least in part on the signal and noise characteristics of the memory cell group, a model of changes of the group of memory cells., 'a logic circuit configured to, in response to commands to read data from the memory cells,'}2. The device of claim 1 , comprising:a calibration circuit configured to apply test voltages to the memory cell group to measure the signal and noise characteristics of the memory cell group.3. The device of claim 2 , wherein the logic circuit is configured to generate the model by updating a prior model.4. The device of claim 2 , wherein the logic circuit is configured to generate the model based on a history of the changes reflected at least in part in the signal and noise characteristics of the memory cell group measured during execution of the commands configured to read data from the memory cell groups.5. The device of claim 4 , wherein the logic circuit is ...

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Номер записи: 63
24-01-2019 дата публикации

APPARATUSES AND METHODS FOR PROVIDING INTERNAL MEMORY COMMANDS AND CONTROL SIGNALS IN SEMICONDUCTOR MEMORIES

Номер: US20190027197A1
Автор: Kwak Jongtae, Lee Hyun Yoo, Tatapudi Suryanarayana
Принадлежит: MICRON TECHNOLOGY, INC.

In an example apparatus, a command path receives read commands and provides respective control signals for each read command. The command path is configured to provide initial control signals for an initial read command responsive to a first clock edge of a clock signal of a plurality of multiphase clock signals and to further provide respective control signals for subsequent read commands responsive to receipt of the subsequent mad commands. The example apparatus further includes a read data output circuit configured to receive the control signals from the command path and further receive read data in parallel. The read data output circuit is configured to provide the read data serially responsive to the control signals. 1. A method , comprising:receiving a first read command;providing a first internal read command based on activation of a clock signal;generating first control signals based on the first internal read command, the first control signals associated with the first read command;receiving a second read command after the first read command;providing a second internal read command based on the second read command;generating second control signals based on the second read command; andproviding first read data for the first read command based on the first control signals and providing second read data for the second read command based on the second control signals.2. The method of further comprising ignoring the first read command in providing the first internal read command.3. The method of claim 1 , wherein the first internal read command is provided by a first read command circuit and wherein the second internal read command is provided by a second read circuit.4. The method of claim 1 , wherein providing the first internal read command based on the activation of the clock signal comprises:shifting a high logic level signal through a plurality of flip-flop (FF) circuits based on the activation of the clock signal; andproviding an output of a flip-flop ...

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Номер записи: 64
24-01-2019 дата публикации

APPARATUSES AND METHODS FOR DETERMINING A PHASE RELATIONSHIP BETWEEN AN INPUT CLOCK SIGNAL AND A MULTIPHASE CLOCK SIGNAL

Номер: US20190027199A1
Автор: Kim Kang-Yong, Lee Hyun Yoo
Принадлежит: MICRON TECHNOLOGY, INC.

Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal are disclosed. An example apparatus includes a clock path configured to receive a clock signal and provide internal clock signals and a command path configured to receive a command and propagate the command through the command path responsive to the internal clock signals and provide an internal command having a timing that reflects a timing of the clock signal. The example apparatus further includes a data clock path configured to receive a data clock signal and provide multiphase clock signals based on the data clock signal and provide a delayed multiphase clock signal, and further includes a clock synchronization circuit configured to receive the delayed multiphase clock signal and latch a logic level of the delayed multiphase clock signal responsive to the internal command. 1. An apparatus comprising:a data clock path configured to receive a data clock signal and provide multiphase dock signals based on the data clock signal, wherein the multiphase clock signals have a first or second phase relationship with the data clock signal, the data dock path further configured to provide a delayed it clock signal having a delay relative to a multiphase clock signal of the multiphase clock signals;a command path configured to receive a command and decode the command and provide an internal command having a timing in an internal clock domain; anda clock synchronization circuit configured to be clocked by the internal command to latch a logic level during a static period of the delayed multiphase clock signal and provide an output signal having a logic level indicative of the phase relationship of the multiphase clock signals to the data clock signal.2. The apparatus of claim 1 , wherein the data clock path includes a clock divider circuit configured to provide the multiphase clock signals based on the data clock signal claim 1 , the clock divider circuit ...

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Номер записи: 65
24-01-2019 дата публикации

Frequency synthesis for memory input-output operations

Номер: US20190027208A1
Автор: Daniel Skinner, Dean Gans, Moo Sung Chae
Принадлежит: Micron Technology Inc

A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may include multiple clock circuits that generate multiple internal clock signals. Each portion of the memory channel associated with a different clock circuit may be phase and/or frequency independent of the other portions of the memory channel. The clock circuit may synthesize an internal clock signal based on an external clock signal. The clock circuit may use encoded timing data from an encoded I/O scheme to align the phase of the internal clock signal to a data signal.

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Номер записи: 66
28-01-2021 дата публикации

MEMORY SYSTEM AND METHOD OF OPERATING THE SAME

Номер: US20210026570A1
Автор: KIM Kwang Su
Принадлежит:

Provided herein may be a memory system and a method of operating the same. The method of operating a memory system may include receiving a first program command, and performing an operation corresponding to the first program command, receiving a second program command while performing the operation corresponding to the first program command, delaying setting of a queue status register for the second program command by a first wait time, receiving a third read command before the first wait time elapses, and setting the queue status register for the third read command before setting the queue status register for the second program command. 1. A method for a memory controller controlling a non-volatile memory device , the method comprising:receiving a plurality of commands from a host;queueing a command among the plurality command into a queue status register based on a priority of the plurality of commands; andexecuting a next command among the plurality of commands to be performed after the command based on the priority of the plurality of commands and a category of the plurality of commands.2. The method of claim 1 , wherein the queueing comprises:setting a status of the command as a set status; andsetting the status of the command as a clear status after the memory device starts to perform an operation corresponding to the command.3. The method of claim 1 , wherein the executing the next command comprises setting a status of the next command as a set status.4. The method of claim 3 , wherein the plurality of commands include a write command and a read command.5. The method of claim 4 , wherein the executing the next command comprises setting a status of the read command to the set status prior to the write command for the predetermined time.6. The method of claim 1 , wherein the priority of the plurality of commands is an order provided from the host.7. An apparatus claim 1 , comprising:a memory device; anda controller coupled to the memory device and configured to ...

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Номер записи: 67
23-01-2020 дата публикации

Method and apparatus to improve read latency of a multi-threshold level cell block-based non-volatile memory

Номер: US20200027503A1
Автор: Aliasgar S. Madraswala, Cole UHLMAN, Lei Chen, Xin Guo, Yogesh B. Wakchaure
Принадлежит: Intel Corp

A method and apparatus to reduce read retry operations in a NAND Flash memory is provided. To reduce the number of read retries for future reads, a word line group is assigned an optimal read voltage, the reference voltage that results in eliminating the read error for the word line is selected as the optimal read voltage (also referred to as a “sticky voltage”) for the word line group to be used for a next read of the page. An optimal read voltage per word line group for the page per NAND Flash memory die is stored in the lookup table. Storing an optimal read voltage per word line group instead of per die reduces the number of read retries.

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Номер записи: 68
28-01-2021 дата публикации

CALIBRATION CIRCUIT FOR CONTROLLING RESISTANCE OF OUTPUT DRIVER CIRCUIT, MEMORY DEVICE INCLUDING THE SAME, AND OPERATING METHOD OF THE MEMORY DEVICE

Номер: US20210027827A1
Автор: CHOI HUNDAE, KIM HWAPYONG, LEE Junha
Принадлежит:

A memory device includes a calibration circuit having a pull-up code generator including a pull-up resistor block and generating a pull-up code, and a pull-down code generator including a replica pull-up resistor block and a pull-down resistor block and generating a pull-down code, and an off chip driver/on die termination circuit providing a termination resistance having a resistance value set by the calibration circuit in a data reception operation and outputting data at an output strength set by the calibration circuit in a data output operation. In a calibration operation, a resistance value of the replica pull-up resistor block is adjusted to be less than a resistance value of the pull-up resistor block, and the pull-down code has a code value by which a resistance value of the pull-down resistor block corresponds to the resistance value of the replica pull-up resistor block. 1. A memory device comprising:a calibration circuit having a pull-up code generator comprising a pull-up resistor block and configured to generate a pull-up code, and a pull-down code generator comprising a replica pull-up resistor block and a pull-down resistor block and configured to generate a pull-down code; andan off chip driver (OCD)/on die termination (ODT) circuit configured to provide a termination resistance having a resistance value set by the calibration circuit in a data reception operation and to output data at an output strength set by the calibration circuit in a data output operation,wherein, in a calibration operation, a resistance value of the replica pull-up resistor block is adjusted to be less than a resistance value of the pull-up resistor block, and the pull-down code has a code value by which a resistance value of the pull-down resistor block corresponds to the resistance value of the replica pull-up resistor block.2. The memory device of claim 1 , whereinthe pull-up resistor block comprises at least one pull-up resistor set connected to a power source voltage, the ...

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Номер записи: 69
28-01-2021 дата публикации

PREEMPTIVE IDLE TIME READ SCANS

Номер: US20210027846A1
Автор: Malshe Ashutosh, Miller Michael G., Muchherla Kishore Kumar, Ratnam Sampath, Singidi Harish Reddy, Zhang Xu, ZHOU JIE
Принадлежит:

Devices and techniques for initiating and controlling preemptive idle time read scans in a flash based storage system are disclosed. In an example, a memory device includes a NAND memory array and a memory controller to schedule and initiate read scans among multiple locations of the memory array, with such read scans being preemptively triggered during an idle (background) state of the memory device, thus reducing host latency during read and write operations in an active (foreground) state of the memory device. In an example, the optimization technique includes scheduling a read scan operation, monitoring an active or idle state of host IO operations, and preemptively initiating the read scan operation when entering an idle state, before the read scan operation is scheduled to occur. In further examples, the read scan may preemptively occur based on time-based scheduling, frequency-based conditions, or event-driven conditions triggering the read scan. 1. A system , comprising:a memory device; and identifying a read scan condition of the memory device the read scan condition being associated with a future trigger that causes a read scan;', 'monitoring the memory device to identify an occurrence of an idle state; and', 'initiating the read scan in response to the occurrence of the idle state, the read scan being initiated to occur before the future trigger., 'a processing device operably coupled to the memory device, the processing device configured to perform operations comprising2. The system of claim 1 , wherein the read scan condition is determined from a state of the memory device.3. The system of claim 1 , wherein the read scan is configured to sample data at multiple locations of the memory device by performing reads at the multiple locations.4. The system of claim 1 , wherein the idle state corresponds to an absence of operations initiated on the memory device from a host.5. The system of claim 1 , wherein the future trigger is an identified time based on a ...

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Номер записи: 70
23-01-2020 дата публикации

Data output buffer

Номер: US20200028507A1
Автор: Jin Ha Hwang, Keun Seon AHN
Принадлежит: SK hynix Inc

A data output buffer includes a pull-up main driver outputting output data having a high level through an output pad by performing an emphasis operation according to input data, a pull-down main driver outputting the output data having a low level through the output terminal according to the input data, an active inductor controller selectively outputting an inductor activating voltage by detecting a rising or falling period of the input data, and an active inductor selectively performing a de-emphasis operation on the output terminal in response to the inductor activating voltage.

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Номер записи: 71
29-01-2015 дата публикации

SIGNAL CONTROL CIRCUIT, INFORMATION PROCESSING APPARATUS, AND DUTY RATIO CALCULATION METHOD

Номер: US20150032950A1
Автор: Hashimoto Michitaka, Ookubo Katsuhiko, TOKUHIRO Noriyuki
Принадлежит: FUJITSU LIMITED

A signal control circuit includes: a delay acquisition circuit configured to obtain a first delay amount to be added to an input signal for aligning timing of rise of the input signal with timing of fall or rise of a reference signal and a second delay amount to be added to the input signal for aligning timing of fall of the input signal with timing of the fall or the rise of the reference signal; and a ratio calculation circuit configured to calculate a duty ratio of the input signal based on a difference between the first delay amount and the second delay amount. 1. A signal control circuit , comprising:a delay acquisition circuit configured to obtain a first delay amount to be added to an input signal for aligning timing of rise of the input signal with timing of fall or rise of a reference signal and a second delay amount to be added to the input signal for aligning timing of fall of the input signal with timing of the fall or the rise of the reference signal; anda ratio calculation circuit configured to calculate a duty ratio of the input signal based on a difference between the first delay amount and the second delay amount.2. The signal control circuit according to claim 1 , wherein the delay acquisition circuit is configured to obtain the first delay amount such that rise of a delayed signal formed by adding the first delay amount to the input signal is located to be aligned with the fall or the rise of the reference signal and obtain the second delay amount such that fall of the delayed signal formed by adding the second delay amount to the input signal is located to be aligned with the fall or the rise of the reference signal.3. The signal control circuit according to claim 1 , wherein the delay acquisition circuit is configured to obtain the first delay amount by repeatedly adding a delay amount of a first predetermined phase difference unit to the input signal and the second delay amount by repeatedly adding a delay amount of a second predetermined phase ...

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Номер записи: 72
01-02-2018 дата публикации

IMPEDANCE ADJUSTMENT IN A MEMORY DEVICE

Номер: US20180032453A1
Автор: GRUNZKE Terry
Принадлежит: MICRON TECHNOLOGY, INC.

Methods include configuring termination devices of a driver circuit of a memory device, storing a first plurality of trim values representative of the configuration of the termination devices of the driver circuit, transferring a second plurality of trim values to a different memory device, and configuring a plurality of termination devices of a driver circuit of the different memory device in response to the second plurality of trim values. Methods further include determining configuration information corresponding to a configuration of a particular driver circuit of a memory device adjusted to a desired impedance, storing a first set of trim values representative of the configuration information, and adjusting an impedance of a different driver circuit of the memory device in response to the first set of trim values and a correction factor representative of expected differences in characteristics between the particular driver circuit and the different driver circuit. 1. (canceled)2. A method of operating a plurality of memory devices , the method comprising:configuring a plurality of termination devices of a particular driver circuit of a particular memory device of the plurality of memory devices;storing, to the particular memory device, a first plurality of trim values representative of the configuration of the plurality of termination devices of the particular driver circuit;after storing the first plurality of trim values to the particular memory device, transferring a second plurality of trim values from the particular memory device to a different memory device of the plurality of memory devices; andconfiguring a plurality of termination devices of a driver circuit of the different memory device in response to the second plurality of trim values.3. The method of claim 2 , wherein transferring the second plurality of trim values comprises transferring a same plurality of trim values as the first plurality of trim values.4. The method of claim 3 , further ...

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Номер записи: 73
02-02-2017 дата публикации

Semiconductor memory device, memory system including the same and operating method thereof

Номер: US20170032829A1
Автор: Jin Su Park, Min gi HONG
Принадлежит: SK hynix Inc

A semiconductor memory device includes a program and read unit suitable for programming program data in a memory cell array and for reading read data stored in the memory cell array, and a control unit suitable for generating a control signal for controlling the program and read unit in response to a command input from the outside of the semiconductor memory device, in which the control unit controls the program and read unit to read the read data in a state of storing a first bit data of the program data when a read command is input while programming the program data.

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Номер записи: 74
05-02-2015 дата публикации

Data output circuits

Номер: US20150035575A1
Автор: Jae Woong Yun
Принадлежит: SK hynix Inc

Data output circuits are provided. The data output circuit includes a latch control signal generator and a data output portion. The latch control signal generator generates an input pulse signal and a latch control signal i, and the latch control signal includes a pulse whose width is controlled to have a predetermined time period. The data output portion latches a data loaded on an input/output (I/O) line during a pulse width period of the latch control signal to generate a latch data. Moreover, the data output portion buffers the latch data according to an output control signal generated from a read command signal to output the buffered latch data as an output data.

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Номер записи: 75
17-02-2022 дата публикации

Content-addressable memory for signal development caching in a memory device

Номер: US20220050776A1
Автор: Dmitri A. Yudanov, Shanky Kumar Jain
Принадлежит: Micron Technology Inc

Methods, systems, and devices related to content-addressable memory for signal development caching are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may also include storage, such as a content-addressable memory, configured to store a mapping between addresses of the signal development cache and addresses of the memory array. In various examples, accessing the memory device may include determining and storing a mapping between addresses of the signal development cache and addresses of the memory array, or determining whether to access the signal development cache or the memory array based on such a mapping.

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Номер записи: 76
17-02-2022 дата публикации

HISTOGRAM CREATION PROCESS FOR MEMORY DEVICES

Номер: US20220051046A1
Автор: Willcock Jeremiah James
Принадлежит:

A processor-in-memory device includes a memory array, a sense amplifier, and a processing unit that has an accumulator. The processing unit is configured to receive a set of data. The processing unit then uses the sense amplifier and the accumulator to generate a first histogram of the set of data. 1. A system , comprising:a host processor; and a memory array including a plurality of memory locations, wherein each of the memory locations stores a value;', 'a first accumulator coupled to a first group of the plurality of memory locations; and', 'a plurality of storage elements, wherein the plurality of storage elements are coupled to the first accumulator and the memory array; and, 'a processor-in-memory device coupled to the host processor, wherein the processor-in-memory device comprises receive a data set comprising a plurality of data batches, wherein each data batch comprises a plurality of data points;', 'determine, by the first accumulator, to which category of a plurality of categories each data point in a first batch of the plurality of data batches belongs;', 'set a value of a flag bit, in a first storage element of the plurality of storage elements, wherein the flag bit corresponds, in bit position, to the category of the plurality of categories to which a data point in the first batch of data is determined to belong; and', 'after having set a value of each of a first subset of a set of flag bits in the plurality of storage elements, each flag bit of the first subset respectively corresponding, in bit position, to a category of data determined to be present in the first data batch, increment at least one first value stored in each of the first group of the plurality of memory locations to generate a first histogram of the first batch of a data set using the first accumulator based on whether or not a corresponding respective flag bit stored in the storage element was set as part of the first subset such that a first data point determined to belong to a ...

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Номер записи: 77
17-02-2022 дата публикации

RECEIVER TRAINING OF REFERENCE VOLTAGE AND EQUALIZER COEFFICIENTS

Номер: US20220051742A1
Автор: Baby Kiran, Bala Phalguni, M. Ashwin S., Mishra Navin Kumar, Shelke Anirudha, Shetty Sudhir Kumar Katla, Syed Younus
Принадлежит:

In a receiver having at least a first equalizer and a sampler, a calibration module jointly calibrates a reference voltage and one or more equalizer coefficients. For each of a set of test reference voltages, an equalizer coefficient for the first equalizer may be learned that maximizes a right eye boundary of an eye diagram of a sampler input signal to a sampler of the receiver following the equalization stage. Then, from the possible pairs of reference voltages and corresponding optimal equalizer coefficients, a pair is identified that maximizes an eye width of the eye diagram. After setting the reference voltage, the first equalizer coefficient may then be adjusted together with learning a second equalizer coefficient for the second equalizer using a similar technique. 1. A method for calibrating a receiver of a communication link , the receiver comprising at least a first equalizer to generate a sampler input signal based on a receiver input signal , and a sampler sampling the sampler input signal to generate an output signal , the method comprising:receiving, at the receiver over the communication link, a receiver input signal representing a bit pattern having AC frequency components and DC frequency components;determining, for each of a plurality of reference voltages, a corresponding first equalizer coefficient for the first equalizer and a corresponding plurality of parameters of the sampler input signal that are based on the reference voltage and the corresponding first equalizer coefficient;selecting a reference voltage from among the plurality of reference voltages and the selected reference voltage's corresponding first equalizer coefficient that have the corresponding plurality of parameters of the sampler input signal that satisfy a plurality of optimization criterion; andsetting the selected reference voltage.2. The method of claim 1 , wherein the receiver input signal comprises a bit pattern having alternating current frequency components and direct ...

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Номер записи: 78
31-01-2019 дата публикации

CONTROLLER AND OPERATING METHOD THEREOF

Номер: US20190035443A1
Автор: PARK Byoung Jun, PARK Seong Jo
Принадлежит: SK HYNIX INC.

A controller controls an operation of a semiconductor memory device including a plurality of memory blocks. The controller includes a temperature sensing unit, a period storage unit, and a command generating unit. The temperature sensing unit generates temperature information by sensing a temperature of the semiconductor memory device. The period storage unit updates an output period of a dummy read command that allows the semiconductor memory device to perform a dummy read operation, based on the temperature information. The command generating unit generates the dummy read command, based on the output period. 1. A controller that controls an operation of a semiconductor memory device including a plurality of memory blocks , the controller comprising:a temperature sensing unit configured to generate temperature information by sensing a temperature of the semiconductor memory device;a period storage unit configured to update an output period of a dummy read command that allows the semiconductor memory device to perform a dummy read operation, based on the temperature information; anda command generating unit configured to generate the dummy read command, based on the output period.2. The controller of claim 1 , wherein the period storage unit includes a lookup table that includes an output period corresponding to each temperature range claim 1 ,wherein the period storage unit updates a currently applied output period with reference to the lookup table.3. The controller of claim 1 , wherein claim 1 , as the temperature measured by the temperature sensing unit increases claim 1 , the period storage unit updates a shorter period as the output period.4. The controller of claim 1 , wherein the command generating unit generates the dummy read command by comparing an output reference time with the output period claim 1 , where the output reference time indicates a period between a time when a preceding dummy read command was generated and a current time.5. The controller of ...

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Номер записи: 79
31-01-2019 дата публикации

MEMORY CONTROL CIRCUIT, MEMORY, AND MEMORY CONTROL METHOD

Номер: US20190035469A1
Автор: ISE Masahiro, MAEDA Masazumi
Принадлежит: FUJITSU LIMITED

A memory control circuit includes an input circuit that receives data to be written to a storage having multiple nonvolatile memory cells, and a control circuit, when a second number of bits that are included in a first bit string and having a first number of bits and have a second logical value different from a first logical value equal to initial values stored in the multiple nonvolatile memory cells is equal to or smaller than a first threshold, writes the first bit string and the first additional value to the storage, and that associates, when the second number of the bits is larger than a second threshold larger than the first threshold, a second bit string obtained by reversing logical values of all the bits of the first bit string with a second additional value and writes the second bit string and the second additional value to the storage. 1. A memory control circuit comprising:an input circuit that receives data to be written to a storage having multiple nonvolatile memory cells; anda control circuit that associates, when a second number of bits that are included in a first bit string included in the data and having a first number of bits and have a second logical value different from a first logical value equal to initial values stored in the multiple nonvolatile memory cells is equal to or smaller than a first threshold, the first bit string with a first additional value and writes the first bit string and the first additional value to the storage, that associates, when the second number of the bits is larger than a second threshold larger than the first threshold, a second bit string obtained by reversing logical values of all the bits of the first bit string with a second additional value and writes the second bit string and the second additional value to the storage, that generates, when the second number of the bits is larger than the first threshold and smaller than the second threshold, a fourth bit string by calculating a logical sum of the second ...

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Номер записи: 80
30-01-2020 дата публикации

AUTOMATED VOLTAGE AND TIMING MARGIN MEASUREMENT FOR NAND FLASH INTERFACE

Номер: US20200035276A1
Автор: SIJHER Taninder, Sirajudeen Shajith Musaliar
Принадлежит:

A storage device comprises a controller, such as an ASIC controller, and one or more NAND flash memory devices. The controller comprises a differential receiver and a delay locked loop circuit. During read and write operations, the controller is configured to vary a delay of a data strobe signal by an interval across a width of a data window using the delay locked loop circuit, and to compare a write pattern to a read pattern for each delayed interval to determine the timing margins of the storage device. During read and write operations, the controller is further configured to apply a reference voltage to a host interface or a memory interface, increment and decrement the reference voltage by a set value, and compare a write pattern to a read pattern for each varied reference voltage value to determine the voltage margins of the storage device. 1. A method for measuring timing margins used during write operations of a storage device , comprising:varying a delay of a data strobe signal by an interval across a width of a data window using a delay locked loop circuit, wherein the interval is less than a width of the data window;writing a predefined pattern to a memory device for each varied interval of the delayed data strobe;reading the predefined pattern from the memory device for each varied interval of the delayed data strobe; anddetermining one or more valid timing margins based on each varied interval of the delayed data strobe.2. The method of claim 1 , further comprising:determining, for each varied interval of the delayed data strobe, a write pattern by writing a predefined pattern to a flash memory device of the storage device; anddetermining, for each varied interval of the delayed data strobe, a read pattern by reading the predefined pattern from the flash memory device.3. The method of claim 2 , further comprising:comparing, for each varied interval of the delayed data strobe, the write pattern to the read pattern; andwherein the one or more valid timing ...

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Номер записи: 81
30-01-2020 дата публикации

Word-Line Driver and Method of Operating a Word-Line Driver

Номер: US20200035288A1
Автор: Ali Taghvaei, Atul Katoch
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Word-line drivers, memories, and methods of operating word-line drivers are provided. A word-line driver coupled to an array of memory cells includes a decoder powered by a first power supply. The decoder is configured to decode an address to provide a plurality of word-line signals. The word-line driver also includes a plurality of output stages powered by a second power supply that is different than the first power supply. Each of the output stages includes a first transistor having a gate controlled by a first control signal and an inverter. The inverter is coupled between the first transistor and a ground and has an input coupled to the decoder to receive one of the word-line signals. The word-line driver also includes pull-down circuitry coupled between the gates of the first transistors and the ground and activated by a second control signal.

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Номер записи: 82
30-01-2020 дата публикации

Extended write modes for non-volatile static random access memory architectures having word level switches

Номер: US20200035293A1
Автор: Francois Tailliet, Marc Battista
Принадлежит: STMICROELECTRONICS ROUSSET SAS

Disclosed herein is a method of performing a non-volatile write to a memory containing a plurality of volatile memory cells grouped into words, with each volatile memory cell having at least one non-volatile memory cell associated therewith. The method includes steps of a) receiving a non-volatile write instruction including at least one address and at least one data word to be written to that at least one address, b) writing the at least one data word to the volatile memory cells of a word at the at least one address, and c) writing data from the volatile memory cells written to during step b) to the non-volatile memory cells associated to those volatile memory cells by individually addressing those non-volatile memory cells for non-volatile writing, but not writing data from other volatile memory cells to their associated non-volatile memory cells because those non-volatile memory cells are not addressed.

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Номер записи: 83
31-01-2019 дата публикации

TIMING BASED ARBITRATION METHODS AND APPARATUSES FOR CALIBRATING IMPEDANCES OF A SEMICONDUCTOR DEVICE

Номер: US20190036740A1
Автор: Johnson Jason, Wieduwilt Christopher G.
Принадлежит: MICRON TECHNOLOGY, INC.

Systems and apparatuses are provided for an arbiter circuit for timing based ZQ calibration. An example system includes a resistor and a plurality of chips. Each of the plurality of chips further includes a terminal coupled to the resistor and a calibration circuit. The calibration circuit determines whether the resistor is available based, at least in part, on timing information that is unique to a corresponding chip of the plurality of chip. The timing information of each chip of the plurality of chips has a fixed duration of time common to the plurality of chips. 1. A system comprising:a resistor; and a terminal coupled to the resistor; and', 'a calibration circuit configured to determine whether the resistor is available based, at least in part, on timing information unique to a corresponding chip., 'a plurality of chips, each chip of the plurality of chips including2. The system of claim 1 , wherein the timing information of each chip of the plurality of chips has a fixed duration of time common to the plurality of chips.3. The system of claim 2 , wherein the calibration circuit of each chip of the plurality of chips includes:a driver circuit coupled to the terminal; andan arbiter circuit configured to enable and disable the driver circuit for the fixed duration of time based on the liming information unique to each respective chip among the plurality of chips.4. The system of claim 2 , wherein the calibration circuit of each chip of the plurality of chips includes:a driver circuit coupled to the terminal; andan arbiter circuit configured to disable the driver circuit to change a voltage of the terminal for a predetermined time in the beginning of the fixed duration of time and further configured to enable the driver circuit after the predetermined time.5. The system of claim 1 , wherein the calibration circuit of each chip of the plurality of chips includes an arbiter circuit claim 1 , andwherein an order in which the plurality of chips requesting calibration ...

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Номер записи: 84
30-01-2020 дата публикации

TIMING BASED ARBITRATION METHODS AND APPARATUSES FOR CALIBRATING IMPEDANCES OF A SEMICONDUCTOR DEVICE

Номер: US20200036560A1
Автор: Johnson Jason, Wieduwilt Christopher G.
Принадлежит: MICRON TECHNOLOGY, INC.

Systems and apparatuses are provided for an arbiter circuit for timing based ZQ calibration. An example system includes a resistor and a plurality of chips. Each of the plurality of chips further includes a terminal coupled to the resistor and a calibration circuit. The calibration circuit determines whether the resistor is available based, at least in part, on timing information that is unique to a corresponding chip of the plurality of chip. The timing information of each chip of the plurality of chips has a fixed duration of time common to the plurality of chips. 1. An apparatus comprising:a driver circuit coupled to a terminal of a chip; andan arbiter circuit configured to enable the driver circuit to change a voltage of the terminal before determining a resistor coupled to the terminal is available for a calibration operation of the chip, wherein the arbiter circuit enables the driver circuit based at least in part, on timing information unique to the chip.2. The apparatus of claim 1 , further comprising a calibration control circuit coupled to the driver circuit wherein the calibration control circuit is configured to adjust an impedance of the driver circuit when the resistor is available for the calibration operation.3. The apparatus of claim 1 , wherein the driver circuit includes a pull-up circuit and a pull-down circuit.4. The apparatus of claim 3 , wherein the pull-up circuit includes a first plurality of transistors coupled in parallel between a first power supply terminal and a node and the pull-down circuit includes a second plurality of transistors coupled in parallel between a second power supply terminal and the node.5. The apparatus of claim 1 , further comprising a comparator configured to compare a first voltage to a reference voltage and provide a comparator result to the arbiter circuit.6. The apparatus of claim 5 , further comprising a reference voltage generator configured to provide the reference voltage to the comparator.7. The apparatus ...

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Номер записи: 85
30-01-2020 дата публикации

SEMICONDUCTOR DEVICE AND MEMORY SYSTEM

Номер: US20200036561A1
Автор: Yamamoto Kensuke, YANAGIDAIRA Kosuke
Принадлежит:

A semiconductor device includes a first chip and a second chip. The first chip includes a first circuit having a first output terminal. The second chip includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line. When the first chip and the second chip receive a first command, the second circuit calibrates an output impedance at the second output terminal through a first calibration operation based on an output impedance at the first output terminal. 1. A semiconductor device configured to communicate with a controller , the semiconductor device comprising:a first chip that includes a first circuit having a first output terminal; anda second chip that includes a second circuit having a second output terminal, which is electrically connected to the first output terminal via a first signal line, whereinupon receipt of a first command, the first circuit calibrates an output impedance at the first output terminal through a first calibration operation,upon receipt of a second command after the first calibration operation is performed, the second circuit calibrates an output impedance at the second output terminal through a second calibration operation based on the output impedance at the first output terminal, anda duration of the second calibration operation is shorter than a duration of the first calibration operation.2. The semiconductor device according to claim 1 , whereinthe first chip transmits to the controller a signal indicating that the first chip is in a busy state upon starting the first calibration operation, and transmits to the controller a signal indicating that the first chip is in a ready state upon completion of the first calibration operation, andthe second chip transmits to the controller a signal indicating that the second chip is in the busy state upon starting the second calibration operation, and transmits to the controller a signal indicating that the second ...

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Номер записи: 86
04-02-2021 дата публикации

FLOATING BODY DRAM WITH REDUCED ACCESS ENERGY

Номер: US20210035623A1
Автор: Linstadt John Eric, LU Zhichao, Ware Frederick A., Wright Kenneth Lee
Принадлежит:

Memory devices, controllers and associated methods are disclosed. In one embodiment, a memory device is disclosed. The memory device includes storage cells that are each formed with a metal-oxide-semiconductor (MOS) transistor having a floating body. Data is stored as charge in the floating body. A transfer interface receives a read command to access data stored in a first group of the storage cells. Sensing circuitry detects the data stored in the first group of storage cells. The transfer interface selectively performs a writeback operation of the sensed data associated with the read command. 1. (canceled)2. A memory controller , comprising:a transfer interface to transmit a read command to access first read data stored in a first group of floating body storage cells;conditional writeback circuitry coupled to the transfer interface, the conditional writeback circuitry to generate a writeback command in response to one of a predetermined probability, a threshold count of a number of accesses to the first group of the storage cells, or a tag value exhibiting a first sense characteristic; andwherein the transfer interface is configured to conditionally perform a writeback operation of sensed data associated with the read command in response to the writeback command generated by the conditional writeback circuitry.3. The memory controller of :wherein the conditional writeback circuitry generates the writeback command randomly based on the predetermined probability.4. The memory controller of claim 3 , wherein the conditional writeback circuitry further comprises:a control register to store a value N corresponding to the predetermined probability.5. The memory controller of claim 4 , wherein the conditional writeback circuitry further comprises:a random signal generator configured to generate the writeback command with the predetermined probability based on the relationship 1/N.6. The memory controller of claim 1 , wherein the conditional writeback circuitry further ...

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Номер записи: 87
04-02-2021 дата публикации

ON-DEMAND HIGH PERFORMANCE MODE FOR MEMORY WRITE COMMANDS

Номер: US20210035627A1
Автор: Huang Jianmin, Tanpairoj Kulachet
Принадлежит:

A processing device in a memory system determines whether a number of a plurality memory commands stored in a queue satisfies a queue depth threshold criterion. Responsive to the queue depth threshold criterion being satisfied, the processing device initiates a high performance mode of operation for the system and executes, in the high performance mode of operation, a first memory command of the plurality of memory commands. 1. A system comprising:a memory component; and determine whether a number of a plurality memory commands stored in a queue satisfies a queue depth threshold criterion;', 'responsive to the queue depth threshold criterion being satisfied, initiate a high performance mode of operation for the system; and', 'execute, in the high performance mode of operation, a first memory command of the plurality of memory commands., 'a processing device, operatively coupled with the memory component, to2. The system of claim 1 , wherein the processing device further to:receive the plurality of memory commands from a host system coupled to the system; andstore the plurality of memory commands in the queue.3. The system of claim 1 , wherein the number of the plurality memory commands satisfies the queue depth threshold criterion when the number of the plurality of memory commands exceeds a queue depth threshold number.4. The system of claim 1 , wherein the plurality of memory commands comprise write commands claim 1 , and wherein to execute the first memory command claim 1 , the processing device to write first data associated with the first memory command to the memory component.5. The system of claim 4 , wherein to execute the first memory command in the high performance mode of operation claim 4 , the processing device to write the first data to a first data block of the memory component configured as single-level-cell (SLC) memory.6. The system of claim 1 , wherein the processing device further to:determine that the plurality of memory commands have been ...

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Номер записи: 88
04-02-2021 дата публикации

Apparatuses including conductive structures and layouts thereof

Номер: US20210035985A1
Автор: Masahiko Igeta
Принадлежит: Micron Technology Inc

Embodiments of the disclosure are drawn to arrangements of one or more conductive structures to provide connections to circuits or portions thereof located in different regions of a device. One or more of the conductive structures may include extensions and recesses. The extensions and recesses of different conductive structures may be complementary. That is, the extensions of one conductive structure may extend into a recess of another conductive structure.

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Номер записи: 89
12-02-2015 дата публикации

Semiconductor memory device, memory system including the same and operating method thereof

Номер: US20150043286A1
Автор: Jin Su Park, Min gi HONG
Принадлежит: SK hynix Inc

A semiconductor memory device includes a program and read unit suitable for programming program data in a memory cell array and for reading read data stored in the memory cell array, and a control unit suitable for generating a control signal for controlling the program and read unit in response to a command input from the outside of the semiconductor memory device, in which the control unit controls the program and read unit to read the read data in a state of storing a first bit data of the program data when a read command is input while programming the program data.

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Номер записи: 90
12-02-2015 дата публикации

Semiconductor device

Номер: US20150043299A1
Автор: Hiroki Fujisawa, Kazutaka Miyano
Принадлежит: Micron Technology Inc

A device includes an output circuit, a DLL (Delay Locked Loop) circuit including a first delay line receiving a first clock signal and outputting, in response to receiving the clock signal, a second clock signal supplied to the output circuit, and an ODT (On Die Termination) circuit receiving an ODT activation signal and outputting, in response to receiving the ODT activation signal, an ODT output signal supplied to the output circuit to set the output circuit in a resistance termination state, and the ODT circuit including a second delay line configured to be set by the DLL circuit in an equivalent delay amount that is equivalent to a delay amount of the first delay line, the ODT output signal being, in a first time-period during which the ODT activation signal is in an active state, generated by being conveyed via the second delay line in which the equivalent delay amount has been set.

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Номер записи: 91
08-02-2018 дата публикации

SEMICONDUCTOR DEVICES AND INTEGRATED CIRCUITS INCLUDING THE SAME

Номер: US20180040361A1
Автор: Kim Jaeil, KWON Kihun
Принадлежит: SK HYNIX INC.

An integrated circuit may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to output a chip section signal and command/address signals. The second semiconductor device may be configured to enter a power-down operation based on the chip section signal and the command/address signals. The second semiconductor device may be configured to interrupt input of a first group of the command/address signals during the power-down operation. The second semiconductor device may be configured to selectively perform an on-die termination (ODT) operation according to a level combination of a second group of the command/address signals. 1. An integrated circuit comprising:a first semiconductor device configured to output a chip section signal and command and address (command/address) signals; anda second semiconductor device configured to enter a power-down operation based on the chip section signal and the command/address signals, configured to interrupt input of a first group of the command/address signals during the power-down operation, and configured to selectively perform an on-die termination (ODT) operation according to a level combination of a second group of the command/address signals.2. The integrated circuit of claim 1 ,wherein the second semiconductor device performs the ODT operation during the power-down operation if the second group of the command/address signals has a first level combination; andwherein the second semiconductor device does not perform the ODT operation if a level combination of the second group of the command/address signals is different from the first level combination.3. The integrated circuit of claim 1 ,wherein the second semiconductor device enters the power-down operation if a third group of the command/address signals has a second level combination; andwherein the second semiconductor device ends the power-down operation if the third group of the command/address signals ...

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Номер записи: 92
08-02-2018 дата публикации

Nonvolatile memory devices and memory systems

Номер: US20180040362A1
Автор: Dong-Hun Kwak, Hee-Won Lee, Hee-Woong Kang, Jun-Ho SEO
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.

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Номер записи: 93
12-02-2015 дата публикации

System and method of page buffer operation for memory devices

Номер: US20150046639A1
Автор: Hakjune Oh, Hong Beom Pyeon, Jin-Ki Kim
Принадлежит: Conversant Intellectual Property Management Inc, Mosaid Technologies Inc

Systems and methods are provided for using page buffers of memory devices connected to a memory controller through a common bus. A page buffer of a memory device is used as a temporary cache for data which is written to the memory cells of the memory device. This can allow the memory controller to use memory devices as temporary caches so that the memory controller can free up space in its own memory.

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Номер записи: 94
24-02-2022 дата публикации

MEMORY DEVICE FOR SUPPORTING COMMAND BUS TRAINING MODE AND METHOD OF OPERATING THE SAME

Номер: US20220059148A1
Автор: HA KYUNG-SOO, KIM Si-hong, Kim Young-Hun, Oh Tae-Young
Принадлежит:

There are provided a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode. 1. A memory controller configured to control a command bus training (CBT) operation of a memory device , the memory controller comprising:a clock terminal configured to transmit a clock signal;a data clock terminal configured to transmit a data clock signal;a first data terminal configured to transmit a first data signal;a plurality of command/address terminals configured to transmit a command bus training (CBT) pattern during the CBT operation, the CBT pattern comprising a plurality of command/address signals; anda plurality of second data terminals configured to transmit second data signals, the plurality of second data terminals being in one-to-one correspondence with the command/address signals during the CBT operation,wherein the memory controller is configured to:send a first logic level of the first data signal to the memory device at one of rising edge and falling edge of the data clock signal and make the memory device enter a command bus training (CBT) mode;send logic levels of the CBT pattern to the memory device at one of rising edge and falling edge of the clock signal and receive the CBT pattern output by the memory ...

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Номер записи: 95
24-02-2022 дата публикации

Three-dimensional memory device with static random-access memory

Номер: US20220059150A1
Автор: Chun Yuan Hou, Yue Ping Li
Принадлежит: Yangtze Memory Technologies Co Ltd

Embodiments of 3D memory devices with a static random-access memory (SRAM) and fabrication methods thereof are disclosed herein. In certain embodiments, the 3D memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes an array of SRAM cells and a first bonding layer, and the second semiconductor structure includes an array of 3D NAND memory strings and a second bonding layer. The first semiconductor structure is attached with the second semiconductor structure through the first bonding layer and the second bonding layer. The array of 3D NAND memory strings and the array of SRAM cells are coupled through a plurality of bonding contacts in the first bonding layer and the second bonding layer and are arranged at opposite sides of the plurality of bonding contacts.

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Номер записи: 96
24-02-2022 дата публикации

Tracking and refreshing state metrics in memory sub-systems

Номер: US20220059179A1
Автор: Bruce A. Liikanen, Michael Sheperek, Steven Michael Kientz
Принадлежит: Micron Technology Inc

Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, responsive to detecting a triggering event, selecting a family of memory blocks of the memory device, the selected family being associated with a set of bins, each bin associated with a plurality of read voltage offsets to be applied to base read voltages during read operations. The operations performed by the processing device further include calibration operations to determine data state metric values characterizing application of read voltage offsets of various bins. The operations performed by the processing device further include identifying, based on the determined data state metrics, a target bin and associating the selected family with the target bin.

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Номер записи: 97
06-02-2020 дата публикации

MEMORY SYSTEM AND METHOD OF OPERATING THE SAME

Номер: US20200042251A1
Автор: KIM Kwang Su
Принадлежит:

Provided herein may be a memory system and a method of operating the same. The method of operating a memory system may include receiving a first program command, and performing an operation corresponding to the first program command, receiving a second program command while performing the operation corresponding to the first program command, delaying setting of a queue status register for the second program command by a first wait time, receiving a third read command before the first wait time elapses, and setting the queue status register for the third read command before setting the queue status register for the second program command. 1. A memory controller controlling a memory device , the memory controller , comprising:a queue status register configured to store operation commands according to an order provided from a host, wherein the operation commands include a write command and a read command; anda command execution control unit configured to control the queue status register to set a status of an operation command to be performed among the operation commands as a set status and to set the status of the operation command as a clear status after the memory device starts to perform an operation corresponding to the operation command,wherein the command execution control unit sets a status of the read command to the set status prior to the write command for a predetermined time since the status of the operation command to be performed is set to the clear status.2. The memory controller of claim 1 , wherein the predetermined time is determined based on an operation time of the operation.3. The memory controller of claim 1 , wherein the command execution control unit sets a status of a next operation command to the set status according to the order provided from the host after the predetermined time.4. The memory controller of claim 1 , wherein the predetermined time is shorter than an operation time of the operation.5. The memory controller of claim 1 , wherein ...

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Номер записи: 98
07-02-2019 дата публикации

PERIODIC CALIBRATIONS DURING MEMORY DEVICE SELF REFRESH

Номер: US20190043557A1
Автор: COX Christopher E., NALE Bill
Принадлежит:

A memory device is described. The memory device includes logic circuitry to perform calibrations of resistive network terminations and data drivers of the memory device while the memory device is within a self refresh mode. 1. A memory controller , comprising:logic circuitry to command to a memory device to perform calibrations of resistive network terminations and data drivers of the memory device while the memory device is within a self refresh mode.2. The memory controller of wherein the logic circuitry is to set a flag within a mode register of the memory device that enables the performing of the calibrations while the memory device is within the self refresh mode.3. The memory controller of wherein the logic circuitry is to not send the memory device a command to calibrate the resistive network terminations and data drivers upon exit of the self refresh mode because the memory has been commanded to perform the calibrations.4. The memory controller of wherein the logic circuitry is to send the memory device a first command to exit the self refresh mode and a second command to latch settings of the calibrations.5. The memory controller of wherein the logic circuitry is to check a register of the memory device that contains information that indicates whether a most recent one of the calibrations was successfully performed claim 1 , and claim 1 , if a most recent one of the calibrations was not successfully performed claim 1 , the logic circuitry is to command the memory device to perform a calibration of the resistive network terminations and data drivers as part of the memory device's transition out of the self refresh mode even though the memory device was commanded to perform the calibrations during the self refresh mode.6. A memory device claim 1 , comprising:logic circuitry to perform calibrations of resistive network terminations and data drivers of the memory device while the memory device is within a self refresh mode.7. The memory device of wherein the ...

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Номер записи: 99
03-03-2022 дата публикации

Systems and Methods for Controlling Power Assertion In a Memory Device

Номер: US20220068330A1
Автор: JAIN Sanjeev Kumar
Принадлежит:

Systems and methods are provided for controlling a sleep operation for a memory array. A memory system may include a memory array with a memory cell and a word line driver, the memory array receiving a word line clock signal that enables and disables memory read and write operations of the memory cell. The memory array may further including a switching circuit coupled between the word line driver and a power source, the switching circuit being controlled by a local word line sleep signal to turn power to the word line driver on and off. A latch circuit may generate the local word line sleep signal in response to a delayed clock signal and one or more power management control signals. The word line clock signal and the delayed clock signal may both being generated as a function of a memory clock signal. The latch circuit may synchronize the local word line sleep signal with the delayed clock signal such that the local word line sleep signal is prevented from turning off power to the word line driver until memory read and write operations of the memory cell are disabled by the word line clock signal. 1. A memory system , comprising:a memory array including a memory cell and a word line driver, the memory array receiving a word line clock signal that enables and disables memory read and write operations of the memory cell;the memory array further including a switching circuit coupled between the word line driver and a power source, the switching circuit being controlled by a local word line sleep signal to turn power to the word line driver on and off; anda latch circuit that generates the local word line sleep signal in response to a delayed clock signal and one or more power management control signals,the word line clock signal and the delayed clock signal both being generated as a function of a memory clock signal,wherein the latch circuit synchronizes the local word line sleep signal with the delayed clock signal such that the local word line sleep signal is ...

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Номер записи: 100