Halbleiterstruktur und Verfahren

Verfahren zum Herstellen eines Halbleiterbauelements, wobei das Verfahren umfasst: Kombinieren eines Halbleiterrohmaterials und eines leerstellenverstärkenden Rohmaterials, um eine kombinierte Rohmaterialmischung auszubilden; und Schmelzen der Rohmaterialmischung und Kristallisieren der dabei entstehenden Halbleiterschmelze zu einem Halbleiter-Ingot mit einer Lehrstellenkonzentration von 1010/cm3 bis 1015/cm3; Trennen eines Halbleiterwafers oder mehrerer Halbleiterwafer von dem Halbleiter-Ingot; Ausbilden von Isolierbereichen innerhalb eines der Halbleiterwafer durch Abscheiden eines dielektrischen Materials innerhalb eines Grabens in dem Halbleiterwafer; und Tempern des Halbleiterwafers mit dem dielektrischen Material, wobei der Halbleiterwafer in einer Umgebung von Wasserstoff, Helium, Argon oder Kombinationen derselben gehalten wird und das Tempern des dielektrischen Materials bulk micro defects innerhalb des Halbleiterwafers erzeugt, wobei das Tempern die Schritte aufweist: – Erhöhen ...

SEMICONDUCTOR INGOT INSPECTING METHOD AND APPARATUS, AND LASER PROCESSING APPARATUS

Method for reducing heavy metal and vaporific defects through washing after BSD

The invention provides a method for reducing heavy metal and vaporific defects through washing after BSD. After a BSD procedure, washing is performed by adopting the following steps that 1, pre-washing is performed by using a pre-washing solution which comprises ammonia water, hydrogen peroxide and deionized water; 2, washing is performed by using distilled water; 3, soaking and cleaning with a primary cleaning solution are performed, wherein the primary cleaning solution comprises hydrofluoric acid, citric acid and deionized water, and the volume ratio of the hydrofluoric acid to the citric acid to the deionized water is 15: (3-5): (55-57); 4, soaking and cleaning with a secondary cleaning solution are performed, wherein the secondary cleaning solution comprises hydrochloric acid, hydrogen peroxide and deionized water, and the ratio of the hydrochloric acid to the hydrogen peroxide is 1: 1; 5, cleaning with distilled water is performed; and 6, spin-drying by adopting a silicon wafer spin-drying ...

ADHESIVE FILM, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE

SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD, AND STORAGE MEDIUM

A substrate processing apparatus includes a liquid processing tank, a movement mechanism, an ejector, and a controller. The liquid processing tank stores a processing liquid. The movement mechanism moves a plurality of substrates immersed in the liquid processing tank to above the liquid surface of the processing liquid. The ejector ejects a vapor of an organic solvent toward portions of the plurality of substrates exposed from the liquid surfaces. The controller moves up the ejection position of the vapor of the organic solvent by the ejection unit as the plurality of substrates are moved up.

円形状研磨パッド

The wafer and wafer generation method of generating device

Improved bearing head film

SEMICONDUCTOR WAFER AND METHOD FOR MANUFACTURING SAME

Processing gas generation device, processing gas generation method, substrate processing method and recording medium

SiC WAFER PRODUCING METHOD

SUBSTRATE PROCESSING SYSTEM AND SUBSTRATE PROCESSING METHOD

A substrate processing system includes: a batch-type processing part that collectively processes a lot including substrates arranged at a first pitch; a single-substrate-type processing part that processes the substrates of the lot one by one; and an interface part that delivers the substrates between the batch-type processing part and the single-substrate-type processing part. The batch-type processing part includes a processing bath that stores a processing solution having a lump shape or a mist shape, a first holder that holds the substrates arranged at the first pitch, and a second holder that receives the substrates arranged at a second pitch from the first holder in the processing solution. The interface part includes a transfer part that transfers the substrates held separately by the first and second holders in the processing solution, from the batch-type processing part to the single-substrate-type processing part.

CARRIER HEAD MEMBRANE WITH A BEAD

A method and apparatus for planarizing a substrate are provided. A substrate carrier head with an improved cover for holding the substrate securely is provided. The cover may have a bead that is larger than the recess into which it fits, such that the compression forms a conformal seal inside the recess. The bead may also be left uncoated to enhance adhesion of the bead to the surface of the groove. The surface of the cover may be roughened to reduce adhesion of the substrate to the cover without using a non-stick coating.

GROUP III NITRIDE WAFERS AND FABRICATION METHOD AND TESTING METHOD

The invention provides, in one instance, a group III nitride wafer sliced from a group III nitride ingot, polished to remove the surface damage layer and tested with x-ray diffraction. The x-ray incident beam is irradiated at an angle less than 15 degree and diffraction peak intensity is evaluated. The group III nitride wafer passing this test has sufficient surface quality for device fabrication. The invention also provides, in one instance, a method of producing group III nitride wafer by slicing a group III nitride ingot, polishing at least one surface of the wafer, and testing the surface quality with x-ray diffraction having an incident beam angle less than 15 degree to the surface. The invention also provides, in an instance, a test method for testing the surface quality of group III nitride wafers using x-ray diffraction having an incident beam angle less than 15 degree to the surface.

HALBLEITERSUBSTRAT-RISSMINDERUNGSSYSTEME UND VERWANDTE VERFAHREN

Implementierungen von Verfahren zum Ausheilen eines Risses in einem Halbleitersubstrat können das Identifizieren eines Risses in einem Halbleitersubstrat und das Erwärmen in einem Bereich des Halbleitersubstrats einschließlich des Risses, bis der Riss ausgeheilt ist, einschließen.

Halbleiterwafer und Herstellungsverfahren dafür

Die vorliegende Erfindung sieht einen Halbleiterwafer mit einem Durchhang vor, der an einem äußeren Umfang während des Polierens gebildet wird, wobei eine Versetzung des Halbleiterwafers in der Dickenrichtung 100 nm oder weniger zwischen der Mitte und der äußeren peripheren Durchhangausgangsstelle des Halbleiterwafers ist, und die Mitte des Halbleiterwafers eine konvexe Form hat, der Betrag an äußerem peripherem Durchhang des Halbleiterwafers 100 nm oder weniger ist, und die äußere periphere Durchhangausgangsstelle von einem äußeren peripheren Abschnitt des Halbleiterwafers zur Mitte oder 20 mm oder mehr vom äußeren peripheren Ende des Halbleiterwafers zur Mitte entfernt ist, wobei der äußere periphere Abschnitt ein Messobjekt von ESFQR ist. Im Ergebnis besteht eine Aufgabe darin, einen Halbleiterwafer, mit dem mehrere Ebenheitsindices, z. B. SFQR, ESFQR, ZDD, ROA, GBIR, SBIR und andere, gleichzeitig unter denselben Verarbeitungsbedingungen erfüllt werden können, und ein Herstellungsverfahren ...

THERMAL PLATE WITH PLANAR THERMAL ZONES FOR SEMICONDUCTOR PROCESSING

Improved carrier head membrane

Apparatus and method for wafer bonding

An apparatus and a method for wafer bonding are provided. The apparatus comprises a transfer module and a plasma module. The transfer module is configured to transfer a semiconductor wafer. The plasma module is configured to perform a plasma operation and a reduction operation to a surface of the semiconductor wafer to convert metal oxides on the surface of the semiconductor wafer to the metal.

Packaging method, panel module, wafer package and chip package

Embodiments of the present disclosure disclose a packaging method, panel module, wafer package and chip package. The semiconductor element packaging method includes: providing at least one wafer, the wafer includes a first surface, a second surface and a lateral surface, wherein the second surface is opposite to the first surface, the lateral surface connects the first surface and the second surface, and the first surface is the active surface; and forming a connecting portion which surrounds the wafer at the lateral surface of the at least one wafer so as to make the wafer and the connecting portion form a panel module, the connecting portion includes a third surface and a fourth surface, the third surface is at the same side of the first surface of the wafer, the fourth surface is at the same side of the second surface of the wafer, the third surface and the first surface form a to-be-processed surface of the panel module. The packaging method according to the embodiments of the present ...

THERMAL PLATE WITH PLANAR THERMAL ZONES FOR SEMICONDUCTOR PROCESSING

A thermal plate for a substrate support assembly in a semiconductor plasma processing apparatus, comprises multiple independently controllable planar thermal zones arranged in a scalable multiplexing layout, and electronics to independently control and power the planar heater zones. Each planar thermal zone uses at least one Peltier device as a thermoelectric element. A substrate support assembly in which the thermal plate is incorporated includes an electrostatic clamping electrode layer and a temperature controlled base plate. Methods for manufacturing the thermal plate include bonding together ceramic or polymer sheets having planar thermal zones, positive, negative and common lines and vias.

DIAMOND SUBSTRATE PRODUCING METHOD

A diamond substrate producing method includes a belt-shaped separation layer forming step of applying a laser beam to a diamond ingot as relatively moving the ingot and a focal point of the laser beam in a [110]-direction perpendicular to a (110)-plane, thereby forming a belt-shaped separation layer extending in the [110]-direction inside the ingot, an indexing step of relatively moving the ingot and the focal point in an indexing direction parallel to a (001)-plane and perpendicular to the [110]-direction, a planar separation layer forming step of repeating the belt-shaped separation layer forming step and the indexing step to thereby form a planar separation layer parallel to the (001)-plane inside the ingot, the planar separation layer being composed of a plurality of belt-shaped separation layers arranged side by side in the indexing direction, and a separating step of separating a substrate from the diamond ingot along the planar separation layer.

HALBLEITERINGOT-UNTERSUCHUNGSVERFAHREN UND -VORRICHTUNG UND LASERBEARBEITUNGSVORRICHTUNG

Es wird hierin ein Untersuchungsverfahren für einen Halbleiteringot offenbart, bei dem modifizierte Schichten parallel zu einer oberen Fläche des Ingots und Risse, die sich von jeder modifizierten Schicht erstrecken, zuvor als ein Trennstartpunkt ausgebildet werden. Das Untersuchungsverfahren schließt einen Lichtaufbringschritt mit einem Aufbringen von Licht von einer Lichtquelle auf die obere Fläche des Ingots, wobei das Licht mit einem vorbestimmten Einfallswinkel auf die obere Fläche trifft, einen Ausbildungsschritt für ein projiziertes Bild mit einem Reflektieren des Lichts an der oberen Fläche des Ingots, um reflektiertes Licht zu erhalten, und dann einem Ausbilden eines projizierten Bilds aus dem reflektierten Licht, wobei das projizierte Bild die Hervorhebung der Unebenheiten zeigt, die aufgrund des Ausbildens der modifizierten Schichten und der Risse im Inneren des Ingots an der oberen Fläche des Ingots erzeugt werden, einen Abbildungsschritt mit einem Erfassen des projizierten ...

WAFERHERSTELLUNGSVERFAHREN UND LASERBEARBEITUNGSVORRICHTUNG

Ein Waferherstellungsverfahren schließt einen Facettenbereichserfassungsschritt mit einem Erfassen eines Facettenbereichs von einer oberen Fläche eines SiC-Ingots, einen Koordinateneinstellschritt mit einem Einstellen der X- und Y-Koordinaten mehrerer Punkte, die auf der Grenze zwischen dem Facettenbereich und einem Nicht-Facettenbereich in einer XY-Ebene liegen, und einen Zuführschritt mit einem Einstellen eines Brennpunkts eines Laserstrahls, der eine Transmissionswellenlänge für SiC aufweist, auf eine von der oberen Fläche des SiC-Ingots aus vorbestimmte Tiefe im Inneren des SiC-Ingots, wobei die vorbestimmte Tiefe mit der Dicke eines herzustellenden SiC-Wafers korrespondiert, als Nächstes einem Aufbringen des Laserstrahls von einer Fokussiereinheit in einer Laserbearbeitungsvorrichtung auf den SiC-Ingot und einem relativen Bewegen des SiC-Ingots und des Brennpunkts in einer X-Richtung parallel zu der X-Achse in der XY-Ebene ein, wodurch eine bandförmige Trennschicht, die sich in der ...

SUBSTRATE CARRIER DETERIORATION DETECTION AND REPAIR

IMPROVED CARRIER HEAD MEMBRANE

SEMICONDUCTOR WAFER AND MANUFACTURING METHOD THEREOF

The present invention provides a semiconductor wafer in which sagging is formed on the outer circumference during polishing, the semiconductor wafer being characterized in that: the amount of displacement of the semiconductor wafer in the thickness direction between the center of the semiconductor wafer and the starting position of the outer circumference sagging is equal to or less than 100 nm; the center of the semiconductor wafer has a convex profile; the amount of outer circumference sagging of the semiconductor wafer is equal to or less than 100 nm; and the starting position of the outer circumference sagging is at least 20 mm further towards the center from the outer circumferential edge of the semiconductor wafer or further towards the center than the outer circumferential section of the semiconductor wafer that is to be measured for ESFQR. The purpose of the present invention is to thereby provide: a semiconductor wafer that can simultaneously satisfy a plurality of flatness indicators ...

DIAMOND SUBSTRATE PRODUCING METHOD

METHODS AND APPARTUS FOR TRANSFER OF FILMS AMONG SUBSTRATES

A method is disclosed which includes: forming at least one layer of material on at least part of a surface of a first substrate, wherein a first surface of the at least one layer of material is in contact with the first substrate thereby defining an interface; attaching a second substrate to a second surface of the at least one layer of material; forming bubbles at the interface; and applying mechanical force; whereby the second substrate and the at least one layer of material are jointly separated from the first substrate. Related arrangements are also described.

Wafer assembly with carrier wafer

A wafer assembly includes a process wafer and a carrier wafer. Integrated circuits are formed on the process wafer. The carrier wafer is bonded to the process wafer. The carrier wafer has at least one alignment mark.

SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SAME

A substrate capable of achieving a lowered probability of defects produced in a step of forming an epitaxial film or a semiconductor element, a semiconductor device including the substrate, and a method of manufacturing a semiconductor device are provided. A substrate is a substrate having a front surface and a back surface, in which at least a part of the front surface is composed of single crystal silicon carbide, the substrate having an average value of surface roughness Ra at the front surface not greater than 0.5 nm, a standard deviation of that surface roughness Ra not greater than 0.2 nm, an average value of surface roughness Ra at the back surface not smaller than 0.3 nm and not greater than 10 nm, standard deviation of that surface roughness Ra not greater than 3 nm, and a diameter D of the front surface not smaller than 110 mm.

Method for utilizing ultraviolet light to activate bonded laminated glass and other materials

DEFECT CAPPING FOR REDUCED DEFECT DENSITY EPITAXIAL ARTICLES

반도체 처리를 위한 평면형 열적 존을 갖는 열적 플레이트

... 반도체 플라즈마 처리 장치 내의 기판 지지 어셈블리를 위한 열적 플레이트는,스케일링 가능한 다중화 층 내에 배열된 다중의 독립적으로 제어가능한 평면형 열적 존과, 상기 평면형 열적 존을 독립적으로 제어하고 전력을 공급하기 위한 전자 기술을 포함한다. 각각의 평면형 열적 존은 열전기 엘리먼트로서 적어도 하나의 펠티에 디바이스를 사용한다. 상기 열적 플레이트가 합체된 기판 지지 어셈블리는 정전기적 클램핑 전극 층 및 온도 제어형 베이스 플레이트를 포함한다. 상기 열적 플레이트를 제조하는 방법은 평면형 열적 존을 갖는 세라믹 또는 폴리머 시트와, 양 전압 라인, 음 전압 라인 및 공통 라인과, 비아 (via) 를 포함한다.

SiC substrate evaluation method and method for manufacturing SiC epitaxial wafer

In a SiC substrate evaluation method, a bar-shaped stacking fault is observed by irradiating a surface of a SiC substrate before stacking an epitaxial layer with excitation light and extracting light having a wavelength range from equal to or greater than 405 nm and equal to or less than 445 nm among photoluminescence light beams emitted from the first surface.

Package structure and method of fabricating the same

A package structure including at least one conductive plate, a redistribution layer, a first semiconductor chip, a conductive shielding structure and an insulating encapsulant is provided. The first semiconductor chip is sandwiched in between the at least one conductive plate and the redistribution layer, wherein the first semiconductor chip is disposed on the at least one conductive plate and electrically connected to the redistribution layer. The conductive shielding structure is sandwiched in between the at least one conductive plate and the redistribution layer, wherein the conductive shielding structure surrounds the first semiconductor chip and electrically connects the at least one conductive plate with the redistribution layer. The insulating encapsulant is disposed on the redistribution layer, encapsulating the first semiconductor chip, the conductive shielding structure, and surrounding the at least one conductive plate.

SiC SUBSTRATE EVALUATION METHOD AND METHOD FOR MANUFACTURING SiC EPITAXIAL WAFER

In a SiC substrate evaluation method, a bar-shaped stacking fault is observed by irradiating a surface of a SiC substrate before stacking an epitaxial layer with excitation light and extracting light having a wavelength range from equal to or greater than 405 nm and equal to or less than 445 nm among photoluminescence light beams emitted from the first surface.

METHOD OF PRODUCING WAFER AND APPARATUS FOR PRODUCING WAFER

A method of producing a wafer includes forming a peel-off layer in a hexagonal single-crystal ingot by applying a laser beam having a wavelength transmittable through the ingot while positioning a focal point of the laser beam in the ingot at a depth corresponding to the thickness of a wafer to be produced from an end face of the ingot, generating ultrasonic waves from an ultrasonic wave generating unit positioned in facing relation to the wafer to be produced across a water layer interposed therebetween, thereby to break the peel-off layer, and detecting when the wafer to be produced is peeled off the ingot based on a change that is detected in the height of an upper surface of the wafer to be produced by a height detecting unit positioned above the upper surface of the wafer to be produced across the water wafer interposed therebetween.

Adhesive film, method of manufacturing semiconductor device, and semiconductor device

Provided is an adhesive film that enables manufacturing of a high quality semiconductor device with good yield ratio, and related methods of manufacturing a semiconductor device, and semiconductor devices. Provided is an adhesive film for embedding a first semiconductor element fixed to an adherend and fixing a second semiconductor element that is different from the first semiconductor element to the adherend, wherein the adhesive film has a thickness T that is larger than a thickness T1 of the first semiconductor element, and the adherend and the first semiconductor element are connected by wire bonding and a difference between the thickness T and the thickness T1 is 40 m or more and 260 m or less, or the adherend and the first semiconductor element are connected by flip-chip bonding and a difference between the thickness T and the thickness T1 is 10 m or more and 200 m or less.

Method for extreme ultraviolet electrostatic chuck with reduced clamp effect

The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a front surface and a backside surface; integrated circuit features formed on the front surface of the semiconductor substrate; and a polycrystalline silicon layer disposed on the backside surface of the semiconductor substrate.

Large aluminum nitride crystals with reduced defects and methods of making them

Reducing the microvoid (MV) density in AlN ameliorates numerous problems related to cracking during crystal growth, etch pit generation during the polishing, reduction of the optical transparency in an AlN wafer, and, possibly, growth pit formation during epitaxial growth of AlN and/or AlGaN. This facilitates practical crystal production strategies and the formation of large, bulk AlN crystals with low defect densities-e.g., a dislocation density below 104 cm-2 and an inclusion density below 104 cm-3 and/or a MV density below 104 cm-3.

SUBSTRATE, SEMICONDUCTOR DEVICE, METHOD FOR PRODUCING SUBSTRATE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Provided are: a substrate which is capable of reducing the failure probability in a process for forming an epitaxial film or a semiconductor element; a semiconductor device which uses the substrate; and a method for producing a semiconductor device. A substrate (1) has a front surface and a back surface, and at least a part of the front surface is formed of single crystal silicon carbide. The surface roughness (Ra) of the front surface has an average of 0.5 nm or less, and the surface roughness (Ra) has a standard deviation (σ) of 0.2 nm or less. The surface roughness (Ra) of the back surface has an average of from 0.3 nm to 10 nm (inclusive), and the surface roughness (Ra) has a standard deviation (σ) of 3 nm or less. The front surface has a diameter (D) of 110 mm or more.

SANDBLASTING AGENT, WAFER TREATED WITH THE SAME, AND METHOD OF TREATMENT WITH THE SAME

L'invention concerne un agent de sablage qui empêche l'encrassement par ions métalliques et un procédé de sablage d'une galette de silicium au moyen dudit agent. Le procédé consiste à utiliser un agent de sablage contenant un agent chélateur. L'agent chélateur est sélectionné, par exemple, parmi les composés de (1) à (4) et les sels de ces composés: 1) acide de nitriloacétate (NTA); (2) acide éthylène diaminetétracétique (EDTA); (3) acide pentacétique de diéthyle diamine-N,N,N'',N'' (DTPA); et (4) acide cyclohexane diaminetétracétique (CyDTA).

Negative capacitance FET with improved reliability performance

A negative capacitance device includes a semiconductor layer. An interfacial layer is disposed over the semiconductor layer. An amorphous dielectric layer is disposed over the interfacial layer. A ferroelectric layer is disposed over the amorphous dielectric layer. A metal gate electrode is disposed over the ferroelectric layer. At least one of the following is true: the interfacial layer is doped; the amorphous dielectric layer has a nitridized outer surface; a diffusion-barrier layer is disposed between the amorphous dielectric layer and the ferroelectric layer; or a seed layer is disposed between the amorphous dielectric layer and the ferroelectric layer.

CARRIER HEAD MEMBRANE WITH A BEAD

A method and apparatus for planarizing a substrate are provided. A substrate carrier head with an improved cover for holding the substrate securely is provided. The cover may have a bead that is larger than the recess into which it fits, such that the compression forms a conformal seal inside the recess. The bead may also be left uncoated to enhance adhesion of the bead to the surface of the groove. The surface of the cover may be roughened to reduce adhesion of the substrate to the cover without using a non-stick coating.

SIC-WAFERHERSTELLUNGSVERFAHREN

Es wird hierin ein SiC-Waferherstellungsverfahren zum Herstellen eines SiC-Wafers aus einem SiC-Einkristallingot offenbart. Das SiC-Waferherstellungsverfahren schließt einen Waferherstellungsschritt mit einem Trennen eines Teils des Ingots entlang einer Trennschicht als Interface ein. Der Waferherstellungsschritt schließt die Schritte eines Eintauchens des Ingots in eine Flüssigkeit und eines Aufbringens der Ultraschallwelle von einem Ultraschallschwinger über die Flüssigkeit auf den Ingot ein, wobei die Ultraschallwelle eine Frequenz größer als oder gleich wie eine kritische Frequenz nahe der Eigenfrequenz des Ingots aufweist.

SELF-COMPENSATING HYDROSTATIC FLATTENING OF SEMICONDUCTOR SUBSTRATES

Semiconductor device and method for providing the same

IMPROVED CARRIER HEAD MEMBRANE

... 기판을 평탄화하기 위한 방법 및 장치가 제공된다. 기판을 단단히 지지하기 위한 향상된 커버를 구비한 기판 캐리어 헤드가 제공된다. 이러한 커버는 그것 내로 피팅되는 리세스보다 큰 비드를 가질 수 있어서, 압축이 리세스 내부에서 컨포멀 밀봉을 형성한다. 또한, 헤드는 그루브의 표면에 대한 비드의 부착을 향상시키도록 코팅되지 아니한 채로 남겨질 수 있다. 커버의 표면은 비교착(non-stick) 코팅을 이용하지 아니하면서 커버에 대한 기판의 부착을 감소시키도록 거칠어질 수 있다.

SILICON WAFER AND SEMICONDUCTOR DEVICE

Vertical wafer boat

Semiconductor Device Having a Defined Oxygen Concentration

A method for manufacturing a substrate wafer 100 includes providing a device wafer (110) having a first side (111) and a second side (112); subjecting the device wafer (110) to a first high temperature process for reducing the oxygen content of the device wafer (110) at least in a region (112a) at the second side (112); bonding the second side (112) of the device wafer (110) to a first side (121) of a carrier wafer (120) to form a substrate wafer (100); processing the first side (101) of the substrate wafer (100) to reduce the thickness of the device wafer (110); subjecting the substrate wafer (100) to a second high temperature process for reducing the oxygen content at least of the device wafer (110); and at least partially integrating at least one semiconductor component (140) into the device wafer (110) after the second high temperature process.

SELF-COMPENSATING HYDROSTATIC FLATTENING OF SEMICONDUCTOR SUBSTRATES

SiC ingot slicing method

Silicon wafer and semiconductor device

Disclosed is a silicon wafer wherein a plurality of terraces are formed on the surface with steps which are formed of a monatomic layer. There is no slip line in the wafer.

Method for manufacturing semiconductor device

SUBSTRATE CARRIER DETERIORATION DETECTION AND REPAIR

Method for protecting wafer, protective member and method for producing protective member which can prevent the quality degradation of a wafer

This invention provides a method for protecting a wafer, a protective member and a method for producing a protective member for preventing the quality degradation of a wafer. According to the present invention, a method for protecting a wafer is provided, wherein a sheet-shaped protective member 22a is disposed on a surface of the wafer 10 to protect the wafer. The method for protecting a wafer at least comprises the following steps: a sheet preparation step of preparing a polyolefin-based sheet or a polyester-based sheet as the base material of the protective member 22a; an adhesive generating step of heating a surface of the sheet 20 and generating an adhesive force; and a sheet crimping step of laying the surface of the sheet 20 that has the generated adhesive force on the surface (front surface 10a) of the wafer 10 to be protected, and applying a pushing force to press the sheet 20 on the front surface 10a of the wafer 10.

Thermal plate and substrate support assembly comprising the thermal plate and method for manufacturing the thermal plate

A thermal plate for a substrate support assembly in a semiconductor plasma processing apparatus, comprises multiple independently controllable planar thermal zones arranged in a scalable multiplexing layout, and electronics to independently control and power the planar heater zones. Each planar thermal zone uses at least one Peltier device as a thermoelectric element. A substrate support assembly in which the thermal plate is incorporated includes an electrostatic clamping electrode layer and a temperature controlled base plate. Methods for manufacturing the thermal plate include bonding together ceramic or polymer sheets having planar thermal zones, positive, negative and common lines and vias.

Carbon-doped silicon single crystal wafer and method for manufacturing the same

A method for manufacturing a carbon-doped silicon single crystal wafer, including steps of: preparing a silicon single crystal wafer not doped with carbon; performing a first RTA treatment on the silicon single crystal wafer in an atmosphere containing compound gas; performing a second RTA treatment at a higher temperature than the first RTA treatment; cooling the silicon single crystal wafer after the second RTA treatment; and performing a third RTA treatment. The crystal wafer is modified to a carbon-doped silicon single crystal wafer, sequentially from a surface thereof: a 3C-SiC single crystal layer; a carbon precipitation layer; a diffusion layer of interstitial carbon and silicon; and a diffusion layer of vacancy and carbon. A carbon-doped silicon single crystal wafer having a surface layer with high carbon concentration and uniform carbon concentration distribution to enable wafer strength enhancement; and a method for manufacturing the carbon-doped silicon single crystal wafer.

Verfahren zur Herstellung von Halbleiterscheiben

Verfahren zur Herstellung von Halbleiterscheiben, wobei ein einkristalliner Stab aus Halbleitermaterial gezogen und mindestens eine Scheibe vom Stab aus Halbleitermaterial abgetrennt wird, wobei die Scheibe einem thermischen Behandlungsverfahren unterworfen wird, bei dem zumindest ein Wärmebehandlungsschritt, der vorzugsweise radial ist, mit einem Temperaturgradient von innen nach außen oder von außen nach innen erfolgt, und eine Untersuchung der Scheibe aus Halbleitermaterial hinsichtlich der Ausbildung von Fehlern im Kristallgitter, sogenannten Stressfeldern, erfolgt.

SELF-COMPENSATING HYDROSTATIC FLATTENING OF SEMICONDUCTOR SUBSTRATES

SELF-COMPENSATING HYDROSTATIC FLATTENING OF SEMICONDUCTOR SUBSTRATES A semiconductive substrate (1), such as a silicon wafer, is mounted on a baseplate (3), for inclusion in an optical device such as a liquid crystal light valve. An optical flat (9) presses the top surface of the silicon wafer toward the baseplate and against a ring seal (5) surrounding a fluid adhesive (7). The fluid adhesive hydrostatically distributes the force of compression to guarantee optical flatness and selfcompensation for the amount fluid adhesive surrounded by the O-ring. The optical flatness of the semiconductor substrate is limited only by the flatness of the optical flat against which it is compressed. Parallel alignment of the optical flat (9), the substrate (1) and the baseplate (3) is achieved by reflecting a laser beam (20) through the semiconductive substrate and observing the interference fringes therein, while adjusting the relative alignment so as to maximize the distance between fringes.

SELF-COMPENSATING HYDROSTATIC FLATTENING OF SEMICONDUCTOR SUBSTRATES

본딩된 웨이퍼 에지 보호 설계

... 방법은, 웨이퍼 고정 모듈에 의해서, 본딩된 웨이퍼들을 고정하는 단계를 포함한다. 본딩된 웨이퍼들 사이의 갭이 에지를 따라 보호 물질로 충진된다.

캐리어 헤드 멤브레인

... 기판을 평탄화하기 위한 방법 및 장치가 제공된다. 기판을 단단히 지지하기 위한 향상된 커버를 구비한 기판 캐리어 헤드가 제공된다. 이러한 커버는 그것 내로 피팅되는 리세스보다 큰 비드를 가질 수 있어서, 압축이 리세스 내부에서 컨포멀 밀봉을 형성한다. 또한, 헤드는 그루브의 표면에 대한 비드의 부착을 향상시키도록 코팅되지 아니한 채로 남겨질 수 있다. 커버의 표면은 비교착(non-stick) 코팅을 이용하지 아니하면서 커버에 대한 기판의 부착을 감소시키도록 거칠어질 수 있다.

THERMAL PLATE WITH PLANAR THERMAL ZONES FOR SEMICONDUCTOR PROCESSING

Method of cleaning and micro-etching semiconductor wafers

A method of simultaneously cleaning inorganic and organic contaminants from semiconductor wafers and micro-etching the semiconductor wafers. After the semiconductor wafers are cut or sliced from ingots, they are contaminated with cutting fluid as well as metal and metal oxides from the saws used in the cutting process. Aqueous alkaline cleaning and micro-etching solutions containing alkaline compounds and mid-range alkoxylates are used to simultaneously clean and micro-etch the semiconductor wafers.

Process for producing semiconductor wafers

SUBSTRATE HOLDING APPARATUS, SUBSTRATE SUCTION DETERMINATION METHOD, SUBSTRATE POLISHING APPARATUS, SUBSTRATE POLISHING METHOD, METHOD OF REMOVING LIQUID FROM UPPER SUFACE OF WAFER TO BE POLISHED, ELASTIC FILM FOR PRESSING WAFER AGAINST POLISHING PAD, SUBSTRATE RELEASE METHOD, AND CONSTANT AMOUNT GAS SUPPLY APPARATUS

A substrate holding apparatus is provided, which includes a top ring main body to which an elastic film having a surface that can suck a substrate can be attached, a first line communicating with a first area of the plurality of areas, a second line communicating with a second area different from the first area of the plurality of areas, a pressure adjuster that can pressurize the first area by feeding fluid into the first area through the first line and can generate negative pressure in the second area through the second line, and a determiner that performs determination of whether or not the substrate is sucked to the elastic film based on a volume of the fluid fed into the first area or a measurement value corresponding to pressure in the first area.

WAFERBEARBEITUNGSVERFAHREN

Ein Waferbearbeitungsverfahren beinhaltet einen Polyolefinfolienbereitstellungsschritt des Positionierens eines Wafers in einer inneren Öffnung eines Ringrahmens und des Vorsehens einer Polyolefinfolie an einer Rückseite des Wafers und an einer Rückseite des Ringrahmens, einen Verbindungsschritt des Erwärmens der Polyolefinfolie während eines Aufbringens eines Drucks auf die Polyolefinfolie, um dadurch den Wafer und den Ringrahmen über die Polyolefinfolie durch ein Thermokompressionsverbinden zu verbinden, einen Teilungsschritt des Aufbringens eines Laserstrahls auf den Wafer, um Teilungsnuten im Wafer auszubilden, wodurch der Wafer in einzelne Bauelementchips geteilt wird, und einen Aufnahmeschritt des Aufnehmens jedes Bauelementchips von der Polyolefinfolie.

Halbleiterstruktur und Verfahren

Ein System und Verfahren zum Bereitstellen von Hilfe für einen Halbleiterwafer wird bereitgestellt. Eine Ausührungsform umfasst Zugeben eines leerstellenverstärkenden Materials während des Ausbilden eines Halbleiter-Ingots, bevor der Halbleiterwafer von dem Halbleiter-Ingot abgetrennt wird. Das leerstellenverstärkende Material bildet innerhalb des Halbleiter-Ingots in einer hohen Dichte Leerstellen aus, und die Leerstellen bilden innerhalb des Halbleiterwafers während Hochtemperaturprozessen, wie etwa Tempern, bulk micro defects aus. Diese bulk micro defects helfen, den Halbleiterwafer während nachfolgenden Verarbeiten zu unterstützen und zu festigen, und helfen beim Reduzieren oder Eliminieren einer Fingerabdrucküberlagerung, die andernfalls auftreten kann.

반도체 웨이퍼의 세정 및 마이크로-에칭방법

... 본 발명은 반도체 웨이퍼의 세정 및 마이크로-에칭방법에 관한 것으로, 더욱 상세하게는 하나 이상의 4급 암모늄 수산화물, 하나 이상의 알칼리 금속 수산화물 및 하나 이상의 중급 알콕실레이트를 포함하는 수성 알칼리성 용액을 충분량으로 적용하여 반도체 웨이퍼로부터 무기 오염물질 및 유기 오염물질을 제거하고, 동시에 반도체 웨이퍼를 마이크로-에칭할 수 있는 방법에 관한 것이다.

Adhesive film, fabricating method of semicondoctor device and semicondoctor device

This invention provides an adhesive film which can fabricate high quality semiconductor device with good throughput yield and a fabricating method of a semiconductor device using the adhesive film, and a semiconductor device fabricated using the same. An adhesive film is used for embedding a first semiconductor device mounted on an object to be adhered and for mounting a second semiconductor device different from the first semiconductor device on the object to be adhered, wherein the adhesive film has a thickness T thicker than a thickness T1 of the first semiconductor device. The object to be adhered is connected to the first semiconductor device by wire bonding, and a difference of thickness between T and T1 is 40 m to 260 m. Or the object to be adhered is connected to the first semiconductor device by a flip chip, and a difference of thickness between T and T1 is 10 m to 200 m.

Panel assembly, wafer package and chip package

SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS

A substrate processing method includes: holding a substrate having a processing target surface and an opposite surface which is opposite to the processing target surface; preheating a center portion of the opposite surface of the substrate; after the preheating, ejecting a sulfuric acid hydrogen peroxide mixture (SPM) to a peripheral edge portion of the processing target surface of the substrate; and after the ejecting, moving an ejection position of the SPM from the peripheral edge portion of the processing target surface to a center portion of the substrate.

Semiconductor device using a silicon wafer with a pattern arrangement

A semiconductor device comprising: a support part; a flexible part, one end of which is supported by the support part; a spindle part supported by the other end of the flexible part; a displacement detection means which detects displacement of the spindle part; and an aperture part arranged adjacent to the spindle part; wherein a plurality of patterns comprised from the aperture part is formed on a silicon wafer parallel to a first direction and a second direction which intersects the first direction, the plurality of patterns include one or more patterns arranged in a straight line in the first direction and the second direction, the plurality of patterns is arranged so that an axis in which a cleavage plane of the silicon wafer and a surface arranged with the pattern on the silicon wafer intersect, and the first direction are different.

SiC ingot slicing method

Disclosed herein is an SiC ingot slicing method including: an initial separation layer formation step for scanning a focal point of a laser beam parallel to an end face of the SiC ingot along a scheduled separation plane, and forming a separation layer at a position at a distance from the end face; a repetition step for sequentially moving, after the initial separation layer formation step, the focal point by the distance equal to the thickness of an SiC plate from the separation layer toward the end face, scanning the focal point parallel to the end face, repeating the formation of the separation layer, and forming the plurality of separation layers; and a separation step for applying an external force to the plurality of separation layers formed by the repetition step, peeling off the SiC plates starting from the separation layers, and acquiring the plurality of SiC plates.

DEFECT CAPPING FOR REDUCED DEFECT DENSITY EPITAXIAL ARTICLES

パターン配置方法並びにシリコンウェハ及び半導体デバイスの製造方法

Material capable of inducing bacterial morphology extension by mechanical stress, and preparation and application thereof

Processing gas generating device, processing gas generating method, substrate processing method

Method SiC for slicing four-ingot block

Packaging method and panel module

Silicon wafer and semiconductor device

APPARATUS AND METHOD FOR WAFER BONDING

An apparatus for wafer bonding includes a transfer module and a plasma module. The transfer module is configured to transfer a semiconductor wafer. The plasma module is configured to apply a first type of plasma to perform a reduction operation upon a surface of the semiconductor wafer at a temperature within a predetermined temperature range to convert metal oxides on the surface of the semiconductor wafer to metal, and apply a second type of plasma to perform a plasma operation upon the surface of the semiconductor wafer at a room temperature outside the predetermined temperature range to activate a surface of the semiconductor wafer.

Verfahren zur Herstellung von Halbleiterscheiben mittels einer Drahtsäge, Drahtsäge und Halbleiterscheibe aus einkristallinem Silizium

Verfahren zur Herstellung von Halbleiterscheiben aus einem Werkstück durch Bearbeiten des Werkstücks mittels einer Drahtsäge, Drahtsäge und Halbleiterscheibe aus einkristallinem Silizium. Das Verfahren umfasstdas Zustellen des Werkstücks durch eine Anordnung von Drähten, die in Drahtgruppen gegliedert zwischen Drahtführungsrollen gespannt sind und sich in eine Laufrichtung bewegen;das Erzeugen von Schnittspalten beim Eingriff der Drähte in das Werkstück;für jede der Drahtgruppen das Ermitteln einer Fehllage der Schnittspalte der Drahtgruppe; undfür jede der Drahtgruppen das Herbeiführen von Ausgleichsbewegungen der Drähte der Drahtgruppe in Abhängigkeit der ermittelten Fehllage der Schnittspalte der Drahtgruppe in eine Richtung senkrecht zur Laufrichtung der Drähte der Drahtgruppe während des Zustellens des Werkstücks durch die Anordnung von Drähten durch Aktivieren mindestens eines Antriebselements.

SIC-SUBSTRATBEWERTUNGSVERFAHREN, VERFAHREN ZUR HERSTELLUNG VON SIC-EPITAXIEWAFERN UND SIC-EPITAXIEWAFER

SiC-Substratbewertungsverfahren, umfassend:Beobachten eines balkenförmigen Stapelfehlers durch Bestrahlen einer ersten Oberfläche eines SiC-Substrats vor dem Aufstapeln einer Epitaxieschicht mit Anregungslicht und Extrahieren von Licht mit einem Wellenlängenbereich von gleich oder größer als 405 nm und gleich oder kleiner als 445 nm unter den von der ersten Oberfläche emittierten Photolumineszenzlichtstrahlen,wobei die erste Oberfläche des SiC-Substrats einen Versatzwinkel von einer {0001}-Ebene aufweist, eine Bestrahlungszeit des Anregungslichts gleich oder größer als 1 msec und gleich oder kleiner als 10 sec ist und eine Intensität des Anregungslichts gleich oder kleiner als 1 W/cm2ist, undwobei sich der balkenförmige Stapelfehler in einer Balkenform in einer Richtung im Wesentlichen senkrecht zu der Versatzrichtung erstreckt, der balkenförmige Stapelfehler eine Länge in einer Richtung im Wesentlichen senkrecht zur Versatzrichtung aufweist, die in Bezug auf die Breite in der Versatzrichtung ...

DIAMANTSUBSTRATHERSTELLUNGSVERFAHREN

Ein Diamantsubstratherstellungsverfahren schließt einen Schritt zum Ausbilden einer bandförmigen Trennschicht mit einem Aufbringen eines Laserstrahls auf einen Diamantingot bei einem relativ zueinander Bewegen des Diamantingots und eines Brennpunkts des Laserstrahls in einer [110]-Richtung senkrecht zu einer (110)-Ebene, um dadurch eine bandförmige Trennschicht auszubilden, die sich im Inneren des Diamantingots in der [110]-Richtung erstreckt, einen Einteilungsschritt mit einem relativ zueinander Bewegen des Diamantingots und des Brennpunkts in einer Einteilungsrichtung parallel zu einer (001)-Ebene und senkrecht zu der [110]-Richtung, einen Schritt zum Ausbilden einer planaren Trennschicht mit einem Wiederholen des Schritts zum Ausbilden einer bandförmigen Trennschicht und des Einteilungsschritts, um dadurch im Inneren des Diamantingots parallel zu der (001)-Ebene eine planare Trennschicht auszubilden, wobei die planare Trennschicht aus mehreren bandförmigen Trennschichten, die Seite an ...

Methods and apparatuses for effluent monitoring for brush conditioning

An example system for monitoring contamination level of effluent of an offline brush conditioning system includes a first reservoir configured to collect a first effluent from a first portion of a brush in the offline brush conditioning system and a second reservoir configured to collect a second effluent from a second portion of the brush, where the second portion is different from the first portion, and the first and second effluents are from a fluid used to condition a brush configured to clean a surface of a semiconductor wafer. An effluent contamination monitor is configured to monitor a first contamination level of the first effluent and a second contamination level of the second effluent.

Method for manufacturing a semiconductor wafer, and semiconductor device having a low concentration of interstitial oxygen

A method for manufacturing a substrate wafer 100 includes providing a device wafer (110) having a first side (111) and a second side (112); subjecting the device wafer (110) to a first high temperature process for reducing the oxygen content of the device wafer (110) at least in a region (112a) at the second side (112); bonding the second side (112) of the device wafer (110) to a first side (121) of a carrier wafer (120) to form a substrate wafer (100); processing the first side (101) of the substrate wafer (100) to reduce the thickness of the device wafer (110); subjecting the substrate wafer (100) to a second high temperature process for reducing the oxygen content at least of the device wafer (110); and at least partially integrating at least one semiconductor component (140) into the device wafer (110) after the second high temperature process.

基板、半導体装置およびこれらの製造方法

VERFAHREN ZUR HERSTELLUNG EINES HALBLEITER-WAFERS MIT EINER NIEDRIGEN KONZENTRATION VON INTERSTITIELLEM SAUERSTOFF

Ein Verfahren zur Herstellung eines Substrat-Wafers (100) umfasst: Vorsehen eines Bauelement-Wafers (110) mit einer ersten Seite (111) und einer zweiten Seite (112); Unterziehen des Bauelement-Wafers (110) einem ersten Hochtemperaturprozess zum Reduzieren des Sauerstoffgehalts des Bauelement-Wafers (110) wenigstens in einem Gebiet (112a) auf der zweiten Seite (112); Bonden der zweiten Seite (112) des Bauelement-Wafers (110) an eine erste Seite (121) eines Träger-Wafers (120), um einen Substrat-Wafer (100) zu bilden; Bearbeiten der ersten Seite (101) des Substrat-Wafers (100), um die Dicke des Bauelement-Wafers (110) zu reduzieren; Unterziehen des Substrat-Wafers (100) einem zweiten Hochtemperaturprozess zum Reduzieren des Sauerstoffgehalts wenigstens des Bauelement-Wafers (110); und wenigstens teilweises Integrieren wenigstens einer Halbleiterkomponente (140) in den Bauelement-Wafer (110) nach dem zweiten Hochtemperaturprozess.

Semiconductor structure and method

METHOD FOR EXTREME ULTRAVIOLET ELECTROSTATIC CHUCK WITH REDUCED CLAMPING EFFECT

The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a front surface and a backside surface; integrated circuit features formed on the front surface of the semiconductor substrate; and a polycrystalline silicon layer disposed on the backside surface of the semiconductor substrate.

Surface oxidation method for wafer

A surface oxidation method for a wafer, the method comprises: raising a temperature on the wafer in an oxidation atmosphere, the temperature is raised from a start temperature to a target temperature at a temperature raising rate greater than 5° C./min, the temperature is raised in a vertical furnace tube of an annealing furnace, the vertical furnace tube includes a gas intake conduit arranged on a side wall, the gas intake conduit includes a gas inlet arranged to be proximate to a bottom of the vertical furnace tube and a gas outlet arranged to be proximate to a top of the furnace tube, the wafer overlying the vertical furnace tube; and isothermally oxidizing the wafer at the target temperature in the oxidation atmosphere.

VERFAHREN ZUM HERSTELLEN EINES WAFERS UND VORRICHTUNG ZUM HERSTELLEN EINES WAFERS

Ein Verfahren zum Herstellen eines Wafers schließt einen Abziehschichtausbildungsschritt zum Ausbilden einer Abziehschicht in einem hexagonalen Einkristallingot durch Aufbringen eines Laserstrahls mit einer Wellenlänge, die durch den hexagonalen Einkristallingot übertragbar ist, während eines Positionierens eines Brennpunkts des Laserstrahls in dem hexagonalen Einkristallingot in einer Tiefe von einer Stirnseite des hexagonalen Einkristallingots aus, die mit der Dicke eines herzustellenden Wafers korrespondiert, einen Ultraschallwellenerzeugungsschritt zum Erzeugen von Ultraschallwellen durch eine Ultraschallwellenerzeugungseinheit, die in gegenüberliegender Beziehung zu dem herzustellenden Wafer positioniert ist, über eine dazwischen eingefügten Wasserschicht, um dadurch die Abziehschicht zu zerstören, und einen Abzieherfassungsschritt ein, um basierend auf einer Änderung, die durch eine Höhenerfassungseinheit, die über der oberen Fläche des herzustellenden Wafers positioniert ist, bei ...

Verfahren und Lösung zur Herstellung und Nachbehandlung von Wafern

Beschrieben werden ein Verfahren zur Herstellung und Nachbehandlung von Wafern aus einem poly- oder monokristallinen Material sowie eine hierbei verwendete wässrige Reinigungslösung. Bei dem Verfahren wird ein Block aus dem poly- oder monokristallinen Material auf einem Träger fixiert und in Wafer zerteilt. Die Oberflächen der Wafer werden mittels einer sauren oder alkalischen Ätzlösung behandelt, nachdem sie mit der wässrigen Reinigungslösung behandelt wurden. Die Reinigungslösung enthält mindestens eine C, S oder B enthaltende Perverbindung mit mindestens einer -O-O- Atomgruppe und mindestens eine basische Komponente.

Large aluminum nitride crystals with reduced defects and methods of making them

Diamond semiconductor element and process for producing the same

A process of producing a diamond thin-film includes implanting dopant into a diamond by an ion implantation technique, forming a protective layer on at least part of the surface of the ion-implanted diamond, and firing the protected ion-implanted diamond at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C. A process of producing a diamond semiconductor includes implanting dopant into each of two diamonds by an ion implantation technique and superimposing the two ion-implanted diamonds on each other such that at least part of the surfaces of each of the ion-implanted diamonds makes contact with each other, and firing the ion implanted diamonds at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C.

Iii nitride semiconductor substrate, epitaxial substrate, and semiconductor device

In a semiconductor device 100 , it is possible to prevent C from piling up at a boundary face between an epitaxial layer 22 and a group III nitride semiconductor substrate 10 by the presence of 30×10 10 pieces/cm 2 to 2000×10 10 pieces/cm 2 of sulfide in terms of S and 2 at % to 20 at % of oxide in terms of O in a surface layer 12 . By thus preventing C from piling up, a high-resistivity layer is prevented from being formed on the boundary face between the epitaxial layer 22 and the group III nitride semiconductor substrate 10 . Accordingly, it is possible to reduce electrical resistance at the boundary face between the epitaxial layer 22 and the group III nitride semiconductor substrate 10 , and improve the crystal quality of the epitaxial layer 22 . Consequently, it is possible to improve the emission intensity and yield of the semiconductor device 100.

Manufacturing method for semiconductor wafer

All treatments performed in machining processes other than a polishing process are performed while pure water free from free abrasive grains is supplied. Thus, an amount of abrasive grains included in a used processing liquid discharged in each process is reduced and semiconductor scraps are collected from the used slurry for recycling.

Adhesive film for semiconductor device, film for backside of flip-chip semiconductor, and dicing tape-integrated film for backside of semiconductor

Provided is an adhesive film for a semiconductor device that is capable of having the same physical properties as these at the time of manufacture even after it is stored for a long time. The adhesive film for a semiconductor device of the present invention contains a thermosetting resin, and in which the amount of reaction heat generated in a temperature range of ±80° C. of a reaction heat peak temperature measured by a differential scanning calorimeter after the adhesive film is stored at 25° C. for 4 weeks is 0.8 to 1 time the amount of reaction heat generated before storage.

Method for manufacturing nitride semiconductor substrate

There is provided a method for manufacturing a nitride semiconductor substrate, comprising: etching and flattening a surface of a nitride semiconductor substrate disposed facing a surface plate, by using the surface plate having a surface composed of any one of Ni, Ti, Cr, W, and Mo or nitride of any one of them, disposing the surface of the surface plate and a flattening surface of a nitride semiconductor substrate proximately so as to be faced each other, and supplying gas containing at least hydrogen and ammonia between the surface of the surface plate and the surface of the nitride semiconductor substrate, wherein the surface plate and the nitride semiconductor substrate facing each other are set in a high temperature state of 900° C. or more.

Silicon carbide substrate manufacturing method and silicon carbide substrate

Silicon carbide single crystal is prepared. Using the silicon carbide single crystal as a material, a silicon carbide substrate having a first face and a second face located at a side opposite to the first face is formed. In the formation of the silicon carbide substrate, a first processed damage layer and a second processed damage layer are formed at the first face and second face, respectively. The first face is polished such that at least a portion of the first processed damage layer is removed and the surface roughness of the first face becomes less than or equal to 5 nm. At least a portion of the second processed damage layer is removed while maintaining the surface roughness of the second plane greater than or equal to 10 nm.

Semiconductor Device and Method of Manufacturing a Semiconductor Device Including Grinding Steps

A method of manufacturing a device includes providing a semiconductor chip having a first face and a second face opposite to the first face with a contact pad arranged on the first face. The semiconductor chip is placed on a carrier with the first face facing the carrier. The semiconductor chip is encapsulated with an encapsulation material. The carrier is removed and the semiconductor material is removed from the second face of the first semiconductor chip without removing encapsulation material at the same time.

Surface profile adjustment using gas cluster ion beam processing

A method of treating a workpiece is described. The method comprises computing correction data from metrology data related to a workpiece surface profile, adjusting the surface profile in accordance with the correction data using a gas cluster ion beam (GCIB), and further adjusting the surface profile by performing an etching process following the GCIB adjustment.

DEFECT CAPPING METHOD FOR REDUCED DEFECT DENSITY EPITAXIAL ARTICLES

A method for forming an epitaxial layer on a substrate surface having crystalline defect or amorphous regions and crystalline non-defect regions includes preferential polishing or etching the crystalline defect or amorphous regions relative to the crystalline non-defect regions to form a decorated substrate surface having surface recess regions. A capping layer is deposited on the decorated substrate surface to cover the crystalline non-defect regions and to at least partially fill the surface recess regions. The capping layer is patterned by removing the capping layer over the crystalline non-defect regions to form exposed non-defect regions while retaining the capping layer in at least a portion of the surface recess regions. Selective epitaxy is then used to form the epitaxial layer, wherein the capping layer in the surface recess regions restricts epitaxial growth of the epitaxial layer over the surface recess regions. 1. A method for forming an epitaxial layer on a substrate comprising a substrate surface having crystalline defect or amorphous regions and crystalline non-defect regions , comprising:preferential polishing or etching said crystalline defect or amorphous regions relative to said crystalline non-defect regions to form a decorated substrate surface comprising surface recess regions;depositing a capping layer on said decorated substrate surface to cover said crystalline non-defect regions and to at least partially fill said surface recess regions;patterning said capping layer by removing said capping layer over said crystalline non-defect regions to form exposed non-defect regions while retaining said capping layer in at least a portion of said surface recess regions, andselective epitaxy to form said epitaxial layer, wherein said capping layer in said surface recess regions restricts epitaxial growth of said epitaxial layer over said surface recess regions.2. The method of claim 1 , further comprising chemical mechanical polishing (CMP) after said ...

METHOD AND APPARATUS FOR TEMPORARY BONDING OF ULTRA THIN WAFERS

A method for temporary bonding first and second wafers includes, applying a first adhesive layer upon a first surface of a first wafer and then curing the first adhesive layer. Next, applying a second adhesive layer upon a first surface of a second wafer. Next, inserting the first wafer into a bonder module and holding the first wafer by an upper chuck assembly so that its first surface with the cured first adhesive layer faces down. Next, inserting the second wafer into the bonder module and placing the second wafer upon a lower chuck assembly so that the second adhesive layer faces up and is opposite to the first adhesive layer. Next, moving the lower chuck assembly upwards and bringing the second adhesive layer in contact with the cured first adhesive layer, and then curing the second adhesive layer. 1. A method for temporary bonding two wafer surfaces comprising:providing a first wafer comprising first and second wafer surfaces opposite to each other;providing a second wafer comprising first and second wafer surfaces opposite to each other;applying a first adhesive layer upon said first surface of said first wafer;curing the first adhesive layer, thereby producing a cured first adhesive layer;applying a second adhesive layer upon said first surface of said second wafer;providing a bonder module comprising an upper chuck assembly and a lower chuck assembly arranged below and opposite the upper chuck assembly;inserting said first wafer into said bonder module and holding said first wafer by said upper chuck assembly so that its first surface with the cured first adhesive layer faces down;inserting said second wafer into said bonder module and placing said second wafer upon said lower chuck assembly so that said second adhesive layer faces up and is opposite to said first adhesive layer;moving said lower chuck assembly upwards and bringing said second adhesive layer in contact with said cured first adhesive layer; andcuring said second adhesive layer, thereby ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A method of manufacturing a semiconductor device disclosed herein includes: mounting a substrate on an electrostatic chuck placed inside a chamber, the electrostatic chuck having a first temperature and the substrate being retained in advance in an atmosphere having a second temperature lower than the first temperature; fixing the substrate onto the electrostatic chuck by applying a voltage to the electrostatic chuck; heating the electrostatic chuck to a third temperature higher than the first temperature and the second temperature after mounting the substrate; and processing the substrate after the heating. 1. A method of manufacturing a semiconductor device , the method comprising:mounting a substrate on an electrostatic chuck placed inside a chamber, the electrostatic chuck having a first temperature and the substrate being retained in advance in an atmosphere having a second temperature lower than the first temperature;fixing the substrate onto the electrostatic chuck by applying a voltage to the electrostatic chuck;heating the electrostatic chuck to a third temperature higher than the first temperature and the second temperature after mounting the substrate; andprocessing the substrate after the heating.2. The method of manufacturing a semiconductor device according to claim 1 , whereina plurality of the substrates are prepared, andthe mounting a substrate, the fixing the substrate, the heating, and the processing are performed in this order on each of the plurality of the substrates.3. The method of manufacturing a semiconductor device according to claim 2 , the method further comprising:taking one of the substrates out of the chamber; andsetting the temperature of the electrostatic chuck to the first temperature, whereinthe taking one of the substrates out and the setting the temperature are executed after the processing the one of the substrates and before mounting a subsequent one of the substrates.4. The method of manufacturing a semiconductor device ...

ULTRA HIGH-SPEED WET ETCHING APPARATUS

There is provided with an etching method using an etching apparatus. Four arms can be positioned in a direction substantially from a center of the stage toward a peripheral portion with an angle difference of about 90°. Etchant is supplied to a first position nearest to the center of the object which is rotating, from a first etchant supply nozzle placed on a first arm. Etchant is further supplied to a second position second nearest to the center of the object, from a second etchant supply nozzle placed on a second arm. The second arm is substantially symmetrically positioned with respect to the first arm and the second arm has an angle difference of about 180° with respect to the first arm. 1. An etching method using an etching apparatus , wherein the etching apparatus comprises:a rotatable stage where an object to be etched is placed; andfour arms comprising an etchant supply nozzle for supplying etchant to a surface to be etched on the object;wherein the four arms can be positioned in a direction substantially from a center of the stage toward a peripheral portion with an angle difference of about 90°; andwherein the etching method comprises:supplying the etchant to a first position nearest to the center of the object which is rotating, from a first etchant supply nozzle placed on a first arm;supplying the etchant to a second position second nearest to the center of the object, from a second etchant supply nozzle placed on a second arm, wherein the second arm is substantially symmetrically positioned with respect to the first arm and the second arm has an angle difference of about 180° with respect to the first arm;supplying the etchant to a third position on the object from a third etchant supply nozzle placed on a third arm, wherein the third arm is positioned between the first arm and the second arm;supplying the etchant to a fourth position of the object from a fourth etchant supply nozzle placed on a fourth arm, wherein the fourth arm is substantially ...

Substrate processing apparatus and substrate processing method

In a substrate processing apparatus, with an internal space of a chamber brought into a reduced pressure atmosphere, a first processing liquid is supplied onto an upper surface of a substrate while the substrate is rotated, and the first processing liquid is thereby quickly spread from a center portion toward a peripheral portion on the upper surface of the substrate. It is thereby possible to coat the upper surface of the substrate with the first processing liquid in a shorter time as compared with under normal pressure. Further, by sucking the first processing liquid from the vicinity of an edge of the substrate, it is possible to coat the upper surface of the substrate with the first processing liquid in a still shorter time. As a result, it is possible to shorten the time required for the processing of the substrate.

THERMAL PLATE WITH PLANAR THERMAL ZONES FOR SEMICONDUCTOR PROCESSING

A thermal plate for a substrate support assembly in a semiconductor plasma processing apparatus, includes multiple independently controllable planar thermal zones arranged in a scalable multiplexing layout, and electronics to independently control and power the planar heater zones. Each planar thermal zone uses at least one Peltier device as a thermoelectric element. A substrate support assembly in which the thermal plate is incorporated has an electrostatic clamping electrode layer and a temperature controlled base plate. Methods for manufacturing the thermal plate include bonding together ceramic or polymer sheets having planar thermal zones, positive, negative and common lines and vias. 1. A thermal plate , configured to overlay a temperature controlled base plate of a substrate support assembly used to support a semiconductor substrate in a semiconductor processing apparatus , the thermal plate comprising:an electrically insulating plate;planar thermal zones comprising at least first, second, third and fourth planar thermal zones, each comprising one or more Peltier devices as thermoelectric elements, the planar thermal zones laterally distributed across the electrically insulating plate and operable to tune a spatial temperature profile on the substrate;positive voltage lines comprising first and second electrically conductive positive voltage lines laterally distributed across the electrically insulating plate;negative voltage lines comprising first and second electrically conductive negative voltage lines laterally distributed across the electrically insulating plate;common lines comprising first and second electrically conductive common lines laterally distributed across the electrically insulating plate;wherein:the first common line is connected to both the first and third planar thermal zones; andthe second common line is connected to both the second and fourth planar thermal zones.2. The thermal plate of claim 1 , wherein the planar thermal zones do not ...

WAFER PROCESSING LAMINATE, WAFER PROCESSING MEMBER, TEMPORARY BONDING ARRANGEMENT, AND THIN WAFER MANUFACTURING METHOD

A wafer processing laminate is provided comprising a support (), a temporary adhesive layer (), and a wafer (). The temporary adhesive layer () has a trilayer structure consisting of a first temporary bond layer (A) of thermoplastic siloxane bond-free polymer, a second temporary bond layer (B) of thermoplastic siloxane polymer, and a third temporary bond layer (C) of thermosetting modified siloxane polymer. In a peripheral region, the second layer (B) is removed so that the first layer (A) is in close contact with the third layer (C). 1. A wafer processing laminate comprising a support , a temporary adhesive layer on the support , and a wafer laid contiguous to the temporary adhesive layer , the wafer having a circuit-forming front surface and a back surface to be processed ,said temporary adhesive layer being a composite temporary adhesive layer having a trilayer structure consisting of a first temporary bond layer (A) of thermoplastic siloxane bond-free polymer which is releasably bonded to the front surface of the wafer, a second temporary bond layer (B) of thermoplastic siloxane polymer which is laid contiguous to a central region of the first temporary bond layer excluding a peripheral region, and a third temporary bond layer (C) of thermosetting modified siloxane polymer which is laid contiguous to the support, wherein in the peripheral region where the second temporary bond layer (B) is removed, a peripheral portion of the first temporary bond layer (A) is in close contact with a peripheral portion of the third temporary bond layer (C).2. The wafer processing laminate of wherein a ratio of the removal of the peripheral region of the secondary temporary bond layer (B) to the radius of the wafer is 0.1 to 20%.3. The wafer processing laminate of wherein the peripheral region where the second temporary bond layer (B) is removed is a region extending between the outermost periphery of the wafer and a position spaced apart 0.5 to 10 mm radially inward from the ...

METHOD FOR SEPARATING A PRODUCT SUBSTRATE FROM A CARRIER SUBSTRATE

The invention relates to a method for stripping a product substrate from a carrier substrate which is connected to the product substrate by an interconnect layer with the following steps, especially the following sequence: 2. Method as claimed in claim 1 , wherein throughflow takes place through channels of the carrier substrate.3. Method as claimed in claim 1 , wherein throughflow takes place by means of permeation through pores of the carrier substrate.4. Method as claimed in claim 1 , wherein the interconnect layer is dissolved uniformly distributed along the carrier substrate.5. Method as claimed in claim 1 , wherein there is a solvent reservoir for holding the solvent claim 1 , a reservoir especially of variable volume claim 1 , which is formed by a film frame and a flexible film connected to the film frame claim 1 , and in which the solvent is applied claim 1 , especially by feed of the solvent.6. Method as claimed in claim 1 , wherein said ultrasonic vibrations have a frequency between 500 kHz and 1500 kHz.7. Method as claimed in claim 1 , wherein said ultrasonic vibrations have a frequency between 800 kHz and 1200 kHz.8. A method for removing a product substrate from a carrier substrate that is attached to the product substrate by an interconnect layer claim 1 , said method comprised of the following steps:applying a solvent to one flat side of a carrier substrate that is connected to a product substrate by an interconnect layer, said one flat side facing away from said interconnect layer and said carrier substrate having openings therethrough, wherein said one flat side is in communication with said interconnect layer through said openings, a throughflow portion of said solvent flowing through said opening in said carrier substrate to the interconnect layer;exposing the throughflow portion of the solvent to ultrasonic vibrations having a frequency between 16 kHz and 1 GHz;maintaining said ultrasonic vibrations until at least part of the interconnect layers ...

METHOD OF FORMING A FREESTANDING SEMICONDUCTOR WAFER

A method of forming a freestanding semiconductor wafer includes providing a semiconductor substrate including a semiconductor layer having a back surface and an upper surface opposite the back surface, wherein the semiconductor layer comprises at least one permanent defect between the upper surface and back surface, removing a portion of the back surface of the semiconductor layer and the permanent defect from the semiconductor layer, and forming a portion of the upper surface after removing a portion of the back surface and the permanent defect. 1. A method of forming a freestanding semiconductor wafer comprising:providing a semiconductor substrate comprising a semiconductor layer having a back surface and an upper surface opposite the back surface, wherein the semiconductor layer comprises at least one permanent defect between the upper surface and back surface;removing a portion of the back surface of the semiconductor layer and the permanent defect from the semiconductor layer; andforming a portion of the upper surface after removing a portion of the back surface and the permanent defect.27.-. (canceled)8. The method of claim 1 , wherein the semiconductor layer comprises a Group 13-15 material.9. The method of claim 1 , wherein the semiconductor layer comprises an average thickness of at least about 1 mm.10. The method of claim 1 , wherein the semiconductor layer comprises a dislocation density of not greater about 1×10dislocations/cm.1112.-. (canceled)13. The method of claim 1 , wherein the at least one permanent defect between the upper surface and back surface defines a bottom surface of a permanent pit.14. The method of claim 13 , wherein the permanent pit comprises an upper opening intersecting the upper surface of the semiconductor layer.15. The method of claim 1 , wherein the permanent defect defines a region of the semiconductor layer having a shift in the regular arrangement of crystalline planes.16. The method of claim 1 , wherein removing a portion of ...

Semiconductor Structure and Method

A system and method for providing support to semiconductor wafer is provided. An embodiment comprises introducing a vacancy enhancing material during the formation of a semiconductor ingot prior to the semiconductor wafer being separated from the semiconductor ingot. The vacancy enhancing material forms vacancies at a high density within the semiconductor ingot, and the vacancies form bulk micro defects within the semiconductor wafer during high temperature processes such as annealing. These bulk micro defects help to provide support and strengthen the semiconductor wafer during subsequent processing and helps to reduce or eliminate a fingerprint overlay that may otherwise occur.

Semiconductor wafer and manufacturing method thereof

A semiconductor wafer having sag formed at an outer periphery at the time of polishing, wherein a displacement of the semiconductor wafer in a thickness direction is 100 nm or less between a center and a outer peripheral sag start position of the semiconductor wafer, and the center of the semiconductor wafer has a convex shape, an amount of outer peripheral sag of the semiconductor wafer is 100 nm or less, and the outer peripheral sag start position is away from an outer peripheral portion of the semiconductor wafer toward the center or 20 mm or more away from an outer peripheral end of the semiconductor wafer toward the center, the outer peripheral portion being a measurement target of ESFQR.

Substrate processing apparatus and substrate processing method

A substrate processing apparatus includes a substrate holding part, a substrate rotating mechanism, and a chamber. The substrate rotating mechanism incudes an annular rotor part disposed in an internal space of the chamber and a stator part disposed around the rotor part outside the chamber. The substrate holding part is attached to the rotor part in the internal space of the chamber. In the substrate rotating mechanism, a rotating force is generated about a central axis between the stator part and the rotor part. The rotor part is thereby rotated about the central axis, being in a floating state, together with a substrate and the substrate holding part. In the substrate processing apparatus, the substrate can be easily rotated in the internal space having excellent sealability. As a result, it is possible to easily perform single-substrate processing in a sealed internal space.

Group iii nitride wafer and its production method

The present invention discloses a group III nitride wafer such as GaN, AlN, InN and their alloys having one surface visually distinguishable from the other surface. After slicing of the wafer from a bulk crystal of group III nitride with a mechanical method such as multiple wire saw, the wafer is chemically etched so that one surface of the wafer is visually distinguishable from the other surface. The present invention also discloses a method of producing such wafers.

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE

There is provided a method of fabricating a semiconductor device, method including: a) forming semiconductor elements in plural element regions surrounded by assumed dicing lines on a first principal surface of a semiconductor wafer; b) grinding the second principal surface in such a way that an outer peripheral portion of a second principal surface on the opposite side of the first principal surface of the semiconductor wafer becomes thicker than an inner peripheral portion of the second principal surface; c) forming a metal film, in such a way as to avoid sections corresponding to the dicing lines, on the second principal surface that has been ground in the grinding step; and d) cutting the semiconductor wafer from the second principal surface side along portions where the metal film is not formed on the dicing lines. 1. A method of fabricating a semiconductor device , method comprising:a) forming semiconductor elements in plural element regions surrounded by assumed dicing lines on a first principal surface of a semiconductor wafer;b) grinding the second principal surface in such a way that an outer peripheral portion of a second principal surface on the opposite side of the first principal surface of the semiconductor wafer becomes thicker than an inner peripheral portion of the second principal surface;c) forming a metal film, in such a way as to avoid sections corresponding to the dicing lines, on the second principal surface that has been ground in the grinding step; andd) cutting the semiconductor wafer from the second principal surface side along portions where the metal film is not formed on the dicing lines.2. The method according to claim 1 , wherein the forming a metal film c) comprises:forming a first metal film on the second principal surface of the semiconductor wafer,removing sections of the first metal film coinciding with the dicing lines, andforming a second metal film on the first metal film remaining on the second principal surface.3. The ...

SEMICONDUCTOR MEMORY CARD

A semiconductor memory card includes a lead frame having external connection terminals, a controller chip mounted on the lead frame and a memory chip mounted on the lead frame. The lead frame, the controller chip, and the memory chip are sealed with a sealing resin layer that has a surface at which the external connection terminals are exposed and a recess surrounding the external connection terminals. 1. A semiconductor memory card , comprising:a lead frame including a plurality of external connection terminals and a lead portion having a plurality of leads with at least one lead connected to the external connection terminals;a controller chip mounted on the lead frame and electrically connected to the at least one lead;a memory chip mounted on the lead frame and electrically connected to the controller chip;a sealing resin layer that seals the lead frame, the controller chip, and the memory chip, the sealing resin layer having a surface at which the external connection terminals are exposed; anda recess in the sealing resin layer at the surface, the recess surrounding the external connection terminals and exposing a part of side surfaces of the external connection terminals.2. The semiconductor memory card according to claim 1 , further comprising:a metallic plating film, formed by electrolytic plating, that covers the exposed surfaces of the external connection terminals.3. The semiconductor memory card according to claim 2 , wherein the metallic plating layer comprises a precious metal.4. The semiconductor memory card according to claim 1 , wherein the lead frame has a connection terminal for coming into electrical contact with a plating contact pin claim 1 , the connection terminal being located at a position other than the external connection terminals.5. The semiconductor memory card according to claim 4 , wherein the connection terminal extends to the surface.6. The semiconductor memory card according to claim 4 , further comprising an insulating resin film ...

SUBSTRATE PROCESSING METHOD, SUBSTRATE PROCESSING APPARATUS, AND STORAGE MEDIUM

A wafer is held horizontally and rotated by a substrate holding mechanism. An aqueous alkaline solution is supplied to a wafer by a nozzle and caused to flow from a central portion to a peripheral edge portion of the wafer, thereby etching the wafer. An amount of oxygen, which is equal to or more than the amount of oxygen in atmospheric air involved in the aqueous alkaline solution flowing on the wafer, is previously dissolved in the aqueous alkaline solution. 1. A substrate processing method of processing a substrate to be processed , the method comprising:a step of holding the substrate horizontally and rotating the substrate; anda step of supplying an aqueous alkaline solution to the substrate and allowing the aqueous alkaline solution to flow from a central portion to a peripheral edge portion of the substrate, thereby etching the substrate;wherein an amount of oxygen, which is equal to or more than the amount of oxygen in atmospheric air involved in the aqueous alkaline solution flowing on the substrate, is dissolved previously in the aqueous alkaline solution.2. The substrate processing method according to claim 1 , whereinthe concentration of oxygen in the aqueous alkaline solution is 200 ppb to 1000 ppb.3. The substrate processing method according to claim 2 , whereinthe concentration of oxygen in the aqueous alkaline solution is 200 ppb to 500 ppb.4. A substrate processing apparatus for processing a substrate to be processed claim 2 , the apparatus comprising:a substrate holding mechanism configured to hold the substrate horizontally and rotating the substrate;a nozzle for supplying an aqueous alkaline solution to the substrate, thereby etching the substrate; anda liquid supplying mechanism connected to the nozzle, the liquid supplying mechanism supplying to the nozzle an aqueous alkaline solution in which an amount of oxygen, which is equal to or more than the amount of oxygen in atmospheric air involved in the aqueous alkaline solution flowing from a ...

SEMICONDUCTOR PACKAGES HAVING THROUGH ELECTRODES AND METHODS OF FABRICATING THE SAME

Provided are semiconductor packages having through electrodes and methods of fabricating the same. The method may include may include forming a wafer-level package including first semiconductor chips stacked on a second semiconductor chip, forming a chip-level package including fourth semiconductor chips stacked on a third semiconductor chip stacking a plurality of the chip-level packages on a back surface of the second semiconductor substrate of the wafer-level package, polishing the first mold layer of the wafer-level package and the first semiconductor chips to expose a first through electrodes of the first semiconductor chip, and forming outer electrodes on the polished first semiconductor chips to be connected to the first through electrodes, respectively. 1. A method of forming a semiconductor package , the method comprising:providing a first chip and a second chip, the providing comprising:providing a first active layer on a front surface of a first substrate of a first chip;providing a second active layer on a front surface of a second substrate of a second chip;stacking the first chip and the second chip so that the first active layer of the first chip faces the second active layer of the second chip;forming a mold layer on the first chip and on the front surface of the second substrate of the second chip to provide rigidity to the semiconductor package, the mold layer including a polymer material;thinning a back surface of the second substrate having the mold layer; andforming back-side electrodes on the thinned back surface of the second substrate, the back-side electrodes being electrically connected to second through electrodes in the second substrate.2. The method of claim 1 , wherein the thinning the back surface of the second substrate comprises thinning the back surface using a mechanical process.3. The method of claim 2 , wherein the thinning the back surface of the second substrate exposes the second through electrodes in the second substrate ...

WAFER PROCESSING TEMPORARY BONDING ARRANGEMENT, WAFER PROCESSING LAMINATE, AND THIN WAFER MANUFACTURING METHOD

A temporary bonding arrangement for wafer processing is provided comprising a first temporary bond layer (A) of thermoplastic resin, a second temporary bond layer (B) of thermosetting siloxane polymer, and a third temporary bond layer (C) of thermosetting polymer. Layer (B) is cured with a curing catalyst contained in layer (A) which is laid contiguous to layer (B). An adhesive layer of uniform thickness is formed without insufficient step coverage and other failures. 1. An arrangement for temporarily bonding a wafer to a support for wafer processing , the wafer having a circuit-forming front surface and a back surface to be processed ,said temporary bonding arrangement being a composite temporary adhesive layer comprising a first temporary bond layer (A) of thermoplastic resin, a second temporary bond layer (B) of thermosetting siloxane polymer which is laid contiguous to the first temporary bond layer, and a third temporary bond layer (C) of thermosetting polymer which is laid contiguous to the second temporary bond layer,wherein the first temporary bond layer (A) is a resin layer of a composition comprising (A-1) 100 parts by weight of a thermoplastic resin and (A-2) an amount of a curing catalyst to provide more than 0 part to 1 part by weight of an active ingredient per 100 parts by weight of component (A-1), and the thermosetting siloxane polymer layer (B) is cured with the aid of the curing catalyst in the layer (A) which is contiguous to the layer (B).2. The temporary bonding arrangement of wherein the wafer is a substrate having steps of 10 to 80 μm high on its surface.3. The temporary bonding arrangement of wherein component (A-2) is a platinum-based catalyst.4. The temporary bonding arrangement of wherein the second temporary bond layer (B) is a polymer layer of a composition comprising (B-1) 100 parts by weight of an organopolysiloxane having an alkenyl group in the molecule and (B-2) an organohydrogenpolysiloxane having at least two silicon-bonded ...

SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD

In a substrate processing apparatus, with an internal space of a chamber brought into a reduced pressure atmosphere, a first processing liquid is supplied onto an upper surface of a substrate while the substrate is rotated, and the first processing liquid is thereby quickly spread from a center portion toward a peripheral portion on the upper surface of the substrate. It is thereby possible to coat the upper surface of the substrate with the first processing liquid in a shorter time as compared with under normal pressure. Further, by sucking the first processing liquid from the vicinity of an edge of the substrate, it is possible to coat the upper surface of the substrate with the first processing liquid in a still shorter time. As a result, it is possible to shorten the time required for the processing of the substrate. 1. A substrate processing method of processing a substrate , comprising the steps of:a) holding a substrate with a main surface thereof directed upward in an internal space of a chamber; andb) bringing said internal space of said chamber into a reduced pressure atmosphere and supplying a processing liquid onto a center portion of said main surface of said substrate while rotating said substrate in said reduced pressure atmosphere, to thereby coat said main surface of said substrate with said processing liquid.2. The substrate processing method according to claim 1 , whereina pattern is formed on said main surface of said substrate, andsaid substrate processing method further comprising the step of:c) increasing pressure in said internal space of said chamber and continuously supplying said processing liquid onto said main surface of said substrate coated with said processing liquid while rotating said substrate, to thereby perform a predetermined processing after said step b).3. The substrate processing method according to claim 2 , whereinsaid predetermined processing is performed in a pressurized atmosphere in said step c).4. The substrate ...

SUBSTRATE TREATING APPARATUS AND METHOD OF TREATING SUBSTRATE

A substrate treating apparatus includes a rotating and holding unit that rotates a substrate, a first supply source that supplies first pure water having a first temperature, a second supply source that supplies second pure water having a second temperature higher than the first temperature, a treatment solution supply unit that supplies a treatment solution to a central section of an upper surface of the substrate, a first supply unit that supplies a first liquid containing the first pure water to a central section of a lower surface of the substrate, a second supply unit that supplies a second liquid containing the second pure water to a peripheral section and an intermediate section of the lower surface, and a heat amount control unit that independently controls an amount of heat to be supplied by the first supply unit and an amount of heat to be supplied by the second supply unit. 1. A substrate treating apparatus , comprising:a rotating and holding unit that rotates a substrate while horizontally holding the substrate;a first supply source that supplies first pure water having a first temperature;a second supply source that supplies second pure water having a second temperature higher than the first temperature;a pipe system that guides said first pure water by dividing said first pure water into one first pure water and the other first pure water;a treatment solution supply unit that is supplied with said one first pure water from said pipe system and supplies a treatment solution to a central section of an upper surface of said substrate, said treatment solution containing said one first pure water and a chemical solution mixed so as to mainly contain said one first pure water;a first supply unit that is supplied with said other first pure water from said pipe system and supplies a first liquid mainly containing said other first pure water to a central section of a lower surface of said substrate;a second supply unit that supplies a second liquid mainly ...

Method of forming and transferring thin film using soi wafer and heat treatment process

The present invention relates to a method of forming and transferring a thin film. The method of forming and transferring a thin film according to one embodiment may include a step of bonding a carrier wafer coated with a polymer bonding material to the top of a silicon-on-insulator (SOI) wafer formed by sequentially laminating a backside silicon layer, a buried oxide layer, and a silicon layer; a step of etching the backside silicon layer using the buried oxide layer as an etching barrier, and then selectively etching the buried oxide layer; a step of separating the carrier wafer from the polymer bonding material, and bonding a target wafer including an oxide layer to the bottom of the silicon layer through direct bonding; and a step of transferring the silicon layer to the top of the target wafer including the oxide layer by removing the polymer bonding material.

METHOD FOR MANUFACTURING WAFER

A method for manufacturing a wafer product, including the steps of: chamfering a circumferential edge portion of a wafer; lapping or double-side grinding main surfaces thereof; etching; mirror-polishing the main surface; and mirror-polishing the chamfered portion. The chamfered portion has a cross-sectional shape including: a first inclined portion continuous from the first main surface; a first arc portion continuous from the first inclined portion and having a radius of curvature; a second inclined portion continuous from the second main surface; a second arc portion continuous from the second inclined portion and having a radius of curvature; and an end portion connecting the first arc portion to the second arc portion. This provides a method for manufacturing a wafer by which a variation in a chamfered cross-sectional shape in a circumferential direction caused by etching can be suppressed. 14.-. (canceled)5. A method for manufacturing a wafer as a product , comprising the steps of:grinding and chamfering a circumferential edge portion of a wafer sliced from a single crystal ingot;lapping or double-side grinding main surfaces of the chamfered wafer;etching the lapped or double-side ground wafer;one-side or double-side mirror-polishing main surfaces of the etched wafer; andmirror-polishing a chamfered portion of the mirror-polished wafer, whereinafter the chamfering step, the chamfered portion of the wafer has a cross-sectional shape comprising:a first inclined portion continuous from a first main surface, which is one of the main surfaces of the wafer, and inclined from the first main surface;a first arc portion which is an arc-shaped portion continuous from the first inclined portion and has a radius of curvature;a second inclined portion continuous from a second main surface, which is another main surface of the wafer, and inclined from the second main surface;a second arc portion which is an arc-shaped portion continuous from the second inclined portion and ...

METHODS AND APPARATUSES FOR EFFLUENT MONITORING FOR BRUSH CONDITIONING

Provided is a disclosure for embodiments that perform effluent monitoring for brush conditioning, where the monitored data may be fed back for use in the conditioning. 1. A system for monitoring contamination level of effluent of an offline brush conditioning system , the system comprising:a first reservoir configured to collect a first effluent from a first portion of a brush in the offline brush conditioning system;a second reservoir configured to collect a second effluent from a second portion of the brush, wherein the second portion is different from the first portion, and the first and second effluents are from a fluid used to condition a brush configured to clean a surface of a semiconductor wafer; andan effluent contamination monitor configured to monitor a first and a second contamination levels of the first effluent and the second effluent, respectively.2. The system of claim 1 , further comprising a control system configured to control the conditioning of the brush based on the first and second contamination levels.3. The system of claim 1 , wherein a material for at least one of the first reservoir or the second reservoir comprises at least one of quartz claim 1 , perfluoroalkoxy alkane (PFA) claim 1 , polyvinylidene fluoride (PVDF) claim 1 , or polyethylene terephthalate (PET).4. The system of claim 1 , wherein each of the measured first and second contamination levels comprises at least one of: a liquid particle count claim 1 , a pH level claim 1 , or a resistivity.5. The system of claim 4 , wherein the effluent contamination monitor comprises a liquid particle counter (LPC) configured to measure the liquid particle count.6. The system of claim 5 , wherein the LPC is configured to use a laser light scattering measurement system.7. The system of claim 4 , wherein at least a portion of the first and second contamination levels are recorded in real-time.8. The system of claim 1 , further comprising a pump system downstream of the first and second ...

SEMICONDUCTOR WAFER AND METHOD OF WAFER THINNING

A semiconductor wafer has a base material. The semiconductor wafer may have an edge support ring. A grinding phase of a surface of the semiconductor wafer removes a portion of the base material. The grinder is removed from or lifted off the surface of the semiconductor wafer during a separation phase. The surface of the semiconductor wafer and under the grinder is rinsed during the grinding phase and separation phase to remove particles. A rinsing solution is dispensed from a rinsing solution source to rinse the surface of the semiconductor wafer. The rinsing solution source can move in position while dispensing the rinsing solution to rinse the surface of the semiconductor wafer. The grinding phase and separation phase are repeated during the entire grinding operation, when grinding conductive TSVs, or during the final grinding stages, until the final thickness of the semiconductor wafer is achieved. 1. A method of thinning a semiconductor wafer , the method comprising:providing a semiconductor wafer including a base material;grinding a surface of the semiconductor wafer during a grinding phase using a grinder to remove a portion of the base material; andlifting the grinder off the surface of the semiconductor wafer only in a z axis during a separation phase.2. The method of claim 1 , further including repeating the grinding phase and separation phase.3. The method of claim 1 , further including rinsing the surface of the semiconductor wafer during the grinding phase and separation phase to remove the particles.4. The method of claim 3 , wherein the rinsing is continuous.5. The method of claim 3 , wherein the rinsing is pulsed.6. The method of claim 1 , further including reversing movement of the grinder during the separation phase.7. A method of thinning a semiconductor wafer claim 1 , the method comprising:performing a grinding phase on a surface of a semiconductor wafer using a grinder; andseparating the grinder from the surface of the semiconductor wafer only ...

WAFER PRODUCING APPARATUS

A wafer producing apparatus for producing an SiC wafer from a single-crystal SiC ingot includes an ingot grinding unit, a laser applying unit that applies a pulsed laser beam having a wavelength that is transmittable through the single-crystal SiC ingot while positioning a focal point of the pulsed laser beam in the single-crystal SiC ingot at a depth corresponding to the thickness of the SiC wafer to be produced from an upper surface of the single-crystal SiC ingot, thereby forming a peel-off layer in the single-crystal SiC ingot, a wafer peeling unit that peels the SiC wafer off the peel-off layer in the single-crystal SiC ingot, and a delivery unit assembly that delivers the single-crystal SiC ingot between the ingot grinding unit, the laser applying unit, and the wafer peeling unit. 1. A wafer producing apparatus for producing an SiC wafer from a single-crystal SiC ingot , comprising:an ingot grinding unit that includes a first holding table for holding the single-crystal SiC ingot thereon and grinding means for grinding and planarizing an upper surface of the single-crystal SiC ingot held on the first holding table;a laser applying unit that includes a second holding table for holding the single-crystal SiC ingot thereon and laser applying means for applying a pulsed laser beam having a wavelength that is transmittable through the single-crystal SiC ingot while positioning a focal point of the pulsed laser beam in the single-crystal SiC ingot at a depth corresponding to the thickness of the SiC wafer to be produced from the upper surface of the single-crystal SiC ingot held on the second holding table, thereby forming a peel-off layer in the single-crystal SiC ingot;a wafer peeling unit that includes a third holding table for holding the single-crystal SiC ingot thereon and wafer peeling means for holding the upper surface of the single-crystal SiC ingot held on the third holding table and peeling the SiC wafer off the peel-off layer;a wafer housing unit ...

HIGH ASPECT RATIO GAP FILL

The present disclosure describes a method of forming a dielectric layer or a dielectric stack on a photoresist layer while minimizing or avoiding damage to the photoresist. In addition, the dielectric layer or dielectric stack can till high-aspect ratio openings and can be removed with etching. The dielectric layer or dielectric stack can be deposited with a conformal, low-temperature chemical vapor deposition process or a conformal, low-temperature atomic layer deposition process that utilizes a number of precursors and plasmas or reactant gases. 1. A method comprising:forming a plurality of patterned structures over a substrate;forming a spacer material over the plurality of patterned structures;disposing a photoresist layer over the spacer material;forming one or more openings in the photoresist layer to expose a portion of the spacer material;depositing a dielectric over the photoresist layer to fill the one or more openings; andetching the dielectric and the photoresist layer until the spacer material is exposed.2. The method of claim 1 , further comprising:removing the spacer material over a top surface of the plurality of patterned structures.3. The method of claim 1 , wherein the depositing the dielectric comprises depositing the dielectric with a plasma-enhanced chemical vapor deposition (PECVD) or a plasma-enhanced atomic layer deposition (PEALD) process.4. The method of claim 3 , wherein the PECVD or PEALD process uses a tris(dimethylamino)silane (3DMAS) claim 3 , a tetrakis(dimethylamino)titanium (TDMAT) claim 3 , a bis(tertiary-butyl-amino)silane (BTBAS) claim 3 , or a bis(diethylamino)silane (BDEAS) precursor and an oxygen claim 3 , a carbon dioxide claim 3 , an argon claim 3 , a nitrogen claim 3 , or a nitrogen-based plasma.5. The method of claim 3 , wherein the PECVD or PEALD process comprises a processing temperature below 300° C.6. The method of claim 1 , wherein the one or more openings have an aspect ratio greater than 10 to 1.7. A method ...

SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SAME

A substrate capable of achieving a lowered probability of defects produced in a step of forming an epitaxial film or a semiconductor element, a semiconductor device including the substrate, and a method of manufacturing a semiconductor device are provided. A substrate is a substrate having a front surface and a back surface, in which at least a part of the front surface is composed of single crystal silicon carbide, the substrate having an average value of surface roughness Ra at the front surface not greater than 0.5 nm, a standard deviation σ of that surface roughness Ra not greater than 0.2 nm, an average value of surface roughness Ra at the back surface not smaller than 0.3 nm and not greater than 10 nm, standard deviation σ of that surface roughness Ra not greater than 3 nm, and a diameter D of the front surface not smaller than 110 mm. 112-. (canceled)13. A substrate having a front surface and a back surface , the back surface having a distorted crystal lattice , and at least a part of said front surface is composed of single crystal silicon carbide ,said substrate having an average value of surface roughness Ra at said front surface not greater than 0.5 nm and a standard deviation of said surface roughness Ra not greater than 0.2 nm, and an average value of surface roughness Ra at said back surface not smaller than 0.3 nm and not greater than 10 nm and a standard deviation of said surface roughness Ra not greater than 3 nm, and a diameter of said front surface not smaller than 110 mm.14. The substrate according to claim 13 , wherein{'sup': 19', '3, 'nitrogen is introduced in said single silicon carbide, and concentration of said nitrogen in said single crystal silicon carbide is not higher than 2×10/cm.'}15. The substrate according to claim 13 , wherein{'sup': 18', '3', '19', '3, 'nitrogen is introduced in said single silicon carbide, and concentration of said nitrogen in said single crystal silicon carbide is not lower than 4×10/cmand not higher than 2×10/cm ...

WAFER SCALE ULTRASONIC SENSING DEVICE AND MANUFACTURING METHOD THEREOF

A wafer scale ultrasonic sensing device includes a substrate assembly, an ultrasonic component, a first protective layer, a first conductive circuit, a second conductive circuit, a second protective layer, a conductive material, electrical connection layers, and soldering portions. The substrate assembly includes a first wafer and a second wafer, and the second wafer covers a groove on the first wafer to define a hollow chamber. The first wafer, the second wafer, and the first protective layer are coplanar with the first conductive circuit on a first side surface and coplanar with the second conductive circuit on a second side surface. The second protective layer has an opening, where the conductive material is in the opening and is in contact with the ultrasonic component. The electrical connection layers are on the first side surface and the second side surface, and the soldering portions are respectively connected to the electrical connection layers. 1. A wafer scale ultrasonic sensing device , comprising:a substrate assembly, comprising a first wafer and a second wafer, wherein the first wafer is provided with a groove, and the second wafer is bonded with the first wafer and covers the groove to define a hollow chamber;an ultrasonic component on the second wafer, wherein projections of the ultrasonic component and the hollow chamber are overlapped in a perpendicular direction;a first protective layer on a first surface of the second wafer and surrounding the ultrasonic component;a first conductive circuit and a second conductive circuit on the first protective layer, and connected to an upper surface of the ultrasonic component, wherein the first wafer, the second wafer, the first protective layer and the first conductive circuit are coplanar on a first side surface, and the first wafer, the second wafer, the first protective layer and the second conductive circuit are coplanar on a second side surface;a second protective layer covering the first conductive ...

PLASMA DICING METHOD

Provided is a plasma dicing method. The plasma dicing method includes: performing plasma etching on a first surface of a substrate exposed between a plurality of membrane structures; forming a passivation layer on a semiconductor wafer to cover the plurality of membrane structures and at least one trench; performing plasma etching on a second surface of the substrate such that a through hole exposing a portion of the plurality of membrane structures and a dicing lane connected to the trench and having a width less than a width of the through hole are formed at the substrate; and removing the passivation layer and singulating the semiconductor wafer into a plurality of devices including a membrane partially exposed by the through hole. 1. A plasma dicing method comprising:providing a semiconductor wafer including a plurality of membrane structures arranged on a first surface of a substrate and spaced apart from each other;performing a first plasma etching process on the first surface of the substrate such that at least one trench is formed at the first surface of the substrate exposed between the plurality of membrane structures;forming a passivation layer on the semiconductor wafer to cover the plurality of membrane structures and the at least one trench;performing a second plasma etching process on a second surface of the substrate opposite to the first surface of the substrate such that a through hole exposing a portion of the plurality of membrane structures and a dicing lane connected to the at least one trench are formed on the second surface of the substrate, the dicing lane having a first width less than a second width of the through hole; andremoving the passivation layer and dividing the semiconductor wafer into a plurality of devices, each of the plurality of devices including a membrane structure, among plurality of membrane structure, partially exposed by the through hole.2. The plasma dicing method of claim 1 , wherein a first etch rate of the through ...

PRE-STACKING MECHANICAL STRENGTH ENHANCEMENT OF POWER DEVICE STRUCTURES

A method includes placing a coupling mechanism material layer on a backside of a wafer having power devices fabricated on a frontside thereof, and placing conductive spacer blocks on the coupling mechanism material layer on a backside of the selected wafer. The method further includes activating the coupling mechanism material to bond the conductive spacer blocks to the backside of the selected wafer, and singulating the wafer to separate the vertical device stacks, each of the singulated vertical device stacks including a device die bonded to, or fused with, a conductive spacer block. 1. A method , comprising:coupling a conductive spacer block to a carrier;coupling a solder or sinter material layer to the conductive spacer block;coupling a device die to the solder or sinter material layer;reflowing the solder material or sintering the sinter material to bond the device die and the conductive spacer block to form the vertical device stack; andremoving the vertical device stack from the carrier as a single pre-formed unit.2. The method of claim 1 , wherein the device die includes at least one of a fast recovery diode (FRD) or an insulated gate bipolar transistor (IGBT).3. The method of claim 1 , wherein the device die is about 100 microns thick or less.4. The method of claim 3 , wherein the device die includes a power device having a size that is greater than 25 square millimeters.5. The method of claim 1 , wherein the conductive spacer block has thickness in a range of about 100 microns to 2500 microns claim 1 , and wherein the solder or sinter material layer has thickness of about 50 microns to 300 microns.6. A method claim 1 , method comprising:placing a coupling mechanism material layer on a backside of a wafer having power devices fabricated on a frontside thereof;placing conductive spacer blocks on the coupling mechanism material layer on a backside of the selected wafer;activating the coupling mechanism material to bond the conductive spacer blocks to the ...

Shaped silicon ingot using layer transfer

A shaped crystalline ingot for an ion cleaving process has a major surface that is substantially planar, a first side face that is substantially planar along a first direction orthogonal to the major surface, and a second side face that is substantially planar along a second direction orthogonal to the major surface. The ion cleaving process is a process in which ions are implanted into the shaped crystalline ingot to form a cleave plane that separates a substrate comprising the major surface from the shaped crystalline ingot.

METHOD FOR PREPARING LOW-WARPAGE SEMICONDUCTOR SUBSTRATE

Disclosed is a method for preparing a low-warpage semiconductor substrate. The method includes: providing a first substrate and a second substrate, the first substrate including a first surface and a second surface which are opposite to each other, a first insulating layer is disposed on the first surface. A second insulating layer is disposed on the second surface. The second substrate includes a support layer, an oxidation layer arranged on a surface of the support layer, and a device layer arranged on a surface of the oxidation layer. The method further includes bonding the first substrate and the second substrate by using the device layer and the first insulating layer as an intermediate layer; and forming a passivation layer on a surface of the second insulating layer by means of adhesion, where the second insulating layer and the passivation layer are configured to adjust warpage of the semiconductor substrate. 1. A method for preparing a low-warpage semiconductor substrate , comprising:providing a first substrate and a second substrate, the first substrate comprising a first surface and a second surface which are opposite to each other, disposing a first insulating layer on the first surface, disposing a second insulating layer on the second surface, wherein the second substrate comprises a support layer, an oxidation layer arranged on a surface of the support layer, and a device layer arranged on a surface of the oxidation layer;bonding the first substrate and the second substrate by using the device layer and the first insulating layer as an intermediate layer;forming a passivation layer on a surface of the second insulating layer by means of adhesion, the second insulating layer and the passivation layer being configured to adjust warpage of the semiconductor substrate.2. The method for preparing the low-warpage semiconductor substrate according to claim 1 , wherein the passivation layer is a blue type claim 1 , and the first insulating layer and the ...

PROCESSING METHOD OF WAFER, PROTECTIVE SHEET, AND PROTECTIVE SHEET LAYING METHOD

There is provided a processing method of a wafer. The processing method includes a protective sheet preparation step of preparing a protective sheet including a first sheet that is thermocompression-bonded to a surface of the wafer by heating, a second sheet that is laid on the first sheet and has fluidity due to the heating, and a third sheet that is laid on the second sheet and keeps flatness even with the heating. The processing method also includes a protective sheet laying step of causing a side of the first sheet to face a front surface of the wafer and executing heating to execute thermocompression bonding to lay the protective sheet on the front surface of the wafer and a grinding step of causing a side of the protective sheet to be held by a holding surface of a chuck table and grinding a back surface of the wafer. 1. A processing method of a wafer , the processing method comprising: a first sheet that is thermocompression-bonded to a surface of the wafer by heating,', 'a second sheet that is laid on the first sheet and has fluidity due to the heating, and', 'a third sheet that is laid on the second sheet and keeps flatness even with the heating;, 'a protective sheet preparation step of preparing a protective sheet including'}a protective sheet laying step of causing a side of the first sheet to face a front surface of the wafer and executing heating to execute thermocompression bonding to lay the protective sheet on the front surface of the wafer; anda grinding step of causing a side of the protective sheet to be held by a holding surface of a chuck table and grinding a back surface of the wafer.2. A protective sheet laid on a surface of a wafer , the protective sheet comprising:a first sheet that is thermocompression-bonded to the surface of the wafer by heating;a second sheet that is laid on the first sheet and has fluidity due to the heating; anda third sheet that is laid on the second sheet and is allowed to keep flatness even with the heating.3. The ...

METHOD FOR PROCESSING A WAFER, AND LAYER STACK

In various embodiments, a method for processing a wafer is provided. The method includes forming a layer stack, including a support layer and a useful layer and a sacrificial region between them, said sacrificial region having, vis-à-vis a processing fluid, a lower mechanical and/or chemical resistance than the support layer and than the useful layer. The support layer has a depression, which exposes the sacrificial region. The method further includes forming at least one channel in the exposed sacrificial region by means of the processing fluid. The channel connects the depression to an exterior of the layer stack. 1. A method for processing a wafer , the method comprising:forming a layer stack, comprising a support layer and a useful layer and a sacrificial region between them, said sacrificial region having, vis-à-vis a processing fluid, at least one of a lower mechanical or chemical resistance than the support layer and than the useful layer;wherein the support layer has a depression, which exposes the sacrificial region;forming at least one channel in the exposed sacrificial region by means of the processing fluid, wherein the channel connects the depression to an exterior of the layer stack.2. The method of claim 1 ,wherein the useful layer comprises at least one electrical circuit element.3. The method of claim 1 ,wherein the depression is formed through the support layer or at least into the latter by virtue of material being removed from the support layer or by virtue of material being deposited by means of a mask.4. The method of claim 1 ,wherein the support layer comprises the wafer; orwherein the useful layer is arranged between the support layer and the wafer.5. The method of claim 1 ,wherein at least one of the useful layer and the support layer or the useful layer and the sacrificial region have an epitaxial relation to one another.6. The method of claim 1 ,wherein the useful layer is grown epitaxially onto the support layer and the sacrificial region ...

VERTICAL WAFER BOAT

A vertical wafer boat includes a plurality of struts formed with a shelf plate portion configured to mount a silicon wafer, and a top plate and a bottom plate which fix upper and lower ends of the struts. The shelf plate portion is inclined downward toward the center of the boat, and a wafer support portion which protrudes upward and abuts on an edge portion of the silicon wafer is formed at a distal end of the shelf plate portion. To obtain the vertical wafer boat which supports a silicon wafer to be processed by a shelf plate portion provided in multiple stages, the vertical wafer boat being capable of reducing a risk of contact between a warped outer peripheral portion of a wafer and the shelf plate portion and suppressing deflection of the silicon wafer even when the silicon wafer has a large diameter. 1. A vertical wafer boat comprising:a plurality of struts formed with a shelf plate portion being configured to mount a silicon wafer; anda top plate and a bottom plate which fix upper and lower ends of the struts,wherein the shelf plate portion is inclined downward toward the center of the boat, and a wafer support portion which protrudes upward and abuts on an edge portion of the silicon wafer is formed at a distal end of the shelf plate portion.2. The vertical wafer boat according to claim 1 , wherein an inclination angle of the shelf plate portion is in a range of 1° or more and 2° or less.3. The vertical wafer boat according to claim 1 , wherein an upper surface of the wafer support portion is formed in a horizontal plane.4. The vertical wafer boat according to claim 1 , wherein a length of the shelf plate portion in a radial direction is in a range of 40 mm or more and 80 mm or less.5. The vertical wafer boat according to claim 1 , wherein a length of the wafer support portion in a radial direction is in a range of 5 mm or more and 10 mm or less. The present invention relates to a vertical wafer boat, for example, relates to a vertical wafer boat which holds ...

METHODS OF REDUCING WAFER THICKNESS

A semiconductor wafer has a base material with a first thickness and first and second surfaces. A wafer scribe mark is disposed on the first surface of the base material. A portion of an interior region of the second surface of the base material is removed to a second thickness less than the first thickness, while leaving an edge support ring of the base material of the first thickness and an asymmetric width around the semiconductor wafer. The second thickness of the base material is less than 75 micrometers. The wafer scribe mark is disposed within the edge support ring. The removed portion of the interior region of the second surface of the base material is vertically offset from the wafer scribe mark. A width of the edge support ring is wider to encompass the wafer scribe mark and narrower elsewhere around the semiconductor wafer. 1. A method of thinning a semiconductor wafer , the method comprising:providing a semiconductor wafer including a base material with a first thickness between a first surface and a second surface of the base material;providing a wafer scribe identification mark on the first surface of the base material; andremoving a portion of an interior region of the second surface of the base material to leave a second thickness of the base material less than the first thickness and an edge support ring of the base material, the edge support ring having the first thickness and an asymmetric width around the semiconductor wafer where the wafer scribe identification mark is completely disposed within the edge support ring;wherein the first thickness of the edge support ring is uniform around the semiconductor wafer.2. The method of claim 1 , wherein the second thickness of the base material is less than 75 micrometers.3. The method of claim 1 , wherein the second thickness of the base material is 10-50 micrometers.4. The method of claim 1 , wherein the removed portion of the interior region of the second surface of the base material is vertically ...

THINNED SEMICONDUCTOR WAFER

A semiconductor wafer has a base material with a first thickness and first and second surfaces. A wafer scribe mark is disposed on the first surface of the base material. A portion of an interior region of the second surface of the base material is removed to a second thickness less than the first thickness, while leaving an edge support ring of the base material of the first thickness and an asymmetric width around the semiconductor wafer. The second thickness of the base material is less than 75 micrometers. The wafer scribe mark is disposed within the edge support ring. The removed portion of the interior region of the second surface of the base material is vertically offset from the wafer scribe mark. A width of the edge support ring is wider to encompass the wafer scribe mark and narrower elsewhere around the semiconductor wafer. 1. A semiconductor wafer including a base material , comprising:a wafer scribe mark on a first surface of the base material;an edge support ring of the base material with a first thickness and an asymmetric width around the semiconductor wafer; andan interior region of a second surface of the base material with a second thickness less than the first thickness, wherein the wafer scribe mark is disposed within the edge support ring.2. The semiconductor wafer of claim 1 , wherein the wafer scribe mark is an identification mark.3. The semiconductor wafer of claim 1 , wherein the second thickness of the base material is less than 75 micrometers.4. The semiconductor wafer of claim 1 , wherein the second thickness of the base material is 10-50 micrometers.5. The semiconductor wafer of claim 1 , wherein a width of the semiconductor wafer is 150-300 millimeters.6. The semiconductor wafer of claim 1 , wherein the interior region of the base material is offset from the wafer scribe mark.7. The semiconductor wafer of claim 1 , wherein a width of the edge support ring is wider to encompass the wafer scribe mark and narrower elsewhere around the ...

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

A method for forming a semiconductor structure includes forming a dielectric layer on a substrate, including a first region and a second region; forming a first gate opening and a second gate opening in dielectric layer of the first region and the second region, respectively; forming initial work function layers on bottom and sidewall surfaces of the first gate opening and the second gate opening; and performing at least one cycle of a combined etching process to etch the initial work function layers formed in the first gate opening and form a work function layer in the second gate opening from the initial work function layers. Each cycle of the combined etching process includes performing an oxide etching process to etch the initial work function layers; and then performing a main etching process on the initial work function layers to remove an exposed initial work function layer. 1. A method for forming a semiconductor structure , comprising: a substrate, including a first region and a second region, and', 'a dielectric layer disposed on the substrate, wherein the dielectric layer in the first region includes a first gate opening, and the dielectric layer in the second region includes, 'providing a substrate structure, includinga second gate opening;forming a plurality of initial work function layers on bottom and sidewall surfaces of the first gate opening and bottom and sidewall surfaces of the second gate opening; and performing an oxide etching process to etch the plurality of initial work function layers; and', 'after the oxide etching process, performing a main etching process on the plurality of initial work function layers to remove an exposed initial work function layer of the plurality of initial work function layers., 'performing at least one cycle of a combined etching process to etch the plurality of initial work function layers formed in the first gate opening and form a work function layer in the second gate opening from the plurality of initial ...

METHOD AND DEVICE FOR SLICING A SHAPED SILICON INGOT USING LAYER TRANSFER

A method for slicing a crystalline material ingot includes providing a crystalline material boule characterized by a cropped structure including a first end-face, a second end-face, and a length along an axis in a first crystallographic direction extending from the first end-face to the second end-face. The method also includes cutting the crystalline material boule substantially through a first crystallographic plane in parallel to the axis to separate the crystalline material boule into a first portion with a first surface and a second portion with a second surface. The first surface and the second surface are planar surfaces substantially along the first crystallographic plane. The method further includes exposing either the first surface of the first portion or the second surface of the second portion, and performing a layer transfer process to form a crystalline material sheet from either the first surface of the first portion or from the second surface of the second portion. 1. A method for slicing a crystalline material ingot , the method comprising:providing a crystalline material boule characterized by a cropped structure including a first end-face, a second end-face, and a length along an axis in a first crystallographic direction substantially extending from the first end-face to the second end-face;cutting the crystalline material boule substantially through a first crystallographic plane in parallel to the axis to separate the crystalline material boule into a first portion with a first surface and a second portion with a second surface, wherein the first surface of the first portion is a planar surface substantially along the first crystallographic plane, and the second surface of the second portion is a planar surface substantially along the first crystallographic plane;exposing either the first surface of the first portion or the second surface of the second portion; andperforming a layer transfer process to form a crystalline material sheet from ...

WAFER PROCESSING METHODS

Wafer processing methods are provided. The methods may include cutting respective edges of a wafer and an adhesive a predetermined angle before grinding a back surface of the wafer. 1. A wafer processing method comprising:attaching a first wafer to a second wafer using an adhesive extending between the first wafer and the second wafer, a front surface of the first wafer facing the second wafer;cutting respective edges of the first wafer, the adhesive and the second wafer at a predetermined angle with respect to a back surface of the first wafer opposite the front surface of the first wafer, a cut side of the first wafer comprising a sloped side; andgrinding the back surface of the first wafer.2. The method of claim 1 , wherein the predetermined angle is in a range of about 35° to about 45°.3. The method of claim 1 , wherein cutting the edges of the first wafer claim 1 , the adhesive and the second wafer comprises cutting an edge only in an upper half of the second wafer.4. The method of claim 1 , wherein grinding the back surface of the first wafer comprises grinding the first wafer until a thickness of the first wafer becomes equal to or less than about 100 μm.5. The method of claim 1 , wherein cutting the edges of the first wafer claim 1 , the adhesive and the second wafer is performed using a cutting bit having a tip in a shape corresponding to the predetermined angle.6. The method of claim 1 , wherein a thickness of the adhesive is in a range of about 5 μm to about 200 μm.7. The method of claim 1 , wherein cutting the edges of the first wafer claim 1 , the adhesive and the second wafer comprises cutting the edge of the first wafer to reduce a diameter of the back surface of the first wafer by at least about 1 claim 1 ,000 μm.8. The method of claim 1 , further comprising disposing wires on the back surface of the first wafer and arranging bumps on the respective wires after grinding the back surface of the first wafer.9. The method of claim 8 , further comprising ...

METHOD FOR POLISHING SILICON SUBSTRATE AND POLISHING COMPOSITION SET

Provided are a method for polishing a silicon substrate according to which PID can be reduced and a polishing composition set usable in the polishing method. The silicon substrate polishing method provided by this invention comprises a stock polishing step and a final polishing step. The stock polishing step comprises several stock polishing sub-steps carried out on one same platen. The several stock polishing sub-steps comprise a final stock polishing sub-step carried out while supplying a final stock polishing slurry Pto the silicon substrate. The total amount of the final stock polishing slurry Psupplied to the silicon substrate during the final stock polishing sub-step has a total weight of Cu and a total weight of Ni, at least one of which being 1 μg or less. 1. A method for polishing a silicon substrate , the method comprising ,a stock polishing step and a final polishing step, whereinthe stock polishing step comprises several stock polishing sub-steps that are carried out on one same platen,{'sub': 'F', 'the several stock polishing sub-steps comprise a final stock polishing sub-step that is carried out while supplying a final stock polishing slurry Pto the silicon substrate, and'}{'sub': 'F', 'the total amount of the final stock polishing slurry Psupplied to the silicon substrate during the final stock polishing sub-step has a total weight of Cu and a total weight of Ni, at least one of which being 1 μg or less.'}2. The polishing method according to claim 1 , wherein claim 1 , in the final stock polishing sub-step claim 1 , the total weight of Cu and the total weight of Ni in the total amount of the final stock polishing slurry Psupplied to the silicon substrate add to a total of 2 μg or less claim 1 ,3. A method for polishing a silicon substrate claim 1 , the method comprisinga stock polishing step and a final polishing step, whereinthe stock polishing step comprises several stock polishing sub-steps that are earned out on one same platen, [{'sub': 'F', 'a ...

Method for chemical mechanical polishing substrates containing ruthenium and copper

A method for chemical mechanical polishing of a substrate comprising ruthenium and copper.

HYBRID WAFER DICING APPROACH USING A RECTANGULAR SHAPED TWO-DIMENSIONAL TOP HAT LASER BEAM PROFILE OR A LINEAR SHAPED ONE-DIMENSIIONAL TOP HAT LASER BEAM PROFILE LASER SCRIBING PROCESS AND PLASMA ETCH PROCESS

Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a top hat laser beam profile laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits. 1. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits , the method comprising:forming a mask above the semiconductor wafer, the mask comprising a layer covering and protecting the integrated circuits;patterning the mask with a top hat laser beam profile laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits, wherein the top hat laser beam profile laser scribing process comprises scribing with a laser beam having a rectangular shaped two-dimensional top hat beam, wherein scribing with the laser beam having the rectangular shaped two-dimensional top hat beam comprises shaping a Gaussian-shaped beam into the rectangular shaped two-dimensional top hat beam;subsequent to patterning the mask with the top hat laser beam profile laser scribing process, cleaning the exposed regions of the semiconductor wafer with a plasma process; andsubsequent to cleaning the exposed regions of the semiconductor wafer with the plasma process, plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the integrated circuits.2. (canceled)3. The method of claim 1 , wherein scribing with the laser beam having the rectangular shaped two-dimensional top hat beam comprises using a femto-second ...

BACK-SIDE FRICTION REDUCTION OF A SUBSTRATE

A processing chamber system includes a substrate mounting module configured to secure a substrate within a first processing chamber. The system also includes a first deposition module configured to apply a light-sensitive film to a front side surface of the substrate, and a second deposition module configured to apply a film layer to a backside surface of the substrate. The front side surface is opposite to the backside surface of the substrate. A substrate has a bare backside surface with a first coefficient of friction. A film layer is formed onto the backside surface of the substrate. The film layer formed on the backside surface of the substrate has a second coefficient of friction. The second coefficient of friction is lower than the first coefficient of friction. 1. A method of treating a substrate , the method comprising:receiving the substrate into a substrate processing chamber, the substrate having a front side surface and a backside surface opposite to the front side surface;forming a film layer on the backside surface of the substrate;forming a photoresist layer on the front side surface of the substrate;developing the photoresist layer; andremoving the film layer from the backside surface of the substrate.2. The method of claim 1 , whereinthe backside surface of the substrate has a first coefficient of friction prior to forming the film layer,the film layer formed on the backside surface of the substrate has a second coefficient of friction, andthe second coefficient of friction is lower than the first coefficient of friction.3. The method of claim 1 , wherein the film layer comprises a fluorochemical layer.4. The method of claim 3 , wherein the fluorochemical layer comprises one of perfluorodecyltrichlorosilane claim 3 , perfluorocthylrichlorosilane claim 3 , perfluorheptachlorosilane claim 3 , perfluorobuthylchlorosilane claim 3 , perfluoroooctyltriethoxysilane claim 3 , perfluorodecyltriethoxysilane claim 3 , perfluoroooctyltrimethoxysilane claim 3 , ...

METHOD FOR MANUFACTURING LIGHT EMITTING DIODE DEVICE

According to one embodiment, a method for manufacturing an LED device includes forming a laminated semiconductor layer including a GaN layer of a first conductivity type, a GaN-based luminous layer, and a GaN layer of a second conductivity type stacked in this order on a surface of a substrate, forming a resist pattern on the laminated semiconductor layer, subjecting the laminated semiconductor layer to reactive ion etching using the resist pattern as a mask to selectively remove the laminated semiconductor layer to form an LED element structure part and an electrode connection region, removing the resist pattern, and treating the substrate including the LED element structure part and the electrode connection region with a first etching residue removing aqueous solution. 1. A method for manufacturing an LED device comprising:forming a laminated semiconductor layer including a GaN layer of a first conductivity type, a GaN-based luminous layer, and a GaN layer of a second conductivity type stacked in this order on a surface of a substrate;forming a resist pattern with a predetermined shape on the laminated semiconductor layer;subjecting the laminated semiconductor layer to reactive ion etching using the resist pattern as a mask to selectively remove the laminated semiconductor layer so that the GaN layer of the first conductivity type remains to have a predetermined thickness on a surface of the substrate, thereby forming an LED element structure part and an electrode connection region integrated with the GaN layer of the first conductivity type of the structure part on the substrate;removing the resist pattern; andtreating the substrate including the LED element structure part and the electrode connection region with a first etching residue removing aqueous solution containing a peroxosulfate, a fluorine-containing compound, and an acid for pH adjustment, and possessing a pH value of 0 to 3.2. The method of claim 1 , wherein the substrate is a sapphire substrate.3. ...

WAFER STRUCTURE AND TRIMMING METHOD THEREOF

A wafer structure and a trimming method thereof are provided. The trimming method includes the following steps. A first wafer having a first surface and a second surface opposite to the first surface is provided. A first pre-trimming mark is formed on the first surface of the first wafer, where forming the first pre-trimming mark includes forming a plurality of recesses arranged as a path along a periphery of the first wafer. The first wafer is trimmed on the first pre-trimming mark and along the path of the first pre-trimming mark to remove a portion of the first wafer and form a trimmed edge having first regions thereon. 1. A trimming method , comprising:providing a first wafer having a first surface and a second surface opposite to the first surface;forming a first pre-trimming mark on the first surface of the first wafer, wherein forming the first pre-trimming mark comprises forming a plurality of recesses arranged as a path along a periphery of the first wafer; andtrimming the first wafer on the first pre-trimming mark and along the path of the first pre-trimming mark to remove a portion of the first wafer and form a trimmed edge having first regions thereon.2. The trimming method according to claim 1 , wherein forming the first pre-trimming mark on the first surface of the first wafer comprises:performing an etching process to the first surface of the first wafer to form the first pre-trimming mark, wherein the first regions comprise etching streaks.3. The trimming method according to claim 1 , wherein forming the first pre-trimming mark on the first surface of the first wafer comprises:performing a laser marking process to the first surface of the first wafer to form the first pre-trimming mark, wherein the first regions comprise laser marking streaks.4. The trimming method according to claim 1 , wherein trimming the first wafer comprises:cutting into the first wafer and cutting through the first pre-trimming mark to a trimming depth, wherein the trimming ...

METHOD FOR PRODUCING SEMICONDUCTOR EPITAXIAL WAFER AND SEMICONDUCTOR EPITAXIAL WAFER

A method for producing a semiconductor epitaxial wafer, including steps of: fabricating an epitaxial wafer by epitaxially growing a semiconductor layer on a silicon-based substrate; observing the outer edge portion of the fabricated epitaxial wafer; and removing portions in which a crack, epitaxial layer peeling, and a reaction mark observed in the step of observing are present. As a result, a method for producing a semiconductor epitaxial wafer in which a completely crack-free semiconductor epitaxial wafer can be obtained, is provided. 111-. (canceled)12. A method for producing a semiconductor epitaxial wafer , comprising:fabricating an epitaxial wafer by epitaxially growing a semiconductor layer on a silicon-based substrate;observing an outer edge portion of the fabricated epitaxial wafer; andremoving portions in which a crack, epitaxial layer peeling, and a reaction mark observed in the step of observing are present.13. The method for producing a semiconductor epitaxial wafer according to claim 12 , whereinin the step of removing, the portions in which the crack, the epitaxial layer peeling, and the reaction mark are present are ground without change in an outside diameter of the silicon-based substrate of the epitaxial wafer.14. The method for producing a semiconductor epitaxial wafer according to claim 13 , whereinafter the step of removing, a ground surface of the epitaxial wafer is turned into a mirror surface or a quasi-mirror surface by mixed acid etching.15. The method for producing a semiconductor epitaxial wafer according to claim 14 , whereinan overhang portion of the epitaxial layer, the overhang portion formed as a result of the silicon-based substrate being etched by the mixed acid etching, is removed by chamfering.16. The method for producing a semiconductor epitaxial wafer according to claim 12 , whereinthe semiconductor layer is composed of a nitride semiconductor.17. The method for producing a semiconductor epitaxial wafer according to claim 13 , ...

METHOD FOR MANUFACTURING SIC WAFER FIT FOR INTEGRATION WITH POWER DEVICE MANUFACTURING TECHNOLOGY

A method for producing silicon carbide substrates fit for epitaxial growth in a standard epitaxial chamber normally used for silicon wafers processing. Strict limitations are placed on any substrate that is to be processed in a chamber normally used for silicon substrates, so as to avoid contamination of the silicon wafers. To take full advantage of standard silicon processing equipment, the SiC substrates are of diameter of at least 150 mm. For proper growth of the SiC boule, the growth crucible is made to have interior volume that is six to twelve times the final growth volume of the boule. Also, the interior volume of the crucible is made to have height to width ratio of 0.8 to 4.0. Strict limits are placed on contamination, particles, and defects in each substrate. 1. A method for manufacturing SiC crystal to a grown volume , comprising:i. introducing a mixture comprising silicon chips into a reaction cell, the reaction cell being made of graphite and having cylindrical interior of internal volume in the range of from six to twelve times the grown volume of the SiC crystal;ii. placing a silicon carbide seed crystal inside the reaction cell adjacent to a lid of the reaction cell;iii. sealing the cylindrical reaction cell using the lid;iv. surrounding the reaction cell with graphite insulation;v. introducing the cylindrical reaction cell into a vacuum furnace;vi. evacuating the vacuum furnace;vii. filling the vacuum furnace with a gas mixture comprising inert gas to a pressure near atmospheric pressure;viii. heating the cylindrical reaction cell in the vacuum furnace to a temperature in the range from 1975° C. to 2500° C.;ix. reducing the pressure in the vacuum furnace to from 0.05 torr to less than 50 torr;{'sup': 2', '2, 'x. introducing source of carbon gas into the vacuum furnace and flowing nitrogen gas configured to introduce nitrogen donor concentration larger than 3E18/cm, and up to 6E18/cm; and,'}xi. allowing for sublimation of silicon and carbon species ...

Carrier System For Processing Semiconductor Substrates, and Methods Thereof

In accordance with an alternative embodiment of the present invention, a method for forming a semiconductor device includes applying a paste over a semiconductor substrate, and forming a ceramic carrier by solidifying the paste. The semiconductor substrate is thinned using the ceramic carrier as a carrier. 1. A method for forming a semiconductor device , the method comprising:forming device regions in a semiconductor substrate comprising a first side and a second side, wherein the device regions are formed adjacent the first side;forming contact pads over the semiconductor substrate to contact the device regions, the contact pads separated by openings;applying a liquid paste over the first side of the semiconductor substrate, the liquid paste surrounding the contact pads and filling the openings;sintering the liquid paste to form an isolating substrate comprising a curved top surface;planarizing the isolating substrate to form a carrier disposed over the first side of the semiconductor substrate, the carrier formed within the opening and surrounding the contact pads;mounting the first side of the semiconductor substrate on the carrier; andsingulating the semiconductor substrate and the carrier to form a plurality of semiconductor dies.2. The method of claim 1 , further comprising:mounting the carrier on a chuck of a process tool; andperforming a processing on the second side of the semiconductor substrate.3. The method of claim 2 , wherein performing the processing comprises performing a back side grinding process to thin the semiconductor substrate.4. (canceled)5. The method of claim 1 , further comprising forming back side metallization over the second side of the semiconductor substrate using the planarized isolating substrate as the carrier.6. The method of claim 1 , further comprising thinning the carrier before the singulating.7. A method for forming a semiconductor device claim 1 , the method comprising:applying a paste over a semiconductor wafer, the ...

SEMICONDUCTOR DEVICE MANUFACTURING METHOD

A semiconductor device manufacturing method includes thinning a wafer to form a wafer having an annular protruding portion on a peripheral portion thereof by grinding a central portion of a back surface of the wafer and then performing wet etching on the back surface of the wafer, forming a backside electrode on the back surface of the wafer, performing plating to evenly form a metal film on a portion of the backside electrode on the annular protruding portion, attaching a dicing tape to the metal film, and dicing the wafer having the dicing tape attached thereto. 1. A semiconductor device manufacturing method comprising:thinning a wafer to form a wafer having an annular protruding portion on a peripheral portion thereof by grinding a central portion of a back surface of the wafer and then performing wet etching on the back surface of the wafer;forming a backside electrode on the back surface of the wafer,performing plating to evenly form a metal film on a portion of the backside electrode on the annular protruding portion;attaching a dicing tape to the metal film; anddicing the wafer having the dicing tape attached thereto.2. The semiconductor device manufacturing method according to claim 1 , whereinthe backside electrode is an Al alloy layer, andin the plating, the wafer is immersed in a zincate solution to deposit Zn on a surface of the Al alloy layer by displacement, the deposited Zn is removed, then the wafer is immersed in a zincate solution again to deposit Zn on the surface of the Al alloy layer by displacement, and subsequently the wafer is immersed in an electroless Ni plating solution.3. The semiconductor device manufacturing method according to claim 2 , wherein a Ni film formed by immersing the wafer in the electroless Ni plating solution has a thickness ranging from 2 to 10 μm.4. The semiconductor device manufacturing method according to claim 2 , wherein in the plating claim 2 , after the wafer is immersed in the electroless Ni plating solution claim ...

TFT BACKPLANE AND MANUFACTURING METHOD THEREOF

The invention provides a TFT backplane structure and manufacturing method thereof. The TFT backplane structure uses the three-layered structure, from bottom up, dielectric layer (), SiNx layer (), and SiOlayer (), for the gate insulating layer () corresponding to the location of the TFT (T), to enhance the TFT reliability; uses a double-layered gate insulating layer (), from bottom up, the dielectric layer (), and at least a portion of SiNx layer (), at the location corresponding to the storage capacitor (C), or a single-layered gate insulating layer (), i.e., the dielectric layer (), at the location corresponding to the storage capacitor (C), the dielectric constant can be increased, the distance between the two storage capacitor electrode plates is reduced, resulting in reducing the capacitor area and improve aperture ratio on the premise of storage capacitance performance. 1. A thin film transistor (TFT) backplane structure , which comprises: a substrate , a buffer layer covering the substrate , a polysilicon active layer and a polysilicon electrode plate , disposed on the buffer layer with gap to separate from each other , a gate insulating layer covering the polysilicon active layer , the polysilicon electrode plate and the buffer layer , a gate disposed on the gate insulating layer above the polysilicon active layer , a metal electrode plate disposed on the gate insulating layer above the polysilicon electrode plate , an interlayer insulating layer covering the gate , the metal electrode plate and the gate insulating layer , and a source and a drain disposed on the interlayer insulating layer;the polysilicon active layer, the gate, the source and the drain constituting a TFT, and the polysilicon electrode plate and the metal electrode plate constituting a storage capacitor;{'sub': '2', 'the gate insulating layer having a three-layered structure at the location corresponding to the TFT, which comprising, from bottom up, a dielectric layer, a SiNx layer, and a ...

Temperature modification for chemical mechanical polishing

Among other things, one or more systems and techniques for increasing temperature for chemical mechanical polishing (CMP) are provided. For example, a liquid heater component is configured to supply heated liquid to a polishing pad upon which a semiconductor wafer is to be polished, resulting in a heated polishing pad having a heated polishing pad temperature. The increased temperature of the heated polishing pad increases oxidation of the semiconductor wafer, which improves a CMP removal rate of material from the semiconductor wafer due to a decreased oxidation timespan and a stabilization timespan for reaching a stable CMP removal rate during CMP. In this way, the semiconductor wafer is polished utilizing the heated polishing pad, such as by a tungsten CMP process.

ACIDIC ETCHING PROCESS FOR SI WAFERS

The present invention relates to a method for acidic surface etching of a silicon wafer, such as those used for solar cells, comprising contacting at least one surface of a silicon wafer as cut with an acidic etching agent, provided that the wafer is, prior to the acidic etching, not subjected to an alkaline etching step or process. Further, the present invention is directed to Si wafer, photovoltaic cells, PERC photovoltaic cells and solar modules produced according to the method of the present invention. 1. A method for acidic etching of a Si wafer , comprising contacting at least one surface of a Si wafer as cut with an acidic etching agent with the proviso that the Si wafer is , prior to the acidic etching , not subjected to an alkaline etching step or process.2. The method according to claim 1 , wherein the Si wafer is a monocrystalline or a quasi-monocrystalline Si wafer.3. The method according to claim 1 , wherein the Si wafer is saw-damaged and/or cleaned prior to etching.4. The method according to claim 1 , wherein the acidic etching agent is an aqueous solution of an acid selected from the group consisting of HF claim 1 , HCl claim 1 , HBr claim 1 , HI claim 1 , AcOH claim 1 , HNO claim 1 , HPO claim 1 , HSO claim 1 , citric acid claim 1 , oxalic acid claim 1 , lactic acid and mixtures Thereof.5. The method according to claim 1 , wherein the acid etching agent is an aqueous solution containing a mixture of AcOH claim 1 , HNOand HF.6. The method according to claim 5 , wherein the solution comprises AcOH (98 wt.-% in water) claim 5 , HNO3 (69 wt.-% in water) claim 5 , and HF (49 wt.-% in water) claim 5 , wherein the volume ratio of AcOH:HNO:HF is 10:6:4.7. The method according to claim 1 , wherein the acid etching agent is a mixture of HNOand HF.8. The method according to claim 7 , wherein the mixture consists of HNO(67-70 wt.-% in water) and HF (49 wt.-% in water) claim 7 , wherein the volume ratio of HNO:HF gradually changes over time from about 6:1 to 10: ...

Wafer Thinning Method and Wafer Structure

A wafer thinning method and a wafer structure are provided. In the wafer thinning method, a to-be-thinned wafer is provided, and the to-be-thinned wafer is grinded on a rear surface of the to-be-thinned wafer. Then, a first planarization process is performed on a rear surface of the grinded wafer to restore surface flatness of the grinded wafer, and a second planarization process is performed on a rear surface of the wafer obtained after the first planarization process is performed until a target thinned thickness is reached. 1. A wafer thinning method , comprising:providing a to-be-thinned wafer;grinding the to-be-thinned wafer on a rear surface of the to-be-thinned wafer;performing a first planarization process on a rear surface of the grinded wafer to restore surface flatness of the grinded wafer; andperforming a second planarization process on a rear surface of the wafer obtained after the first planarization process is performed until a target thinned thickness is reached.2. The method according to claim 1 , wherein each of the first planarization process and the second planarization process is a chemical-mechanical planarization process.3. The method according to claim 1 , wherein the to-be-thinned wafer is a silicon wafer.4. The method according to claim 1 , wherein the to-be-thinned wafer is bonded to another wafer.5. The method according to claim 1 , wherein an error of the surface flatness of the grinded wafer is less than 0.5 μm.6. The method according to claim 2 , wherein an error of the surface flatness of the grinded wafer is less than 0.5 μm.7. The method according to claim 3 , wherein an error of the surface flatness of the grinded wafer is less than 0.5 μm.8. The method according to claim 4 , wherein an error of the surface flatness of the grinded wafer is less than 0.5 μm.9. The method according to claim 1 , wherein the grinding is controlled by performing the following processes comprising:controlling a grinder to grind the to-be-thinned wafer ...

Method And Apparatus For Determining Expansion Compensation In Photoetching Process, And Method For Manufacturing Device

A method and an apparatus for determining expansion compensation in a photoetching process, and a method for manufacturing a semiconductor device are provided. A relative vector misalignment value of a first wafer and a second wafer after being bonded is obtained based on a relative position relationship between a first alignment pattern of the first wafer and a second alignment pattern of the second wafer in a boding structure. A relative expansion value of the first wafer and the second wafer is obtained based on the relative vector misalignment value. A developing expansion compensation value in the photoetching process is obtained. The expansion compensation value is used to the photoetching process of a first conductor layer including the first alignment pattern of the first wafer and/or a second conductor layer including the second alignment pattern of the second wafer. 1. A method for determining expansion compensation in a photoetching process , wherein expansion compensation on the photoetching process is performed based on a bonding structure; the bonding structure comprises a first wafer and a second wafer to be bonded , the first wafer is provided with a first conductor layer comprising a first wiring layer and a first alignment pattern , the second wafer is provided with a second conductor layer comprising a second wiring layer and a second alignment pattern; the bonding structure is obtained by aligning the first wafer with the second wafer through the first alignment pattern and the second alignment pattern , and bonding the first wafer to the second wafer; and wherein the method comprises:obtaining a relative vector misalignment value of the first wafer and the second wafer based on a relative position relationship between the first alignment pattern and the second alignment pattern in the bonding structure;obtaining a relative expansion value of the first wafer and the second wafer based on the relative vector misalignment value; anddetermining a ...

Grinding Control Method And Device For Wafer, And Grinding Device

A grinding control method and device for a wafer, and a grinding device are provided. A grinder is controlled to grind a mass production wafer with a set grinding parameter. In a case that it is determined to perform a test using a test wafer, the grinder may be controlled to grind the test wafer with the set grinding parameter. A first total thickness variation of the grinded test wafer is acquired by a dedicated measurement device, and an updated grinding parameter is acquired based on the first total thickness variation. The grinder is controlled to grind the mass production wafer with the updated grinding parameter. In this way, a wafer with a uniform thickness can be obtained, thereby improving flatness of the grinded wafer. 1. A grinding control method for a wafer , comprising:controlling a grinder to grind a mass production wafer with a set grinding parameter;determining whether to perform a test using a test wafer;controlling, in a case that it is determined to perform the test using the test wafer, the grinder to grind a test wafer with the set grinding parameter; andacquiring an updated grinding parameter, and updating the set grinding parameter to be the updated grinding parameter, and controlling the grinder to grind the mass production wafer with the updated grinding parameter, wherein the updated grinding parameter is determined based on a first total thickness variation of the grinded test wafer, and the first total thickness variation of the grinded test wafer is acquired by a dedicated measurement device.2. The grinding control method according to claim 1 , wherein the determining whether to perform the test using the test wafer comprises:determining whether the number of the mass production wafer reaches a mass production cycle; anddetermining to perform the test using the test wafer in a case that the number of the mass production wafer reaches the mass production cycle.3. The grinding control method according to claim 1 , wherein 'acquiring, by ...

Wafer processing method

A wafer processing method includes forming a resist film on the front side of a wafer in an area except division lines, plasma etching the wafer to form a groove on the front side of the wafer along each division line, the groove having a depth greater than a finished thickness, removing the resist film from the front side of the wafer by cleaning, and grinding the back side of the wafer to reduce the thickness of the wafer to the finished thickness, so that the groove is exposed to the back side of the wafer to thereby divide the wafer into individual device chips. In the resist film removing step, a chemical fluid is sprayed to the resist film formed on the front side of the wafer, thereby removing the resist film.

SEMICONDUCTOR WAFER AND METHOD OF WAFER THINNING USING GRINDING PHASE AND SEPARATION PHASE

A semiconductor wafer has a base material. The semiconductor wafer may have an edge support ring. A grinding phase of a surface of the semiconductor wafer removes a portion of the base material. The grinder is removed from or lifted off the surface of the semiconductor wafer during a separation phase. The surface of the semiconductor wafer and under the grinder is rinsed during the grinding phase and separation phase to remove particles. A rinsing solution is dispensed from a rinsing solution source to rinse the surface of the semiconductor wafer. The rinsing solution source can move in position while dispensing the rinsing solution to rinse the surface of the semiconductor wafer. The grinding phase and separation phase are repeated during the entire grinding operation, when grinding conductive TSVs, or during the final grinding stages, until the final thickness of the semiconductor wafer is achieved. 1. A method of making a semiconductor device , comprising:providing a semiconductor wafer including a base material;grinding a surface of the semiconductor wafer during a grinding phase using a grinder to remove a portion of the base material;lifting the grinder off the surface of the semiconductor wafer during a separation phase; andrinsing the surface of the semiconductor wafer and under the grinder during the separation phase to remove particles.2. The method of claim 1 , further including repeating the grinding phase and separation phase.3. The method of claim 1 , further including rinsing the surface of the semiconductor wafer during the grinding phase and separation phase to remove the particles.4. The method of claim 1 , further including lifting the grinder 3-10 micrometers off the surface of the semiconductor wafer.5. The method of claim 1 , further including pausing movement of the grinder in the downward direction during the separation phase.6. The method of claim 1 , wherein the semiconductor wafer includes an edge support ring.7. A method of making a ...

SILICON WAFER AND METHOD FOR MANUFACTURING THE SAME

A silicon wafer is manufactured by subjecting a silicon wafer sliced from a silicon single-crystal ingot grown by the Czochralski process to a rapid thermal process in which the silicon wafer is heated to a maximum temperature within a range of 1300 to 1380° C., and kept at the maximum temperature for 5 to 60 seconds; and removing a surface layer of the wafer where a semiconductor device is to be manufactured by a thickness of not less X [μm] which is calculated according to the below equations (1) to (3): 1. A method of manufacturing a silicon wafer comprising:subjecting a silicon wafer sliced from a silicon single-crystal ingot grown by a Czochralski process to a rapid thermal process in which the silicon wafer is heated to a maximum temperature within a range of 1300 to 1380° C., and kept at the maximum temperature for 5 to 60 seconds; and [{'br': None, 'i': X', 'a', 'b, '[μm]=[μm]+[μm]\u2003\u2003(1);'}, {'br': None, 'i': 'a', 'sup': '−0.4', '[μm]=(0.0031×(said maximum temperature)[° C.]−3.1)×6.4×(cooling rate)[° C./second] . . . (2); and'}, {'br': None, 'i': b', 'a, 'sup': 3', '3, '[μm]=/(solid solubility limit of oxygen)[atoms/cm]/(oxygen concentration in substrate)[atoms/cm]\u2003\u2003(3).'}], 'removing a surface layer of the wafer where a semiconductor device is to be manufactured by a thickness of not less X [μm] which is calculated according to below-identified equations (1) to (3)2. The method of claim 1 , wherein during the step of removing the surface layer claim 1 , a side peripheral surface of the silicon wafer is removed by a thickness which is not more than the above-defined value “a”.3. The method of claim 1 , wherein during the step of removing the surface layer claim 1 , a bevel surface of the wafer is removed such that oxygen precipitation nuclei are exposed.4. A silicon wafer manufactured by the method of claim 1 , wherein at least said surface layer is free of crystal-originated particles and oxygen precipitation nuclei claim 1 , and wherein ...

METHOD OF DOUBLE-SIDE POLISHING SEMICONDUCTOR WAFER

Provided is a method of double-side polishing a semiconductor wafer, which can suppress variation in the polishing quality by providing for changes in the polishing environment during polishing. The method of double-side polishing of a semiconductor wafer includes: a step of predetermining a criterion function for determining polishing tendencies of double-side polishing; a first step of starting double-side polishing of the semiconductor wafer under initial polishing conditions; a second step of while performing double-side polishing on the semiconductor wafer under the initial polishing conditions, calculating a value of the criterion function using the apparatus log data in a predetermined period of polishing in the first step, and setting on the double-side polishing apparatus polishing conditions obtained by adjusting the initial polishing conditions based on the value of the criterion function; and a third step of performing double-side polishing of the semiconductor wafer under the adjusted polishing conditions. 1. A method of double-side polishing of a semiconductor wafer using a double-side polishing apparatus , comprising:a step of predetermining a criterion function for determining polishing tendencies of double-side polishing by performing multiple regression analysis based on a shape index of a plurality of semiconductor wafers having subjected to double-side polishing using the double-side polishing apparatus and on apparatus log data of the double-side polishing apparatus in a last stage of polishing corresponding to the shape index;a first step of starting double-side polishing of the semiconductor wafer under initial polishing conditions;subsequent to the first step, a second step of while performing double-side polishing on the semiconductor wafer under the initial polishing conditions, calculating a value of the criterion function using the apparatus log data in the last stage of polishing in the first step, and setting on the double-side ...

INDIUM PHOSPHIDE SUBSTRATE, METHOD OF INSPECTING INDIUM PHOSPHIDE SUBSTRATE, AND METHOD OF PRODUCING INDIUM PHOSPHIDE SUBSTRATE

An indium phosphide substrate, a method of inspecting thereof and a method of producing thereof are provided, by which an epitaxial film grown on the substrate is rendered excellently uniform, thereby allowing improvement in PL characteristics and electrical characteristics of an epitaxial wafer formed using this epitaxial film. The indium phosphide substrate has a first main surface and a second main surface, a surface roughness Ra1 at a center position on the first main surface, and surface roughnesses Ra2, Ra3, Ra4, and Ra5 at four positions arranged equidistantly along an outer edge of the first main surface and located at a distance of 5 mm inwardly from the outer edge. An average value m1 of the surface roughnesses Ra1, Ra2, Ra3, Ra4, and Ra5 is 0.5 nm or less, and a standard deviation σ1 of the surface roughnesses Ra1, Ra2, Ra3, Ra4, and Ra5 is 0.2 nm or less. 1. An indium phosphide substrate having a first main surface and a second main surface ,the first main surface having a surface roughness Ra1 at a center position and surface roughnesses Ra2, Ra3, Ra4, and Ra5 at four positions, the four positions being arranged equidistantly along an outer edge of the first main surface and located at a distance of 5 mm inwardly from the outer edge,{'b': '1', 'an average value m of the surface roughnesses Ra1, Ra2, Ra3, Ra4, and Ra5 being 0.4 nm or less,'}a standard deviation σ1 of the surface roughnesses Ra1, Ra2, Ra3, Ra4, and Ra5 being 10% or less of the average value m1,the second main surface having a surface roughness Ra6 at a center position and surface roughnesses Ra7, Ra8, Ra9, and Ra10 at four positions, the four positions being arranged equidistantly along an outer edge of the second main surface and located at a distance of 5 mm inwardly from the outer edge,an average value m2 of the surface roughnesses Ra6, Ra7, Ra8, Ra9, and Ra10 being more than 0.4 nm and 3 nm or less, anda standard deviation σ2 of the surface roughnesses Ra6, Ra7, Ra8, Ra9, and Ra10 ...

SEED CRYSTAL FOR SINGLE CRYSTAL 4H-SiC GROWTH AND METHOD FOR PROCESSING THE SAME

A seed crystal for single crystal 4H-SiC growth of the present invention is a disk-shaped seed crystal for single crystal 4H-SiC growth having a diameter of more than 150 mm and having a thickness within a range of more than or equal to 1 mm and less than or equal to 0.03 times of the diameter, in which one surface on which the single crystal 4H-SiC is grown is a mirror surface and an Ra of the other surface is more than 10 nm, and an absolute value of magnitude of waviness in a state where the seed crystal is freely deformed so that an internal stress distribution is reduced is less than or equal to 12 μm. 1. A disk-shaped seed crystal for single crystal 4H-SiC growth having a diameter of more than 150 mm and having a thickness within a range of more than or equal to 1 mm and less than or equal to 0.03 times of the diameter ,wherein one surface on which the single crystal 4H-SiC is grown is a mirror surface and an Ra of the other surface is more than 10 nm, andwherein an absolute value of magnitude of waviness, in a state where the seed crystal is freely deformed so that an internal stress distribution is reduced, is less than or equal to 12 μm.2. The seed crystal for single crystal 4H-SiC growth according to claim 1 ,wherein the absolute value of the magnitude of the waviness is less than or equal to 8 μm.3. The seed crystal for single crystal 4H-SiC growth according to claim 1 ,wherein the one surface on which the single crystal 4H-SiC is grown is a carbon surface.4. A method for processing a disk-shaped seed crystal for single crystal 4H-SiC growth having a diameter of more than 150 mm and having a thickness within a range of more than or equal to 1 mm and less than or equal to 0.03 times of the diameter claim 1 , the method comprising:a first step of cutting out a disk-shaped crystal from a columnar single crystal 4H-SiC ingot having a diameter of more than 150 mm;a second step of fixing the crystal to a base material to grind one surface on which the single ...

APPARATUS FOR CLEANING SEMICONDUCTOR SILICON WAFER AND METHOD FOR CLEANING SEMICONDUCTOR SILICON WAFER

A method for cleaning a semiconductor silicon wafer including: an ozone water treatment step after polishing in ozone water, a step of performing a first ultrasonic-wave-ozone-water treatment of cleaning at room temperature while immersing in ozone water and applying ultrasonic waves; and a step of performing a second ultrasonic-wave-ozone-water treatment of, after the step of performing the first ultrasonic-wave-ozone-water treatment, pulling out the semiconductor silicon wafer from the ozone water, performing rotation process, and cleaning at room temperature while immersing in ozone water and applying ultrasonic waves; wherein the step of performing the second ultrasonic-wave-ozone-water treatment is performed, and a hydrofluoric acid treatment step and an ozone water treatment step are performed. Accordingly, a method for cleaning a semiconductor silicon wafer and an apparatus for cleaning by which projecting defects on the wafer surface and the degradation of surface roughness can be suppressed to improve wafer quality reduce costs. 19-. (canceled)10. A method for cleaning a semiconductor silicon wafer for cleaning a semiconductor silicon wafer after polishing , the method comprising:an ozone water treatment step after polishing, of immersing, in ozone water, the semiconductor silicon wafer after polishing;a step of performing a first ultrasonic-wave-ozone-water treatment of cleaning the semiconductor silicon wafer at room temperature while immersing in ozone water and applying ultrasonic waves; anda step of performing a second ultrasonic-wave-ozone-water treatment of, after the step of performing the first ultrasonic-wave-ozone-water treatment, pulling out the semiconductor silicon wafer from the ozone water, performing a wafer rotation process of rotating, and cleaning the semiconductor silicon wafer after the wafer rotation process again at room temperature while immersing in ozone water and applying ultrasonic waves; whereinthe step of performing the second ...

Method of Growing High Quality, Thick SiC Epitaxial Films by Eliminating Silicon Gas Phase Nucleation and Suppressing Parasitic Deposition

Methods for forming an epilayer on a surface of a substrate are generally provided. For example, a substrate can be positioned within a hot wall CVD chamber (e.g., onto a susceptor within the CVD chamber). At least two source gases can then be introduced into the hot wall CVD chamber such that, upon decomposition, fluorine atoms, carbon atoms, and silicon atoms are present within the CVD chamber. The epilayer comprising SiC can then be grown on the surface of the substrate in the presence of the fluorine atoms. 1. A method of forming an epilayer on a surface of a substrate , the method comprising:positioning a silicon carbide seed substrate within a hot wall chemical vapor deposition (CVD) chamber,introducing one or more source gases into the hot wall CVD chamber to provide fluorine, carbon, and silicon to the hot wall CVD chamber, each of the source gases comprising one or more of fluorine, carbon, and silicon;heating the hot wall CVD chamber to a growth temperature of about 1400° C. to about 2000° C., silicon-fluorine bonds forming at the growth temperature, the silicon-fluorine bond formation inhibiting formation of silicon-silicon bonds in the heated hot wall CVD chamber, the heated hot wall CVD chamber atmosphere including Si—Si vapor in an amount that is less than 5% by volume;growing a homeoepitaxial film on the silicon carbide seed substrate at the growth temperature, the homeoepitaxial film comprising a silicon carbide crystal comprising silicon and carbon in the crystal at a 1:1 stoichiometric ratio.2. The method of claim 1 , wherein one or more of the source gases comprises SiHFwhere x=1 claim 1 , 2 claim 1 , or 3; and y=4−x.3. The method of claim 1 , wherein one or more of the source gases comprises CHFwhere x=0 claim 1 , 1 claim 1 , 2 claim 1 , or 3; and y=4−x.4. The method of claim 1 , wherein one of the source gases is HF.5. The method of claim 1 , wherein one or more of the source gases comprises both fluorine and silicon.6. The method of claim 1 , ...

CHEMICAL MECHANICAL POLISHING COMPOSITION FOR POLISHING A SAPPHIRE SURFACE AND METHODS OF USING SAME

A method of polishing a sapphire substrate is provided, comprising: providing a substrate having an exposed sapphire surface; providing a chemical mechanical polishing slurry, wherein the chemical mechanical polishing slurry comprises, as initial components: colloidal silica abrasive, wherein the colloidal silica abrasive has a negative surface charge; and, wherein the colloidal silica abrasive exhibits a multimodal particle size distribution with a first particle size maximum between 2 and 25 nm; and, a second particle size maximum between 75 and 200 nm; optionally, a biocide; optionally, a nonionic defoaming agent; and, optionally, a pH adjuster. A chemical mechanical polishing composition for polishing an exposed sapphire surface is also provided. 1. A method of polishing a sapphire substrate , comprising:providing a substrate having an exposed sapphire surface; colloidal silica abrasive, wherein the colloidal silica abrasive has a negative surface charge; and, wherein the colloidal silica abrasive exhibits a multimodal particle size distribution with a first particle size maximum between 2 and 25 nm; and, a second particle size maximum between 75 and 200 nm;', 'optionally, a biocide;', 'optionally, a nonionic defoaming agent; and,', 'optionally, a pH adjuster;, 'providing a chemical mechanical polishing slurry having a pH of >8 to 12, wherein the chemical mechanical polishing slurry comprises, as initial componentsproviding a chemical mechanical polishing pad;creating dynamic contact at an interface between the chemical mechanical polishing pad and the substrate; anddispensing the chemical mechanical polishing slurry onto the chemical mechanical polishing pad at or near the interface between the chemical mechanical polishing pad and the substrate;wherein at least some sapphire is removed from the exposed sapphire surface of the substrate and wherein the chemical mechanical polishing slurry exhibits a sapphire removal rate of ≧14,000 Å/hr with a platen speed of ...

BONDED SEMICONDUCTOR DEVICES HAVING PROCESSOR AND STATIC RANDOM-ACCESS MEMORY AND METHODS FOR FORMING THE SAME

Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure including a device layer, a first interconnect layer, and a first bonding layer. The device layer includes a processor and a logic circuit, and the first bonding layer includes a first bonding contact. The semiconductor device also includes a second semiconductor structure including an array of static random-access memory (SRAM) cells, a second interconnect layer, and a second bonding layer including a second bonding contact. The first bonding contact is in contact with the second bonding contact. The processor is electrically connected to the array of SRAM cells through the first interconnect layer, the first bonding contact, the second bonding contact, and the second interconnect layer. The logic circuit is electrically connected to the array of SRAM cells through the first interconnect layer, the first bonding contact, the second bonding contact, and the second interconnect layer.

A MIRROR PLATE FOR A FABRY-PEROT INTERFEROMETER AND A FABRY-PEROT INTERFEROMETER

A method for producing a mirror plate for a Fabry-Perot interferometer includes 1. A method for producing a mirror plate for a Fabry-Perot interferometer , the method comprising:providing a substrate, which comprises silicon,implementing a semi-transparent reflective coating,forming a passivated region in and/or on the substrate etching a plurality of voids in the substrate, and by passivating the surfaces of the voids,forming a first sensor electrode on top of the passivated region, andforming a second sensor electrode supported by the substrate.2. The method of claim 1 , wherein the total surface area of the voids is greater than 5 times the projected area of the passivated region.3. The method of claim 1 , wherein forming the passivated region comprises:forming a plurality of voids in the substrates by etching, andforming insulating material on the surfaces of the voids.4. The method according to claim 1 , wherein forming the passivated region comprises:forming a plurality of voids in the substrate by etching, andoxidizing the surfaces of the voids.5. The method according to claim 1 , wherein forming the passivated region comprises:forming a plurality of voids in the substrate by etching, anddepositing insulating material on the surfaces of the voids.6. The method according to claim 1 , wherein the passivated region comprises passivated porous silicon claim 1 , and forming the passivated region comprises:converting silicon into porous silicon by etching, andpassivating surfaces of the pores of the porous silicon.7. The method according to claim 1 , wherein the inner widths of the voids are smaller than 100 μm in a transverse direction.8. The method according to claim 1 , wherein the widths of the walls between the voids are smaller than 100 μm in a transverse direction.9. The method according to claim 1 , wherein the voids are grooves claim 1 , holes claim 1 , channels and/or pores.10. The method according to claim 1 , wherein the thickness of the passivated ...

Method and device for etching patterns inside objects

Systems and methods for etching complex patterns on an interior surface of a hollow object are disclosed. A method generally includes positioning a laser system within the hollow object with a focal point of the laser focused on the interior surface, and operating the laser system to form the complex pattern on the interior surface. Motion of the laser system and the hollow object is controlled by a motion control system configured to provide rotation and/or translation about a longitudinal axis of one or both of the hollow object and the laser system based on the complex pattern, and change a positional relationship between a reflector and a focusing lens of the laser system to accommodate a change in distance between the reflector and the interior surface of the hollow object.

METHOD FOR THE VAPOUR PHASE ETCHING OF A SEMICONDUCTOR WAFER FOR TRACE METAL ANALYSIS

The surface layer of a semiconductor wafer lying on a rotatable plate within an etching chamber is etched by a process whereby homogeneous etching of the surface is obtained by introducing an etching gas into the etching chamber in such a way that the flow of the etching gas is not directed directly to the wafer but is allowed first to distribute within the etching chamber before coming into contact with the surface of the semiconductor wafer to be etched. 110.-. (canceled)11. A method for etching the surface of a semiconductor wafer lying on a rotatable plate in an etching chamber , the etching chamber comprising a bottom , above which the rotatable plate , is located , a cover which fits to the bottom , at least one opening in the cover or between the lower edge of the cover and the bottom , respectively , and a valve or nozzle located beside the rotatable plate for introducing an etching gas into the etching chamber through a second opening , arranged such that gas flowing into the etching chamber does not flow directly in the direction of the semiconductor wafer , and introducing an etching gas into the chamber.12. The method of claim 11 , wherein an opening of the nozzle or valve is directed either to a top or to a side wall of the etching chamber claim 11 , so that the etching gas is not directed directly to the semiconductor wafer.13. The method of claim 11 , wherein the etching gas comprises a mixture of HF and O.14. The method of claim 11 , wherein the etching gas is introduced into the etching chamber for a time period between 3 and 60 seconds.15. The method of claim 11 , wherein the rotatable plate is cooled or heated.16. The method of claim 11 , wherein the rotatable plate is rotated with a rotation speed of 5 to 15 rpm during the etching process.17. The method of claim 11 , wherein after a surface of the semiconductor wafer is etched claim 11 , a resulting etched surface is dried with N.18. The method of claim 11 , wherein the etching process is ...

Wafer processing method

A wafer formed from an SiC substrate having a first surface and a second surface is divided into individual device chips. A division start point formed by a laser has a depth corresponding to the finished thickness of each device chip along each division line formed on the first surface. The focal point of the laser beam is set inside the SiC substrate at a predetermined depth from the second surface, and the laser beam is applied to the second surface while relatively moving the focal point and the SiC substrate to thereby form a modified layer parallel to the first surface and cracks extending from the modified layer along a c-plane, thus forming a separation start point. An external force is applied to the wafer, thereby separating the wafer into a first wafer having the first surface and a second wafer having the second surface.

Wafer processing method

A wafer processing method of processing a wafer with a plurality of devices disposed in areas demarcated by projected division lines and formed on a face side thereof includes a protective member placing step of placing a protective member for protecting the face side of the wafer on the face side of the wafer which is divided into individual device chips, a resin laying step of laying a die-bonding resin on the reverse sides of the individual device chips by applying a die-bonding liquid resin on the reverse side of the wafer and hardening the applied die-bonding liquid resin, and a separation step of separating the device chips with the die-bonding liquid resin laid on the reverse sides thereof from the wafer.

SYSTEM AND METHOD FOR A TRANSDUCER IN AN EWLB PACKAGE

According to an embodiment, a sensor package includes an electrically insulating substrate including a cavity in the electrically insulating substrate, an ambient sensor, an integrated circuit die embedded in the electrically insulating substrate, and a plurality of conductive interconnect structures coupling the ambient sensor to the integrated circuit die. The ambient sensor is supported by the electrically insulating substrate and arranged adjacent the cavity. 1. A method of forming a sensor package , the method comprising:forming an ambient sensor on a first surface of a dummy patterning structure;arranging the dummy patterning structure on a carrier substrate;arranging an integrated circuit die on the carrier substrate;embedding the dummy patterning structure and the integrated circuit die in electrically insulating material;removing the carrier substrate;exposing a second surface of the dummy patterning structure by thinning the electrically insulating material, the second surface opposite the first surface; andforming a cavity in the electrically insulating material by etching the dummy patterning structure.2. The method of claim 1 , further comprising forming a lid layer covering the cavity in the electrically insulating material claim 1 , the lid layer comprising an opening connected to the cavity.3. The method of claim 1 , wherein forming the ambient sensor comprises forming a gas sensor.4. The method of claim 3 , whereinthe dummy patterning structure comprises a plurality of dummy patterning structures;forming the gas sensor comprises forming a plurality of gas sensors, each gas sensor of the plurality of gas sensors being formed on a first surface of at least one dummy patterning structure of the plurality of dummy patterning structures;arranging the dummy patterning structure on the carrier substrate comprises arranging the plurality of dummy patterning structures on the carrier substrate; andforming the cavity in the electrically insulating material ...

POLISHING PAD AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE SAME

The present disclosure relates to an endpoint detection window of a polishing pad for use in a polishing process. The polishing pad may prevent an error in detection of the endpoint of the polishing process by preventing a difference in endpoint detection performance from occurring due to a difference in the wavelength of a laser between polishing apparatuses. The present disclosure may also provide a method of fabricating a semiconductor device using the polishing pad. 2. The polishing pad of claim 1 , wherein the window has an absorbance change uniformity (ACU) of 2 to 3.5 claim 1 , when x is 400 nm claim 1 , y is 800 nm claim 1 , and z is 600 nm.3. The polishing pad of claim 1 , wherein the window has an absorbance change uniformity (ACU) of 1.5 to 2.5 claim 1 , when x is 600 nm claim 1 , y is 750 nm claim 1 , and z is 675 nm.5. The polishing pad of claim 4 , wherein the absorbance difference calculated according to Equation 2 is 4 to 6.6. The polishing pad of claim 1 , wherein the window comprises a cured product obtained by curing a window composition containing a urethane-based prepolymer claim 1 , and the urethane-based prepolymer has an unreacted NCO content (%) of 8 to 10%.6. The polishing pad of claim 1 , wherein the absorbance of the endpoint detection window is measured by irradiating the window with light having a wavelength of 400 nm to 800 nm claim 1 , and an average of the measured absorbance is 0.61 to 0.80.9. The method of claim 8 , wherein the window has an absorbance change uniformity (ACU) of 2 to 3.5 claim 8 , when x is 400 nm claim 8 , y is 800 nm claim 8 , and z is 600 nm.10. The method of claim 8 , wherein the window has an absorbance change uniformity (ACU) of 1.5 to 2.5 claim 8 , when x is 600 nm claim 8 , y is 750 nm claim 8 , and z is 675 nm.12. The method of claim 8 , wherein the urethane-based prepolymer has an unreacted NCO content (%) of 8 to 10%.13. The method of claim 8 , wherein the absorbance of the endpoint detection window is ...

SUBSTRATE HANDLING SYSTEMS AND METHODS FOR CMP PROCESSING

A system and method for sequential single-sided CMP processing of opposite facing surfaces of a silicon carbide (SiC) substrate are disclosed. A method includes urging a first surface of a substrate against one of plurality of polishing pads, wherein the plurality of polishing pads are disposed on corresponding ones of a plurality of rotatable polishing platens. The method includes transferring, using the first side of the end effector, the substrate from the substrate carrier loading station to a substrate alignment station. The method includes transferring, using the first side of the end effector, the substrate from the substrate alignment station to a substrate carrier loading station. The method includes urging a second surface of the substrate against one of the plurality of polishing platens. 1. A substrate polishing system , comprising:a substrate alignment station;a plurality of polishing stations, each comprising a rotatable polishing platen;a substrate carrier loading station;a substrate handler comprising an end effector having a first side and a second side that is opposite of the first side; and (a) urging a first surface of a substrate against one of a plurality of polishing pads, wherein the plurality of polishing pads are disposed on corresponding ones of the plurality of rotatable polishing platens;', '(b) transferring, using the first side of the end effector, the substrate from the substrate carrier loading station to the substrate alignment station;', '(c) transferring, using the first side of the end effector, the substrate from the substrate alignment station to the substrate carrier loading station; and', '(d) urging a second surface of the substrate against one of the plurality of polishing pads., 'a computer readable medium having instructions stored thereon for a substrate processing method, the method comprising sequentially2. The system of claim 1 , wherein the substrate handler further comprises an arm movable along an overhead track ...

Method of Controlled Crack Propagation for Material Cleavage using Electromagnetic Forces

To address the needs in the art, a method of cleaving substrate material that includes forming an initial crack in a bulk substrate material, where the crack is aligned along a cleaving plane of the bulk substrate material, aligning the cleaving plane between two parallel electrodes in a controlled environment, wherein the parallel electrodes include a top electrode and a bottom electrode, where the cleaving plane is parallel with the two parallel electrodes, where a bottom portion of the bulk substrate material is physically and electrically connected to the bottom electrode, and applying a voltage across the two parallel electrodes, where the voltage is at least 50 kV and establishes a uniform electromagnetic force on the top surface of the bulk substrate material, where the electromagnetic force is capable of inducing crack propagation along the cleaving plane and separating a cleaved substrate material from the bulk substrate material. 1. A method of cleaving substrate material , comprising:a. forming an initial crack in a bulk substrate material, wherein said crack is aligned along a cleaving plane of said bulk substrate material;b. aligning said cleaving plane between two parallel electrodes in a controlled environment, wherein said parallel electrodes comprise a top electrode and a bottom electrode, wherein said cleaving plane is parallel with said two parallel electrodes, wherein a bottom portion of said bulk substrate material is physically and electrically connected to said bottom electrode; andc. applying a voltage across said two parallel electrodes, wherein said voltage is at least 50 kV, wherein said voltage establishes a uniform electromagnetic force on said top surface of said bulk substrate material, wherein said electromagnetic force is capable of inducing crack propagation along said cleaving plane and separating a cleaved substrate material from said bulk substrate material.2. The method according to claim 1 , wherein forming said initial crack ...

WAFER SURFACE TEST PREPROCESSING DEVICE AND WAFER SURFACE TEST APPARATUS HAVING THE SAME

A wafer surface test preprocessing device includes a chamber; a supporting component disposed in the chamber; an atomizer connected to a lateral side of the chamber; a cooling component connected to a bottom of the chamber; and a lid disposed on a top of the chamber. With the wafer surface test preprocessing device having the cooling component to thereby dispense with a ventilation device and collect hydrofluoric acid residues in the chamber at the bottom of the chamber, thereby saving costs and time effectively. 1. A wafer surface test preprocessing device , comprising:a chamber;a supporting component disposed in the chamber;an atomizer connected to a lateral side of the chamber;a cooling component connected to a bottom of the chamber; anda lid disposed on a top of the chamber.2. The wafer surface test preprocessing device of claim 1 , wherein the cooling component is a hydrocooling chamber.3. The wafer surface test preprocessing device of claim 1 , wherein the supporting component comprises a plurality of supporting posts.4. The wafer surface test preprocessing device of claim 1 , wherein the wafer surface test preprocessing device is made of PFA composite plastic.5. A wafer surface test apparatus claim 1 , comprising:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'the wafer surface test preprocessing device of ; and'}a test device for testing a wafer processed with the wafer surface test preprocessing device.6. A wafer surface test apparatus claim 1 , comprising:{'claim-ref': {'@idref': 'CLM-00002', 'claim 2'}, 'the wafer surface test preprocessing device of ; and'}a test device for testing a wafer processed with the wafer surface test preprocessing device.7. A wafer surface test apparatus claim 1 , comprising:{'claim-ref': {'@idref': 'CLM-00003', 'claim 3'}, 'the wafer surface test preprocessing device of ; and'}a test device for testing a wafer processed with the wafer surface test preprocessing device.8. A wafer surface test apparatus claim 1 , comprising ...

Substrate recycling method and recycled substrate

Exemplary embodiments of the present invention provide a substrate recycling method and a recycled substrate. The method includes separating a substrate having a first surface from an epitaxial layer, performing a first etching of the first surface using electrochemical etching, and performing, after the first etching, a second etching of the first surface using chemical etching, dry etching, or performing, after the first etching, chemical mechanical polishing of the first surface.

SEQUENTIAL ETCHING TREATMENT FOR SOLAR CELL FABRICATION

A method of processing a silicon substrate can include etching the silicon substrate with a first etchant having a first concentration and etching with a second etchant having a second concentration. In an embodiment, the second concentration of the second etchant can be greater than the first concentration of the first etchant. In one embodiment, the first etchant can be a different type of etchant than the second etchant. In an embodiment, the first and second etchant can be the same type of etchant. In some embodiments the silicon substrate can be cleaned with a first cleaning solution to remove contaminants from the silicon substrate prior to etching with the first etchant. In an embodiment, the silicon substrate can be cleaned with a second cleaning solution after etching the silicon substrate with a second etchant. 1. A method of processing a silicon substrate , the method comprising:etching the silicon substrate with a first etchant having a first concentration; andetching the silicon substrate with a second etchant having a second concentration higher than the first concentration.2. The method of claim 1 , wherein the second etchant is a same type of etchant as the first etchant.3. The method of claim 1 , wherein etching the silicon substrate with the first or second etchant comprises etching the silicon substrate with potassium hydroxide (KOH) claim 1 , sodium hydroxide (NaOH) claim 1 , tetramethylammonium hydroxide (TMAH) claim 1 , hydrofluoric acid (HF) and nitric acid (HNO) claim 1 , hydrofluoric acid (HF) with nitric acid (HNO) and deionized (DI) water claim 1 , hydrofluoric acid (HF) with nitric acid (HNO) claim 1 , acetic acid (CHO) and deionized (DI) water or ammonium hydroxide (NHOH).4. The method of claim 1 , wherein etching the silicon substrate with the first etchant having the first concentration comprises etching the silicon substrate with potassium hydroxide (KOH) having a concentration in the range of approximately 15-30%.5. The method of ...

ABRASIVE GRAINS, EVALUATION METHOD THEREFOR, AND WAFER MANUFACTURING METHOD

Provided are abrasive grains, an evaluation method and a wafer manufacturing method. A predetermined amount of abrasive grains is prepared as an abrasive grain sample group, the grain diameter of individual abrasive grains in the abrasive grain sample group is measured, the number of abrasive grains in the abrasive grain sample group as a whole is counted, abrasive grains having a grain diameter equal to or smaller than a predetermined reference grain e diameter criterion which is smaller than the average grain diameter of the abrasive grain sample are defined as small grains and the number of the small grains is counted, a small grain ratio is calculated as the number ratio of the small grains occupied in the abrasive grain sample group as a whole, and a determination is made as to whether or not the small grain ratio is equal to or smaller than a predetermined threshold value. 1. An abrasive grain evaluation method comprising:preparing a predetermined amount of abrasive grains as an abrasive grain sample group;measuring the grain diameters of individual abrasive grains in the abrasive grain sample group and counting the number of the abrasive grains in the abrasive grain sample group;defining abrasive grains having a grain diameter equal to or smaller than a predetermined diameter criterion which is smaller than the average grain diameter of the abrasive grain sample group as small grains and counting the number of the small grains;calculating a small grain ratio which is the number ratio of the small grains occupied in the abrasive grain sample group; anddetermining whether or not the small grain ratio is equal to or smaller than a predetermined threshold value.2. The abrasive grain evaluation method as claimed in includes:measuring the grain size distribution based on the volume of the abrasive grain sample group from the grain diameters of the individual abrasive grains in the abrasive grain sample group;calculating the average grain diameter of the abrasive ...

WAFER FLATNESS CONTROL USING BACKSIDE COMPENSATION STRUCTURE

Embodiments of semiconductor structures for wafer flatness control and methods for using and forming the same are disclosed. In an example, a model indicative of a flatness difference of a wafer between a first direction and a second direction is obtained. The flatness difference is associated with one of a plurality of fabrication stages of a plurality of semiconductor devices on a front side of the wafer. A compensation pattern is determined for reducing the flatness difference based on the model. At the one of the plurality of the fabrication stages, a compensation structure is formed on a backside opposite to the front side of the wafer based on the compensation pattern to reduce the flatness difference. 1. A method for controlling wafer flatness , comprising:obtaining a model indicative of a flatness difference of a wafer between a first direction and a second direction, the flatness difference being associated with one of a plurality of fabrication stages of a plurality of semiconductor devices on a front side of the wafer;determining a compensation pattern for reducing the flatness difference based on the model; andat the one of the plurality of the fabrication stages, forming a compensation structure on a backside opposite to the front side of the wafer based on the compensation pattern to reduce the flatness difference.2. The method of claim 1 , wherein the flatness difference comprises a difference of wafer bow.3. The method of claim 1 , wherein the first direction is perpendicular to the second direction.4. The method of claim 1 , wherein the plurality of semiconductor devices comprise a plurality of three-dimensional (3D) memory devices.5. The method of claim 4 , whereineach of the 3D memory devices comprises a plurality of slit structures nominally parallel to one another; andthe first direction is the same as a direction in which the slit structures extend.6. The method of claim 5 , wherein the compensation structure comprises a plurality of strips ...

METHOD AND APPARATUS TO TREAT SEMICONDUCTOR SUBSTRATE

A method of treating a semiconductor substrate includes converting a first main side of the semiconductor substrate having a first coefficient of static friction relative to a surface of a wafer table to a second coefficient of static friction relative to the surface of the wafer table, wherein the second coefficient of static friction is less than the first coefficient of static friction. A photoresist layer is applied over a second main side of the semiconductor substrate having the first coefficient of static friction. The second main side opposes the first main side. The semiconductor substrate is placed on the wafer table so that the first main side of the semiconductor substrate faces the wafer table. 1. A method of treating a semiconductor substrate , comprising:converting a first main side of the semiconductor substrate having a first coefficient of static friction relative to a surface of a wafer table to a second coefficient of static friction relative to the surface of the wafer table,wherein the second coefficient of static friction is less than the first coefficient of static friction;applying a photoresist layer over a second main side of the semiconductor substrate having the first coefficient of static friction,wherein the second main side opposes the first main side; andplacing the semiconductor substrate on the wafer table so that the first main side of the semiconductor substrate faces the wafer table.2. The method according to claim 1 , wherein the converting a first main side of the semiconductor substrate comprises applying a friction-reducing material to the first main side of the semiconductor substrate.3. The method according to claim 2 , wherein the friction-reducing material is hexamethyldisilazane (HMDS) or tetramethyl ammonium hydroxide (TMAH).4. The method according to claim 2 , wherein the friction-reducing material is applied in a deposition chamber configured to allow only the first main side of the semiconductor substrate to be ...

METHOD FOR POLISHING SILICON SUBSTRATE AND POLISHING COMPOSITION SET

Provided are a polishing method that can be commonly applied to different types of silicon substrates varying in resistivity as well as a polishing composition set used in the polishing method. The silicon substrate polishing method provided by this invention comprises supplying a first polishing slurry Sand a second polishing slurry Sto a silicon substrate to be polished, switching them in this order midway through polishing the silicon substrate. The first polishing slurry Scomprises an abrasive Aand a water-soluble polymer P. The polishing removal rate of the first polishing slurry Sis higher than that of the second polishing slurry S. 1. A method for polishing a silicon substrate , the method comprising{'sub': 1', '2, 'supplying a first polishing slurry Sand a second polishing slurry Sto a silicon substrate to be polished, switching them in this order midway through polishing the silicon substrate,'}{'sub': 1', '1', '1, 'the first polishing slurry Scomprises an abrasive Aand a water-soluble polymer P, and'}{'sub': 1', '2, 'the first polishing slurry Sshows higher polishing removal rate than the second polishing slurry S.'}2. The polishing method according to claim 1 , wherein the first polishing slurry Scomprises at least 0.001% water-soluble polymer Pby weight.3. The polishing method according to claim 1 , wherein the water-soluble polymer Pcomprises a vinyl alcohol-based polymer chain.4. The polishing method according to claim 1 , wherein the water-soluble polymer Pcomprises an N-vinyl-based polymer chain.5. The polishing method according to claim 1 , wherein the first polishing slurry Scomprises an alkali metal hydroxide as a basic compound B.6. The polishing method according to claim 1 , wherein the abrasive Ahas a BET diameter smaller than 60 nm.7. The polishing method according to claim 1 , wherein the second polishing slurry Scomprises an abrasive Aand a water-soluble polymer P claim 1 , and the concentration of the water-soluble polymer Pin the second ...

ETCHING COMPOSITIONS

The present disclosure is directed to etching compositions that are useful for, e.g., selectively removing silicon germanium (SiGe) from a semiconductor substrate as an intermediate step in a multistep semiconductor manufacturing process. 1. An etching composition , comprising:at least one fluorine-containing acid, the at least one fluorine-containing acid comprising hydrofluoric acid or hexafluorosilicic acid;at least one oxidizing agent;at least one catalyst comprising sulfuric acid, a sulfonic acid, or a phosphonic acid;at least one organic acid or an anhydride thereof, the at least one organic acid comprising formic acid, acetic acid, propionic acid, or butyric acid;at least one polymerized naphthalene sulfonic acid or a salt thereof; and{'sub': 1', '2', '3', '1', '1', '8', '2', '2', '1', '8', '3', '1', '8, 'at least one amine, the at least one amine comprising an amine of formula (I): N—RRR, wherein Ris C-Calkyl optionally substituted by OH or NH, Ris H or C-Calkyl optionally substituted by OH, and Ris C-Calkyl optionally substituted by OH.'}2. The composition of claim 1 , wherein the at least one fluorine-containing acid is in an amount of from about 0.01 wt % to about 2 wt % of the composition.3. The composition of claim 1 , wherein the at least one oxidizing agent comprises hydrogen peroxide or peracetic acid.4. The composition of claim 1 , wherein the at least one oxidizing agent is in an amount of from about 5 wt % to about 20 wt % of the composition.5. The composition of claim 1 , wherein the at least one catalyst comprises sulfuric acid claim 1 , methanesulfonic acid claim 1 , phosphonic acid claim 1 , or phenylphosphonic acid.6. The composition of claim 1 , wherein the at least one catalyst is in an amount of from about 0.1 wt % to about 5 wt % of the composition.7. The composition of claim 1 , wherein the at least one organic acid or an anhydride thereof comprises acetic acid or acetic anhydride.8. The composition of claim 1 , wherein the at least one ...

SEMICONDUCTOR SUBSTRATE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR SUBSTRATE

A semiconductor substrate includes a surface having a groove. The groove includes an inner bottom surface and an inner wall surface. The inner wall surface has a depression. The depression has a depth from a direction along a surface of the inner wall surface to a width direction of the groove. The substrate being exposed to the inner wall surface. 1. A semiconductor substrate , comprisinga surface having a groove, the groove including an inner bottom surface and an inner wall surface, the inner wall surface having a depression, the depression having a depth from a direction along a surface of the inner wall surface to a width direction of the groove, andthe substrate being exposed to the inner wall surface.2. The substrate according to claim 1 , wherein:the inner wall surface has a plurality of the depressions; andthe depressions are spaced along a depth direction of the groove or along an inner periphery of the groove.3. The substrate according to claim 1 , further comprisinga semiconductor layer partly provided on the surface and extending along the inner wall surface.4. The substrate according to claim 1 , further comprisinga second surface provided on an opposite side of the surface and having a second groove, the second groove including a second inner wall surface.5. The substrate according to claim 1 , whereinthe substrate is a silicon wafer, a silicon carbide wafer, a glass wafer, a quartz wafer, a sapphire wafer, or a compound semiconductor wafer.6. A method of manufacturing a semiconductor device claim 1 , comprising:placing a first semiconductor substrate into a chamber, the first semiconductor substrate including a first surface and a film provided on the first surface, the film having a first groove;{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'placing a second semiconductor substrate into the chamber, the second semiconductor substrate being the substrate according to ; and'}processing the first and second semiconductor substrates in the chamber.7 ...

Method for manufacturing semiconductor chip and circuit board and electronic apparatus including semiconductor chip

A method for manufacturing a semiconductor chip includes forming at least a portion of a front-side groove by anisotropic dry etching from a front surface of a substrate along a cutting region; forming a modified region in the substrate along the cutting region by irradiating the inside of the substrate with a laser along the cutting region; and dividing the substrate along the cutting region by applying stress to the substrate.

WAFER STACKING TO FORM A MULTI-WAFER-BONDED STRUCTURE

In one aspect, a method includes heating a wafer chuck, heating a first wafer, depositing a first epoxy along at least a portion of a surface of the first wafer disposed on the wafer chuck, spinning the wafer chuck to spread the first epoxy at least partially across the first wafer, placing a second wafer on the first epoxy disposed on the first wafer and bonding the second wafer to the first epoxy under vacuum to form a two-wafer-bonded structure. 115-. (canceled)16. A multi-wafer-bonded stack , comprising:a first wafer having a first surface; anda second wafer having a first surface bonded to the first surface of the first wafer by a first epoxy, wherein the first epoxy covers an entirety of the first surface of the first wafer and an entirety of the first surface of the second wafer,wherein the first epoxy is free of voids.17. The multi-wafer-bonded stack of claim 16 , further comprising a third wafer bonded to the first wafer by a second epoxy claim 16 ,wherein the second epoxy is free of voids.18. The multi-wafer-bonded stack of claim 17 , wherein the first wafer is one of a controlled expansion (CE) wafer claim 17 , a stainless steel wafer or a titanium wafer claim 17 , andwherein the second wafer is a readout integrated circuit (ROIC) wafer.19. The multi-wafer-bonded stack of claim 18 , wherein the third wafer is silicon.20. The multi-wafer-bonded stack of claim 18 , wherein the ROIC wafer comprises indium bumps.21. The multi-wafer-bonded stack of claim 17 , wherein the first epoxy and the second epoxy can withstand cryogenic temperatures of −150° C. or less.22. A multi-wafer-bonded stack claim 17 , comprising:a first wafer having a first surface and a second surface, wherein the first wafer is one of a controlled expansion (CE) wafer, a stainless steel wafer or a titanium wafer;a second wafer having a first surface bonded to the first surface of the first wafer by a first epoxy, wherein the second wafer is a readout integrated circuit (ROIC) wafer; anda ...

CVD REACTOR AND METHOD FOR NANOMETRIC DELTA DOPING OF DIAMOND

An apparatus and method for creating nanometric delta doped layers in epitaxial diamond includes providing a dummy gas load with gas impedance equivalent to the reactor, and switching gas supplied between the reactor and the gas dummy load without stopping either flow, thereby enabling rapid flow and rapid gas switching without turbulence. An atomically smooth, undamaged substrate can be prepared, preferably in the (100) plane, by etching the surface after polishing to remove subsurface damage. A gas phase chemical getter reactant such as hydrogen disulfide can be used to suppress incorporation of residual boron into the intrinsic layers. Embodiments can produce interfaces between doped and mobile layers that provide at least 100 cm/Vsec carrier mobility and 10cmsheet carrier concentration. 1. An epitaxial CVD reactor for growing delta-doped layers on diamond substrates , the reactor comprising:a reaction chamber configured to enable a flow of gas from an inlet thereof through an interior thereof;a substrate support located within the reaction chamber and configured for supporting a diamond substrate on a surface thereof;a plasma generator configured to excite the gas so as to surround the substrate with a gas plasma;a first gas source;a second gas source;a dummy gas load configured to allow gas from one of the gas sources to flow therethrough, the dummy gas load being configured to present a dummy gas flow impedance to a gas source that is equivalent to a reactor gas flow impedance of the reaction chamber;a gas manifold configured to direct a flow from one of the gas sources to the reaction chamber while directing a flow from the other of the gas sources to the dummy gas load;a gas switch configured to switch the gas flows between the reaction chamber and the dummy gas load, while maintaining both gas flows; anda switch controller configured to control switching by the gas switch of the gas flows.2. The reactor of claim 1 , wherein the reaction chamber is a fused ...

Carrier Substrate For Semiconductor Structures Suitable For A Transfer By Transfer Print And Manufacturing Of The Semiconductor Structures On The Carrier Substrate

A carrier substrate for semiconductor structures which can be transferred by transfer printing, and manufacture of the semiconductor structures on the carrier substrate. The number of the required process steps and thus the required effort is to be generally reduced in the manufacture of component structures on a carrier substrate for providing the component structures in a state in which they can be transferred to a further substrate by transfer printing. For this purpose, it is suggested to produce semiconductor structures to be transferred on a carrier substrate. The method comprises providing a carrier substrate () including a semiconductor material with a selected crystal orientation. An active region () is produced which has an exposed semiconductor surface () and is almost completely delimited by dielectric regions () including an isolating dielectric material. Forming a semiconductor structure () to be transferred by depositing at least one semiconductor layer on the active region () is provided. Removal of at least a part or portion of the dielectric material is performed as well as an etching and removal of semiconductor material beneath the semiconductor structure (). 1. A method for producing semiconductor structures to be transferred on a carrier substrate , the method comprising:{'b': '10', 'providing a carrier substrate () including a semiconductor material with a selected crystal orientation;'}{'b': 11', '11', '30', '80, 'producing an active region () which has an exposed semiconductor surface () and is almost completely delimited by dielectric regions (, ) including an isolating dielectric material;'}{'b': 40', '11, 'forming a semiconductor structure () to be transferred by depositing at least one semiconductor layer on the active region ();'}removing at least a portion of the dielectric material;{'b': 60', '70', '110', '120', '40, 'performing an etching (, , , ) for removing semiconductor material beneath the semiconductor structure () to be ...

METHOD FOR MANUFACTURING THIN SiC WAFER AND THIN SiC WAFER

Provided is a method for manufacturing a thin SiC wafer by which a SiC wafer is thinned using a method without generating crack or the like, the method in which polishing after adjusting the thickness of the SiC wafer can be omitted. The method for manufacturing the thin SiC wafer 40 includes a thinning step. In the thinning step, the thickness of the SiC wafer 40 can be decreased to 100 μm or less by performing the Si vapor pressure etching in which the surface of the SiC wafer 40 is etched by heating the SiC wafer 40 after cutting out of an ingot 4 under Si vapor pressure.

METHOD OF CLEANING AND MICRO-ETCHING SEMICONDUCTOR WAFERS

A method of simultaneously cleaning inorganic and organic contaminants from semiconductor wafers and micro-etching the semiconductor wafers. After the semiconductor wafers are cut or sliced from ingots, they are contaminated with cutting fluid as well as metal and metal oxides from the saws used in the cutting process. Aqueous alkaline cleaning and micro-etching solutions containing alkaline compounds and mid-range alkoxylates are used to simultaneously clean and micro-etch the semiconductor wafers. 17-. (canceled)8. A composition comprising one or more quaternary ammonium hydroxides , one or more alkali metal hydroxides and one or more mid-range alkoxylates in sufficient amounts to remove inorganic and organic contaminants from a semiconductor wafer and micro-etch the wafer. This Application is a Divisional of U.S. Non-Provisional Application No. 12/904,609, filed Oct. 14, 2010, which application claims the benefit of priority under 35 U.S.C. §119(e) to U.S. Provisional Application No. 61/278,942, filed Oct. 14, 2009, the entire contents of which application are incorporated herein by reference.The present invention is directed to a method of simultaneously cleaning semiconductor wafers of inorganic and organic contaminants and micro-etching the semiconductor wafers. More specifically, the present invention is directed to a method of simultaneously cleaning semiconductor wafers of inorganic and organic contaminants and micro-etching the semiconductor wafers with an aqueous alkaline solution containing alkaline compounds and mid-range alkoxylates.Conventionally, semiconductor wafers may be fabricated by the following steps:(1) a semiconductor ingot is sliced by an inner diameter saw to obtain a wafer;(2) the wafer is washed with water to remove contaminants; and(3) the wafer is then cleaned to remove contaminants including heavy metals and particles and then dried.Such wafers are typically used in the manufacture of photovoltaic devices, such as solar cells. A solar ...

WAFER PROCESSING METHOD

A wafer is divided into device chips each of which is surrounded by a mold resin. The wafer has a plurality of devices arranged like a matrix with a spacing having a predetermined width, the front side of each device being covered with the mold resin, the spacing being filled with the mold resin to form a street between any adjacent ones of the devices. The wafer processing method includes a division start point forming step of forming a division start point along each street at the lateral center of the mold resin filling the spacing and a dividing step of applying an external force to the wafer after performing the division start point forming step, thereby laterally dividing each street into two parts at the division start point to obtain the device chips divided from each other, each device chip being surrounded by the mold resin. 1. A wafer processing method for dividing a wafer into device chips each of which is surrounded by a mold resin , said wafer having a plurality of devices arranged like a matrix with a spacing having a predetermined width , the front side of each device being covered with said mold resin , said spacing being filled with said mold resin to form a street between any adjacent ones of said devices , said wafer processing method comprising:a division start point forming step of forming a division start point along each street at the lateral center of said mold resin filling said spacing; anda dividing step of applying an external force to said wafer after performing said division start point forming step, thereby laterally dividing each street into two parts at said division start point to obtain said device chips divided from each other, each device chip being surrounded by said mold resin.2. The wafer processing method according to claim 1 , wherein said wafer is manufactured by a method including:an original wafer preparing step of preparing an original wafer having a front side on which a plurality of crossing division lines are formed ...