LITHOGRAPHY PATTERNING METHOD

A method for fabricating an integrated circuit device is disclosed. The method is a lithography patterning method that can include providing a substrate; forming a protective layer over the substrate; forming a conductive layer over the protective layer; forming a resist layer over the conductive layer; and exposing and developing the resist layer.

Wafer assembly with carrier wafer

A wafer assembly includes a process wafer and a carrier wafer. Integrated circuits are formed on the process wafer. The carrier wafer is bonded to the process wafer. The carrier wafer has at least one alignment mark.

Hybrid focus-exposure matrix

A method for controlling semiconductor production through use of a hybrid Focus Exposure Matrix (FEM) model includes taking measurements of a set of structures formed onto a substrate. The method further includes using a FEM model to determine focus and exposure conditions used to form the structure The model was created through use of measurements of structures formed on a substrate under varying focus and exposure conditions, the measurements being taken using both an optical measurement tool and a scanning electron microscope.

SYSTEM AND METHOD FOR SUPPLYING AND DISPENSING BUBBLE-FREE PHOTOLITHOGRAPHY CHEMICAL SOLUTIONS

A photolithography system includes a variable-volume buffer tank, a dispensing system connected to the buffer tank, and a valve configured to release gas from a head space of the buffer tank while blocking the release of liquid from the head space. A storage container has an opening at the bottom and drains to the buffer tank through that opening. The buffer tank has a storage capacity sufficient to receive the full contents of the storage container. The system supplies chemical solutions to the dispensing system while keeping the chemical solutions from contact with air and other gases. 1. A photolithography system , comprising:a variable-volume tank;a dispensing system connected to the variable-volume tank and configured to dispense a photolithography chemical solution from the variable-volume tank onto one or more wafers; anda valve configured to release gas from a head space of the variable-volume tank; andwherein the variable-volume tank includes a photolithography chemical solution inlet and a photolithography chemical solution outlet which is separate from the photolithography chemical solution inlet.2. The photolithography system of claim 1 , wherein the variable-volume tank comprises a collapsible liner within a rigid shell.3. The photolithography system of claim 2 , wherein collapsible liner comprises a body portion and a head portion claim 2 , and the rigid shell surrounds the body portion of the collapsible liner but not the head portion of the collapsible liner.4. The photolithography system of claim 3 , wherein the photolithography chemical solution inlet and the photolithography chemical solution outlet adjoin the head portion of the collapsible liner.5. The photolithography system of claim 2 , further comprising:a pressure gauge configured to measure a pressure in the variable-volume tank; anda controller configured to regulate the pressure by adding or removing fluid with regard to space between the collapsible liner and the rigid shell using a pump ...

METHOD AND STRUCTURE OF STACKING SCATTEROMETRY-BASED OVERLAY OR CD MARKS FOR MARK FOOTPRINT REDUCTION

The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; a plurality of material layers formed on the semiconductor substrate, each of the material layers including a circuit pattern therein; and a plurality of diffraction-based periodic marks formed in the plurality of material layers and stacked in a same region. One of the diffraction-based periodic marks is different from at least one other of the diffraction-based periodic marks in pitch.

In-Situ Immersion Hood Cleaning

An apparatus includes a wafer stage configured to secure a wafer; and a cleaning module including a tank adjacent to the wafer stage, and is positioned outside the region occupied by the wafer. The cleaning module is configured to receive de-ionized (DI) water into the tank and extract the DI water out of the tank. The tank is configured to hold DI water with a top surface of the DI water substantially level with a top surface of the wafer.

Dual wavelength exposure method and system for semiconductor device manufacturing

A dual wavelength exposure system provides for patterning a resist layer formed on a wafer for forming semiconductor devices, using two exposure operations, one including a first radiation having a first wavelength and the other including a second radiation including a second wavelength. Different or the same lithography tool may be used to generate the first and second radiation. For each die formed on the semiconductor device, a critical portion of the pattern is exposed using a first exposure operation that uses a first radiation with a first wavelength and a non-critical portion of the pattern is exposed using a second exposure operation utilizing the second radiation at a second wavelength. The resist material is chosen to be sensitive to both the first radiation having a first wavelength and the second radiation having the second wavelength.

Litho cluster and modulization to enhance productivity

The present disclosure relates to a lithographic tool arrangement for semiconductor workpiece processing. The lithographic tool arrangement groups lithographic tools into clusters, and selectively transfers a semiconductor workpiece between a plurality of lithographic tools of a first type in a first cluster to a plurality of lithographic tools of a second type in a second cluster. The selective transfer is achieved though a transfer assembly, which is coupled to a defect scan tool that identifies defects generated in the lithographic tool of the first type. The disclosed lithographic tool arrangement also utilizes shared structural elements such as a housing assembly, and shared functional elements such as gases and chemicals. The lithographic tool arrangement may consist of baking, coating, exposure, and development units configured to provide a modularization of these various components in order to optimize throughput and efficiency for a given lithographic fabrication process.

SYSTEM AND METHOD FOR SUPPLYING AND DISPENSING BUBBLE-FREE PHOTOLITHOGRAPHY CHEMICAL SOLUTIONS

A method of supplying a chemical solution to a photolithography system. The chemical solution is pumped from a variable-volume buffer tank. The pumped chemical solution is dispensed in a spin-coater. The variable-volume buffer tank is refilled by emptying a storage container filled with the chemical solution into the variable-volume buffer tank.

METHOD AND APPARATUS FOR REDUCING DOWN TIME OF A LITHOGRAPHY SYSTEM

An apparatus includes a radiation source that emits a radiation beam that causes substantially all of a quantity of material to evaporate; and structure having first and second surface portions, a first operational mode wherein a greater quantity of a byproduct of the evaporation impinges on the first surface portion, and a second operational mode wherein a greater quantity of the byproduct impinges on the second surface portion. A different aspect involves emitting a radiation beam toward a quantity of material, the radiation beam causing substantially all of the quantity of material to evaporate; operating a structure having first and second surface portions in a first operational mode wherein a greater quantity of a byproduct of the evaporation impinges on the first surface portion; and thereafter operating the structure in a second operational mode wherein a greater quantity of the byproduct impinges on the second surface portion.

Method and apparatus for reducing down time of a lithography system

An apparatus includes a radiation source that emits a radiation beam that causes substantially all of a quantity of material to evaporate; and structure having first and second surface portions, a first operational mode wherein a greater quantity of a byproduct of the evaporation impinges on the first surface portion, and a second operational mode wherein a greater quantity of the byproduct impinges on the second surface portion. A different aspect involves emitting a radiation beam toward a quantity of material, the radiation beam causing substantially all of the quantity of material to evaporate; operating a structure having first and second surface portions in a first operational mode wherein a greater quantity of a byproduct of the evaporation impinges on the first surface portion; and thereafter operating the structure in a second operational mode wherein a greater quantity of the byproduct impinges on the second surface portion.

Adaptive baking method

A method includes supporting a wafer on a heating element, wherein the heating element is located in a baking chamber. The method further includes heating the wafer for a first duration using the heating element. The method further includes measuring a temperature of the heating element and a temperature of the wafer during the first duration to obtain temperature information. The method further includes adjusting an amount of heat provided by the heating element during the first duration, wherein the adjusting of the amount of heat includes decreasing the amount of heat provided by the heating element as a rate of change of the temperature information versus time increases.

Two-dimensional marks

A method for controlling semiconductor production through use of a Focus Exposure Matrix (FEM) model includes taking measurements of characteristics of a two-dimensional mark formed onto a substrate, the two-dimensional mark including two different patterns along two different cut-lines, and comparing the measurements with a FEM model to determine focus and exposure conditions used to form the two-dimensional mark. The FEM model was created using measurements taken of corresponding two-dimensional marks formed onto a substrate under varying focus and exposure conditions.

Method of inhibiting photoresist pattern collapse

A method of inhibiting photoresist pattern collapse which includes the steps of providing a substrate; providing a photoresist layer on the substrate; exposing and developing the photoresist layer; applying a top anti-reflective coating layer to the photoresist layer; rinsing the photoresist layer; and drying the photoresist layer.

Semiconductor processing apparatus with simultaneously movable stages

A method and apparatus provide for simultaneously moving multiple semiconductor wafers in opposite directions while simultaneously performing processing operations on each of the wafers. The semiconductor wafers are orientated in coplanar fashion and are disposed on stages that simultaneously translate in opposite directions to produce a net system momentum of zero. The die of the respective semiconductor wafers are processed in the same spatial sequence with respect to a global alignment feature of the semiconductor wafer. A balance mass is not needed to counteract the motion of a stage because the opposite motions of the respective stages cancel each other.

System and method for supplying and dispensing bubble-free photolithography chemical solutions

A photolithography system includes a variable-volume buffer tank, a dispensing system connected to the buffer tank, and a valve configured to release gas from a head space of the buffer tank while blocking the release of liquid from the head space. A storage container has an opening at the bottom and drains to the buffer tank through that opening. The buffer tank has a storage capacity sufficient to receive the full contents of the storage container. The system supplies chemical solutions to the dispensing system while keeping the chemical solutions from contact with air and other gases.

Tool Induced Shift Reduction Determination for Overlay Metrology

One embodiment relates to a method for semiconductor workpiece processing. In this method, a baseline tool induced shift (TIS) is measured by performing a baseline number of TIS measurements on a first semiconductor workpiece. After the baseline TIS has been determined, the method determines a subsequent TIS based on a subsequent number of TIS measurements taken on a first subsequent semiconductor workpiece. The subsequent number of TIS measurements is less than the baseline number of TIS measurements. 1. A method for measuring tool induced shift (TIS) , comprising:positioning a semiconductor workpiece so that a field of view (FOV) corresponding to a first alignment mark on the semiconductor workpiece changes its directional orientation from a first angular orientation to a second angular orientation, wherein the first and second angular orientations are measured with respect to a first diametric axis extending through the semiconductor workpiece;viewing the first alignment mark at a plurality of optical angles at both the first angular orientation and the second angular orientation; andmeasuring a first plurality of overlay offsets, respectively, for the plurality of optical angles at the first and second angular orientations for the first alignment mark.2. The method of claim 1 , further comprising:using the first plurality of overlay offsets to determine a first curve or line representing TIS for the first alignment mark as a function of optical angle.3. The method of claim 2 , further comprising:repositioning the semiconductor workpiece so that the FOV corresponds to a second alignment mark on the semiconductor workpiece;viewing the second alignment mark at a plurality of optical angles at both the first angular orientation and the second angular orientation;measuring a second plurality of overlay offsets, respectively, for the plurality of optical angles at the first and second angular orientations for the second alignment mark; anddetermining a plurality of ...

WAFER EDGE EXPOSURE UNIT

A wafer edge exposure unit comprises a chuck for supporting a wafer. The chuck is rotatable about a central axis. A plurality of light sources are positioned or movably positionable with a common radial distance from the axis of the rotatable chuck, each light source configured to direct exposure light on a respective edge portion of the wafer simultaneously.

System and method for supplying and dispensing bubble-free photolithography chemical solutions

A photolithography system includes a variable-volume buffer tank, a dispensing system connected to the buffer tank, and a valve configured to release gas from a head space of the buffer tank while blocking the release of liquid from the head space. A storage container has an opening at the bottom and drains to the buffer tank through that opening. The buffer tank has a storage capacity sufficient to receive the full contents of the storage container. The system supplies chemical solutions to the dispensing system while keeping the chemical solutions from contact with air and other gases.

Photoresist materials and photolithography processes

A lithography apparatus generates a tunable magnetic field to facilitate processing of photoresist. The lithography apparatus includes a chamber and a substrate stage in the chamber operable to hold a substrate. A magnetic module provides a magnetic field to the substrate on the substrate stage. The magnetic module is configured to provide the magnetic field in a tunable and alternating configuration with respect to its magnitude and frequency. The magnetic field is provided to have a gradient in magnitude along a Z-axis that is perpendicular to the substrate stage to cause magnetically-charged particles disposed over the substrate stage to move up and down along the Z-axis. The lithography apparatus also includes a radiation energy source and an objective lens configured to receive radiation energy from the radiation energy source and direct the radiation energy toward the substrate positioned on the substrate stage.

SYSTEM AND METHOD FOR SUPPLYING AND DISPENSING BUBBLE-FREE PHOTOLITHOGRAPHY CHEMICAL SOLUTIONS

A method of supplying a chemical solution to a photolithography system. The chemical solution is pumped from a variable-volume buffer tank. The pumped chemical solution is dispensed in a spin-coater. The variable-volume buffer tank is refilled by emptying a storage container filled with the chemical solution into the variable-volume buffer tank.

Enhanced scanner throughput system and method

A method and system to improve scanner throughput is provided. An image from a reticle is projected onto a substrate using a continuous linear scanning procedure in which an entire column of die or cells of die is scanned continuously, i.e. without stepping to a different location. Each scan includes translating a substrate with respect to a fixed beam. While the substrate is translated, the reticle is also translated. When a first die or cell of die is projected onto the substrate, the reticle translates along a direction opposite the scan direction and as the scan continues along the same direction, the reticle then translates in the opposite direction of the substrate thereby forming an inverted pattern on the next die or cell. The time associated with exposing the substrate is minimized as the stepping operation only occurs after a complete column of cells is scanned.

LITHO CLUSTER AND MODULIZATION TO ENHANCE PRODUCTIVITY

The present disclosure relates to a lithographic tool arrangement for semiconductor workpiece processing. The lithographic tool arrangement groups lithographic tools into clusters, and selectively transfers a semiconductor workpiece between a plurality of lithographic tools of a first type in a first cluster to a plurality of lithographic tools of a second type in a second cluster. The selective transfer is achieved though a transfer assembly, which is coupled to a defect scan tool that identifies defects generated in the lithographic tool of the first type. The disclosed lithographic tool arrangement also utilizes shared structural elements such as a housing assembly, and shared functional elements such as gases and chemicals. The lithographic tool arrangement may consist of baking, coating, exposure, and development units configured to provide a modularization of these various components in order to optimize throughput and efficiency for a given lithographic fabrication process.

SYSTEM AND METHOD FOR SUPPLYING AND DISPENSING BUBBLE-FREE PHOTOLITHOGRAPHY CHEMICAL SOLUTIONS

A photolithography system includes a variable-volume buffer tank, a dispensing system connected to the buffer tank, and a valve configured to release gas from a head space of the buffer tank while blocking the release of liquid from the head space. A storage container has an opening at the bottom and drains to the buffer tank through that opening. The buffer tank has a storage capacity sufficient to receive the full contents of the storage container. The system supplies chemical solutions to the dispensing system while keeping the chemical solutions from contact with air and other gases. 1. A photolithography system , comprising:a variable-volume buffer tank;a dispensing system connected to the buffer tank and configured to dispense a photolithography chemical solution from the buffer tank onto wafers; anda valve configured to release gas from a head space of the buffer tank while blocking the release of liquid from the head space.2. The photolithography system of claim 1 , further comprising:a storage container having a storage capacity; anda connector forming a connection for transferring fluid from the storage container to the buffer tank;wherein the variable-volume buffer tank has a maximum volume that is greater than the storage capacity of the storage container.3. The photolithography system of claim 2 , wherein the connection for transferring fluid from the storage container to the buffer tank is configured to drain the contents of the storage container from out of the bottom of the storage container.4. The photolithography system of claim 1 , wherein the buffer tank comprises a collapsible liner within a rigid shell.5. The photolithography system of claim 1 , wherein the buffer tank comprises a piston and cylinder arrangement.6. The photolithography system of claim 1 , wherein the buffer tank comprises a flexible container with accordion pleats.7. The photolithography system of claim 1 , wherein the valve is an electronically controlled valve.8. The ...

Wafer edge exposure module

A wafer edge exposure module connected to a semiconductor wafer track system. The wafer edge exposure module includes a wafer spin device, an optical system, a scanner interface module, and a controller. The wafer spin device supports a wafer for processing. The optical system directs exposure light on a respective edge portion of the wafer simultaneously to create a dummy track on the edge of the wafer. The scanner interface module sends and/or receives dummy edge exposure information from a scanner via a computer network. The controller receives the dummy edge exposure information from the scanner interface module and uses the exposure information to control the optical system.

Structure of stacking scatterometry based overlay marks for marks footprint reduction

The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; a plurality of material layers formed on the semiconductor substrate, each of the material layers including a circuit pattern therein; and a plurality of diffraction-based periodic marks formed in the plurality of material layers and stacked in a same region. One of the diffraction-based periodic marks is different from at least one other of the diffraction-based periodic marks in pitch.

Method To Improve Mask Critical Dimension Uniformity (CDU)

A method and system for fabricating a substrate is disclosed. First, a plurality of process chambers are provided, at least one of the plurality of process chambers adapted to receive at least one plasma filtering plate and at least one of the plurality of process chambers containing a plasma filtering plate library. A plasma filtering plate is selected and removed from the plasma filtering plate library. Then, the plasma filtering plate is inserted into at least one of the plurality of process chambers adapted to receive at least one plasma filtering plate. Subsequently, an etching process is performed in the substrate.

Cost-effective method for extreme ultraviolet (EUV) mask production

The present disclosure provides for many different embodiments. An exemplary method can include providing a blank mask and a design layout to be patterned on the blank mask, the design layout including a critical area; inspecting the blank mask for defects and generating a defect distribution map associated with the blank mask; mapping the defect distribution map to the design layout; performing a mask making process; and performing a mask defect repair process based on the mapping.

FRAME CELL FOR SHOT LAYOUT FLEXIBILITY

A method includes receiving an integrated circuit chip size and determining a frame structure segment size based on the chip size. The frame structure segment size is less than the chip size. An initial shot layout having a chip count is established in which a number of shots, each including at least one frame structure segment and at least one chip, are arranged in vertically and horizontally aligned columns and rows. At least one additional shot layout is established in which at least one of a row or column of shots is offset from an adjacent row or column of shots. The initial shot layout is compared to the at least one additional shot layout, and a final shot layout is selected based in part on the total number of shots in the shot layout and has a final chip count that is greater than or equal to the initial chip count.

System and Method for Cleaning a Wafer Chuck

A wafer chuck is cleaned using a cleaning cap to remove processing residue and particulate matter. The cleaning cap is configured to overlie and align with the wafer chuck and includes a base and a first roller connected to the base and having wound therearound a cleaning cloth. The cleaning cap further includes a second roller connected to the base and having attached thereto a free end of the cleaning cloth. During use, the cleaning cloth winds upon the second roller from the first roller when the second roller rotates about its axis. The cleaning cap can be positioned relative the wafer chuck by way of a manipulator to ensure the cleaning cloth contacts the wafer chuck with sufficient force. The cleaning cloth rubs the wafer chuck with both translational motion and rotational motion. 1. A device comprising:a wafer chuck; a base,', 'a first roller connected to the base and having wound therearound a cleaning cloth;', 'a second roller connected to the base and having attached thereto a free end of the cleaning cloth, such that the cleaning cloth winds upon the second roller from the first roller when the second roller rotates about its axis; and, 'a cleaning cap configured to overlie and align with the wafer chuck, the cleaning cap includinga manipulator configured to position the cleaning cap onto the wafer chuck such that the cleaning cloth comes into contact with surface of the wafer chuck.2. The device of further comprising:a third roller connected to the base and having wound therearound a second cleaning cloth;a fourth roller connected to the base and having attached thereto a free end of the second cleaning cloth, such that the second cleaning cloth winds upon the fourth roller from the third roller when the second roller rotates about its axis.3. The device of further comprising:a brush connected to the base and positioned to sweep particulate matter from the cleaning cloth.4. The device of further comprising a vacuum orifice positioned adjacent the brush ...

Lithography patterning method

A method for fabricating an integrated circuit device is disclosed. The method is a lithography patterning method that can include providing a substrate; forming a protective layer over the substrate; forming a conductive layer over the protective layer; forming a resist layer over the conductive layer; and exposing and developing the resist layer.

Litho cluster and modulization to enhance productivity

The present disclosure relates to a lithographic tool arrangement for semiconductor workpiece processing. The lithographic tool arrangement groups lithographic tools into clusters, and selectively transfers a semiconductor workpiece between a plurality of lithographic tools of a first type in a first cluster to a plurality of lithographic tools of a second type in a second cluster. The selective transfer is achieved though a transfer assembly, which is coupled to a defect scan tool that identifies defects generated in the lithographic tool of the first type. The disclosed lithographic tool arrangement also utilizes shared structural elements such as a housing assembly, and shared functional elements such as gases and chemicals. The lithographic tool arrangement may consist of baking, coating, exposure, and development units configured to provide a modularization of these various components in order to optimize throughput and efficiency for a given lithographic fabrication process.

Frame cell for shot layout flexibility

A method includes receiving an integrated circuit chip size and determining a frame structure segment size based on the chip size. The frame structure segment size is less than the chip size. An initial shot layout having a chip count is established in which a number of shots, each including at least one frame structure segment and at least one chip, are arranged in vertically and horizontally aligned columns and rows. At least one additional shot layout is established in which at least one of a row or column of shots is offset from an adjacent row or column of shots. The initial shot layout is compared to the at least one additional shot layout, and a final shot layout is selected based in part on the total number of shots in the shot layout and has a final chip count that is greater than or equal to the initial chip count.

Line end spacing measurement

A method including: providing collinear first and second lines in a mask layer over a substrate, the first line having at one end a first line end and having a first line body adjacent the first line end, and the second line having at one end a second line end and having a second line body adjacent the second line end; measuring line widths of the first line body and the second line body; locating effective line end positions for the first line end based on the line width of the first line body and for the second line end based on the line width of the second line body; and measuring a distance between the effective line end positions, as an effective line end spacing.

Wafer edge exposure unit

A wafer edge exposure unit comprises a chuck for supporting a wafer. The chuck is rotatable about a central axis. A plurality of light sources are positioned or movably positionable with a common radial distance from the axis of the rotatable chuck, each light source configured to direct exposure light on a respective edge portion of the wafer simultaneously.

Method of making wafer assembly

A method including bonding a process wafer having integrated circuits and a carrier wafer having at least one alignment mark to form a wafer assembly. The method further includes aligning the wafer assembly using the at least one alignment mark of the carrier wafer.

COST-EFFECTIVE METHOD FOR EXTREME ULTRAVIOLET (EUV) MASK PRODUCTION

The present disclosure provides for many different embodiments. An exemplary method can include providing a blank mask and a design layout to be patterned on the blank mask, the design layout including a critical area; inspecting the blank mask for defects and generating a defect distribution map associated with the blank mask; mapping the defect distribution map to the design layout; performing a mask making process; and performing a mask defect repair process based on the mapping.

NOVEL TREATMENT FOR MASK SURFACE CHEMICAL REDUCTION

A method includes forming an absorption material layer on a mask; applying a plasma treatment to the mask to reduce chemical contaminants after the forming of the absorption material layer; performing a chemical cleaning process of the mask; and performing a gas injection to the mask.

Adaptive baking system and method of using the same

An adaptive baking system includes a baking chamber configured to receive a wafer, and a heating element configured to support the wafer. The adaptive baking system further includes a controller configured to receive temperature information related to the heating element and the wafer, wherein the controller is further configured to adjust an amount of heat provided by the heating element during a baking process in response to the temperature information.

LITHOGRAPHIC PLANE CHECK FOR MASK PROCESSING

The present disclosure provides for many different embodiments. An exemplary method can include providing a mask fabricated according to a design pattern; extracting a mask pattern from the mask; converting the mask pattern into a rendered mask pattern, wherein the simulated design pattern includes the design pattern and any defects in the mask; simulating a lithography process using the rendered mask pattern to create a virtual wafer pattern; and determining whether any defects in the mask are critical based on the virtual wafer pattern. The critical defects in the mask can be repaired.

Method of Inhibiting Photoresist Pattern Collapse

A method of inhibiting photoresist pattern collapse which includes the steps of providing a substrate; providing a photoresist layer on the substrate; exposing and developing the photoresist layer; applying a top anti-reflective coating layer to the photoresist layer; rinsing the photoresist layer; and drying the photoresist layer.

Photoresist materials and photolithography processes

A material for use in lithography processing includes a polymer that turns soluble to a base solution in response to reaction with acid and a plurality of magnetically amplified generators (MAGs) each having a magnetic element and each decomposing to form acid bonded with the magnetic element in response to radiation energy.

In-situ immersion hood cleaning

An apparatus includes a wafer stage configured to secure a wafer; and a cleaning module including a tank adjacent to the wafer stage, and is positioned outside the region occupied by the wafer. The cleaning module is configured to receive de-ionized (DI) water into the tank and extract the DI water out of the tank. The tank is configured to hold DI water with a top surface of the DI water substantially level with a top surface of the wafer.

Tool induced shift reduction determination for overlay metrology

One embodiment relates to a method for semiconductor workpiece processing. In this method, a baseline tool induced shift (TIS) is measured by performing a baseline number of TIS measurements on a first semiconductor workpiece. After the baseline TIS has been determined, the method determines a subsequent TIS based on a subsequent number of TIS measurements taken on a first subsequent semiconductor workpiece. The subsequent number of TIS measurements is less than the baseline number of TIS measurements.

Litho Cluster and Modulization to Enhance Productivity

The present disclosure relates to a lithographic tool arrangement for semiconductor workpiece processing. The lithographic tool arrangement groups lithographic tools into clusters, and selectively transfers a semiconductor workpiece between a plurality of lithographic tools of a first type in a first cluster to a plurality of lithographic tools of a second type in a second cluster. The selective transfer is achieved though a transfer assembly, which is coupled to a defect scan tool that identifies defects generated in the lithographic tool of the first type. The disclosed lithographic tool arrangement also utilizes shared structural elements such as a housing assembly, and shared functional elements such as gases and chemicals. The lithographic tool arrangement may consist of baking, coating, exposure, and development units configured to provide a modularization of these various components in order to optimize throughput and efficiency for a given lithographic fabrication process.

Lithographic plane check for mask processing

The present disclosure provides for many different embodiments. An exemplary method can include providing a mask fabricated according to a design pattern; extracting a mask pattern from the mask; converting the mask pattern into a rendered mask pattern, wherein the simulated design pattern includes the design pattern and any defects in the mask; simulating a lithography process using the rendered mask pattern to create a virtual wafer pattern; and determining whether any defects in the mask are critical based on the virtual wafer pattern. The critical defects in the mask can be repaired.

WAFER ASSEMBLY WITH CARRIER WAFER

A wafer assembly includes a process wafer and a carrier wafer. Integrated circuits are formed on the process wafer. The carrier wafer is bonded to the process wafer. The carrier wafer has at least one alignment mark. 1. A wafer assembly , comprising:a process wafer, wherein integrated circuits are formed on the process wafer; anda carrier wafer bonded to the process wafer, wherein the carrier wafer has at least one alignment mark.2. The wafer assembly of claim 1 , further comprising a bonding adhesive layer that bonds the process wafer and the carrier wafer.3. The wafer assembly of claim 1 , further comprising an epi layer that bonds the process wafer and the carrier wafer.4. The wafer assembly of claim 1 , wherein the epi layer has a thickness ranging from 100 angstrom to 1000 angstrom.5. The wafer assembly of claim 1 , wherein the process wafer has no alignment mark.6. The wafer assembly of claim 1 , wherein the carrier wafer has multiple alignment marks distributed at equal distance along the circumference of the carrier wafer.7. The wafer assembly of claim 6 , wherein the multiple alignment marks have different sizes.8. The wafer assembly of claim 1 , wherein a first thickness of the process wafer is less than a second thickness of the carrier wafer.917-. (canceled)18. A wafer assembly claim 1 , comprising:a process wafer having a first thickness and no alignment mark, wherein integrated circuits are formed on the process wafer; anda carrier wafer having a second thickness and bonded to the process wafer,wherein the carrier wafer has multiple alignment marks distributed at equal distance along the circumference of the carrier wafer and the first thickness is less than the second thickness.19. The wafer assembly of claim 18 , further comprising a bonding adhesive layer that bonds the process wafer and the carrier wafer.20. The wafer assembly of claim 18 , further comprising an epi layer that bonds the process wafer and the carrier wafer claim 18 , wherein the epi ...

ENHANCED SCANNER THROUGHPUT SYSTEM AND METHOD

A method and system to improve scanner throughput is provided. An image from a reticle is projected onto a substrate using a continuous linear scanning procedure in which an entire column of die or cells of die is scanned continuously, i.e. without stepping to a different location. Each scan includes translating a substrate with respect to a fixed beam. While the substrate is translated, the reticle is also translated. When a first die or cell of die is projected onto the substrate, the reticle translates along a direction opposite the scan direction and as the scan continues along the same direction, the reticle then translates in the opposite direction of the substrate thereby forming an inverted pattern on the next die or cell. The time associated with exposing the substrate is minimized as the stepping operation only occurs after a complete column of cells is scanned. 1. A method for patterning a substrate , said method comprising:providing a substrate that is divided into a plurality of die arranged in columns and rows;providing an illumination source, a reticle and a projection lens;patterning said substrate with a pattern from said reticle by projecting a beam from said illumination source through said reticle and said projection lens and onto said substrate by scanning by carrying out a plurality of scans, each said scan comprising continuously translating said substrate relative to said beam in a continuous linear scan along a complete one of said columns in a scan direction.2. The method as in claim 1 , wherein said pattern comprises a cell including a plurality of said die claim 1 , and wherein each said scan includes repeatedly projecting said cell onto said substrate along said scan direction.3. The method as in claim 1 , wherein said patterning said substrate includes translating said reticle relative to said beam during said scanning claim 1 , said translating said reticle including translating said reticle along said scan direction to form a first ...

ADAPTIVE BAKING METHOD

A controller includes a non-transitory computer readable medium configured to store information related to a target temperature of a wafer, a target temperature of a heating element, a temperature of the wafer, and a temperature of the heating element. The controller further includes a processor connected to the non-transitory computer readable medium, the processor configured to generate at least one heating signal during a baking process to adjust a duration of an entirety of the baking process in response to the temperature of the wafer and the temperature of the heating element. 1. A controller comprising:a non-transitory computer readable medium configured to store information related to a target temperature of a wafer, a target temperature of a heating element, a temperature of the wafer, and a temperature of the heating element; anda processor connected to the non-transitory computer readable medium, the processor configured to generate at least one heating signal during a baking process to adjust a duration of an entirety of the baking process in response to the temperature of the wafer and the temperature of the heating element.2. The controller of claim 1 , wherein the processor is further configured to generate a plurality of heating signals claim 1 , wherein each heating signal of the plurality of heating signals corresponds to a heating zone of a plurality of heating zones of the heating element.3. The controller of claim 1 , wherein the processor is configured to generate the at least one heating signal for a first heating zone of the heating element based on an amount of heat provided by a plurality of heating zones of the heating element adjacent to the first heating zone.4. A method comprising:performing a baking process on a wafer, wherein the baking process comprises heating the wafer for a first duration using a heating element;measuring a temperature of the heating element and a temperature of the wafer during the first duration to obtain ...

Two-Dimensional Marks

A method for controlling semiconductor production through use of a Focus Exposure Matrix (FEM) model includes taking measurements of characteristics of a two-dimensional mark formed onto a substrate, the two-dimensional mark including two different patterns along two different cut-lines, and comparing the measurements with a FEM model to determine focus and exposure conditions used to form the two-dimensional mark. The FEM model was created using measurements taken of corresponding two-dimensional marks formed onto a substrate under varying focus and exposure conditions.

Hybrid Focus-Exposure Matrix

A method for controlling semiconductor production through use of a hybrid Focus Exposure Matrix (FEM) model includes taking measurements of a set of structures formed onto a substrate. The method further includes using a FEM model to determine focus and exposure conditions used to form the structure The model was created through use of measurements of structures formed on a substrate under varying focus and exposure conditions, the measurements being taken using both an optical measurement tool and a scanning electron microscope.

ADAPTIVE BAKING SYSTEM AND METHOD OF USING THE SAME

An adaptive baking system includes a baking chamber configured to receive a wafer, and a heating element configured to support the wafer. The adaptive baking system further includes a controller configured to receive temperature information related to the heating element and the wafer, wherein the controller is further configured to adjust an amount of heat provided by the heating element during a baking process in response to the temperature information. 1. An adaptive baking system comprising:a baking chamber configured to receive a wafer;a heating element configured to support the wafer; anda controller configured to receive temperature information related to the heating element and the wafer, wherein the controller is further configured to adjust an amount of heat provided by the heating element during a baking process in response to the temperature information.2. The adaptive baking system of claim 1 , wherein the heating element comprises a plurality of heating zones.3. The adaptive baking system of claim 2 , wherein the controller is configured to individually control each heating zone of the plurality of heating zones.4. The adaptive baking system of claim 2 , wherein the controller is configured to control a first zone of the plurality of heating zones based on an amount of heat provided by heating zones adjacent to the first heating zone.5. The adaptive baking system of claim 1 , wherein the controller is configured to increase a duration of the baking process in response to the temperature information.6. The adaptive baking system of claim 1 , wherein the heating element comprises at least one temperature sensor embedded in a surface of the heating element configured to support the wafer.7. The adaptive baking system of claim 1 , wherein the controller is configured to provide a single heating signal to the heating element for adjusting the amount of heat provided by the heating element.8. The adaptive baking system of claim 1 , wherein the controller is ...

METHOD OF MAKING WAFER ASSEMBLY

A method including bonding a process wafer having integrated circuits and a carrier wafer having at least one alignment mark to form a wafer assembly. The method further includes aligning the wafer assembly using the at least one alignment mark of the carrier wafer. 1. A method , comprising:bonding a process wafer having integrated circuits and a carrier wafer having at least one alignment mark to form a wafer assembly; andaligning the wafer assembly using the at least one alignment mark of the carrier wafer.2. The method of claim 1 , wherein the bonding is performed by using a bonding adhesive layer between the process wafer and the carrier wafer.3. The method of claim 1 , wherein the bonding comprises:growing an epi layer under the process wafer or over the carrier wafer;placing the process wafer and the carrier wafer together with the epi layer located between the process wafer and the carrier wafer; andannealing the process wafer, the epi layer, and the carrier wafer.4. The method of claim 3 , wherein the epi layer has a thickness ranging from 100 angstroms to 1000 angstroms.5. The method of claim 3 , wherein the annealing is performed at a temperature ranging from 300° C. to 500° C.6. The method of claim 1 , further comprising debonding the process wafer and the carrier wafer.7. The method of claim 1 , wherein bonding the process wafer to the carrier wafer comprises bonding the process wafer to the carrier wafer having multiple alignment marks distributed at equal distance along the circumference of the carrier wafer.8. The method of claim 7 , wherein bonding the process wafer to the carrier wafer comprises bonding the process wafer to the carrier wafer having at least one alignment mark of the multiple alignment marks having a different size from at least one other alignment mark of the multiple alignment marks.9. The method of claim 1 , wherein bonding the process wafer to the carrier wafer comprises bonding the process wafer having a first thickness to the ...

ADAPTIVE BAKING METHOD

A method includes supporting a wafer on a heating element, wherein the heating element is located in a baking chamber. The method further includes heating the wafer for a first duration using the heating element. The method further includes measuring a temperature of the heating element and a temperature of the wafer during the first duration to obtain temperature information. The method further includes adjusting an amount of heat provided by the heating element during the first duration, wherein the adjusting of the amount of heat includes decreasing the amount of heat provided by the heating element as a rate of change of the temperature information versus time increases. 1. A method comprising:supporting a wafer on a heating element, wherein the heating element is located in a baking chamber;heating the wafer for a first duration using the heating element;measuring a temperature of the heating element and a temperature of the wafer during the first duration to obtain temperature information; andadjusting an amount of heat provided by the heating element during the first duration, wherein the adjusting of the amount of heat comprises decreasing the amount of heat provided by the heating element as a rate of change of the temperature information versus time increases.2. The method of claim 1 , wherein the heating the wafer comprises heating the wafer using a plurality of heating zones claim 1 , and adjusting the amount of heat provided by the heating element comprises individually controlling each heating zone of the plurality of heating zones.3. The method of claim 2 , wherein the adjusting the amount of heat provided by the heating element comprises adjusting the amount of heat provided by a first heating zone of the plurality of heating zones based on an amount of heat of heating zones of the plurality of heating zones adjacent to the first heating zone.4. The method of claim 2 , wherein the adjusting the amount of heat comprises receiving claim 2 , via the ...

Wafer assembly with carrier wafer and manufacturing method therefor

Waferanordnung mit: einem Prozesswafer (102), wobei auf dem Prozesswafer integrierte Schaltkreise ausgebildet sind, und einem Trägerwafer (104), der mit dem Prozesswafer (102) lösbar verbunden ist, wobei der Trägerwafer wenigstens eine Ausrichtmarke (106) und der Prozesswafer (102) keine Ausrichtmarken aufweist. A wafer assembly comprising: a process wafer (102) having integrated circuits formed on the process wafer and a carrier wafer (104) detachably connected to the process wafer (102), the carrier wafer having at least one alignment mark (106) and the process wafer (102 ) has no alignment marks.

Adaptive baking system, method of using the same, and controller for the same

一種適應性烘烤系統，包含烘烤腔體與加熱元件。烘烤腔體設置以接收晶圓。加熱元件設置以承載晶圓。適應性烘烤系統更包含控制器。控制器設置以接收關於加熱元件與晶圓的溫度訊息，其中控制器更設置以因應溫度訊息調整加熱元件於烘烤程序期間所提供之熱量。

System and method for cleaning a wafer chuck

A wafer chuck is cleaned using a cleaning cap to remove processing residue and particulate matter. The cleaning cap is configured to overlie and align with the wafer chuck and includes a base and a first roller connected to the base and having wound therearound a cleaning cloth. The cleaning cap further includes a second roller connected to the base and having attached thereto a free end of the cleaning cloth. During use, the cleaning cloth winds upon the second roller from the first roller when the second roller rotates about its axis. The cleaning cap can be positioned relative the wafer chuck by way of a manipulator to ensure the cleaning cloth contacts the wafer chuck with sufficient force. The cleaning cloth rubs the wafer chuck with both translational motion and rotational motion.

半導體製程裝置及半導體製造方法

微影設備配置及提升半導體工件製程生產率的方法

本揭示是關於半導體工件製程的微影設備配置，其將微影設備聚集成集束型製程設備，並且在第一集束型製程設備的多個第一型微影設備之間選擇性地將半導體工件傳送至第二集束型製程設備的多個第二型微影設備，此選擇性傳送是經由傳送組件達成，傳送組件耦接至缺陷掃瞄工具以鑑定在第一型微影設備內所產生的缺陷。本揭示之微影設備配置還使用共用結構的元件例如外殼組件，以及共用功能的元件例如共用氣體與化學藥品。此微影設備配置可由烘烤、塗佈、曝光以及顯影單元組成，可調整各組成單元讓特定微影製程的生產率及效率最佳化。

System and method for supplying and dispensing bubble-free photolithography chemical solutions

A method of supplying a chemical solution to a photolithography system. The chemical solution is pumped from a variable-volume buffer tank. The pumped chemical solution is dispensed in a spin-coater. The variable-volume buffer tank is refilled by emptying a storage container filled with the chemical solution into the variable-volume buffer tank.

System und verfahren zum zuführen und abgeben blasenfreier fotolithographischer chemischer lösungen

Fotolithographisches System (100), welches umfasst:einen Puffertank (145) mit variablem Volumen;einen Speicherbehälter (105), der konfiguriert ist, eine fotolithographische chemische Lösung (150) in den Puffertank (145) abzulassen, bis der Speicherbehälter (105) leer ist,wobei der Speicherbehälter (105) im Verhältnis zum Puffertank (145) erhöht angeordnet ist, so dass der Abfluss der Lösung (150) von dem Speicherbehälter (105) zu dem Puffertank (145) durch Schwerkraft erfolgt;ein Abgabesystem (160), das mit dem Puffertank (145) verbunden und dazu konfiguriert ist, die fotolithographische chemische Lösung (150) von dem Puffertank (145) an Wafer abzugeben; undein Ventil (141), das dazu konfiguriert ist, Gas aus einem Kopfraum (143) des Puffertanks (145) austreten zu lassen, während es das Austreten von Flüssigkeit aus dem Kopfraum verhindert.