Halbleitervorrichtung und Verfahren zum Herstellen einer Halbleitervorrichtung

Halbleitervorrichtung (200), die Folgendes umfasst:einen ersten aktiven Bereich (205) benachbart zu einer ersten Seite (256) eines Grabenisolierungsbereichs, eines STI-Bereichs (209), wobei der erste aktive Bereich (205) Folgendes umfasst:- einen ersten proximalen Grat (252) benachbart zu dem STI-Bereich (209), der eine erste proximale Grathöhe (226) aufweist; und- einen ersten distalen Grat (254) benachbart zu dem ersten proximalen Grat (252), der eine erste distale Grathöhe (224) aufweist;einen zweiten aktiven Bereich (207) benachbart zu einer zweiten Seite (258) des STI-Bereichs (209), wobei der zweite aktive Bereich (207) Folgendes umfasst:- einen zweiten proximalen Grat (253) benachbart zu dem STI-Bereich (209), der eine zweite proximale Grathöhe (227) aufweist; und- einen zweiten distalen Grat (255) benachbart zu dem zweiten proximalen Grat (253), der eine zweite distale Grathöhe (225) aufweist; undein Oxid (230) des STI-Bereichs (209), das in einer Öffnung in einer Oberseite einer ...

Mechanisms for semiconductor device structure

Semiconductor device structures and methods for forming the same are provided. The method for forming a semiconductor device structure includes forming a dummy gate structure over a substrate and forming a dielectric layer over the substrate around the dummy gate structure. The method for forming a semiconductor device structure further includes removing the dummy gate structure and removing a portion of the dielectric layer to form a funnel shaped trench. The method for forming a semiconductor device structure further includes forming a gate structure in a bottom portion of the funnel shaped trench and filling a hard mask material in a top portion of the funnel shaped trench to form a funnel shaped hard mask structure.

Method for manufacturing semiconductor structure with mask structure

Semiconductor structures and methods for forming the same are provided. The method includes forming a dummy gate structure and forming a spacer on a lower portion of a sidewall of the dummy gate structure and exposing an upper portion of the sidewall of the dummy gate structure. The method further includes forming a dielectric layer covering the upper portion of the sidewall of the dummy gate structure exposed by the spacer and removing the dummy gate structure to form a tube-shaped trench. The method further includes removing a portion of the dielectric layer to form a cone-shaped trench and forming a gate structure in a bottom portion of the tube-shaped trench. The method further includes forming a hard mask structure in the cone-shaped trench and an upper portion of the tube-shaped trench, and an interface between the hard mask structure and the dielectric layer overlaps the spacer.

Method of forming trenches with different depths

A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure.

SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF

A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.

Verfahren zum Ausbilden von Gräben mit unterschiedlichen Tiefen und Vorrichtung

Verfahren, umfassend:Ausbilden einer dielektrischen Schicht (310) über einem Substrat (210), das eine Gate-Struktur (230A) aufweist;Ausbilden eines ersten Grabens (430, 430B) in der dielektrischen Schicht (310);Ausbilden von dielektrischen Abstandshaltern (510) entlang Seitenwänden des ersten Grabens (430, 430B), wobei die Seitenwände des ersten Grabens (430) durch die dielektrische Schicht (310) definiert sind;Entfernen eines Teils der dielektrischen Abstandshalter (510), um einen Teil der Seitenwände des ersten Grabens (430, 430B) freizulegen, die durch die dielektrische Schicht (310) definiert sind, wobei ein weiterer Teil der dielektrischen Abstandshalter (510) in dem ersten Graben (430, 430B) zurück bleibt, nachdem der Teil der dielektrischen Abstandshalter (510) entfernt wurde;Ausbilden eines ersten Metallmerkmals (730) in dem ersten Graben (430) über dem weiteren Teil der dielektrischen Abstandshalter (510) und entlang der freiliegenden Teile der Seitenwände des ersten Grabens (430, 430B)Ausbilden einer weiteren dielektrischen Schicht (810) über dem ersten Metallmerkmal (730) und der Gate-Struktur (230A) ; undAusbilden eines zweiten Grabens (826) durch die weitere dielektrische Schicht (810), um einen Teil des ersten Metallmerkmals (730) freizulegen, und eines dritten Grabens (825) durch die weitere dielektrische Schicht (810) und die dielektrische Schicht (310), um einen Teil der Gate-Struktur (230A) freizulegen, wobei der zweite Graben (826) und der dritte Graben (825) in dem gleichen Ätzverfahren ausgebildet werden. A method comprising: forming a dielectric layer (310) over a substrate (210) having a gate structure (230A); forming a first trench (430, 430B) in the dielectric layer (310); forming dielectric spacers ( 510) along sidewalls of the first trench (430, 430B), the sidewalls of the first trench (430) being defined by the dielectric layer (310); removing a portion of the dielectric spacers (510) around a portion of the sidewalls of the first trench ...

Semiconductor arrangement and formation thereof

A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.

Semiconductor arrangement and formation thereof

A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.

Halbleiteranordnung und deren Herstellung

Eine Halbleiteranordnung und ein Verfahren zum Bilden der Gleichen werden beschrieben. Eine Halbleiteranordnung umfasst eine dritte Metallverbindung in Kontakt mit einer ersten Metallverbindung in einer ersten aktiven Region und eine zweite Metallverbindung in einer zweiten aktiven Region und ist über eine flache Grabenisolationsregion, die zwischen der ersten aktiven Region und der zweiten aktiven Region gebildet ist, gebildet. Ein Verfahren zum Bilden der Halbleiteranordnung umfasst ein Bilden einer ersten Öffnung über der ersten Metallverbindung, der STI Region und der zweiten Metallverbindung, und ein Bilden einer dritten Metallverbindung in der ersten Öffnung. Das Bilden der dritten Metallverbindung über der ersten Metallverbindung und der zweiten Metallverbindung verringert die RC Kopplung.

Method of forming contact structure of gate structure

A method of forming a contact structure of a gate structure is provided. In the method, an oxidation layer and a first sidewall layer disposed between a first metal gate and a second metal gate are etched to expose an underlying silicon substrate. A silicide portion defined by a contact profile is deposited in the exposed portion of the silicon substrate. A second sidewall layer substantially covers the first sidewall layer and at least partially covering the silicide portion is formed after depositing the silicide portion. A metal glue layer is deposited around the first metal gate and the second metal gate defining a trench above the silicide portion. A metal plug is deposited within the trench.

Structure and method for overlay marks

The overlay mark and method for making the same are described. In one embodiment, a semiconductor overlay structure includes gate stack structures formed on the semiconductor substrate and configured as an overlay mark, and a doped semiconductor substrate disposed on both sides of the gate stack structure that includes at least as much dopant as the semiconductor substrate adjacent to the gate stack structure in a device region. The doped semiconductor substrate is formed by at least three ion implantation steps.

METHOD AND APPARATUS FOR ENHANCED DIPOLE LITHOGRAPHY

Provided is a lithography system that includes a source for providing energy, an imaging system configured to direct the energy onto a substrate to form an image thereon, and a diffractive optical element (DOE) incorporated with the imaging system, the DOE having a first dipole located in a first direction and a second dipole located in the first direction or a second direction perpendicular the first direction. The first dipole includes a first energy-transmitting region spaced a first distance from a center of the DOE. The second dipole includes a second energy-transmitting region spaced a second distance from the center of the DOE. The first distance is greater than the second distance.

Method for forming integrated circuit structure with thinned contact

Methods for forming integrated circuit structures are provided. The method includes providing a substrate including a first diffusion region, a second diffusion region, and an isolation structure separating the first diffusion region and the second diffusion region. The method further includes forming a gate structure over the substrate and forming an inter-layer dielectric (ILD) layer over the substrate. The method further includes forming a cutting mask over a portion of the gate structure over the isolation structure, and the cutting mask has an extending portion covering a portion of the ILD layer. The method further includes forming a photoresist layer having an opening, and a portion of the extending portion of the cutting mask is exposed by the opening. The method further includes etching the ILD layer through the opening to form a trench and filling the trench with a conductive material to form a contact.

VERFAHREN ZUM BILDEN EINER KONTAKTSTRUKTUR EINER GATE-STRUKTUR

Es wird ein Verfahren zum Bilden einer Kontaktstruktur einer Gate-Struktur bereitgestellt. In dem Verfahren werden eine Oxidationsschicht und eine erste Seitenwandschicht, die zwischen einem ersten Metall-Gate und einem zweiten Metall-Gate angeordnet ist, geätzt, um eine darunterliegende Siliziumträgerschicht freizulegen. Ein Silizidabschnitt, definiert durch ein Kontaktprofil, wird im freigelegten Abschnitt der Siliziumträgerschicht abgeschieden. Eine zweite Seitenwandschicht, die im Wesentlichen die erste Seitenwandschicht bedeckt und zumindest teilweise den Silizidabschnitt bedeckt, wird nach dem Abscheiden des Silizidabschnitts gebildet. Eine Metallkleberschicht wird um das erste Metall-Gate und das zweite Metall-Gate abgeschieden, die einen Graben über dem Silizidabschnitt definiert. Ein Metallstecker wird innerhalb des Grabens abgeschieden.

Method of forming contact structure of gate structure

A method of forming a contact structure of a gate structure is provided. In the method, an oxidation layer and a first sidewall layer disposed between a first metal gate and a second metal gate are etched to expose an underlying silicon substrate. A silicide portion defined by a contact profile is deposited in the exposed portion of the silicon substrate. A second sidewall layer substantially covers the first sidewall layer and at least partially covering the silicide portion is formed after depositing the silicide portion. A metal glue layer is deposited around the first metal gate and the second metal gate defining a trench above the silicide portion. A metal plug is deposited within the trench.

Method for forming self-aligned contact

A method for forming a self-aligned contact is provided. In an embodiment, a metal gate is formed on a substrate, and a gate spacer is formed adjacent the metal gate. A conductive plug is formed over the substrate, with the gate spacer disposed between the metal gate and the conductive plug. The metal gate and the conductive plug are recessed. A first dielectric layer is deposited over the gate spacer, over the metal gate, over the conductive plug, and along sidewalls of the metal gate. A first opening is formed in the first dielectric layer exposing the metal gate, and a second opening is formed in the first dielectric layer exposing the conductive plug. The first opening and the second opening are filled with a first conductive material.

Structure and method for overlay marks

A partially fabricated semiconductor device includes a semiconductor overlay structure. The semiconductor overlay structure includes a first gate stack structure over the semiconductor substrate, the first gate stack structure being configured as an overlay mark in an overlay region of the semiconductor substrate. The semiconductor overlay structure further includes a doped region in the semiconductor substrate surrounding the first gate stack structure. The doped region has a first dopant concentration greater than or equal to a second dopant concentration next to a second gate stack structure in a device region of the semiconductor substrate.

Verfahren zum Ausbilden von Gräben mit unterschiedlichen Tiefen

Ein Verfahren zur Herstellung einer Halbleitervorrichtung umfasst das Ausbilden einer ersten dielektrischen Schicht über einem Substrat, das eine Gate-Struktur aufweist, das Ausbilden eines ersten Grabens in der ersten dielektrischen Schicht, das Ausbilden von dielektrischen Abstandshaltern entlang Seitenwänden des ersten Grabens, das Entfernen eines Teils der dielektrischen Abstandshalter, um einen Teil der Seitenwände des ersten Graben freizulegen, das Ausbilden eines ersten Metallmerkmals in dem ersten Graben über dem weiteren Teil der dielektrischen Abstandshalter und entlang der freiliegenden Teile der Seitenwände des ersten Grabens, das Ausbilden einer zweiten dielektrischen Schicht über dem ersten Metallmerkmal und der Gate-Struktur und das Ausbilden eines zweiten Grabens durch die zweite dielektrische Schicht, um einen Teil des ersten Metallmerkmals freizulegen, und eines dritten Grabens durch die zweite dielektrische Schicht und die erste dielektrische Schicht in dem gleichen Ätzverfahren ...

METHOD AND APPARATUS FOR CLEANING A SUBSTRATE

A method for photolithography processing includes forming a photoresist layer on a surface of a substrate, baking the substrate to remove solvents from the photoresist layer, cleaning an edge of the substrate with a tape, and exposing the photoresist layer with radiation energy. The tape includes a cleaning material. The tape is positioned proximate to or in contact with the edge of the substrate while the substrate is rotating.

Halbleitervorrichtung und Verfahren zum Herstellen der Halbleitervorrichtung

Es wird ein Verfahren zum Herstellen einer Halbleitervorrichtung bereitgestellt. Das Verfahren beinhaltet die folgenden Arbeitsabläufe: Bereitstellen eines ersten leitenden Abschnitts, eines zweiten leitenden Abschnitts und eines dritten leitenden Abschnitts über einer Trägerschicht; Bilden einer dielektrischen Schicht über dem ersten leitenden Abschnitt, dem zweiten leitenden Abschnitt und dem dritten leitenden Abschnitt; Bilden einer Hochohmwiderstandsschicht über dem ersten leitenden Abschnitt; Bilden einer Oxidschicht über der Hochohmwiderstandsschicht und der dielektrischen Schicht; Strukturieren der dielektrischen Schicht und der Oxidschicht durch Verwendung der Hochohmwiderstandsschicht als eine Sperrschicht, um eine erste Vertiefung zu bilden, um den zweiten leitenden Abschnitt und den dritten leitenden Abschnitt freizulegen und ein Freilegen des ersten leitenden Abschnitts zu verhindern; und Bilden einer Steckerschicht in der ersten Vertiefung, um den zweiten leitenden Abschnitt und den dritten leitenden Abschnitt zu verbinden.

Semiconductor arrangement and formation thereof

一種半導體配置及其形成方法被描述。一種半導體配置包括一第三金屬連接，其與一第一主動區域中的一第一金屬連接及一第二主動區域中的一第二金屬連接接觸，並位於第一主動區域和第二主動區域之間的一淺溝槽隔離(STI)區域之上。一種半導體配置的形成方法包括形成一第一開口於第一金屬連接、淺溝槽隔離(STI)區域、及第二金屬連接之上，並形成第三金屬連接於第一開口中。形成第三金屬連接於第一金屬連接與第二金屬連接之上減緩RC耦合(RC coupling)。

Halbleitervorrichtung und Ausbildung

Es ist eine Halbleitervorrichtung und ein Ausbildungsverfahren vorgesehen. Eine Halbleitervorrichtung umfasst einen ersten aktiven Bereich benachbart zu einer ersten Seite eines Grabenisolierungs-(STI)-Bereichs. Der erste aktive Bereich umfasst einen ersten proximalen Grat, der eine erste proximale Grathöhe aufweist, benachbart zu dem STI-Bereich und einen ersten distalen Grat, der eine erste distale Grathöhe aufweist, benachbart zu dem ersten proximalen Grat, wobei die erste proximale Grathöhe kleiner als die erste distale Grathöhe ist. Der STI-Bereich umfasst ein Oxid, wobei das Oxid ein Oxidvolumen aufweist, wobei das Oxidvolumen umgekehrt proportional zu der ersten proximalen Grathöhe ist. Ein Ausbildungsverfahren umfasst das Ausbilden eines ersten proximalen Grats mit einer ersten proximalen Grathöhe, die kleiner als eine erste distale Grathöhe eines ersten distalen Grats ist, so dass der erste proximale Grat zwischen dem ersten distalen Grat und dem STI-Bereich angeordnet ist.

LITHOGRAPHY METHOD AND APPARATUS FOR SEMICONDUCTOR DEVICE FABRICATION

Provided is a lithography system operation to include a first aperture or a second aperture. Each of the first and second apertures has two pairs of radiation-transmitting regions where one pair of radiation-transmitting regions are larger than a second pair. For an aperture, each pair of radiation-transmitting regions are on different diametrical axis. In an embodiment, one aperture is used for x-dipole illumination and the second aperture is used for y-dipole illumination.

Semiconductor arrangement and formation thereof

A semiconductor arrangement and method of formation are provided herein. A semiconductor arrangement includes a metal connect in contact with a first active region and a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes recessing the metal connect over the STI region to form a recessed portion of the metal connect. Forming the recessed portion of the metal connect in contact with the first active region and the second active region mitigates RC coupling, such that a first gate is formed closer to a second gate, thus reducing a size of a chip on which the recessed portion is located.

Novel photoresist material and photolithography processes

Semiconductor device and formation thereof

A semiconductor device and method of formation are provided herein. A semiconductor device includes a first active region adjacent a first side of a shallow trench isolation (STI) region. The first active region including a first proximal fin having a first proximal fin height adjacent the STI region, and a first distal fin having a first distal fin height adjacent the first proximal fin, the first proximal fin height less than the first distal fin height. The STI region includes oxide, the oxide having an oxide volume, where the oxide volume is inversely proportional to the first proximal fin height. A method of formation includes forming a first proximal fin with a first proximal fin height less than a first distal fin height of a first distal fin, such that the first proximal fin is situated between the first distal fin and an STI region.

Cross quadrupole double lithography method and apparatus for semiconductor device fabrication using two apertures

Provided is a lithography system operation to include a first aperture or a second aperture. Each of the first and second apertures has two pairs of radiation-transmitting regions where one pair of radiation-transmitting regions are larger than a second pair. For an aperture, each pair of radiation-transmitting regions are on different diametrical axis. In an embodiment, one aperture is used for x-dipole illumination and the second aperture is used for y-dipole illumination.

Exposure apparatus and method for photolithography process

Provided is an exposure apparatus including a variable focusing device. The variable focusing device may include a transparent membrane that may be deformed in the presence of an electric field. The deformation of the transparent membrane may allow the focus length of a radiation beam to be modified. In an embodiment, the variable focusing device may be modulated such that a radiation beam having a first focus length is provided for a first position on an exposure target and a radiation beam having a second focus length is provided for a second position on the exposure target. A method and computer-readable medium are also provided.

Photoresist materials and photolithography processes

A lithography apparatus generates a tunable magnetic field to facilitate processing of photoresist. The lithography apparatus includes a chamber and a substrate stage in the chamber operable to hold a substrate. A magnetic module provides a magnetic field to the substrate on the substrate stage. The magnetic module is configured to provide the magnetic field in a tunable and alternating configuration with respect to its magnitude and frequency. The magnetic field is provided to have a gradient in magnitude along a Z-axis that is perpendicular to the substrate stage to cause magnetically-charged particles disposed over the substrate stage to move up and down along the Z-axis. The lithography apparatus also includes a radiation energy source and an objective lens configured to receive radiation energy from the radiation energy source and direct the radiation energy toward the substrate positioned on the substrate stage.

MASK-LESS DUAL SILICIDE PROCESS

A method of forming a semiconductor device is provided. The method includes forming a mask layer, such as an oxidized layer, over first source/drain regions in a first device region. A dielectric layer, such as an interlayer dielectric layer, is formed and patterned to expose the first source/drain regions and second source/drain regions in a second device region. A silicide treatment is performed on the second source/drain regions while the mask layer protects the first source/drain regions. The mask layer is then removed and a silicide treatment is performed on the first source/drain regions. 1. A method of forming a semiconductor device , the method comprising:forming a first gate stack in a first device region of a substrate and a second gate stack in a second device region of the substrate, first source/drain regions being on opposing sides of the first gate stack, second source/drain regions being on opposing sides of the second gate stack;oxidizing the first source/drain regions, thereby forming a mask layer along a surface of the first source/drain regions;forming a patterned dielectric layer over the first device region and the second device region, the first source/drain regions and the second source/drain regions being exposed through the patterned dielectric layer;forming a second silicide layer over the second source/drain regions;removing the mask layer; andforming a first silicide layer over the first source/drain regions.2. The method of claim 1 , the forming the mask layer comprises:forming one or more first masking layers over the first device region and the second device region; andpatterning the first masking layers in the first device region to form first spacers alongside the first gate stack.3. The method of claim 1 , wherein the oxidizing comprises implanting oxygen.4. The method of claim 1 , wherein the first gate stack and the second gate stack are dummy gate stacks.5. The method of claim 1 , further comprising removing the first gate stack ...

Structure and method for alignment marks

The alignment mark and method for making the same are described. In one embodiment, a semiconductor structure includes a plurality of gate stacks formed on the semiconductor substrate and configured as an alignment mark; doped features formed in the semiconductor substrate and disposed on sides of each of the plurality of gate stacks; and channel regions underlying the plurality of gate stacks and free of channel dopant.

Semiconductor Device with Self-Aligned Contact

Self-aligned contacts are provided. In an embodiment the self-aligned contacts are formed by partially removing a first dielectric material from adjacent to a gate electrode and fully removing a second dielectric material from adjacent to the gate electrode. A conductive material is deposited into the regions of the removed first dielectric material and the second dielectric material, and the conductive material and metal gates are recessed below a spacer. A dielectric layer is deposited over the recessed conductive material and the recessed metal gates, and the self-aligned contacts are formed through the dielectric layer. 1. A method of manufacturing a semiconductor device , the method comprising:providing a metal gate with a first spacer on a first side of the metal gate and a second spacer on a second side of the metal gate, wherein a first portion of a dielectric material is located in a first region adjacent to the first spacer and a second portion of the dielectric material is located in a second region adjacent to the second spacer;fully removing the first portion of the dielectric material from the first region;partially removing the second portion of the dielectric material from the second region, the partially removing the second portion leaving a third portion of the dielectric material;forming a conductive material over the third portion of the dielectric material and within the first region;recessing the conductive material and the metal gate from a top surface of the first spacer and the second spacer;forming a first dielectric layer conformally over the conductive material, the first spacer, and the second spacer after the recessing the conductive material;forming a first contact through the first dielectric layer and in contact with the conductive material; andforming a second contact through the first dielectric layer and in contact with the metal gate.2. The method of claim 1 , wherein the forming the first contact further comprises:forming a ...

NOVEL PHOTORESIST MATERIALS AND PHOTOLITHOGRAPHY PROCESS

A material for use in lithography processing includes a polymer that turns soluble to a base solution in response to reaction with acid and a plurality of magnetically amplified generators (MAGs) each having a magnetic element and each decomposing to form acid bonded with the magnetic element in response to radiation energy.

Photoresist materials and photolithography process

A material for use in lithography processing includes a polymer that turns soluble to a base solution in response to reaction with acid and a plurality of magnetically amplified generators (MAGs) each having a magnetic element and each decomposing to form acid bonded with the magnetic element in response to radiation energy.

Method of Forming Trenches with Different Depths

A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure. 1. A device comprising:a gate structure disposed over a substrate;a first dielectric layer disposed over the substrate, including and over the gate structure;a first dielectric spacer disposed along a first sidewall of the first dielectric layer, wherein the first dielectric spacer and the substrate are spaced apart from each other;a first metal feature disposed along the first dielectric spacer in the first dielectric layer, with at least a portion of the first metal feature being disposed over the first dielectric spacer;a second dielectric spacer disposed along a second sidewall of the first dielectric layer, the second sidewall opposing the first sidewall of the first dielectric layer; anda second metal feature disposed along the second dielectric spacer in the first dielectric layer, wherein no portion of the second metal feature is disposed over the first dielectric spacer.2. The device of claim 1 , wherein the first metal feature physically contacts the first sidewall of the first dielectric layer claim 1 , andwherein the second metal feature is prevented from ...

SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF

A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.

Mechanisms for semiconductor device structure

Embodiments of mechanisms of a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a metal gate structure formed over the substrate. The semiconductor device structure further includes a funnel shaped hard mask structure formed over the metal gate structure. Formation of voids, which tend to be formed in a rectangular hard mask structure, is prevented. In addition, formation of a self-aligned contact in the semiconductor device becomes easier, and risks of shortage between the contact and a metal gate structure in the semiconductor device decreased. In addition, a method for forming the semiconductor device structure is also provided. The method may include a gate last process.

STRUCTURE AND METHOD FOR OVERLAY MARKS

The overlay mark and method for making the same are described. In one embodiment, a semiconductor overlay structure includes gate stack structures formed on the semiconductor substrate and configured as an overlay mark, and a doped semiconductor substrate disposed on both sides of the gate stack structure that includes at least as much dopant as the semiconductor substrate adjacent to the gate stack structure in a device region. The doped semiconductor substrate is formed by at least three ion implantation steps.

Overlay mark assistant feature

A method and apparatus for alignment are disclosed. An exemplary apparatus includes a substrate having an alignment region; an alignment feature in the alignment region of the substrate; and a dummy feature disposed within the alignment feature. A dimension of the dummy feature is less than a resolution of an alignment mark detector.

Integrated circuit device and the manufacturing method thereof

The invention provides an integrated circuit device and the manufacturing method thereof. An exemplary apparatus includes a substrate having an alignment region; an alignment feature in the alignment region of the substrate; and a dummy feature disposed within the alignment feature. A dimension of the dummy feature is less than a resolution of an alignment mark detector.

Method of forming trenches with different depths

A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure.

Mask-less dual silicide process

A method of forming a semiconductor device is provided. The method includes forming a mask layer, such as an oxidized layer, over first source/drain regions in a first device region. A dielectric layer, such as an interlayer dielectric layer, is formed and patterned to expose the first source/drain regions and second source/drain regions in a second device region. A silicide treatment is performed on the second source/drain regions while the mask layer protects the first source/drain regions. The mask layer is then removed and a silicide treatment is performed on the first source/drain regions.

SEMICONDUCTOR DEVICE AND FORMATION THEREOF

A semiconductor device and method of formation are provided herein. A semiconductor device includes a first active region adjacent a first side of a shallow trench isolation (STI) region. The first active region including a first proximal fin having a first proximal fin height adjacent the STI region, and a first distal fin having a first distal fin height adjacent the first proximal fin, the first proximal fin height less than the first distal fin height. The STI region includes oxide, the oxide having an oxide volume, where the oxide volume is inversely proportional to the first proximal fin height. A method of formation includes forming a first proximal fin with a first proximal fin height less than a first distal fin height of a first distal fin, such that the first proximal fin is situated between the first distal fin and an STI region.

Semiconductor device having a carbon containing insulation layer formed under the source/drain

A semiconductor arrangement and method of formation are provided herein. A semiconductor arrangement includes a metal connect in contact with a first active region and a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes recessing the metal connect over the STI region to form a recessed portion of the metal connect. Forming the recessed portion of the metal connect in contact with the first active region and the second active region mitigates RC coupling, such that a first gate is formed closer to a second gate, thus reducing a size of a chip on which the recessed portion is located.

Semiconductor arrangement and formation thereof

A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.

Semiconductor device and method for manufacturing semiconductor device

A method for manufacturing semiconductor device is provided. The method includes the following operations: providing a first conductive portion, a second conductive portion and a third conductive portion over a substrate; forming a dielectric layer over the first conductive portion, the second conductive portion, and the third conductive portion; forming a high-resistance layer over the first conductive portion; forming an oxide layer over the high-resistance layer and the dielectric layer; patterning the dielectric layer and the oxide layer by using the high-resistance layer as a blocking layer to form a first recess to expose the second conductive portion and the third conductive portion and to prevent the first conductive portion from exposure; and forming a plug layer in the first recess to connect the second conductive portion and the third conductive portion.

INTEGRATED CIRCUIT STRUCTURE WITH THINNED CONTACT

Embodiments of mechanism for an integrated circuit (IC) structure are provided. The IC structure includes a substrate including a first diffusion region, a second diffusion region, and an isolation structure separating the first diffusion region and the second diffusion region. The IC structure further includes a gate structure formed over the substrate, and the gate structure extends from the first diffusion region to the second diffusion region. The IC structure further includes a contact formed over the substrate, and the contact includes a wide portion over the first diffusion region and the second diffusion region and a thin portion over the isolation structure.

Semiconductor device and formation thereof

此處提供一種半導體裝置及形成方法。一種半導體裝置包括一第一主動區域鄰近一淺溝槽隔離(shallow trench isolation；STI)區域的第一側。第一主動區域包括一第一近端(proximal)鰭片具有一第一近端鰭片高度並鄰近淺溝槽隔離(STI)區域，及一第一遠端(distal)鰭片具有一第一遠端鰭片高度並鄰近第一近端鰭片，第一近端鰭片高度小於第一遠端鰭片高度。淺溝槽隔離(STI)區域包括氧化物，該氧化物具有一氧化物體積，其中氧化物體積與第一近端鰭片高度成反比。一種形成方法包括形成一第一近端鰭片，其具有一第一近端鰭片高度小於第一遠端鰭片的第一遠端鰭片高度，而使得第一近端鰭片位於第一遠端鰭片和一淺溝槽隔離(STI)區域之間。

NOVEL PHOTORESIST MATERIALS AND PHOTOLITHOGRAPHY PROCESSES

A material for use in lithography processing includes a polymer that turns soluble to a base solution in response to reaction with acid and a plurality of magnetically amplified generators (MAGs) each having a magnetic element and each decomposing to form acid bonded with the magnetic element in response to radiation energy.

Semiconductor device and method of fabricating the same

A method of fabricating a semiconductor device includes forming a first dielectric layer over a substrate that includes a gate structure, forming a first trench in the first dielectric layer, forming dielectric spacers along sidewalls of the first trench, removing a portion of the dielectric spacers to expose a portion of the sidewalls, forming a first metal feature in the first trench over the another portion of the dielectric spacers and along the exposed portions of the sidewalls of the first trench, forming a second dielectric layer over the first metal feature and the gate structure and forming a second trench through the second dielectric layer to expose a portion of the first metal feature and a third trench through the second dielectric layer and the first dielectric layer to expose a portion of the gate structure in the same etching process.

METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE WITH MASK STRUCTURE

Semiconductor structures and methods for forming the same are provided. The method includes forming a dummy gate structure and forming a spacer on a lower portion of a sidewall of the dummy gate structure and exposing an upper portion of the sidewall of the dummy gate structure. The method further includes forming a dielectric layer covering the upper portion of the sidewall of the dummy gate structure exposed by the spacer and removing the dummy gate structure to form a tube-shaped trench. The method further includes removing a portion of the dielectric layer to form a cone-shaped trench and forming a gate structure in a bottom portion of the tube-shaped trench. The method further includes forming a hard mask structure in the cone-shaped trench and an upper portion of the tube-shaped trench, and an interface between the hard mask structure and the dielectric layer overlaps the spacer.

SEMICONDUCTOR STRUCTURE WITH MASK STRUCTURE

Semiconductor structures are provided. The semiconductor structure includes a substrate and a metal gate structure formed over the substrate. The semiconductor structure further includes a sealing layer comprising an inner sidewall and an outermost sidewall. In addition, the inner sidewall is in direct contact with the metal gate structure and the outermost sidewall is away from the metal gate structure. The semiconductor structure further includes a mask structure formed over the metal gate structure. In addition, the mask structure has a straight sidewall over the metal gate structure and a sloped sidewall extending from the inner sidewall of the sealing layer and passing over the outmost sidewall of the sealing layer. 1. A semiconductor structure , comprising:a substrate;a metal gate structure formed over the substrate;a sealing layer comprising an inner sidewall and an outermost sidewall, wherein the inner sidewall is in direct contact with the metal gate structure and the outermost sidewall is away from the metal gate structure; anda mask structure formed over the metal gate structure, wherein the mask structure has a straight sidewall over the metal gate structure and a sloped sidewall extending from the inner sidewall of the sealing layer and passing over the outmost sidewall of the sealing layer.2. The semiconductor structure as claimed in claim 1 , wherein the straight sidewall is substantially aligned with a sidewall of the metal gate structure.3. The semiconductor structure as claimed in claim 1 , wherein the mask structure has a cone-shaped top portion and a tube-shaped bottom portion.4. The semiconductor structure as claimed in claim 3 , wherein an interface between the metal gate structure and the tube-shaped bottom portion is lower than a top portion of the sealing layer.5. The semiconductor structure as claimed in claim 1 , wherein a width of a top surface of the mask structure is greater than a sum of a width of the metal gate structure and a width ...

NOVEL PHOTORESIST MATERIALS AND PHOTOLITHOGRAPHY PROCESSES

A material for use in lithography processing includes a polymer that turns soluble to a base solution in response to reaction with acid and a plurality of magnetically amplified generators (MAGs) each having a magnetic element and each decomposing to form acid bonded with the magnetic element in response to radiation energy.

Integrated circuit structure with thinned contact

Embodiments of mechanism for an integrated circuit (IC) structure are provided. The IC structure includes a substrate including a first diffusion region, a second diffusion region, and an isolation structure separating the first diffusion region and the second diffusion region. The IC structure further includes a gate structure formed over the substrate, and the gate structure extends from the first diffusion region to the second diffusion region. The IC structure further includes a contact formed over the substrate, and the contact includes a wide portion over the first diffusion region and the second diffusion region and a thin portion over the isolation structure.

Method of Forming Trenches with Different Depths

A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure. 1. A method comprising:forming a first conductive feature and a second conductive feature on a substrate;forming a first interlayer dielectric layer over the first and second conductive features;forming a first trench and a second trench through the first interlayer dielectric layer;forming a first sidewall spacer along a first sidewall of the first interlayer dielectric layer that defines the first trench and a second sidewall spacer along a second sidewall of the first interlayer dielectric layer that defines the second trench;removing a first portion of the first sidewall spacer to expose a portion of the first sidewall of the first interlayer dielectric layer, wherein a second portion of the first sidewall spacer remains disposed along the first sidewall of the first interlayer dielectric layer after the removing of the first portion of the first sidewall spacer; andforming a first metal feature in the first trench and a second metal feature in the second trench, the first metal feature interfacing with the exposed portion of the first sidewall of the first ...

SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF

A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.

STRUCTURE AND METHOD FOR OVERLAY MARKS

A partially fabricated semiconductor device includes a semiconductor overlay structure. The semiconductor overlay structure includes a first gate stack structure over the semiconductor substrate, the first gate stack structure being configured as an overlay mark in an overlay region of the semiconductor substrate. The semiconductor overlay structure further includes a doped region in the semiconductor substrate surrounding the first gate stack structure. The doped region has a first dopant concentration greater than or equal to a second dopant concentration next to a second gate stack structure in a device region of the semiconductor substrate.

PHOTOLITHOGRAPHY PROCESS FOR SEMICONDUCTOR DEVICE

Provided is a non-transitory computer readable medium including instructions to generate a level sensor map and create a compensation map from the level sensor map. The level sensor map includes a first determination of a first height above a reference plane of a feature disposed on a semiconductor substrate, and a second determination of a second height above the reference plane of a second feature disposed on a semiconductor substrate. The first and second feature are in a single exposure field. The compensation map includes a determination of at least one parameter to be used during exposure of a single field during an exposure process for the semiconductor substrate. 1. A non-transitory computer readable medium , comprising computer-readable instructions to determine a photolithography parameter , the computer-readable instructions comprising instructions to:generate a level sensor map, wherein the level sensor map includes a first determination of a first height above a reference plane of a feature disposed on a semiconductor substrate, and a second determination of a second height above the reference plane of a second feature disposed on a semiconductor substrate, wherein the first and second feature are in a single exposure field; andcreate a compensation map based on generated level sensor map, wherein the compensation map includes a determination of at least one parameter to be used during exposure of a single field during an exposure process for the semiconductor substrate.2. The non-transitory computer readable medium of claim 1 , wherein the at least one parameter includes a determination of a first focus length for a first region of the semiconductor substrate and a determination of a second focus length for a second region of the semiconductor substrate claim 1 , wherein the first and second regions are within the single exposure field.3. The non-transitory computer readable medium of claim 1 , wherein the at least one parameter includes a ...

OVERLAY MARK ASSISTANT FEATURE

A method and apparatus for alignment are disclosed. An exemplary apparatus includes a substrate having an alignment region; an alignment feature in the alignment region of the substrate; and a dummy feature disposed within the alignment feature. A dimension of the dummy feature is less than a resolution of an alignment mark detector.

Semiconductor device and formation thereof

A semiconductor device and method of formation are provided herein. A semiconductor device includes a first active region adjacent a first side of a shallow trench isolation (STI) region. The first active region including a first proximal fin having a first proximal fin height adjacent the STI region, and a first distal fin having a first distal fin height adjacent the first proximal fin, the first proximal fin height less than the first distal fin height. The STI region includes oxide, the oxide having an oxide volume, where the oxide volume is inversely proportional to the first proximal fin height. A method of formation includes forming a first proximal fin with a first proximal fin height less than a first distal fin height of a first distal fin, such that the first proximal fin is situated between the first distal fin and an STI region.

Semiconductor device with self-aligned contact

Self-aligned contacts are provided. In an embodiment the self-aligned contacts are formed by partially removing a first dielectric material from adjacent to a gate electrode and fully removing a second dielectric material from adjacent to the gate electrode. A conductive material is deposited into the regions of the removed first dielectric material and the second dielectric material, and the conductive material and metal gates are recessed below a spacer. A dielectric layer is deposited over the recessed conductive material and the recessed metal gates, and the self-aligned contacts are formed through the dielectric layer.

Method of forming trenches with different depths

A method of fabricating a semiconductor device includes forming a first dielectric layer over a substrate that includes a gate structure, forming a first trench in the first dielectric layer, forming dielectric spacers along sidewalls of the first trench, removing a portion of the dielectric spacers to expose a portion of the sidewalls, forming a first metal feature in the first trench over the another portion of the dielectric spacers and along the exposed portions of the sidewalls of the first trench, forming a second dielectric layer over the first metal feature and the gate structure and forming a second trench through the second dielectric layer to expose a portion of the first metal feature and a third trench through the second dielectric layer and the first dielectric layer to expose a portion of the gate structure in the same etching process.

Method of forming contact structure of gate structure

A method of forming a contact structure of a gate structure is provided. In the method, an oxidation layer and a first sidewall layer disposed between a first metal gate and a second metal gate are etched to expose an underlying silicon substrate. A silicide portion defined by a contact profile is deposited in the exposed portion of the silicon substrate. A second sidewall layer substantially covers the first sidewall layer and at least partially covering the silicide portion is formed after depositing the silicide portion. A metal glue layer is deposited around the first metal gate and the second metal gate defining a trench above the silicide portion. A metal plug is deposited within the trench.

Semiconductor device and method of fabricating the same

METHOD FOR FORMING INTEGRATED CIRCUIT STRUCTURE WITH THINNED CONTACT

Methods for forming integrated circuit structures are provided. The method includes providing a substrate including a first diffusion region, a second diffusion region, and an isolation structure separating the first diffusion region and the second diffusion region. The method further includes forming a gate structure over the substrate and forming an inter-layer dielectric (ILD) layer over the substrate. The method further includes forming a cutting mask over a portion of the gate structure over the isolation structure, and the cutting mask has an extending portion covering a portion of the ILD layer. The method further includes forming a photoresist layer having an opening, and a portion of the extending portion of the cutting mask is exposed by the opening. The method further includes etching the ILD layer through the opening to form a trench and filling the trench with a conductive material to form a contact. 1. A method for forming an integrated circuit (IC) structure , comprising:providing a substrate comprising a first diffusion region, a second diffusion region, and an isolation structure separating the first diffusion region and the second diffusion region;forming a gate structure over the substrate;forming an inter-layer dielectric (ILD) layer adjacent to the gate structure over the substrate;forming a cutting mask over a portion of the gate structure over the isolation structure, wherein the cutting mask has an extending portion covering a portion of the ILD layer over the isolation structure;forming a photoresist layer having an opening, wherein a portion of the extending portion of the cutting mask is exposed by the opening;etching the ILD layer through the opening to form a trench; andfilling the trench with a conductive material to form a contact.2. The method for forming the IC structure as claimed in claim 1 , wherein when the ILD layer is etched through the opening to form the trench claim 1 , the portion of the ILD layer covered by the extending ...

Structure and Method for Alignment Marks

The alignment mark and method for making the same are described. In one embodiment, a semiconductor structure includes a plurality of gate stacks formed on the semiconductor substrate and configured as an alignment mark; doped features formed in the semiconductor substrate and disposed on sides of each of the plurality of gate stacks; and channel regions underlying the plurality of gate stacks and free of channel dopant. 1. A method comprising:forming a patterned material layer over a substrate;performing a first ion implantation to a device region of the substrate while an alignment region of the semiconductor substrate is covered by the patterned material layer;after performing the first ion implantation, forming a first gate stack in the device region and a second gate stack in the alignment region; andafter forming the first gate stack in the device region and the second gate stack in the alignment region, performing a second ion implantation in the alignment region to a first portion of the substrate proximate the second gate to alter the refractive index of the first portion of the substrate.2. The method of claim 1 , wherein the performing of the first ion implantation to the device region of the substrate forms a doped region in the substrate claim 1 , andwherein the forming of the first gate stack in the device region includes forming the first gate stack directly over the doped region such that the first gate stack interfaces with the doped region.3. The method of claim 2 , wherein the doped region includes a dopant claim 2 , andwherein the forming of the second gate stack in the alignment region includes forming the second gate stack directly over a second portion of the substrate that is free of the dopant.4. The method of claim 1 , wherein the performing of the second ion implantation in the alignment region to the first portion of the substrate proximate the second gate stack to alter the refractive index of the first portion of the substrate includes ...

Structure and method for alignment marks

The alignment mark and method for making the same are described. In one embodiment, a semiconductor structure includes a plurality of gate stacks formed on the semiconductor substrate and configured as an alignment mark; doped features formed in the semiconductor substrate and disposed on sides of each of the plurality of gate stacks; and channel regions underlying the plurality of gate stacks and free of channel dopant.

METHOD OF FORMING TRENCHES WITH DIFFERENT DEPTHS

A method of fabricating a semiconductor device includes forming a first dielectric layer over a substrate that includes a gate structure, forming a first trench in the first dielectric layer, forming dielectric spacers along sidewalls of the first trench, removing a portion of the dielectric spacers to expose a portion of the sidewalls, forming a first metal feature in the first trench over the another portion of the dielectric spacers and along the exposed portions of the sidewalls of the first trench, forming a second dielectric layer over the first metal feature and the gate structure and forming a second trench through the second dielectric layer to expose a portion of the first metal feature and a third trench through the second dielectric layer and the first dielectric layer to expose a portion of the gate structure in the same etching process.

Structure and Method for Alignment Marks

The alignment mark and method for making the same are described. In one embodiment, a semiconductor structure includes a plurality of gate stacks formed on the semiconductor substrate and configured as an alignment mark; doped features formed in the semiconductor substrate and disposed on sides of each of the plurality of gate stacks; and channel regions underlying the plurality of gate stacks and free of channel dopant.

Overlay mark assistant feature

A method and apparatus for alignment are disclosed. An exemplary apparatus includes a substrate having an alignment region; an alignment feature in the alignment region of the substrate; and a dummy feature disposed within the alignment feature. A dimension of the dummy feature is less than a resolution of an alignment mark detector.

MECHANISMS FOR SEMICONDUCTOR DEVICE STRUCTURE

Embodiments of mechanisms of a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a metal gate structure formed over the substrate. The semiconductor device structure further includes a funnel shaped hard mask structure formed over the metal gate structure. In addition, a method for forming the semiconductor device structure is also provided. 1. A semiconductor device structure , comprising:a substrate;a metal gate structure formed over the substrate; anda funnel shaped hard mask structure formed over the metal gate structure.2. The semiconductor device structure as claimed in claim 1 , further comprising:a contact formed over the substrate, wherein a sidewall of the contact is adjacent to an edge of a top surface of the funnel shaped hard mask structure.3. The semiconductor device structure as claimed in claim 1 , wherein the funnel shaped hard mask structure has a cone-shaped top portion and a tube-shaped bottom portion.4. The semiconductor device structure as claimed in claim 1 , wherein a top surface of the funnel shaped hard mask structure has a first width and a bottom surface of the funnel shaped hard mask structure has a second width smaller than the first width.5. The semiconductor device structure as claimed in claim 4 , wherein a ratio of the first width to the second width is in a range from about 1.1 to about 5.6. The semiconductor device structure as claimed in claim 4 , wherein the first width is in a range from about 12 nm to about 200 nm.7. The semiconductor device structure as claimed in claim 4 , wherein the second width is in a range from about 10 nm to about 200 nm.8. The semiconductor device structure as claimed in claim 1 , wherein a thickness of the funnel shaped hard mask structure is in a range from about 10 nm to about 50 nm.9. The semiconductor device structure as claimed in claim 1 , wherein an angle between a top surface and a sidewall of the funnel shaped hard mask structure is in a ...

Contact structure of gate structure

A method of forming a contact structure of a gate structure is provided. In the method, an oxidation layer and a first sidewall layer disposed between a first metal gate and a second metal gate are etched to expose an underlying silicon substrate. A silicide portion defined by a contact profile is deposited in the exposed portion of the silicon substrate. A second sidewall layer substantially covers the first sidewall layer and at least partially covering the silicide portion is formed after depositing the silicide portion. A metal glue layer is deposited around the first metal gate and the second metal gate defining a trench above the silicide portion. A metal plug is deposited within the trench.

Semiconductor arrangement and formation thereof

A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.

Semiconductor device and method for manufacturing semiconductor device

A method for manufacturing semiconductor device is provided. The method includes the following operations: providing a first conductive portion, a second conductive portion and a third conductive portion over a substrate; forming a dielectric layer over the first conductive portion, the second conductive portion, and the third conductive portion; forming a high-resistance layer over the first conductive portion; forming an oxide layer over the high-resistance layer and the dielectric layer; patterning the dielectric layer and the oxide layer by using the high-resistance layer as a blocking layer to form a first recess to expose the second conductive portion and the third conductive portion and to prevent the first conductive portion from exposure; and forming a plug layer in the first recess to connect the second conductive portion and the third conductive portion.

Semiconductor arrangement and formation thereof

A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.

Photoresist materials and photolithography processes

A material for use in lithography processing includes a polymer that turns soluble to a base solution in response to reaction with acid and a plurality of magnetically amplified generators (MAGs) each having a magnetic element and each decomposing to form acid bonded with the magnetic element in response to radiation energy.

Structure and method for alignment marks

The alignment mark and method for making the same are described. In one embodiment, a semiconductor structure includes a plurality of gate stacks formed on the semiconductor substrate and configured as an alignment mark; doped features formed in the semiconductor substrate and disposed on sides of each of the plurality of gate stacks; and channel regions underlying the plurality of gate stacks and free of channel dopant.

MECHANISMS FOR SEMICONDUCTOR DEVICE STRUCTURE

Semiconductor device structures and methods for forming the same are provided. The method for forming a semiconductor device structure includes forming a dummy gate structure over a substrate and forming a dielectric layer over the substrate around the dummy gate structure. The method for forming a semiconductor device structure further includes removing the dummy gate structure and removing a portion of the dielectric layer to form a funnel shaped trench. The method for forming a semiconductor device structure further includes forming a gate structure in a bottom portion of the funnel shaped trench and filling a hard mask material in a top portion of the funnel shaped trench to form a funnel shaped hard mask structure. 1. A method for forming a semiconductor device structure , comprising:forming a dummy gate structure over a substrate;forming a dielectric layer over the substrate around the dummy gate structure;removing the dummy gate structure;removing a portion of the dielectric layer to form a funnel shaped trench;forming a gate structure in a bottom portion of the funnel shaped trench; andfilling a hard mask material in a top portion of the funnel shaped trench to form a funnel shaped hard mask structure.2. The method for forming a semiconductor device structure as claimed in claim 1 , wherein the funnel shaped trench has a cone-shaped top portion and a tube-shaped bottom portion.3. The method for forming a semiconductor device structure as claimed in claim 2 , further comprising:forming a spacer on a bottom portion of a sidewall of the dummy gate before the dielectric layer is formed,wherein a top portion of the dielectric layer is formed over the spacer and a bottom portion of the dielectric layer is formed around the spacer, and a portion the top portion of the dielectric layer is removed to form the cone-shape top portion of the funnel shaped trench.4. The method for forming a semiconductor device structure as claimed in claim 3 , wherein the portion of the ...

Semiconductor arrangement and formation thereof

A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.

DOUBLE DIPOLE LITHOGRAPHY METHOD FOR SEMICONDUCTOR DEVICE FABRICATION

A method of photolithography including coupling a first aperture to a lithography system, then performing a first illumination process to form a first pattern on a layer of a substrate using the first aperture, thereafter coupling a second aperture to the lithography system, and performing a second illumination process to form a second pattern on the layer of the substrate using the second aperture. The first aperture includes a first pair and a second pair of radiation-transmitting regions. The second aperture includes a second plate having a third pair and a fourth pair of radiation-transmitting regions. 1. A method , comprising:using a first aperture plate to expose a first pattern on a layer of a substrate, wherein the first aperture plate has a first pair of radiation-transmitting regions disposed at a first pole angle and a second pair of radiation-transmitting regions along a second pole angle, wherein the first pole angle is different than the second pole angle; andthereafter, using a second aperture plate, complementary to the first aperture plate, to expose a second pattern on the layer of the substrate, wherein the second aperture plate has a third pair of radiation-transmitting regions and a fourth pair of radiation-transmitting regions, wherein the third pair of radiation-transmitting regions are along a third pole angle and the fourth pair of radiation-transmitting regions are along a fourth pole angle, wherein the third pole angle is different than the fourth pole angle.2. The method claim 1 , wherein an optical axis is perpendicular to the first claim 1 , second claim 1 , third claim 1 , and fourth pole angles.3. The method of claim 1 , wherein at least one of the first claim 1 , second claim 1 , third claim 1 , and fourth pair of radiation-transmitting regions are oval in shape.4. The method of claim 1 , wherein the first pole angle and the fourth pole angle are located at a same position relative to an optical axis of the lithography system.5. The ...

MANUFACTURING METHOD OF A TEST STRIP

The present invention discloses a manufacturing method of a test strip, which comprises making a first semi-finished product and a second semi-finished product. The manufacturing process of the first semi-finished product comprises: providing a substrate, forming a plurality of electrodes on the substrate, forming a supporting layer with a plurality of channels on the substrate, and providing a reaction material to fill in the channels. The manufacturing process of the second semi-finished product comprises: providing a lid, forming a hydrophilic layer on a first surface of the lid, forming an adhesive layer on the first surface without the hydrophilic layer. Thereafter, a test strip assembly is formed by adhering the channels of the first semi-finished product to the hydrophilic layer of the second semi-finished product. Finally, a plurality of test strips are produced by cutting the test strip assembly along a first axis of the substrate. 1. A manufacturing method of a test strip for a fluid sample , comprising steps of: providing a substrate defined by a first axis and a second axis being orthogonal to each other;', 'forming a plurality of electrodes on the substrate electrodes being disposed in parallel with the second axis;', 'directly forming a supporting layer on the substrate having the electrodes with the supporting layer including a plurality of fluid channels disposed in array pattern along the first axis and correspondingly on the electrodes, and with a thickness of the supporting layer being at least 30 micrometers; and', 'filling the fluid channels with a reactive material;, 'making a first semi-finished product by steps of providing a lid having a first surface and a second surface and being defined by a third axis and a fourth axis with the first surface being opposite to the second surface and the third axis being orthogonal to the fourth axis;', 'forming a hydrophilic layer on the first surface of the lid; and', 'forming an adhering layer on the ...

SELF-LOCKING AND POSITIONING DEVICE FOR DENTAL BRACE

A self-locking and positioning device for a dental brace, comprising: a brace main body, an elastic piece, and an upper cover. Wherein, on the brace main body is provided with a track and a fixing slot, while on the elastic piece is provided with a positioning piece and a slot. The positioning piece is provided with a barb, while the upper cover slides and fixes into the brace main body through the track. Then, the barb of the positioning piece on the elastic piece will act against a block portion on bottom of said upper cover, to restrict movement of the upper cover, to lock automatically the upper cover into position. The dental brace is simple in construction and easy to assemble, hereby raising production efficiency and yield. 1. A self-locking and positioning device for a dental brace , comprising:a brace main body, on which is provided with a track and a fixing slot;an elastic piece, on which is provided a positioning piece and a slot; andan upper cover, to slide from said track into said brace main body to fix thereon, and fasten said elastic piece.2. The self-locking and positioning device for a dental brace as claimed in claim 1 , wherein orientations of said track and said fixing slot are perpendicular to each other.3. The self-locking and positioning device for a dental brace as claimed in claim 1 , wherein on both sides of said upper cover are each provided with a long strip shaped protrusion portion claim 1 , on both sides inside said track of said brace main body is provided with an indent portion claim 1 , so that said two protrusion portions of said upper cover slide into said brace main body along said two indent portions of said track.4. The self-locking and positioning device for a dental brace as claimed in claim 3 , wherein below said two indent portions is an receiving space claim 3 , and said positioning piece of said elastic piece is placed in said receiving space claim 3 , then claim 3 , said upper cover is slid into said track claim 3 , so ...

OVERLAY MARK ASSISTANT FEATURE

A method and apparatus for alignment are disclosed. An exemplary apparatus includes a substrate having an alignment region; an alignment feature in the alignment region of the substrate; and a dummy feature disposed within the alignment feature. A dimension of the dummy feature is less than a resolution of an alignment mark detector. 1. A method comprising:providing a substrate having an alignment region;forming an alignment feature in the alignment region of the substrate; andforming a dummy feature in the alignment region of the substrate, such that the dummy feature is formed within the alignment feature, and wherein a dimension of the dummy feature is less than a resolution of an alignment mark detector.2. The method of wherein the forming the alignment feature comprises forming an outer box of a box-in-box alignment pattern in a material layer over the substrate.3. The method of wherein the forming the dummy feature claim 2 , such that the dummy feature is formed within the alignment feature claim 2 , comprises forming the dummy feature within an open region of the outer box.4. The method of further comprising performing a chemical mechanical polishing process.5. The method of further comprising forming a semiconductor device in a device region of the substrate.6. The method of wherein the forming the alignment feature claim 5 , dummy feature claim 5 , and semiconductor device comprises:forming a polysilicon (poly) layer over the substrate;patterning the poly layer to form a poly gate stack as the alignment feature, a dummy poly gate stack as the dummy feature, and another poly gate stack as the semiconductor device;forming an inter-level dielectric (ILD) layer over the substrate; andperforming a chemical mechanical polishing (CMP) process to planarize the ILD layer.7. The method of wherein the forming the alignment feature claim 5 , dummy feature claim 5 , and semiconductor device comprises:forming a material layer over the substrate;patterning the material ...

Semiconductor arrangement and formation thereof

A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.

Self-Aligned Contact and Method

Self-aligned contacts are provided. In an embodiment the self-aligned contacts are formed by partially removing a first dielectric material from adjacent to a gate electrode and fully removing a second dielectric material from adjacent to the gate electrode. A conductive material is deposited into the regions of the removed first dielectric material and the second dielectric material, and the conductive material and metal gates are recessed below a spacer. A dielectric layer is deposited over the recessed conductive material and the recessed metal gates, and the self-aligned contacts are formed through the dielectric layer.

Method of Forming Trenches with Different Depths

A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure. 1. A device comprising:a gate structure disposed over a substrate;a first dielectric layer disposed over the substrate, including and over the gate structure;a dielectric spacer;a first metal feature disposed in the first dielectric layer, with at least a portion of the first metal feature being disposed over the dielectric spacer;a second dielectric layer disposed over the first dielectric layer, including over the first metal feature;a second metal feature extending through the second dielectric layer to physically contact with the first metal feature; anda third metal feature extending through the second dielectric layer and the first dielectric layer to physically contact the gate structure.2. The device of claim 1 , wherein the first metal feature has an upper portion having a first width and a lower portion having a second width that is different than the first width.3. The device of claim 1 ,wherein the dielectric spacer includes a first dielectric spacer portion and a second dielectric spacer portion positioned on opposite sides of a first trench, andwherein ...

Semiconductor arrangement and formation thereof

A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.

Contact Structure of Gate Structure

A method of forming a contact structure of a gate structure is provided. In the method, an oxidation layer and a first sidewall layer disposed between a first metal gate and a second metal gate are etched to expose an underlying silicon substrate. A silicide portion defined by a contact profile is deposited in the exposed portion of the silicon substrate. A second sidewall layer substantially covers the first sidewall layer and at least partially covering the silicide portion is formed after depositing the silicide portion. A metal glue layer is deposited around the first metal gate and the second metal gate defining a trench above the silicide portion. A metal plug is deposited within the trench.

Intersection speed deciding method and system thereof

An intersection speed deciding method includes a dataset obtaining and calculating step and a speed adjusting step. At least one of the vehicles expected to pass through one of the points is defined as the approaching vehicle, and a first arrival time of the approaching vehicle is obtained. Whether a preceding vehicle is on the host route is judged. If yes, a second arrival time of the preceding vehicle is obtained. Whether the host vehicle is expected to wait for a red light is judged. If yes, a red light duration is obtained. A time difference exists between a best arrival time and a corresponding expected arrival time, and each time difference is minimized based on the first arrival time, the second arrival time and the red time duration. A speed of the host vehicle is adjusted or remained based on the expected arrival times.

Automatic driving method and device able to diagnose decisions

An automatic driving method and device able to diagnose decisions is disclosed herein, wherein a vehicle body signal sensor detects vehicle body information, and an environment sensor detects traffic environment information. The information is transmitted to a central processor to generate a future driving track. The central processor examines whether the differences between the future driving track and the traffic environment information and the indexes of the future driving track meet tolerances. If no, the central processor transmits notification information to an automatic driving controller. If yes, the central processor transmits the future driving track to the automatic driving controller to make the automatic driving controller undertake automatic driving according to the future driving track. The present invention can automatically judge whether the future driving track generated by the central processor is within tolerances and determine whether the automatic driving track is safe.

Intelligent driving method for passing intersections based on support vector machine and intelligent driving system thereof

The intelligent driving method applied to a vehicle includes a support vector machine providing step in which the support vector machine is provided. The support vector machine has been trained by a training process. In the training process, a training dataset is provided to the support vector machine. The training dataset is obtained after an original dataset processed by a dimensionality reducing module and a time scaling module. The intelligent driving method includes a dataset processing step in which p features from an environment sensing unit are processed by the dimensionality reducing module and the time scaling module, and the processed dataset will be provided to the support vector machine. The intelligent driving method further includes a deciding step for providing a driving decision for the vehicle according to a classed result of the support vector machine.

Method of Forming Trenches with Different Depths

A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure. 1. A device comprising:a first dielectric layer disposed on a substrate;a first gate structure disposed within the first dielectric layer;a first dielectric spacer disposed on the first gate structure, the first dielectric spacer extending to a first height above the substrate;a second dielectric layer disposed over the substrate;a first conductive feature disposed in the second dielectric layer, the first conductive feature including a first portion having a first width and a second portion having a second width that is different than the first width; anda second dielectric spacer disposed on the first conductive feature without extending below the first height above the substrate.2. The device of claim 1 , further comprising a shallow trench isolation feature disposed in the substrate claim 1 , andwherein the gate structure is disposed over the shallow trench isolation feature.3. The device of claim 1 , wherein the first dielectric spacer interfaces with the first dielectric layer.4. The device of claim 1 , further comprising:a second gate structure disposed within ...

Semiconductor device and method for manufacturing semiconductor device

A method for manufacturing semiconductor device is provided. The method includes the following operations: providing a first conductive portion, a second conductive portion and a third conductive portion over a substrate; forming a dielectric layer over the first conductive portion, the second conductive portion, and the third conductive portion; forming a high-resistance layer over the first conductive portion; forming an oxide layer over the high-resistance layer and the dielectric layer; patterning the dielectric layer and the oxide layer by using the high-resistance layer as a blocking layer to form a first recess to expose the second conductive portion and the third conductive portion and to prevent the first conductive portion from exposure; and forming a plug layer in the first recess to connect the second conductive portion and the third conductive portion.

SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF

A semiconductor arrangement and method of formation are provided herein. A semiconductor arrangement includes a metal connect in contact with a first active region and a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes recessing the metal connect over the STI region to form a recessed portion of the metal connect. Forming the recessed portion of the metal connect in contact with the first active region and the second active region mitigates RC coupling, such that a first gate is formed closer to a second gate, thus reducing a size of a chip on which the recessed portion is located. 1. A semiconductor arrangement comprising:a first active region;a second active region;a shallow trench isolation (STI) region between the first active region and the second active region; anda metal connect over the first active region, the STI region and the second active region, and connected to the first active region and the second active region, such that a first unrecessed portion of the metal connect over the first active region has a first height, a recessed portion of the metal connect over the STI region has a second height and a second unrecessed portion of the metal connect over the second active region has a third height, the first height and the third height greater than the second height.2. The semiconductor arrangement of claim 1 , the first height substantially equal to the third height.3. The semiconductor arrangement of claim 1 , comprising a first gate adjacent a first side of the metal connect and a second gate adjacent a second side of the metal connect claim 1 , the first gate and the second gate over the first active region claim 1 , the STI region and the second active region and connected to the first active region and the second active region.4. The semiconductor arrangement of claim 3 , the first gate a first distance ...

Semiconductor device and formation thereof

A semiconductor device and method of formation are provided herein. A semiconductor device includes a first active region adjacent a first side of a shallow trench isolation (STI) region. The first active region including a first proximal fin having a first proximal fin height adjacent the STI region, and a first distal fin having a first distal fin height adjacent the first proximal fin, the first proximal fin height less than the first distal fin height. The STI region includes oxide, the oxide having an oxide volume, where the oxide volume is inversely proportional to the first proximal fin height. A method of formation includes forming a first proximal fin with a first proximal fin height less than a first distal fin height of a first distal fin, such that the first proximal fin is situated between the first distal fin and an STI region.

SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF

A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling. 1. A semiconductor arrangement comprising:a first active region;a second active region;a shallow trench isolation (STI) region between the first active region and the second active region;a first metal connect over the first active region and connected to the first active region;a second metal connect over the second active region and connected to the second active region; anda third metal connect over the first metal connect, the STI region and the second metal connect, and connected to the first metal connect and to the second metal connect such that the third metal connect connects the first metal connect to the second metal connect.2. The semiconductor arrangement of claim 1 , further comprising a gate adjacent the first metal connect and the second metal connect claim 1 , and over the first active region claim 1 , the second active region and the STI region.3. The semiconductor arrangement of claim 2 , further comprising a metal contact over the gate and adjacent the third metal connect.4. The semiconductor arrangement of claim 1 , the first metal connect having a third height claim 1 , the second metal connect having a fourth height claim 1 , the third height and the fourth height being substantially equal.5. The semiconductor arrangement of claim 4 , further comprising a gate ...

METHOD OF FORMING CONTACT STRUCTURE OF GATE STRUCTURE

A method of forming a contact structure of a gate structure is provided. In the method, an oxidation layer and a first sidewall layer disposed between a first metal gate and a second metal gate are etched to expose an underlying silicon substrate. A silicide portion defined by a contact profile is deposited in the exposed portion of the silicon substrate. A second sidewall layer substantially covers the first sidewall layer and at least partially covering the silicide portion is formed after depositing the silicide portion. A metal glue layer is deposited around the first metal gate and the second metal gate defining a trench above the silicide portion. A metal plug is deposited within the trench. 1. A method of forming a contact structure of a gate structure , comprising:etching an oxidation layer and a first sidewall layer disposed between a first metal gate and a second metal gate to expose an underlying silicon substrate;depositing a silicide portion defined by a contact profile in the exposed portion of the silicon substrate;forming a second sidewall layer substantially covering the first sidewall layer and at least partially covering the silicide portion after the depositing the silicide portion;depositing a metal glue layer around the first metal gate and the second metal gate defining a trench above the silicide portion; anddepositing a metal plug within the trench.2. The method of claim 1 , further comprising:performing a first chemical-mechanical polishing (CMP) process on the first metal gate, the second metal gate, the first sidewall layer, and the oxidation layer before the etching the oxidation layer and the first sidewall.3. The method of claim 1 , further comprising:performing a second CMP process on the metal plug, the metal glue layer, the first metal gate, the second metal gate, the first sidewall layer, and the second sidewall layer.4. The method of claim 1 , wherein the etching the oxidation layer and the first sidewall layer to expose the ...

Structure and Method for Alignment Marks

The alignment mark and method for making the same are described. In one embodiment, a semiconductor structure includes a plurality of gate stacks formed on the semiconductor substrate and configured as an alignment mark; doped features formed in the semiconductor substrate and disposed on sides of each of the plurality of gate stacks; and channel regions underlying the plurality of gate stacks and free of channel dopant. 1. A device comprising:a first gate stack disposed over a semiconductor substrate and configured as an alignment mark; anddoped feature disposed in the semiconductor substrate and associated with the first gate stack, wherein the doped feature has a refractive index of about 3.2. The device of claim 1 , wherein the doped feature includes a p-type dopant.3. The device of claim 1 , wherein the doped feature includes an n-type dopant.4. The device of claim 1 , further comprising a second gate stack disposed over the semiconductor substrate;a doped well feature formed of a well dopant disposed in the semiconductor substrate under the second gate stack; anda channel region disposed in the substrate under the first gate stack and free of the well dopant.5. The device of claim 1 , wherein the first gate stack includes a high-k dielectric layer and a polysilicon material layer disposed over the high-k dielectric layer.6. The device of claim 1 , wherein the first gate stack includes a high-k dielectric layer and a metal layer disposed over the high-k dielectric layer.7. The device of claim 6 , wherein the metal layer includes a n-type work function metal layer.8. The device of claim 6 , wherein the metal layer includes a p-type work function metal layer.9. A device comprising:a semiconductor substrate having a device region and an alignment region;a first gate stack disposed over the semiconductor substrate in the device region;a first source/drain region formed in the semiconductor substrate adjacent the first gate stack;a second gate stack disposed over ...

Semiconductor arrangement and formation thereof

A semiconductor arrangement and method of formation are provided herein. A semiconductor arrangement includes a metal connect in contact with a first active region and a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes recessing the metal connect over the STI region to form a recessed portion of the metal connect. Forming the recessed portion of the metal connect in contact with the first active region and the second active region mitigates RC coupling, such that a first gate is formed closer to a second gate, thus reducing a size of a chip on which the recessed portion is located.

Method of forming contact structure of gate structure

A method of forming a contact structure of a gate structure is provided. In the method, an oxidation layer and a first sidewall layer disposed between a first metal gate and a second metal gate are etched to expose an underlying silicon substrate. A silicide portion defined by a contact profile is deposited in the exposed portion of the silicon substrate. A second sidewall layer substantially covers the first sidewall layer and at least partially covering the silicide portion is formed after depositing the silicide portion. A metal glue layer is deposited around the first metal gate and the second metal gate defining a trench above the silicide portion. A metal plug is deposited within the trench.

Superimposition device of virtual guiding indication and reality image and the superimposition method thereof

A superimposition device of virtual guiding indication and reality image includes at least an image capturing device, a processor, a graphic processing unit (GPU), and a display device. The image capturing device captures reality image including instant scene. The processor receives the reality image and obtains height variation information. The GPU performs image correction processing on the reality image to obtain corrected image, generates updated transformation matrix according to the height variation information, and performs inverse perspective projection transformation by using the updated transformation matrix to generate bird's-eye view image of the corrected image and superimposes virtual guiding indication on the bird's-eye view image and performs perspective projection transformation on the bird's-eye view image to transform the bird's-eye view image into three-dimensional (3D) navigation image which includes the guiding indication. The display device displays the 3D navigation image which superimposes the virtual guiding indication into the reality image.

Exposure apparatus and method for photolithography process

Provided is an exposure apparatus including a variable focusing device. The variable focusing device may include a transparent membrane that may be deformed in the presence of an electric field. The deformation of the transparent membrane may allow the focus length of a radiation beam to be modified. In an embodiment, the variable focusing device may be modulated such that a radiation beam having a first focus length is provided for a first position on an exposure target and a radiation beam having a second focus length is provided for a second position on the exposure target. A method and computer-readable medium are also provided.

A ink point set for LCD defect location

Driving risk assessment and control decision-making method for autonomous vehicle

A driving risk assessment and control decision-making method for an autonomous vehicle includes: detecting the surrounding state of the vehicle multiple times to generate multiple sensing signals; quantifying the sensing signals to generate multiple sensing values and calculating a sensing average value of the sensing values; calculating a sensing error value between each sensing value and the sensing average value, a sensing error average value of sensing error values and a sensing error variation value; integrating the sensing error average value, the sensing error variation value and a sensor systematic error average value and a sensor systematic error variation value to generate a sensing signal correction value; combining the sensing values and the sensing signal correction value to generate multiple sensing signal reference values; judging whether a stability of the sensing signal reference values falls within a preset range; generating a control mechanism based on the judgement.

Verfahren zum bilden einer kontaktstruktur einer gate-struktur und kontaktstruktur einer gate-struktur

Verfahren zum Bilden einer Kontaktstruktur einer Gate-Struktur, umfassend:Ätzen einer Oxidationsschicht (360) und einer ersten Seitenwandschicht (350), angeordnet zwischen einem ersten Metall-Gate (330) und einem zweiten Metall-Gate (340), um eine darunterliegende Siliziumträgerschicht (320) freizulegen;Abscheiden eines Silizidabschnitts (520), der durch ein Kontaktprofil (410) im freigelegten Abschnitt der Siliziumträgerschicht (320) definiert ist;Bilden einer zweiten Seitenwandschicht (630), die die erste Seitenwandschicht (350) bedeckt und zumindest einen Teil des Silizidabschnitts (520) bedeckt, nach dem Abscheiden des Silizidabschnitts (520)Abscheiden einer Metallkleberschicht (740) um das erste Metall-Gate (330) und das zweite Metall-Gate (340), die einen Graben (750) über dem Silizidabschnitt (520) definiert, wobei die Metallkleberschicht (740) unter Verwendung von Wolfram abgeschieden wird;Abscheiden eines Metallsteckers (760) innerhalb des Grabens (750), undAusführen eines chemisch-mechanischen Polier- (CMP) Prozesses an dem Metallstecker (760), der Metallkleberschicht (740), dem ersten Metall-Gate (330), dem zweiten Metall-Gate (340), der ersten Seitenwandschicht (350) und der zweiten Seitenwandschicht (630) zum Planarisieren des Metallsteckers (760), der Metallkleberschicht (740), des ersten Metall-Gates (330), des zweiten Metall-Gates (340), der ersten Seitenwandschicht (350) und der zweiten Seitenwandschicht (630).

Automatic driving method and device able to diagnose decisions

An automatic driving method and device able to diagnose decisions is disclosed herein, wherein a vehicle body signal sensor detects vehicle body information, and an environment sensor detects traffic environment information. The information is transmitted to a central processor to generate a future driving track. The central processor examines whether the differences between the future driving track and the traffic environment information and the indexes of the future driving track meet tolerances. If no, the central processor transmits notification information to an automatic driving controller. If yes, the central processor transmits the future driving track to the automatic driving controller to make the automatic driving controller undertake automatic driving according to the future driving track. The present invention can automatically judge whether the future driving track generated by the central processor is within tolerances and determine whether the automatic driving track is safe.

Deciding system for stopping and dispatching vehicles and deciding method thereof

A deciding system for stopping and dispatching vehicles includes a memory and a cloud processing unit. The cloud processing unit is configured to determine one of a fixed vehicle dispatching algorithm and a non-fixed vehicle dispatching algorithm to be executed by the cloud processing unit according to a temporary car-hailing order message; execute the one of the fixed vehicle dispatching algorithm and the non-fixed vehicle dispatching algorithm to generate a stop message corresponding to a stop station according to a dispatch parameter set from the memory, and generate a stop number set corresponding to the first vehicle according to the stop message; and execute the one of the fixed vehicle dispatching algorithm and the non-fixed vehicle dispatching algorithm to generate a dispatch message according to the dispatch parameter set, and generate a dispatch vehicle number set corresponding to the second vehicle according to the dispatch message.

Dispositivo de fijación automática y posicionamiento para aparato dental

Un dispositivo de autobloqueo y posicionamiento para un aparato dental, que comprende: un cuerpo (10) principal del aparato que comprende una pista (102) y una ranura (104) de fijación, en el que ambos lados dentro de dicha pista (102) de dicho cuerpo (10) principal del aparato comprenden respectivamente una porción (106) de hendidura, en la que se forma una espacio (108) de recepción bajo dichas dos porciones (106) de hendidura; una pieza (14) elástica que comprende una pieza (144) de posicionamiento y una ranura (142), en la que un extremo de la pieza (144) de posicionamiento se conecta a la ranura (142), mientras que el otro extremo de dicha pieza (144) de posicionamiento se dobla en una forma de lengüeta, en la que la ranura (142) de la pieza (14) elástica se dispone en la ranura (104) de fijación del cuerpo (10) principal del aparato y la pieza (144) de posicionamiento de dicha pieza (14) elástica se coloca en dicho espacio (108) de recepción por debajo de la pista (102)'', en la que la ranura (142) se configura para pasar un arco (16) de alambre a través de la misma; y una cubierta(12) superior, en la que ambos lados de dicha cubierta (12) superior comprenden cada uno una porción (122) de protrusión en forma de tira, en la que dichas dos porciones (122) de protrusión de dicha cubierta (12) superior se pueden deslizar dentro de dicho cuerpo (10) principal del aparato a lo largo de dichas dos porciones (106) de hendidura de la pista (102), en el que, cuando la cubierta (12) superior se desliza en el cuerpo (10) principal del aparato a lo largo de la pista (102), la cubierta (12) superior se sitúa por encima de dicha pieza (144) de posicionamiento y dicha ranura (142) con el orificio (124) de fijación de la cubierta (12) superior que se sitúa justo por encima de la ranura (142) y se engancha mediante la púa, de manera que la pieza (144) de posicionamiento de la pieza (14) elástica se fija a la parte inferior de la cubierta (12) superior para bloquear ...

Self-locking and positioning device for dental brace

Magnet-guiding switching system and magnet-guiding switching method

A magnet-guiding switching system includes a lane magnetic field device, a switching controlling module and a route controlling center. As the switching controlling unit informs the magnetic field switching unit to turn on the first switching electromagnets and to turn off the second switching electromagnets according to the driving signal, the vehicle is guided by magnetic fields of the first switching electromagnets to drive from the first section of the first route to the second section along the guiding section; as the switching controlling unit informs the magnetic field switching unit to turn on the second switching electromagnets and to turn off the first switching electromagnets according to the driving signal, the vehicle is guided by magnetic fields of the second switching electromagnets to drive from the first section of the first route to the continuous section of the second route along the switching section.

提高oled結構中鋁反射率的方法

本發明公開了一種提高OLED結構中鋁反射率的方法，所述OLED結構包括頂層ITO、中間反射層和底層ITO，所述中間反射層為鋁反射層，方法包括：形成一底層ITO；在所述底層ITO表面鍍所述鋁反射層，同時並通入充足氧氣，從而在所述鋁反射層表面均勻形成一氧化鋁膜層；調配所述鋁反射層的鍍膜速率直至所述氧化鋁膜層形成；在所述氧化鋁層表面形成所述頂層ITO。

有機發光結構

揭露一種有機發光結構，包括陽極層、陰極層、位於陽極層與陰極層之間的有機發光層，以及側面反射層。陽極層具有一反射層，陰極層為透明結構。側面反射層位於陰極層之下，側面反射層與陽極層構成出光區，陽極層和側面反射層反射有機發光層發出的光線，使光線從出光區射出。

Wheel structure capable of creating music