Method and System for Optimizing Lithography Focus and/or Energy Using a Specially-Designed Optical Critical Dimension Pattern

Disclosed is a method and a system for optimizing lithography focus and/or energy using a specially-designed optical critical dimension pattern. A wafer comprising a plurality of photomasks is received. Critical dimension, line-end shortening, and side wall angle of the plurality of photomasks are measured using an integrated metrology equipment. A spectrum analysis is performed in a simulated spectra library to form analysis data. The analysis data is stored into a plurality of lookup tables of an optical critical dimension library. A lookup of the plurality of lookup tables is performed to determine a focus or energy of the wafer.

Method and System For Optimizing Sub-Nanometer Critical Dimension Using Pitch Offset

A method and a system are provided for calibrating metrological tools used to measure features of a semiconductor device. A critical dimension (CD) ruler defines a known pitch plus a pitch offset. A photoresist layer is measured to determine a measured pitch whereupon the measured pitch is compared to the known pitch. From the comparison, appropriate calibration steps can be taken to reduce the difference between the known pitch and the measured pitch.

Seal ring arrangements for immersion lithography systems

Various seal ring arrangements for an immersion lithography system are disclosed. With the seal ring arrangements, the immersion lithography system can provide better sealing effect for processing the wafers on a wafer chuck.

Method and system for a pattern layout split

A method for splitting a pattern layout including providing the pattern layout having features, checking the pattern layout to determine the features that require splitting, coloring the features that require splitting with a first and second color, resolving coloring conflicts by decomposing the feature with the coloring conflict and coloring the decomposed feature with the first and second color, and generating a first mask with features of the first color and a second mask with features of the second color.

Method of merging color sets of layout

A method includes determining one or more potential merges corresponding to a color set Ai and a color set Aj of N color sets, represented by A1 to AN, used in coloring polygons of a layout of an integrated circuit. N is a positive integer, i and j are integers from 1 to N, and ij. One or more potential cuts corresponding to the color set Ai and the second color set Aj are determined. An index Aij is determined according to the one or more potential merges and the one or more potential cuts. A plurality of parameters F related to the index Aij is obtained based on various values of indices fi and fj. A parameter F is selected among the plurality of parameters F based on a definition of the index Aij.

Methods for integrated circuit design and fabrication

The present disclosure provides a method that includes forming a first pattern feature and a second pattern feature over a material layer by a first photolithographic process. The method also includes forming a first spacer feature on a sidewall of the first pattern feature and a second spacer feature on a sidewall of the second pattern feature. Additionally, the method includes forming a third pattern feature on the material layer between the first spacer feature and the second spacer feature by a second photolithographic process. In addition, the method includes removing the first and second spacer features to expose a portion of the material layer.

Method and apparatus for extracting systematic defects

The present disclosure provides a method of systematic defect extraction. Primary and secondary areas are defined in a wafer layout. A plurality of defects is identified by a first wafer inspection for an outside-process-window wafer. Defects located in the secondary area are removed. Defects associated with non-critical semiconductor features are also removed via a grouping process. Sensitive regions are defined around defects associated with critical semiconductor features. A second inspection is then performed on the sensitive regions for an inside-process-window wafer, thereby identifying a plurality of potentially systematic defects. Thereafter, a Scanning Electron Microscopy (SEM) process is performed to determine whether the defects in the sensitive regions of the inside-process-window wafer are true systematic defects.

Via Connection to a Partially Filled Trench

A method includes forming a trench that is partially filled with a first metal material, the trench being formed within a first Interlayer Dielectric (ILD) layer, filling a remaining portion of the trench with a sacrificial material, depositing a buffer layer on the first ILD layer, patterning the buffer layer to form a hole within the buffer layer to expose the sacrificial material, and removing the sacrificial material. 1. A method comprising:forming a trench that is partially filled with a first metal material, the trench being formed within a first Interlayer Dielectric (ILD) layer;filling a remaining portion of the trench with a sacrificial material;depositing a buffer layer on the first ILD layer, the buffer layer being a different material than the sacrificial material;patterning the buffer layer to form a hole within the buffer layer to expose the sacrificial material; andremoving the sacrificial material.2. The method of claim 1 , further comprising claim 1 , filling the remaining portion of the trench and the hole with a second metal material to form a via.3. The method of claim 2 , wherein a top portion of the via is offset from a bottom portion of the via.4. The method of claim 2 , wherein the second metal material and the first metal material comprise the same metal material.5. The method of claim 2 , further comprising:removing the buffer layer; andforming a second ILD layer on the first ILD layer.6. The method of claim 5 , further comprising claim 5 , forming a metal line on the second ILD layer claim 5 , the metal line contacting the top of the via.7. The method of claim 5 , wherein the forming of the metal line in the second ILD layer includesforming a second trench in the second ILD layer;filling the second trench by a third metal material; andpolishing the third metal material to remove excessive portion of the third metal material.8. The method of claim 7 , wherein the first ILD layer and the second ILD layer comprise a same material; the buffer ...

System For Improving Critical Dimension Uniformity

A system for improving substrate critical dimension uniformity is described. The system includes an exposing means for exposing a plurality of mask patterns on a first plurality of substrates at predetermined locations with common splits of focus ({Fj}) and exposure dose ({Ek}) for each of the first plurality of substrates to form a plurality of perturbed wafers. A measuring means is provided for measuring a critical dimension of the plurality of mask patterns at each of the predetermined locations for each of the plurality of perturbed wafers. An averaging means is provided for averaging the critical dimension measured at each of the predetermined locations over the plurality of perturbed wafers to form a perturbed critical dimension map. A second measuring means is provided for measuring a sidewall angle of the plurality of mask patterns at each of the predetermined locations for each of the plurality of perturbed wafers. A second averaging means is provided for averaging the sidewall ...

Method of defining an intensity selective exposure photomask

An embodiment of a feed-forward method of determining a photomask pattern is provided. The method includes providing design data associated with an integrated circuit device. A thickness of a coating layer to be used in fabricating the integrated circuit device is predicted based on the design data. This prediction is used to generate a gradating pattern. A photomask is formed having the gradating pattern.

Measurement of overlay offset in semiconductor processing

A system for overlay offset measurement in semiconductor manufacturing including a radiation source, a detector, and a calculation unit. The radiation source is operable to irradiate an overlay offset measurement target. The detector is operable to detect a first reflectivity and a second reflectivity of the irradiated overlay offset measurement target. The calculation unit is operable to determine an overlay offset using the detected first and second reflectivity by determining a predetermined overlay offset amount which provides an actual offset of zero.

Geometric compensation method for charged particle beam irradiation

A charged particle beam method for irradiating an array of sub-regions within an areal region within a substrate with a series of shots of a charged particle beam provides that a sequencing of irradiation of the array of sub-regions is geometrically determined such as to minimize charged particle beam deflection when irradiating the series of sub-regions with the series of shots of the charged particle beam. Due to the geometric determination which provides the minimized charged particle beam deflection, the charged particle beam method has enhanced accuracy.

Mechanisms for forming patterns using multiple lithography processes

The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern.

Patterning process and photoresist with a photodegradable base

A resist material and methods using the resist material are disclosed herein. An exemplary method includes forming a resist layer over a substrate, wherein the resist layer includes a polymer, a photoacid generator, an electron acceptor, and a photodegradable base; performing an exposure process that exposes portions of the resist layer with radiation, wherein the photodegradable base is depleted in the exposed portions of the resist layer during the exposure process; and performing an developing process on the resist layer.

METHOD AND SYSTEM FOR OPTIMIZING INTRA-FIELD CRITICAL DIMENSION UNIFORMITY USING A SACRIFICIAL TWIN MASK

Disclosed is a method and a system for optimizing intra-field critical dimension of an integrated circuit. A first mask for an integrated circuit is provided comprising at least one device region. A second mask is provided by copying the first mask and a lithography operation is provided to the integrated circuit using the first and second masks, wherein the critical dimension of the integrated circuit is optimized using the second mask. The second mask comprises a plurality of sacrificial patterns, which may be a plurality of flat patterns or a plurality of grating patterns.

METHOD AND APPARATUS FOR EXTRACTING SYSTEMATIC DEFECTS

The present disclosure provides a method of systematic defect extraction. Primary and secondary areas are defined in a wafer layout. A plurality of defects is identified by a first wafer inspection for an outside-process-window wafer. Defects located in the secondary area are removed. Defects associated with non-critical semiconductor features are also removed via a grouping process. Sensitive regions are defined around defects associated with critical semiconductor features. A second inspection is then performed on the sensitive regions for an inside-process-window wafer, thereby identifying a plurality of potentially systematic defects. Thereafter, a Scanning Electron Microscopy (SEM) process is performed to determine whether the defects in the sensitive regions of the inside-process-window wafer are true systematic defects. 1. A method , comprising:defining a primary area and a secondary area in a wafer layout;identifying, using a first sensitivity detection, a first plurality of defects by performing a first inspection on the primary area and the secondary area for an outside-process-window wafer;performing a first nuisance defect filtering process by removing identified defects from the secondary area;generating a care area that includes patterns of interest;identifying, using a second sensitivity detection more sensitive than the first sensitivity detection, a second plurality of defects by performing a second inspection on the care area for an inside-process-window wafer; andvisually examining each of the defects in the care area of the inside-process-window wafer to ascertain a list of systematic defects.2. The method of claim 1 , wherein the second plurality of defects includes a plurality of potentially systematic defects.3. The method of claim 1 , further comprising:after performing the first nuisance defect filtering process, performing a grouping process in an area outside the secondary area, wherein the grouping process forms a plurality of groups of ...

MECHANISMS FOR FORMING PATTERNS USING MULTIPLE LITHOGRAPHY PROCESSES

The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern. 1. A method for forming patterns in a semiconductor device , comprising:forming a main pattern in a patterning-target layer over a substrate;forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer;patterning the hard mask layer to form a first cut pattern;forming a second cut pattern in a first resist layer formed over the hard mask layer;patterning the middle layer through an opening corresponding to a first intersection portion to expose a portion of the patterning-target layer, the exposed portion of the patterning-target layer corresponding to a second intersection portion;forming a fill layer to fill the opening;etching the middle layer using the fill layer and the hard mask layer as etching masks to expose one or more portions of the patterning-target layer; andetching the one or more exposed portions of the patterning-target layer using the fill layer and the hard mask layer as etching masks to form a final pattern in the patterning-target layer,wherein the first intersection portion corresponds to ...

Multi-layer metal contacts

A method for forming metal contacts within a semiconductor device includes forming a first-layer contact into a first dielectric layer that surrounds at least one gate electrode, the first-layer contact extending to a doped region of an underlying substrate. The method further includes forming a second dielectric layer over the first dielectric layer and forming a second-layer contact extending through the second dielectric layer to the first-layer contact.

Lithographic Technique Incorporating Varied Pattern Materials

A technique for patterning a workpiece such as an integrated circuit workpiece is provided. In an exemplary embodiment, the method includes receiving a workpiece having a material layer disposed on a substrate. A first set of fins is formed on the material layer, and a second set of fins is formed on the material layer interspersed between the first set of fins. The second set of fins have a different etchant sensitivity from the first set of fins. A first etching process is performed on the first set of fins and configured to avoid substantial etching of the second set of fins. A second etching process is performed on the second set of fins and configured to avoid substantial etching of the first set of fins. The material layer is etched to transfer a pattern defined by the first etching process and the second etching process. 1. A method of patterning a workpiece , the method comprising:receiving a workpiece having a material layer to be patterned;forming a first set of fins on the material layer;forming a second set of fins on the material layer and interspersed between the first set of fins, wherein the second set of fins have a different etchant sensitivity from the first set of fins;performing a first etching process on the first set of fins configured to avoid substantial etching of the second set of fins;performing a second etching process on the second set of fins configured to avoid substantial etching of the first set of fins; andetching the material layer to transfer a pattern defined by the first etching process and the second etching process to the material layer.2. The method of claim 1 , wherein the forming of the second set of fins includes:applying a directed self assembly material to the workpiece between the first set of fins; andperforming a curing process on the directed self assembly material that causes a component of the directed self assembly material to align as the second set of fins.3. The method of claim 2 , wherein the forming of the ...

Systems and Methods for a Sequential Spacer Scheme

Methods disclosed herein form semiconductor devices having minimum spacings that correlate with spacer widths. An exemplary method includes forming a target layer over a substrate, forming a patterning layer over the target layer, and etching the target layer using the patterning layer as an etch mask. The patterning layer includes a first pattern feature, a second pattern feature spaced a first distance (corresponding with a first width of a first spacer fabricated during a first spacer patterning process) from the first pattern feature, and a third pattern feature spaced a second distance (corresponding with a second width of a second spacer fabricated during a second spacer patterning process) from the first pattern feature and a third distance (corresponding with a third width of a third spacer formed during the second spacer patterning process) from the second pattern feature. 1. A method comprising:forming a target layer over a substrate; a first pattern feature,', 'a second pattern feature spaced a first distance from the first pattern feature, wherein the first distance corresponds with a first width of a first spacer fabricated during a first spacer patterning process, and', 'a third pattern feature spaced a second distance from the first pattern feature and a third distance from the second pattern feature, wherein the second distance corresponds with a second width of a second spacer fabricated during a second spacer patterning process and the third distance corresponds with a third width of a third spacer formed during the second spacer patterning process; and, 'forming a patterning layer over the target layer, wherein the patterning layer includesetching the target layer using the patterning layer as an etch mask, such that the target layer includes a first target feature that corresponds with the first pattern feature, a second target feature that corresponds with the second pattern feature, and a third target feature that corresponds with the third ...

SUB-RESOLUTION ROD IN THE TRANSITION REGION

The present disclosure provides a photomask. The photomask includes a first integrated circuit (IC) feature formed on a substrate; and a second IC feature formed on the substrate and configured proximate to the first IC feature. The first and second IC features define a dense pattern having a first pattern density. The second IC feature is further extended from the dense pattern, forming an isolated pattern having a second pattern density less than the first pattern density. A transition region is defined from the dense pattern to the isolated pattern. The photomask further includes a sub-resolution rod (SRR) formed on the substrate, disposed in the transition region, and connected with the first IC feature. 1. A photomask , comprising:a first integrated circuit (IC) feature formed on a substrate; the first and second IC features define a dense pattern having a first pattern density;', 'the second IC feature is further extended from the dense pattern to form an isolated pattern having a second pattern density less than the first pattern density; and', 'a transition region is defined from the dense pattern to the isolated pattern; and, 'a second IC feature formed on the substrate and configured proximate to the first IC feature, wherein'}a sub-resolution rod (SRR) formed on the substrate, disposed in the transition region, and connected with the first IC feature.2. The photomask of claim 1 , whereinthe second IC feature includes a first width cd greater than a printable width defined as a minimum dimension printable to a photoresist layer during a lithography patterning process; andthe SRR includes at least a second width W less than the printable width.3. The photomask of claim 2 , wherein the SRR includes a length L equal to or greater than 0.8 times of the first width cd.4. The photomask of claim 2 , wherein the dense pattern includes a first spacing sp1 between the first and second IC features claim 2 , the first spacing sp1 being less than or equal to 2*cd.5. ...

INTEGRATED CIRCUIT LAYOUT AND METHOD WITH DOUBLE PATTERNING

The present disclosure provides one embodiment of a method for an integrated circuit (IC). The method includes forming a mandrel pattern on a substrate by a first lithography process; forming a first spacer pattern on sidewalls of the mandrel pattern; removing the mandrel pattern; forming a second spacer pattern on sidewalls of the first spacer pattern; removing the first spacer pattern; and etching the substrate using the second spacer pattern as an etch mask. 114-. (canceled)15. A method for integrated circuit (IC) , comprising:receiving an IC layout having a plurality of features;determining pitches in the plurality of features;determining mask parameters and processing parameters based on the pitches in the features; andfabricating a mask according to the mask parameters.16. The method of claim 15 , further comprising fabricating a wafer according to the processing parameters and using the mask.17. The method of claim 16 , whereinthe mask parameters include a width L and a spacing S defined in the features; andthe processing parameters include a first thickness b of a first spacer material layer to be deposited on the wafer and a second thickness of a second spacer material layer to be deposited on the wafer.1817. The method of claim claim 16 , claim 16 , wherein the fabricating of the wafer includesdepositing the first spacer material layer of the first thickness b; andperforming a first anisotropic etch to the first spacer material layer, thereby forming a first spacer pattern.19. The method of claim 17 , wherein the fabricating of the wafer includesdepositing a second spacer material layer of the second thickness c; andperforming a second anisotropic etch to the second spacer material layer, thereby forming a second spacer pattern.20. A method for integrated circuit (IC) claim 17 , comprising:receiving an IC layout having a plurality of features having a first pitch P1 and a second pitch P2 being different from each other;determining a first processing ...

Mechanisms for forming patterns using lithography processes

The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate, a patterning-target layer over the substrate, and a hard mask layer over the patterning-target layer; forming a first pattern in the hard mask layer; removing a trim portion from the first pattern in the hard mask layer to form a trimmed first pattern; forming a first resist layer over the hard mask layer; forming a main pattern in the first resist layer; and etching the patterning-target layer using the main pattern and the trimmed first pattern as etching mask elements to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting a first overlapping portion between the main pattern and the trimmed first pattern.

Method of heating semiconductor wafer to improve wafer flatness

A method of heating-treating a semiconductor wafer is provided. In one embodiment, a first layer is formed over a first side of a substrate. A second layer is formed over the first layer and over a second side of the substrate and the wafer is then flash annealed. In another embodiment, a first layer is formed over a first side of a substrate and over a second side of the substrate. A second layer is formed over the first layers and the wafer is then flash annealed.

Immersion optical projection system

An immersion optical projection system for photolithography is provided. A transparent plate is located between a last lens element and the wafer during a usage of the system. The transparent plate has a lens-side surface and a wafer-side surface. The system is adapted to have a layer of lens-side fluid located between the last lens element and the lens-side surface of the transparent plate, e.g., when the last lens element is operably located over the wafer during a photolithography process. The system is also adapted to have a layer of wafer-side fluid located between the wafer-side surface of the transparent plate and the wafer, during a usage of the system. The wafer-side fluid may or may not be fluidly connected to the lens-side fluid. The wafer-side fluid may or may not differ from the lens-side fluid.

Method and System For Wafer Inspection

A method for inspecting semiconductor wafers patterned by a photomask includes loading a first wafer and scanning a first image of the first wafer, loading a second wafer and scanning a second image of the second wafer, comparing the first and second images, and classifying a difference detected between the first and second images as a potential defect on the photomask. The potential defect includes a haze defect on the photomask.

Method of patterning a feature of a semiconductor device

A method including forming a trench over a layer disposed on a semiconductor substrate. The trench is filled with a first material to form a filled trench. A feature of a second material is formed over the filled trench. The feature is disposed over the filled trench and extends along two opposing sidewalls of the filled trench to a top surface of the layer. The feature is then planarized to expose a top surface of the filled trench and provide a first portion of the feature adjacent a first sidewall of the two opposing sidewalls of the filled trench and a second portion of the feature adjacent a second sidewall of the two opposing sidewalls of the filled trench. The first and second portions of the feature are used to define a dimension of an interconnect feature disposed over the semiconductor substrate.

System for improving critical dimension uniformity

A system for improving substrate critical dimension uniformity is described. The system includes an exposing means for exposing a plurality of mask patterns on a first plurality of substrates at predetermined locations with common splits of focus ({Fj}) and exposure dose ({Ek}) for each of the first plurality of substrates to form a plurality of perturbed wafers. A measuring means is provided for measuring a critical dimension of the plurality of mask patterns at each of the predetermined locations for each of the plurality of perturbed wafers. An averaging means is provided for averaging the critical dimension measured at each of the predetermined locations over the plurality of perturbed wafers to form a perturbed critical dimension map. A second measuring means is provided for measuring a sidewall angle of the plurality of mask patterns at each of the predetermined locations for each of the plurality of perturbed wafers. A second averaging means is provided for averaging the sidewall ...

Mechanisms for forming patterns using multiple lithography processes

The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern.

Extraction of systematic defects

In one embodiment, a method for extracting systematic defects is provided. The method includes inspecting a wafer outside a process window to obtain inspection data, defining a defect pattern from the inspection data, filtering defects from design data using a pattern search for the defined defect pattern within the design data, inspecting defects inside the process window with greater sensitivity than outside the process window, and determining systematic defects inside the process window. A computer readable storage medium, and a system for extracting systematic defects are also provided.

METHODS FOR GENERATING A MANDREL MASK

Embodiments of the present disclosure provide a method of generating mandrel patterns. A mandrel pattern is generated by constructing a boundary box, initiating a plurality of lead mandrels, and extending the lead mandrels across the boundary box. When a pattern region includes holes, portions of mandrels are removed from the holes after extension of the leading mandrels.

Lithography using high selectivity spacers for pitch reduction

A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer.

Spacer etching process for integrated circuit design

A method of forming a target pattern includes forming a first material layer on a substrate; performing a first patterning process using a first layout to form a first plurality of trenches in the first material layer; performing a second patterning process using a second layout to form a second plurality of trenches in the first material layer; forming spacer features on sidewalls of both the first plurality of trenches and the second plurality of trenches, the spacer features having a thickness; removing the first material layer; etching the substrate using the spacer features as an etch mask; and thereafter removing the spacer features. The target pattern is to be formed with the first layout and the second layout.

Systems and methods for a sequential spacer scheme

Methods disclosed herein form semiconductor devices having minimum spacings that correlate with spacer widths. An exemplary method includes forming a target layer over a substrate, forming a patterning layer over the target layer, and etching the target layer using the patterning layer as an etch mask. The patterning layer includes a first pattern feature, a second pattern feature spaced a first distance (corresponding with a first width of a first spacer fabricated during a first spacer patterning process) from the first pattern feature, and a third pattern feature spaced a second distance (corresponding with a second width of a second spacer fabricated during a second spacer patterning process) from the first pattern feature and a third distance (corresponding with a third width of a third spacer formed during the second spacer patterning process) from the second pattern feature.

Systems and methods for a sequential spacer scheme

The present disclosure describes methods for transferring a desired layout into a target layer. The method includes a step of forming a spacer, having a second width, around a first and a second desired layout feature pattern of the desired layout over a semiconductor substrate. The first desired layout feature pattern is formed using a first sub-layout and the second desired layout feature pattern is formed using a second sub-layout. The first and second desired layout feature patterns are separated by a first width. The method further includes forming a third desired layout feature pattern according to a third sub-layout. The third desired layout feature pattern is shaped in part by the spacer. The method further includes removing the spacer from around the first and second desired layout feature pattern and etching the target layer using the first, second, and third layout feature patterns as masking features.

Photolithography system to increase overlay accuracy

A semiconductor photolithography system to improve overlay accuracy is disclosed. Such a system can include an exposure tool, at least one track, and a number of photoresist modules. The exposure tool performs functionality related to both at least a front-end and a back-end wafer. Each track has one or more paths to and from the exposure tool. The photoresist modules each perform functionality related to photoresist, on only either the front-end wafer or the back-end wafer, not both. Each module is located on one of the tracks. More specifically, a two-track system is disclosed, where each track has a path to and from the exposure tool, and a single-track system is disclosed having two paths to and from the exposure tool.

System and method for alignment in semiconductor device fabrication

A method of determining overlay error in semiconductor device fabrication includes receiving an image of an overlay mark formed on a substrate. The received image is separated into a first image and a second image, where the first image includes representations of features formed on a first layer of the substrate and the second image includes representations of the features formed on a second layer of the substrate. A quality indicator is determined for the first image and a quality indicator is determined for the second image. In an embodiment, the quality indicators include asymmetry indexes.

Methods for Integrated Circuit Design and Fabrication

The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein. 1. A method comprising:forming a first pattern feature and a second pattern feature over a material layer by a first photolithographic process;forming a first spacer feature on a sidewall of the first pattern feature and a second spacer feature on a sidewall of the second pattern feature;forming a third pattern feature on the material layer between the first spacer feature and the second spacer feature by a second photolithographic process; andremoving the first and second spacer features to expose a portion of the material layer.2. The method of claim 1 , wherein after the forming of the first spacer feature on the sidewall of the first pattern feature claim 1 , the first spacer feature physically contacts the sidewall of the first pattern feature claim 1 , andwherein after the forming of the second spacer feature on the sidewall of the second pattern feature, the second spacer feature physically contacts the sidewall of the second pattern feature.3. The method of claim 1 , wherein the first spacer feature includes a top surface facing away from the material layer claim 1 , andwherein the forming of the third pattern feature on the material layer between the first spacer feature and the second spacer feature by the second photolithographic process includes forming a portion of the third pattern feature over the top surface of the first spacer feature.4. ...

PELLICLE ASSEMBLY AND METHOD OF MAKING SAME

A method for preparing a pellicle assembly includes reducing the thickness of one or more initial membrane(s) to obtain a pellicle membrane. The pellicle membrane is then affixed to a mounting frame to obtain the pellicle assembly. Compressive pressure can be applied to reduce the thickness of the initial membrane(s). Alternatively, the thickness can be reduced by stretching the initial membrane(s) to obtain an extended membrane. A mounting frame is then affixed to a portion of the extended membrane. The mounting frame and the portion of the extended membrane are then separated from the remainder of the extended membrane to obtain the pellicle assembly. The resulting pellicle assemblies include a pellicle membrane that is attached to a mounting frame. The pellicle membrane can be formed from nanotubes and has a combination of high transmittance, low deflection, and small pore size.

Method of defining forbidden pitches for a lithography exposure tool

A method of identifying and defining forbidden pitches or forbidden pitch ranges for a lithographic exposure tool under a given set of exposure conditions is provided. In the method, a computer simulation is performed, and its results are compared to frequently used pitches to see if such frequently used pitches may yield depth-of-focus (DOF) values greater than the focus budget for the exposure tool. If so, a verification test is performed by using a test mask and actually exposing a surface with the same pattern pitches simulated. From this, actual DOF values are obtained and compared to the focus budget of the exposure tool. Any pitches having a DOF value greater than the focus budget are designated as forbidden pitches. This forbidden pitch information may be integrated into a design rule to restrict the use of such forbidden pitches under the given exposure conditions where they are likely to arise.

Method of inter-field critical dimension control

A method of inter-field critical dimension control. The method is applied to a wafer with a plurality of dies manufactured by a wafer manufacturing process that includes exposure. According to the method, a plurality of manufacturing modules is obtained by selecting a manufacturing device for each process of the manufacture. Then, for each manufacturing module, exposure is performed with a predetermined exposure energy to obtain critical dimension distribution data corresponding to the predetermined exposure energy, and critical dimension calibration data for each of the dies is further determined. Thus, when one of the manufacturing modules is applied to perform the manufacture, an exposure energy for each of the dies is determined according to the predetermined exposure energy and the critical dimension calibration data for each of the dies, and the manufacture is performed with the exposure energy on each of the dies for the manufacturing module.

PATTERNING PROCESS AND CHEMICAL AMPLIFIED PHOTORESIST WITH A PHOTODEGRADABLE BASE

A method for fabricating an integrated circuit device is disclosed. The method includes providing a substrate; forming a first material layer over the substrate; forming a second material layer over the first material layer, wherein the second material layer comprises a photodegradable base material; and exposing at least a portion of the second material layer.

Method of fabricating semiconductor device with reduced trench distortions

A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.

Via connection to a partially filled trench

A method includes forming a trench that is partially filled with a first metal material, the trench being formed within a first Interlayer Dielectric (ILD) layer, filling a remaining portion of the trench with a sacrificial material, depositing a buffer layer on the first ILD layer, patterning the buffer layer to form a hole within the buffer layer to expose the sacrificial material, and removing the sacrificial material.

In-line particle detection for immersion lithography

An immersion lithography system, comprising a lens unit configured to project a pattern from an end thereof and onto a wafer, a hood unit configured to confine an immersion fluid to a region of the wafer surrounding the end of the lens unit, a wafer stage configured to position the wafer proximate the end of the lens unit, and at least one of an image capturing apparatus and a scattering light detection apparatus, wherein the image capturing apparatus is coupled to the wafer stage and is configured to capture an image of a surface of the hood unit proximate the wafer stage, and wherein the scattering light detection apparatus is proximate the end of the lens unit and the hood unit and is configured to detect particles on a surface of the wafer stage.

Spacer etching process for integrated circuit design

A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a patterning process; and forming a second plurality of trenches in the first layer by another patterning process, resulting in combined trench patterns in the first layer. A first trench of the second plurality connects two trenches of the first plurality. The method further includes forming dielectric spacer features on sidewalls of the combined trench patterns. A space between two opposing sidewalls of the first trench is completely filled by the dielectric spacer features and another space between two opposing sidewalls of one of the two trenches is partially filled by the dielectric spacer features.

IN-LINE PARTICLE DETECTION FOR IMMERSION LITHOGRAPHY

An immersion lithography system, comprising a lens unit configured to project a pattern from an end thereof and onto a wafer, a hood unit configured to confine an immersion fluid to a region of the wafer surrounding the end of the lens unit, a wafer stage configured to position the wafer proximate the end of the lens unit, and at least one of an image capturing apparatus and a scattering light detection apparatus, wherein the image capturing apparatus is coupled to the wafer stage and is configured to capture an image of a surface of the hood unit proximate the wafer stage, and wherein the scattering light detection apparatus is proximate the end of the lens unit and the hood unit and is configured to detect particles on a surface of the wafer stage.

Seal ring arrangements for immersion lithography systems

Various seal ring arrangements for an immersion lithography system are disclosed. With the seal ring arrangements, the immersion lithography system can provide better sealing effect for processing the wafers on a wafer chuck.

VIA CONNECTION TO A PARTIALLY FILLED TRENCH

An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on the first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.

Integrated optical metrology and lithographic process track for dynamic critical dimension control

A method and apparatus for improving a yield and throughput of a lithographic process track, the method including providing a first resist layer on a first process wafer; forming a first resist pattern in the first resist layer including a heating process according to a first temperature profile wherein the heating process comprises a plurality of temperature controllable heating zones; producing and collecting scattered light spectra from the first resist pattern processing the scattered light spectrum to obtain 3-dimensional information including first resist pattern critical dimensions; determining a second temperature profile for performing the heating process to achieve targeted resist pattern critical dimensions including a second resist pattern on a second process wafer; and, forming the second resist pattern dimensions including the heating process according to the second temperature profile.

Wafer repair method using direct-writing

A method of wafer repairing comprises identifying locations and patterns of defective regions in a semiconductor wafer; communicating the locations and patterns of defective regions to a direct-writing tool; forming a photoresist layer on the semiconductor wafer; locally exposing the photoresist layer within the defective regions using an energy beam; developing the photoresist layer on the semiconductor wafer; and wafer-processing the semiconductor wafer under the photoresist layer after exposing and developing.

Lithography using high selectivity spacers for pitch reduction

A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer.

Systems and methods for a sequential spacer scheme

The present disclosure describes methods for transferring a desired layout into a target layer. The method includes a step of forming a spacer, having a second width, around a first and a second desired layout feature pattern of the desired layout over a semiconductor substrate. The first desired layout feature pattern is formed using a first sub-layout and the second desired layout feature pattern is formed using a second sub-layout. The first and second desired layout feature patterns are separated by a first width. The method further includes forming a third desired layout feature pattern according to a third sub-layout. The third desired layout feature pattern is shaped in part by the spacer. The method further includes removing the spacer from around the first and second desired layout feature pattern and etching the target layer using the first, second, and third layout feature patterns as masking features.

Optical proximity correction convergence control

A method of optical proximity correction (OPC) convergence control that includes providing a lithography system having a photomask and an illuminator. The method further includes performing an exposure by the illuminator on the photomask. Also, the method includes optimizing an optical illuminator setting for the lithography system with a defined gate pitch in a first direction in a first template. Additionally, the method includes determining OPC correctors to converge the OPC results with a target edge placement error (EPE) to produce a first OPC setting for the first template. The first OPC setting targets a relatively small EPE and mask error enhancement factor (MEEF)of the defined gate pitch in the first template. In addition, the method includes checking the first OPC setting for a relatively small EPE, MEEF and DOM consistency with the first template of the defined gate pitch in a second, adjacent template.

Self-alignment for using two or more layers and methods of forming same

Embodiments of the present disclosure include self-alignment of two or more layers and methods of forming the same. An embodiment is a method for forming a semiconductor device including forming at least two gates over a substrate, forming at least two alignment structures over the at least two gates, forming spacers on the at least two alignment structures, and forming a first opening between a pair of the at least two alignment structures, the first opening extending a first distance from a top surface of the substrate. The method further includes filling the first opening with a first conductive material, forming a second opening between the spacers of at least one of the at least two alignment structures, the second opening extending a second distance from the top surface of the substrate, and filling the second opening with a second conductive material.

METHOD OF DEFINING AN INTENSITY SELECTIVE EXPOSURE PHOTOMASK

An embodiment of a feed-forward method of determining a photomask pattern is provided. The method includes providing design data associated with an integrated circuit device. A thickness of a coating layer to be used in fabricating the integrated circuit device is predicted based on the design data. This prediction is used to generate a gradating pattern. A photomask is formed having the gradating pattern. 1. A method , comprising:receiving design data associated with an integrated circuit device;predicting a thickness of a coating layer based on the design data;generating a gradating pattern based on the predicted thickness; andforming a photomask having the generated gradating pattern.2. The method of claim 1 , wherein the coating layer is a photosensitive material.3. The method of claim 1 , wherein the predicting includes using a model generated from experimental data.4. The method of claim 1 , further comprising:passing a radiation beam through the photomask to expose a target substrate, wherein the photomask includes a first region that allows a first energy level of the radiation beam to traverse the photomask and a second region that allows a second energy level of the radiation beam, different than the first energy level, to traverse the photomask.5. The method of claim 4 , further comprising:forming the coating layer on a semiconductor substrate; andexposing the coating layer to the first energy level of the radiation beam and the second energy level of the radiation beam.6. The method of claim 1 , wherein the predicting the thickness of the coating layer includes determining a first pattern density associated with a first area of the integrated circuit device and a second pattern density associated with a second area of the integrated circuit device.7. The method of claim 1 , wherein the generating the gradating pattern includes generating an array of pixels having a first pixel with an opening of a first width.8. The method of claim 7 , wherein the ...

Method for metal correlated via split for double patterning

A method of via patterning mask assignment for a via layer using double patterning technology, the method includes determining, using a processor, if a via of the via layer intercepts an underlying or overlaying metal structure assigned to a first metal mask. If the via intercepts the metal structure assigned to the first metal mask, assigning the via to a first via mask, wherein the first via mask aligns with the first metal mask. Otherwise, assigning the via to a second via mask, wherein the second via mask aligns with a second metal mask different from the first metal mask.

Method and system for patterning alignment marks on a transparent substrate

Disclosed is a method and a system for forming alignment marks on a transparent substrate. A light reflective layer is deposited over an optically transparent substrate of a wafer. A region is defined around an alignment mark on the optically transparent substrate. The light reflective layer is removed from a substantial portion of the transparent substrate excluding the region. In addition, a micro electro-mechanical systems device is disclosed. The device comprises an optically transparent substrate, at least one optically partially transparent alignment mark on the optically transparent substrate, and a plurality of reflective elements or imaging pixels attached to the optically transparent substrate.

MECHANISMS FOR FORMING PATTERNS

The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer over the substrate; forming one or more mandrel patterns over the patterning-target layer; forming an opening in a resist layer by removing a first mandrel pattern and removing a portion of the resist layer that covers the first mandrel pattern; forming spacers adjacent to sidewalls of a second mandrel pattern; removing the second mandrel pattern to expose the spacers; forming a patch pattern over the spacers and aligned with the opening; etching the patterning-target layer using the patch pattern and the spacers as mask elements to form final patterns; and removing the patch pattern and the spacers to expose the final patterns.

Lithography using high selectivity spacers for pitch reduction

A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer.

Self-Alignment for using Two or More Layers and Methods of Forming Same

Embodiments of the present disclosure include self-alignment of two or more layers and methods of forming the same. An embodiment is a method for forming a semiconductor device including forming at least two gates over a substrate, forming at least two alignment structures over the at least two gates, forming spacers on the at least two alignment structures, and forming a first opening between a pair of the at least two alignment structures, the first opening extending a first distance from a top surface of the substrate. The method further includes filling the first opening with a first conductive material, forming a second opening between the spacers of at least one of the at least two alignment structures, the second opening extending a second distance from the top surface of the substrate, and filling the second opening with a second conductive material. 1. A method for forming a semiconductor device , the method comprising:forming at least two gates over a substrate;forming at least two alignment structures over the at least two gates;forming spacers on opposite sidewalls of the at least two alignment structures;forming a first opening between a pair of the at least two alignment structures, a portion of the first opening exposing a top surface of at least one of the pair, the first opening extending a first distance from a top surface of the substrate;filling the first opening with a first conductive material to form a first conductive feature;forming a second opening between the spacers of at least one of the at least two alignment structures, the second opening extending a second distance from the top surface of the substrate, the second distance being different than the first distance; andfilling the second opening with a second conductive material to form a second conductive feature.2. The method of further comprising:forming a first dielectric layer over the at least two gates, the at least two alignment structures being formed on a top surface of the ...

Mandrel spacer patterning in multi-pitch integrated circuit manufacturing

A method of manufacturing an integrated circuit (IC) includes receiving a design layout of the IC, wherein the design layout includes two abutting blocks, the two blocks include target patterns, and the target patterns have different pitches in the two blocks. The method further includes generating mandrel pattern candidates in spaces between adjacent target patterns, and assigning first and second colors to the mandrel pattern candidates according to their priorities. The method further includes removing the mandrel pattern candidates assigned with the second color, and outputting a mandrel pattern in computer-readable format for mask fabrication. The mandrel pattern includes the mandrel pattern candidates that are colored with the first color.

Self-alignment for two or more layers and methods of forming same

Embodiments of the present disclosure include self-alignment of two or more layers and methods of forming the same. An embodiment is a method for forming a semiconductor device including forming at least two gates over a substrate, forming at least two alignment structures over the at least two gates, forming spacers on the at least two alignment structures, and forming a first opening between a pair of the at least two alignment structures, the first opening extending a first distance from a top surface of the substrate. The method further includes filling the first opening with a first conductive material, forming a second opening between the spacers of at least one of the at least two alignment structures, the second opening extending a second distance from the top surface of the substrate, and filling the second opening with a second conductive material.

Intensity selective exposure photomask

An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage. Each of the features of the first and second array includes an opening disposed in an area of attenuating material.

Scatterometric method of monitoring hot plate temperature and facilitating critical dimension control

A method of determining temperatures at localized regions of a substrate during processing of the substrate in a photolithography process includes the following steps: independently illuminating a photoresist layer including a photoresist pattern at a plurality of locations on the substrate with a light source, so that light is diffracted off the plurality of locations of the photoresist pattern; measuring the diffracted light from the plurality of locations to determine measured diffracted values associated with respective locations from the plurality of locations; and comparing the measured diffracted values against a library to determine a pre-illumination process temperature of the photoresist layer at the plurality of locations.

METHOD OF FABRICATING SEMICONDUCTOR DEVICE

A method for fabricating a semiconductor device includes forming a hard mask (HM) layer over a material layer, forming a first trench in the HM layer, which extends along a first direction. The method also includes forming a first patterned resist layer over the HM layer. The first patterned resist layer has a first opening and a second opening a second direction. The first opening overlaps with the first trench in a middle portion of the first trench and the second opening overlaps with the first trench at an end portion of the first trench. The method also includes etching the HM layer through the first patterned resist layer to form a second trench and a third trench in the HM layer and forming a first feature to fill in a section of the first trench between the second trench and the third trench. 1. A method comprising:forming a hard mask (HM) layer over a material layer;forming a first trench in the HM layer, wherein the first trench extends along a first direction;forming a first patterned resist layer over the HM layer, wherein the first patterned resist layer has a first opening and a second opening such that:the first opening extends along a second direction that is perpendicular to the first direction, the first opening overlaps with the first trench in a middle portion of the first trench;the second opening is parallel to the first opening and overlaps with the first trench at an end portion of the first trench;etching the HM layer through the first patterned resist layer to form a second trench and a third trench in the HM layer; andforming a first feature to fill in a section of the first trench between the second trench and the third trench.2. The method of claim 1 , further comprising:after forming the first feature, etching the material layer, by using the HM layer as an etch mask, to transfer the first trench, the second trench and third trench to the material layer.3. The method of claim 1 , wherein the first trench connects to the second trench ...

Method for coloring circuit layout and system for performing the same

Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.

Methods for Integrated Circuit Design and Fabrication

The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein. 1. A method comprising:forming a first pattern feature over a material layer by a first photolithographic process;forming a first spacer feature on a first sidewall of the first pattern feature and a second spacer feature on a second sidewall of the first pattern feature, the second sidewall opposing the first sidewall;removing a first portion of the first pattern feature to expose the material layer, wherein after removing the first portion of the first pattern feature a remaining portion of the first pattern feature remains disposed on the first and second spacer features; andpatterning the material layer using the remaining portion of the first pattern feature as a mask.2. The method of claim 1 , wherein the first spacer feature physically contacts the first sidewall and the second spacer feature physically contacts the second sidewall.3. The method of claim 1 , wherein the forming of the first pattern feature over the material layer by the first photolithographic process includes forming a second pattern feature over the material layer by the first photolithographic process claim 1 ,wherein the removing of the portion of the first pattern feature to expose the material layer occurs without removing the second pattern feature.4. The method of claim 3 , wherein the remaining portion of the first pattern feature includes a second portion disposed on the ...

Spacer etching process for integrated circuit design

A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a first patterning process; and forming a second plurality of trenches in the first layer by second patterning process, wherein a first trench of the second plurality merges with two trenches of the first plurality to form a continuous trench. The method further includes forming spacer features on sidewalls of the first and second pluralities of trenches. The spacer features have a thickness. A width of the first trench is equal to or less than twice the thickness of the spacer features thereby the spacer features merge inside the first trench.

Immersion optical projection system

An immersion optical projection system for photolithography is provided. A transparent plate is located between a last lens element and the wafer during a usage of the system. The transparent plate has a lens-side surface and a wafer-side surface. The system is adapted to have a layer of lens-side fluid located between the last lens element and the lens-side surface of the transparent plate, e.g., when the last lens element is operably located over the wafer during a photolithography process. The system is also adapted to have a layer of wafer-side fluid located between the wafer-side surface of the transparent plate and the wafer, during a usage of the system. The wafer-side fluid may or may not be fluidly connected to the lens-side fluid. The wafer-side fluid may or may not differ from the lens-side fluid.

Method and system for improving accuracy of critical dimension metrology

A method for improving accuracy of optical critical dimension measurement of a substrate is provided. A process parameter that influences the refractive index and extinction coefficient of a thin film in the substrate is identified. A refractive index and extinction coefficient across a plurality of wavelengths as a function of the process parameter is identified. During the regression modeling of the optical critical dimension measurement, the refractive index and extinction coefficient across the plurality of wavelengths is adjusted through the function via the process parameter.

Generating final mask pattern by performing inverse beam technology process

The present disclosure provides an integrated circuit (IC) method in accordance with some embodiments. The method includes receiving an IC design layout; and performing an inverse beam technology (IBT) process to the IC design layout, thereby generating a final mask pattern, wherein the IBT process uses a single IBT model to simulate both a mask making process and a wafer making process.

DECOMPOSING INTEGRATED CIRCUIT LAYOUT

Various embodiments of the invention provide techniques to ensure a layout for an integrated circuit is split-able. In a method embodiment, a layout is generated in a customer site having a layout library as inputs wherein the library provides exemplary layouts that have been verified to be spit-able and that can be used and layouts that can cause conflicts to avoid. A real-time odd cycle checker is also provided in which the checker identifies in real time conflict areas and odd cycles as they arise during layout generation. To reduce memory usage layouts of various devices may be separated so that each individual layout or a small number of layouts, rather than a large layout for the whole application circuit, can be checked against conflicts. Once the layout is ready at the customer site, it is sent to the foundry site to be decomposed into two masks and taped-out. Other embodiments are also disclosed.

Method and apparatus for extracting systematic defects

The present disclosure provides a method of systematic defect extraction. Primary and secondary areas are defined in a wafer layout. A plurality of defects is identified by a first wafer inspection for an outside-process-window wafer. Defects located in the secondary area are removed. Defects associated with non-critical semiconductor features are also removed via a grouping process. Sensitive regions are defined around defects associated with critical semiconductor features. A second inspection is then performed on the sensitive regions for an inside-process-window wafer, thereby identifying a plurality of potentially systematic defects. Thereafter, a Scanning Electron Microscopy (SEM) process is performed to determine whether the defects in the sensitive regions of the inside-process-window wafer are true systematic defects.

Methods for integrated circuit design and fabrication

The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.

Mechanisms for forming patterns using multiple lithography processes

The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate, a patterning-target layer over the substrate, and a hard mask layer over the patterning-target layer; forming a first pattern in the hard mask layer; removing a trim portion from the first pattern in the hard mask layer to form a trimmed first pattern; forming a first resist layer over the hard mask layer; forming a main pattern in the first resist layer; and etching the patterning-target layer using the main pattern and the trimmed first pattern as etching mask elements to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting a first overlapping portion between the main pattern and the trimmed first pattern.

OPTICAL PROXIMITY CORRECTION CONVERGENCE CONTROL

A method of optical proximity correction (OPC) convergence control that includes providing a lithography system having a photomask and an illuminator. The method further includes performing an exposure by the illuminator on the photomask. Also, the method includes optimizing an optical illuminator setting for the lithography system with a defined gate pitch in a first direction in a first template. Additionally, the method includes determining OPC correctors to converge the OPC results with a target edge placement error (EPE) to produce a first OPC setting for the first template. The first OPC setting targets a relatively small EPE and mask error enhancement factor (MEEF)of the defined gate pitch in the first template. In addition, the method includes checking the first OPC setting for a relatively small EPE, MEEF and DOM consistency with the first template of the defined gate pitch in a second, adjacent template. 1. A method for use in a lithography system including an optical illuminator with first and second templates , wherein the first and second templates are adjacent , the method comprising:performing an exposure by the illuminator on a photomask;optimizing an optical illuminator setting based, at least in part, on one or more of a numerical aperture, a sigma-in, a sigma-out, and a wave phase for the photomask with a defined gate pitch in a first direction in the first template;determining optical proximity correction (OPC) results for the photomask;determining one or more OPC correctors to converge the OPC results with a target edge placement error (EPE) to produce a first OPC setting for the first template, wherein the first OPC setting targets a relatively small EPE and mask error enhancement factor (MEEF) of the defined gate pitch in the first template;checking the first OPC setting for a relatively small EPE and a relatively small MEEF and dimension of mask (DOM) consistency of the defined gate pitch in the first direction in the second template,wherein ...

Lithography Using High Selectivity Spacers for Pitch Reduction

A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer. 1. A method comprising:patterning a dummy layer over a mask layer to form one or more dummy lines;forming a spacer layer over top surfaces and sidewalls of the one or more dummy lines, wherein the spacer layer comprises a transition metal oxide or a transition metal nitride;forming a first reverse material layer over the spacer layer, wherein the spacer layer and the first reverse material layer comprise different materials;patterning the first reverse material layer, wherein the patterning of the first reverse material layer comprises etching the first reverse material layer at a faster rate than the spacer layer;removing the one or more dummy lines; andpatterning the mask layer using the spacer layer and the first reverse material layer as a mask.2. The method of claim 1 , wherein patterning the dummy layer comprises:forming a hard mask layer and a bi-layered photoresist successively over the dummy layer, the bi-layered photoresist comprising a top layer and a bottom layer;patterning the top layer of the bi-layered photoresist to form a first pattern;transferring the first pattern of the top layer to the bottom layer of the bi-layered photoresist and to ...

Method of heating semiconductor wafer to improve wafer flatness

A method of heating-treating a semiconductor wafer is provided. In one embodiment, a first layer is formed over a first side of a substrate. A second layer is formed over the first layer and over a second side of the substrate and the wafer is then flash annealed. In another embodiment, a first layer is formed over a first side of a substrate and over a second side of the substrate. A second layer is formed over the first layers and the wafer is then flash annealed.

Method for metal correlated via split for double patterning

The embodiments of via mask splitting methods for double patterning technology described enable via patterning to align to a metal layer underneath or overlying to reduce overlay error and to increase via landing. If adjacent vias violate the G0-mask-split-rule for space or pitch (or both) between vias, the mask assignment of end vias are given higher priority to ensure good landing of end vias, since they are at higher risk of mislanding. The metal correlated via mask splitting methods enable better via performance, such as lower via resistance, and higher via yield.

Methods for patterning a target layer through fosse trenches using reverse sacrificial spacer lithography

The present disclosure describes methods for transferring a desired layout into a target layer on a semiconductor substrate. An embodiment of the methods includes forming a first desired layout feature as a first line over the target layer; forming a spacer around the first line; depositing a spacer-surrounding material layer; removing the spacer to form a fosse pattern trench surrounding the first line; and transferring the fosse pattern trench into the target layer to form a fosse feature trench in the target layer, wherein the fosse feature trench surrounds a first portion of the target layer that is underneath a protection layer. In some embodiments, the method further includes patterning a second desired layout feature of the desired layout into the target layer wherein the fosse feature trench and the protection layer serve to self-align the second desired layout feature with the first portion of the target layer.

Mechanisms for Forming Patterns Using Multiple Lithography Processes

The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern. 1. A method for forming patterns in a semiconductor device , comprising:providing a substrate and a patterning-target layer over the substrate;patterning the patterning-target layer to form a main pattern;forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer;patterning the hard mask layer to form a first cut pattern;patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern;transferring the combined cut pattern to the middle layer;etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer,wherein the final pattern includes the main pattern subtracting an intersection portion between the main pattern and the combined cut pattern.2. The method of claim 1 , wherein the patterning the patterning-target layer to form the main pattern includes:forming a first resist layer over the patterning-target layer;forming the ...

Method and system for improving critical dimension uniformity

A method for improving critical dimension uniformity of a wafer includes exposing a plurality of mask patterns on a first plurality of substrates at predetermined locations with common splits conditions of focus and exposure dose for each of the first plurality of substrates to form a plurality of perturbed wafers; measuring a critical dimension of the plurality of mask patterns at each of the predetermined locations for each of the plurality of perturbed wafers; averaging the critical dimension measured at each of the predetermined locations over the plurality of perturbed wafers to form a perturbed critical dimension map; measuring a sidewall angle of the plurality of mask patterns; averaging the sidewall angle measured to form a perturbed sidewall angle map; and providing the perturbed critical dimension map and the perturbed sidewall angle map to an exposure tool.

Apparatus and method for immersion lithography

Immersion lithography apparatus and method using a shield module are provided. An immersion lithography apparatus including a lens module having an imaging lens, a substrate table positioned beneath the lens module and configured for holding a substrate for processing, a fluid module for providing an immersion fluid to a space between the lens module and the substrate on the substrate table, and a shield module for covering an edge of the substrate during processing.

Illumination aperture filter design using superposition

A design method, based on the principle of superposition, is presented for complex apertures used to form a filter for condenser lens illumination in an optical reduction system. The method is relatively simple to implement and achieves near optimum results without the need to perform long and error prone calculations. Both OPE and DOF are simultaneously optimized over a wide range of duty ratios.

Line end spacing measurement

A method including: providing collinear first and second lines in a mask layer over a substrate, the first line having at one end a first line end and having a first line body adjacent the first line end, and the second line having at one end a second line end and having a second line body adjacent the second line end; measuring line widths of the first line body and the second line body; locating effective line end positions for the first line end based on the line width of the first line body and for the second line end based on the line width of the second line body; and measuring a distance between the effective line end positions, as an effective line end spacing.

Via Connection to a Partially Filled Trench

An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via. 1. A device comprising:a first dielectric layer disposed over a substrate;a second dielectric layer disposed over the first dielectric layer;a first metal feature disposed in the first dielectric layer;a second metal feature disposed in the second dielectric layer;a conductive via connecting the first metal feature to the second metal feature, wherein a top portion of the conductive via is offset from a bottom portion of the via; anda polymeric feature disposed in the first dielectric layer, wherein a top surface of the polymeric feature is coplanar with an interface between the first dielectric layer and the second dielectric layer2. Th device of claim 1 , wherein the first metal feature claim 1 , the second metal feature disposed and the conductive via are formed of the same material.3. The device of claim 1 , further comprising a third metal feature disposed in the first dielectric layer claim 1 , andwherein the polymeric feature is disposed over the third metal feature.4. The device of claim 3 , wherein the polymeric feature physically contacts the third metal feature.5. The device of claim 1 , wherein the first dielectric layer is formed of a different dielectric material than the second dielectric layer.6. The device of claim 1 , wherein the top portion of the conductive via is disposed within the second dielectric layer and the bottom portion of the conductive via is disposed within the first dielectric layer.7. The device of claim 1 , wherein the top portion of the conductive via has a bottommost surface facing the substrate and physically contacting the first dielectric layer ...

SELF-ALIGNED SEMICONDUCTOR FABRICATION WITH FOSSE FEATURES

The present disclosure describes methods for transferring a desired layout into a target layer on a semiconductor substrate. An embodiment of the methods includes forming a first desired layout feature as a first line over the target layer; forming a spacer around the first line; depositing a spacer-surrounding material layer; removing the spacer to form a fosse pattern trench surrounding the first line; and transferring the fosse pattern trench into the target layer to form a fosse feature trench in the target layer, wherein the fosse feature trench surrounds a first portion of the target layer that is underneath a protection layer. In some embodiments, the method further includes patterning a second desired layout feature of the desired layout into the target layer wherein the fosse feature trench and the protection layer serve to self-align the second desired layout feature with the first portion of the target layer. 1. A method comprising:forming a hard mask layer over a target layer;forming a patterned material layer over the target layer;forming a spacer on the patterned material layer;removing the spacer to form a fosse pattern trench adjacent the patterned material layer;performing a first etching of the target layer through the fosse pattern trench thereby forming a first trench in the target layer; andafter performing the first etching of the target layer, removing the patterned material layer while keeping a portion of the hard mask layer over a first portion of the target layer, the first portion of the target layer being surrounded by the first trench.2. The method of claim 1 , further comprising forming a plug material layer on the spacer.3. The method of claim 2 , wherein removing the patterned material layer while keeping the portion of the hard mask layer over the first portion of the target layer further includes removing the plug material layer.4. The method of claim 2 , wherein a portion of the plug material layer defines a first sidewall of the ...

Method of fabricating semiconductor device with reduced trench distortions

A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.

Photomask with wavelength reduction material and pellicle

Disclosed is a photomask comprising a transparent substrate, an absorption layer proximate to the transparent substrate, and a pellicle mounted proximate to the transparent substrate. The absorption layer has at least one opening formed therein for receiving a wavelength-reducing material (WRM). The wavelength-reducing material and the absorption layer form a generally planar surface.

Method and system for patterning alignment marks on a transparent substrate

Disclosed is a method and a system for forming alignment marks on a transparent substrate. A light reflective layer is deposited over an optically transparent substrate of a wafer. A region is defined around an alignment mark on the optically transparent substrate. The light reflective layer is removed from a substantial portion of the transparent substrate excluding the region. In addition, a micro electro-mechanical systems device is disclosed. The device comprises an optically transparent substrate, at least one optically partially transparent alignment mark on the optically transparent substrate, and a plurality of reflective elements or imaging pixels attached to the optically transparent substrate.

Patterning process and chemical amplified photoresist with a photodegradable base

A method for fabricating an integrated circuit device is disclosed. The method includes providing a substrate; forming a first material layer over the substrate; forming a second material layer over the first material layer, wherein the second material layer comprises a photodegradable base material; and exposing at least a portion of the second material layer.

Via connection to a partially filled trench

An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.

Via Connection to a Partially Filled Trench

An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via. 1. A method comprising:forming a first dielectric layer, wherein the first dielectric layer includes a first conductive feature, a second conductive feature, a first polymeric feature disposed on the first conductive feature and a second polymeric feature disposed on the second conductive feature;forming a second dielectric layer on the first dielectric layer;forming a first trench through the second dielectric layer to expose the second polymeric feature, wherein the first polymeric feature is covered by the second dielectric layer after the forming of the first trench through the second dielectric layer to expose the second polymeric feature;removing the exposed second polymeric feature to expose the second conductive feature, wherein the first polymeric feature is covered by the second dielectric layer after the removing of the exposed second polymeric feature to expose the second conductive feature; andforming a third conductive feature within the first trench on the exposed second conductive feature.2. The method of claim 1 , further comprising forming a second trench through the second dielectric layer claim 1 , wherein the second trench is in communication with the first trench.3. The method of claim 2 , wherein the second trench is wider than the first trench along a first axis that is substantially parallel to a top surface of the first dielectric layer.4. The method of claim 2 , wherein the first polymeric feature is covered by the second dielectric layer after the forming of the second trench through the second dielectric layer.5. The method of claim 2 , wherein the forming ...

Systems and Methods for a Sequential Spacer Scheme

The present disclosure describes methods for transferring a desired layout into a target layer. The method includes a step of forming a spacer, having a second width, around a first and a second desired layout feature pattern of the desired layout over a semiconductor substrate. The first desired layout feature pattern is formed using a first sub-layout and the second desired layout feature pattern is formed using a second sub-layout. The first and second desired layout feature patterns are separated by a first width. The method further includes forming a third desired layout feature pattern according to a third sub-layout. The third desired layout feature pattern is shaped in part by the spacer. The method further includes removing the spacer from around the first and second desired layout feature pattern and etching the target layer using the first, second, and third layout feature patterns as masking features. 1. A semiconductor device comprising:a substrate having a top surface and a bottom surface; and a first desired layout feature pattern, a second desired layout feature pattern, and a third desired layout feature pattern, each feature pattern being formed from a different sub-layout of the desired layout;', 'the second desired layout feature pattern includes a plug contacting a portion of the target material layer; and', 'the third desired layout feature pattern is separated from the first and second desired layout feature patterns by a minimum spacing., 'a target material layer over the substrate and patterned by a desired layout, wherein the desired layout includes2. The semiconductor device of claim 1 , wherein the target material layer includes material only between the substrate and the desired layout.3. The semiconductor device of claim 1 , wherein the first desired layout feature pattern is formed from a first material that is different from a second material from which the second and third desired layout feature patterns are formed.4. The ...

Multi-focus scanning with a tilted mask or wafer

A method for implementing discrete superpositioning of two or more defocal wafer images at different defocal positions in a lithographic step and scan projection system. The method includes tilting one of a mask and a wafer with respect to a scanning direction and splitting an illumination beam into at least two illumination areas which are in different defocus zones of the mask.

Method of fabricating semiconductor device

A method for fabricating a semiconductor device includes forming a hard mask (HM) layer over a material layer, forming a first trench in the HM layer, which extends along a first direction. The method also includes forming a first patterned resist layer over the HM layer. The first patterned resist layer has a first opening and a second opening a second direction. The first opening overlaps with the first trench in a middle portion of the first trench and the second opening overlaps with the first trench at an end portion of the first trench. The method also includes etching the HM layer through the first patterned resist layer to form a second trench and a third trench in the HM layer and forming a first feature to fill in a section of the first trench between the second trench and the third trench.

Multiple Directed Self-Assembly Patterning Process

Disclosed is a method of forming a target pattern for a semiconductor device using multiple directed self-assembly (DSA) patterning processes. The method includes receiving a substrate and forming a guide pattern over the substrate by performing a process that includes a first DSA process. The method further includes performing a second DSA process over the substrate using the guide pattern. In an embodiment, the first DSA process controls the first pitch of a dense pattern in a first direction and the second DSA process controls the second pitch of the dense pattern in a second direction. 1. A method of forming a target pattern for a semiconductor device , comprising:receiving a substrate;forming a guide pattern over the substrate by performing a process that includes a first directed self-assembly (DSA) process, wherein the first DSA process results in a first copolymer layer over the substrate, the first copolymer layer includes a first constituent polymer and a second constituent polymer, and the guide pattern corresponds to the first constituent polymer; andperforming a second DSA process over the substrate using the guide pattern.2. The method of claim 1 , wherein the forming of the guide pattern includes:forming a first layer over the substrate;forming a second layer over the first layer;patterning the second layer thereby forming first trenches in the second layer; andforming the first copolymer layer in the first trenches by the first DSA process.3. The method of claim 2 , wherein the first DSA process includes:depositing a first copolymer material in the first trenches, wherein the first copolymer material is directed self-assembling; andinducing microphase separation within the first copolymer material thereby defining the first constituent polymer and the second constituent polymer.4. The method of claim 2 , wherein the forming of the guide pattern further includes:selectively removing the first constituent polymer from the first copolymer layer, ...

Method of Fabricating Semiconductor Device with Reduced Trench Distortions

A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench. 1. A method comprising:forming a material layer over a substrate;forming a first hard mask (HM) layer over the material layer;forming a first trench in the first HM layer, wherein the first trench extends along a first direction;forming a first spacer layer in the first trench;forming a second trench in the first HM layer, wherein the first spacer layer is disposed within the first trench during the forming of the second trench;removing a first portion of the material layer to extend the first trench into the material layer and removing a second portion of the material layer to extend the second trench into the material layer;removing the first HM layer and the first spacer layer;forming a second HM layer over the material layer;forming a third trench in the second HM layer, wherein the third trench extends along a second direction that is different than the first direction, wherein the third trench overlaps the extended first trench; andremoving a third portion of the material layer through the third trench.2. The method of claim 1 , further comprising forming a conductive layer over the substrate claim 1 , wherein ...

Method of patterning a feature of a semiconductor device

A method including forming a first pattern having a first and second feature is described. A masking layer is formed over the first and second features. An opening is patterned in the masking layer. The opening can extend over at least one of the first and second features. The patterned opening is then used to form a third feature (filled trench) between the first and second features. A second pattern is then formed that includes a fourth feature and fifth feature each having an edge defined by the third feature. The first, second, fourth and fifth features may then be used to pattern an underlying layer over the semiconductor substrate.

Intensity selective exposure photomask

An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage.

Patterning process and photoresist with a photodegradable base

A resist material and methods using the resist material are disclosed herein. An exemplary method includes forming a resist layer over a substrate, wherein the resist layer includes a polymer, a photoacid generator, an electron acceptor, and a photodegradable base; performing an exposure process that exposes portions of the resist layer with radiation, wherein the photodegradable base is depleted in the exposed portions of the resist layer during the exposure process; and performing an developing process on the resist layer.

EXTRACTION OF SYSTEMATIC DEFECTS

In one embodiment, a method for extracting systematic defects is provided. The method includes inspecting a wafer outside a process window to obtain inspection data, defining a defect pattern from the inspection data, filtering defects from design data using a pattern search for the defined defect pattern within the design data, inspecting defects inside the process window with greater sensitivity than outside the process window, and determining systematic defects inside the process window. A computer readable storage medium, and a system for extracting systematic defects are also provided. 1. A method of extracting systematic defects , the method comprising:inspecting a wafer outside a process window to obtain inspection data;defining a defect pattern from the inspection data;filtering defects from design data using a pattern search for the defined defect pattern within the design data;inspecting defects inside the process window with greater sensitivity than outside the process window; anddetermining systematic defects inside the process window.2. The method of claim 1 , wherein inspecting the wafer outside the process window includes inspecting the wafer outside an active area of the wafer.3. The method of claim 1 , wherein inspecting the wafer outside the process window includes inspecting the wafer inside a dummy area of the wafer.4. The method of claim 1 , further comprising:defining an enhanced inspection area on the wafer.5. The method of claim 1 , further comprising:filtering nuisance defects from outside the process window.6. The method of claim 1 , further comprising:importing defects data different than the defined defect pattern from the inspection data.7. The method of claim 1 , further comprising:filtering the systematic defects from the design data.8. The method of claim 1 , further comprising:inspecting the wafer outside and inside the process window to obtain first and second inspection data, respectively, and an intersection of defects; ...

METHOD FOR METAL CORRELATED VIA SPLIT FOR DOUBLE PATTERNING

A method of via patterning mask assignment for a via layer using double patterning technology, the method includes determining, using a processor, if a via of the via layer intercepts an underlying or overlaying metal structure assigned to a first metal mask. If the via intercepts the metal structure assigned to the first metal mask, assigning the via to a first via mask, wherein the first via mask aligns with the first metal mask. Otherwise, assigning the via to a second via mask, wherein the second via mask aligns with a second metal mask different from the first metal mask. 1. A method of via patterning mask assignment for a via layer using double patterning technology , said method comprising: if the via intercepts the metal structure assigned to the first metal mask, assigning the via to a first via mask, wherein the first via mask aligns with the first metal mask,', 'otherwise, assigning the via to a second via mask, wherein the second via mask aligns with a second metal mask different from the first metal mask., 'determining, using a processor, if a via of the via layer intercepts an underlying or overlaying metal structure assigned to a first metal mask,'}2. The method of claim 1 , wherein vias of the via layer align with respective underlying or overlaying metal structures to improve at least one of via landing claim 1 , via resistance claim 1 , or via yield3. The method of claim 1 , further comprising claim 1 , before said determining:assigning the underlying or overlaying metal structure to the first metal mask; andassigning a further underlying or overlaying metal structure to the second metal mask4. The method of claim 1 , further comprising:aligning the second metal mask with the first metal mask.5. The method of claim 1 , further comprising:limiting vias that intercept the same underlying or overlaying metal structures to have pitches equal to or greater than a distance specified by a via-mask-split rule, wherein adjacent vias with pitches less than ...

System and method for alignment in semiconductor device fabrication

A method of determining overlay error in semiconductor device fabrication includes receiving an image of an overlay mark formed on a substrate. The received image is separated into a first image and a second image, where the first image includes representations of features formed on a first layer of the substrate and the second image includes representations of the features formed on a second layer of the substrate. A quality indicator is determined for the first image and a quality indicator is determined for the second image. In an embodiment, the quality indicators include asymmetry indexes

Method of merging color sets of layout

A method includes determining one or more potential merges corresponding to a color set A i and a color set A j of N color sets, represented by A 1 to A N , used in coloring polygons of a layout of an integrated circuit. N is a positive integer, i and j are integers from 1 to N, and i≠j. One or more potential cuts corresponding to the color set A i and the second color set A j are determined. An index A ij is determined according to the one or more potential merges and the one or more potential cuts. A plurality of parameters F related to the index A ij is obtained based on various values of indices f i and f j . A parameter F is selected among the plurality of parameters F based on a definition of the index A ij .

Spacer Etching Process for Integrated Circuit Design

A method includes forming a first material layer on a substrate and performing a first patterning process using a first layout to form a first plurality of trenches in the first material layer. The method further includes performing a second patterning process using a second layout to form a second plurality of trenches in the first material layer, wherein the second layout a cut pattern for the first layout. The method further includes forming spacer features on sidewalls of both the first and second pluralities of trenches, wherein the spacer features have a thickness and the cut pattern corresponds to a first trench of the second plurality whose width is less than twice the thickness of the spacer features. The method further includes removing the first material layer; forming a second material layer on the substrate and within openings defined by the spacer features; and removing the spacer features. 1. A method , comprising:forming a first material layer on a substrate;performing a first patterning process using a first layout to form a first plurality of trenches in the first material layer, the first layout including a first subset of a target pattern;performing a second patterning process using a second layout to form a second plurality of trenches in the first material layer, the second layout including a second subset of the target pattern and a cut pattern for the first subset;forming spacer features on sidewalls of both the first plurality of trenches and the second plurality of trenches, the spacer features having a thickness, wherein the cut pattern corresponds to a first trench of the second plurality whose width is less than twice the thickness of the spacer features;removing the first material layer;forming a second material layer on the substrate and within openings defined by the spacer features; andremoving the spacer features.2. The method of claim 1 , wherein the forming of the second material layer includes:forming the second material layer by ...

METHOD FOR COLORING CIRCUIT LAYOUT AND SYSTEM FOR PERFORMING THE SAME

Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features. 1. A mask data generation apparatus , comprising:a non-transitory computer-readable memory storing a program and a design rule checker; anda processor operatively coupled with the memory,wherein the program, when executed by the processor, causes the processor to perform:identifying target networks in a circuit layout, each of the target networks having two or more linked nodes representing circuit patterns, each of the target networks being presented in an imaginary X-Y coordinate plane;determining a starting node in each of the target networks using a coordinate-based method;assigning a first feature to the starting node as a first node in each of the target networks and assigning the first feature and a second feature to remaining nodes in each target network so that any two immediately adjacent linked nodes in each target network have different features; andoutputting mask data based on the first feature and the second feature.2. The mask data generation apparatus of claim 1 , wherein the assigning the first feature and the second feature comprises a coordinate-based method including:(i) assigning the first feature to the first node in each of the target networks;(ii) assigning the ...

Lithography Using High Selectivity Spacers for Pitch Reduction

A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer.

LAYOUT DECOMPOSITION METHOD

A method of assigning layout patterns includes identifying a first set of layout patterns of a current layout design that is new or has been modified in comparison with a reference layout design. A second set of layout patterns of the current layout design is identified. A member of the second set of layout patterns that is not a member of the first set of layout patterns has a distance, less than a predetermined threshold distance, to at least another member of the second set of layout patterns. A third set of layout patterns is not modified in comparison with the reference layout design. The third set of layout patterns is assigned to a plurality of masks according to the reference pattern-assigning result. 1. A method of assigning layout patterns of a current layout design for an integrated circuit to a plurality of masks , the method comprising:identifying a first set of layout patterns among the layout patterns of the current layout design that is new or has been modified in comparison with a reference layout design;identifying a second set of layout patterns among the layout patterns of the current layout design, the second set of layout patterns including the first set of layout patterns and wherein a member of the second set of layout patterns that is not a member of the first set of layout patterns has a distance, less than a predetermined threshold distance, to at least another member of the second set of layout patterns; andassigning a third set of layout patterns among the layout patterns of the current layout design to the plurality of masks according to a reference pattern-assigning result of the reference layout design, the third set of layout patterns being not modified in comparison with the reference layout design,wherein at least one of the identifying a first set, identifying a second set, or assigning a third set is performed by using a hardware processor.2. The method of claim 1 , further comprising:setting one or more preference parameters for ...

Method for coloring circuit layout and system for performing the same

Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.

Method of Mask Data Synthesis and Mask Making

The present disclosure provides an integrated circuit (IC) method in accordance with some embodiments. The method includes receiving an IC design layout; and performing an inverse beam technology (IBT) process to the IC design layout, thereby generating a final mask pattern, wherein the IBT process uses a single IBT model to simulate both a mask making process and a wafer making process. 1. An integrated circuit (IC) method comprising:receiving an IC design layout; andperforming an inverse beam technology (IBT) process to the IC design layout, thereby generating a final mask pattern, wherein the IBT process uses a single IBT model to simulate both a mask making process and a wafer making process.2. The method of claim 1 , further comprising forming a final wafer pattern according to the IC design layout claim 1 , wherein the final wafer pattern is a desired wafer pattern to be formed on a semiconductor wafer.3. The method of claim 2 , wherein the IBT model is defined in a formula P(x claim 2 , y)=Φ(Φ(Φ(f(x claim 2 , y)))) claim 2 , whereinP(x, y) defines a simulated wafer contour;f(x, y) defines an electron-beam shot map;{'sub': '1', 'Φdefines a mask making function that simulates the mask making process;'}{'sub': '2', 'Φdefines a wafer imaging function that simulates an imaging of the mask on the semiconductor wafer during the a lithography exposing process; and'}{'sub': '3', 'φdefines a wafer pattern function that simulates characteristics of a photoresist coated on the semiconductor wafer.'}7. The method of claim 2 , wherein the forming of the final wafer pattern includes adding dummy features to the IC design layout claim 2 , wherein the dummy features are added to tune pattern density for improved fabrication effect.8. The method of claim 2 , further comprising performing a fracturing process to the final mask pattern claim 2 , thereby generating an electron-beam shot map to be used in an electron-beam lithography process to pattern a mask.9. The method of ...

METHOD OF FABRICATING SEMICONDUCTOR DEVICE WITH REDUCED TRENCH DISTORTIONS

A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench. 1. A method comprising:forming a first material layer over a substrate;forming a first hard mask layer over the first material layer;forming a first trench in the first hard mask layer, wherein the first trench extends along a first direction;after forming the first trench in the first hard mask layer, forming a patterned resist layer on the first hard mask layer including within the first trench;forming a second trench in the first hard mask layer while using the patterned resist layer as a mask;removing the patterned resist layer;removing a first portion of the first material layer to extend the first trench into the first material layer and removing a second portion of the first material layer to extend the second trench into the first material layer to thereby forming a patterned first material layer;after removing the first portion and the second portion of the first material layer, removing the first hard mask layer;forming a patterned second material layer over the patterned first material layer;forming a third trench extending through the patterned second material, wherein the third trench extends along a ...

Photomask and method for fabricating integrated circuit

A photomask and method for fabricating an integrated circuit is provided. The photomask includes a plurality of main features, enclosed in at least one first region and at least one second region, wherein the first region comprises single the main feature and the second region comprises multiple the main features; and a plurality of assistant features disposed between the first region and the second region, or between the second regions. The photomask enhances the accuracy of the critical dimension and facilitate fabricating an integrated circuit.

Lithography Process and System with Enhanced Overlay Quality

The present disclosure provides a method. The method includes forming a resist layer on a patterned substrate; collecting first overlay data from the patterned substrate; determining an overlay compensation based on mapping of second overlay data from an integrated circuit (IC) pattern to the first overlay data from the patterned substrate; performing a compensation process to a lithography system according to the overlay compensation; and thereafter performing a lithography exposing process to the resist layer by the lithography system, thereby imaging the IC pattern to the resist layer. 1. A method , comprising:forming a resist layer on a patterned substrate;collecting first overlay data from the patterned substrate;determining an overlay compensation based on mapping of second overlay data from an integrated circuit (IC) pattern to the first overlay data from the patterned substrate;performing a compensation process to a lithography system according to the overlay compensation; andperforming a lithography exposing process to the resist layer by the lithography system, thereby imaging the IC pattern to the resist layer.2. The method of claim 1 , wherein the collecting of the first overlay data from the patterned substrate includes collecting the first overlay data from at least one overlay metrology tool.3. The method of claim 1 , wherein the collecting of the first overlay data from the patterned substrate includes collecting the first overlay data from the patterned substrate when the patterned substrate is secured on alignment wafer stages of the lithography system.4. The method of claim 3 , wherein a number of the alignment wafer stages integrated in the lithography system is chosen such that the collecting of the first overlay data and the performing of the lithography exposing process are substantially matched in terms of processing time without impacting throughput of the lithography exposing process executed by the lithography system.5. The method of claim ...

Spacer Etching Process for Integrated Circuit Design

A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a first patterning process; and forming a second plurality of trenches in the first layer by second patterning process, wherein a first trench of the second plurality merges with two trenches of the first plurality to form a continuous trench. The method further includes forming spacer features on sidewalls of the first and second pluralities of trenches. The spacer features have a thickness. A width of the first trench is equal to or less than twice the thickness of the spacer features thereby the spacer features merge inside the first trench. 1. A method , comprising:forming a first layer on a substrate;forming a first plurality of trenches in the first layer by a first patterning process;forming a second plurality of trenches in the first layer by a second patterning process, resulting in combined trench patterns in the first layer, wherein a first trench of the second plurality merges with two trenches of the first plurality to form a continuous trench; andforming spacer features on sidewalls of the combined trench patterns, the spacer features having a thickness, wherein a width of the first trench is equal to or less than twice the thickness of the spacer features, thereby the spacer features merge inside the first trench.2. The method of claim 1 , further comprising:removing the first layer; andetching the substrate using the spacer features as an etch mask.3. The method of claim 1 , further comprising:removing the first layer;forming a second layer over the substrate and within openings defined by the spacer features; andremoving the spacer features.4. The method of claim 3 , wherein the forming of the second layer includes:spin coating a material layer over the substrate and within the openings defined by the spacer features; andselectively etching back the material layer to expose the spacer features, wherein remaining portions of the ...

Directional Patterning Methods

Directional patterning methods are disclosed herein. An exemplary method includes performing a lithography process to form a pattered hard mask layer over a wafer, wherein the patterned hard mask layer includes a hard mask feature having an associated horizontally-defined characteristic; tuning an etching process to direct etching species in a substantially horizontal direction relative to a horizontal surface of the wafer, such that the etching process horizontally removes portions of the patterned hard mask layer, thereby modifying the horizontally-defined characteristic of the hard mask feature; and forming an integrated circuit feature that corresponds with the hard mask feature having the modified horizontally-defined characteristic. Horizontally-defined characteristic can include a length, a width, a line edge roughness, a line width roughness, a line end profile, other horizontally-defined characteristics, or combinations thereof. In some implementations, the directional patterning method disclosed herein can achieve oblique interconnects and/or slot (rectangular) via interconnects. 1. A method comprising:forming a patterned hard mask layer over a wafer, wherein the patterned hard mask layer includes a hard mask feature; andperforming a surface directional etching process to modify a horizontal profile of the hard mask feature, wherein the surface directional etching process directs etching species in a substantially horizontal direction relative to a horizontal surface of the wafer.2. The method of claim 1 , further comprising forming an integrated circuit feature that corresponds with the hard mask feature.3. The method of claim 1 , wherein the surface directional etching process directs the etching species towards a horizontal surface of the wafer at an angle θ that is less than about 10° relative to a horizontal plane that is substantially parallel to the horizontal surface.4. The method of claim 1 , wherein the surface directional etching process further ...

METHOD FOR COLORING CIRCUIT LAYOUT AND SYSTEM FOR PERFORMING THE SAME

Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features. 1. A method , comprising:identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane;assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method; andassigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.2. The method of claim 1 , wherein the circuit patterns in the circuit layout are separable into two photomasks and a distance between any two immediately adjacent linked nodes in each target network is less than a minimum separation distance.3. The method of claim 2 , wherein the minimum separation distance is about 70 nm to about 120 nm.4. The method of claim 1 , wherein the first node has lowest X coordinate and lowest Y coordinate.5. The method of claim 1 , wherein the first node has lowest X coordinate and largest Y coordinate.6. The method of claim 1 , wherein the first node has largest X coordinate and lowest Y ...

Lithography Using High Selectivity Spacers for Pitch Reduction

A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer. 1. A method for patterning a semiconductor device comprising:patterning a dummy layer over a hard mask to form one or more dummy lines;forming a sidewall aligned spacer conformably over the one or more dummy lines and the hard mask;forming a first reverse material layer over the sidewall aligned spacer, wherein a material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer;forming a first photoresist over the first reverse material layer;patterning the first photoresist;selectively etching the first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched;removing the one or more dummy lines; andpatterning the hard mask using the sidewall aligned spacer and the first reverse material layer as a mask.2. The method of claim 1 , wherein the material used for forming the sidewall aligned spacer is titanium nitride or titanium oxide.3. The method of claim 1 , wherein the material used for forming the first reverse material layer is spin on glass (SOG).4. The method of claim 1 , wherein the patterning the dummy layer comprises ...

Mechanisms for Forming Patterns Using Lithography Processes

The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate, a patterning-target layer over the substrate, and a hard mask layer over the patterning-target layer; forming a first pattern in the hard mask layer; removing a trim portion from the first pattern in the hard mask layer to form a trimmed first pattern; forming a first resist layer over the hard mask layer; forming a main pattern in the first resist layer; and etching the patterning-target layer using the main pattern and the trimmed first pattern as etching mask elements to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting a first overlapping portion between the main pattern and the trimmed first pattern. 1. A method for forming patterns in a semiconductor device , the method comprising:providing a substrate, a patterning-target layer over the substrate, and a hard mask layer over the patterning-target layer;forming and patterning a first resist layer above the hard mask layer according to a first pattern;first etching the hard mask layer using the patterned first resist layer to produce a first patterned hard mask layer;after first etching, removing the patterned first resist layer;forming and patterning a second resist layer above the first patterned hard mask layer according to a second pattern; andsecond etching the first patterned target layer using the patterned second resist layer to produce a final patterned hard mask layer, different from the first patterned hard mask layer;wherein the final pattern includes the first pattern subtracting a first overlapping portion between the first pattern and the second pattern.2. The method of claim 1 , wherein the patterning-target layer has a thickness in a range from about 5 nm to about 50 nm.3. The method of claim 1 , wherein the hard mask layer is from the group ...

Photomask and method for fabricating integrated circuit

A photomask and method for fabricating an integrated circuit is provided. A design layout is provided, wherein the design layout has a plurality of main features. A plurality of assistant features are added in an assistant region of the design layout to form a first layout, wherein the assistant region has no main feature and a width of the assistant region is larger than five times of a width of the main feature. A plurality of optical proximity correction (OPC) features are added on the first layout to form a second layout. And a photomask is formed according to the second layout.

Self-Alignment for Two or More Layers and Methods of Forming Same

Embodiments of the present disclosure include self-alignment of two or more layers and methods of forming the same. An embodiment is a method for forming a semiconductor device including forming at least two gates over a substrate, forming at least two alignment structures over the at least two gates, forming spacers on the at least two alignment structures, and forming a first opening between a pair of the at least two alignment structures, the first opening extending a first distance from a top surface of the substrate. The method further includes filling the first opening with a first conductive material, forming a second opening between the spacers of at least one of the at least two alignment structures, the second opening extending a second distance from the top surface of the substrate, and filling the second opening with a second conductive material. 1. A structure comprising:a first gate and a second gate over a substrate, the first and second gates each comprising a gate electrode, a hard mask over the gate electrode, and spacers on opposing sidewalls of the gate electrode and hard mask;an interlayer dielectric (ILD) over the first and second gates and the substrate, the ILD having a top surface, the top surface of the ILD being substantially planar; anda first contact extending from the top surface of the ILD to contact the gate electrode of the first gate, the first contact having tapered sidewalls in the ILD and substantially parallel sidewalls in the hard mask of the first gate.2. The structure of further comprising:a second contact extending from the top surface of the ILD to contact a first portion of the substrate.3. The structure of claim 2 , wherein the second contact has tapered sidewalls from the top surface the ILD to the first portion of the substrate.4. The structure of claim 2 , wherein the first portion of the substrate is between the first and second gates.5. The structure of claim 2 , wherein the first portion of the substrate comprises a ...

Mask Assignment Optimization

A method for optimizing mask assignment for multiple pattern processes includes, through a computing system, defining which of a number of vias to be formed between two metal layers are critical based on metal lines interacting with the vias, determining overlay control errors for an alignment tree that defines mask alignment for formation of the two metal layers and the vias, and setting both the alignment tree and mask assignment for the vias so as to maximize the placement of critical vias on masks that have less overlay control error to the masks forming the relevant metal lines. 1. A method for optimizing mask assignment for multiple pattern processes , the method comprising:through a computing system, defining which of a number of vias to be formed between two metal layers are critical based on metal lines interacting with the vias;through the computing system, determining overlay control errors for an alignment tree that defines mask alignment for formation of the two metal layers and the vias; andthrough the computing system, setting both the alignment tree and mask assignment for the vias so as to maximize the placement of critical vias on masks that have less overlay control error to the masks forming the relevant metal lines.2. The method of claim 1 , wherein a critical via is a via that interacts with a metal line that is narrower than a predetermined width.3. The method of claim 2 , wherein a via defined as critical due to an interacting line is assigned to a via layer mask that is aligned to a metal layer mask for the interacting metal line for that critical via.4. The method of claim 1 , wherein a critical via is defined as a via that is placed within a predetermined distance from a non-interacting metal line.5. The method of claim 4 , wherein a via defined as critical due to a non-interacting metal line is assigned to a via layer mask that is aligned to the non-interacting metal line.6. The method of claim 1 , wherein the mask assignment is done ...

Multi-Layer Metal Contacts

A method for forming metal contacts within a semiconductor device includes forming a first-layer contact into a first dielectric layer that surrounds at least one gate electrode, the first-layer contact extending to a doped region of an underlying substrate. The method further includes forming a second dielectric layer over the first dielectric layer and forming a second-layer contact extending through the second dielectric layer to the first-layer contact.

Spacer Etching Process For Integrated Circuit Design

A method of forming a target pattern includes forming a first material layer on a substrate; performing a first patterning process using a first layout to form a first plurality of trenches in the first material layer; performing a second patterning process using a second layout to form a second plurality of trenches in the first material layer; forming spacer features on sidewalls of both the first plurality of trenches and the second plurality of trenches, the spacer features having a thickness; removing the first material layer; etching the substrate using the spacer features as an etch mask; and thereafter removing the spacer features. The target pattern is to be formed with the first layout and the second layout. 1. A method of forming a target pattern for an integrated circuit , the method comprising:forming a first material layer on a substrate;performing a first patterning process using a first layout to form a first plurality of trenches in the first material layer;performing a second patterning process using a second layout to form a second plurality of trenches in the first material layer;forming spacer features on sidewalls of both the first plurality of trenches and the second plurality of trenches, the spacer features having a thickness;removing the first material layer;etching the substrate using the spacer features as an etch mask; andthereafter removing the spacer features;wherein the target pattern is formed with the first layout and the second layout.2. The method of claim 1 , wherein a portion of the first plurality of trenches is merged with a portion of the second plurality of trenches;3. The method of claim 1 , wherein forming the spacer features results in cut features for the target pattern wherein a portion of the trenches have a width less than twice the thickness of the spacer features.4. The method of claim 1 , wherein performing the first patterning process using the first layout includes:forming a second material layer over the first ...

Method of Patterning a Feature of a Semiconductor Device

A method including forming a first pattern having a first and second feature is described. A masking layer is formed over the first and second features. An opening is patterned in the masking layer. The opening can extend over at least one of the first and second features. The patterned opening is then used to form a third feature (filled trench) between the first and second features. A second pattern is then formed that includes a fourth feature and fifth feature each having an edge defined by the third feature. The first, second, fourth and fifth features may then be used to pattern an underlying layer over the semiconductor substrate. 1. A method , comprising:forming a first pattern over a semiconductor substrate having a target layer, wherein the first pattern includes a first feature and a second feature;after forming the first pattern, forming a trench between the first and second features;filling the trench with a first material, thereby forming a filled trench;after filling the trench, forming a second pattern over the semiconductor substrate, wherein the second pattern includes a third feature and a fourth feature, wherein the filled trench abuts and interposes the third and fourth features; andremoving a material comprising the first, second, third and fourth features to form a first, second, third and fourth openings and using the first, second, third and fourth openings as a masking element to pattern the target layer.2. The method of claim 1 , wherein forming the first pattern includes forming a conformal layer over the first and second feature.3. The method of claim 1 , wherein the first and second features are photoresist.4. The method of claim 1 , wherein the material comprising the first claim 1 , second claim 1 , third and fourth features includes photoresist.5. The method of claim 1 , wherein the first material includes a silicon-containing antireflective coating (Si-ARC).6. The method of claim 1 , wherein forming the trench between the first and ...

Method for Integrated Circuit Patterning

A method of forming a target pattern includes forming a mandrel pattern on a substrate, the mandrel pattern having a line with a first dimension in a first direction and a second dimension in a second direction; forming a spacer around the mandrel pattern, the spacer having a first width; forming a cut pattern over the mandrel pattern and the spacer wherein the cut pattern partially overlaps the spacer on both sides of the line in the first direction; etching the mandrel pattern using the cut pattern as an etch mask, thereby defining a plurality of openings with sidewalls of the spacer, the cut pattern, and a portion of the mandrel pattern underneath the cut pattern; and reducing the first width of the spacer thereby to enlarge the plurality of openings. 1. A method of forming a target pattern for an integrated circuit , the method comprising:forming a mandrel pattern on a substrate, the mandrel pattern having a line with a first dimension in a first direction and a second dimension in a second direction;forming a spacer around the mandrel pattern, the spacer having a first width;forming a cut pattern over the mandrel pattern and the spacer, wherein the cut pattern partially overlaps the spacer on both sides of the line in the first direction;removing at least a portion of the mandrel pattern to define a plurality of openings; andreducing the first width of the spacer thereby enlarging the plurality of openings.2. The method of claim 1 , further comprising claim 1 ,reducing the first dimension of the line before forming the spacer, including etching sidewalls of the line in the first direction.3. The method of claim 1 , wherein forming the spacer around the mandrel pattern includes deposition and an anisotropic etching process.4. The method of claim 1 , wherein the first width of the spacer is at least two and half times greater than the first dimension of the line.5. The method of claim 1 , wherein reducing the first width of the spacer includes etching sidewalls ...

Method and Apparatus for Extracting Systematic Defects

The present disclosure provides a method of systematic defect extraction. Primary and secondary areas are defined in a wafer layout. A plurality of defects is identified by a first wafer inspection for an outside-process-window wafer. Defects located in the secondary area are removed. Defects associated with non-critical semiconductor features are also removed via a grouping process. Sensitive regions are defined around defects associated with critical semiconductor features. A second inspection is then performed on the sensitive regions for an inside-process-window wafer, thereby identifying a plurality of potentially systematic defects. Thereafter, a Scanning Electron Microscopy (SEM) process is performed to determine whether the defects in the sensitive regions of the inside-process-window wafer are true systematic defects. 1. A method , comprising:defining a primary area and a secondary area in a wafer layout;identifying a plurality of defects by performing a first inspection on the primary area and the secondary area for an outside-process-window wafer;performing a first nuisance defect filtering process by removing the defects in the secondary area;thereafter performing a grouping process to the defects outside the secondary area to separate the defects into a plurality of groups, wherein the defects that are grouped together have substantially similar characteristics;determining one or more groups of the defects that are associated with non-critical semiconductor features;performing a second nuisance defect filtering process by removing the one or more groups of the defects that are associated with non-critical semiconductor features;thereafter defining localized regions around remaining groups of the defects on the wafer layout;thereafter performing a second inspection on the localized regions for an inside-process-window wafer, thereby identifying a plurality of potentially systematic defects; andvisually examining each of the defects in the localized ...

Via Connection to a Partially Filled Trench

An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via. 1. An integrated circuit structure comprising:a first metal feature formed into a first dielectric layer;a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer; anda via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.2. The integrated circuit structure of claim 1 , wherein the offset is positioned to be coplanar with an interface between the first dielectric layer and the second dielectric layer.3. The integrated circuit structure of claim 1 , further comprising a third metal feature formed in the first dielectric layer.4. The integrated circuit structure of claim 3 , wherein the third metal feature is isolated from the first metal feature by the first dielectric layer.5. The integrated circuit structure of claim 3 , wherein the third metal feature has a top surface below a top surface of the first dielectric layer.6. The integrated circuit structure of claim 3 , wherein the third metal feature has a bottom surface being coplanar with a bottom surface of the first metal feature.7. The integrated circuit structure of claim 1 , further comprising claim 1 , an etch stop layer positioned between the first dielectric layer and the second dielectric layer.8. An integrated circuit comprising:a first dielectric layer;a first trench within the first dielectric layer;a first metal feature disposed within a bottom portion of the first trench;a second dielectric layer disposed on the first dielectric layer;a second metal ...

Multi-Layer Metal Contacts

A method for forming metal contacts within a semiconductor device includes forming a first-layer contact into a first dielectric layer that surrounds at least one gate electrode, the first-layer contact extending to a doped region of an underlying substrate. The method further includes forming a second dielectric layer over the first dielectric layer and forming a second-layer contact extending through the second dielectric layer to the first-layer contact. 1. A method comprising:forming a hard mask layer directly on opposing sidewalls of a gate electrode that is disposed over a substrate;forming a first dielectric layer over the gate electrode;forming a second dielectric layer over the hard mask layer and the first dielectric layer;forming a trench extending through the second dielectric layer, the first dielectric layer, and the hard mask layer, wherein the hard mask layer defines a sidewall of the trench while physically contacting the opposing sidewalls of the gate electrode;forming a first contact in the trench;forming a third dielectric layer over the first dielectric layer; andforming a second contact extending through the second dielectric layer to the first contact.2. The method of claim 1 , wherein the first contact has a top surface facing away from the substrate claim 1 , andwherein the second contact and the third dielectric layer physically contact the top surface of the first contact.3. The method of claim 1 , further comprising removing the second dielectric layer prior to forming the third dielectric layer over the first dielectric layer.4. The method of claim 1 , further comprising forming an etch stop layer over the hard mask layer.5. The method of claim 4 , wherein forming the etch stop layer over the hard mask layer includes forming the etch stop layer directly on the hard mask layer and the first dielectric layer.6. The method of claim 4 , further comprising removing the etch stop layer prior to forming the third dielectric layer over the first ...

Fin patterning methods for increased process margin

A method for fabricating a semiconductor device includes forming a plurality of first spacers over a substrate. A second spacer of a plurality of second spacers is deposited on sidewalls of each first spacer. In some embodiments, a spacing between adjacent first spacers is configured such that second spacers formed on sidewalls of the adjacent first spacers physically merge to form a merged second spacer. A second spacer cut process may be performed to selectively remove at least one second spacer. In some embodiments, a third spacer of a plurality of third spacers is formed on sidewalls of each second spacer. A third spacer cut process may be performed to selectively remove at least one third spacer. A first etch process is performed on the substrate to form fin regions. The plurality of third spacers mask portions of the substrate during the first etch process.

MECHANISMS FOR FORMING PATTERNS USING MULTIPLE LITHOGRAPHY PROCESSES

The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate, a patterning-target layer over the substrate, and a hard mask layer over the patterning-target layer; forming a first pattern in the hard mask layer; removing a trim portion from the first pattern in the hard mask layer to form a trimmed first pattern; forming a first resist layer over the hard mask layer; forming a main pattern in the first resist layer; and etching the patterning-target layer using the main pattern and the trimmed first pattern as etching mask elements to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting a first overlapping portion between the main pattern and the trimmed first pattern. 1. A method for forming patterns in a semiconductor device , comprising:providing a substrate, a patterning-target layer over the substrate, and a hard mask layer over the patterning-target layer;forming a first pattern in the hard mask layer;removing a trim portion from the first pattern in the hard mask layer to form a trimmed first pattern;forming a first resist layer over the hard mask layer;forming a main pattern in the first resist layer; andetching the patterning-target layer using the main pattern and the trimmed first pattern as etching mask elements to form a final pattern in the patterning-target layer,wherein the final pattern includes the main pattern subtracting a first overlapping portion between the main pattern and the trimmed first pattern.2. The method of claim 1 , wherein the forming the first pattern includes:forming a second resist layer over the hard mask layer;forming the first pattern in the second resist layer; andetching the hard mask layer using the second resist layer as an etching mask to form the first pattern in the hard mask layer.3. The method of claim 1 , wherein the removing the trim ...

METHOD OF PATTERNING A FEATURE OF A SEMICONDUCTOR DEVICE

A method including forming a trench over a layer disposed on a semiconductor substrate. The trench is filled with a first material to form a filled trench. A feature of a second material is formed over the filled trench. The feature is disposed over the filled trench and extends along two opposing sidewalls of the filled trench to a top surface of the layer. The feature is then planarized to expose a top surface of the filled trench and provide a first portion of the feature adjacent a first sidewall of the two opposing sidewalls of the filled trench and a second portion of the feature adjacent a second sidewall of the two opposing sidewalls of the filled trench. The first and second portions of the feature are used to define a dimension of an interconnect feature disposed over the semiconductor substrate. 1. A method , comprising:forming a trench over a layer disposed on a semiconductor substratefilling the trench with a first material, thereby forming a filled trench over the layer;forming a feature of a second material over the filled trench, wherein the feature is disposed over the filled trench and extends along two opposing sidewalls of the filled trench to a top surface of the layer;planarizing the feature to expose a top surface of the filled trench, wherein the planarizing provides a first portion of the feature adjacent a first sidewall of the two opposing sidewalls of the filled trench and a second portion of the feature adjacent a second sidewall of the two opposing sidewalls of the filled trench; andusing the first and second portions of the feature to define a dimension of an interconnect feature disposed over the semiconductor substrate.2. The method of claim 1 , further comprising:forming first and second features over the layer, wherein the trench extends between the first and second feature; andusing the first and second features to define another dimension of the interconnect feature disposed over the semiconductor substrate.3. The method of claim ...

METHODS FOR INTEGRATED CIRCUIT DESIGN AND FABRICATION

The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein. 1. A method of patterning a target material layer on a semiconductor substrate , the method comprising:forming a spacer feature over the target material layer using a first sub-layout;performing a photolithographic patterning process using a second sub-layout to form a first feature, a portion of the first feature extending over the spacer feature;removing the portion of the first feature extending over the spacer feature; andremoving the spacer feature.2. The method of claim 1 , wherein removing the portion of the first feature extending over the spacer feature comprises forming a first separate portion of the first feature and a second separate portion of the first feature.3. The method of claim 2 , wherein the second separate portion of the first feature is smaller than a minimum feature size permitted by the photolithographic patterning process.4. The method of claim 1 , further comprising forming a masking feature over the target material layer using the first sub-layout claim 1 , and wherein forming the spacer feature over the target material layer using the first sub-layout comprises forming the spacer feature around the masking feature.5. The method of claim 4 , further comprising patterning the target material layer using the first feature and the masking feature as etch masking features during a material removal process.6. The method of claim 1 , ...

Lithographic Technique Incorporating Varied Pattern Materials

Patterning techniques are disclosed that can relax overlay requirements and/or increase integrated circuit design flexibility. An exemplary method includes forming a first set of fins and a second set of fins having different etch sensitivities on a material layer. The fins of the second set of fins are interspersed between the fins of the first set of fins. A first patterning process removes a subset of the first set of fins and a portion of the material layer underlying the subset of the first set of fins. The first patterning process avoids substantial removal of an exposed portion of the second set of fins. A second patterning process removes a subset of the second set of fins and a portion of the material layer underlying the subset of the second set of fins. The second patterning process avoids substantial removal of an exposed portion of the first set of fins.

Methods for Integrated Circuit Design and Fabrication

The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of: forming a plurality of first features over the target material layer using a first sub-layout, with each first feature having sidewalls; forming a plurality of spacer features, with each spacer feature conforming to the sidewalls of one of the first features and having a spacer width; and forming a plurality of second features over the target material layer using a second sub-layout. The method further includes steps of removing the plurality of spacer features from around each first feature and patterning the target material layer using the plurality of first features and the plurality of second features. Other methods and associated patterned semiconductor wafers are also provided herein. 1. A method of patterning a target material layer on a semiconductor substrate , the method comprising:forming a plurality of first features over the target material layer using a first sub-layout, each first feature having sidewalls;forming a plurality of spacer features, each spacer feature conforming to the sidewalls of one of the first features and having a spacer width;forming a plurality of second features over the target material layer using a second sub-layout;removing the plurality of spacer features from around each first feature; andpatterning the target material layer using the plurality of first features and the plurality of second features.2. The method of claim 1 , wherein the plurality of second features is formed such that a gap separates at least some of the plurality of second features from the plurality of spacer features.3. The method of claim 1 , wherein at least one second feature is formed with a portion of the second feature over at least one of the spacer features.4. The method of claim 3 , wherein the portion of the second feature over at least one of the spacer features from over the at least one of the spacer ...

Systems and Methods for a Sequential Spacer Scheme

The present disclosure describes methods for transferring a desired layout into a target layer. The method includes a step of forming a spacer, having a second width, around a first and a second desired layout feature pattern of the desired layout over a semiconductor substrate. The first desired layout feature pattern is formed using a first sub-layout and the second desired layout feature pattern is formed using a second sub-layout. The first and second desired layout feature patterns are separated by a first width. The method further includes forming a third desired layout feature pattern according to a third sub-layout. The third desired layout feature pattern is shaped in part by the spacer. The method further includes removing the spacer from around the first and second desired layout feature pattern and etching the target layer using the first, second, and third layout feature patterns as masking features. 1. A method for transferring a desired layout into a target layer on a semiconductor substrate , the method comprising:forming a spacer around a first desired layout feature pattern and a second desired layout feature pattern of the desired layout over the semiconductor substrate, the first desired layout feature pattern formed over the target layer using a first sub-layout and the second desired layout feature pattern formed over the target layer using a second sub-layout, wherein the first and second desired layout feature patterns are separated by a first width and the spacer has a second width;forming a third desired layout feature pattern over the target layer according to a third sub-layout, the third desired layout feature pattern shaped in part by the spacer;etching the spacer from around the first and second desired layout feature pattern; andafter etching the spacer, etching the target layer using the first, second, and third layout feature patterns as masking features to form corresponding first, second, and third layout features in the target ...

Spacer Etching Process For Integrated Circuit Design

A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a patterning process; and forming a second plurality of trenches in the first layer by another patterning process, resulting in combined trench patterns in the first layer. A first trench of the second plurality connects two trenches of the first plurality. The method further includes forming dielectric spacer features on sidewalls of the combined trench patterns. A space between two opposing sidewalls of the first trench is completely filled by the dielectric spacer features and another space between two opposing sidewalls of one of the two trenches is partially filled by the dielectric spacer features. 1. A method , comprising:forming a first layer on a substrate;forming a first plurality of trenches in the first layer by a first patterning process;forming a second plurality of trenches in the first layer by a second patterning process, resulting in combined trench patterns in the first layer, wherein a first trench of the second plurality connects two trenches of the first plurality; andforming dielectric spacer features on sidewalls of the combined trench patterns, wherein a first space between two opposing sidewalls of the first trench is completely filled by the dielectric spacer features and a second space between two opposing sidewalls of one of the two trenches is partially filled by the dielectric spacer features.2. The method of claim 1 , wherein the first layer includes silicon nitride and the dielectric spacer features include titanium nitride.3. The method of claim 1 , wherein the forming of the first plurality of trenches is performed before the forming of the second plurality of trenches.4. The method of claim 3 , wherein the forming of the second plurality of trenches includes:forming a second layer over the first layer and within the first plurality of trenches, the first and second layers having different materials;forming a resist ...

Self-Aligned Semiconductor Fabrication With Fosse Features

The present disclosure describes methods for transferring a desired layout into a target layer on a semiconductor substrate. An embodiment of the methods includes forming a first desired layout feature as a first line over the target layer; forming a spacer around the first line; depositing a spacer-surrounding material layer; removing the spacer to form a fosse pattern trench surrounding the first line; and transferring the fosse pattern trench into the target layer to form a fosse feature trench in the target layer, wherein the fosse feature trench surrounds a first portion of the target layer that is underneath a protection layer. In some embodiments, the method further includes patterning a second desired layout feature of the desired layout into the target layer wherein the fosse feature trench and the protection layer serve to self-align the second desired layout feature with the first portion of the target layer. 1. A method for transferring a desired layout into a target layer on a semiconductor substrate , the method comprising:forming a first desired layout feature as a first line over the target layer;forming a spacer around the first line;depositing a spacer-surrounding material layer, the spacer-surrounding material layer surrounding the spacer;removing the spacer to form a fosse pattern trench surrounding the first line; andtransferring the fosse pattern trench into the target layer to form a fosse feature trench in the target layer, wherein the fosse feature trench surrounds a first portion of the target layer that is underneath a protection layer.2. The method of claim 1 , wherein the first line includes a patterning layer portion over a hard mask layer portion.3. The method of claim 2 , wherein the patterning layer portion and the spacer-surrounding material layer are formed from the same material claim 2 , and further comprising:before removing the spacer, performing an etch-back process on the spacer-surrounding material layer and the patterning ...

Mandrel Spacer Patterning in Multi-Pitch Integrated Circuit Manufacturing

A method of manufacturing an integrated circuit (IC) includes receiving a design layout of the IC, wherein the design layout includes two abutting blocks, the two blocks include target patterns, and the target patterns have different pitches in the two blocks. The method further includes generating mandrel pattern candidates in spaces between adjacent target patterns, and assigning first and second colors to the mandrel pattern candidates according to their priorities. The method further includes removing the mandrel pattern candidates assigned with the second color, and outputting a mandrel pattern in computer-readable format for mask fabrication. The mandrel pattern includes the mandrel pattern candidates that are colored with the first color.

METHOD OF FABRICATING SEMICONDUCTOR DEVICE WITH REDUCED TRENCH DISTORTIONS

A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench. 1. A method comprising:forming a material layer over a substrate;forming a first hard mask (HM) layer over the material layer;forming a first trench in the first HM layer, wherein the first trench extends along a first direction;forming a first spacer layer in the first trench;forming a second trench in the first HM layer, wherein the first spacer layer is disposed within the first trench during the forming of the second trench;removing a first portion of the material layer to extend the first trench into the material layer and removing a second portion of the material to extend the second trench into the material layer;removing the first HM layer and the first spacer layer;forming a second HM layer over the material layer;forming a third trench in the second HM layer, wherein the third trench extends along a second direction that is different than the first direction, wherein the third trench overlaps the extended first trench; andremoving a third portion of the material layer through the third trench.2. The method of claim 1 , further comprising forming a conductive layer over the substrate claim 1 , wherein the ...

Systems and Methods for a Sequential Spacer Scheme

Semiconductor devices disclosed herein have minimum spacings that correlate with spacer widths. An exemplary semiconductor device includes a substrate and a target layer disposed over the substrate. The target layer includes a first target feature, a second target feature, and a third target feature. The second target feature is spaced a first distance from the first target feature, and the third target feature is spaced a second distance from the first target feature. The first distance corresponds with a first width of a first spacer fabricated during a first spacer patterning process, and the second distance corresponds with a second width of a second spacer fabricated during a second spacer patterning process. 1. A semiconductor device comprising:a substrate; and a first target feature,', 'a second target feature spaced a first distance from the first target feature, wherein the first distance corresponds with a first width of a first spacer fabricated during a first spacer patterning process, and', 'a third target feature spaced a second distance from the first target feature, wherein the second distance corresponds with a second width of a second spacer fabricated during a second spacer patterning process., 'a target layer disposed over the substrate, wherein the target layer includes2. The semiconductor device of claim 1 , wherein the first width is the same as the second width claim 1 , such that the first distance is the same as the second distance.3. The semiconductor device of claim 1 , wherein the first width is different than the second width claim 1 , such that the first distance is different than the second distance.4. The semiconductor device of claim 1 , wherein the third target feature is also spaced a third distance from the second target feature claim 1 , wherein the third distance corresponds with the second width of the second spacer.5. The semiconductor device of claim 4 , wherein the target layer further includes a fourth target feature ...

Mechanisms for Forming Patterns Using Multiple Lithography Processes

The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern. 1. A method for forming patterns in a semiconductor device , comprising:forming a main pattern in a patterning-target layer over a substrate;forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer;patterning the hard mask layer to form a first cut pattern;forming a second cut pattern in a first resist layer formed over the hard mask layer;patterning the middle layer through an opening corresponding to a first intersection portion to expose a portion of the patterning-target layer, the exposed portion of the patterning-target layer corresponding to a second intersection portion; andetching the exposed portion of the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer,wherein the first intersection portion corresponds to an intersection between the first cut pattern and the second cut pattern, andwherein the second intersection portion corresponds to an intersection between the first intersection portion and the main pattern.2. The method of ...

Methods for Integrated Circuit Design and Fabrication

The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein. 1. A method comprising:forming a first pattern feature and a second pattern feature over a material layer;forming a first spacer feature on a sidewall of the first pattern feature and a second spacer feature on a sidewall of the second pattern feature, wherein a sidewall of the first spacer feature faces a sidewall of the second spacer feature such that a trench is defined between the sidewall of first spacer feature and the sidewall of the second spacer feature;forming a third pattern feature in the trench, wherein an air gap is positioned within the trench between the sidewall of the first spacer feature and the third pattern feature after forming the third pattern feature in the trench; andremoving the first and second spacer features to expose a portion of the material layer.2. The method of claim 1 , wherein the forming of the third pattern feature in the trench includes forming the third pattern feature directly on the material layer such that the third pattern feature physically contacts the material layer.3. The method of claim 1 , wherein the forming of the third pattern feature in the trench includes forming a portion of the third pattern feature over a top surface of the first spacer feature such that the third pattern feature physically contacts the top surface of the first spacer feature.4. The method of claim 3 , further comprising performing ...

DEVICE AND METHOD FOR IMMERSION LITHOGRAPHY

PHOTOLITHOGRAPHIC DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTORS

Photolithography tool for manufacturing semiconductor device, has wafer whose patterned portion is immersed in liquid, where liquid`s flow direction is controlled and directed outwardly by manipulating nozzle and drain assemblies

Un système de lithographie par immersion pour la fabrication de semiconducteurs fournit un montage de lentille qui se déplace relativement à la surface (113) d'une plaque et comprend un ensemble de buses (106) et de conduits d'évacuation (108) couplé à -et se déplaçant avec- le montage de lentille. Les ensembles de buses (106) et de conduits d'évacuation (108) peuvent être disposés circonférentiellement en face de l'un l'autre autour de la lentille (102), ou bien une bague annulaire (202) peut être fournie pour encercler la lentille (102) et comporter un jeu de buses et de conduits d'évacuation sélectionnables alternativement. Les ensembles de buses (106) et de conduits d'évacuation (108) peuvent encercler l'objectif de manière rotative. Au moins une partie de la plaque qui est imprimée est immergée dans un liquide fourni par l'ensemble de buses (106) et une direction d'écoulement est contrôlée en manoeuvrant les ensembles de buses (106) et de conduits d'évacuation. La direction d'écoulement peut être avantageusement dirigée vers l'extérieur pour réduire la pollution par particules.

Apparatus and method for immersion lithography

Integrated circuit layout and method with double patterning

The present disclosure provides one embodiment of a method for an integrated circuit (IC). The method includes forming a mandrel pattern on a substrate by a first lithography process; forming a first spacer pattern on sidewalls of the mandrel pattern; removing the mandrel pattern; forming a second spacer pattern on sidewalls of the first spacer pattern; removing the first spacer pattern; and etching the substrate using the second spacer pattern as an etch mask.

Method and apparatus for removing particles in immersion lithography

A method and system involve supplying an immersion fluid to a space between an imaging lens and a substrate to be patterned, generating an electric field in the immersion fluid within the space so that the electric field urges particles away from a surface of the substrate, removing the immersion fluid along with the particles from the space, and thereafter supplying immersion fluid to the space and performing a lithographic exposing process on the surface of the substrate.

Measurement of overlay offset in semiconductor processing

A method of semiconductor manufacturing including forming an overlay offset measurement target including a first feature on a first layer and a second feature on a second layer. The first feature and the second feature have a first predetermined overlay offset. The target is irradiated. The reflectivity of the irradiated target is determined. An overlay offset for the first layer and the second layer is calculated using the determined reflectivity.

System and method for direct writing to a wafer

A direct-write (DW) exposure system is provided which includes a stage for holding a substrate and configured to scan the substrate along an axis during exposure, a data processing module for processing pattering data and generating instructions associated with the patterning data, and an exposure module that includes a plurality of beams that are focused onto the substrate such that the beams cover a width that is larger than a width of a field size and a beam controller that controls the plurality of beams in accordance with the instructions as the substrate is scanned along the axis. The widths are in a direction different from the axis.

Method for improving the critical dimension uniformity of patterned features on wafers

A method for improving the critical dimension uniformity of a patterned feature on a wafer in semiconductor and mask fabrication is provided. In one embodiment, an evaluation means for evaluating the critical dimension distribution of a plurality of circuit layouts formed on the wafer, the plurality of circuit layouts defined by a mask is provided. A logic operation is performed on the plurality of circuit layouts to extract the patterned feature. The patterned feature is compared with design rules and if there is a deviation or difference between the patterned feature and the design rules, this difference is compensated for by adjusting photolithography adjustable parameters, such as, for example, mask-making.

Layout generation and optimization to improve photolithographic performance

Disclosed are a system and method for designing a mask layout. In one example, the method includes representing the mask layout using a plurality of pixels, each having a mask transmittance coefficient. A control parameter is initialized and a representative of the mask layout is generated. The method determines acceptance of the representative of the mask layout by a cost function and a Boltzmann factor, where the cost function is related to the mask layout and a target substrate pattern, and the Boltzmann factor is related to the cost function and the control parameter. The methods repeats the steps of generating the representative and determining acceptance until the mask layout is stabilized. The control parameter is decreased according to an annealing schedule. The generating, determining, repeating, and decreasing steps are reiterated until the mask layout is optimized.

Method of patterning a film layer

A method of fabricating a semiconductor device is disclosed. The method includes forming a first patterned hard mask over a material layer. The first patterned hard mask defines an opening. The method also includes forming a direct-self-assembly (DSA) layer having a first portion and a second portion within the opening, removing the first portion of the DSA layer, forming spacers along sidewalls of the second portion of the DSA layer and removing the second portion of the DSA layer. The spacers form a second patterned hard mask over the material layer.

System and method for photolithography in semiconductor manufacturing

Verfahren für die Photolithographie in der Halbleiterherstellung, aufweisend ein Bereitstellen (12) eines Substrats für einen Wafer (28, 110) und ein Bereitstellen einer Maske (24) zum Belichten des Wafers (28, 110). Der Wafer (28, 110) wird unter Verwendung einer Kombination von einer Aufsichtbelichtung und von Fokusdrift-Belichtungsverfahren belichtet (16).

Multi-focus scanning with a tilted mask or wafer

A method for implementing discrete superpositioning of two or more defocal wafer images at different defocal positions in a lithographic step and scan projection system. The method includes tilting one of a mask and a wafer with respect to a scanning direction and splitting an illumination beam into at least two illumination areas which are in different defocus zones of the mask.

Control method of critical dimension and monitoring method of the hot plate temperature and the thermal uniformity thereof

System and method for photolithography in semiconductor manufacturing

A method for photolithography in semiconductor manufacturing includes providing a substrate for a wafer and providing a mask for exposing the wafer. The wafer is exposed by utilizing a combination of high angle illumination and focus drift exposure methods.

Hood for immersion lithography

A lithography apparatus includes an imaging lens module; a substrate table positioned underlying the imaging lens module and configured to hold a substrate; a fluid retaining module configured to hold a fluid in a space between the imaging lens module and a substrate on the substrate stage; and a heating element configured in the fluid retaining module and adjacent to the space. The heating element includes at least one of following: a sealant insoluble to the fluid for sealing the heating element in the fluid retaining module; a sealed opening configured in one of top portion and side portion of the fluid retaining module for sealing the heating element in the fluid retaining module; and/or a non-uniform temperature compensation device configured with the heating element.

Intensity selective exposure photomask

An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage. Each of the features of the first and second array includes an opening disposed in an area of attenuating material.

Via connection to a partially filled trench

An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.

Method and system for optimizing intra-field critical dimension uniformity using a sacrificial twin mask

在半導體裝置內形成圖案的方法

本揭露提供一種在半導體裝置內形成圖案的方法。根據某些實施例，該方法包括提供一基底、基底上的一圖案化目標層以及圖案化目標層上的一硬式罩幕層。在硬式罩幕層內形成一第一圖案。自硬式罩幕層內的第一圖案去除一修整部分，以形成一經修整的第一圖案。在硬式罩幕層上形成一第一阻劑層。在第一阻劑層內形成一主要圖案。使用主要圖案及經修整的第一圖案作為一蝕刻遮罩元件來蝕刻圖案化目標層，以在圖案化目標層內形成一最終圖案。在某些實施例中，最終圖案包括主要圖案減去主要圖案與經修整的第一圖案之間的一第一重疊部分。

Systems and methods for a sequential spacer scheme

Semiconductor devices disclosed herein have minimum spacings that correlate with spacer widths. An exemplary semiconductor device includes a substrate and a target layer disposed over the substrate. The target layer includes a first target feature, a second target feature, and a third target feature. The second target feature is spaced a first distance from the first target feature, and the third target feature is spaced a second distance from the first target feature. The first distance corresponds with a first width of a first spacer fabricated during a first spacer patterning process, and the second distance corresponds with a second width of a second spacer fabricated during a second spacer patterning process.