E-beam direct writing to pattern step profiles of dielectric layers applied to fill poly via with poly line, contact with metal line, and metal via with metal line

A method is disclosed for employing direct electron beam writing in the lithography used for forming step-profiles in semiconductor devices. The number of steps in the profiles are not limited. An electron beam sensitive resist is formed over a substrate. The resist is then exposed to a scanning electron beam having precise information, including proximity effect correction data, to directly form stair-case-like openings in the resist. The highly accurately dimensioned step-profiles are then transferred into the underlying layers by performing appropriate etchings. The resulting structures are shown to be especially suitable for forming damascene interconnects for submicron technologies.

Isolation Regions For Isolating Transistors and the Methods Forming the Same

A method includes etching a gate stack in a wafer to form a trench, depositing a silicon nitride liner extending into the trench, and depositing a silicon oxide layer. The process of depositing the silicon oxide layer includes performing a treatment process on the wafer using a process gas including nitrogen and hydrogen, and performing a soaking process on the wafer using a silicon precursor.

High aspect ratio gap fill application using high density plasma chemical vapor deposition

A high density plasma chemical vapor deposition process including exciting gas mixture to create a plasma including ions, and directing the plasma into a dense region above the upper surface of the semiconductor wafer, heating the wafer using an additional heat source, and allowing a material from the plasma to deposit onto the semiconductor wafer.

Semiconductor structures with shallow trench isolations

A method is disclosed that includes the operations outlined below. An insulating material is disposed within a plurality of trenches on a semiconductor substrate and over the semiconductor substrate. The first layer is formed over the insulating material. The first layer and the insulating material are removed.

Surface treated low-k dielectric as diffusion barrier for copper metallization

A Cu damascene structure is formed where Cu diffusion barrier is formed by treating the top surface of the surrounding low-k interlayer dielectric with nitrogen or carbon containing medium to form a silicon nitride or silicon carbide diffusion barrier rather than capping the top surface of the Cu with metal diffusion barrier as is conventionally done.

ELECTRONIC DEVICE

An electronic device is disclosed and includes a base substrate, a first circuit layer and a plurality of light-emitting elements. The base substrate has a first surface and a second surface opposite to each other. The first circuit layer includes a first portion and a second portion. The first portion is disposed on the first surface of the base substrate, and the second portion is disposed on the second surface of the base substrate. The light-emitting elements are disposed on the first portion of the first circuit layer. At least one of the second surface of the base substrate and the first portion of the first circuit layer includes at least one microstructure.

Semiconductor Fin cutting process and structures formed thereby

Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.

Method for proximity effect compensation on alternative phase-shift masks with bias and optical proximity correction

A method of forming an alternative phase shifting mask and forming a circuit pattern on a wafer using the mask are described. Optical proximity correction is added to a data file, in which a description of a circuit pattern has been stored, to obtain a first modified data file. The first modified data file is then separated into a second modified data file, for regions of the mask having dense line/space patterns, and a third modified data file, for regions of the mask having isolated line space patterns. Critical dimension bias is then added to the second modified data file forming a fourth modified data file. The third modified data file and the fourth modified data file are then merged into a single fifth modified data file. The fifth modified data file is then is then converted to an alternative phase shift data file. An alternative phase shift mask is then formed from the alternative phase shift data file. The alternative phase shift mask has then been corrected for optical proximity ...

Method of forming dram capacitors with protected outside crown surface for more robust structures

A method for fabricating a high-density array of crown capacitors with increased capacitance while reducing process damage to the bottom electrodes is achieved. The process is particularly useful for crown capacitors for future DRAM circuits with minimum feature sizes of 0.18 micrometer or less. A conformal conducting layer is deposited over trenches in an interlevel dielectric (ILD) layer, and is polished back to form capacitor bottom electrodes. A novel photoresist mask and etching are then used to pattern the ILD layer to provide a protective interlevel dielectric structure between capacitors. The protective structures prevent damage to the bottom electrodes during subsequent processing. The etching also exposes portions of the outer surface of bottom electrodes for increased capacitance (>50%). In a first embodiment the ILD structure is formed between pairs of adjacent bottom electrodes, and in a second embodiment the ILD structure is formed between four adjacent bottom electrodes.

Method for forming a semiconductor device having high-K gate dielectric material

In a method of forming an integrated circuit, a sacrificial layer is formed over a substrate. The sacrificial layer has a gate trench formed therein and a first layer of a first material formed over the substrate in the gate trench. A second layer of a second material is formed over the first layer in the gate trench. The first and second layers are processed to form a layer of a high-K dielectric material.

Project management method and information integration system

A method of managing a project comprises: receiving data representing attributes of a project from a project manager; receiving data identifying attributes of the task; assigning a task to a task-responsible person; automatically providing a notice to the task-responsible person, the notice identifying the assignment of the task; receiving at least one task report from the corresponding task-responsible person; providing the corresponding task-responsible person and the project manager read-write access to the task report; and providing at least one other person read-only access to the task report. A computer-implemented information integration system comprises: a database for receiving a plurality of patent data; the database for receiving a plurality of entity data; the database for receiving a plurality of evidence data; the database associating the patent data, the entity data, and the evidence data to each other and storing the patent data, the entity data, and the evidence data.

Method for multiple spacer width control

A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a first plurality of gate structures; blanket depositing a first dielectric layer over the first plurality of gate structures; blanket depositing a second dielectric layer over the first dielectric layer; etching back through a thickness of the first and second dielectric layers; blanket depositing a first photoresist layer to cover the first plurality and patterning to selectively expose at least a second plurality of gate structures; isotropically etching the at least a second plurality of gate structures for a predetermined time period to selectively etch away a predetermined portion of the first dielectric layer; and, selectively etching away the second dielectric layer to leave gate structures comprising a plurality of associated sidewall spacer widths.

Electronic device

An electronic device is disclosed and includes a substrate, a circuit layer, and a plurality of diodes. The substrate has a plurality of structures. The circuit layer is disposed on the substrate. The diodes are disposed on the circuit layer, wherein a first spacing is defined as a distance between a center point of a first one of the structures and a center point of a second one of the structures, a second spacing is defined as a distance between a center point of a third one of the structures and a center point of a fourth one of the structures, and an absolute value of a difference between the first spacing and the second spacing is less than 0.5 times radius of curvature of the electronic device when the electronic device is bent.

Structure for high resolution mouse

Improved structure for high resolution mouse is equipped with a frictional sleeve on each one of a pair of transmission shafts with transmission wheel circumferential length multiple of that of corresponding frictional sleeves so as to increase rotational ratio and facilitate an associated pair of infrared detectors able to detect bright/dark intermitten variation of light imput more distinctly and reliably from a pair of light shading wheels in a given time duration and send out corresponding high resolution (DPT) signals.

Pattern compensation for stitching

A method for transferring a pattern from a mask to a substrate (or wafer), comprises dividing a mask generation data file into a plurality of segments. The segments include a main pattern area and a stitching area. Each stitching area contains a respective common pattern. An image of an illuminated portion of the main pattern area is formed. Connection ends of the segments in a substrate area (or wafer area) are illuminated with an illumination beam. An image of the illuminated portion of the main pattern area is formed, and a halftone gray level dosage distribution is produced in the substrate area (or wafer area) corresponding to the common pattern. The common patterns of adjacent segments substantially overlap in the substrate area (or wafer area).

Semiconductor Device and Method of Manufacture

An etch stop layer is formed over a semiconductor fin and gate stack. The etch stop layer is formed utilizing a series of pulses of precursor materials. A first pulse introduces a first precursor material to the semiconductor fin and gate stack. A second pulse introduces a second precursor material, which is turned into a plasma and then directed towards the semiconductor fin and gate stack in an anisotropic deposition process. As such, a thickness of the etch stop layer along a bottom surface is larger than a thickness of the etch stop layer along sidewalls. 1. A method of manufacturing a semiconductor device , the method comprising:forming spacers adjacent to a gate stack over a semiconductor fin; and pulsing a first precursor over the gate stack, the first precursor being a non-plasma; and', 'after the pulsing the first precursor, pulsing a second precursor over the gate stack, the second precursor being a plasma biased towards the semiconductor fin, the etch stop layer having a first thickness adjacent to the spacers and a second thickness different from the first thickness over the gate stack., 'depositing an etch stop layer over the gate stack and adjacent to the spacers, the depositing the etch stop layer comprising2. The method of claim 1 , wherein the depositing the etch stop layer comprises depositing the etch stop layer over the semiconductor fin.3. The method of claim 1 , wherein the depositing the etch stop layer is performed with a bias formed with a first electrode and a second electrode claim 1 , the first electrode being set at a power of between about 0 W and about 1500 W.4. The method of claim 3 , wherein the second electrode is set at a power of between about 300 W and about 500 W.5. The method of claim 1 , further comprising igniting the plasma over the semiconductor fin.6. The method of claim 1 , wherein the first precursor is diiodosilane and the second precursor is nitrogen.7. The method of claim 1 , further comprising etching the etch stop ...

Forming doped regions in semiconductor strips

A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip, and depositing a dielectric dose film on sidewalls of the semiconductor strip. The dielectric dose film is doped with a dopant of n-type or p-type. The remaining portions of the trenches are filled with a dielectric material. A planarization is performed on the dielectric material. Remaining portions of the dielectric dose film and the dielectric material form Shallow Trench Isolation (STI) regions. A thermal treatment is performed to diffuse the dopant in the dielectric dose film into the semiconductor strip.

Method for creating the sub-resolution phase shifting pattern for outrigger type phase shifting masks

A method is described for using computer aided design data for contact holes in a background, such as an opaque background or a phase shifting background, to generate computer aided design data for fabricating a mask an outrigger pattern. The outrigger pattern mask has contact holes surrounded by a first border of opaque material and the first border of opaque material surrounded by a third border of attenuating or 100% transmittance phase shifting material. The third border of attenuating or 100% transmittance phase shifting material is surrounded by opaque material. The design data for the contact hole pattern, a background pattern, a first correction pattern, and a second correction pattern are combined in a computer processor to generate final data. The final data is used to fabricate the mask.

Method for forming multiple spacer widths

A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a plurality of gate structures formed overlying a substrate and a plurality of dielectric layers formed substantially conformally overlying the gate structures; exposing a first selected portion of the plurality followed by anisotropically etching through a thickness portion comprising at least the uppermost dielectric layer to form a first sidewall spacer width; exposing a first subsequent selected portion of the plurality followed by etching through at least a thickness portion of the uppermost dielectric layer; and, exposing a second subsequent selected portion of the plurality followed by anisotropically etching through at least a thickness portion of the uppermost dielectric layer to form a subsequent sidewall spacer width.

Composite fluorescent gold nanoclusters with high quantum yield and method for manufacturing the same

Disclosed herein are composite fluorescent gold nanoclusters with high quantum yield, as well as methods for manufacturing the same. According to some embodiments, the composite fluorescent gold nanocluster includes a gold nanocluster and a capping layer that encapsulates at least a portion of the outer surface of the gold nanocluster. The capping layer includes a matrix made of a benzene-based compound, and multiple phosphine-based compounds distributed across the matrix.

Surface treatment of metal interconnect lines

Apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.

Semiconductor Fin Cutting Process and Structures Formed Thereby

Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV. 1. A method of forming a semiconductor device , the method comprising:forming a fin on a substrate;forming isolation regions on the substrate, where the fin protrudes above the isolation regions;forming a gate structure over the fin;forming first spacer and a second spacer adjacent the gate structure, wherein the gate structure is interposed between the first spacer and the second spacer;removing a first portion of the gate structure and a first portion of the fin to form a first recess, wherein the first recess extends lower than an upper surface of the isolation regions;forming a liner layer in the first recess; andafter forming the liner layer, forming a fill material on the liner layer in the first recess, wherein the fill material is an insulating material.2. The method of claim 1 , wherein forming the liner layer comprises forming a conformal liner layer.3. The method of claim 1 , wherein the liner layer comprises a material having a band gap greater than 5 eV.4. The method of claim 1 , wherein the gate structure comprises a dummy gate structure claim 1 , and further comprising:replacing the dummy gate structure with a replacement gate structure.5. The method of claim 4 , wherein replacing the dummy gate structure is performed after forming the fill material.6. The method of claim 1 , wherein the first recess exposes a sidewall of the first spacer and a sidewall of the second spacer ...

Method for forming multiple spacer widths

A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a plurality of gate structures formed overlying a substrate and a plurality of dielectric layers formed substantially conformally overlying the gate structures; exposing a first selected portion of the plurality followed by anisotropically etching through a thickness portion comprising at least the uppermost dielectric layer to form a first sidewall spacer width; exposing a first subsequent selected portion of the plurality followed by etching through at least a thickness portion of the uppermost dielectric layer; and, exposing a second subsequent selected portion of the plurality followed by anisotropically etching through at least a thickness portion of the uppermost dielectric layer to form a subsequent sidewall spacer width.

Semiconductor device and method

A four-layer photoresist and method of forming the same are disclosed. In an embodiment, a method includes forming a semiconductor fin; depositing a target layer on the semiconductor fin; depositing a BARC layer on the target layer; depositing a first mask layer over the BARC layer, the first mask layer being deposited using a plasma process with an RF power of less than 50 W; depositing a second mask layer over the first mask layer using a plasma process with an RF power of less than 500 W; depositing a photoresist layer over the second mask layer; patterning the photoresist layer, the second mask layer, the first mask layer, and the BARC layer to form a first mask; and selectively removing the target layer from a first portion of the semiconductor fin using the first mask, the target layer remaining on a second portion of the semiconductor fin.

ELECTRONIC DEVICE

An electronic device is disclosed and includes a substrate, a circuit layer, and a plurality of diodes. The substrate has a plurality of structures. The circuit layer is disposed on the substrate. The diodes are disposed on the circuit layer, wherein a first spacing is defined as a distance between a center point of a first one of the structures and a center point of a second one of the structures, a second spacing is defined as a distance between a center point of a third one of the structures and a center point of a fourth one of the structures, and an absolute value of a difference between the first spacing and the second spacing is less than 0.5 times radius of curvature of the electronic device when the electronic device is bent.

Protein For Improving Cell-Attachment Efficiency and Use Thereof

The present invention provides a method for improving cell-attachment efficiency comprising (a) preparing a protein in aqueous solution, wherein the protein has a formula A-B-C, wherein A represents a GRGDS amino acid sequence; B represents a cellulose binding domain (CBD); and C represents a GRGDS amino acid sequence, an RGD amino acid sequence, or an amino acid sequence of growth factor; (b) coating the protein solution into a carrier; and (c) seeding cells onto the carrier.

Centrifuge/magnet-based analyzers and method of operating thereof

The present invention provides centrifuge/magnet-based analyzers and methods of operating thereof. The analyzer comprises three discs sandwiched together, in which each disc has difference functions. The top disc comprises magnetic units configured in patterns, whereas the bottom disc comprises tracks and magnetic units free to move in the tracks. The magnetic field co-generated by the top disc and the bottom disc attracts the magnetic beads in the intermediate disc to move and thus facilitates the reactions in the intermediate disc.

Gas-based microfluidic devices and operating methods thereof

Gas-based microfluidic devices and operating methods of gas-based microfluidic devices are provided. The gas-based microfluidic devices comprise a drive module and a microfluidic platform, in which the microfluidic platform further comprises a microfluidic element having an injection chamber, a process chamber, an air chamber, an overflow channel, a barrier, and at least one detection chamber. Gases in the air chamber enable solutions to move toward the direction opposite to the centrifugal force applied by the drive module. Accordingly, the operating methods utilize the gases compressed in the air chamber to move solutions to difference components in the microfluidic element.

DRAM capacitor structure with increased electrode support for preventing process damage and exposed electrode surface for increasing capacitor area

A method for fabricating a high-density array of crown capacitors with increased capacitance while reducing process damage to the bottom electrodes is achieved. The process is particularly useful for crown capacitors for future DRAM circuits with minimum feature sizes of 0.18 micrometer or less. A conformal conducting layer is deposited over trenches in an interlevel dielectric (ILD) layer, and is polished back to form capacitor bottom electrodes. A novel photoresist mask and etching are then used to pattern the ILD layer to provide a protective interlevel dielectric structure between capacitors. The protective structures prevent damage to the bottom electrodes during subsequent processing. The etching also exposes portions of the outer surface of bottom electrodes for increased capacitance (>50%). In a first embodiment the ILD structure is formed between pairs of adjacent bottom electrodes, and in a second embodiment the ILD structure is formed between four adjacent bottom electrodes.

Semiconductor device structure and method for forming the same

Semiconductor device structures and methods for forming the same are provided. A semiconductor device structure includes a gate structure over a semiconductor substrate. The gate structure includes a gate electrode layer and a gate dielectric layer covering a bottom surface and sidewalls of the gate electrode layer. The semiconductor device structure also includes spacer elements in contact with sidewalls of the gate structure and protruding from a top surface of the gate electrode layer. The semiconductor device structure also includes a first protection layer over the gate electrode layer and between the spacer elements. The semiconductor device structure also includes a dielectric layer over the first protection layer and between the spacer elements. A portion of the dielectric layer is between sidewalls of the spacer elements and sidewalls of the first protection layer.

Unicast and broadcast protocol for wireless local area network ranging and direction finding

Disclosed embodiments facilitate wireless channel calibration, ranging, and direction finding, between networked devices. A method on a first station (STA) may comprise: broadcasting, at a first time, a first NDPA frame to a plurality of second STAs. The first NDPA frame may include a first bit indicating that one or more subsequent frames comprise ranging or angular information. After a Short Interval Frame Space (SIFS) time interval from the first time, a second frame may be broadcast. The second frame may be a Null Data Packet (NDP) frame. In response, a plurality of Compressed Beamforming (CBF) frames may be received at the first STA where each CBF frame may be received from a distinct corresponding second STA, and may include Channel Feedback Information field with information pertaining to communication channel between the first STA and the corresponding second STA. The communications may be encoded using Orthogonal Frequency Division Multiple Access.

Method of forming DRAM capacitors with protected outside crown surface for more robust structures

A method for fabricating a high-density array of crown capacitors with increased capacitance while reducing process damage to the bottom electrodes is achieved. The process is particularly useful for crown capacitors for future DRAM circuits with minimum feature sizes of 0.18 micrometer or less. A conformal conducting layer is deposited over trenches in an interlevel dielectric (ILD) layer, and is polished back to form capacitor bottom electrodes. A novel photoresist mask and etching are then used to pattern the ILD layer to provide a protective interlevel dielectric structure between capacitors. The protective structures prevent damage to the bottom electrodes during subsequent processing. The etching also exposes portions of the outer surface of bottom electrodes for increased capacitance (>50%). In a first embodiment the ILD structure is formed between pairs of adjacent bottom electrodes, and in a second embodiment the ILD structure is formed between four adjacent bottom electrodes.

Electronic device

The present disclosure provides an electronic device including a substrate, a first circuit layer, and a plurality of diodes. The substrate has a plurality of first through holes. The first circuit layer is disposed on the substrate and has a plurality of light through holes. The diodes disposed on the first circuit layer. One of the light through holes is located between two adjacent ones of the diodes, and the light through holes overlap a portion of the plurality of first through holes and do not overlap another portion of the plurality of first through holes in a normal direction of the substrate.

Selective spacer layer deposition method for forming spacers with different widths

A method of forming spacers with different widths on a semiconductor substrate, includes the steps of disposing a first spacer layer over the substrate, defining the first spacer layer into a plurality of spacers of a first width, and disposing a second spacer layer selectively over the first spacer layer of a number of the spacers preselected for the second spacer layer, the predetermined number of the spacers with the second spacer layer each having a second width which is different from the first width.

Semiconductor device structure and method for forming the same

Semiconductor device structures and methods for forming the same are provided. A method for forming a semiconductor device structure includes forming a gate structure over a semiconductor substrate. The method also includes forming spacer elements adjoining sidewalls of the gate structure. The method further includes forming a protection material layer over the gate structure. The formation of the protection material layer includes a substantial non-plasma process. In addition, the method includes depositing a dielectric material layer over the protection material layer. The deposition of the dielectric material layer includes a plasma-involved process.

Method and system for immersion lithography

A system ( 100 ) and method for immersion lithography is disclosed in which an immersion medium ( 112 ) interfaces with a proximal lens ( 110 ) that focuses a patterned light beam on a light sensitive material ( 116 ), wherein the light sensitive material ( 116 ) is covered by a protective film ( 300 ) that interfaces with the immersion medium ( 112 ).

Semiconductor Device and Method of Manufacture

An etch stop layer is formed over a semiconductor fin and gate stack. The etch stop layer is formed utilizing a series of pulses of precursor materials. A first pulse introduces a first precursor material to the semiconductor fin and gate stack. A second pulse introduces a second precursor material, which is turned into a plasma and then directed towards the semiconductor fin and gate stack in an anisotropic deposition process. As such, a thickness of the etch stop layer along a bottom surface is larger than a thickness of the etch stop layer along sidewalls.

Fan-Out Stacked Package and Methods of Making the Same

In an embodiment, a package includes a first device and a second device attached to a first redistribution structure, wherein the second device includes a second redistribution structure, a first die disposed over the second redistribution structure, a first encapsulant extending along sidewalls of the first die, a first via extending through the first encapsulant, a third redistribution structure disposed over the first encapsulant and including a first metallization pattern connecting to the first via, a second die disposed over the third redistribution structure, and a second encapsulant extending along sidewalls of the second die, the first die and the second die being free of through substrate vias. The package also includes a third encapsulant disposed over the first redistribution structure and surrounding sidewalls of the first device and the second device, wherein top surfaces of the second encapsulant and the third encapsulant are level with each other.

Multi-focus scanning with a tilted mask or wafer

A method for implementing discrete superpositioning of two or more defocal wafer images at different defocal positions in a lithographic step and scan projection system. The method includes tilting one of a mask and a wafer with respect to a scanning direction and splitting an illumination beam into at least two illumination areas which are in different defocus zones of the mask.

Selective spacer layer deposition method for forming spacers with different widths

A method of forming spacers with different widths on a semiconductor substrate, includes the steps of disposing a first spacer layer over the substrate, defining the first spacer layer into a plurality of spacers of a first width, and disposing a second spacer layer selectively over the first spacer layer of a number of the spacers preselected for the second spacer layer, the predetermined number of the spacers with the second spacer layer each having a second width which is different from the first width.

Unicast and broadcast protocol for wireless local area network ranging and direction finding

Disclosed embodiments facilitate wireless channel calibration, including ranging and direction finding, between wirelessly networked devices. In some embodiments. a method on a first station (STA) may comprise: transmitting a first NDPA frame to one or more second stations (STAs), the first NDPA frame comprising a first bit indicating that one or more subsequent frames comprise ranging or angular information; and transmitting, after a Short Interval Frame Space (SIFS) time interval, a second frame. The second frame may be one of: a Null Data Packet az (NDP_az) frame with information about a time of transmission of the NDP_az frame, or a Null Data Packet (NDP) frame, or a Beam Refinement Protocol (BRP) frame. The first NDPA frame may be unicast, multicast, or broadcast.

Semiconductor Fin Cutting Process and Structures Formed Thereby

Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.

Structure for high resolution mouse

Improved structure for high resolution mouse is equipped with a frictional sleeve on each one of a pair of transmission shafts with transmission wheel circumferential length multiple of that of corresponding frictional sleeves so as to increase rotational ratio and facilitate an associated pair of infrared detectors able to detect bright/dark intermitten variation of light imput more distinctly and reliably from a pair of light shading wheels in a given time duration and send out corresponding high resolution (DPT) signals.

Surface treatment of metal interconnect lines

Methods and apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.

Pattern compensation for stitching

A method for transferring a pattern from a mask to a substrate (or wafer), comprises dividing a mask generation data file into a plurality of segments. The segments include a main pattern area and a stitching area. Each stitching area contains a respective common pattern. An image of an illuminated portion of the main pattern area is formed. Connection ends of the segments in a substrate area (or wafer area) are illuminated with an illumination beam. An image of the illuminated portion of the main pattern area is formed, and a halftone gray level dosage distribution is produced in the substrate area (or wafer area) corresponding to the common pattern. The common patterns of adjacent segments substantially overlap in the substrate area (or wafer area).

Semiconductor Device and Method

A four-layer photoresist and method of forming the same are disclosed. In an embodiment, a method includes forming a semiconductor fin; depositing a target layer on the semiconductor fin; depositing a BARC layer on the target layer; depositing a first mask layer over the BARC layer, the first mask layer being deposited using a plasma process with an RF power of less than 50 W; depositing a second mask layer over the first mask layer using a plasma process with an RF power of less than 500 W; depositing a photoresist layer over the second mask layer; patterning the photoresist layer, the second mask layer, the first mask layer, and the BARC layer to form a first mask; and selectively removing the target layer from a first portion of the semiconductor fin using the first mask, the target layer remaining on a second portion of the semiconductor fin. 1. A method comprising:forming a semiconductor fin over a substrate;depositing a target layer on the semiconductor fin;depositing a first mask layer over the target layer, wherein the first mask layer is deposited using a first plasma process with an RF power of less than 50 W;depositing a second mask layer over the first mask layer, wherein the second mask layer is deposited using a second plasma process with an RF power greater than the first plasma process and less than 500 W;patterning the second mask layer and the first mask layer to form a first mask; andselectively removing the target layer from a first portion of the semiconductor fin using the first mask as a mask, the target layer remaining on a second portion of the semiconductor fin.2. The method of claim 1 , wherein the first mask layer and the second mask layer are deposited at a temperature of between 50° C. and 150° C.3. The method of claim 1 , wherein the first mask layer and the second mask layer are deposited from a precursor gas comprising N-(Diethylaminosilyl)-N-ethylethanamine.4. The method of claim 3 , wherein depositing the first mask layer comprises ...

WEBPHONE VOICE & DATA COMMUNICATIONS INTERFACE UNDER SIP FRAMEWORK

A system and method for allowing a person to place a call to another person under the SIP framework when viewing a display portion on a webpage with only one click of a mouse or one press of a keyboard key and using a stand-alone communication program is provided. The above system includes a client end, a server, a service end, an application program obtained from a server, a user-executable portion accessible at the client end on a webpage, a digital certificate authenticated against a digital signature, an active communication channel established between the client end and the service end, a ready message displayed on the webpage, an active communication session established at the client end and the service end, a session key for session registration, and one or more voice communication devices.

Semiconductor Device and Method

A four-layer photoresist and method of forming the same are disclosed. In an embodiment, a method includes forming a semiconductor fin; depositing a target layer on the semiconductor fin; depositing a BARC layer on the target layer; depositing a first mask layer over the BARC layer, the first mask layer being deposited using a plasma process with an RF power of less than 50 W; depositing a second mask layer over the first mask layer using a plasma process with an RF power of less than 500 W; depositing a photoresist layer over the second mask layer; patterning the photoresist layer, the second mask layer, the first mask layer, and the BARC layer to form a first mask; and selectively removing the target layer from a first portion of the semiconductor fin using the first mask, the target layer remaining on a second portion of the semiconductor fin.

Semiconductor fin cutting process and structures formed thereby

Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.

Method for multiple spacer width control

A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a first plurality of gate structures; blanket depositing a first dielectric layer over the first plurality of gate structures; blanket depositing a second dielectric layer over the first dielectric layer; etching back through a thickness of the first and second dielectric layers; blanket depositing a first photoresist layer to cover the first plurality and patterning to selectively expose at least a second plurality of gate structures; isotropically etching the at least a second plurality of gate structures for a predetermined time period to selectively etch away a predetermined portion of the first dielectric layer; and, selectively etching away the second dielectric layer to leave gate structures comprising a plurality of associated sidewall spacer widths.

Forming Doped Regions in Semiconductor Strips

A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip, and depositing a dielectric dose film on sidewalls of the semiconductor strip. The dielectric dose film is doped with a dopant of n-type or p-type. The remaining portions of the trenches are filled with a dielectric material. A planarization is performed on the dielectric material. Remaining portions of the dielectric dose film and the dielectric material form Shallow Trench Isolation (STI) regions. A thermal treatment is performed to diffuse the dopant in the dielectric dose film into the semiconductor strip. 1. A method comprising:forming a dielectric layer comprising a portion extending on a top surface of a semiconductor region, wherein the dielectric layer is un-doped with p-type and n-type dopants;depositing a dose film over the dielectric layer, wherein the dose film is formed of a dielectric material doped with a dopant of n-type or p-type; andperforming a thermal treatment to diffuse the dopant in the dose film into the semiconductor region.2. The method of further comprising etching a semiconductor substrate to form a trench claim 1 , wherein the semiconductor region comprising a sidewall facing the trench claim 1 , and the dielectric layer and the dose film extend into the trench.3. The method of claim 2 , wherein the dielectric layer and the dose film extend on the sidewall claim 2 , and the method further comprises:removing an upper portion of the dose film in the trench, with a lower portion of the dose film remaining, wherein the thermal treatment is performed after the removing the upper portion.4. The method of further comprising performing an additional thermal treatment to diffuse the dopant in the dose film into a top portion of the semiconductor region claim 2 , wherein the additional thermal treatment is performed before the top portion of the dose film is removed.5. The method of ...

Variable transmittance phase shifter to compensate for side lobe problem on rim type attenuating phase shifting masks

This invention describes an attenuating phase shifting mask, a method of forming the attenuating phase shifting mask, and a method of using the attenuating phase shifting mask to expose a contact hole pattern having both dense and isolated contact holes on a layer of photosensitive dielectric. The mask has a rim of first attenuating phase shifting material, having a first transmittance and providing a phase shift of 180°, surrounding the dense holes and a rim of second attenuating phase shifting material, having a second transmittance and providing a phase shift of 180°, surrounding the isolated holes. The second transmittance is greater than the first transmittance. The dense holes have a duty ratio of less than 2.0 and the isolated holes have a duty ratio of greater than or equal to 2.0. The second attenuating phase shifting material results from treating the first attenuating phase shifting material for a first time with a first solution which increases the transmittance and changes ...

Methods for information search and citation search

A computer-based information search method comprises the steps of: receiving a search query, the search query comprising at least one term; receiving a network resource list, the list comprising at least one web site selected from a predetermined web site list; semantically analyzing the search query; and searching the network resource list for a response to the search query using a search engine. A computer-based citation search method comprises the steps of: receiving a search query, the search query comprising an patent identification condition; receiving a list of patent databases; searching the list of patent databases to collect at least one reference patent that cites patents or is cited by patents satisfying the condition of the search query; and producing a citation list, the list comprising at least an owner of the reference patent.

Tiling electronic apparatus

An electronic device and a tiling electronic apparatus are disclosed and include a base substrate, a first circuit layer and a plurality of light-emitting elements. The base substrate has a first surface and a second surface opposite to each other. The first circuit layer includes a first portion and a second portion. The first portion is disposed on the first surface of the base substrate, and the second portion is disposed on the second surface of the base substrate. The light-emitting elements are disposed on the first portion of the first circuit layer. At least one of the second surface of the base substrate and the first portion of the first circuit layer includes at least one microstructure.

SEMICONDUCTOR DIE, SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A semiconductor die, a semiconductor package and manufacturing methods thereof are provided. The semiconductor die includes: a front-end-of-line (FEOL) structure, built on a semiconductor substrate; a back-end-of-line (BEOL) structure, formed on the FEOL structure, and including a stack of metallization layers; and bonding metals, disposed on the BEOL structure. The bonding metals include: a conductive pad, disposed over the BEOL structure, and electrically connected to the metallization layers in the BEOL structure; a conductive capping layer, lining along a top surface of the conductive pad; and an engaging feature, landing on the conductive capping layer and separated from the conductive pad by the conductive capping layer. The semiconductor die is bonded to another semiconductor die or a package component by the engaging feature.

Electronic device

An electronic device is disclosed and includes a base substrate, a first circuit layer and a plurality of light-emitting elements. The base substrate has a first surface and a second surface opposite to each other. The first circuit layer includes a first portion and a second portion. The first portion is disposed on the first surface of the base substrate, and the second portion is disposed on the second surface of the base substrate. The light-emitting elements are disposed on the first portion of the first circuit layer. At least one of the second surface of the base substrate and the first portion of the first circuit layer includes at least one microstructure.

Method to overcome image distortion of lines and contact holes in optical lithography

A process to correct distortions due to optical proximity effects is described. A two reticle per pattern approach is used. The first, or primary, reticle contains the image that is to be transferred to the photoresist. It is used to expose the resist in the usual way to the correct dosage of light needed to optimally activate it. For a primary reticle bearing a line pattern, the second, or correction, reticle bears a pattern of rectangles which are located and dimensioned so that, when aligned relative to the primary reticle, they overlap all line ends in the pattern. The amount by which the rectangles overlap the lines is similar to the amount by which serifs (if they had been used) would overlap. The amount by which the rectangles extend outside the line ends is not critical (provided it is at least as large as the inside overlap amount). This property allows a single rectangle to be shared by many line ends. After the first exposure, the correction reticle is substituted for the primary ...

Simplified process for making an outrigger type phase shift mask

A simple, cost-effective method for forming a lithography mask with a directly imaged portion and an attenuated, phase shifted portion. In particular, the use of such a method for forming an outrigger-type phase shift mask. The mask is formed on a blank consisting of a transparent quartz substrate over which is an attenuating phase shift layer and an optically opaque layer, by a process that produces a pattern in an E-beam sensitive resist with two different E-beam energy depositions. The higher energy deposition is used to form the main pattern, while the lower energy deposition forms the pattern for the outrigger.

Forming doped regions in semiconductor strips

A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip, and depositing a dielectric dose film on sidewalls of the semiconductor strip. The dielectric dose film is doped with a dopant of n-type or p-type. The remaining portions of the trenches are filled with a dielectric material. A planarization is performed on the dielectric material. Remaining portions of the dielectric dose film and the dielectric material form Shallow Trench Isolation (STI) regions. A thermal treatment is performed to diffuse the dopant in the dielectric dose film into the semiconductor strip.

Forming Doped Regions in Semiconductor Strips

A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip, and depositing a dielectric dose film on sidewalls of the semiconductor strip. The dielectric dose film is doped with a dopant of n-type or p-type. The remaining portions of the trenches are filled with a dielectric material. A planarization is performed on the dielectric material. Remaining portions of the dielectric dose film and the dielectric material form Shallow Trench Isolation (STI) regions. A thermal treatment is performed to diffuse the dopant in the dielectric dose film into the semiconductor strip. 1. A device comprising:a semiconductor substrate; a dielectric liner;', 'a first dose film comprising a portion overlying a first bottom portion of the dielectric liner, wherein the first dose film comprises a first dopant of a first conductivity type selected from p-type and n-type; and', 'a dielectric region over a second bottom portion of the first dose film;, 'an isolation region extending into the semiconductor substrate, wherein the isolation region comprisesa semiconductor fin protruding higher than top surfaces of the isolation region; anda gate stack extending on a top surface and sidewalls of the semiconductor fin.2. The device of claim 1 , wherein the first dose film comprises sidewall portions connecting to opposing ends of the second bottom portion of the first dose film.3. The device of claim 1 , wherein the first dopant has a highest doping concentration in the first dose film claim 1 , and doping concentrations of the first dopant in the dielectric liner and the dielectric region are lower than the highest doping concentration.4. The device of claim 1 , wherein the first dose film comprises silicon oxide claim 1 , with the first dopant being doped in the silicon oxide.5. The device of further comprising an anti-punch-through region in a portion of the semiconductor substrate claim ...

Modified CBD/RGD recombinant attachment factor for improving cell-attachment efficiency and the manufacturing method thereof

A modified CBD/RGD recombinant attachment factor for improving cell attachment efficiency and the manufacturing method thereof, wherein the Arg-Gly-Asp (RGD) amino acid sequence is grafted on the C-terminal having a cellulose binding domain (CBD), thus the CBD-RGD polypeptide is capable of promoting the cell to attach onto the cellulose culturing plate; and as an RGD sequence is added, it can be accommodated in a stable annular structure built up by disulfide bonds, and is grafted on the N-terminal of said cellulose binding domain (CBD); thus, a CBD/RGD recombinant attachment factor for improving the promotion capability of cell-attachment is composed, and therefore the promotion capability of cell-attachment can be enhanced conspicuously.

Microfluidic device and method for operating thereof

The present invention provides a microfluidic device which comprises a drive module and a microfluidic platform. The drive module further comprises a rotary unit and a vibration unit for driving the microfluidic platform, and the microfluidic platform further comprises multiple microfluidic elements for performing tests. The present invention also provides a method for operating a microfluidic device. The method comprises steps using the rotary unit and steps using the vibration unit to distribute sample in a microfluidic structure.

Cut Metal Gate Devices and Processes

A method includes etching a gate structure to form a trench extending into the gate structure, wherein sidewalls of the trench comprise a metal oxide material, applying a sidewall treatment process to the sidewalls of the trench, wherein the metal oxide material has been removed as a result of applying the sidewall treatment process and filling the trench with a first dielectric material to form a dielectric region, wherein the dielectric region is in contact with the sidewall of the gate structure.

UNICAST AND BROADCAST PROTOCOL FOR WIRELESS LOCAL AREA NETWORK RANGING AND DIRECTION FINDING

Disclosed embodiments facilitate wireless channel calibration, ranging, and direction finding, between networked devices. A method on a first station (STA) may comprise: broadcasting, at a first time, a first NDPA frame to a plurality of second STAs. The first NDPA frame may include a first bit indicating that one or more subsequent frames comprise ranging or angular information. After a Short Interval Frame Space (SIFS) time interval from the first time, a second frame may be broadcast. The second frame may be a Null Data Packet (NDP) frame. In response, a plurality of Compressed Beamforming (CBF) frames may be received at the first STA where each CBF frame may be received from a distinct corresponding second STA, and may include Channel Feedback Information field with information pertaining to communication channel between the first STA and the corresponding second STA. The communications may be encoded using Orthogonal Frequency Division Multiple Access. 1. A method on a first station (STA) comprising:broadcasting, at a first time, a first NDPA frame to a plurality of second stations (STAs), the first NDPA frame comprising a first bit indicating that one or more subsequent frames comprise ranging or angular information; a Null Data Packet az (NDP_az) frame with information about a time of transmission of the NDP_az frame, or', 'a Null Data Packet (NDP) frame; and, 'broadcasting, after a Short Interval Frame Space (SIFS) time interval from the first time, a second frame to the plurality of second station (STAs), wherein the second frame is one of received from a distinct corresponding second STA in the plurality of second STAs, and', 'comprises a corresponding Channel Feedback Information (CFI) field with information pertaining to communication channel between the first STA and the corresponding second STA., 'receiving, at the first STA, in response to the second frame, a plurality of Compressed Beamforming (CBF) frames, wherein each CBF frame in the plurality of ...

ELECTRONIC DEVICE

An electronic device is disclosed and includes a base substrate, a circuit layer, and a plurality of light-emitting elements. The base substrate has a plurality of through holes, the circuit layer is disposed on the base substrate, and the light-emitting elements are disposed on the first circuit layer. An absolute value of a difference between two adjacent spacings of the plurality of through holes of the base substrate is less than 0.5 times radius of curvature of the electronic device when the electronic device is bent.

Automatic patent claim reader and computer-aided claim reading method

A method of analyzing a claim in a patent or patent application is disclosed, comprising retrieving a patent claim which has been rendered into a format parsable by a computer program into a computer memory; parsing the claim into a set of discrete elements; categorizing each element in the set of elements according to a predetermined rule; and storing a set of categorized elements in a data store. A parsing program executable in a computer may be used to parse the patent claim and, optionally, to identify one or more keyword sets in the parsed claim. A rating program may also be used to assign a rating weight to each categorized element. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Approach to increase the resolution of dense line/space patterns for 0.18 micron and below design rules using attenuating phase shifting masks

A mask and method of forming a pattern on an integrated circuit wafer having regions of dense line/space patterns and regions of isolated lines or widely spaced line/space patterns. The mask uses a binary mask pattern to form the dense line/space region and an attenuating phase shifting mask pattern to form the isolated line or widely spaced line/space region. Scattering bars are used in the widely spaced line/space region of the mask to improve depth of focus. The method uses the mask in a projection exposure system to expose a layer of photosensitive dielectric on an integrated circuit wafer.

Semiconductor Structures With Shallow Trench Isolations

A method is disclosed that includes the operations outlined below. An insulating material is disposed within a plurality of trenches on a semiconductor substrate and over the semiconductor substrate. The first layer is formed over the insulating material. The first layer and the insulating material are removed. 1. A method comprising:disposing an insulating material within a plurality of trenches on a semiconductor substrate and over the semiconductor substrate;forming a first layer over the insulating material; andremoving the first layer and the insulating material.2. The method of claim 1 , wherein the first layer has a substantially flat surface.3. The method of claim 1 , wherein the first layer is formed by a spin-coating process.4. The method of claim 1 , wherein the insulating material comprises oxide.5. The method of claim 1 , wherein the first layer comprises a layer of photoresist.6. The method of claim 1 , wherein removing the first layer and the insulating material is performed by at least one of a chemical mechanical polishing (CMP) process claim 1 , an etching process claim 1 , a sputter process claim 1 , a laser process and combinations thereof.7. The method of claim 1 , wherein a portion of the first layer is etched claim 1 , and the rest of the first layer and the insulating material are removed by a chemical mechanical polishing (CMP) process.8. The method of claim 1 , wherein the first layer and the insulating material have a similar etch rate.9. The method of claim 1 , wherein at least two trenches of the plurality of the trenches have different depths.10. A method comprising:coating an insulating layer with a first layer by a spin-coating process; andremoving the first layer and the insulating layer;wherein the insulating layer fills a plurality of trenches on a semiconductor substrate and covers the semiconductor substrate, andat least two of the plurality of trenches have different depths.11. The method of claim 10 , wherein the first layer ...

Surface treated low-k dielectric as diffusion barrier for copper metallization

A Cu damascene structure is formed where Cu diffusion barrier is formed by treating the top surface of the surrounding low-k interlayer dielectric with nitrogen or carbon containing medium to form a silicon nitride or silicon carbide diffusion barrier rather than capping the top surface of the Cu with metal diffusion barrier as is conventionally done.

Semiconductor Fin cutting process and structures formed thereby

Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.

High aspect ratio gap fill application using high density plasma chemical vapor deposition

A high density plasma chemical vapor deposition process including exciting gas mixture to create a plasma including ions, and directing the plasma into a dense region above the upper surface of the semiconductor wafer, heating the wafer using an additional heat source, and allowing a material from the plasma to deposit onto the semiconductor wafer.

Semiconductor structure with barrier layer and method for forming the same

A method for forming a semiconductor structure is provided. The method includes forming a gate structure over a fin structure, forming a source/drain structure in the fin structure and adjacent to the gate structure, forming a dielectric layer over the gate structure and the source/drain structure, and forming an opening in the dielectric layer to expose the source/drain structure. The method further includes depositing a barrier layer lining a sidewall surface of the opening and a top surface of the source/drain structure. The method further includes etching a portion of the barrier layer to expose the source/drain structure. The method further includes depositing a glue layer covering the sidewall surface of the opening and the source/drain structure in the opening. The method further includes forming a contact structure filling the opening in the dielectric layer. The contact structure is surrounded by the glue layer.

Method of forming DRAM capactiors with protected outside crown surface for more robust structures

A method for fabricating a high-density array of crown capacitors with increased capacitance while reducing process damage to the bottom electrodes is achieved. The process is particularly useful for crown capacitors for future DRAM circuits with minimum feature sizes of 0.18 micrometer or less. A conformal conducting layer is deposited over trenches in an interlevel dielectric (ILD) layer, and is polished back to form capacitor bottom electrodes. A novel photoresist mask and etching are then used to pattern the ILD layer to provide a protective interlevel dielectric structure between capacitors. The protective structures prevent damage to the bottom electrodes during subsequent processing. The etching also exposes portions of the outer surface of bottom electrodes for increased capacitance (>50%). In a first embodiment the ILD structure is formed between pairs of adjacent bottom electrodes, and in a second embodiment the ILD structure is formed between four adjacent bottom electrodes.

Semiconductor structure with barrier layer and method for forming the same

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a gate spacer, a source/drain structure, a contact structure, a glue layer and a barrier layer. The gate structure is positioned over a fin structure. The gate spacer is positioned over the fin structure and on a sidewall surface of the gate structure. The source/drain structure is positioned in the fin structure and adjacent to the gate spacer. The contact structure is positioned over the source/drain structure. The glue layer covers a bottom surface and a sidewall surface of the contact structure. The barrier layer encircles the sidewall surface of the contact structure. A bottom surface of the glue layer is exposed to the barrier layer.

Multi-focus scanning with a tilted mask or wafer

A method for implementing discrete superpositioning of two or more defocal wafer images at different defocal positions in a lithographic step and scan projection system. The method includes tilting one of a mask and a wafer with respect to a scanning direction and splitting an illumination beam into at least two illumination areas which are in different defocus zones of the mask.

POLY SILICON HARD MASK

A method of forming an opening on a low-k dielectric layer using a polysilicon hard mask rather than a metal hard mask as used in prior art. A polysilicon hard mask is formed over a low-k dielectric layer and a photoresist layer is formed over the polysilicon hard mask. The photoresist layer is patterned and the polysilicon hard mask is etched with a gas plasma to create exposed portions of the low-k dielectric layer. The photoresist layer in stripped prior to the etching of the exposed portions of the low-k dielectric layer to avoid damage to the low-k dielectric layer.

Blockchain system and method thereof

A method includes the steps of: monitoring status information of a blockchain system; determining whether the status information meets a blockchain branch condition; when the status information matches the blockchain branch condition, writing a branch instruction to a selected block of the blockchain, wherein the branch instruction is configured to enable the blockchain to form a plurality of branches, and divide a plurality of blockchain devices in the blockchain system into a plurality of groups to verify the branches in parallel; and obtaining a maximum transmission delay time in the group, and deciding a new one to generate blocks of the first branch according to the maximum transmission delay time.

Semiconductor device and method

A four-layer photoresist and method of forming the same are disclosed. In an embodiment, a method includes forming a semiconductor fin; depositing a target layer on the semiconductor fin; depositing a BARC layer on the target layer; depositing a first mask layer over the BARC layer, the first mask layer being deposited using a plasma process with an RF power of less than 50 W; depositing a second mask layer over the first mask layer using a plasma process with an RF power of less than 500 W; depositing a photoresist layer over the second mask layer; patterning the photoresist layer, the second mask layer, the first mask layer, and the BARC layer to form a first mask; and selectively removing the target layer from a first portion of the semiconductor fin using the first mask, the target layer remaining on a second portion of the semiconductor fin.

Forming doped regions in semiconductor strips

A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip, and depositing a dielectric dose film on sidewalls of the semiconductor strip. The dielectric dose film is doped with a dopant of n-type or p-type. The remaining portions of the trenches are filled with a dielectric material. A planarization is performed on the dielectric material. Remaining portions of the dielectric dose film and the dielectric material form Shallow Trench Isolation (STI) regions. A thermal treatment is performed to diffuse the dopant in the dielectric dose film into the semiconductor strip.

Surface treatment of metal interconnect lines

Apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.

UNICAST AND BROADCAST PROTOCOL FOR WIRELESS LOCAL AREA NETWORK RANGING AND DIRECTION FINDING

Disclosed embodiments facilitate wireless channel calibration, including ranging and direction finding, between wirelessly networked devices. In some embodiments. a method on a first station (STA) may comprise: transmitting a first NDPA frame to one or more second stations (STAs), the first NDPA frame comprising a first bit indicating that one or more subsequent frames comprise ranging or angular information; and transmitting, after a Short Interval Frame Space (SIFS) time interval, a second frame. The second frame may be one of: a Null Data Packet az (NDP_az) frame with information about a time of transmission of the NDP_az frame, or a Null Data Packet (NDP) frame, or a Beam Refinement Protocol (BRP) frame. The first NDPA frame may be unicast, multicast, or broadcast. 1. A method on a first station (STA) comprising:transmitting, at a first time, a first NDPA frame to one or more second stations (STAs), the first NDPA frame comprising a first bit indicating that one or more subsequent frames comprise ranging or angular information; and a Null Data Packet az (NDP_az) frame with information about a time of transmission of the NDP_az frame, or', 'a Null Data Packet (NDP) frame, or', 'a Beam Refinement Protocol (BRP) frame., 'transmitting, after a Short Interval Frame Space (SIFS) time interval from the first time, a second frame, wherein the second frame is one of2. The method of claim 1 , wherein:transmitting the first NDPA frame comprises unicasting the first NDPA frame to a corresponding STA of the one or more second STAs; andtransmitting the second frame comprises unicasting the second frame to the corresponding STA of the one or more second STAs.3. The method of claim 2 , further comprising:receiving, at the first STA, in response to the second frame, a Fine Timing Measurement (FTM) frame from the corresponding STA with at least one of:a first timing information for Round Trip Time (RTT) calculations by the first STA, the first timing information comprising one or ...

Selective spacer layer deposition method for forming spacers with different widths

A method of forming spacers with different widths on a semiconductor substrate, includes the steps of disposing a first spacer layer over the substrate, defining the first spacer layer into a plurality of spacers of a first width, and disposing a second spacer layer selectively over the first spacer layer of a number of the spacers preselected for the second spacer layer, the predetermined number of the spacers with the second spacer layer each having a second width which is different from the first width.

Cut metal gate devices and processes

A method includes etching a gate structure to form a trench extending into the gate structure, wherein sidewalls of the trench comprise a metal oxide material, applying a sidewall treatment process to the sidewalls of the trench, wherein the metal oxide material has been removed as a result of applying the sidewall treatment process and filling the trench with a first dielectric material to form a dielectric region, wherein the dielectric region is in contact with the sidewall of the gate structure.

ELECTRONIC DEVICE

The present disclosure provides an electronic device including a substrate, a first circuit layer, and a plurality of diodes. The substrate has a plurality of first through holes. The first circuit layer is disposed on the substrate and has a plurality of light through holes. The diodes disposed on the first circuit layer. One of the light through holes is located between two adjacent ones of the diodes, and the light through holes overlap a portion of the plurality of first through holes and do not overlap another portion of the plurality of first through holes in a normal direction of the substrate.

Gas distribution systems for deposition processes

Gas distribution systems for deposition processes and methods of using the same. A substrate support member holding a substrate is disposed in a processing chamber. A plurality of first and second gas nozzles is connected to a gas distribution ring disposed in the processing chamber. The first gas nozzles provide a first reactant gas and include at least first and second outlet apertures. The second gas nozzles provide a second reactant gas and include third outlet apertures. The first outlet aperture is larger than the second outlet aperture, such that the first gas nozzle with the first outlet aperture creates an increased gas flow adjacent to a determined portion of the substrate to increase deposition from the first reactant gas on the determined portion of the substrate.

ELECTRONIC DEVICE AND TILING ELECTRONIC APPARATUS

An electronic device and a tiling electronic apparatus are disclosed and include a base substrate, a first circuit layer and a plurality of light-emitting elements. The base substrate has a first surface and a second surface opposite to each other. The first circuit layer includes a first portion and a second portion. The first portion is disposed on the first surface of the base substrate, and the second portion is disposed on the second surface of the base substrate. The light-emitting elements are disposed on the first portion of the first circuit layer. At least one of the second surface of the base substrate and the first portion of the first circuit layer includes at least one microstructure.

Surface treatment of metal interconnect lines

Methods and apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.

Forming Doped Regions in Semiconductor Strips

A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip, and depositing a dielectric dose film on sidewalls of the semiconductor strip. The dielectric dose film is doped with a dopant of n-type or p-type. The remaining portions of the trenches are filled with a dielectric material. A planarization is performed on the dielectric material. Remaining portions of the dielectric dose film and the dielectric material form Shallow Trench Isolation (STI) regions. A thermal treatment is performed to diffuse the dopant in the dielectric dose film into the semiconductor strip. 1. A method comprising:etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip;forming a dielectric dose film on a lower portion of a sidewall of the semiconductor strip, wherein the dielectric dose film is doped with a dopant of n-type or p-type, and a top end of the dielectric dose film is lower than a top surface of the semiconductor strip; andperforming a thermal treatment to diffuse the dopant in the dielectric dose film into the semiconductor strip, wherein the thermal treatment results in the dopant to be diffused into a bottom portion of the semiconductor strip.2. The method of claim 1 , wherein the forming the dielectric dose film comprises:depositing a blanket dose film; andetching upper portions of the blanket dose film on a top surface and sidewalls of the semiconductor strip, with lower portions of the blanket dose film remaining as the dielectric dose film, and the thermal treatment is performed on the blanket dose film that has been etched.3. The method of further comprising:filling remaining portions of the trenches with a dielectric material, with the dielectric material over the blanket dose film; andperforming a planarization on the dielectric material, wherein remaining portions of the ...

Electronic device

An electronic device is disclosed and includes a base substrate, a circuit layer, and a plurality of light-emitting elements. The base substrate has a plurality of through holes, the circuit layer is disposed on the base substrate, and the light-emitting elements are disposed on the first circuit layer. An absolute value of a difference between two adjacent spacings of the plurality of through holes of the base substrate is less than 0.5 times radius of curvature of the electronic device when the electronic device is bent.

Forming doped regions in semiconductor strips

A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip, and depositing a dielectric dose film on sidewalls of the semiconductor strip. The dielectric dose film is doped with a dopant of n-type or p-type. The remaining portions of the trenches are filled with a dielectric material. A planarization is performed on the dielectric material. Remaining portions of the dielectric dose film and the dielectric material form Shallow Trench Isolation (STI) regions. A thermal treatment is performed to diffuse the dopant in the dielectric dose film into the semiconductor strip.

MICROFLUIDIC DEVICE AND METHOD FOR OPERATING THEREOF

The present invention provides a microfluidic device which comprises a drive module and a microfluidic platform. The drive module further comprises a rotary unit and a vibration unit for driving the microfluidic platform, and the microfluidic platform further comprises multiple microfluidic elements for performing tests. The present invention also provides a method for operating a microfluidic device. The method comprises steps using the rotary unit and steps using the vibration unit to distribute sample in a microfluidic structure. 1. A microfluidic device , comprising:a drive module, containing a rotary unit and a vibration unit; and an injection chamber, for accommodating a sample;', 'a metering chamber, connected with the injection chamber; and', 'a reaction chamber, connected with the measuring chamber, for accommodating a test strip., 'a microfluidic platform, mounting on the drive module, controlled by the rotary unit and the vibration unit, wherein the microfluidic platform contains a center of rotation and at least one microfluidic element, and wherein each microfluidic element further comprises2. The microfluidic device according to claim 1 , wherein the microfluidic platform contains multiple microfluidic elements claim 1 , and wherein at least two injection chamber are integrated with each other.3. The microfluidic device according to claim 1 , wherein each microfluidic element further comprises:an overflow chamber; anda microfluidic channel, connected between the metering chamber and the overflow chamber.4. The microfluidic device according to claim 3 , wherein the metering chamber and the reaction chamber are connected at a first access claim 3 , and the microfluidic channel and the overflow chamber are connected at a second access claim 3 , and wherein the distance from the center of rotation to the first access is equal to or smaller than the distance from the center of rotation to the second access.5. The microfluidic device according to claim 3 , ...

CENTRIFUGE/MAGNET-BASED ANALYZERS AND METHOD OF OPERATING THEREOF

The present invention provides centrifuge/magnet-based analyzers and methods of operating thereof. The analyzer comprises three discs sandwiched together, in which each disc has difference functions. The top disc comprises magnetic units configured in patterns, whereas the bottom disc comprises tracks and magnetic units free to move in the tracks. The magnetic field co-generated by the top disc and the bottom disc attracts the magnetic beads in the intermediate disc to move and thus facilitates the reactions in the intermediate disc. 1. A centrifuge/magnet-based analyzer , comprising:a first disc, comprising multiple first magnetic units, wherein the multiple first magnetic units are located on the same radius ring or different radius rings centered on the center of the first disc; a first air vent, disposed at the center of the second disc;', 'a first main chamber, connected with the first air vent;', 'a second main chamber, comprising a second air vent, wherein the second main chamber is connected to the first main chamber via a first microvalve; and', 'a third main chamber, comprising a third air vent, wherein the third main chamber is connected to the second main chamber via a second microvalve;', an entry, connected to the third microvalve;', 'an incubation chamber, connected to the entry;', 'a sample chamber, connected to the incubation chamber;', 'a detection chamber, connected to the incubation chamber;', 'a waste chamber, connected to the detection chamber via a fourth microvalve; and', 'a forth air valve, connected to the waste chamber; and, 'multiple reaction units, wherein each reaction unit is connected to the third chamber via a third microvalve, and wherein each reaction unit comprises, 'a third disc, configured below and attached to the second disc, comprising multiple tracks, wherein each track accommodates a second magnetic unit, and wherein the second magnetic unit is movable;', 'wherein the number of the at least one reaction unit is equal to the ...

APPARATUSES WITH PRE-PACKAGED REAGENTS

Apparatuses with pre-packaged reagents comprise a reagent package and a protrusion member. More particularly, the reagent package comprises a base and a cover layer, in which the base further comprises at least one pocket. Each pocket is configured to store a reagent, and the cover layer is configured on the at least one pocket to seal the at least one pocket. The protrusion member further comprises an opening and is configured at an injection site, in which the injection site is on each storage chamber disposed on a microfluidic disc. Furthermore, the configuration of the pockets on the base is in accordance with the configuration of the protrusion members. Therefore, the protrusion members would punch through the pockets once the protrusion members are aligned and combined to the pockets. And the following rotation of the microfluidic disc would generate centrifugal force and sequentially release reagents into storage chambers. 1. An apparatus with pre-packaged reagents , comprising: a base comprising at least one pocket, wherein the at least one pocket each is configured to store a reagent; and', 'a cover layer disposed on the at least one pocket, wherein the cover layer is configured to seal the at least one pocket; and, 'a reagent package, comprisingat least one protrusion member having an opening, wherein the at least one protrusion member is disposed at an injection site, and wherein the injection site is located at each storage chamber configured on each microfluidic channel disposed on a microfluidic disc;wherein the position of the at least one pocket on the base is in accordance with the position of the at least one protrusion member;wherein the at least one protrusion member is configured to punch through the cover layer when the at least one pocket is aligned and combined with the at least one protrusion member and to sequentially release the reagent in the at least one pocket into the storage chamber by the centrifugal force generated by rotation of ...

Gas-based microfluidic devices and operating methods thereof

Gas-based microfluidic devices and operating methods of gas-based microfluidic devices are provided. The gas-based microfluidic devices comprise a drive module and a microfluidic platform, in which the microfluidic platform further comprises a microfluidic element having an injection chamber, a process chamber, an air chamber, an overflow channel, a barrier, and at least one detection chamber. Gases in the air chamber enable solutions to move toward the direction opposite to the centrifugal force applied by the drive module. Accordingly, the operating methods utilize the gases compressed in the air chamber to move solutions to difference components in the microfluidic element.

SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME

Semiconductor device structures and methods for forming the same are provided. A method for forming a semiconductor device structure includes forming a gate structure over a semiconductor substrate. The method also includes forming spacer elements adjoining sidewalls of the gate structure. The method further includes forming a protection material layer over the gate structure. The formation of the protection material layer includes a substantial non-plasma process. In addition, the method includes depositing a dielectric material layer over the protection material layer. The deposition of the dielectric material layer includes a plasma-involved process. 1. A method for forming a semiconductor device structure , comprising:forming a gate structure over a semiconductor substrate;forming spacer elements adjoining sidewalls of the gate structure;forming a protection material layer over the gate structure, wherein the formation of the protection material layer comprises a non-plasma process; anddepositing a dielectric material layer over the protection material layer, wherein the deposition of the dielectric material layer comprises a plasma process.2. The method for forming a semiconductor device structure as claimed in claim 1 , wherein the formation of the protection material layer comprises oxidizing a top surface of the gate structure.3. The method for forming a semiconductor device structure as claimed in claim 1 , wherein the formation of the protection material layer comprises a non-plasma chemical vapor deposition process claim 1 , a non-plasma atomic layer deposition process claim 1 , a non-plasma thermal deposition process claim 1 , or a combination thereof.4. The method for forming a semiconductor device structure as claimed in claim 1 , wherein the plasma process comprises a plasma-enhanced chemical vapor deposition process.5. The method for forming a semiconductor device structure as claimed in claim 1 , wherein the spacer elements and the gate structure ...

THERMAL GREASE HAVING LOW THERMAL RESISTANCE

A thermally conductive grease includes a carrier oil, at least one dispersant, and thermally conductive particles. The thermally conductive particles have a D50 (Vol. Average) particle size of no greater than about 11 microns and the thermally conductive particles in the thermally conductive grease contain less than 3% by volume of particles having a particle size of 0.7 microns or less, based on the total volume of thermally conductive particles in the thermally conductive grease. 1. A thermally conductive grease comprising:a carrier oil;a dispersant; andthermally conductive particles, wherein the thermally conductive particles have a D50 (Vol. Average) particle size of no greater than about 11 microns, and wherein the thermally conductive particles in the thermally conductive grease contain less than about 3% by volume of particles having a particle size of 0.7 microns or less, based on a total volume of thermally conductive particles in the thermally conductive grease.2. The thermally conductive grease of claim 1 , wherein the carrier oil is one of a hydrocarbon based carrier oil and a silicone oil.3. The thermally conductive grease of claim 1 , wherein when the carrier oil is a hydrocarbon based carrier oil claim 1 , the carrier oil is selected from the group consisting of: polyol esters claim 1 , epoxides claim 1 , and polyolefins or a combination thereof.4. The thermally conductive grease of claim 1 , further comprising a thixotropic agent.5. The thermally conductive grease of claim 1 , wherein the thermally conductive particles comprise materials selected from the group consisting of: diamond claim 1 , polycrystalline diamond claim 1 , silicon carbide claim 1 , alumina claim 1 , boron nitride (hexagonal or cubic) claim 1 , boron carbide claim 1 , silica claim 1 , graphite claim 1 , amorphous carbon claim 1 , aluminum nitride claim 1 , aluminum claim 1 , zinc oxide claim 1 , nickel claim 1 , tungsten claim 1 , silver claim 1 , and combinations thereof.6. The ...

Semiconductor structure with barrier layer and method for forming the same

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a gate spacer, a source/drain structure, a contact structure, a glue layer and a barrier layer. The gate structure is positioned over a fin structure. The gate spacer is positioned over the fin structure and on a sidewall surface of the gate structure. The source/drain structure is positioned in the fin structure and adjacent to the gate spacer. The contact structure is positioned over the source/drain structure. The glue layer covers a bottom surface and a sidewall surface of the contact structure. The barrier layer encircles the sidewall surface of the contact structure. A bottom surface of the glue layer is exposed to the barrier layer.

SEMICONDUCTOR STRUCTURE CUTTING PROCESS AND STRUCTURES FORMED THEREBY

Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV. 1. A structure comprising:a first fin on a substrate;a second fin on the substrate, the first fin and the second fin being longitudinally aligned; and an insulating liner abutting a first sidewall of the first fin and a second sidewall of the second fin, the insulating liner comprising a material with a band gap greater than 5 eV; and', 'a fill material on the insulating liner., 'a fin cut-fill structure disposed between the first fin and the second fin, the fin cut-fill structure comprising2. The structure of claim 1 , wherein the material of the insulating liner is selected from the group consisting of silicon oxide (SiO) claim 1 , aluminum oxide (AlO) claim 1 , titanium oxide (TiO) claim 1 , tantalum oxide (TaO) claim 1 , aluminum fluoride (AlF) claim 1 , aluminum oxyfluoride (AlOF) claim 1 , zirconium silicate (ZrSiO) claim 1 , hafnium silicate (HfSiO) claim 1 , hafnium oxide (HfO) claim 1 , zirconium oxide (ZrO) claim 1 , or a combination thereof.3. The structure of claim 1 , wherein the fill material is an insulating material.4. The structure of claim 1 , wherein the fill material is silicon nitride.5. The structure of further comprising neighboring isolation regions claim 1 , the first fin and the second fin each protruding from between the neighboring isolation regions claim 1 , a bottom surface of the fin cut-fill structure being below respective top surfaces of the neighboring ...

Thermoplastic polyurethane compositions, articles, and methods thereof

Disclosed herein are improved thermoplastic polyurethane compositions, articles, and related methods. These compositions include aliphatic thermoplastic polyurethanes having a hard segment content ranging from 57 percent to 80 percent by weight. The hard coat compositions have a Shore D hardness of at least 70 and can display an Elongation at Break test result at 25 degrees Celsius of at least 150 percent. These materials, when hardened, can serve decorative and/or protective functions while displaying both a high degree of elongation at moderate temperatures and high hardness.

Semiconductor structure with barrier layer and method for forming the same

A method for forming a semiconductor structure is provided. The method includes forming a gate structure over a fin structure, forming a source/drain structure in the fin structure and adjacent to the gate structure, forming a dielectric layer over the gate structure and the source/drain structure, and forming an opening in the dielectric layer to expose the source/drain structure. The method further includes depositing a barrier layer lining a sidewall surface of the opening and a top surface of the source/drain structure. The method further includes etching a portion of the barrier layer to expose the source/drain structure. The method further includes depositing a glue layer covering the sidewall surface of the opening and the source/drain structure in the opening. The method further includes forming a contact structure filling the opening in the dielectric layer. The contact structure is surrounded by the glue layer.

BLOCKCHAIN SYSTEM AND METHOD THEREOF

A method includes the steps of: monitoring status information of a blockchain system; determining whether the status information meets a blockchain branch condition; when the status information matches the blockchain branch condition, writing a branch instruction to a selected block of the blockchain, wherein the branch instruction is configured to enable the blockchain to form a plurality of branches, and divide a plurality of blockchain devices in the blockchain system into a plurality of groups to verify the branches in parallel; and obtaining a maximum transmission delay time in the group, and deciding a new one to generate blocks of the first branch according to the maximum transmission delay time. 1. A method implemented in a blockchain system , the blockchain system comprising a plurality of blockchain devices that participate in a verification of a blockchain to generate a plurality of blocks in the blockchain , wherein the method comprises:monitoring a status information of the blockchain system by a first blockchain device of the blockchain devices;determining whether the status information complies with a blockchain branch condition by the first blockchain device;when the first blockchain device determines that the status information complies with the blockchain branch condition, the first blockchain device writes a branch instruction to a selected block in the blockchain, wherein the branch instruction is configured for enabling the blockchain to form a plurality of branches, and the blockchain devices are divided into a plurality of groups in response to the branch instruction for verifying the branches in parallel, wherein the first blockchain device joins a first group of the groups, and the first group is responsible for verifying a first branch of the branches; andobtaining an in-group maximum transmission delay time of the first group by the first blockchain device, and determining a time interval of generation of new block to generate a plurality ...

SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME

Semiconductor device structures and methods for forming the same are provided. A semiconductor device structure includes a gate structure over a semiconductor substrate. The gate structure includes a gate electrode layer and a gate dielectric layer covering a bottom surface and sidewalls of the gate electrode layer. The semiconductor device structure also includes spacer elements in contact with sidewalls of the gate structure and protruding from a top surface of the gate electrode layer. The semiconductor device structure also includes a first protection layer over the gate electrode layer and between the spacer elements. The semiconductor device structure also includes a dielectric layer over the first protection layer and between the spacer elements. A portion of the dielectric layer is between sidewalls of the spacer elements and sidewalls of the first protection layer. 1. A semiconductor device structure , comprising:a gate structure over a semiconductor substrate, wherein the gate structure comprises a gate electrode layer and a gate dielectric layer covering a bottom surface and sidewalls of the gate electrode layer;spacer elements in contact with sidewalls of the gate structure and protruding from a top surface of the gate electrode layer;a first protection layer over the gate electrode layer and between the spacer elements; anda dielectric layer over the first protection layer and between the spacer elements, wherein a portion of the dielectric layer is between sidewalls of the spacer elements and sidewalls of the first protection layer.2. The semiconductor device structure as claimed in claim 1 , wherein the gate electrode layer comprises a metal material claim 1 , and the first protection layer comprises an oxide containing the metal material.3. The semiconductor device structure as claimed in claim 1 , wherein the dielectric layer comprises silicon oxide claim 1 , silicon oxycarbide claim 1 , silicon nitride claim 1 , nitrogen silicon carbide claim 1 , ...

ELECTRONIC DEVICE

An electronic device includes a substrate, a light-emitting element, and a spacing structure. The light-emitting element is disposed on the substrate. The spacing structure is disposed adjacent to the light-emitting element, and the spacing structure includes a first wall, a second wall, and a boundary portion. The first wall includes a first protrusion portion and extends in a first direction. The second wall includes a second protrusion portion and extends in a second direction, and the first direction is different from the second direction. The boundary portion is connected to the first protrusion portion and the second protrusion portion, and the height of the boundary portion is lower than the height of the first protrusion portion. 1. An electronic device , comprising:a substrate;a light-emitting element disposed on the substrate; and a first wall comprising a first protrusion portion and extending in a first direction;', 'a second wall comprising a second protrusion portion and extending in a second direction; and', 'a boundary portion connected to the first protrusion portion and the second protrusion portion;, 'a spacing structure disposed adjacent to the light-emitting element, wherein the spacing structure compriseswherein the first direction is different from the second direction, and a height of the boundary portion is lower than a height of the first protrusion portion.2. The electronic device according to claim 1 , wherein the first direction is perpendicular to the second direction.3. The electronic device according to claim 1 , wherein the height of the boundary portion is lower than a height of the second protrusion portion.4. The electronic device according to claim 1 , wherein a thickness of the first protrusion portion is greater than a thickness of the boundary portion claim 1 , and a thickness of the second protrusion portion is greater than the thickness of the boundary portion.5. The electronic device according to claim 1 , wherein a ...

CELL-FREE NUCLEIC ACID STANDARDS AND USES THEREOF

The present disclosure provides cell-free nucleic acid standards comprising genomic polynucleotides and methods of using cell-free nucleic acid standards comprising genomic polynucleotides for developing, optimizing, and validating cell-free nucleic acid assays. 1. A method for estimating abundance of a target nucleic acid present in a cell-free nucleic acid (CFNA) sample comprising the target nucleic acid and non-target nucleic acids , the method comprising:(a) quantifying copy number of the target nucleic acid in the CFNA sample to obtain an observed abundance of the target nucleic acid; (i) at least a subset of the plurality of genomic polynucleotides of the CFNA standard have a length ranging from about 100-300 bases; and', '(ii) a majority of the genomic polynucleotides of the CFNA standard have a phosphate group at a 5′ terminal end and a hydroxyl group at a 3′ terminal end, which majority of genomic polynucleotides are ligatable without generating a phosphate group at a 5′ terminal end and/or generating a hydroxyl group at a 3′ terminal end; and, '(b) generating a calibration scheme by correlating an observed abundance of a reference nucleic acid present in a CFNA standard to an expected abundance of the reference nucleic acid present in the CFNA standard, which CFNA standard comprises a plurality of genomic polynucleotides, individual members of the plurality having a 5′ terminal end and a 3′ terminal end, wherein(c) estimating abundance of the target nucleic acid in the CFNA sample by adjusting the observed abundance of the target nucleic acid using the calibration scheme.2. The method of claim 1 , wherein less than 50% of individual genomic polynucleotides of the CFNA standard have identical sequences.3. The method of claim 1 , wherein the CFNA standard comprises a subset of genomic polynucleotides having identical members claim 1 , and wherein the subset represents less than 50% of the CFNA standard.4. The method of claim 1 , wherein at least 30% of the ...

COMPOSITE FLUORESCENT GOLD NANOCLUSTERS WITH HIGH QUANTUM YIELD AND METHOD FOR MANUFACTURING THE SAME

Disclosed herein are composite fluorescent gold nanoclusters with high quantum yield, as well as methods for manufacturing the same. According to some embodiments, the composite fluorescent gold nanocluster includes a gold nanocluster and a capping layer that encapsulates at least a portion of the outer surface of the gold nanocluster. The capping layer includes a matrix made of a benzene-based compound, and multiple phosphine-based compounds distributed across the matrix. 1. A composite fluorescent gold nanocluster , comprising ,a gold nanocluster; anda capping layer composed of a matrix made of a benzene-based compound, and a plurality of phosphine-based compounds distributed across the matrix;wherein, the capping layer encapsulates at least a portion of an outer surface of the gold nanocluster.2. The composite fluorescent gold nanocluster of claim 1 , wherein the benzene-based compound is selected from the group consisting of benzene claim 1 , alkylbenzene claim 1 , halobenzene claim 1 , phenol claim 1 , benzoic acid claim 1 , acetophenone claim 1 , methyl benzoate claim 1 , anisole claim 1 , aniline claim 1 , nitrobenzene claim 1 , benzonitrile claim 1 , benzamide claim 1 , benzenesulfonic acid claim 1 , naphthalene claim 1 , and anthracene.3. The composite fluorescent gold nanocluster of claim 2 , wherein claim 2 ,the alkylbenzene is toluene, cumene, ethylbenzene, styrene, or xylene; andthe halobenzene is fluorobenzene, chlorobenzene, bromobenzene, or iodobenzene.4. The composite fluorescent gold nanocluster to claim 3 , wherein the benzene-based compound is toluene.5. The composite fluorescent gold nanocluster of claim 1 , wherein the phosphine-based compounds is selected from the group consisting of phosphine claim 1 , phosphine oxide claim 1 , phosphonium claim 1 , diphosphine claim 1 , triphosphine claim 1 , alkyl phosphine claim 1 , cycloalkyl phosphine claim 1 , aryl phosphine claim 1 , aryl phosphine oxide claim 1 , bidentate phosphine claim 1 , silicone ...

A modified CBD/RGD recombinant attachment factor for improving cell-attachment efficiency and the manufacturing method thereof

A modified CBD/RGD recombinant attachment factor for improving cell attachment efficiency and the manufacturing method thereof, wherein the Arg-Gly-Asp (RGD) amino acid sequence is grafted on the C-terminal having a cellulose binding domain (CBD), thus the CBD-RGD polypeptide is capable of promoting the cell to attach onto the cellulose culturing plate; and as an RGD sequence is added, it can be accommodated in a stable annular structure built up by disulfide bonds, and is grafted on the N-terminal of said cellulose binding domain (CBD); thus, a CBD/RGD recombinant attachment factor for improving the promotion capability of cell-attachment is composed, and therefore the promotion capability of cell-attachment can be enhanced conspicuously.

Intelligence physiological monitoring device

Protection film composition for laser dicing and application thereof

【課題】本発明は、（Ａ）水溶性ポリマーと、（Ｂ）架橋剤とを含むレーザーダイシング用保護膜組成物を提供するものである。【解決手段】（Ａ）水溶性ポリマーの重量平均分子量（Ｍｗ）が１００００〜１５００００であり、特に１２５００〜１２５０００であることが好ましい。架橋剤を添加することによって、水溶性ポリマーの官能基の間に架橋反応を生じさせることで、水溶性ポリマーの熱安定性を向上させることができる。よって、この組成物をレーザーダイシング工程に応用することで、切削屑が付着しにくいことによって基材を保護し、且つ基材が汚染されるという問題を減らすことができる。そして、保護膜の熱安定性が向上することで、ダイシングする時、保護膜の安定性が向上し、保護膜を劣化させにくく、且つ切断線を平らにするという効果がある。【選択図】 図１

Methods and systems for disease detection

Provided herein are methods of determining that a subject has or is at risk of having a disease (e.g., cancer) using nucleic acid molecules derived from a cell-free biological sample of the subject.

Method and tool for transferring mask pattern

A testing method for network transmission speed

Mask containing subresolution line to minimize proximity effect of contact hole

A electrical connection structure pattern according to the present invention includes a relatively dense first electrical connection structure area to a second electrical connection structure area. First, the electrical connection structure pattern is expensed to generate a first dummy pattern. The area of the first dummy pattern is larger than that of electrical connection structure pattern. Next, a second dummy pattern is generated by narrowing the line width of the first dummy pattern. A third dummy pattern is obtained by using CAD. The area of the third dummy pattern is smaller than that of the second dummy pattern, but larger than that of the electrical connection structure pattern. A fourth dummy pattern is generated by using CAD to remove the overlap area between the second dummy pattern and the third dummy pattern.

Computer mouse

Electronic device and tiling electronic apparatus

Microfluidic disc analyzer

Cell-free nucleic acid standards and uses thereof

Photoelectric sensor for an X-Y position device

An improved photoelectric sensor for an X-Y input device, the input device including vertical and horizontal slotted discs at ends of respective vertical and horizontal shafts, the discs being situated adjacent but not touching one another, is made up of a single photoelectric sensor and a single LED installed on opposite sides of the portions of the slotted discs that are adjacent each other, with the photosensor including four photoelectric sensor areas A, B, C, and D located on a single chip and having a width corresponding to the width of a slot or slotted wall of the slotted disc such that the rotation direction of the respective discs can be determined by whether the phase difference between signals generated by sensors A and B, and between signals generated by sensors C and D, is positive or negative.

Project management method and information integration system

Access control and burglarproof system with immediately monitoring and controlling by mobile device

一種即時監控並提供行動裝置控制的門禁與防盜系統及其方法，驗證裝置定時提供回報請求至監控伺服端，而當監控伺服端於預設時間內連續經過預設次數未接收到回報請求時，生成警告訊息並發送至備用驗證裝置以執行鎖定功能並發出警報，同時行動裝置自監控伺服端獲得警告訊息，並以行動裝置所生成的控制指令透過監控伺服端對備用驗證裝置的控制，藉此可以達成當驗證裝置遭到破壞、故障或是電力中斷依然可提供門禁驗證與防盜的技術功效。

Cell-free nucleic acid standards and uses thereof

The present disclosure provides cell-free nucleic acid standards comprising genomic polynucleotides and methods of using cell-free nucleic acid standards comprising genomic polynucleotides for developing, optimizing, and validating cell-free nucleic acid assays.

Electrical label security device

Method of analysis of methylated dna-binding proteins

Provided herein are methods of assaying a methylated DNA-binding protein comprising contacting methylated DNA-binding proteins with labeled oligonucleotides, obtaining sample partitions for oligonucleotides with different methylation states, and quantifying the labeled oligonucleotides in the partitions.

thermoplastic polyurethane compositions and articles and methods thereof

a presente invenção refere-se a composições aprimoradas de poliuretano termoplástico, e aos artigos e métodos relacionados. essas composições incluem poliuretanos termoplásticos alifáticos tendo um teor de segmento duro na faixa de 57 por cento a 80 por cento em peso. as composições de revestimento duro têm uma dureza shore d de ao menos 70 e um resultado do teste de alongamento na ruptura, a 25 graus celsius, de ao menos 150 por cento. estes materiais, quando endurecidos, podem servir funções decorativas e/ou protetoras enquanto apresen-tam um alto grau de alongamento a temperaturas moderadas e alta dureza. The present invention relates to improved thermoplastic polyurethane compositions, and related articles and methods. Such compositions include aliphatic thermoplastic polyurethanes having a hard segment content in the range of 57 percent to 80 percent by weight. the hardcoat compositions have a shore hardness of at least 70 and a rupture elongation test result at 25 degrees celsius of at least 150 percent. These materials, when hardened, can serve decorative and / or protective functions while presenting a high degree of elongation at moderate temperatures and high hardness.

多區域生物水族養殖箱

Herstellung von dotierten bereichen in halbleiter-streifen und mit diesem verfahren hergestellte vorrichtung

Verfahren mit den folgenden Schritten:Ätzen eines Halbleitersubstrats (20), um Gräben (32) herzustellen, wobei ein Teil des Halbleitersubstrats (20) zwischen den Gräben (32) ein Halbleiter-Streifen (30) ist;Abscheiden einer ersten dielektrischen Dosisschicht (36B) auf Seitenwänden des Halbleiter-Streifens (30), wobei die erste dielektrische Dosisschicht (36B) mit einem n-Dotanden dotiert wird;Abscheiden einer zweiten Dosisschicht (36A) über der ersten dielektrischen Dosisschicht (36B), wobei die zweite Dosisschicht (36A) mit einem p-Dotanden dotiert wird;Füllen der übrigen Teile der Gräben (32) mit einem dielektrischen Material (38);Durchführen einer Planarisierung an dem dielektrischen Material (38), wobei die übrigen Teile der dielektrischen ersten Dosisschicht (36B), der zweiten Dosisschicht (36A) und des dielektrischen Materials (38) flache Grabenisolationsbereiche, STI-Bereiche (40, 40A, 40B), bilden; undDurchführen einer Wärmebehandlung (37A-C, 44), um die Dotanden in der ersten dielektrischen Dosisschicht (36B) und in der zweiten Dosisschicht (36A) in den Halbleiter-Streifen (30) einzudiffundieren.

For a specific area of ​​the power storage system

Method of producing outrigger type phase shifting mask

Method of defining pattern

Semiconductor structure

A semiconductor structure is provided. The semiconductor structure includes a gate structure, a source/drain structure, a barrier layer, and a glue layer. The gate structure is over a fin structure. The source/drain structure is in the fin structure and adjacent to the gate structure. The barrier layer is over the source/drain structure. The glue layer is adjacent to the barrier layer. The glue layer has an extending portion in direct contact with the gate structure.

具有低熱阻之熱油脂

本發明係關於一種導熱油脂，其包括載劑油、至少一種分散劑及導熱粒子。導熱粒子之D50(體積平均)粒度不大於約11微米，且以該導熱油脂中導熱粒子之總體積計，該導熱油脂中之該等導熱粒子含有小於3體積%之粒度為0.7微米或小於0.7微米的粒子。

Energy-storing system used in the specific region

Isolationsgebiete zum isolieren von transistoren und die verfahren zum bilden davon

Ein Verfahren umfasst Ätzen eines Gate-Stapels in einem Wafer, um einen Graben zu bilden, Abscheiden einer Siliziumnitridauskleidung, die sich in den Graben erstreckt, und Abscheiden einer Siliziumoxidschicht. Der Prozess zum Abscheiden der Siliziumoxidschicht umfasst Durchführen eines Behandlungsprozesses an dem Wafer unter Verwendung eines Prozessgases, das Stickstoff und Wasserstoff enthält, und Durchführen eines Tränkprozesses an dem Wafer unter Verwendung eines Siliziumvorprodukts.

Entrance machine image/video transmission system

依據使用者之生理狀態改變提示圖示之系統、裝置及其方法

一種依據使用者之生理狀態改變提示圖示之系統、裝置及其方法，其在偵測出生理狀態資料後，分析生理狀態資料來產生分析結果，並顯示對應分析結果的提示圖示，可以在測量生理狀態後快速獲得生理狀態分析結果，並達成提供使用者透過電腦顯示的提示圖示得知自身生理狀態的技術功效。

Individualized network service system

Crown-type capacitor and its manufacturing method

Method, device and system for intelligent right data search management as well as the storage medium storing and executing computer program of this method

依據指定不同辭典優先順序之全文翻譯系統及其方法

一種依據指定不同辭典優先順序之全文翻譯系統及其方法，其透過依據專業辭典之預定順序，依序由專業辭典中匹配出與文件內容中之各個字詞相符之專業字詞，藉以得到專業字詞翻譯清單，並由常用辭典中匹配出與文件內容中不存在於專業字詞翻譯清單中之字詞相符的常用字詞，藉以得到常用字詞翻譯清單，而後依據專業字詞翻譯清單與常用字詞翻譯清單配合語意規則，將文件內容翻譯為翻譯文件的技術手段，可以達成提高專業領域文件翻譯效果的技術功效。

Direct type LED light sources

Unicast and broadcast protocol for wireless local area network ranging and direction finding

Disclosed embodiments facilitate wireless channel calibration, including ranging and direction finding, between wirelessly networked devices. In some embodiments. a method on a first station (STA) may comprise: transmitting a first NDPA frame to one or more second stations (STAs), the first NDPA frame comprising a first bit indicating that one or more subsequent frames comprise ranging or angular information; and transmitting, after a Short Interval Frame Space (SIFS) time interval, a second frame. The second frame may be one of: a Null Data Packet az (NDP_az) frame with information about a time of transmission of the NDP_az frame, or a Null Data Packet (NDP) frame, or a Beam Refinement Protocol (BRP) frame. The first NDPA frame may be unicast, multicast, or broadcast.

Virus detection system and method of notifying detection of viruses for use in instant communication systems

Method to form different gate spacer widths

Packing box structure

具事件反饋參數之寵物遊戲系統及方法

一種具事件反饋參數之寵物遊戲系統及方法，用以解決先前技術無法提供使用者與寵物遊戲中的寵物豐富的互動關係，造成使用者與寵物互動性不高的問題，其透過在寵物遊戲中讓寵物因使用者輸入事件反饋相對應的行為參數或使用者沒有進行操作時反饋的閒置參數，經過累計後當判斷累計參數高於或低於標準值時，顯示累計參數並將寵物顯示更新相對應的圖像與訊息的手段，以達成提高使用者與寵物遊戲中的寵物互動性與豐富性，讓使用者更樂於參與寵物遊戲的技術功效。

網站使用者身分認證系統與方法

Unicast and broadcast protocol for wireless local area network ranging and direction finding

Disclosed embodiments facilitate wireless channel calibration, ranging, and direction finding, between networked devices. A method on a first station (STA) may comprise: broadcasting, at a first time, a first NDPA frame to a plurality of second STAs. The first NDPA frame may include a first bit indicating that one or more subsequent frames comprise ranging or angular information. After a Short Interval Frame Space (SIFS) time interval from the first time, a second frame may be broadcast. The second frame may be a Null Data Packet (NDP) frame. In response, a plurality of Compressed Beamforming (CBF) frames may be received at the first STA where each CBF frame may be received from a distinct corresponding second STA, and may include Channel Feedback Information field with information pertaining to communication channel between the first STA and the corresponding second STA. The communications may be encoded using Orthogonal Frequency Division Multiple Access.

Household electrical appliance control system

顯示來電建議之系統及其方法

一種顯示來電建議之系統及其方法，其透過計算發話方等待使用者接聽之響鈴時間長度後，依據響鈴時間長度以及發話方電話是否包含於聯絡人電話中之判斷結果產生建議訊息的技術手段，可以判斷來電的重要程度，並達成提供使用者來電重要程度之建議的技術功效。