Verfahren und Struktur für eine Halbleitervorrichtung mit einer Gatespacer-Schutzschicht

Ein Verfahren zum Ausbilden einer Halbleitervorrichtung umfasst ein Bereitstellen einer Vorstufe. Die Vorstufe umfasst ein Substrat, einen Gatestapel über dem Substrat, eine erste dielektrische Schicht über dem Gatestapel, einen Gatespacer auf Seitenwänden des Gatestapels und auf Seitenwänden der ersten dielektrischen Schicht, und Source- und Drainkontakte (S/D-Kontakte) auf gegenüberliegenden Seiten des Gatestapels. Das Verfahren umfasst ferner ein Aussparen des Gatespacers, um die Seitenwände der ersten dielektrischen Schicht zumindest teilweise freizulegen, aber nicht die Seitenwände des Gatestapels freizulegen. Das Verfahren umfasst ferner ein Ausbilden einer Spacerschutzschicht über dem Gatespacer, der ersten dielektrischen Schicht und den S/D-Kontakten.

Method for forming semiconductor structure

A method for forming a semiconductor structure is provided. A substrate including a metal portion and a low-k dielectric portion formed thereon is provided. The metal portion adjoins the low-k dielectric portion. A SAM solution is prepared. The SAM solution includes at least one blocking compound and a multi-solvent system. The multi-solvent system includes an alcohol and an ester. The SAM solution is applied over surfaces of the metal portion and the low-k dielectric portion. The substrate is heated to remove the multi-solvent system of the SAM solution to form a blocking layer on one of the metal portion and the low-k dielectric portion. A material layer is selectively deposited on the other one of the metal portion and the low-k dielectric portion using the blocking layer as a stencil. The blocking layer is removed from the substrate.

Halbleitervorrichtung-Metallisierungssysteme und -verfahren

Halbleitervorrichtung-Metallisierungssysteme und -verfahren werden offenbart. Bei manchen Ausführungen weist ein Metallisierungssystem für Halbleitervorrichtungen ein Hauptgerät und mehrere nahe dem Hauptgerät angeordnete Module auf. Eines der mehreren Module umfasst ein physikalische-Dampfabscheidung (PVD) Modul und eines der mehreren Module umfasst ein Ultraviolettlicht (UV) Aushärtemodul.

Semiconductor device and manufacturing method thereof

A layer of an interconnect structure is formed over a substrate. The layer contains an interlayer dielectric (ILD) material and a metal line disposed in the ILD. A first etching stop layer is formed on the ILD but not on the metal line. The first etching stop layer is formed through a selective atomic layer deposition (ALD) process. A second etching stop layer is formed over the first etching stop layer. A high etching selectivity exists between the first and second etching stop layers. A via is formed to be at least partially aligned with, and electrically coupled to, the metal line. The first etching stop layer prevents the ILD from being etched through during the formation of the via.

Porogen Bonded Gap Filling Material in Semiconductor Manufacturing

A method for semiconductor manufacturing includes receiving a device that includes a substrate and a first layer disposed over the substrate, wherein the first layer includes a trench. The method further includes applying a first material over the first layer and filling in the trench, wherein the first material contains a matrix and a porogen that is chemically bonded with the matrix. The method further includes curing the first material to form a porous material layer. The porous material layer has a first portion and a second portion. The first portion is disposed in the trench. The second portion is disposed over the first layer. The first and second portions contain substantially the same percentage of each of Si, O, and C. The first and second portions contain substantially the same level of porosity.

Verbindungsstruktur und Verfahren zum Ausbilden derselben

Es sind eine Verbindungsstruktur und ein Verfahren zum Ausbilden einer Verbindungsstruktur offenbart. Die Verbindungsstruktur umfasst eine low-k-(LK)-dielektrische Schicht über einem Substrat; eine erste leitende Einrichtung und eine zweite leitende Einrichtung in der LK-dielektrischen Schicht; einen ersten Abstandhalter entlang einer Seitenwand der ersten leitenden Einrichtung; einen zweiten Abstandhalter entlang einer zweiten Seitenwand der zweiten leitenden Einrichtung, wobei die zweite Seitenwand der zweiten leitenden Einrichtung der ersten Seitenwand der ersten leitenden Einrichtung gegenüberliegt; eine Luftspalte zwischen dem ersten Abstandhalter und dem zweiten Abstandhalter; und eine dritte leitende Einrichtung über der ersten leitenden Einrichtung, wobei die dritte leitende Einrichtung mit der ersten leitenden Einrichtung verbunden ist.

Semiconductor device structure

A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first conductive structure over the substrate. The semiconductor device structure includes a first dielectric layer over the substrate and the first conductive structure. The semiconductor device structure includes a second conductive structure over the first conductive structure and extending into the first dielectric layer. The second conductive structure is electrically connected to the first conductive structure. The semiconductor device structure includes a cover layer between the second conductive structure and the first dielectric layer. The cover layer surrounds the second conductive structure, the second conductive structure passes through the cover layer and is partially between the cover layer and the first conductive structure, and the cover layer includes a metal oxide.

Semiconductor device having a porous low-k structure

The present disclosure involves forming a porous low-k dielectric structure. A plurality of conductive elements is formed over the substrate. The conductive elements are separated from one another by a plurality of openings. A barrier layer is formed over the conductive elements. The barrier layer is formed to cover sidewalls of the openings. A treatment process is performed to the barrier layer. The barrier layer becomes hydrophilic after the treatment process is performed. A dielectric material is formed over the barrier layer after the treatment process has been performed. The dielectric material fills the openings and contains a plurality of porogens.

Method of Fabrication Polymer Waveguide

A method of fabricating a waveguide device is disclosed. The method includes providing a substrate having an elector-interconnection region and a waveguide region and forming a patterned dielectric layer and a patterned redistribution layer (RDL) over the substrate in the electro-interconnection region. The method also includes bonding the patterned RDL to a vertical-cavity surface-emitting laser (VCSEL) through a bonding stack. A reflecting-mirror trench is formed in the substrate in the waveguide region, and a reflecting layer is formed over a reflecting-mirror region inside the waveguide region. The method further includes forming and patterning a bottom cladding layer in a wave-tunnel region inside the waveguide region and forming and patterning a core layer and a top cladding layer in the waveguide region.

Semiconductor integrated circuit and fabricating the same

A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a precursor. A decomposable polymer layer (DPL) is deposited between the conductive features of the precursor. The DPL is annealed to form an ordered periodic pattern of different types of polymer nanostructures. One type of polymer nanostructure is decomposed by a first selectively to form a trench. The trench is filled by a dielectric layer to form a dielectric block. The remaining types of polymer nanostructures are decomposed by a second selectively etching to form nano-air-gaps.

Interconnect with flexible dielectric layer

An integrated circuit device has a dual damascene structure including a lower via portion and an upper line portion. The lower via portion is formed in a polyimide layer, and the upper line portion is formed in an inter-metal dielectric (IMD) layer formed of USG or polyimide. A passivation layer is formed on the IMD layer, and a bond pad is formed overlying the passivation layer to electrically connect the upper line portion.

Verfahren und Struktur für eine Halbleitervorrichtung mit einer Gatespacer-Schutzschicht

Verfahren zum Ausbilden einer Halbleitervorrichtung, wobei das Verfahren umfasst: Bereitstellen einer Vorstufe, die umfasst ein Substrat, einen Gatestapel über dem Substrat, eine erste dielektrische Schicht über dem Gatestapel, einen Gatespacer auf Seitenwänden des Gatestapels und auf Seitenwänden der ersten dielektrischen Schicht, und Source- und Drainkontakte (S/D-Kontakte) auf gegenüberliegenden Seiten des Gatestapels, Aussparen des Gatespacers, um die Seitenwände der ersten dielektrischen Schicht zumindest teilweise freizulegen, aber nicht die Seitenwände des Gatestapels freizulegen, und Ausbilden einer Spacerschutzschicht über dem ausgesparten Gatespacer, der ersten dielektrischen Schicht und den S/D-Kontakten.

System and Method of Forming a Porous Low-K Structure

The present disclosure involves forming a porous low-k dielectric structure. A plurality of conductive elements is formed over the substrate. The conductive elements are separated from one another by a plurality of openings. A barrier layer is formed over the conductive elements. The barrier layer is formed to cover sidewalls of the openings. A treatment process is performed to the barrier layer. The barrier layer becomes hydrophilic after the treatment process is performed. A dielectric material is formed over the barrier layer after the treatment process has been performed. The dielectric material fills the openings and contains a plurality of porogens.

Novel Copper Etch Scheme for Copper Interconnect Structure

The present disclosure is directed to a method of manufacturing an interconnect structure in which a low-k dielectric layer is formed over a semiconductor substrate followed by formation of a copper or copper alloy layer over the low-k dielectric layer. The copper or copper alloy layer is patterned and etched to form a copper body having recesses, which are then filled with a low-k dielectric material. The method allows for formation of a damascene structures without encountering the various problems presented by non-planar features and by porus low-K dielectric damage. 1. A method for forming an interconnect structure , comprising:providing a semiconductor substrate having a conductive region at a surface of the substrate;forming a layer of a low-k dielectric material over the substrate and covering the conductive region;forming a single, continuous metal layer of copper or copper alloy overlying the low-k dielectric layer;patterning the single, continuous copper or copper alloy metal layer to define a first feature having a single, continuous copper or copper alloy body with first recesses about opposing sidewalls of the body;patterning a portion of the first feature copper or copper alloy body to define a second feature having second recesses in an upper portion of the single, continuous copper or copper alloy body and the first feature in a lower portion of the single, continuous copper or copper alloy body.2. The method of claim 1 , wherein the copper or copper alloy body comprises a lower region comprising a trench and an upper region comprising a via.3. (canceled)4. A method for forming an interconnect structure claim 1 , comprising:providing a semiconductor substrate having a conductive region at a surface of the substrate;forming a layer of a low-k dielectric material over the substrate and covering the conductive region;depositing a metal layer of copper or copper alloy overlying the dielectric layer;forming a barrier layer between the low-k dielectric ...

Adhesion promoter apparatus and method

A method comprises forming a plateau region and a trench region over a substrate, wherein the trench region comprises a slope and a flat bottom, depositing a reflecting layer over the flat bottom and a portion of the slope, depositing a first adhesion promoter layer over the reflecting layer, applying a first curing process to the first adhesion promoter layer, wherein, after the first curing process finishes, the reflecting layer and the first adhesion promoter layer form a first bonding interface, depositing a bottom cladding layer deposited over the first adhesion promoter layer, applying a second curing process to the bottom cladding layer to form a second bonding interface layer, depositing a core layer over the bottom cladding layer and depositing a top cladding layer over the core layer.

Verbindungsstruktur und Verfahren zum Ausbilden derselben

Verbindungsstruktur (100), die Folgendes umfasst:eine low-k-(LK)-dielektrische Schicht (140) über einem Substrat (110);eine erste leitende Einrichtung (122) und eine zweite leitende Einrichtung (124) in der LK-dielektrischen Schicht (140);einen ersten Abstandhalter (132) entlang einer ersten Seitenwand der ersten leitenden Einrichtung (122), wobei der erste Abstandhalter eine im Wesentlichen rechteckige Form hat;einen zweiten Abstandhalter (134) entlang einer zweiten Seitenwand der zweiten leitenden Einrichtung(124), wobei die zweite Seitenwand der zweiten leitenden Einrichtung der ersten Seitenwand der ersten leitenden Einrichtung gegenüberliegt und wobei der zweite Abstandhalter eine im Wesentlichen rechteckige Form hat;ein Luftspalt (150) zwischen dem ersten Abstandhalter und dem zweiten Abstandhalter; undeine dritte leitende Einrichtung (160) über der ersten leitenden Einrichtung, wobei die dritte leitende Einrichtung mit der ersten leitenden Einrichtung verbunden ist, wobei ein Seitenverhältnis ...

Schemes for Forming Barrier Layers for Copper in Interconnect Structures

A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.

Forming interlayer dielectric material by spin-on metal oxide deposition

A plurality of high-k metal gate (HKMG) structures is formed over a substrate. The (HKMG) structures are separated by a plurality of gaps. The HKMG structures each include a first dielectric layer at an upper surface of the HKMG structure. The gaps are filled with a first conductive material. A portion of the first conductive material is removed in each of the gaps through an etching-back process. A metal oxide layer is formed using a spin-on deposition process. The metal oxide layer is formed over the (HKMG) structures and over the first conductive material. A second dielectric layer is formed over the metal oxide layer. An opening is etched in the second dielectric layer. The opening is etched through the second dielectric layer and through the metal oxide layer. The opening is filled with a second conductive material.

Structure and method for interconnection with self-alignment

The present disclosure provides a method of forming an integrated circuit structure. The method includes depositing a first metal layer on a semiconductor substrate; forming a hard mask on the first metal layer; patterning the first metal layer to form first metal features using the hard mask as an etch mask; depositing a dielectric layer of a first dielectric material on the first metal features and in gaps among the first metal features; performing a chemical mechanical polishing (CMP) process to both the dielectric layer and the hard mask; removing the hard mask, thereby having portions of the dielectric layer extruded above the metal features; forming an inter-layer dielectric (ILD) layer of the second dielectric material different from the first dielectric material; and patterning the ILD layer to form openings that expose the first metal features and are constrained to be self-aligned with the first metal features by the extruded portions of the first dielectric layer.

Semiconductor Structure and Method Making the Same

The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.

Etchant and Etching Process for Substrate of a Semiconductor Device

A system and method for manufacturing semiconductor devices is provided. An embodiment comprises using an etchant to remove a portion of a substrate to form an opening with a 45° angle with a major surface of the substrate. The etchant comprises a base, a surfactant, and an oxidant. The oxidant may be hydrogen peroxide.

Semiconductor devices and methods for manufacturing the same

Methods for Fabricating a Low-Resistance Interconnect

Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a first metal feature in a dielectric layer and a capping layer over the first metal feature, selectively depositing a blocking layer over the capping layer, depositing an etch stop layer (ESL) over the workpiece, removing the blocking layer, and depositing a second metal feature over the workpiece such that the first metal feature is electrically coupled to the second metal feature. The blocking layer prevents the ESL from being deposited over the capping layer.

Graphene-Assisted Low-Resistance Interconnect Structures and Methods of Formation Thereof

A semiconductor structure is provided. The semiconductor structure comprises a first conductive feature embedded within a first dielectric layer, a via disposed over the first conductive feature, a second conductive feature disposed over the via, and a graphene layer disposed over at least a portion of the first conductive feature. The via electrically couples the first conductive feature to the second conductive feature. 1. A semiconductor structure comprising:a first conductive feature embedded within a first dielectric layer;a via disposed over the first conductive feature;a second conductive feature disposed over the via, wherein the via electrically couples the first conductive feature to the second conductive feature; anda graphene layer disposed over at least a portion of the first conductive feature.2. The semiconductor structure of claim 1 , further comprising:a third conductive feature embedded within the first dielectric layer, anda second dielectric layer, wherein:a top surface of the third conductive feature is substantially co-planar with a top surface of the first conductive feature; andthe third conductive feature is separated from the first conductive feature by the second dielectric layer.3. The semiconductor structure of claim 2 , further comprising:a third dielectric layer disposed over a portion of the first conductive feature and at least a portion of the third conductive feature, wherein the second dielectric layer is disposed between the first dielectric layer and the third dielectric layer.4. The semiconductor structure of claim 3 , wherein the third conductive feature is separated from the via by at least a portion of the second dielectric layer.5. The semiconductor structure of claim 1 , wherein at least a portion of the graphene layer interposes between the via and the first conductive feature.6. The semiconductor structure of claim 1 , further comprising a capping layer disposed over a portion of the first conductive feature and beneath ...

SEMICONDUCTOR STRUCTURE AND METHOD MAKING THE SAME

The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer. 1. A semiconductor device , comprising:a first conductive element;a first dielectric layer disposed over the first conductive element, wherein the first dielectric layer has a porous structure;a second dielectric layer disposed over the first dielectric layer, wherein the first dielectric layer and the second dielectric layer have different material compositions; anda second conductive element disposed in the second dielectric layer and over the first dielectric layer.2. The semiconductor device of claim 1 , further comprising: a cap layer disposed between the first conductive element and the first dielectric layer.3. The semiconductor device of claim 2 , wherein the cap layer and the first conductive element have substantially similar lateral dimensions.4. The semiconductor device of claim 1 , further comprising: an etch stop layer (ESL) disposed over the first dielectric layer.5. The semiconductor device of claim 4 , wherein an etching selectivity exists between the ESL and the first dielectric layer.6. The semiconductor device of claim 1 , wherein the second conductive element is at least partially aligned with the first conductive element.7. The semiconductor device of claim 1 , wherein the first dielectric layer contains aluminum claim 1 , oxygen claim 1 , and nitrogen.8. The semiconductor device of claim 7 , wherein an aluminum composition of the first dielectric layer is in a range from about 5 wt % to about 20 wt %.9. The semiconductor device of claim 7 , wherein an ...

FORMING INTERLAYER DIELECTRIC MATERIAL BY SPIN-ON METAL OXIDE DEPOSITION

A plurality of high-k metal gate (HKMG) structures is formed over a substrate. The (HKMG) structures are separated by a plurality of gaps. The HKMG structures each include a first dielectric layer at an upper surface of the HKMG structure. The gaps are filled with a first conductive material. A portion of the first conductive material is removed in each of the gaps through an etching-back process. A metal oxide layer is formed using a spin-on deposition process. The metal oxide layer is formed over the (HKMG) structures and over the first conductive material. A second dielectric layer is formed over the metal oxide layer. An opening is etched in the second dielectric layer. The opening is etched through the second dielectric layer and through the metal oxide layer. The opening is filled with a second conductive material. 1. A method of fabricating a semiconductor device , comprising:forming a plurality of gate structures over a substrate, the gate structures being separated by a plurality of gaps;filling the gaps with a conductive material;forming a metal oxide layer over the gate structures and over the conductive material filling the gaps;forming a dielectric layer over the metal oxide layer; andforming one or more conductive contacts that extend through the dielectric layer and through the metal oxide layer.2. The method of claim 1 , wherein the forming of the metal oxide layer is performed using a spin-on deposition process.3. The method of claim 2 , wherein the spin-on deposition process is free of using an oxygen-containing gas.4. The method of claim 1 , wherein:the forming of the one or more conductive contacts is performed via one or more etching processes; andat least one of the etching processes is configured to have an etching selectivity between the metal oxide layer and a silicon-containing dielectric material.5. The method of claim 1 , further comprising: after the filling but before the forming of the metal oxide layer claim 1 , etching back a portion ...

System und Verfahren zur Dunkelfeldinspektion

Die vorliegende Offenbarung sieht ein Verfahren zur Herstellung einer Halbleiterstruktur vor. Das Verfahren umfasst das Bereitstellen eines Substrats und einer strukturierten Schicht, die auf dem Substrat ausgebildet ist, wobei eine oder mehrere Überlagerungsmarkierungen auf der strukturierten Schicht ausgebildet sind; das Ausführen einer Überlagerungsinspektion vor dem Ausbilden eines Films mittels eines Hellfeld-(BF)-Inspektionswerkzeugs, um Daten vor dem Ausbilden des Films über die eine oder die mehreren Überlagerungsmarkierungen auf der strukturierten Schicht zu erhalten; Ausbilden einer oder mehrerer Schichten auf der strukturierten Schicht; Ausführen einer Überlagerungsinspektion nach dem Ausbilden des Films mittels eines Dunkelfeld-(DF)-Inspektionswerkzeugs, um Daten nach dem Ausbilden des Films über die eine oder die mehreren Überlagerungsmarkierungen zu erhalten, die unter der einen oder den mehreren Schichten liegen; und das Ermitteln, ob die Daten vor dem Ausbilden des Films ...

Semiconductor device and method for making the same

A method for semiconductor manufacturing includes receiving a device that includes a substrate and a first layer disposed over the substrate, wherein the first layer includes a trench. The method further includes applying a first material over the first layer and filling in the trench, wherein the first material contains a matrix and a porogen that is chemically bonded with the matrix. The method further includes curing the first material to form a porous material layer. The porous material layer has a first portion and a second portion. The first portion is disposed in the trench. The second portion is disposed over the first layer. The first and second portions contain substantially the same percentage of each of Si, O, and C. The first and second portions contain substantially the same level of porosity.

LOW DIELECTRIC CONSTANT MATERIAL

The present disclosure provides a dielectric material including a low dielectric constant material and an additive. The additive includes a compound having a Si—X—Si bridge, where X is a number of carbon atoms between 1 and 8. The additive may include terminal Si—CHgroups. The dielectric material including the additive may be used as an inter-layer dielectric (ILD) layer of a semiconductor device. The dielectric material including the additive may be formed using a CVD or sol-gel process. One example of the additive is bis(triethoxysilyl)ethene. 1. A material , comprising:a low dielectric constant material; andan additive, wherein the additive includes a compound having a Si—X—Si bridge, wherein X is a number of carbon atoms between 1 and 8.2. The material of claim 1 , wherein the material has a carbon content of greater than approximately 16% atomic concentration.3. The material of claim 1 , wherein X is two.4. The material of claim 1 , wherein the low dielectric material is a porous dielectric.6. The material of claim 5 , wherein at least one of R1 to R6 is a methyl group.7. The material of claim 1 , wherein the dielectric constant is between approximately 1.8 and 2.6.8. The material of claim 1 , wherein the compound includes at least one terminal Si—CHgroup.9. The material of claim 1 , wherein the low dielectric constant material has a first dielectric constant claim 1 , and the low dielectric constant combined with the additive has a second dielectric constant claim 1 , and wherein the second dielectric constant is lower than the first dielectric constant.10. The material of claim 1 , wherein the low dielectric constant material has a first carbon content amount claim 1 , and the low dielectric constant combined with the additive has a second carbon content amount claim 1 , and wherein the second carbon content amount is at least 10% atomic concentration greater than the first carbon content amount.11. The material of claim 1 , wherein the compound is selected ...

Self-Alignment Due to Wettability Difference of an Interface

Some embodiments relate to a method of processing a workpiece. The workpiece includes a first surface region having a first wettability coefficient, and a second surface region having a second wettability coefficient that differs from the first wettability coefficient. A liquid, which corresponds to an optical structure, is dispensed on the first and second surface regions of the workpiece, wherein the liquid self-aligns to the second surface region due to the difference between the first and second wettability coefficients. The self-aligned liquid is hardened to form the optical structure. 1. An apparatus , comprising:a substrate including a first surface region which separates neighboring second surface regions from one another, wherein the first surface region has a first wettability coefficient and the second surface regions have a second wettability coefficient; andan optical structure which is arranged on the second surface regions but which does not cover the first surface region, the optical structure having sidewalls that are aligned to an interface between the first and second surface regions.2. The apparatus of claim 1 , wherein the first surface region corresponds to an upper surface of the substrate and wherein the second surface regions comprise a landing pad surface that is elevated or recessed relative to the upper substrate surface.3. The apparatus of claim 2 , wherein the substrate is a glass substrate.4. The apparatus of claim 3 , wherein the landing pad surface comprises at least one of: spin-on-glass or a sol-gel polymer.5. The apparatus of claim 1 , wherein the neighboring second surface regions have a ball lens and a waveguide claim 1 , respectively claim 1 , arranged thereon claim 1 , and wherein the neighboring second surface regions are spaced apart by the first surface region which has a length that is approximately equal to a focal length of the ball lens.6. The apparatus of claim 5 , wherein the interface between the first and second ...

Method and apparatus for forming self-aligned via with selectively deposited etching stop layer

A first conductive element is disposed in a first dielectric layer. An etching stop layer is disposed on the first dielectric layer but not on the first conductive element. A first metal capping layer segment is disposed on the first conductive element but not on the first dielectric layer. The etching stop layer has a greater thickness than the first metal capping layer segment. A first segment of a second conductive element is disposed on the first metal capping layer segment. A second segment of the second conductive element is disposed over the first segment of the second conductive element and partially over the etching stop layer. A third conductive element is disposed over the second conductive element.

Schemes for forming barrier layers for copper in interconnect structures

A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.

Semiconductor structure

Some embodiments relate to a semiconductor structure including an inter-level dielectric (ILD) layer overlying a substrate. A conductive via is disposed within the ILD layer. A plurality of conductive wires overlie the ILD layer. The plurality of conductive wires includes a first conductive wire laterally offset a second conductive wire. A dielectric structure is disposed laterally between the first and second conductive wires. The dielectric structure includes a first dielectric liner, a dielectric layer, and an air-gap. The air-gap is disposed between an upper surface of the first dielectric liner and a lower surface of the dielectric layer. A dielectric capping layer is disposed along an upper surface of the dielectric structure. The dielectric capping layer continuously extends between opposing sidewalls of the dielectric structure and is laterally offset from the plurality of conductive wires.

Semiconductor device structure

A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first conductive structure over the substrate. The semiconductor device structure includes a first dielectric layer over the substrate. The first dielectric layer has a first opening exposing the first conductive structure. The semiconductor device structure includes a cover layer covering a first inner wall of the first opening. The cover layer has a second opening exposing the first conductive structure. The cover layer includes a metal oxide. The semiconductor device structure includes a second conductive structure filled in the first opening and surrounded by the cover layer. The second conductive structure is electrically connected to the first conductive structure.

Liner formation in 3DIC structures

An integrated circuit structure includes a semiconductor substrate; a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and a TSV liner in the TSV opening. The TSV liner includes a sidewall portion on a sidewall of the TSV opening and a bottom portion at a bottom of the TSV opening. The bottom portion of the TSV liner has a bottom height greater than a middle thickness of the sidewall portion of the TSV liner.

Semiconductor devices and methods for manufacturing the same

A structure is provided that includes a first conductive component and a first interlayer dielectric (ILD) that surrounds the first conductive component. A self-assembly layer is formed on the first conductive component but not on the first ILD. A first dielectric layer is formed over the first ILD but not over the first conductive component. A second ILD is formed over the first conductive component and over the first ILD. An opening is etched in the second ILD. The opening is at least partially aligned with the first conductive component. The first dielectric layer protects portions of the first ILD located therebelow from being etched. The opening is filled with a conductive material to form a second conductive component in the opening.

Structure and Method for Interconnection with Self-Alignment

The present disclosure provides a method of forming an integrated circuit structure. The method includes depositing a first metal layer on a semiconductor substrate; forming a hard mask on the first metal layer; patterning the first metal layer to form first metal features using the hard mask as an etch mask; depositing a dielectric layer of a first dielectric material on the first metal features and in gaps among the first metal features; performing a chemical mechanical polishing (CMP) process to both the dielectric layer and the hard mask; removing the hard mask, thereby having portions of the dielectric layer extruded above the metal features; forming an inter-layer dielectric (ILD) layer of the second dielectric material different from the first dielectric material; and patterning the ILD layer to form openings that expose the first metal features and are constrained to be self-aligned with the first metal features by the extruded portions of the first dielectric layer. 1. A method of forming an integrated circuit structure , comprising:depositing a first metal layer on a semiconductor substrate;forming a hard mask on the first metal layer;patterning the first metal layer to form first metal features using the hard mask as an etch mask;depositing a dielectric layer of a first dielectric material on the first metal features and in gaps among the first metal features;performing a chemical mechanical polishing (CMP) process to both the dielectric layer and the hard mask;removing the hard mask, thereby having portions of the dielectric layer extruded above the metal features;forming an inter-layer dielectric (ILD) layer of the second dielectric material different from the first dielectric material; andpatterning the ILD layer to form openings that expose the first metal features and are constrained to be self-aligned with the first metal features by the extruded portions of the first dielectric layer.2. The method of claim 1 , further comprising forming second ...

Porogen bonded gap filling material in semiconductor manufacturing

A device includes a substrate; a first layer over the substrate, the first layer containing a metallic material, wherein the first layer includes a trench; and a porous material layer having a first portion and a second portion. The first portion is disposed in the trench. The second portion is disposed on a top surface of the first layer. The first and the second portions contain substantially same percentage of Si, substantially same percentage of O, and substantially same percentage of C.

Lithography using high selectivity spacers for pitch reduction

A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer.

Method for fabricating a semiconductor structure and system for inspecting overlay marks

The present disclosure provides a method for fabricating a semiconductor structure. The method comprises providing a substrate and a patterned layer formed on the substrate, one or more overlay marks being formed on the patterned layer; performing a pre-film-formation overlay inspection using a bright field (BF) inspection tool to receive a pre-film-formation data on the one or more overlay marks on the patterned layer; forming one or more layers on the patterned layer; performing a post-film-formation overlay inspection using a dark field (DF) inspection tool to receive a post-film-formation data on the one or more overlay marks underlying the one or more layers; and determining whether the pre-film-formation data matches the post-film-formation data.

Semiconductor structure and method making the same

The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a first metal wiring layer, an interlayer insulating layer formed over the first metal layer, a second metal wiring structure embedded in the interlayer dielectric layer and connected to the first metal wiring layer, and an etch-stop layer disposed between the first metal wiring and the first interlayer dielectric layer. The etch-stop layer includes one or more sub-layers. The etch-stop layer includes a first sub-layer made of an aluminum-based insulating material, hafnium oxide, zirconium oxide or titanium oxide.

Optical element structure and optical element fabricating process for the same

An optical element structure and a fabricating process for the same are provided. The optical element fabricating process includes providing a substrate forming thereon a protrusion; and forming an over coating layer over the protrusion and the substrate by a deposition scheme to form an optical element.

OPTICAL BENCH ON SUBSTRATE

A method of making an optical bench includes forming a trench in a substrate and wherein the trench has a sloping side, forming a reflector layer over the sloping side, depositing a redistribution layer over the substrate, disposing an under bump metallization (UBM) layer over the redistribution layer, depositing a passivation layer over the redistribution layer and surrounding sidewalls of the UBM layer, and mounting an optical component over an uppermost portion of the substrate, wherein the optical component is electrically connected to a through substrate via (TSV) extending through the substrate. The reflector layer is configured to reflect an electromagnetic wave from the optical component, and wherein the optical component is mounted outside the trench. 1. A method of forming an optical bench , comprising:forming a trench in a substrate, wherein the trench has a sloping side;forming a reflector layer over the sloping side;depositing a redistribution layer over the substrate;disposing an under bump metallization (UBM) layer over the redistribution layer;forming a passivation layer over the redistribution layer and surrounding sidewalls of the UBM layer; andmounting an optical component over an uppermost portion of the substrate, wherein the optical component is electrically connected to a through substrate via (TSV) extending through the substrate, wherein the reflector layer is configured to reflect an electromagnetic wave from the optical component, and wherein the optical component is mounted outside the trench.2. The method of claim 1 , further comprising forming a waveguide inside the trench claim 1 , wherein the waveguide is configured to guide the electromagnetic wave to or from the reflector layer.3. The method of claim 2 , wherein forming the waveguide comprises forming a polymer as an optical path inside the trench.4. The method of claim 2 , wherein forming the waveguide comprises:depositing a bottom cladding layer over a bottom surface of the trench ...

Three-dimensional integrated circuit structure

The preferred embodiments of the present invention provide a three-dimensional (3D) semiconductor structure and a method of forming the same. The 3D semiconductor structure includes a first substrate bonded to a second substrate. The first substrate includes substantially all NMOS devices. The second substrate includes substantially all PMOS devices. The substrates can be bonded face-to-face, face-to-back, or back-to-back. The method includes providing a first substrate and a second substrate, forming a first circuit comprising at least one NMOS device on the first substrate, wherein the first substrate includes substantially no PMOS devices, forming a second circuit comprising at least one PMOS device on the second substrate, wherein the second substrate includes substantially no NMOS devices, and bonding the first and second substrates after forming the first and second circuits.

Light coupling device and methods of forming same

An embodiment is a semiconductor device comprising an optical device over a first substrate, a vertical waveguide on a top surface of the optical device, the vertical waveguide having a first refractive index, and a capping layer over the vertical waveguide, the capping layer configured to be a lens for the vertical waveguide and the capping layer having a second refractive index.

System and Method of Forming a Porous Low-K Structure

The present disclosure involves forming a porous low-k dielectric structure. A plurality of conductive elements is formed over the substrate. The conductive elements are separated from one another by a plurality of openings. A barrier layer is formed over the conductive elements. The barrier layer is formed to cover sidewalls of the openings. A treatment process is performed to the barrier layer. The barrier layer becomes hydrophilic after the treatment process is performed. A dielectric material is formed over the barrier layer after the treatment process has been performed. The dielectric material fills the openings and contains a plurality of porogens.

Copper etch scheme for copper interconnect structure

The present disclosure is directed to a method of manufacturing an interconnect structure in which a low-k dielectric layer is formed over a semiconductor substrate followed by formation of a copper or copper alloy layer over the low-k dielectric layer. The copper or copper alloy layer is patterned and etched to form a copper body having recesses, which are then filled with a low-k dielectric material. The method allows for formation of a damascene structures without encountering the various problems presented by non-planar features and by porus low-K dielectric damage.

High mechanical strength additives for porous ultra low-k material

A semiconductor device and method for making such that provides improved mechanical strength is disclosed. The semiconductor device comprises a semiconductor substrate; an adhesion layer disposed over the semiconductor substrate; and a porous low-k film disposed over the semiconductor substrate, wherein the porous low-k film comprises a porogen and a composite bonding structure including at least one SiOSi bonding group and at least one bridging organic functional group.

Schemes for forming barrier layers for copper in interconnect structures

A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.

Etching apparatus

A system and method of etching a semiconductor device are provided. Etching solution is sampled and analyzed by a monitoring unit to determine a concentration of components within the etching solution, such as an oxidant concentration. Then, based upon such measurement, a makeup amount of the components may be added be a makeup unit to the etching solution to control the concentration of the components within the etching system.

System and method for chemical-mechanical planarization of a metal layer

A method for forming a field-effect transistor with a raised drain structure is disclosed. The method includes depositing a low-k inter-metal layer over a semiconductor substrate, depositing a porogen-containing low-k layer over the low-k inter-metal layer, and etching a space for the via through the low-k inter-metal layer and the porogen-containing low-k layer. The method further includes depositing a metal layer, a portion of the metal layer filling the space for the via, another portion of the metal layer being over the porogen-containing low-layer, removing the portion of the metal layer over the porogen-containing layer by a CMP process, and curing the porogen-containing low-k layer to form a cured low-k layer.

Package Structure and Methods of Forming Same

A semiconductor device, a package structure, and methods of forming the same are disclosed. An embodiment is a semiconductor device comprising a first optical device over a first substrate, a vertical waveguide on a top surface of the first optical device, and a second substrate over the vertical waveguide. The semiconductor device further comprises a lens capping layer on a top surface of the second substrate, wherein the lens capping layer is aligned with the vertical waveguide, and a second optical device over the lens capping layer. 1. A device comprising:a first optical device on a first side of a first substrate;a vertical waveguide on a top surface of the first optical device;a second substrate bonded to the first side of the first substrate, the second substrate being over the vertical waveguide; anda lens capping layer on the second substrate, a portion of the second substrate being directly between the vertical waveguide and the lens capping layer.2. The device of further comprising:a second optical device over the lens capping layer.3. The device of claim 2 , wherein the first optical device comprises a laser diode claim 2 , and wherein the second optical device comprises a photo diode.4. The device of claim 1 , wherein the vertical waveguide comprises a polymer and the lens capping layer comprises a polymer.5. The device of claim 1 , wherein the second substrate is a silicon substrate.6. The device of claim 1 , wherein a top surface of the vertical waveguide is in direct contact with a first side of the second substrate.7. The device of further comprising:a first redistribution layer over the first substrate, the first optical device being over and coupled to the first redistribution layer.8. The device of further comprising:a through substrate via extending through the second substrate, the through substrate via being coupled to the first redistribution layer.9. The device of claim 1 , wherein the second substrate is free from through substrate vias.10. ...

Verfahren und System zur Dunkelfeldinspektion

Verfahren zur Herstellung einer Halbleiterstruktur, das Folgendes umfasst: Bereitstellen eines Substrats (302) und einer strukturierten Schicht (304), die auf dem Substrat (302) ausgebildet ist, wobei eine oder mehrere Überlagerungsmarkierungen (352, 354) auf der strukturierten Schicht (304) ausgebildet sind; Ausführen einer Überlagerungsinspektion vor dem Ausbilden eines Films mittels eines Hellfeld-(BF)-Inspektionswerkzeugs (116) und Erhalten von Daten über die eine oder die mehreren Überlagerungsmarkierungen (352, 354) auf der strukturierten Schicht (304) vor dem Ausbilden des Films; Ausbilden einer oder mehrerer Schichten (306) auf der strukturierten Schicht (304); Ausführen einer Überlagerungsinspektion nach dem Ausbilden des Films mittels eines Dunkelfeld-(DF)-Inspektionswerkzeugs (113) und Erhalten von Daten über die eine oder die mehreren Überlagerungsmarkierungen (352, 354), die unter der einen oder den mehreren Schichten (306) liegen, um nach dem Ausbilden des Films zu ermitteln ...

System and method of forming a porous low-k structure

The present disclosure involves forming a porous low-k dielectric structure. A plurality of conductive elements is formed over the substrate. The conductive elements are separated from one another by a plurality of openings. A barrier layer is formed over the conductive elements. The barrier layer is formed to cover sidewalls of the openings. A treatment process is performed to the barrier layer. The barrier layer becomes hydrophilic after the treatment process is performed. A dielectric material is formed over the barrier layer after the treatment process has been performed. The dielectric material fills the openings and contains a plurality of porogens.

Low-Resistance Interconnect

Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a first metal feature in a dielectric layer and a capping layer over the first metal feature, selectively depositing a blocking layer over the capping layer, depositing an etch stop layer (ESL) over the workpiece, removing the blocking layer, and depositing a second metal feature over the workpiece such that the first metal feature is electrically coupled to the second metal feature. The blocking layer prevents the ESL from being deposited over the capping layer. 1. A semiconductor structure , comprising:a first conductive feature disposed in a first dielectric layer;a conductive capping layer disposed in the first dielectric layer and over the first conductive feature;a dielectric filling layer disposed over the first dielectric layer;a second conductive feature extending alongside the dielectric filling layer and in direct contact with the conductive capping layer; andan encapsulating layer extending continuously along a bottom surface and sidewalls of the dielectric filling layer,wherein the dielectric filling layer is spaced apart from the first dielectric layer by the encapsulating layer.2. The semiconductor structure of claim 1 , wherein the first conductive feature is formed of a first material claim 1 , and the conductive capping layer is formed of a second material different than the first material.3. The semiconductor structure of claim 2 , wherein the second conductive feature is formed of the first material.4. The semiconductor structure of claim 1 , wherein the conductive capping layer comprises copper claim 1 , cobalt claim 1 , ruthenium claim 1 , molybdenum claim 1 , chromium claim 1 , tungsten claim 1 , manganese claim 1 , rhodium claim 1 , iridium claim 1 , nickel claim 1 , palladium claim 1 , platinum claim 1 , silver claim 1 , gold claim 1 , aluminum claim 1 , or a combination thereof.5. The ...

Porogen Bonded Gap Filling Material in Semiconductor Manufacturing

A device includes a substrate; a first layer over the substrate, the first layer containing a plurality of fin features and a trench between two adjacent fin features. The device also includes a porous material layer having a first portion and a second portion. The first portion is disposed in the trench. The second portion is disposed on a top surface of the first layer. The first and the second portions contain substantially same percentage of Si, substantially same percentage of O, and substantially same percentage of C. 1. A device , comprising:a substrate;a first layer over the substrate, the first layer including a plurality of fin features and a trench between two adjacent fin features; anda dielectric material layer having a first portion and a second portion, the first portion disposed in the trench, the second portion disposed on a top surface of the first layer, wherein the first and the second portions contain substantially a same level of porosity.2. The device of claim 1 , wherein the first and the second portions contain substantially same percentage of Si element claim 1 , substantially same percentage of O element claim 1 , substantially same percentage of C element claim 1 , and substantially same percentage of N element.3. The device of claim 2 , wherein a percentage of O element in the first and the second portions is higher than a percentage of C element in the first and the second portions.4. The device of claim 3 , wherein the percentage of O element in the first and the second portions is more than twice of the percentage of C element in the first and the second portions.5. The device of claim 2 , wherein a percentage of Si element in the first and the second portions is higher than a percentage of O element in the first and the second portions.8. The device of claim 7 , wherein the matrix and the polymer are bonded through a Si—O—[CHCHO]bond.9. The device of claim 8 , wherein the matrix includes one or more monomers of tetramethoxysilane ( ...

Package Structure and Methods of Forming Same

A semiconductor device, a package structure, and methods of forming the same are disclosed. An embodiment is a semiconductor device comprising a first optical device over a first substrate, a vertical waveguide on a top surface of the first optical device, and a second substrate over the vertical waveguide. The semiconductor device further comprises a lens capping layer on a top surface of the second substrate, wherein the lens capping layer is aligned with the vertical waveguide, and a second optical device over the lens capping layer. 1. A method comprising:dispensing a polymer waveguide on a first surface of a first optical device;disposing a first substrate over the polymer waveguide;after disposing the first substrate over the polymer waveguide, forming an underfill material on a first surface of the first substrate, the underfill material contacting side surfaces of the first optical device and the polymer waveguide, the underfill material comprising a different material than the polymer waveguide; anddispensing a lens layer on a second surface of the first substrate, the second surface of the first substrate being opposite the first surface, a portion of the first substrate being directly between the polymer waveguide and the lens layer.2. The method of claim 1 , further comprising:attaching the first optical device to a second substrate, wherein the first substrate is bonded to the second substrate after attaching the first optical device to the second substrate; andattaching a second optical device over the second surface of the first substrate.3. The method of claim 1 , wherein the polymer waveguide has a longitudinal axis claim 1 , the longitudinal axis being substantially orthogonal to the first surface of the first substrate.4. The method of claim 1 , wherein the polymer waveguide and the lens layer have a same material composition.5. The method of claim 1 , wherein a surface of the polymer waveguide is in direct contact with the first surface of the ...

INTERCONNECT STRUCTURE AND METHOD FOR FORMING THE SAME

A method for forming an interconnect structure is provided. The method for forming the interconnect structure includes forming a metal line over a substrate, forming a first dielectric layer surrounding the metal line, selectively forming a dielectric block over the first dielectric layer without forming the dielectric block on the metal line, forming a second dielectric layer over the dielectric block and the metal line, etching the second dielectric layer to form a via hole corresponding to the metal line, and filling the via hole with a conductive material. 1. A method for forming an interconnect structure , comprising:forming a metal line over a substrate;forming a first dielectric layer surrounding the metal line;selectively forming a dielectric block over the first dielectric layer without forming the dielectric block on the metal line;forming a second dielectric layer over the dielectric block and the metal line;etching the second dielectric layer to form a via hole corresponding to the metal line; andfilling the via hole with a conductive material.2. The method for forming the interconnect structure as claimed in claim 1 , further comprising:selectively forming a catalyst layer on the first dielectric layer without forming the catalyst layer on the metal line, wherein the dielectric block is selectively formed on the catalyst layer.3. The method for forming the interconnect structure as claimed in claim 2 , wherein the catalyst layer includes an oxide of Al claim 2 , Ti claim 2 , Zr claim 2 , Hf claim 2 , or Y.4. The method for forming the interconnect structure as claimed in claim 2 , wherein selectively forming the dielectric block on the catalyst layer comprises introducing a precursor including alkoxy silanol or aryloxy silanol to the catalyst layer.5. The method for forming the interconnect structure as claimed in claim 1 , further comprising:before forming the second dielectric layer over the dielectric block and the metal line, forming an etching stop ...

Semiconductor Structure and Method Making the Same

The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.

Optical bench on substrate and method for forming the same

An optical bench on substrate includes a substrate and a trench formed inside the substrate and having a sloping side. A reflector layer is formed over the sloping side. An optical component is mounted over the substrate. The reflector layer is configured to reflect an electromagnetic wave to or from the optical component.

Method and apparatus for forming self-aligned via with selectively deposited etching stop layer

A layer of an interconnect structure is formed over a substrate. The layer contains an interlayer dielectric (ILD) material and a metal line disposed in the ILD. A first etching stop layer is formed on the ILD but not on the metal line. The first etching stop layer is formed through a selective atomic layer deposition (ALD) process. A second etching stop layer is formed over the first etching stop layer. A high etching selectivity exists between the first and second etching stop layers. A via is formed to be at least partially aligned with, and electrically coupled to, the metal line. The first etching stop layer prevents the ILD from being etched through during the formation of the via.

VERWENDUNG EINER SELBSTASSEMBLIERUNGSSCHICHT ZUR UNTERSTÜTZUNG DER SELEKTIVEN BILDUNG EINER ÄTZSTOPPSCHICHT

Es wird eine Struktur bereitgestellt, die eine erste leitende Komponente und ein erstes Zwischenschichtdielektrikum (ILD) umfasst, das die erste leitende Komponente umgibt. Auf der ersten leitenden Komponente, aber nicht auf dem ersten ILD ist eine Selbstassemblierungsschicht gebildet. Über dem ersten ILD, aber nicht über der ersten leitenden Komponente ist eine erste Dielektrikumschicht gebildet. Über der ersten leitenden Komponente und über dem ersten ILD ist ein zweites ILD gebildet. In das zweite ILD ist eine Öffnung geätzt. Die Öffnung ist zumindest teilweise an der ersten leitenden Komponente ausgerichtet. Die erste Dielektrikumschicht schützt Abschnitte des darunter befindlichen ersten ILD vor dem Ätzen. Die Öffnung ist mit einem leitenden Material gefüllt, um in der Öffnung eine zweite leitende Komponente zu bilden.

Package structure and methods of forming same

A semiconductor device, a package structure, and methods of forming the same are disclosed. An embodiment is a semiconductor device comprising a first optical device over a first substrate, a vertical waveguide on a top surface of the first optical device, and a second substrate over the vertical waveguide. The semiconductor device further comprises a lens capping layer on a top surface of the second substrate, wherein the lens capping layer is aligned with the vertical waveguide, and a second optical device over the lens capping layer.

Lithography using high selectivity spacers for pitch reduction

A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer.

Optical bench on substrate

An optical bench on substrate includes a substrate and a trench formed inside the substrate and having a sloping side. A reflector layer is formed over the sloping side. An optical component is mounted over the substrate. The reflector layer is configured to reflect an electromagnetic wave to or from the optical component.

Semiconductor device structure and method for forming the same

A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first conductive structure over the substrate. The semiconductor device structure includes a first dielectric layer over the substrate. The first dielectric layer has a first opening exposing the first conductive structure. The semiconductor device structure includes a cover layer covering a first inner wall of the first opening. The cover layer has a second opening exposing the first conductive structure. The cover layer includes a metal oxide. The semiconductor device structure includes a second conductive structure filled in the first opening and surrounded by the cover layer. The second conductive structure is electrically connected to the first conductive structure.

METALLOXID-ZUSAMMENSETZUNG ALS ÄTZSTOPPSCHICHT

Ein Verfahren umfasst die folgenden Schritte: Bereitstellen einer dielektrischen Schicht; Herstellen einer Metallleitung in der dielektrischen Schicht; Herstellen einer Ätzstoppschicht auf der Metallleitung, wobei die Ätzstoppschicht ein Metallatom aufweist, das mit einer Hydroxylgruppe verbunden ist; Durchführen eines Behandlungsprozesses an der Ätzstoppschicht, um Wasserstoff in der Hydroxylgruppe durch ein von Wasserstoff verschiedenes Element zu ersetzen; partielles Ätzen der Ätzstoppschicht, um die Metallleitung freizulegen; und Herstellen eines leitfähigen Strukturelements über der Ätzstoppschicht und in physischem Kontakt mit der Metallleitung.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a first metal wiring layer, an interlayer insulating layer formed over the first metal layer, a second metal wiring structure embedded in the interlayer dielectric layer and connected to the first metal wiring layer, and an etch-stop layer disposed between the first metal wiring and the first interlayer dielectric layer. The etch-stop layer includes one or more sub-layers. The etch-stop layer includes a first sub-layer made of an aluminum-based insulating material, hafnium oxide, zirconium oxide or titanium oxide.

Etchant and etching process

A system and method for manufacturing semiconductor devices is provided. An embodiment comprises using an etchant to remove a portion of a substrate to form an opening with a 45° angle with a major surface of the substrate. The etchant comprises a base, a surfactant, and an oxidant. The oxidant may be hydrogen peroxide.

METAL CAPPING LAYER AND METHODS THEREOF

A method and structure for forming an enhanced metal capping layer includes forming a portion of a multi-level metal interconnect network over a substrate. In some embodiments, the portion of the multi-level metal interconnect network includes a plurality of metal regions. In some cases, a dielectric region is disposed between each of the plurality of metal regions. By way of example, a metal capping layer may be deposited over each of the plurality of metal regions. Thereafter, in some embodiments, a self-assembled monolayer (SAM) may be deposited, where the SAM forms selectively on the metal capping layer, while the dielectric region is substantially free of the SAM. In various examples, after selectively forming the SAM on the metal capping layer, a thermal process may be performed, where the SAM prevents diffusion of the metal capping layer during the thermal process. 1. A method of fabricating a semiconductor device , comprising:forming a metal layer over a substrate;depositing a capping layer over the metal layer;selectively forming a self-assembled monolayer (SAM) over the capping layer; andafter selectively forming the SAM over the capping layer, performing a thermal process to the semiconductor device, wherein the SAM prevents diffusion of the capping layer during the thermal process.2. The method of claim 1 , wherein the metal layer is part of a multi-level metal interconnect network.3. The method of claim 2 , wherein the metal layer includes a metal line or a metal via of the multi-level metal interconnect network.4. The method of claim 1 , further comprising:forming the metal layer within a low-K dielectric layer.5. The method of claim 1 , further comprising:prior to forming the metal layer, forming a barrier layer over the substrate; andforming the metal layer over the barrier layer.6. The method of claim 1 , wherein the capping layer includes a Co layer.7. The method of claim 1 , wherein the SAM is selectively formed over the capping layer by a vapor ...

Waveguide structure and method for fabricating the same

Embodiments of forming a waveguide structure are provided. The waveguide structure includes a substrate, and the substrate has an interconnection region and a waveguide region. The waveguide structure also includes a trench formed in the substrate, and the trench has a sloping sidewall surface and a substantially flat bottom. The waveguide structure further includes a bottom cladding layer formed on the substrate, and the bottom cladding layer extends from the interconnection region to the waveguide region, and the bottom cladding layer acts as an insulating layer in the interconnection region. The waveguide structure further includes a metal layer formed on the bottom cladding layer on the sloping sidewall surface.

Low dielectric constant material

The present disclosure provides a dielectric material including a low dielectric constant material and an additive. The additive includes a compound having a SiXSi bridge, where X is a number of carbon atoms between 1 and 8. The additive may include terminal SiCH3 groups. The dielectric material including the additive may be used as an inter-layer dielectric (ILD) layer of a semiconductor device. The dielectric material including the additive may be formed using a CVD or sol-gel process. One example of the additive is bis(triethoxysilyl)ethene.

Interconnect Structure That Avoids Insulating Layer Damage and Methods of Making the Same

A method for forming an interconnect structure includes forming an insulating layer on a substrate. A damascene opening is formed through a thickness portion of the insulating layer. A diffusion barrier layer is formed to line the damascene opening. A conductive layer is formed overlying the diffusion barrier layer to fill the damascene opening. A carbon-containing metal oxide layer is formed on the conductive layer and the insulating layer. 1forming a low-k dielectric material having a porous structure;depositing a inorganic layer over the low-k dielectric material;performing a first dry etching through a first photolithographic material and the inorganic layer to remove a first section of the low-k dielectric material;performing a second dry etching different through the inorganic layer and a second photolithographic material different from the first photolithographic material to remove a second section of the low-k dielectric material to form a first opening;filling the first opening with a conductive material;removing the inorganic layer with a chemical mechanical planarization after the filling the first opening; mixing aluminum-sec-butoxide with acetylacetone to form a homogenous first precursor;', 'adding water to the homogenous first precursor and stirring to form a second precursor;', 'adding nitric acid to the second precursor to form a third precursor;', 'aging the third precursor; and', 'adding cobalt, manganese, chromium, iron, gold, silver, sodium, titanium, zinc or calcium;, 'forming a diphasic substance with both a liquid phase and a solid phase, the forming the diphasic substance comprisingdispensing the diphasic substance using a spin-coating process between 1000 revolutions per minute and 2000 revolutions per minute;post-treating the diphasic substance with an ultra-violet curing process to form a carbon containing metal oxide layer; anddepositing an etch stop layer directly on the carbon containing metal oxide layer.. A method for manufacturing ...

Lithography using high selectivity spacers for pitch reduction

A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer.

Adhesion Promoter Apparatus and Method

A structure comprises a substrate having a plateau region and a trench region, a reflecting layer formed over a top surface of the trench region, a first adhesion promoter layer formed over the reflecting layer, a bottom cladding layer deposited over the first adhesion promoter layer, a core layer formed over the bottom cladding layer and a top cladding layer formed over the core layer. 1. A structure comprising:a substrate having a high aspect ratio surface feature;an adhesion promoter layer formed over the high aspect ratio surface feature; anda polymer layer formed over the adhesion promoter layer.2. The structure of claim 1 , wherein the substrate comprises:a plateau region; anda trench region, wherein the plateau region and the trench region form the high aspect ratio surface feature.3. The structure of claim 2 , further comprising:a semiconductor structure formed over the trench region; anda metal layer formed over the plateau region.4. The structure of claim 3 , wherein:the semiconductor structure is formed of an oxidized polymer material.5. The structure of claim 3 , wherein:the semiconductor structure is formed of silicon oxide.6. The structure of claim 1 , wherein:the adhesion promoter layer is formed of aminopropyltriethoxysilane (APTES).7. The structure of claim 1 , wherein:the adhesion promoter layer is of a thickness in range from about 10 nm to about 100 nm.8. The structure of claim 1 , wherein:the substrate is of a multi-hydrophilic surface.9. A device comprising: a slope; and', 'a flat bottom, wherein the slope and the flat bottom form an angle of about 45 degrees;, 'a substrate having a plateau region and a trench region, wherein the trench region comprisesa reflecting layer formed over a top surface of the trench region;a first adhesion promoter layer formed over the reflecting layer;a bottom cladding layer deposited over the first adhesion promoter layer;a core layer formed over the bottom cladding layer; anda top cladding layer formed over the ...

Adhesion Promoter Apparatus and Method

An apparatus comprises a substrate having a plateau region and a trench region, a metal layer over the plateau region, a semiconductor component over the trench region, wherein a gap is between the plateau region and the semiconductor component, an adhesion promoter layer over the plateau region, the semiconductor component and the gap, a dielectric layer over the adhesion promoter layer and a bonding interface formed between the adhesion promoter layer and the dielectric layer, wherein the bonding interface comprises a chemical structure comprising a first dielectric material of the adhesion promoter layer and a second dielectric material of the dielectric layer. 1. An apparatus comprising:a substrate having a plateau region and a trench region;a metal layer over the plateau region;an adhesion promoter layer over the plateau region;a dielectric layer over the adhesion promoter layer; anda bonding interface formed between the adhesion promoter layer and the dielectric layer, wherein the bonding interface comprises a chemical structure comprising a first dielectric material of the adhesion promoter layer and a second dielectric material of the dielectric layer.2. The apparatus of claim 1 , wherein:opposite sides of the adhesion promoter layer contact one of hydrophilic surface and one of hydrophobic surface.3. The apparatus of claim 1 , further comprising:a semiconductor component in the trench region, the semiconductor component being formed of non-conductive materials.4. The apparatus of claim 3 , wherein:a gap between the semiconductor component and a sidewall of the trench region has a high aspect ratio.5. The apparatus of claim 1 , wherein:the metal layer is in contact with the substrate and the adhesion promoter layer, and wherein at least one sidewall of the metal layer is covered by the adhesion promoter layer.6. The apparatus of claim 1 , wherein:the dielectric layer is a polymer layer.7. The apparatus of claim 1 , further comprising:the adhesion promoter ...

Semiconductor device metallization systems and methods

Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a mainframe, and a plurality of modules disposed proximate the mainframe. One of the plurality of modules comprises a physical vapor deposition (PVD) module and one of the plurality of modules comprises an ultraviolet light (UV) cure module.

Self-alignment due to wettability difference of an interface

Some embodiments relate to a method of processing a workpiece. The workpiece includes a first surface region having a first wettability coefficient, and a second surface region having a second wettability coefficient that differs from the first wettability coefficient. A liquid, which corresponds to an optical structure, is dispensed on the first and second surface regions of the workpiece, wherein the liquid self-aligns to the second surface region due to the difference between the first and second wettability coefficients. The self-aligned liquid is hardened to form the optical structure.

Schemes for Forming Barrier Layers for Copper in Interconnect Structures

A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a first metal wiring layer, an interlayer insulating layer formed over the first metal layer, a second metal wiring structure embedded in the interlayer dielectric layer and connected to the first metal wiring layer, and an etch-stop layer disposed between the first metal wiring and the first interlayer dielectric layer. The etch-stop layer includes one or more sub-layers. The etch-stop layer includes a first sub-layer made of an aluminum-based insulating material, hafnium oxide, zirconium oxide or titanium oxide.

Method and apparatus for forming self-aligned via with selectively deposited etching stop layer

A first layer is located over a substrate. The first layer includes a first dielectric component and a first conductive component. A first etching stop layer is located over the first dielectric component. A metal capping layer is located over the first conductive component. A second etching stop layer is located over the first etching stop layer and over the metal capping layer. A second layer is located over the second etching stop layer. The second layer includes a second dielectric component and a second conductive component. A third conductive component electrically interconnects the second conductive component to the first conductive component.

METHOD FOR FORMING SEMICONDUCTOR STRUCTURE

A method for forming a semiconductor structure is provided. A substrate including a metal portion and a low-k dielectric portion formed thereon is provided. The metal portion adjoins the low-k dielectric portion. A SAM solution is prepared. The SAM solution includes at least one blocking compound and a multi-solvent system. The multi-solvent system includes an alcohol and an ester. The SAM solution is applied over surfaces of the metal portion and the low-k dielectric portion. The substrate is heated to remove the multi-solvent system of the SAM solution to form a blocking layer on one of the metal portion and the low-k dielectric portion. A material layer is selectively deposited on the other one of the metal portion and the low-k dielectric portion using the blocking layer as a stencil. The blocking layer is removed from the substrate. 1. A method for forming a semiconductor structure , the method comprising:providing a substrate including a metal portion and a low-k dielectric portion formed thereon, wherein the metal portion adjoins the low-k dielectric portion; at least one blocking compound configured to adhere to one of the metal portion and the low-k dielectric portion; and', 'a multi-solvent system comprising an alcohol and an ester, wherein the alcohol has 1 to 6 carbon atoms and the ester has 1 to 6 carbon atoms;, 'preparing a self-assembled monolayer (SAM) solution comprisingapplying the SAM solution over surfaces of the metal portion and the low-k dielectric portion;heating the substrate to remove the multi-solvent system of the SAM solution over the surfaces of the metal portion and the low-k dielectric portion to form a blocking layer on one of the metal portion and the low-k dielectric portion;selectively depositing a material layer on the other one of the metal portion and the low-k dielectric portion using the blocking layer as a stencil, wherein the material layer comprises a metal material or a dielectric material; andremoving the blocking layer ...

OPTICAL ELEMENT STRUCTURE AND OPTICAL ELEMENT FABRICATING PROCESS FOR THE SAME

An optical element structure and a fabricating process for the same are provided. The optical element fabricating process includes providing a substrate forming thereon a protrusion; and forming an over coating layer over the protrusion and the substrate by a deposition scheme to form an optical element.

Light Coupling Device and Methods of Forming Same

An embodiment is a semiconductor device comprising an optical device over a first substrate, a vertical waveguide on a top surface of the optical device, the vertical waveguide having a first refractive index, and a capping layer over the vertical waveguide, the capping layer configured to be a lens for the vertical waveguide and the capping layer having a second refractive index.

METHOD AND APPARATUS FOR FORMING SELF-ALIGNED VIA WITH SELECTIVELY DEPOSITED ETCHING STOP LAYER

A first conductive element is disposed. in a first dielectric layer. An etching stop layer is disposed on the first dielectric layer but not on the first conductive element. A first metal capping layer segment is disposed on the first conductive element but not on the first dielectric layer. The etching stop layer has a greater thickness than the first metal capping layer segment. A first segment of a second conductive element is disposed on the first metal capping layer segment. A second segment of the second conductive element is disposed over the first segment of the second conductive element and partially over the etching stop layer. A third conductive element is disposed over the second conductive element. 1. A semiconductor device , comprising:a first conductive element disposed in a first dielectric layer;an etching stop layer disposed on the first dielectric layer;a metal capping layer disposed on the first conductive element; anda second conductive element, wherein a first segment of the second conductive element is disposed on the metal capping layer, and wherein a second segment of the second conductive element is disposed over the first segment and partially over the etching stop layer.2. The semiconductor device of claim 1 , wherein the etching stop layer is disposed on the first conductive element.3. The semiconductor device of claim 1 , wherein the metal capping layer is not disposed on the first dielectric layer.4. The semiconductor device of claim 1 , further comprising: a third conductive element disposed over the second conductive element.5. The semiconductor device of claim 4 , wherein:the first conductive element includes a first metal line in a MX interconnect layer;the third conductive element includes a second metal line in a MX+1 interconnect layer; andthe second conductive element includes a via.6. The semiconductor device of claim 1 , further comprising:a fourth conductive element disposed in the first dielectric layer;a further metal ...

Zwischenverbindungsstruktur, die Schäden an der Isolierschicht vermeidet, und Verfahren für ihre Herstellung

Ein Verfahren zum Bilden einer Zwischenverbindungsstruktur enthält das Ausbilden einer Isolierschicht auf einem Substrat. Eine Damaszen-Öffnung wird durch einen Dickenabschnitt der Isolierschicht hindurch gebildet. Eine Diffusionssperrschicht wird gebildet, um die Damaszen-Öffnung auszukleiden. Eine leitfähige Schicht wird über der Diffusionssperrschicht gebildet, um die Damaszen-Öffnung auszufüllen. Eine kohlenstoffhaltige Metalloxidschicht wird auf der leitfähigen Schicht und der Isolierschicht gebildet.

Semiconductor device metallization systems and methods

Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a mainframe, and a plurality of modules disposed proximate the mainframe. One of the plurality of modules comprises a physical vapor deposition (PVD) module and one of the plurality of modules comprises an ultraviolet light (UV) cure module.

PROTECTING LAYER IN A SEMICONDUCTOR STRUCTURE

A semiconductor structure comprises a dielectric layer, a conduction piece, a first metal piece, a first protecting layer, and a second protecting layer. The conduction piece is surrounded by electrical materials of the dielectric layer. The first metal piece is over the dielectric layer and is in contact with the conduction piece. The first protecting layer covers dielectric materials of the dielectric layer that are not covered by the first metal piece. The second protecting layer is over the first protecting layer. 1. A semiconductor structure comprising:a dielectric layer;a conduction piece surrounded by a dielectric material of the dielectric layer;a first metal piece over the dielectric layer and in contact with the conduction piece;a first protecting layer covering dielectric materials of the dielectric layer that are not covered by the first metal piece; anda second protecting layer over the first protecting layer.2. The semiconductor structure of claim 1 , wherein:the semiconductor structure is configured to be subject to a plasma treatment process.3. The semiconductor structure of claim 1 , wherein:the first protecting layer includes at least one of silicon doped nitride, carbon nitride, silicon nitride, and silicon carbon.4. The semiconductor structure of claim 1 , wherein:a thickness of the first protecting layer is at most 30 Å.5. The semiconductor structure of claim 1 , wherein: the first protecting layer is configured to reduce and/or eliminate metal ion diffusion into the dielectric layer; and', 'the first protecting layer is configured to reduce and/or eliminate plasma elements into the dielectric layer., 'the semiconductor is configured to meet at least one of the following conditions6. The semiconductor structure of claim 1 , wherein:the first protecting layer is configured to cover the first metal piece.7. A method for forming a protecting layer claim 1 , the method comprising:determining a plurality of relationships;based on the plurality of ...

Forming Interlayer Dielectric Material by Spin-On Metal Oxide Deposition

A plurality of high-k metal gate (HKMG) structures is formed over a substrate. The (HKMG) structures are separated by a plurality of gaps. The HKMG structures each include a first dielectric layer at an upper surface of the HKMG structure. The gaps are filled with a first conductive material. A portion of the first conductive material is removed in each of the gaps through an etching-back process. A metal oxide layer is formed using a spin-on deposition process. The metal oxide layer is formed over the (HKMG) structures and over the first conductive material. A second dielectric layer is formed over the metal oxide layer. An opening is etched in the second dielectric layer. The opening is etched through the second dielectric layer and through the metal oxide layer. The opening is filled with a second conductive material. 1. A semiconductor device , comprising:a plurality of gate structures disposed over a substrate, wherein the gate structures are separated by a plurality of gaps;a first dielectric material disposed over the substrate and partially filling the gaps;a conductive material disposed over the first dielectric material in each of the gaps; anda metal oxide material disposed over the conductive material.2. The semiconductor device of claim 1 , further comprising a first conductive contact disposed over at least one of the gate structures claim 1 , wherein the first conductive contact extends through at least the metal oxide material.3. The semiconductor device of claim 2 , further comprising a second conductive contact disposed over the conductive material.4. The semiconductor device of claim 3 , wherein:the gate structures each contain a silicon nitride layer at an upper surface of the gate structures;the first conductive contact extends through the silicon nitride layer; andthe second conductive contact extends through the metal oxide material but not through the silicon nitride layer.5. The semiconductor device of claim 3 , wherein the second conductive ...

Adhesion Promoter Apparatus and Method

A method comprises forming a plateau region and a trench region over a substrate, wherein the trench region comprises a slope and a flat bottom, depositing a reflecting layer over the flat bottom and a portion of the slope, depositing a first adhesion promoter layer over the reflecting layer, applying a first curing process to the first adhesion promoter layer, wherein, after the first curing process finishes, the reflecting layer and the first adhesion promoter layer form a first bonding interface, depositing a bottom cladding layer deposited over the first adhesion promoter layer, applying a second curing process to the bottom cladding layer to form a second bonding interface layer, depositing a core layer over the bottom cladding layer and depositing a top cladding layer over the core layer. 1. A method comprising:forming a plateau region and a trench region over a substrate, wherein the trench region comprises a slope and a flat bottom;depositing a reflecting layer over the flat bottom and a portion of the slope;depositing a first adhesion promoter layer over the reflecting layer;applying a first curing process to the first adhesion promoter layer, wherein, after the first curing process finishes, the reflecting layer and the first adhesion promoter layer form a first bonding interface;depositing a bottom cladding layer over the first adhesion promoter layer;applying a second curing process to the bottom cladding layer to form a second bonding interface layer;depositing a core layer over the bottom cladding layer; anddepositing a top cladding layer over the core layer.2. The method of claim 1 , further comprising:after performing the first curing process and the second curing process, forming a chemical structure comprising an oxidized material on a surface of the reflecting layer, a first dielectric material of the first adhesion promoter layer and a second dielectric material of the bottom cladding layer.3. The method of claim 1 , further comprising:prior to ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE

A semiconductor device includes a first conductive feature, a second conductive feature, and a first dielectric layer positioned between the first conductive feature and the second conductive feature. An etch stop layer is over the first dielectric layer. A cap layer is over the first conductive feature, the second conductive feature, and the etch stop layer. 1. A semiconductor device , comprising:a first conductive feature;a second conductive feature;a first dielectric layer positioned between the first conductive feature and the second conductive feature;an etch stop layer over the first dielectric layer; anda cap layer over the first conductive feature, the second conductive feature, and the etch stop layer, wherein the cap layer is adjacent a sidewall of the etch stop layer.2. The semiconductor device of claim 1 , wherein the cap layer is in contact with the sidewall of the etch stop layer and a top surface of the first conductive feature.3. The semiconductor device of claim 1 , comprising:a second dielectric layer positioned over the cap layer; anda contact positioned in the second dielectric layer, wherein the contact is in contact with a top surface of the second conductive feature and a top surface of the etch stop layer.4. The semiconductor device of claim 3 , wherein the contact is in contact with a sidewall of the cap layer and a sidewall of the etch stop layer.5. The semiconductor device of claim 1 , comprising:an encapsulation layer adjacent a sidewall of the second conductive feature, wherein the etch stop layer is over a top surface of the encapsulation layer.6. The semiconductor device of claim 1 , comprising:a second dielectric layer positioned under the first dielectric layer; anda third conductive feature positioned in the second dielectric layer and underlying the second conductive feature.7. The semiconductor device of claim 1 , comprising an air gap defined in the first dielectric layer.8. The semiconductor device of claim 1 , wherein the first ...

Semiconductor device metallization systems and methods

Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a mainframe, and a plurality of modules disposed proximate the mainframe. One of the plurality of modules comprises a physical vapor deposition (PVD) module and one of the plurality of modules comprises an ultraviolet light (UV) cure module.

Self-Aligned Interconnection Structure and Method

The present disclosure provides a method that includes providing a substrate having a first dielectric material layer and first conductive features that are laterally separated from each other by segments of the first dielectric material layer; depositing a first etch stop layer on the first dielectric material layer and the first conductive features, thereby forming the first etch stop layer having oxygen-rich portions self-aligned with the segments of the first dielectric material layer and oxygen-poor portions self-aligned with the first conductive features; performing a selective removal process to selectively remove the oxygen-poor portions of the first etch stop layer; forming a second etch stop layer on the first conductive features and the oxygen-rich portions of the first etch stop layer; forming a second dielectric material layer on the second etch stop layer; and forming a conductive structure in the second dielectric material layer. 1. A method of fabricating an integrated circuit , comprising:providing a substrate having a first dielectric material layer and first conductive features that are embedded in the first dielectric material layer and are laterally separated from each other by segments of the first dielectric material layer;depositing a first etch stop layer on the first dielectric material layer and the first conductive features, thereby forming the first etch stop layer having oxygen-rich portions self-aligned with the segments of the first dielectric material layer and oxygen-poor portions self-aligned with the first conductive features;performing a selective removal process to the first etch stop layer, thereby selectively removing the oxygen-poor portions of the first etch stop layer;forming a second etch stop layer on the first conductive features and the oxygen-rich portions of the first etch stop layer, wherein the second etch stop layer is different from the first etch stop layer in composition;forming a second dielectric material ...

Semiconductor devices and methods of forming same

A semiconductor device structure and methods of forming the same are disclosed. An embodiment is a method of forming a semiconductor device, the method comprising forming a first conductive line over a substrate, and conformally forming a first dielectric layer over a top surface and a sidewall of the first conductive line, the first dielectric layer having a first porosity percentage and a first carbon concentration. The method further comprises forming a second dielectric layer on the first dielectric layer, the second dielectric layer having a second porosity percentage and a second carbon concentration, the second porosity percentage being different from the first porosity percentage, and the second carbon concentration being less than the first carbon concentration.

Semiconductor Integrated Circuit and Fabricating the Same

A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a precursor. A decomposable polymer layer (DPL) is deposited between the conductive features of the precursor. The DPL is annealed to form an ordered periodic pattern of different types of polymer nanostructures. One type of polymer nanostructure is decomposed by a first selectively to form a trench. The trench is filled by a dielectric layer to form a dielectric block. The remaining types of polymer nanostructures are decomposed by a second selectively etching to form nano-air-gaps. 1. A method for fabricating a semiconductor integrated circuit (IC) , the method comprising: a substrate;', 'conductive features extending above the substrate; and', 'a space between the conductive features;, 'receiving a precursor, the precursor includingdepositing a decomposable polymer layer (DPL) in the space between the conductive features on the precursor;annealing the DPL to form an ordered periodic pattern of different types of polymer nanostructures between the conductive features;performing a first selective etch to decompose a first type of the polymer nanostructures to form a trench and a template with the ordered repeating periodic pattern of the trench and a second type of polymer nanostructures between conductive features;filling in the trench with a dielectric layer to form a dielectric block; andperforming a second selectively etching to decompose the second type of polymer nanostructures to form a dielectric matrix of nano-air gaps and the dielectric block between constructive features.2. The method of claim 1 , wherein the conductive features include copper lines.3. The method of claim 1 , wherein the DPL includes a block co-polymer (BCP) layer.4. The method of claim 3 , wherein the BCP layer includes one or more materials from the group consisting of polystyrene-block-polymethylmethacrylate (PS-b-PMMA) claim 3 , polyethyleneoxide-block-polyisoprene (PEO-b-PI) ...

Method of fabricating semiconductor device

A method and structure for forming an enhanced metal capping layer includes forming a portion of a multi-level metal interconnect network over a substrate. In some embodiments, the portion of the multi-level metal interconnect network includes a plurality of metal regions. In some cases, a dielectric region is disposed between each of the plurality of metal regions. By way of example, a metal capping layer may be deposited over each of the plurality of metal regions. Thereafter, in some embodiments, a self-assembled monolayer (SAM) may be deposited, where the SAM forms selectively on the metal capping layer, while the dielectric region is substantially free of the SAM. In various examples, after selectively forming the SAM on the metal capping layer, a thermal process may be performed, where the SAM prevents diffusion of the metal capping layer during the thermal process.

System and method for dark field inspection

The present disclosure provides a method for fabricating a semiconductor structure. The method comprises providing a substrate and a patterned layer formed on the substrate, one or more overlay marks being formed on the patterned layer; performing a pre-film-formation overlay inspection using a bright field (BF) inspection tool to receive a pre-film-formation data on the one or more overlay marks on the patterned layer; forming one or more layers on the patterned layer; performing a post-film-formation overlay inspection using a dark field (DF) inspection tool to receive a post-film-formation data on the one or more overlay marks underlying the one or more layers; and determining whether the pre-film-formation data matches the post-film-formation data.

Methods for fabricating a low-resistance interconnect

Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a first metal feature in a dielectric layer and a capping layer over the first metal feature, selectively depositing a blocking layer over the capping layer, depositing an etch stop layer (ESL) over the workpiece, removing the blocking layer, and depositing a second metal feature over the workpiece such that the first metal feature is electrically coupled to the second metal feature. The blocking layer prevents the ESL from being deposited over the capping layer.

Package structure and methods of forming same

A semiconductor device, a package structure, and methods of forming the same are disclosed. An embodiment is a semiconductor device comprising a first optical device over a first substrate, a vertical waveguide on a top surface of the first optical device, and a second substrate over the vertical waveguide. The semiconductor device further comprises a lens capping layer on a top surface of the second substrate, wherein the lens capping layer is aligned with the vertical waveguide, and a second optical device over the lens capping layer.

Liner Formation in 3DIC Structures

An integrated circuit structure includes a semiconductor substrate; a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and a TSV liner in the TSV opening. The TSV liner includes a sidewall portion on a sidewall of the TSV opening and a bottom portion at a bottom of the TSV opening. The bottom portion of the TSV liner has a bottom height greater than a middle thickness of the sidewall portion of the TSV liner. 1. A method comprising:forming an opening in a substrate; andforming a liner dielectric in the opening, wherein the liner dielectric comprises a sidewall portion on a sidewall of the opening and a bottom portion on a bottom of the opening, and wherein thicknesses of the sidewall portion increase substantially continuously from top to bottom.2. The method of claim 1 , wherein the liner dielectric is formed using spin-on coating.3. The method of claim 2 , wherein the spin-on coating comprises:placing the substrate with the opening facing up;rotating the substrate with a first speed;spraying a chemical on the substrate;after the step of spraying the chemical, stopping rotating the substrate; andafter the step of stopping rotating the substrate, rotating the substrate with a second speed greater than the first speed.4. The method of claim 3 , wherein the first speed is between about 200 revolutions per minute (RPM) and about 250 RPM.5. The method of claim 3 , wherein a duration of the step of stopping rotating is greater than about 10 seconds.6. The method of claim 3 , wherein claim 3 , at a time the chemical is sprayed on the substrate claim 3 , an evaporation rate of the chemical is greater than about 3 pound per square inch (psi).7. The method of claim 3 , wherein the chemical comprises tetra-ethyl-ortho-silicate (TEOS) and methyltriethoxysilane (MTES).8. A method of forming an integrated circuit structure claim 3 , the method comprising:providing a semiconductor substrate;forming a through-semiconductor via (TSV) opening in ...

STRUCTURE AND METHOD FOR TUNABLE INTERCONNECT SCHEME

The present disclosure provides one embodiment of a method to form an interconnect structure. The method includes forming a first dielectric material layer on a substrate; patterning the first dielectric material layer to form a plurality of vias therein; forming a metal layer on the first dielectric layer and the substrate, wherein the metal layer fills in the plurality of vias; and etching the metal layer such that portions of the metal layer above the first dielectric material layer are patterned to form a plurality of metal lines, aligned with plurality of vias, respectively. 1. A method , comprising:forming a first dielectric material layer on a substrate;patterning the first dielectric material layer to form a plurality of vias therein;forming a metal layer on the first dielectric layer and the substrate, wherein the metal layer fills the plurality of vias; andetching the metal layer such that portions of the metal layer above the first dielectric material layer are patterned to form a plurality of metal lines aligned with the plurality of vias, respectively.2. The method of claim 1 , further comprising forming a second dielectric material on the plurality of metal lines and in gaps between neighbor metal lines.3. The method of claim 2 , wherein the forming a second dielectric material layer includes forming air voids inside the second dielectric material layer.4. The method of claim 2 , wherein each of the first and second dielectric material layers includes a low-k dielectric material.5. The method of claim 1 , wherein the forming a metal layer includes forming a copper-containing material selected from a group consisting of copper (Cu) claim 1 , copper magnesium (CuMn) claim 1 , copper aluminum (CuAl) claim 1 , copper silicon (CuSi) and combinations thereof.6. The method of claim 1 , further comprising:forming a first barrier layer of a first material in the plurality of vias and on the first dielectric material layer prior to the forming of the metal layer ...

METHOD OF FABRICATION POLYMER WAVEGUIDE

A method of fabricating a waveguide device is disclosed. The method includes providing a substrate having an elector-interconnection region and a waveguide region and forming a patterned dielectric layer and a patterned redistribution layer (RDL) over the substrate in the electro-interconnection region. The method also includes bonding the patterned RDL to a vertical-cavity surface-emitting laser (VCSEL) through a bonding stack. A reflecting-mirror trench is formed in the substrate in the waveguide region, and a reflecting layer is formed over a reflecting-mirror region inside the waveguide region. The method further includes forming and patterning a bottom cladding layer in a wave-tunnel region inside the waveguide region and forming and patterning a core layer and a top cladding layer in the waveguide region. 1. A method of fabricating a polymer waveguide device , the method comprising:providing a substrate having an elector-interconnection region and a waveguide region;forming a patterned dielectric layer and a patterned redistribution layer (RDL) over the substrate in the electro-interconnection region;bonding the patterned RDL to a vertical-cavity surface-emitting laser (VCSEL) through a bonding stack;forming a reflecting-mirror trench in the substrate in the waveguide region, wherein the waveguide region has a reflecting-mirror region and a wave-tunnel region;forming a reflecting layer at least over the reflecting-mirror region;forming a patterned bottom cladding layer in the wave-tunnel region; andforming a patterned core layer and a patterned top cladding layer over the reflecting layer in the reflecting-mirror region and over the bottom cladding layer in the wave-tunnel region.2. The method of claim 1 , wherein the substrate includes Si with a (100) crystal orientation.3. The method of claim 1 , wherein the reflecting-mirror trench is formed with a 45° inclined slope sidewall profile in the Si (100) substrate.4. The method of claim 3 , wherein the 45° ...

OPTICAL BENCH ON SUBSTRATE

An optical bench on substrate includes a substrate and a trench formed inside the substrate and having a sloping side. A reflector layer is formed over the sloping side. An optical component is mounted over the substrate. The reflector layer is configured to reflect an electromagnetic wave to or from the optical component. 1. An optical bench on substrate , comprising:a substrate;a trench formed inside the substrate and having a sloping side;a reflector layer formed over the sloping side; anda first optical component mounted over the substrate;wherein the reflector layer is configured to reflect an electromagnetic wave to or from the optical component.2. The optical bench on substrate of claim 1 , wherein the substrate comprises silicon.3. The optical bench on substrate of claim 1 , wherein the first optical component is flip-chip mounted over the substrate.4. The optical bench on substrate of claim 1 , wherein the first optical component is a laser diode or a photo diode.5. The optical bench on substrate of claim 1 , further comprising a waveguide formed inside the trench wherein the waveguide is configured to guide the electromagnetic wave to or from the reflector layer.6. The optical bench on substrate of claim 5 , wherein the waveguide comprises an optical fiber.7. The optical bench on substrate of claim 1 , further comprising at least one through substrate via formed through the substrate.8. The optical bench on substrate of claim 1 , further comprising a redistribution layer formed over the substrate.9. The optical bench on substrate of claim 8 , further comprising a dielectric layer formed between the redistribution layer and the substrate.10. The optical bench on substrate of claim 1 , wherein the sloping side has a slope angle ranging from 42° to 48°.11. The optical bench on substrate of claim 1 , wherein the reflector layer comprises at least one of Al claim 1 , Cu claim 1 , Ag claim 1 , or Au.12. A method claim 1 , comprising:forming a trench inside a ...

Interconnect structures

A semiconductor structure includes a first dielectric layer over a substrate. At least one first conductive structure is within the first dielectric layer. The first conductive structure includes a cap portion extending above a top surface of the first dielectric layer. At least one first dielectric spacer is on at least one sidewall of the cap portion of the first conductive structure.

Schemes for Forming Barrier Layers for Copper in Interconnect Structures

A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided. 1. A semiconductor structure comprising:a dielectric layer over a substrate;an opening extending from a top surface of the dielectric layer into the dielectric layer;a first barrier layer lining the opening;a conductive wiring in a remaining portion of the opening, wherein a top edge of the first barrier layer is recessed from at least a portion of a sidewall of the conductive wiring; anda second barrier layer covering a top surface and the portion of the sidewall of the conductive wiring, wherein the second barrier layer does not extend over the dielectric layer.2. The semiconductor structure of claim 1 , wherein the first barrier layer comprises a metal that can be silicided.3. The semiconductor structure of claim 2 , wherein the metal comprises a material selected from the group consisting essentially of cobalt claim 2 , nickel claim 2 , and combinations thereof.4. The semiconductor structure of claim 1 , wherein the first barrier layer is free from cobalt and nickel.5. The semiconductor structure of claim 1 , wherein the conductive wiring comprises copper.6. The semiconductor structure of claim 1 , wherein the second barrier layer is a derivative of a carbon-based silane.7. A semiconductor device comprising:a conductive material embedded within a dielectric layer over a substrate, the conductive material being planar with the dielectric layer;a first barrier ...

Using a self-assembly layer to facilitate selective formation of an etching stop layer

A structure is provided that includes a first conductive component and a first interlayer dielectric (ILD) that surrounds the first conductive component. A self-assembly layer is formed on the first conductive component but not on the first ILD. A first dielectric layer is formed over the first ILD but not over the first conductive component. A second ILD is formed over the first conductive component and over the first ILD. An opening is etched in the second ILD. The opening is at least partially aligned with the first conductive component. The first dielectric layer protects portions of the first ILD located therebelow from being etched. The opening is filled with a conductive material to form a second conductive component in the opening.

Lithography Using High Selectivity Spacers for Pitch Reduction

A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer. 1. A method comprising:patterning a dummy layer over a mask layer to form one or more dummy lines;forming a spacer layer over top surfaces and sidewalls of the one or more dummy lines, wherein the spacer layer comprises a transition metal oxide or a transition metal nitride;forming a first reverse material layer over the spacer layer, wherein the spacer layer and the first reverse material layer comprise different materials;patterning the first reverse material layer, wherein the patterning of the first reverse material layer comprises etching the first reverse material layer at a faster rate than the spacer layer;removing the one or more dummy lines; andpatterning the mask layer using the spacer layer and the first reverse material layer as a mask.2. The method of claim 1 , wherein patterning the dummy layer comprises:forming a hard mask layer and a bi-layered photoresist successively over the dummy layer, the bi-layered photoresist comprising a top layer and a bottom layer;patterning the top layer of the bi-layered photoresist to form a first pattern;transferring the first pattern of the top layer to the bottom layer of the bi-layered photoresist and to ...

Semiconductor Device Having a Porous Low-K Structure

The present disclosure involves forming a porous low-k dielectric structure. A plurality of conductive elements is formed over the substrate. The conductive elements are separated from one another by a plurality of openings. A barrier layer is formed over the conductive elements. The barrier layer is formed to cover sidewalls of the openings. A treatment process is performed to the barrier layer. The barrier layer becomes hydrophilic after the treatment process is performed. A dielectric material is formed over the barrier layer after the treatment process has been performed. The dielectric material fills the openings and contains a plurality of porogens. 1. A semiconductor device , comprising:a substrate;a plurality of conductive elements disposed over the substrate, wherein the conductive elements are separated from one another by a plurality of openings; anda dielectric material disposed over and between the conductive elements, wherein the dielectric material includes:a first portion that is disposed inside the openings; anda second portion that is disposed over the openings and over the conductive elements;wherein the first portion is substantially more porous than the second portion.2. The semiconductor device of claim 1 , wherein the first portion of the dielectric material has a substantially lower dielectric constant than the second portion of the dielectric material.3. The semiconductor device of claim 1 , wherein:the dielectric material contains a plurality of porous structures; andthe porous structures disposed in the first portion of the dielectric material are substantially larger in size than the porous structures disposed in the second portion of the dielectric material.4. The semiconductor device of claim 1 , further comprising a barrier layer disposed between the conductive elements and the dielectric material claim 1 , wherein surfaces of the barrier layer have hydrophilic characteristics.5. The semiconductor device of claim 1 , wherein the ...

Lithography Using High Selectivity Spacers for Pitch Reduction

A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer.

PROCESSING APPARATUS AND METHOD

A processing apparatus includes a spin coating chamber, an ultraviolet curing chamber, a transfer module and an enclosure. The transfer module is assigned with a plurality transfer destinations, in which two of the transfer destinations are respectively located within the spin coating chamber and the ultraviolet curing chamber. The transfer module, the spin coating chamber and the ultraviolet curing chamber are enclosed by the enclosure. 1. A processing apparatus , comprising:a spin coating chamber ;an ultraviolet curing chamber;a transfer module assigned with a plurality transfer destinations, wherein two of the transfer destinations are respectively located within the spin coating chamber and the ultraviolet curing chamber, the transfer module comprising a robot movable from the spin coating chamber to the ultraviolet curing chamber;an enclosure enclosing the transfer module, the spin coating chamber and the ultraviolet curing chamber; anda load port closer to the robot than to the ultraviolet curing chamber.2. The processing apparatus of claim 1 , further comprising:an ultraviolet blocking structure present between the spin coating chamber and the ultraviolet curing chamber.3. The processing apparatus of claim 1 , further comprising:a fluid isolating structure present between the spin coating chamber and the ultraviolet curing chamber.4. The processing apparatus of claim 1 , wherein the enclosure comprises a plurality of spatially separated internal regions that are respectively occupied by the spin coating chamber and the ultraviolet curing chamber.5. The processing apparatus of claim 1 , further comprising:a baking chamber within which another of the transfer destinations assigned to the transfer module is located, the baking chamber being enclosed by the enclosure.6. The processing apparatus of claim 5 , further comprising:a controller configured to control the transfer module to move to the transfer destinations located within the spin coating chamber, the ...

Semiconductor device structure

A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first conductive structure over the substrate. The semiconductor device structure includes a first dielectric layer over the substrate and the first conductive structure. The semiconductor device structure includes a second conductive structure over the first conductive structure and extending into the first dielectric layer. The second conductive structure is electrically connected to the first conductive structure. The semiconductor device structure includes a cover layer between the second conductive structure and the first dielectric layer. The cover layer surrounds the second conductive structure, the second conductive structure passes through the cover layer and is partially between the cover layer and the first conductive structure, and the cover layer includes a metal oxide.

Etchant and Etching Process

A system and method for manufacturing semiconductor devices is provided. An embodiment comprises using an etchant to remove a portion of a substrate to form an opening with a 45° angle with a major surface of the substrate. The etchant comprises a base, a surfactant, and an oxidant. The oxidant may be hydrogen peroxide. 1. A semiconductor material etchant comprising:a base for removing material from a waveguide substrate covered with a patterned hardmask, the base having a concentration of between 25%-wt and about 35%-wt;a surfactant for modifying an angle of etching to about 45% from a major surface of the waveguide substrate, the surfactant reactable on the waveguide substrate to form an oil by-product, the surfactant having a concentration of between about 0.01%-wt and about 0.4%-wt; andan oxidant for oxidizing the waveguide substrate beneath the oil by-product, the oxidant having a concentration of between about 0.1%-wt and about 0.2%-wt.2. The semiconductor material etchant of claim 1 , wherein the oxidant is HO.3. The semiconductor material etchant of claim 1 , wherein the oxidant is ozone.4. The semiconductor material etchant of claim 1 , wherein the oxidant is KMnO.5. The semiconductor material etchant of claim 1 , wherein the base comprises KOH and the oxidant comprises HO.6. The semiconductor material etchant of claim 1 , wherein the base comprises KOH and the oxidant comprises HO.7. The semiconductor material etchant of claim 6 , wherein the surfactant comprises a sulfonate base.8. The semiconductor material etchant of claim 6 , wherein the surfactant comprises alkyl polysaccharide.9. A semiconductor device comprising:an optical bench substrate;an opening in the optical bench substrate, the opening having an angle of about 45%-wt from a major surface of the optical bench substrate and having a bottom surface free from etching hillocks; anda reflective material covering the opening from a first side of the opening to a second side of the opening opposite ...

Method and Structure for Semiconductor Device Having Gate Spacer Protection Layer

A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts. 1. A method of forming a semiconductor device , the method comprising: a substrate;', 'a gate stack over the substrate;', 'a first dielectric layer over the gate stack;', 'a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and', 'source and drain (S/D) contacts on opposing sides of the gate stack;, 'providing a precursor that includesrecessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack; andforming a spacer protection layer over the recessed gate spacer, the first dielectric layer, and the S/D contacts.2. The method of claim 1 , further comprising:before the forming of the spacer protection layer, recessing the S/D contacts below a top surface of the first dielectric layer.3. The method of claim 1 , wherein the gate spacer claim 1 , the first dielectric layer claim 1 , and the S/D contacts are coplanar before the recessing of the gate spacer.4. The method of claim 1 , wherein the recessing of the gate spacer fully exposes the sidewalls of the first dielectric layer.5. The method of claim 1 , further comprising:forming a second dielectric layer over the spacer protection layer; andrecessing at least the second dielectric layer and the spacer protection layer to expose a top ...

Etching Apparatus

A system and method of etching a semiconductor device are provided. Etching solution is sampled and analyzed by a monitoring unit to determine a concentration of components within the etching solution, such as an oxidant concentration. Then, based upon such measurement, a makeup amount of the components may be added be a makeup unit to the etching solution to control the concentration of the components within the etching system. 1. A method of etching a semiconductor device , the method comprising:removing a sample from an etching solution;analyzing the sample to determine a concentration of an oxidant within the sample;introducing a makeup amount of the oxidant into the etching solution based upon the concentration of the oxidant from analyzing the sample; andetching a semiconductor substrate with the etching solution to form a etched surface, wherein after the etching the semiconductor substrate the etched surface is free from hillocks.2. The method of claim 1 , wherein the analyzing the sample further comprises performing an oxidation reduction potential measurement of the sample.3. The method of claim 1 , wherein the analyzing the sample further comprises performing an optical spectrum analysis of the sample.4. The method of claim 3 , wherein the optical spectrum analysis further comprises a UV absorption spectrum analysis.5. The method of claim 1 , further comprising filtering the etching solution to remove oil drop by-products from the etching solution.6. The method of claim 1 , further comprising cooling the sample prior to the analyzing the sample.7. A method of manufacturing a semiconductor device claim 1 , the method comprising:receiving a substrate into an etchant tank holding an etchant, the etchant comprising a strong base, a surfactant, and an oxidant;analyzing a sample of the etchant;determining an amount of makeup to add to the etchant in the etchant tank;mixing one or more of a makeup strong base, a makeup surfactant, and a makeup oxidant to form ...

Metal Oxide Composite as Etch Stop Layer

A method includes providing a dielectric layer; forming a metal line in the dielectric layer; forming an etch stop layer on the metal line, wherein the etch stop layer includes a metal atom bonded with a hydroxyl group; performing a treatment process to the etch stop layer to displace hydrogen in the hydroxyl group with an element other than hydrogen; partially etching the etch stop layer to expose the metal line; and forming a conductive feature above the etch stop layer and in physical contact with the metal line. 1. A method , comprising:providing a dielectric layer;forming a metal line in the dielectric layer;forming an etch stop layer on the metal line, wherein the etch stop layer includes a metal atom bonded with a hydroxyl group;performing a treatment process to the etch stop layer to displace hydrogen in the hydroxyl group with an element other than hydrogen;partially etching the etch stop layer to expose the metal line; andforming a conductive feature above the etch stop layer and in physical contact with the metal line.2. The method of claim 1 , wherein the treatment process includes a plasma treatment containing nitrogen and the element is nitrogen.3. The method of claim 1 , wherein the treatment process includes depositing a dopant and the element is silicon.4. The method of claim 3 , wherein the dopant includes a silicon-based monomer.5. The method of claim 4 , wherein the silicon-based monomer includes at least a functional group selected from methyl claim 4 , ethyl claim 4 , or phenyl.6. The method of claim 1 , wherein after the performing of the treatment process claim 1 , the etch stop layer includes a M-O—Si group claim 1 , M representing the metal atom.7. The method of claim 1 , wherein after the performing of the treatment process claim 1 , the etch stop layer includes a Si—O—Si group.8. The method of claim 7 , wherein the Si—O—Si group is part of a M-O—Si—O—Si-M group claim 7 , M representing the metal atom.9. The method of claim 1 , wherein the ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE

A semiconductor device includes a first conductive feature, a second conductive feature, and a first dielectric layer positioned between the first conductive feature and the second conductive feature. An etch stop layer is over the first dielectric layer. A cap layer is over the first conductive feature, the second conductive feature, and the etch stop layer. 1. A semiconductor device , comprising:a first conductive feature;a second conductive feature;a first dielectric layer positioned between the first conductive feature and the second conductive feature;an etch stop layer over the first dielectric layer;a cap layer over the first conductive feature, the second conductive feature, and the etch stop layer, wherein the cap layer is adjacent a first sidewall of the etch stop layer; and the contact is separated from the portion of the first dielectric layer by the etch stop layer, and', 'the contact in direct contact with a top surface of the etch stop layer and electrically coupled to the second conductive feature., 'a contact overlying a portion of the first dielectric layer positioned between the first conductive feature and the second conductive feature, wherein2. The semiconductor device of claim 1 , wherein the contact is in direct contact with a sidewall of the cap layer and a second sidewall of the etch stop layer.3. The semiconductor device of claim 1 , wherein the contact is in direct contact with a sidewall of the cap layer.4. The semiconductor device of claim 1 , wherein the cap layer is in direct contact with the first sidewall of the etch stop layer.5. The semiconductor device of claim 1 , comprising:a second dielectric layer over the cap layer, wherein a sidewall of the second dielectric layer is adjacent a sidewall of the cap layer.6. The semiconductor device of claim 5 , wherein the sidewall of the second dielectric layer is in direct contact with the sidewall of the cap layer.7. The semiconductor device of claim 1 , comprising:an encapsulation layer ...

Self-Aligned Interconnection Structure and Method

The present disclosure provides a method that includes providing a substrate having a first dielectric material layer and first conductive features that are laterally separated from each other by segments of the first dielectric material layer; depositing a first etch stop layer on the first dielectric material layer and the first conductive features, thereby forming the first etch stop layer having oxygen-rich portions self-aligned with the segments of the first dielectric material layer and oxygen-poor portions self-aligned with the first conductive features; performing a selective removal process to selectively remove the oxygen-poor portions of the first etch stop layer; forming a second etch stop layer on the first conductive features and the oxygen-rich portions of the first etch stop layer; forming a second dielectric material layer on the second etch stop layer; and forming a conductive structure in the second dielectric material layer. 1. A device comprising:a first conductive feature disposed in a first dielectric layer;a metal oxide layer disposed directly on a top surface of the first dielectric layer;a non-metal etch stop layer disposed directly on a top surface of the metal oxide layer and a top surface of the first conductive feature; anda second conductive feature disposed directly on the top surface of the first conductive feature and the top surface of the metal oxide layer.2. The device of claim 1 , further comprising a third conductive feature disposed in the first dielectric layer claim 1 , wherein the non-metal etch stop layer is disposed directly on a top surface of the second conductive feature.3. The device of claim 2 , wherein the top surface of the second conductive feature extends from a first sidewall of the second conductive feature to a second sidewall of the second conductive feature claim 2 , the second sidewall opposing the first sidewall claim 2 , andwherein the non-metal etch stop layer completely covers the top surface of the ...

INTERCONNECT STRUCTURE AND METHOD FOR FORMING THE SAME

A method for forming an interconnect structure is provided. The method for forming the interconnect structure includes forming a first dielectric layer over a substrate, forming a first conductive feature through the first dielectric layer, forming a first blocking layer on the first conductive feature, forming a first etching stop layer over the first dielectric layer and exposing the first blocking layer, removing at least a portion of the first blocking layer, forming a first metal bulk layer over the first etching stop layer and the first conductive feature, and etching the first metal bulk layer to form a second conductive feature electrically connected to the first conductive feature. 1. A method for forming an interconnect structure , comprising:forming a first dielectric layer over a substrate;forming a first conductive feature through the first dielectric layer;forming a first blocking layer on the first conductive feature;forming a first etching stop layer over the first dielectric layer and exposing the first blocking layer;removing at least a portion of the first blocking layer;forming a first metal bulk layer over the first etching stop layer and the first conductive feature; andetching the first metal bulk layer to form a second conductive feature electrically connected to the first conductive feature.2. The method for forming the interconnect structure as claimed in claim 1 , further comprising:treating an upper surface of the first conductive feature before forming the first blocking layer on the first conductive feature, such that the first blocking layer is selectively formed to cover the upper surface of the first conductive feature and expose the first dielectric layer.3. The method for forming the interconnect structure as claimed in claim 1 , wherein the first blocking layer prevents the first etching stop layer from being formed directly above the first conductive feature.4. The method for forming the interconnect structure as claimed in claim ...

INTERCONNECT STRUCTURE

An interconnect structure is provided. The interconnect structure includes a first via in a first dielectric layer, a first metal line on and electrically connected to the first via, a first etching stop layer over the first dielectric layer, a second metal line over the first etching stop layer, and an encapsulating layer. The encapsulating layer includes a first vertical portion along a sidewall of the first metal line, a horizontal portion along an upper surface of the first etching stop layer, and a second vertical portion along a sidewall of the second metal line. The interconnect structure also includes a second dielectric layer nested within the encapsulating layer.

MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

An integrated circuit device includes a ferroelectric layer that is formed with chlorine-free precursors. This ferroelectric material may be of the composition HFZrO. The ferroelectric layer may be used in a memory device such as a ferroelectric field effect transistor (FeFET). A ferroelectric layer formed with chlorine-free precursors has no chlorine residue. The absence of chlorine ameliorates time-dependent dielectric breakdown (TDDB) and Bias Temperature Instability (BTI).

Method and Structure for Semiconductor Device Having Gate Spacer Protection Layer

A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts. 1. A device comprising:a gate stack disposed over a substrate, the gate stack including a gate electrode layer and a first dielectric layer disposed over the gate electrode layer;a sidewall spacer disposed along a sidewall of the gate stack;a first contact disposed over a source/drain feature disposed in the substrate;a protection layer extending from a sidewall of the first dielectric layer to the source/drain feature; anda second contact extending through the protection layer and the first dielectric layer to the gate electrode such that the second contact physically contacts the protection layer and the first dielectric layer.2. The device of claim 1 , wherein the sidewall spacer has a top surface facing away from the substrate claim 1 , andwherein the second contact physically contacts the top surface of the sidewall spacer.3. The device of claim 1 , wherein the first contact has a top surface facing away from the substrate claim 1 , andwherein the protection layer and the second contact both physically contact the top surface of the first contact.4. The device of claim 1 , further comprising a contact etch stop layer disposed along on the sidewall spacer claim 1 , andwherein the protection layer is disposed over the contact etch stop layer.5. The device of claim 1 , wherein the first dielectric layer ...

Method and Apparatus for Forming Self-Aligned Via with Selectively Deposited Etching Stop Layer

A first layer is located over a substrate. The first layer includes a first dielectric component and a first conductive component. A first etching stop layer is located over the first dielectric component. A metal capping layer is located over the first conductive component. A second etching stop layer is located over the first etching stop layer and over the metal capping layer. A second layer is located over the second etching stop layer. The second layer includes a second dielectric component and a second conductive component. A third conductive component electrically interconnects the second conductive component to the first conductive component. 1. A method , comprising:planarizing upper surfaces of a first interconnect layer that includes a plurality of first conductive elements embedded in a first dielectric layer;selectively forming a metal capping layer on the first conductive elements, wherein the metal capping layer protrudes vertically above the first dielectric layer;selectively depositing a first etching stop layer over the first dielectric layer; anddepositing a second etching stop layer over the first etching stop layer and over the metal capping layer.2. The method of claim 1 , wherein the selectively depositing the first etching stop layer is performed using a selective atomic layer deposition (SALD) process that includes turning on a precursor gas and turning on an oxidant gas in alternating cycles.3. The method of claim 2 , wherein the turning on the precursor gas includes turning on Tetrakisethylmethylaminohafnium (TEMAHf) as the precursor gas.4. The method of claim 2 , wherein the turning on the precursor gas includes turning on tetrakis(ethylmethylamido)zirconium (TEMA-Zr) as the precursor gas.5. The method of claim 2 , wherein the turning on the precursor gas includes turning on Tetrakis(dimethylamido) Aluminum (TDMAA) as the precursor gas.6. The method of claim 2 , wherein the turning on the precursor gas includes turning on Trimethyl ...

METHOD AND APPARATUS FOR FORMING SELF-ALIGNED VIA WITH SELECTIVELY DEPOSITED ETCHING STOP LAYER

A layer of an interconnect structure is formed over a substrate. The layer contains an interlayer dielectric (ILD) material and a metal line disposed in the ILD. A first etching stop layer is formed on the ILD but not on the metal line. The first etching stop layer is formed through a selective atomic layer deposition (ALD) process. A second etching stop layer is formed over the first etching stop layer. A high etching selectivity exists between the first and second etching stop layers. A via is formed to be at least partially aligned with, and electrically coupled to, the metal line. The first etching stop layer prevents the ILD from being etched through during the formation of the via. 1. A semiconductor device , comprising:a first layer of an interconnect structure formed over a substrate, wherein the first layer contains a first dielectric material and a first conductive element disposed in the first dielectric material;a first etching stop layer that is disposed on the first dielectric material of the first layer but not on the first conductive element of the first layer; anda second conductive element disposed over the first layer, wherein the second conductive element is at least partially aligned with, and electrically coupled to, the first conductive element;a second etching stop layer disposed over the first etching stop layer and over the first layer, wherein the second conductive element extends through the second etching stop layer; anda second layer of the interconnect structure disposed over the second etching stop layer, wherein the second layer of the interconnect structure includes a second dielectric material and a third conductive element disposed in the second dielectric material, wherein the third conductive element is disposed over, and electrically coupled to, the second conductive element.2. (canceled)3. The semiconductor device of claim 1 , wherein:{'sub': 'X', 'the first layer is a Minterconnect layer of the interconnect structure;'}{'sub ...

Interconnect Structure and Method of Forming The Same

An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a low-k (LK) dielectric layer over a substrate; a first conductive feature and a second conductive feature in the LK dielectric layer; a first spacer along a first sidewall of the first conductive feature; a second spacer along a second sidewall of the second conductive feature, wherein the second sidewall of the second conductive feature faces the first sidewall of the first conductive feature; an air gap between the first spacer and the second spacer; and a third conductive feature over the first conductive feature, wherein the third conductive feature is connected to the first conductive feature. 1. An interconnect structure , comprising:a first conductive feature and a second conductive feature in a first dielectric layer;a first spacer along a first sidewall of the first conductive feature;a second spacer along a second sidewall of the second conductive feature, wherein the first dielectric layer extends at least in part between the first spacer and the second spacer;an air gap between the first spacer and the second spacer; anda third conductive feature over the first conductive feature, wherein the third conductive feature is electrically connected to the first conductive feature.2. The interconnect structure of claim 1 , wherein a ratio of a height of the first spacer to a distance between the first spacer and the second spacer is at least 2.3. The interconnect structure of claim 1 , wherein the first spacer and the second spacer each comprise a metal oxide claim 1 , a metal nitride claim 1 , a metal carbide claim 1 , a metal boride claim 1 , or a combination thereof.4. The interconnect structure of claim 1 , the first conductive feature comprises:one or more barrier layers comprising W, WN, Ti, Al, TiAl, TiN, TiAlN, Ta, TaC, TaN, TaCN, TaSiN, Mn, Zr, Nb, or Ru; anda cap layer comprising a combination of metal, oxygen, and nitrogen.5 ...

Etchant and Etching Process

A system and method of etching a semiconductor device are provided. Etching solution is sampled and analyzed by a monitoring unit to determine a concentration of components within the etching solution, such as an oxidant concentration. Then, based upon such measurement, a makeup amount of the components may be added be a makeup unit to the etching solution to control the concentration of the components within the etching system.

Etchant and Etching Process

A system and method for manufacturing semiconductor devices is provided. An embodiment comprises using an etchant to remove a portion of a substrate to form an opening with a 45° angle with a major surface of the substrate. The etchant comprises a base, a surfactant, and an oxidant. The oxidant may be hydrogen peroxide. 1. A method for manufacturing a device , the method comprising:masking a substrate with a patterned mask; a base;', 'a surfactant; and', 'an oxidant., 'exposing the substrate through the patterned mask to an etchant, the etchant comprising2. The method of claim 1 , wherein the base is potassium hydroxide.3. The method of claim 2 , wherein the oxidant is HO.4. The method of claim 2 , wherein the oxidant is ozone.5. The method of claim 2 , wherein the oxidant is KMnO.6. The method of claim 3 , wherein the surfactant is sulfonate based.7. The method of claim 3 , wherein the surfactant is alkyl based.8. A semiconductor material etchant comprising:a base;a surfactant; andan oxidant.9. The etchant of claim 8 , wherein the oxidant is HO.10. The etchant of claim 8 , wherein the oxidant is ozone.11. The etchant of claim 8 , wherein the oxidant is KMnO.12. The etchant of claim 8 , wherein the base comprises KOH claim 8 , and the oxidant comprises HO.13. The etchant of claim 8 , wherein the base comprises KOH and the oxidant comprises HO.14. The etchant of claim 13 , wherein the surfactant comprises a sulfonate base.15. The etchant of claim 13 , wherein the surfactant comprises alkyl polysaccharide.16. A method of etching a substrate claim 13 , the method comprising:applying an etchant to a substrate, the etchant comprising a base, a surfactant, and an oxidant;oxidizing a portion of the substrate to change the substrate from hydrophobic to hydrophilic; andforming an opening in the substrate with the etchant.17. The method of claim 16 , wherein the oxidant is HO.18. The method of claim 16 , wherein the opening has a 45° angle with a major surface of the ...

Semiconductor Device Metallization Systems and Methods

Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a mainframe, and a plurality of modules disposed proximate the mainframe. One of the plurality of modules comprises a physical vapor deposition (PVD) module and one of the plurality of modules comprises an ultraviolet light (UV) cure module. 1. A method of processing a semiconductor device , the method comprising:in a first tool, depositing a low-k material on a workpiece;in a second tool, etching the low-k material on the workpiece;in a third tool, performing an ash and clean process on the workpiece; and performing an ultraviolet light cure process on the workpiece in a first module of the plurality of modules;', 'performing a K value recovery process on the workpiece in the first module;', 'removing moisture from the low-k material on the workpiece in the first module; and', 'performing a pre-clean process on the workpiece in the first module., 'in a fourth tool having a plurality of modules2. The method of claim 1 , further comprising partially curing the low-k material etching the low-k material.3. The method of claim 1 , wherein the ultraviolet light cure process is performed at a temperature of about 200 degrees C. to about 400 degrees C. claim 1 , in the presence of an ambient gas of He claim 1 , Ar claim 1 , or N claim 1 , and at a pressure of about 0.1 Torr to about 10 Torr.4. The method of claim 1 , wherein the K value recovery process is performed at a temperature of about 150 degrees C. to about 400 degrees C. claim 1 , in the presence of an ambient gas selected from the group consisting of He claim 1 , Ar claim 1 , N claim 1 , and carbon-containing silane claim 1 , at a pressure of about 1 Torr to about 100 Torr.5. The method of claim 4 , wherein the carbon-containing silane includes a chemical selected from the group consisting of CHSi claim 4 , CHOSi claim 4 , CHNSi claim 4 , CHONSi claim 4 , and ...

STACKED FERROELECTRIC STRUCTURE

The present disclosure relates to an integrated circuit (IC) in which a memory structure comprises a ferroelectric structure without critical-thickness limitations. The memory structure comprises a first electrode and the ferroelectric structure. The ferroelectric structure is vertically stacked with the first electrode and comprises a first ferroelectric layer, a second ferroelectric layer, and a first restoration layer. The second ferroelectric layer overlies the first ferroelectric layer, and the first restoration layer is between and borders the first and second ferroelectric layers. The first restoration layer is a different material type than that of the first and second ferroelectric layers and is configured to decouple crystalline lattices of the first and second ferroelectric layers so the first and second ferroelectric layers do not reach critical thicknesses. A critical thickness corresponds to a thickness at and above which the orthorhombic phase becomes thermodynamically unstable, such that remanent polarization is lost. 116-. (canceled)17. A method for forming an integrated circuit (IC) comprising:depositing a first ferroelectric layer over a substrate, wherein the first ferroelectric layer comprises a first material type;depositing a first restoration layer overlying the first ferroelectric layer and comprising a second material type different than the first material type; anddepositing a second ferroelectric layer overlying the first restoration layer;wherein the first and second ferroelectric layers and the first restoration layer define a memory structure, wherein the first and second ferroelectric layers comprise a plurality of crystalline phases after the depositing of the second ferroelectric layer, and wherein an orthorhombic phase is a majority phase amongst the plurality of crystalline phases.18. The method of claim 17 , wherein the first and second ferroelectric layers are amorphous at deposition claim 17 , wherein the first restoration ...

ANNEALED SEED LAYER TO IMPROVE FERROELECTRIC PROPERTIES OF MEMORY LAYER

In some embodiments, the present disclosure relates to an integrated chip that includes a first conductive structure arranged over a substrate. A memory layer is arranged over the first conductive structure, below a second conductive structure, and includes a ferroelectric material. An annealed seed layer is arranged between the first and second conductive structures and directly on a first side of the memory layer. An amount of the crystal structure that includes an orthorhombic phase is greater than about 35 percent. 1. An integrated chip comprising:a first conductive structure arranged over a substrate;a memory layer arranged over the first conductive structure and comprising a ferroelectric material;a second conductive structure arranged over the memory layer; andan annealed seed layer arranged between the first and second conductive structures and directly on a first side of the memory layer,wherein an amount of the crystal structure of the annealed seed layer that comprises an orthorhombic phase is greater than 35 percent.2. The integrated chip of claim 1 , wherein an amount of the crystal structure of the memory layer that comprises the orthorhombic phase is greater than 35 percent.3. The integrated chip of claim 1 , wherein the first side of the memory layer is a bottommost surface of the memory layer.4. The integrated chip of claim 1 , wherein the first side of the memory layer is a topmost surface of the memory layer.5. The integrated chip of claim 1 , wherein the first conductive structure comprises a first metal claim 1 , and wherein the annealed seed layer comprises the first metal and oxygen.6. The integrated chip of claim 1 , wherein the memory layer comprises a first layer comprising a first metal oxide material claim 1 , and wherein the memory layer comprises a second layer arranged over the first layer and comprising a second metal oxide material.7. The integrated chip of claim 1 , further comprising:an active layer arranged over the memory layer, ...

THIN FILM TRANSISTOR INCLUDING A COMPOSITIONALLY-MODULATED ACTIVE REGION AND METHODS FOR FORMING THE SAME

A thin film transistor includes an active layer and at least one gate stack. The active layer may be formed using multiple iterations of a unit layer stack deposition process, which includes an acceptor-type oxide deposition process and a post-transition metal oxide deposition process. A surface of each gate dielectric within the at least one gate stack contacts a surface of a respective layer of the oxide of the acceptor-type element so that leakage current of the active layer may be minimized. A source electrode and a drain electrode may contact an oxide layer providing lower contact resistance such as a layer of the post-transition metal oxide or a zinc oxide layer within the active layer. 1. A thin film transistor comprising:a bottom gate electrode embedded in an insulating layer;a bottom gate dielectric located on a top surface of the bottom gate electrode; andan active layer located over the bottom gate dielectric and having a vertical compositional modulation,wherein the active layer comprises oxygen, an acceptor-type element selected from Ga and W, and a heavy post-transition metal element selected from In and Sn,wherein a vertical compositional profile of an atomic percentage of the acceptor-type element between a bottommost surface of the active layer and a topmost surface of the active layer has N local peaks in which N is an integer greater than 2, andwherein a bottommost peak selected from the N peaks is higher than any of (N−2) intermediate peaks located between the bottommost peak and a topmost peak selected from the N peaks.2. The thin film transistor of claim 1 , wherein:a vertical compositional profile of an atomic percentage of the heavy post-transition metal element between the bottommost surface of the active layer and the topmost surface of the active layer has (N−1) local peaks;the vertical compositional profile of the atomic percentage of the heavy post-transition metal element has N local minima; anda bottommost local minimum of the atomic ...

SELF-ALIGNMENT DUE TO WETTABILITY DIFFERENCE OF AN INTERFACE

Some embodiments relate to a method of processing a workpiece. The workpiece includes a first surface region having a first wettability coefficient, and a second surface region having a second wettability coefficient that differs from the first wettability coefficient. A liquid, which corresponds to an optical structure, is dispensed on the first and second surface regions of the workpiece, wherein the liquid self-aligns to the second surface region due to the difference between the first and second wettability coefficients. The self-aligned liquid is hardened to form the optical structure. 1. A method , comprising:providing a planar workpiece surface that includes a first surface region having a first wettability coefficient and a second surface region having a second wettability coefficient, wherein the first and second surface regions are co-planar and where second wettability coefficient is different from the first wettability coefficient, wherein the second surface region includes first and second sub-region surfaces which are separated from one another by the first surface region, and wherein the first and second sub-region surfaces have first and second lengths, respectively, wherein the first length is different from the second length;dispensing a liquid corresponding to an optical structure on the first and second surface regions of the workpiece, wherein the liquid self-aligns to the first and second sub-region surfaces due to the difference between the first and second wettability coefficients; andhardening the self-aligned liquid to form a first optical structure on the first sub-region surface and a second optical structure on the second sub-region surface.2. The method of claim 1 , wherein the first and second surface regions are formed by lithography claim 1 , and wherein dissolution of the hardened claim 1 , first and second optical structures is non-photosensitive.3. The method of claim 1 , wherein the first optical structure is an optical lens that ...

Schemes for Forming Barrier Layers for Copper in Interconnect Structures

A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided. 1. A semiconductor device comprising:a conductive material embedded within a dielectric layer, the conductive material comprising a first element;a first barrier layer lining sidewalls and a bottom surface of the conductive material, the first barrier layer comprising a second element different from the first element; and a first material in physical contact with the conductive material, wherein the first material comprises the first element and a third element, the third element being different from the first element and the second element; and', 'a second material in physical contact with the first barrier layer, wherein the second material comprises the second element and the third element., 'a capping layer over the conductive material and the first barrier layer but not extending over the dielectric layer, the capping layer comprising2. The semiconductor device of claim 1 , wherein the third element is silicon.3. The semiconductor device of claim 1 , wherein the capping layer extends into a recess between the conductive material and the dielectric layer.4. The semiconductor device of claim 3 , wherein the recess has a first depth of greater than about 50 {acute over (Å)}.5. The semiconductor device of claim 3 , wherein the recess has a first depth of greater than about 5% of a thickness of the conductive material.6. The semiconductor device of claim 1 , ...

SELECTIVE DEPOSITION FOR INTEGRATED CIRCUIT INTERCONNECT STRUCTURES

Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess. 1. A structure , comprising:a first conductive line and a second conductive line extending along a first direction;a first dielectric layer sandwiched between the first conductive line and the second conductive line along a second direction perpendicular to the first direction;a catalyst layer disposed on the first dielectric layer;a dielectric alignment feature disposed directly on the catalyst layer;an etch stop layer conformally extending along a top surface of the first conductive line, a sidewall of the catalyst layer, a sidewall of the dielectric alignment feature, and a top surface of the dielectric alignment feature; anda second dielectric layer over the etch stop layer.2. The structure of claim 1 , wherein the first conductive line comprises:a first liner in contact with the first dielectric layer;a fill material disposed over the first liner; anda first line cap disposed on the first liner and the fill material.3. The structure of claim 2 ,wherein the first liner ...

INTERCONNECT STRUCTURE INCLUDING A CONTINUOUS CONDUCTIVE BODY

Some embodiments of the present disclosure relate to an interconnect structure for connecting devices of a semiconductor substrate. The interconnect structure includes a dielectric layer over the substrate and a continuous conductive body passing through the dielectric layer. The continuous conductive body is made up of a lower body region and an upper body region. The lower body region has a first width defined between opposing lower sidewalls of the continuous conductive body, and the upper body region has a second width defined between opposing upper sidewalls of the continuous conductive body. The second width is less than the first width. A barrier layer separates the continuous conductive body from the dielectric layer. 1. An interconnect structure for connecting devices of a semiconductor substrate , comprising:a dielectric layer over the substrate;a continuous conductive body passing through the dielectric layer and made up of a lower body region and an upper body region, wherein the lower body region has a first width defined between opposing lower sidewalls of the continuous conductive body, and wherein the upper body region has a second width defined between opposing upper sidewalls of the continuous conductive body, wherein the second width is less than the first width; anda barrier layer separating the continuous conductive body from the dielectric layer.2. The interconnect structure of claim 1 , wherein the continuous conductive body is made of copper or a copper alloy.3. The interconnect structure of claim 2 , wherein an alloy component in the copper alloy comprises Mg claim 2 , Al claim 2 , Cr claim 2 , Mn claim 2 , or Ti.4. The interconnect structure of claim 3 , wherein the alloy component has a concentration ranging from about 0.5% to about 50% of the copper alloy by weight.54. The interconnect structure of wherein the dielectric layer has a dielectric constant of less than .6. The interconnect structure of claim 1 , wherein the lower body region ...

FERROELECTRIC MEMORY DEVICE, MANUFACTURING METHOD OF THE FERROELECTRIC MEMORY DEVICE AND SEMICONDUCTOR CHIP

A ferroelectric memory device, a manufacturing method of the ferroelectric memory device and a semiconductor chip are provided. The ferroelectric memory device includes a gate electrode, a ferroelectric layer, a channel layer, first and second blocking layers, and source/drain electrodes. The ferroelectric layer is disposed at a side of the gate electrode. The channel layer is capacitively coupled to the gate electrode through the ferroelectric layer. The first and second blocking layers are disposed between the ferroelectric layer and the channel layer. The second blocking layer is disposed between the first blocking layer and the channel layer. The first and second blocking layers comprise a same material, and the second blocking layer is further incorporated with nitrogen. The source/drain electrodes are disposed at opposite sides of the gate electrode, and electrically connected to the channel layer. 1. A ferroelectric memory device , comprising:a gate electrode;a ferroelectric layer, disposed at a side of the gate electrode;a channel layer, capacitively coupled to the gate electrode through the ferroelectric layer;a first blocking layer and a second blocking layer, disposed between the ferroelectric layer and the channel layer, wherein the second blocking layer is disposed between the first blocking layer and the channel layer, the first and second blocking layers comprise a same material, and the second blocking layer is further incorporated with nitrogen; andsource/drain electrodes, disposed at opposite sides of the gate electrode, and electrically connected to the channel layer.2. The ferroelectric memory device according to claim 1 , wherein the same material contained in the first and second blocking layers results in band offset at an interface of the channel layer and the first and second blocking layers.3. The ferroelectric memory device according to claim 1 , wherein the same material contained in the first and second blocking layers comprises an oxide ...

CARRIER BARRIER LAYER FOR TUNING A THRESHOLD VOLTAGE OF A FERROELECTRIC MEMORY DEVICE

The present disclosure relates to an integrated circuit (IC) chip including a memory cell with a carrier barrier layer for threshold voltage tunning. The memory cell may, for example, include a gate electrode, a ferroelectric structure, and a semiconductor structure. The semiconductor structure is vertically stacked with the gate electrode and the ferroelectric structure, and the ferroelectric structure is between the gate electrode and the semiconductor structure. A pair of source/drain electrodes is laterally separated and respectively on opposite sides of the gate electrode, and a carrier barrier layer separates the source/drain electrodes from the semiconductor structure. 111-. (canceled)12. A method for forming an integrated circuit (IC) chip comprising:forming a gate electrode over a substrate;forming a ferroelectric structure over the gate electrode;forming a semiconductor structure over the ferroelectric structure;forming a carrier barrier layer over the substrate, wherein the carrier barrier layer comprises a pair of barrier segments respectively on opposite sides of the gate electrode; andforming a pair of source/drain electrodes directly over the pair of barrier segments of the carrier barrier layer.13. The method of claim 12 , wherein forming the carrier barrier layer comprises:forming a passivation layer over the semiconductor structure;etching a pair of openings into the passivation layer to define inner sidewalls of the passivation layer; anddepositing the carrier barrier layer lining and partially filling the pair of openings, wherein the carrier barrier layer is along the inner sidewalls of the passivation layer.14. The method of claim 13 , wherein forming the carrier barrier layer further comprises:thinning down the passivation layer until a top surface of the carrier barrier layer is level with a top surface of the passivation layer continuously from a first sidewall of the passivation layer to a second sidewall of the passivation layer opposing ...

Selective Deposition for Integrated Circuit Interconnect Structures

Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess.

Lithography Using High Selectivity Spacers for Pitch Reduction

A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer. 1. A method for patterning a semiconductor device comprising:patterning a dummy layer over a hard mask to form one or more dummy lines;forming a sidewall aligned spacer conformably over the one or more dummy lines and the hard mask;forming a first reverse material layer over the sidewall aligned spacer, wherein a material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer;forming a first photoresist over the first reverse material layer;patterning the first photoresist;selectively etching the first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched;removing the one or more dummy lines; andpatterning the hard mask using the sidewall aligned spacer and the first reverse material layer as a mask.2. The method of claim 1 , wherein the material used for forming the sidewall aligned spacer is titanium nitride or titanium oxide.3. The method of claim 1 , wherein the material used for forming the first reverse material layer is spin on glass (SOG).4. The method of claim 1 , wherein the patterning the dummy layer comprises ...

Schemes for Forming Barrier Layers for Copper in Interconnect Structures

A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided. 1. A semiconductor device comprising:a dielectric layer over a substrate;a conductive wire embedded within the dielectric layer, the conductive wire comprising a conductive material;a first barrier layer between the dielectric layer and the conductive wire; anda capping layer over the conductive wire, the capping layer comprising the conductive material and a carbon-containing silane derivative.2. The semiconductor device of claim 1 , wherein the conductive material is copper.3. The semiconductor device of claim 1 , wherein the capping layer does not extend over the dielectric layer.4. The semiconductor device of claim 1 , wherein the capping layer extends into a first region between the conductive wire and the dielectric layer claim 1 , the first region being over the first barrier layer.5. The semiconductor device of claim 1 , wherein the capping layer is over the first barrier layer.6. The semiconductor device of claim 5 , wherein the dielectric layer has a first top surface that is planar with a second top surface of the conductive wire.7. The semiconductor device of claim 1 , wherein the first barrier layer comprises a material selected from the group consisting essentially of cobalt claim 1 , nickel claim 1 , and combinations thereof.8. The semiconductor device of claim 1 , wherein the capping layer is terminated with nitrogen-containing terminals.9. The ...

INTERCONNECT STRUCUTRE WITH PROTECTIVE ETCH-STOP

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip may comprise a first metal line disposed over a substrate. A via may be disposed directly over a top of the first metal line and the via may comprise a first lower surface and a second lower surface above the first lower surface. A first dielectric structure may be disposed laterally adjacent to the first metal line and may be disposed along a sidewall of the first metal line. A first protective etch-stop structure may be disposed directly over a top of the first dielectric structure and the first protective etch-stop structure may vertically separate the second lower surface of the via from the top of the first dielectric structure. 1. A method for forming an integrated chip , the method comprising:forming a pair of dielectric structures over a substrate and on opposite sides of a first metal line, the pair of dielectric structures comprising a first dielectric;selectively forming a blocking layer directly over a top surface of the first metal line;selectively forming a pair of protective etch-stop structures on top surfaces of the pair of dielectric structures, the pair of protective etch-stop structures comprising a second dielectric, different from the first dielectric;removing the blocking layer from directly over the top surface of the first metal line;depositing an interlayer dielectric (ILD) layer over the pair of protective etch-stop structures and over the first metal line;etching the ILD layer to uncover the top surface of the first metal line, wherein the etching is selective to the ILD layer, and wherein the pair of protective etch-stop structures remain on the top surfaces of the pair of dielectric structures throughout the etching; andforming a metal via directly over the first metal line, wherein the metal via is separated from a first dielectric structure of the pair of dielectric structures by a first protective etch-stop structure of the pair of ...

CAPPING LAYER OVERLYING DIELECTRIC STRUCTURE TO INCREASE RELIABILITY

Some embodiments relate to a method for forming an integrated chip, the method includes forming a first conductive wire and a second conductive wire over a substrate. A dielectric structure is formed laterally between the first conductive wire and the second conductive wire. The dielectric structure comprises a first dielectric liner, a dielectric layer disposed between opposing sidewalls of the first dielectric liner, and a void between an upper surface of the first dielectric liner and a lower surface of the dielectric layer. A dielectric capping layer is formed along an upper surface of the dielectric structure. Sidewalls of the dielectric capping layer are aligned with sidewalls of the dielectric structure. 1. A method for forming an integrated chip , the method comprising:forming a first conductive wire and a second conductive wire over a substrate;forming a dielectric structure laterally between the first conductive wire and the second conductive wire, wherein the dielectric structure comprises a first dielectric liner, a dielectric layer disposed between opposing sidewalls of the first dielectric liner, and a void between an upper surface of the first dielectric liner and a lower surface of the dielectric layer; andforming a dielectric capping layer along an upper surface of the dielectric structure, wherein sidewalls of the dielectric capping layer are aligned with sidewalls of the dielectric structure.2. The method of claim 1 , wherein forming the dielectric capping layer comprises:depositing an inhibitor layer on the first and second conductive wires; andselectively depositing the dielectric capping layer on the upper surface of the dielectric structure with the inhibitor layer in place, wherein the inhibitor layer prevents deposition of the dielectric capping layer on the first and second conductive wires.3. The method of claim 2 , wherein the dielectric capping layer is laterally offset from the first and second conductive wires.4. The method of claim 1 ...

METHOD AND SYSTEM FOR FABRICATION SEMICONDUCTOR DEVICE

A method for fabrication a semiconductor device and a system utilizing the same are provided. In the method for fabrication the semiconductor device, at first, a semiconductor structure having a metal conducting structure is provided. Next, a dielectric layer is deposited over the metal conducting structure. Then, an etching process is performed on the dielectric layer by using a fluorine-containing gas so as to form an opening, in which fluorine-containing compounds are formed on a surface of the opening during the etching process. And then, a pre-cleaning process is performed by using UV radiation so as to remove the fluorine-containing compounds. After the pre-cleaning process is performed, a cleaning process is performed to clean the surface of the opening. 1. A method for fabricating a semiconductor device , wherein the method comprises:providing a semiconductor structure with a metal conducting structure;depositing a dielectric layer over the metal conducting structure;performing an etching process on the dielectric layer by using a fluorine-containing gas so as to form an opening, wherein fluorine-containing compounds are formed on a surface of the opening during the etching process;performing a pre-cleaning process by using UV radiation so as to remove the fluorine-containing compounds; andperforming a cleaning process to clean the surface of the opening after the pre-cleaning process is performed.2. The method of claim 1 , wherein the dielectric layer is formed from a low-k material.3. The method of claim 1 , wherein the UV radiation is illuminated for at least 30 seconds.4. The method of claim 3 , wherein a wavelength of the UV radiation is in a range substantially from 200 nm to 250 nm.5. The method of claim 1 , wherein after the pre-cleaning process is performed claim 1 , the method further comprises:filling a plurality of surface pores of the opening with a precursor followed by the cleaning process.6. The method of claim 5 , wherein the precursor ...

Light Coupling Device and Methods of Forming Same

An embodiment is a semiconductor device comprising an optical device over a first substrate, a vertical waveguide on a top surface of the optical device, the vertical waveguide having a first refractive index, and a capping layer over the vertical waveguide, the capping layer configured to be a lens for the vertical waveguide and the capping layer having a second refractive index. 1. A device comprising:an optical device over a first substrate;a vertical waveguide on a top surface of the optical device, the vertical waveguide having a longitudinal axis that is substantially orthogonal to a top surface of the substrate; anda lens layer over the vertical waveguide, the lens layer encapsulating the vertical waveguide, the optical device, and at least a portion of the top surface of the first substrate.2. The device of claim 1 , wherein the vertical waveguide comprises a polymer and the lens layer comprises a polymer.3. The device of claim 1 , wherein the vertical waveguide has a first refractive index and wherein the lens layer has second refractive index claim 1 , the second refractive index being different than the first refractive index.4. The device of claim 3 , wherein the first refractive index is greater than the second refractive index.5. The device of claim 1 , wherein a top surface of the lens layer forms a dome over a top surface of the first substrate claim 1 , the top surface of the lens layer being over a top surface of the vertical waveguide.6. The device of further comprising:a first redistribution layer over the first substrate;a first wire bond coupling the first redistribution layer and the optical device; anda second redistribution layer over the first substrate, the optical device being coupled to the second redistribution layer.7. The device of claim 6 , wherein the first wire bond is surrounded by the lens layer.8. The device of further comprising:the first substrate being mounted to a second substrate;a second wire bond coupling the second ...

Method and Structure for Semiconductor Device Having Gate Spacer Protection Layer

A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts. 1. A device comprising:a first gate stack disposed over a substrate, the first gate stack including a gate electrode layer;a first sidewall spacer disposed along a first sidewall of the first gate stack and a second sidewall spacer disposed along a second sidewall of the first gate stack, the second sidewall of the first gate stack being opposite the first sidewall of the first gate stack, the first sidewall spacer having a top surface facing away from the substrate;a first dielectric layer disposed between the first sidewall spacer and the second sidewall spacer, the first dielectric layer having a bottom surface facing the substrate and disposed at a lower position over the substrate than the top surface of the first sidewall spacer;a protection layer disposed along a sidewall of the first dielectric layer such that the protection layer physically contacts the sidewall of the first dielectric layer; anda first contact extending through the protection layer and the first dielectric layer to the gate electrode layer such that the first contact physically contacts the protection layer, the first dielectric layer and the first sidewall spacer.2. The device of claim 1 , wherein the protection layer is disposed directly on a top surface of the second sidewall spacer such that the protection layer physically ...

Dielectric capping structure overlying a conductive structure to increase stability

Some embodiments relate to a semiconductor structure including a first inter-level dielectric (ILD) structure overlying a substrate. A conductive contact directly overlies the substrate and is disposed within the first ILD structure. A conductive wire directly overlies the conductive contact. A conductive capping layer overlies the conductive wire such that the conductive capping layer continuously extends along an upper surface of the conductive wire. A second ILD structure overlies the conductive capping layer. The second ILD structure is disposed along opposing sides of the conductive wire. A pair of air-gaps are disposed within the second ILD structure. The conductive wire is spaced laterally between the pair of air-gaps. A dielectric capping layer is disposed along an upper surface of the conductive capping layer. The dielectric capping layer is spaced laterally between the pair of air-gaps and is laterally offset from an upper surface of the first ILD structure.

CAPPING LAYER OVERLYING DIELECTRIC STRUCTURE TO INCREASE RELIABILITY

Some embodiments relate to a semiconductor structure including an inter-level dielectric (ILD) layer overlying a substrate. A conductive via is disposed within the ILD layer. A plurality of conductive wires overlie the ILD layer. The plurality of conductive wires includes a first conductive wire laterally offset a second conductive wire. A dielectric structure is disposed laterally between the first and second conductive wires. The dielectric structure includes a first dielectric liner, a dielectric layer, and an air-gap. The air-gap is disposed between an upper surface of the first dielectric liner and a lower surface of the dielectric layer. A dielectric capping layer is disposed along an upper surface of the dielectric structure. The dielectric capping layer continuously extends between opposing sidewalls of the dielectric structure and is laterally offset from the plurality of conductive wires. 1. A semiconductor structure comprising:an inter-level dielectric (ILD) layer overlying a substrate;a conductive via disposed within the ILD layer;a plurality of conductive wires overlying the ILD layer, wherein the plurality of conductive wires includes a first conductive wire laterally offset a second conductive wire, wherein the first conductive wire directly overlies the conductive via;a dielectric structure disposed laterally between the first and second conductive wires, wherein the dielectric structure comprises a first dielectric liner, a dielectric layer, and an air-gap, wherein the air-gap is disposed between an upper surface of the first dielectric liner and a lower surface of the dielectric layer; anda dielectric capping layer disposed along an upper surface of the dielectric structure, wherein the dielectric capping layer continuously extends between opposing sidewalls of the dielectric structure, and wherein the dielectric capping layer is laterally offset from the plurality of conductive wires.2. The semiconductor structure of claim 1 , wherein a dielectric ...

INTERCONNECT STRUCTURE THAT AVOIDS INSULATING LAYER DAMAGE AND METHODS OF MAKING THE SAME

A method for forming an interconnect structure includes forming an insulating layer on a substrate. A damascene opening is formed through a thickness portion of the insulating layer. A diffusion barrier layer is formed to line the damascene opening. A conductive layer is formed overlying the diffusion barrier layer to fill the damascene opening. A carbon-containing metal oxide layer is formed on the conductive layer and the insulating layer.

Semiconductor Devices and Methods of Forming Same

A semiconductor device structure and methods of forming the same are disclosed. An embodiment is a method of forming a semiconductor device, the method comprising forming a first conductive line over a substrate, and conformally forming a first dielectric layer over a top surface and a sidewall of the first conductive line, the first dielectric layer having a first porosity percentage and a first carbon concentration. The method further comprises forming a second dielectric layer on the first dielectric layer, the second dielectric layer having a second porosity percentage and a second carbon concentration, the second porosity percentage being different from the first porosity percentage, and the second carbon concentration being less than the first carbon concentration.

INTERCONNECT STRUCTURES INCLUDING AIR GAPS

A method and structure for forming a barrier-free interconnect layer includes patterning a metal layer disposed over a substrate to form a patterned metal layer including one or more trenches. In some embodiments, the method further includes selectively depositing a barrier layer on metal surfaces of the patterned metal layer within the one or more trenches. In some examples, and after selectively depositing the barrier layer, a dielectric layer is deposited within the one or more trenches. Thereafter, the selectively deposited barrier layer may be removed to form air gaps between the patterned metal layer and the dielectric layer. 1. A device , comprising:a substrate including one or more semiconductor devices;a metal interconnect layer disposed over the substrate and including a plurality of metal regions interposed by a plurality of dielectric layer regions, wherein each of the plurality of metal regions is separated from an adjacent dielectric layer region of the plurality of dielectric layer regions by an air gap; anda catalyst layer interposing the substrate and each of the plurality of dielectric layer regions.2. The device of claim 1 , wherein the metal interconnect layer provides an electrical connection to the one or more semiconductor devices.3. The device of claim 1 , wherein the catalyst layer includes a trimethylaluminium (TMA) layer.4. The device of claim 1 , wherein the plurality of metal regions includes cobalt (Co) or copper (Cu) regions claim 1 , and wherein the plurality of dielectric layer regions includes SiOx claim 1 , SiCOH claim 1 , or boron carbide.5. The device of claim 1 , wherein the metal interconnect layer includes a metal line or metal via of a multi-level metal interconnect network.6. The device of claim 1 , wherein each of the plurality of metal regions have a first trapezoidal shape claim 1 , and wherein each of the plurality of dielectric layer regions have a second trapezoidal shape with an orientation that is inverted with ...

SYSTEM AND METHOD FOR DARK FIELD INSPECTION

The present disclosure provides a method for fabricating a semiconductor structure. The method comprises providing a substrate and a patterned layer formed on the substrate, one or more overlay marks being formed on the patterned layer; performing a pre-film-formation overlay inspection using a bright field (BF) inspection tool to receive a pre-film-formation data on the one or more overlay marks on the patterned layer; forming one or more layers on the patterned layer; performing a post-film-formation overlay inspection using a dark field (DF) inspection tool to receive a post-film-formation data on the one or more overlay marks underlying the one or more layers; and determining whether the pre-film-formation data matches the post-film-formation data. 1. A method for fabricating a semiconductor structure , comprising:providing a substrate and a patterned layer formed on the substrate, one or more overlay marks being formed on the patterned layer;performing a pre-film-formation overlay inspection using a bright field (BF) inspection tool to receive a pre-film-formation data on the one or more overlay marks on the patterned layer;forming one or more layers on the patterned layer;performing a post-film-formation overlay inspection using a dark field (DF) inspection tool to receive a post-film-formation data on the one or more overlay marks underlying the one or more layers; anddetermining whether the pre-film-formation data matches the post-film-formation data.2. The method of claim 1 , before the performing the post-film-formation overlay inspection using the DF inspection tool claim 1 , further comprising:performing the post-film-formation overlay inspection using the BF inspection tool.3. The method of claim 2 , further comprising:determining whether a number of the overlay marks in the pre-film-formation data matches a number of the overlay marks in the post-film-formation data measured using the BF inspection tool; andwhen the number of the overlay marks in the ...

Semiconductor Device Metallization Systems and Methods

Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a mainframe, and a plurality of modules disposed proximate the mainframe. One of the plurality of modules comprises a physical vapor deposition (PVD) module and one of the plurality of modules comprises an ultraviolet light (UV) cure module. 1. A method of processing a semiconductor device , the method comprising:placing in a metallization system a workpiece having formed thereon a low-k dielectric layer;at least partially curing the low-k dielectric layer in the metallization system using an ultraviolet (UV) light;depositing a layer on the low-k dielectric layer using a physical vapor deposition (PVD) in the metallization system after at least partially curing the low-k dielectric layer; andcuring the low-k dielectric layer using the UV light after depositing the layer.2. The method of claim 1 , further comprising moving the semiconductor device from a UV cure module to a PVD deposition module using robotic device located within the metallization system.3. The method of claim 1 , wherein the step of at least partially curing the low-k dielectric layer includes partially curing the low-k dielectric layer in a UV cure module of the metallization system.4. The method of claim 1 , wherein the step of at least partially curing the low-k dielectric layer includes fully curing the low-k dielectric layer in a UV cure module of the metallization system.5. The method of claim 1 , wherein the step of at least partially curing the low-k dielectric layer in the metallization system and the step of curing the low-k dielectric layer occur in a same UV cure module of the metallization system.6. The method of claim 1 , wherein the step of depositing a layer on the low-k dielectric layer includes forming a barrier liner in a trench formed in the low-k dielectric layer.7. The method of claim 6 , further comprising forming in the ...

Interconnect Structure and Method of Forming the Same

An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a low-k (LK) dielectric layer over a substrate; a first conductive feature and a second conductive feature in the LK dielectric layer; a first spacer along a first sidewall of the first conductive feature; a second spacer along a second sidewall of the second conductive feature, wherein the second sidewall of the second conductive feature faces the first sidewall of the first conductive feature; an air gap between the first spacer and the second spacer; and a third conductive feature over the first conductive feature, wherein the third conductive feature is connected to the first conductive feature. 1. An interconnect structure , comprising:a low-k (LK) dielectric layer over a substrate;a first conductive feature and a second conductive feature in the LK dielectric layer;a first spacer along a first sidewall of the first conductive feature, wherein the first spacer has a substantially rectangular shape;a second spacer along a second sidewall of the second conductive feature, wherein the second sidewall of the second conductive feature faces the first sidewall of the first conductive feature, and wherein the second spacer has a substantially rectangular shape;an air gap between the first spacer and the second spacer; anda third conductive feature over the first conductive feature, wherein the third conductive feature is connected to the first conductive feature.2. The interconnect structure of claim 1 , wherein the substrate comprises a lower LK dielectric layer.3. The interconnect structure of claim 1 , wherein an aspect ratio is a height of the first spacer or the second spacer divided by a spacing between the first spacer and the second spacer claim 1 , the aspect ratio being greater than or equal to about 2.4. The interconnect structure of claim 1 , wherein the first spacer or the second spacer comprises a metal compound.5. The ...

Package Structure and Methods of Forming Same

A semiconductor device, a package structure, and methods of forming the same are disclosed. An embodiment is a semiconductor device comprising a first optical device over a first substrate, a vertical waveguide on a top surface of the first optical device, and a second substrate over the vertical waveguide. The semiconductor device further comprises a lens capping layer on a top surface of the second substrate, wherein the lens capping layer is aligned with the vertical waveguide, and a second optical device over the lens capping layer. 1. A semiconductor device comprising:a first optical device over a first substrate;a vertical waveguide on a top surface of the first optical device;a second substrate over the vertical waveguide;a lens capping layer on a top surface of the second substrate, wherein the lens capping layer is aligned with the vertical waveguide; anda second optical device over the lens capping layer.2. The semiconductor device of claim 1 , wherein the vertical waveguide comprises a polymer and the lens capping layer comprises a polymer.3. The semiconductor device of claim 1 , wherein the second substrate is a silicon substrate.4. The semiconductor device of claim 1 , wherein a top surface of the lens capping layer forms a dome on the top surface of the second substrate.5. The semiconductor device of claim 1 , wherein the vertical waveguide has a longitudinal axis claim 1 , the longitudinal axis being substantially orthogonal to a top surface of the first substrate.6. The semiconductor device of claim 1 , wherein a bottom surface of the second substrate is in direct contact with a top surface of the vertical waveguide.7. The semiconductor device of further comprising:a first die bonded to the first substrate; anda second die bonded to the second substrate.8. The semiconductor device of further comprising:a first redistribution layer over the first substrate;a wire bond coupling the first redistribution layer and a top surface of the first optical ...

Light Coupling Device and Methods of Forming Same

An embodiment is a semiconductor device comprising an optical device over a first substrate, a vertical waveguide on a top surface of the optical device, the vertical waveguide having a first refractive index, and a capping layer over the vertical waveguide, the capping layer configured to be a lens for the vertical waveguide and the capping layer having a second refractive index.

High Boiling Temperature Solvent Additives for Semiconductor Processing

A method for forming an interconnect structure includes forming a patterned layer over a substrate, the patterned layer having an opening therein. A dielectric material is filled in the opening. The dielectric material has a precursor and a solvent, the solvent having a boiling point temperature greater than a precursor cross-linking temperature. A thermal treatment is performed on the dielectric material to form a dielectric layer. 1. A method for forming a dielectric structure , the method comprising:forming a patterned layer over a substrate, the patterned layer having an opening therein;filling a dielectric material in the opening, the dielectric material having a precursor and a solvent, the solvent having a boiling point temperature greater than a precursor cross-linking temperature; andperforming a thermal treatment of the dielectric material, wherein the thermal treatment induces a cross-linking reaction.2. The method of claim 1 , wherein the patterned layer is a conductive layer.3. The method of claim 1 , wherein the dielectric material comprises a low-k dielectric material claim 1 , a porous low-k material claim 1 , a spin-on-glass material claim 1 , or a spin-on-polymer material.4. The method of claim 1 , wherein the solvent comprises benzonitrile (CHN) claim 1 , benzyl alcohol (CHO) claim 1 , propyl benzoate (CHO) claim 1 , ethyl benzoate (CHO) claim 1 , diethylene glycol (CHO) claim 1 , 3-phenyl-1-propanol (CHO) claim 1 , N-Methyl-2-pyrrolidone (NMP) (CHNO) claim 1 , or combinations thereof.5. The method of claim 1 , wherein the filling the dielectric material into the opening comprises depositing the dielectric material using a spin-on coating process.6. The method of claim 1 , wherein the solvent has a boiling point temperature above about 200° C.7. The method of claim 1 , wherein an amount of solvent in the dielectric material is greater than about 5% by weight of the dielectric material.8. The method of claim 1 , wherein the precursor cross-linking ...

Semiconductor Device Metallization Systems and Methods

Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a mainframe, and a plurality of modules disposed proximate the mainframe. One of the plurality of modules comprises a physical vapor deposition (PVD) module and one of the plurality of modules comprises an ultraviolet light (UV) cure module. 1. A metallization system for semiconductor devices , comprising:a mainframe; anda plurality of modules disposed proximate the mainframe, wherein one of the plurality of modules comprises a physical vapor deposition (PVD) module and one of the plurality of modules comprises an ultraviolet light (UV) cure module.2. The metallization system according to claim 1 , wherein the UV cure module comprises a UV light source comprising a bulb type selected from the group consisting essentially of H claim 1 , H+ claim 1 , D claim 1 , V claim 1 , and combinations thereof.3. The metallization system according to claim 1 , further comprising a transport area proximate the mainframe and a load port proximate the transport area claim 1 , wherein the load port includes a support for a wafer carrier claim 1 , and wherein the transport area includes a robotics device adapted to move a wafer comprising a semiconductor device from the wafer carrier into the mainframe.4. The metallization system according to claim 1 , wherein the PVD module includes equipment adapted to perform a PVD process claim 1 , and wherein the PVD module also includes equipment adapted to perform a process selected from the group consisting essentially of: a degas process claim 1 , an atomic layer deposition (ALD) process claim 1 , a chemical vapor deposition (CVD) process claim 1 , an ultra-violet light (UV) exposure process claim 1 , a pre-cleaning process claim 1 , and combinations thereof.5. A method of processing a semiconductor device claim 1 , the method comprising:placing a workpiece in a metallization system, the ...

Method of Fabrication Polymer Waveguide

A method of fabricating a waveguide device is disclosed. The method includes providing a substrate having an elector-interconnection region and a waveguide region and forming a patterned dielectric layer and a patterned redistribution layer (RDL) over the substrate in the electro-interconnection region. The method also includes bonding the patterned RDL to a vertical-cavity surface-emitting laser (VCSEL) through a bonding stack. A reflecting-mirror trench is formed in the substrate in the waveguide region, and a reflecting layer is formed over a reflecting-mirror region inside the waveguide region. The method further includes forming and patterning a bottom cladding layer in a wave-tunnel region inside the waveguide region and forming and patterning a core layer and a top cladding layer in the waveguide region. 1. A device comprising:a substrate having a first region and a second region;a conductive layer disposed over the substrate in the first region;a passivation layer disposed over the conductive layer in the first region;a reflecting layer that includes a first portion disposed over the passivation layer in the first region and a second portion disposed over the second region of the substrate;a first cladding layer disposed over the reflecting layer in the second region;a core layer disposed over the first and second portions of the reflecting layer such that the core layer prevent the first and second portions of the reflecting layer from interfacing with each other, wherein the core layer includes polymer; anda second cladding layer disposed over core layer in the second region.2. The device of claim 1 , wherein the core layer physically contacts the substrate claim 1 , andwherein the reflecting layer physically contacts the substrate.3. The device of claim 2 , wherein the substrate includes silicon.4. The device of claim 1 , wherein at least one of the first cladding layer and the second cladding layer includes polymer.5. The device of claim 1 , wherein the ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a first metal wiring layer, an interlayer insulating layer formed over the first metal layer, a second metal wiring structure embedded in the interlayer dielectric layer and connected to the first metal wiring layer, and an etch-stop layer disposed between the first metal wiring and the first interlayer dielectric layer. The etch-stop layer includes one or more sub-layers. The etch-stop layer includes a first sub-layer made of an aluminum-based insulating material, hafnium oxide, zirconium oxide or titanium oxide. 1. A semiconductor device , comprising:a first metal wiring layer;an interlayer dielectric layer formed over the first metal layer;a second metal wiring structure embedded in the interlayer dielectric layer and connected to the first metal wiring layer; andan etch-stop layer disposed between the first metal wiring and the interlayer dielectric layer, the etch-stop layer including one or more sub-layers,wherein the etch-stop layer includes a first sub-layer made of at least one selected from the group consisting of aluminum oxy-carbide, aluminum oxy-nitride having a non-uniform nitrogen concentration in a thickness direction, hafnium oxide, zirconium oxide and titanium oxide.2. The semiconductor device of claim 1 , wherein:the first sub-layer is made of aluminum oxy-carbide and aluminum oxy-nitride having a non-uniform nitrogen concentration in a thickness direction.3. The semiconductor device of claim 1 , wherein:the etch-stop layer further includes a second sub-layer made of a silicon based insulating material,the first sub-layer is formed on the first metal wiring, andthe second sub-layer is formed on the first sub-layer.4. The semiconductor device of claim 1 , wherein:the etch-stop layer further includes a second sub-layer made of a silicon based insulating material,the second sub-layer is formed on the first metal wiring, andthe first sub-layer is formed on the first sub-layer.5. The semiconductor device of claim 1 , ...

Package Structure and Methods of Forming Same

A semiconductor device, a package structure, and methods of forming the same are disclosed. An embodiment is a semiconductor device comprising a first optical device over a first substrate, a vertical waveguide on a top surface of the first optical device, and a second substrate over the vertical waveguide. The semiconductor device further comprises a lens capping layer on a top surface of the second substrate, wherein the lens capping layer is aligned with the vertical waveguide, and a second optical device over the lens capping layer. 1. A method of forming a semiconductor device , the method comprising:bonding a first optical device to a first side of a first substrate;forming a vertical waveguide on a top surface of the first optical device;bonding a second side of a second substrate to the first side of the first substrate, the second side of the second substrate being over the vertical waveguide; andforming a lens capping layer on a first side of the second substrate, the first side being opposite the second side, a portion of the second substrate being directly between the vertical waveguide and the lens capping layer.2. The method of claim 1 , wherein the forming the vertical waveguide further comprises:dispensing a first polymer material directly on the top surface of the optical device.3. The method of claim 1 , wherein the forming the lens capping layer further comprises:dispensing a second polymer material directly on a first side of the second substrate.4. The method of claim 1 , wherein a top surface of the vertical waveguide is in direct contact with second side of the second substrate.5. The method of further comprising bonding a second optical device to the first side of the second substrate claim 1 , the second optical device being over the lens capping layer.6. The method of further comprising:forming a first redistribution layer over the first substrate;bonding the first optical device to the first redistribution layer;forming a second ...

SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME

A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first conductive structure over the substrate. The semiconductor device structure includes a first dielectric layer over the substrate. The first dielectric layer has a first opening exposing the first conductive structure. The semiconductor device structure includes a cover layer covering a first inner wall of the first opening. The cover layer has a second opening exposing the first conductive structure. The cover layer includes a metal oxide. The semiconductor device structure includes a second conductive structure filled in the first opening and surrounded by the cover layer. The second conductive structure is electrically connected to the first conductive structure. 115-. (canceled)16. A method for forming a semiconductor device structure , comprising:forming a first conductive structure over a substrate;forming a dielectric layer over the substrate, wherein the dielectric layer has an first opening exposing the first conductive structure;performing a deposition process to form a deposition layer over the first conductive structure and the dielectric layer, wherein the deposition layer has a first portion and a second portion, the first portion is over the first conductive structure, the second portion is over a first inner wall of the first opening, and the first portion and the second portion are made of different materials;removing the first portion; andfilling a second conductive structure into the first opening, wherein the second conductive structure is surrounded by the second portion, and the second conductive structure is electrically connected to the first conductive structure.17. The method for forming a semiconductor device structure as claimed in claim 16 , wherein the first portion is made of a metal oxynitride claim 16 , and the second portion is made of a metal oxide.18. The method for forming a ...

METHOD AND APPARATUS FOR FORMING SELF-ALIGNED VIA WITH SELECTIVELY DEPOSITED ETCHING STOP LAYER

A first layer is located over a substrate. The first layer includes a first dielectric component and a first conductive component. A first etching stop layer is located over the first dielectric component. A metal capping layer is located over the first conductive component. A second etching stop layer is located over the first etching stop layer and over the metal capping layer. A second layer is located over the second etching stop layer. The second layer includes a second dielectric component and a second conductive component. A third conductive component electrically interconnects the second conductive component to the first conductive component. 1. A semiconductor device , comprising:a first layer located over a substrate, wherein the first layer includes a first dielectric component and a first conductive component;a first etching stop layer located over the first dielectric component;a metal capping layer located over the first conductive component;a second etching stop layer located over the first etching stop layer and over the metal capping layer;a second layer located over the second etching stop layer, wherein the second layer includes a second dielectric component and a second conductive component; anda third conductive component that electrically interconnects the second conductive component to the first conductive component.2. The semiconductor device of claim 1 , wherein:the first layer includes a MX interconnect layer of a multi-layered interconnect structure; and{'b': '1', 'the second layer includes a MX+ interconnect layer of the multi-layered interconnect structure.'}3. The semiconductor device of claim 2 , wherein:the first conductive component includes a metal line of the MX interconnect layer;the second conductive component includes a second metal line of the MX+1 interconnect layer; andthe third conductive component includes a via between the MX interconnect layer and the MX+1 interconnect layer.4. The semiconductor device of claim 1 , ...

INTERCONNECT LAYER AND METHODS THEREOF

A method and structure for forming a barrier-free interconnect layer includes patterning a metal layer disposed over a substrate to form a patterned metal layer including one or more trenches. In some embodiments, the method further includes selectively depositing a barrier layer on metal surfaces of the patterned metal layer within the one or more trenches. In some examples, and after selectively depositing the barrier layer, a dielectric layer is deposited within the one or more trenches. Thereafter, the selectively deposited barrier layer may be removed to form air gaps between the patterned metal layer and the dielectric layer. 1. A method of fabricating a semiconductor device , comprising:patterning a metal layer disposed over a substrate to form a patterned metal layer including one or more trenches;selectively depositing a barrier layer on metal surfaces of the patterned metal layer within the one or more trenches;after the selectively depositing the barrier layer, depositing a dielectric layer within the one or more trenches; andremoving the selectively deposited barrier layer to form air gaps between the patterned metal layer and the dielectric layer.2. The method of claim 1 , wherein the metal layer is part of a multi-level metal interconnect network.3. The method of claim 2 , wherein the metal layer includes a metal line or a metal via of the multi-level metal interconnect network.4. The method of claim 1 , wherein the one or more trenches include sidewall surfaces and a bottom surface claim 1 , and wherein the barrier layer is selectively deposited on the sidewall surfaces without being deposited on the bottom surface.5. The method of claim 1 , wherein the barrier layer includes a self-assembled monolayer (SAM) or a polymer layer.6. The method of claim 1 , wherein the barrier layer includes a functional group that causes the barrier layer to be selectively deposited on the metal surfaces.7. The method of claim 1 , wherein the functional group includes ...

Porogen Bonded Gap Filling Material in Semiconductor Manufacturing

A device includes a substrate; a first layer over the substrate, the first layer containing a metallic material, wherein the first layer includes a trench; and a porous material layer having a first portion and a second portion. The first portion is disposed in the trench. The second portion is disposed on a top surface of the first layer. The first and the second portions contain substantially same percentage of Si, substantially same percentage of O, and substantially same percentage of C. 1. A device , comprising:a substrate;a first layer over the substrate, the first layer containing a metallic material, wherein the first layer includes a trench; anda porous material layer having a first portion and a second portion, the first portion disposed in the trench, the second portion disposed on a top surface of the first layer, wherein the first and the second portions contain substantially same percentage of Si, substantially same percentage of O, and substantially same percentage of C.2. The device of claim 1 , wherein the metallic material is one of: copper claim 1 , aluminum claim 1 , titanium claim 1 , titanium nitride claim 1 , conductive oxide claim 1 , or a combination thereof.3. The device of claim 1 , wherein the first and the second portions contain substantially the same level of porosity.5. The device of claim 4 , wherein the matrix and the polymer are bonded through a Si—O—[CHCHO]bond.6. The device of claim 4 , wherein the matrix includes one or more monomers of tetramethoxysilane (TMOS) claim 4 , methyltrimethoxysilane (MTMS) claim 4 , methyltriethoxysilane (MTES) claim 4 , or tetraethyl orthosilicate (TEOS).7. The device of claim 1 , wherein the first and the second portions contain substantially the same percentage of N.8. The device of claim 1 , wherein the percentage of O in the first and the second portions is higher than the percentage of C in the first and the second portions.9. The device of claim 8 , wherein the percentage of O in the first and ...

Structure and Method for Interconnection with Self-Alignment

The present disclosure provides a method of forming an integrated circuit structure. The method includes depositing a first metal layer on a semiconductor substrate; forming a hard mask on the first metal layer; patterning the first metal layer to form first metal features using the hard mask as an etch mask; depositing a dielectric layer of a first dielectric material on the first metal features and in gaps among the first metal features; performing a chemical mechanical polishing (CMP) process to both the dielectric layer and the hard mask; removing the hard mask, thereby having portions of the dielectric layer extruded above the metal features; forming an inter-layer dielectric (ILD) layer of the second dielectric material different from the first dielectric material; and patterning the ILD layer to form openings that expose the first metal features and are constrained to be self-aligned with the first metal features by the extruded portions of the first dielectric layer. 1. A method of forming an integrated circuit structure , comprising:forming a first metal layer on a substrate and a hard mask on the first metal layer;patterning the first metal layer to form first metal features using the hard mask as an etch mask;depositing a dielectric layer of a first dielectric material on the hard mask and in gaps among the first metal features;recessing evenly both the dielectric layer and the hard mask;removing the hard mask, thereby having portions of the dielectric layer extruded above the first metal features; andforming an inter-layer dielectric (ILD) layer of a second dielectric material such that the extruded portions of the dielectric layer are embedded in the ILD layer, the second dielectric material being different from the first dielectric material.2. The method of claim 1 , further comprisingpatterning the ILD layer to form openings that expose the first metal features and are constrained to be self-aligned with the first metal features by the extruded ...

Method of Fabrication Polymer Waveguide

A method of fabricating a waveguide device is disclosed. The method includes providing a substrate having an elector-interconnection region and a waveguide region and forming a patterned dielectric layer and a patterned redistribution layer (RDL) over the substrate in the electro-interconnection region. The method also includes bonding the patterned RDL to a vertical-cavity surface-emitting laser (VCSEL) through a bonding stack. A reflecting-mirror trench is formed in the substrate in the waveguide region, and a reflecting layer is formed over a reflecting-mirror region inside the waveguide region. The method further includes forming and patterning a bottom cladding layer in a wave-tunnel region inside the waveguide region and forming and patterning a core layer and a top cladding layer in the waveguide region. 1. A device comprising:a substrate having an electro-interconnection region and a waveguide region;a redistribution metal layer disposed over the substrate in the electro-interconnection region;a passivation layer disposed over the redistribution metal layer in the electro-interconnection region;a reflecting layer disposed over the passivation layer in the electro-interconnection region and over the waveguide region of the substrate;a first cladding layer disposed over the reflecting layer in the waveguide region;a core layer disposed over the first cladding layer in the waveguide region; anda second cladding layer disposed over core layer in the waveguide region.2. The device of claim 1 , wherein the wave guide region includes a trench claim 1 , andwherein the reflective layer, the first cladding layer, the core layer, and the second cladding layer are disposed within the trench.3. The device of claim 1 , wherein the reflecting layer is discontinuous as the reflecting layer does not extend continuously from the electro-interconnection region of the substrate to the waveguide region of the substrate.4. The device of claim 1 , wherein the substrate has a first ...

Semiconductor Integrated Circuit and Fabricating the Same

A semiconductor integrated circuit (IC) with a dielectric matrix is disclosed. The dielectric matrix is located between two conductive features. The matrix includes a first nano-scale dielectric block, a second nano-scale dielectric block, and a first nano-air-gap formed by a space between the first nano-scale dielectric block and the second nano-scale dielectric block. The matrix also includes third nano-scale dielectric block and a second nano-air-gap formed by a space between the second nano-scale dielectric block and the third nano-scale dielectric block. The nano-scale dielectric blocks share a first common width, and the nano-air-gaps share a second common width. An interconnect structure integrates the dielectric matrix with the conductive features. 1. A semiconductor integrated circuit (IC) , the IC comprising:a substrate;two conductive features;a dielectric matrix located between the conductive features, wherein the dielectric matrix includes three scale dielectric blocks with air-gaps formed therebetween, wherein, the scale dielectric blocks have a first common width and the air-gaps have a second common width; andan interconnect structure integrating the dielectric matrix with the conductive features.2. The device of claim 1 , wherein the scale dielectric blocks and the air-gaps are aligned perpendicularly to the conductive features.3. The device of claim 1 , wherein each of the scale dielectric blocks includes a low-k dielectric material.4. The device of claim 3 , wherein the low-k dielectric material includes fluorinated silica glass (FSG) claim 3 , carbon doped silicon oxide claim 3 , amorphous fluorinated carbon claim 3 , Parylene claim 3 , Bis-benzocyclobutenes (BCB) claim 3 , B-staged polymer claim 3 , or polyimide.5. The device of claim 3 , wherein the low-k dielectric material includes an extreme low k dielectric material.6. The device of claim 1 , wherein the first and second common widths are different claim 1 , and the the first common width is ...

Selective Deposition of Barrier Layer

Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a semiconductor substrate, a first ILD layer over the semiconductor substrate, and a first metal feature in the first ILD layer; depositing a second metal feature over the workpiece such that the second metal feature is electrically coupled to the first metal feature; patterning the second metal feature to form a first trench adjacent to the first metal feature; depositing a blocking layer over the workpiece, wherein the blocking layer selectively attaches to the first ILD layer; depositing a barrier layer over the workpiece, wherein the barrier layer selectively forms over the second metal feature relative to the first ILD layer; and depositing a second ILD layer over the workpiece.

WAVEGUIDE STRUCTURE AND METHOD FOR FABRICATING THE SAME

Embodiments of forming a waveguide structure are provided. The waveguide structure includes a substrate, and the substrate has an interconnection region and a waveguide region. The waveguide structure also includes a trench formed in the substrate, and the trench has a sloping sidewall surface and a substantially flat bottom. The waveguide structure further includes a bottom cladding layer formed on the substrate, and the bottom cladding layer extends from the interconnection region to the waveguide region, and the bottom cladding layer acts as an insulating layer in the interconnection region. The waveguide structure further includes a metal layer formed on the bottom cladding layer on the sloping sidewall surface. 1. A waveguide structure , comprising:a substrate, wherein the substrate has an interconnection region and a waveguide region;a trench formed in the substrate, wherein the trench has a sloping sidewall surface and a substantially flat bottom;a bottom cladding layer formed on the substrate, wherein the bottom cladding layer extends from the interconnection region to the waveguide region, and the bottom cladding layer acts as an insulating layer in the interconnection region; anda metal layer formed on the bottom cladding layer on the sloping sidewall surface.2. The waveguide structure as claimed in claim 1 , further comprising:a core layer formed on the bottom cladding layer in the waveguide region; anda top cladding layer formed on the core layer, wherein a waveguiding structure is formed by the bottom cladding layer, the core layer and the top cladding layer.3. The waveguide structure as claimed in claim 1 , wherein a refractive index of the core layer is larger than that of the bottom cladding layer and the refractive index difference is in a range from about 0.02 to about 0.2.4. The waveguide structure as claimed in claim 1 , wherein the metal layer comprises aluminum (Al) claim 1 , copper (Cu) claim 1 , silver (Ag) claim 1 , gold (Au) or combinations ...

STRUCTURE AND FORMATION METHOD OF INTERCONNECT STRUCTURE OF SEMICONDUCTOR DEVICE

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The dielectric layer has a protection region and a lower portion that is between the protection region and the semiconductor substrate. The protection region contains more carbon than the dielectric layer. The semiconductor device structure also includes a conductive feature penetrating through the protection region, and a lower portion of the conductive feature is surrounded by the lower portion of the dielectric layer. 1. A semiconductor device structure , comprising:a semiconductor substrate;a dielectric layer over the semiconductor substrate, wherein the dielectric layer has a protection region and a lower portion that is between the protection region and the semiconductor substrate, wherein a carbon concentration of the protection region is greater than that of the lower portion of the dielectric layer, a nitrogen concentration of the protection region is greater than that of the lower portion of the dielectric layer, and the protection region is denser than the lower portion of the dielectric layer; anda conductive feature penetrating through the protection region, wherein a lower portion of the conductive feature is surrounded by the lower portion of the dielectric layer.2. The semiconductor device structure as claimed in claim 1 , further comprising an etch stop layer over the protection region and the conductive feature.3. The semiconductor device structure as claimed in claim 1 , wherein top surfaces of the protection region and the conductive feature are substantially coplanar.4. (canceled)5. (canceled)6. The semiconductor device structure as claimed in claim 1 , wherein the protection region has a greater dielectric constant than the lower portion of the dielectric layer.7. The semiconductor device structure as claimed in claim 1 , wherein the ...

Integrated Metal Grating

An integrated circuit includes a substrate, a metal grating disposed over the substrate, and a waveguide layer disposed over or under the metal grating. The metal grating is arranged to change a propagation direction of an optical signal and the waveguide layer is arranged to guide the optical signal to a desired direction. 1. An integrated circuit , comprising:a substrate;a metal grating disposed over the substrate; anda waveguide layer disposed over or under the metal grating,wherein the metal grating is arranged to change a propagation direction of an optical signal and the waveguide layer is arranged to guide the optical signal to a desired direction.2. The integrated circuit of claim 1 , further comprising a photo detector disposed over the substrate claim 1 , wherein the waveguide layer is arranged to guide the optical signal towards the photo detector.3. The integrated circuit of claim 1 , further comprising a first dielectric layer disposed over the substrate and below the metal grating.4. The integrated circuit of claim 3 , further comprising at least one via in the first dielectric layer.5. The integrated circuit of claim 3 , further comprising a second dielectric layer disposed over the metal grating.6. The integrated circuit of claim 1 , further comprising a passivation layer over the substrate and below the waveguide layer.7. The integrated circuit of claim 1 , wherein the metal grating comprises copper or aluminum.8. The integrated circuit of claim 1 , wherein the metal grating has a thickness ranging from 20 nm to 200 nm.9. The integrated circuit of claim 1 , wherein the metal grating has a pitch ranging from 20 nm to 800 nm.10. The integrated circuit of claim 1 , wherein the waveguide layer comprises silicon nitride.11. The integrated circuit of claim 1 , wherein the waveguide layer has a thickness ranging from 20 nm to 300 nm.12. An integrated circuit claim 1 , comprising:a substrate;a metal grating disposed over the substrate;a waveguide layer ...

Using A Self-Assembly Layer To Facilitate Selective Formation of An Etching Stop Layer

A structure is provided that includes a first conductive component and a first interlayer dielectric (ILD) that surrounds the first conductive component. A self-assembly layer is formed on the first conductive component but not on the first ILD. A first dielectric layer is formed over the first ILD but not over the first conductive component. A second ILD is formed over the first conductive component and over the first ILD. An opening is etched in the second ILD. The opening is at least partially aligned with the first conductive component. The first dielectric layer protects portions of the first ILD located therebelow from being etched. The opening is filled with a conductive material to form a second conductive component in the opening. 1. A method , comprising:providing a structure that includes a first conductive component and a first interlayer dielectric (ILD) that surrounds the first conductive component;selectively forming a self-assembly layer on the first conductive component;selectively forming a first dielectric layer over the first ILD;forming a second ILD over the first conductive component and over the first ILD;etching an opening in the second ILD, wherein the opening is at least partially aligned with the first conductive component, wherein the first dielectric layer protects portions of the first ILD located therebelow from being etched; andfilling the opening with a conductive material to form a second conductive component in the opening.2. The method of claim 1 , wherein the forming the first dielectric layer comprises performing a deposition process using precursors claim 1 , and wherein during the forming of the first dielectric layer claim 1 , the self-assembly layer prevents the precursors from being formed on the first conductive component.3. The method of claim 1 , wherein the forming of the self-assembly layer comprises depositing the self-assembly layer that includes a head group and a tail group claim 1 , wherein the head group ...

Protecting Layer in a Semiconductor Structure

A method for forming a protecting layer includes determining an expected concentration of metal ions in a dielectric layer. The method also includes determining a thickness of the protecting layer based on the expected concentration of metal ions. The method also includes forming the protecting layer at the determined thickness and in contact with the dielectric layer. The protecting layer can include at least one of silicon doped nitride, carbon nitride, silicon nitride, or silicon carbon.