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Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 4409. Отображено 100.
26-01-2012 дата публикации

Semiconductor-on-insulator (soi) structure with selectively placed sub-insulator layer void(s) and method of forming the soi structure

Номер: US20120018806A1
Автор: Richard Q. Williams, Robert R. Robison, Toshiharu Furukawa
Принадлежит: International Business Machines Corp

Disclosed is a semiconductor-on-insulator (SOI) structure having sub-insulator layer void(s) selectively placed in a substrate so that capacitance coupling between a first section of a semiconductor layer and the substrate will be less than capacitance coupling between a second section of the semiconductor layer and the substrate. The first section may contain a first device on an insulator layer and the second section may contain a second device on the insulator layer. Alternatively, the first and second sections may comprise different regions of the same device on an insulator layer. For example, in an SOI field effect transistor (FET), sub-insulator layer voids can be selectively placed in the substrate below the source, drain and/or body contact diffusion regions, but not below the channel region so that capacitance coupling between the these various diffusion regions and the substrate will be less than capacitance coupling between the channel region and the substrate. Also, disclosed is an associated method of forming such an SOI structure.

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Номер записи: 1
03-05-2012 дата публикации

Showerhead for cvd depositions

Номер: US20120108076A1
Автор: Brian E. Goodlin, Qidu Jiang
Принадлежит: Texas Instruments Inc

A CVD showerhead that includes a circular inner showerhead and at least one outer ring showerhead. At least two process gas delivery tubes are coupled to each showerhead. Also, a dual showerhead that includes a circular inner showerhead and at least one outer ring showerhead where each showerhead is coupled to oxygen plus a gas mixture of lead, zirconium, and titanium organometallics. A method of depositing a CVD thin film on a wafer. Also, a method of depositing a PZT thin film on a wafer.

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Номер записи: 2
14-03-2013 дата публикации

CLEANING METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS AND RECORDING MEDIUM

Номер: US20130065402A1
Автор: Kameda Kenji, URANO Yuji
Принадлежит: HITACHI KOKUSAI ELECTRIC INC.

A method of cleaning an inside of a processing chamber is provided according to an embodiment of the present disclosure. The method includes supplying a fluorine-based gas and a nitrogen oxide-based gas as the cleaning gas, into the processing chamber heated to a first temperature, and removing a deposit by a thermochemical reaction. The method further includes changing a temperature in the processing chamber to a second temperature higher than the first temperature, and supplying the fluorine-based gas and the nitrogen oxide-based gas as the cleaning gas, and removing extraneous materials, remaining on the surface of the member in the processing chamber, by a thermochemical reaction. 1. A method of cleaning an inside of a processing chamber by supplying a cleaning gas into the processing chamber after performing a process of forming a thin film on a substrate in the processing chamber , the method comprising:supplying a fluorine-based gas and a nitrogen oxide-based gas or a fluorine-based gas and a nitrogen oxide-based gas diluted with an inert gas, as the cleaning gas, into the processing chamber heated to a first temperature, and removing a deposit, including the thin film deposited on a surface of a member in the processing chamber, by a thermochemical reaction;changing a temperature in the processing chamber to a second temperature higher than the first temperature; andsupplying the fluorine-based gas and the nitrogen oxide-based gas or the fluorine-based gas and the nitrogen oxide-based gas diluted with the inert gas, as the cleaning gas, into the processing chamber heated to the second temperature, and removing extraneous materials, remaining on the surface of the member in the processing chamber after removing the deposit including the thin film by a thermochemical reaction.2. The method of claim 1 , wherein a flow rate ratio of the nitrogen oxide-based gas to the fluorine-based gas is set to be a first flow rate ratio in the removing of the deposit ...

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Номер записи: 3
28-03-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME

Номер: US20130075819A1
Автор: Kobayashi Yusuke, Takei Manabu
Принадлежит:

A semiconductor device includes an active section for a main current flow and a breakdown withstanding section for breakdown voltage. An external peripheral portion surrounds the active section on one major surface of an n-type semiconductor substrate. The breakdown withstanding section has a ring-shaped semiconductor protrusion, with a rectangular planar pattern including a curved section in each of four corners thereof, as a guard ring. The ring-shaped semiconductor protrusion has a p-type region therein, is sandwiched between a plurality of concavities deeper than the p-type region, and has an electrically conductive film across an insulator film on the surface thereof. Because of this, it is possible to manufacture at low cost a breakdown withstanding structure with which a high breakdown voltage is obtained in a narrow width, wherein there is little drop in breakdown voltage, even when there are variations in a patterning process of a field oxide film. 1. A semiconductor device , comprising:an active section engaged in making a main current flow and a breakdown withstanding section, engaged in breakdown voltage, disposed in an external peripheral portion surrounding the active section on one major surface of a first conductivity type semiconductor substrate, whereinthe breakdown withstanding section has a ring-shaped semiconductor protrusion, with a rectangular planar pattern including a curved section in each of four corners thereof, as a guard ring, andthe ring-shaped semiconductor protrusion has a second conductivity type region therein, is sandwiched between a plurality of concavities deeper than the second conductivity type region and, a difference in height between the ring-shaped semiconductor protrusion and the concavities being less than 2 μm, has an electrically conductive film across an insulator film on a surface thereof.2. The semiconductor device according to claim 1 , whereinthe insulator film is 0.5 μm or less in thickness.3. The semiconductor ...

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Номер записи: 4
28-03-2013 дата публикации

PROCESS FOR PRODUCING A CONDUCTING ELECTRODE

Номер: US20130075832A1
Автор: Gassilloud Remy, Martin François
Принадлежит: Commissariat a l' energie atomique et aux energies alternatives

A process for producing a conducting electrode on a substrate, including: depositing a layer made of a dielectric; depositing a protective layer made of the nitride of a metal on the dielectric layer; depositing a functionalization layer made of a material including a chemical species, such that the free enthalpy of formation of the nitride of the species is less, in absolute value, than the free enthalpy of formation of the nitride of the metal of the protective layer over the temperature range between 0° C. and 1200° C.; and annealing the assembly including the protective layer and the funtionalization layer so that the species diffuse from the functionalization layer into the protective layer and the nitrogen atoms migrate from the protective layer into the functionalization layer. 1. A process for producing a conducting electrode on a substrate comprising:depositing a layer made with a dielectric material;depositing on the dielectric layer a protective layer made of a nitride of a metal;depositing a functionalization layer made of a material comprising a chemical species such that the free enthalpy of formation of a nitride of said species is less, in absolute value, than the free enthalpy of formation of the nitride of the metal of said protective layer over a temperature range of between 0 and 1200° C., said chemical species being chosen from among the following species: Mg or Ca;annealing an assembly comprising said protective layer and said functionalization layer such that the chemical species at least partially diffuse from said functionalization layer into said protective layer and nitrogen atoms at least partially migrate from said protective layer into said functionalization layer, said conducting electrode including said protective and functionalization layers after annealing.2. The process according to claim 1 , wherein the dielectric layer is made with an insulation material in which the dielectric constant is equal to or greater than that of silicon ...

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Номер записи: 5
04-04-2013 дата публикации

RESTRICTED STRESS REGIONS FORMED IN THE CONTACT LEVEL OF A SEMICONDUCTOR DEVICE

Номер: US20130084703A1
Автор: Feustel Frank, Frohberg Kai, Werner Thomas
Принадлежит: GLOBALFOUNDRIES INC.

In sophisticated semiconductor devices, an efficient stress decoupling may be accomplished between neighboring transistor elements of a densely packed device region by providing a gap or a stress decoupling region between the corresponding transistors. For example, a gap may be formed in the stress-inducing material so as to reduce the mutual interaction of the stress-inducing material on the closely spaced transistor elements. In some illustrative aspects, the stress-inducing material may be provided as an island for each individual transistor element. 1. A method , comprising:forming a stress-inducing layer above a first transistor and a second transistor formed in a device level of a semiconductor device; andforming a stress decoupling region in said stress-inducing layer between said first and second transistors, said stress decoupling region extending along a transistor width direction of said first and second transistors by forming a mask material on said stress-inducing layer, removing a portion of said mask material so as to expose a portion of said stress-inducing layer, and performing a surface treatment in the presence of said mask material.2. The method of claim 1 , wherein forming said stress decoupling region comprises reducing a thickness of said stress-inducing layer between said first and second transistors.3. The method of claim 2 , wherein said stress-inducing layer is substantially completely removed in said stress decoupling region.4. The method of claim 1 , wherein said stress decoupling region laterally encloses said first transistor and said second transistor so as to provide a first island of stress-inducing material formed above said first transistor and a second island of stress-inducing material formed above said second transistor.5. The method of claim 1 , wherein forming said stress decoupling region comprises locally modifying a surface condition at an area corresponding to said stress decoupling region so as to obtain a reduced ...

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Номер записи: 6
18-04-2013 дата публикации

Deposited Material and Method of Formation

Номер: US20130093048A1
Автор: Cheng-Yuan Tsai, Hsing-Lien Lin, Yao-Wen Chang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A system and method for manufacturing a semiconductor device is provided. An embodiment comprises forming a deposited layer using an atomic layer deposition (ALD) process. The ALD process may utilize a first precursor for a first time period, a first purge for a second time period longer than the first time period, a second precursor for a third time period longer than the first time period, and a second purge for a fourth time period longer than the third time period.

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Номер записи: 7
18-04-2013 дата публикации

TECHNIQUE FOR REDUCING TOPOGRAPHY-RELATED IRREGULARITIES DURING THE PATTERNING OF A DIELECTRIC MATERIAL IN A CONTACT LEVEL OF CLOSELY SPACED TRANSISTORS

Номер: US20130095648A1
Автор: Richter Ralf, Salz Heike, Seidel Robert
Принадлежит: Advanced Micro Devices, Inc.

In a dual stress liner approach, the surface conditions after the patterning of a first stress-inducing layer may be enhanced by appropriately designing an etch sequence for substantially completely removing an etch stop material, which may be used for the patterning of the second stress-inducing dielectric material, while, in other cases, the etch stop material may be selectively formed after the patterning of the first stress-inducing dielectric material. Hence, the dual stress liner approach may be efficiently applied to semiconductor devices of the 45 nm technology and beyond. 19.-. (canceled)10. A method , comprising:forming a layer stack above first and second conductive lines formed in a device level of a semiconductor device, said layer stack comprising a first stress-inducing dielectric layer and an etch stop layer formed above said first stress-inducing dielectric layer;forming a mask so as to expose said second conductive lines and cover said first conductive lines;performing an etch sequence to remove said first stress-inducing dielectric layer and said etch stop layer from above said second conductive lines and reduce a width of sidewall spacer elements formed on sidewalls of said second conductive lines, wherein reducing said width comprises removing a first thickness portion of said sidewall spacer elements while leaving a second thickness portion of said sidewall spacer elements adjacent to said sidewalls;after performing said etch sequence, forming a second stress-inducing dielectric layer above said second conductive lines and on a portion of said etch stop layer located above said first conductive lines; andselectively removing said second stress-inducing dielectric layer from above said first conductive lines by using said etch stop layer as an etch stop.11. The method of claim 10 , wherein performing said etch sequence comprises performing a first etch process to expose at least a portion of said first stress-inducing dielectric layer and ...

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Номер записи: 8
25-04-2013 дата публикации

SEMICONDUCTOR DEVICE HAVING STRAIN MATERIAL

Номер: US20130099851A1
Автор: Yang Haining
Принадлежит: QUALCOMM INCORPORATED

A semiconductor device having strain material is disclosed in a particular embodiment, the semiconductor device includes a first cell including a first gate between a first drain and a first source. The semiconductor device also includes a second cell adjacent to the first cell. The second cell includes a second gate between a second drain and a second source. The semiconductor device further includes a shallow trench isolation area between the first source and the second source. A first amount of strain material over the first source and over the second source is greater than a second amount of strain material over the first drain and over the second drain. 1. An apparatus comprising: a first cell comprising a first gate between a first drain and a first source;', 'a second cell adjacent to the first cell, the second cell comprising a second gate between a second drain and a second source; and', 'a shallow trench isolation area between the first source and the second source., 'a semiconductor device comprisingwherein a first amount of strain material over the first source and over the second source is greater than a second amount of strain material over the first drain and over the second drain.2. The apparatus of claim 1 , wherein the shallow trench isolation area comprises an isolation material within a substrate of the semiconductor device claim 1 , and wherein the strain material over the first source and over the second source extends substantially continuously over the shallow trench isolation area.3. The apparatus of claim 1 , wherein the semiconductor device further comprises a dummy gate etch region between the first source and the second source.4. The apparatus of claim 1 , wherein the strain material comprises one of silicon nitride and silicon carbide.5. The apparatus of claim 1 , wherein the first cell comprises an n-type field effect transistor (NFET) device and wherein a shallow trench isolation area is positioned between the first source and the ...

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Номер записи: 9
16-05-2013 дата публикации

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE

Номер: US20130119407A1
Автор: Hiyoshi Toru, Masuda Takeyoshi, Wada Keiji
Принадлежит: Sumitomo Electric Industries, Ltd.

A method for manufacturing a semiconductor device includes the steps of: preparing a substrate made of silicon carbide; forming, in the substrate, a trench opened on one main surface side of the substrate; and forming an oxide film in a region including a surface of the trench. In the step of forming the oxide film, the substrate is heated at a temperature of not less than 1250° C. in an atmosphere containing oxygen. 1. A method for manufacturing a semiconductor device , comprising the steps of:preparing a substrate made of silicon carbide;forming, in said substrate, a trench opened on one main surface side of said substrate and including a wall surface having an angle of not less than 40° and not more than 70° with respect to a {0001} plane; andforming an oxide film in a region including said wall surface of said trench,wherein, in the step of forming said oxide film, said substrate is heated at a temperature of not less than 1250° C. in an atmosphere containing oxygen.2. The method for manufacturing a semiconductor device according to claim 1 , wherein claim 1 , in the step of forming said oxide film claim 1 , said substrate is heated at a temperature of not less than 1300° C.3. The method for manufacturing a semiconductor device according to claim 1 , wherein claim 1 , in the step of forming said oxide film claim 1 , said substrate is heated at a temperature of not more than 1400° C.4. The method for manufacturing a semiconductor device according to claim 1 , further comprising the step of introducing nitrogen atoms into a region including an interface between said oxide film and the silicon carbide constituting said substrate claim 1 , by heating said substrate in an atmosphere including a gas containing nitrogen atoms.5. The method for manufacturing a semiconductor device according to claim 1 , wherein said main surface of said substrate is a {0001} plane.6. (canceled)7. A semiconductor device claim 1 , comprising:a substrate made of silicon carbide and having ...

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Номер записи: 10
16-05-2013 дата публикации

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20130122669A1
Автор: KOMATANI Tsutomu, KOYAMA Masatoshi, Matsuura Kazuaki
Принадлежит: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.

A method for manufacturing a semiconductor device includes: forming a first active region, a second active region, an inactive region located between the first active region and the second active region, and a third active region, which crosses the inactive region to electrically connect the first active region to the second active region, in a semiconductor layer; forming an insulating layer on the semiconductor layer; and forming an opening selectively in the insulating layer by dry etching. 1. A method for manufacturing a semiconductor device comprising:forming a first active region, a second active region, an inactive region located between the first active region and the second active region, and a third active region, which crosses the inactive region to electrically connect the first active region to the second active region, in a semiconductor layer;forming an insulating layer on the semiconductor layer; andforming an opening selectively in the insulating layer by dry etching.2. The method according to claim 1 , whereinthe inactive region surrounds the first active region.3. The method according to claim 1 , whereinthe second active region is a scribe line.4. The method according to claim 3 , whereina plurality of the first active regions are formed, andeach of the plurality of the first active regions is electrically connected to the second active region by the third active region.5. The method according to claim 1 , whereinthe first active region includes a layer functioning as a channel layer of a field-effect transistor, andthe second active region and the third active region have the same layer structure as the first active region has.6. The method according to claim 1 , wherein{'sup': −1', '−1, 'the insulating layer is made of silicon nitride, of which an FTIR peak position of a silicon-nitrogen stretching vibration is less than or equal to 2160 cm, or of aluminum oxide, of which an FTIR peak position of an aluminum-oxygen stretching vibration is ...

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Номер записи: 11
16-05-2013 дата публикации

NOVEL HARD MASK REMOVAL METHOD

Номер: US20130122699A1
Автор: WANG Shiang-Bau
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A method of removing a hard mask used for patterning gate stacks including patterning gate stacks on a substrate, wherein the hard mask is deposited over the gate stacks. The method further includes depositing a dielectric layer on the substrate after the gate stacks are patterned and planarizing a first portion of the dielectric layer. The method further includes removing a second portion of the dielectric layer and the hard mask by using an etching gas and etching the remaining dielectric layer by using a wet etching chemistry. 1. A method of removing a hard mask used for patterning gate stacks , comprising:patterning gate stacks on a substrate, wherein the hard mask is formed over the gate stacks;forming a dielectric layer on the patterned gate stacks;planarizing a first portion of the dielectric layer; andremoving a second portion of the dielectric layer and the hard mask by using an etching gas.2. The method according to claim 1 , wherein the hard mask comprises an oxide layer having a thickness ranging from about 50 Angstroms (Å) to about 500 Å over a nitride layer having a thickness ranging from about 50 Å to about 200 Å.3. The method according to claim 1 , wherein removing the second portion of the dielectric layer and the hard mask layer comprises:forming a layer of etch by-product on the patterned gate stacks; anddecomposing the etch by-product by heating.4. The method according to claim 1 , further comprising densifying the dielectric layer prior to planarizing the first portion claim 1 , wherein densifying comprises annealing the dielectric layer at a temperature from about 300° C. to about 450° C.5. The method according to claim 4 , wherein the annealing further comprises introducing an annealing gas claim 4 , wherein the annealing gas comprises at least one of an inert gas claim 4 , nitrogen gas or oxygen gas.6. The method according to claim 1 , further comprising removing the remaining dielectric layer by using a wet etching chemistry claim 1 , ...

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Номер записи: 12
16-05-2013 дата публикации

FILM DEPOSITION APPARATUS, FILM DEPOSITION METHOD, AND STORAGE MEDIUM

Номер: US20130122718A1
Автор: HONMA Manabu, KATO Hitoshi
Принадлежит: TOKYO ELECTRON LIMITED

A disclosed film deposition apparatus includes a turntable including a substrate receiving area; a first reaction gas supplier for supplying a first reaction gas to a surface of the turntable having the substrate receiving area; a second reaction gas supplier, arranged away from the first reaction gas supplier along a circumferential direction of the turntable, for supplying a second reaction gas to the surface; a separation area located along the circumferential direction between a first process area of the first reaction gas and a second process area of the second reaction gas; a separation gas supplier for supplying a first separation gas to both sides of the separation area; a first heating unit for heating the first separation gas to the separation gas supplier; an evacuation opening for evacuating the gases supplied to the turntable; and a driver for rotating the turntable in the circumferential direction. 1. A film deposition method for depositing a film on a substrate by carrying out a cycle of supplying in turn at least two kinds of reaction gases that react with each other to the substrate to produce a layer of a reaction product in a chamber , the film deposition method comprising steps of:substantially horizontally placing the substrate on a turntable in a chamber;supplying a first reaction gas from a first reaction gas supplying portion to a surface of the turntable, the surface having a substrate receiving area in which the substrate is placed;supplying a second reaction gas to the surface of the turntable from a second reaction gas supplying portion arranged away from the first reaction gas supplying portion along a circumferential direction of the turntable;supplying a first separation gas from a separation gas supplying portion provided in a separation area located between a first process area in which the first reaction gas is supplied and a second process area in which the second reaction gas is supplied, in order to separate atmospheres of the ...

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Номер записи: 13
16-05-2013 дата публикации

CURABLE COMPOSITION AND PROCESS FOR PRODUCING CURED FILM

Номер: US20130123382A1
Автор: ABE Takefumi, ERIGUCHI Takeshi, Ito Masahiro, TSURUOKA Kaori
Принадлежит: Asahi Glass Company, Limited

To provide a curable composition which is sufficiently cured even without a heating step at high temperature and from which a low dielectric constant cured film excellent in the solvent resistance is obtained. 1. A curable composition comprising a fluorinated polyarylene prepolymer (A) having a crosslinkable functional group , a compound (B) having a number average molecular weight of from 140 to 5 ,000 , having at least two crosslinkable functional groups and having no fluorine atoms , a copolymer (C) having the following units (c1) and (c2) and a radical polymerization initiator (D):unit (c1): a unit having a fluoroalkyl group having at most 20 carbon atoms, which may have an etheric oxygen atom between carbon atoms, and having no crosslinkable functional group;unit (c2): a unit having a crosslinkable functional group.2. The curable composition according to claim 1 , wherein each of the crosslinkable functional groups in the prepolymer (A) claim 1 , the compound (B) and the compound (C) which are independent of one another claim 1 , is a crosslinkable functional group selected from the group consisting of a vinyl group claim 1 , an allyl group claim 1 , an ethynyl group claim 1 , a vinyloxy group claim 1 , an allyloxy group claim 1 , an acryloyl group claim 1 , an acryloyloxy group claim 1 , a methacryloyl group and a methacryloyloxy group.3. The curable composition according to claim 1 , which contains from 10 to 80 parts by mass of the compound (B) based on the total amount (100 parts by mass) of the prepolymer (A) and the compound (B).4. The curable composition according to claim 1 , wherein the radical polymerization initiator (D) is a thermal initiator or a photoinitiator.5. The curable composition according to claim 1 , which contains from 0.1 to 20 parts by mass of the copolymer (C) based on the total amount (100 parts by mass) of the prepolymer (A) and the compound (B).6. The curable composition according to claim 1 , wherein the unit (c1) is a unit formed ...

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Номер записи: 14
23-05-2013 дата публикации

Guided Wave Applicator with Non-Gaseous Dielectric for Plasma Chamber

Номер: US20130126331A1
Автор: ANWAR Suhail, KUDELA Jozef, SORENSEN Carl A., Tanaka Tsutomu, WHITE John M.
Принадлежит:

A guided wave applicator comprising two electrically conductive waveguide walls and a waveguide dielectric. The volume of the waveguide dielectric is composed of non-gaseous dielectric material and is positioned between the two waveguide walls. The waveguide dielectric includes first and second longitudinal ends and includes first, second, third and fourth sides extending longitudinally between the two longitudinal ends. The first waveguide wall is positioned so that it covers the first side of the waveguide dielectric, and the second waveguide wall is positioned so that it covers the second side of the waveguide dielectric. In operation, electrical power can be supplied to one or both longitudinal ends of the waveguide dielectric, whereby the power can be coupled to a plasma through the exposed sides of the waveguide dielectric. 1. A guided wave applicator for coupling electrical power to a plasma , comprising:first and second waveguide walls, wherein each waveguide wall is electrically conductive; and (i) first and second longitudinal ends, and', '(ii) first, second, third and fourth sides that extend longitudinally between the two longitudinal ends;, 'a waveguide dielectric whose volume is composed of non-gaseous dielectric material, wherein the waveguide dielectric includeswherein:the waveguide dielectric is positioned between the two waveguide walls;the first waveguide wall is positioned so that it covers the first side of the waveguide dielectric;the second waveguide wall is positioned so that it covers the second side of the waveguide dielectric; anda portion of each of the third and fourth sides of the waveguide dielectric is not covered by the waveguide walls.2. The guided wave applicator of claim 1 , wherein:at least half the surface area of each of the third and fourth sides of the waveguide dielectric is not covered by the waveguide walls.3. The guided wave applicator of claim 1 , wherein:at least half the surface area of each of the third and fourth ...

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Номер записи: 15
23-05-2013 дата публикации

GROUP III NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20130126907A1
Автор: Kitano Tsukasa, KOIKE Masayoshi, KONDO Toshiyuki, Maeda Tomohiko, MORI Midori, NANIWAE Koichi, Suzuki Atsushi, Teramae Fumiharu
Принадлежит: EL-SEED Corporation

[Problem] To provide a group III nitride semiconductor device and a method for manufacturing the same in which dislocation density in a semiconductor layer can be precisely reduced. 1. A group III nitride semiconductor device comprising:a substrate made of SiC:a mask layer formed on the substrate and including formation of a predetermined periodic pattern;nanocolumns selectively grown through the predetermined pattern of the mask layer and made of a group III nitride semiconductor; anda group III nitride semiconductor layer formed on the mask layer and grown to be higher than the nanocolumns so as to fill in the nanocolumns.2. The group III nitride semiconductor device according to claim 1 , wherein the mask layer is made of an amorphous material.3. The group III nitride semiconductor device according to claim 2 , wherein a buffer layer made of a group III nitride semiconductor including Al is interposed between the substrate and the mask layer.4. A method for manufacturing the group III nitride semiconductor device according to claim 1 , the method comprising:a mask layer formation process to form the mask layer on the substrate;a nanocolumn growth process to selectively grow the nanocolumns made of a group III nitride semiconductor through the pattern of the mask layer; anda semiconductor layer growth process to grow the group III nitride semiconductor layer on the mask layer.5. The method for manufacturing the group III nitride semiconductor device according to claim 3 , the method comprising:a buffer layer formation process to form the buffer layer on the substrate by the sputtering method;a mask layer formation process to form the mask layer on the substrate provided with the buffer layer formed thereon;a nanocolumn growth process to selectively grow the nanocolumns made of a group III nitride semiconductor through the pattern of the mask layer; anda semiconductor layer growth process to grow the group III nitride semiconductor layer on the mask layer.6. A ...

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Номер записи: 16
23-05-2013 дата публикации

ELECTRONIC FIELD EFFECT DEVICES AND METHODS FOR THEIR MANUFACTURE

Номер: US20130126909A1
Автор: Balmer Richard Stuart, Friel Ian, Scarsbrook Geoffrey Alan, Wort Christopher John Howard
Принадлежит: DIAMOND MICROWAVE DEVICES LIMITED

Electronic field effect devices, and methods of manufacture of these electronic field effect devices are disclosed. In particular, there is disclosed an electronic field effect device which has improved electrical properties due to the formation of a highly mobile two-dimensional charge-carrier gas in a simple structure formed from diamond in combination with polar materials. 1. An electronic field effect device comprising: a first diamond layer, at least a first surface of which comprises crystalline intrinsic diamond, and', 'a second layer disposed on the first surface of the first layer, wherein the second layer is polar; wherein, 'an interface between two materials, wherein the interface is formed bythere is a discontinuity in polarization between the first layer and the second layer; andthere is a band offset between the first layer and the second layer, in the band in which the dominant charge carriers are present, such that the dominant charge carriers are confined to a planar region within the first layer and in close proximity to the interface by the combined effects of a polarization induced sheet charge and an electric field provided by the discontinuity in polarization between the first layer and the second layer, and the band offset.2. The electronic field-effect device of wherein the second layer comprises a pyroelectric layer.3. The electronic field-effect device of wherein the second layer comprises AlN or AlGaN.4. The electronic field-effect device of wherein the diamond layer comprises synthetic diamond formed by chemical vapour deposition.58-. (canceled)97. The electronic field-effect device of claim wherein the second layer is arranged so that a component of its polarization vector points away from the interface.10. The electronic field-effect device of wherein the second layer is arranged so that its polarization vector P is substantially normal to the interface.1120-. (canceled)21. The electronic field-effect device of claim 1 , further ...

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Номер записи: 17
23-05-2013 дата публикации

III-V Compound Semiconductor Epitaxy From a Non-III-V Substrate

Номер: US20130126946A1
Автор: Chen Ding-Yuan, Chiou Wen-Chih, Yu Chen-Hua, YU Chia-Lin
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A structure comprises a substrate, a mask, a buffer/nucleation layer, and a group III-V compound semiconductor material. The substrate has a top surface and has a recess from the top surface. The recess includes a sidewall. The first mask is the top surface of the substrate. The buffer/nucleation layer is along the sidewall, and has a different material composition than a material composition of the sidewall. The III-V compound semiconductor material continuously extends from inside the recess on the buffer/nucleation layer to over the first mask. 1. A structure comprising:a substrate comprising protrusions and recesses between the protrusions, the protrusions comprising respective substrate sidewalls, the substrate sidewalls having a first composition;first masks over the protrusions of the substrate;buffer/nucleation layers along the respective substrate sidewalls, the buffer/nucleation layers having a second composition different from the first composition; anda group-III group-V (III-V) compound semiconductor material comprising first portions and second portions, the first portions extending into the recesses and along the buffer/nucleation layers, the second portions being over the first masks, wherein the first portions and the second portions are portions of a continuous III-V compound semiconductor layer.2. The structure of further comprising second masks in the recesses and covering bottoms of the recesses claim 1 , wherein at least portions of the substrate sidewalls are free from the second masks.3. The structure of claim 1 , wherein the first masks comprise a dielectric material claim 1 , a metal claim 1 , a metal alloy claim 1 , a metal nitride claim 1 , a metal carbide claim 1 , a metal carbon-nitride claim 1 , or a combination thereof.4. The structure of claim 1 , wherein the first masks are conductive.5. The structure of further comprising intermediate layers disposed between the respective substrate sidewalls and the respective buffer/nucleation ...

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Номер записи: 18
23-05-2013 дата публикации

Quantum Well Device

Номер: US20130130474A1
Автор: Baldwin Kirk William, Pfeiffer Loren N., West Kenneth William
Принадлежит:

An apparatus includes a primary planar quantum well and a planar distribution of dopant atoms. The primary planar quantum well is formed by a lower barrier layer, a central well layer on the lower barrier layer, and an upper barrier layer on the central well layer. Each of the layers is a semiconductor layer. One of the barrier layers has a secondary planar quantum well and is located between the planar distribution of dopant atoms and the central well layer, The primary planar quantum well may be undoped or substantially undoped, e.g., intrinsic semiconductor. 111.-. (canceled)12. A method , comprising:forming a primary planar quantum well by growing a semiconductor lower barrier layer over a crystalline substrate, growing a semiconductor central well layer on the lower barrier layer, and growing a semiconductor upper barrier layer on the central well layer; andforming a planar distribution of dopant atoms above the substrate; andwherein the growing of one of the barrier layers includes forming a secondary planar quantum well therein;wherein the planar distribution of dopant atoms is located above or below the primary planar quantum well.wherein the secondary planar quantum well is formed of a bottom barrier layer, a second well layer on the bottom barrier layer, and a top barrier layer on the second well layer; andwherein the second well layer is at least five times narrower than the central well layer of the primary planar quantum well.13. The method of claim 12 , wherein the primary planar quantum well is formed of undoped semiconductor.14. The method of claim 12 , wherein the growing of another of the barrier layers includes forming a secondary planar quantum well in the another of the barrier layers.15. (canceled)16. The method of claim 12 , wherein the one of the barrier layers includes a plurality of secondary planar quantum wells therein.17. The method of claim 12 , further comprising:forming another planar distribution of dopant atoms above the substrate ...

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Номер записи: 19
23-05-2013 дата публикации

METHOD FOR PRODUCING GALLIUM TRICHLORIDE GAS AND METHOD FOR PRODUCING NITRIDE SEMICONDUCTOR CRYSTAL

Номер: US20130130477A1
Автор: Koukuti Akinori, KUMAGAI Yoshinao
Принадлежит: NATIONAL UNIVERSITY CORPORATION TOKYO UNIVERSITY OF AGRICULTURE AND TECHNOLOGY

According to the invention, there is provided a method for producing a gallium trichloride gas, the method including: a first step of reacting a metallic gallium and a chlorine gas to produce a gallium monochloride gas; and a second step of reacting the produced gallium monochloride gas and a chlorine gas to produce a gallium trichloride gas. 1. A method for producing a gallium trichloride gas , the method comprising:a first step of reacting a metallic gallium and a chlorine gas to produce a gallium monochloride gas; anda second step of reacting the produced gallium monochloride gas and a chlorine gas to produce a gallium trichloride gas.2. The method for producing a gallium trichloride gas according to claim 1 , wherein in the first step claim 1 , the reaction of the metallic gallium and the chlorine gas is carried out at a temperature of from 300 to 1 claim 1 ,000° C.3. The method for producing a gallium trichloride gas according to claim 1 , wherein in the second step claim 1 , the reaction of the gallium monochloride gas and the chlorine gas is carried out at a temperature of from 150 to 1 claim 1 ,000° C.4. The method for producing a gallium trichloride gas according to claim 1 , wherein in the first step claim 1 , the reaction of the metallic gallium and the chlorine gas is carried out at a temperature of from 500 to 1 claim 1 ,000° C.5. The method for producing a gallium trichloride gas according to claim 1 , wherein in the second step claim 1 , the reaction of the gallium monochloride gas and the chlorine gas is carried out at a temperature of from 500 to 1 claim 1 ,000° C.6. The method for producing a gallium trichloride gas according to claim 1 , wherein each of the reactions in the first step and the second step is carried out in the presence of a carrier gas in which a molar ratio of a hydrogen gas is 1.0×10or less.7. A method for producing a nitride semiconductor crystal claim 1 , the method comprising:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, ' ...

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Номер записи: 20
23-05-2013 дата публикации

Semiconductor Substrate Transfer/Processing-tunnel -arrangement, with Successive Semiconductor Substrate - Sections

Номер: US20130130510A1
Автор: Bok Edward
Принадлежит:

Semiconductor substrate transfer treatment/processing tunnel-arrangement, containing such means, that thereby also during the uninterrupted operation thereof the uninterruptedly taking place of the establishing of a (sub) micrometer high layer of semiconductor substances with an optimum uniform height thereof upon the successive semiconductor substrate-sections, uninterruptedly displacing therethrough and such by means of through a strip-shaped supply-section of the uppertunnelclock in its central semiconductor section the uninterruptedly taking place of a supply of the combination of fluidic support-medium and parts of a semiconductor substance in a solid- or fluidic form thereof and in the thereupon following strip-shaped semiconductor treatment/processing section underneath a vibrating transducer-arrangement, located in a transducer-compartment of this block, the also by means of the in addition developed heat of this vibrating transducer the taking place of evaporation of this support-medium under an at-least almost uniform deposition of these particles of a semiconductor substance upon these successive semiconductor substrate-sections, displacing underneath, and the discharge of the established vapor through a thereupon following strip-shaped discharge-section in this block. 1136-. (canceled)137. A substrate transfer/processing tunnel-arrangement for transfer and processing of successive substrate-sections , comprising:a) the combination of an uppertunnelblock and a lowertunnelblock, extending in longitudinal direction thereof; andb) above this uppertunnelblock in longitudinal direction thereof the location of at-least one strip-shaped direction device, extending mainly in transverse direction on behalf of during its operation the uninterruptedly taking place of the supply of at-least a fluidic support-medium and particles of a substance in a solid or fluidic form toward strip-shaped uppersplit-sections above the successive underneath this block uninterruptedly ...

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Номер записи: 21
30-05-2013 дата публикации

SEMICONDUCTOR DEVICE STRUCTURES COMPRISING CRYSTALLINE Pr1-xCaxMnO3 (PCMO) MATERIAL AND METHODS OF FORMING CRYSTALLINE PCMO MATERIAL

Номер: US20130134375A1
Автор: Sandhu Gurtej S., Srinivasan Bhaskar
Принадлежит: MICRON TECHNOLOGY, INC.

A method of forming a crystalline PrCaMnO(PCMO) material includes forming an amorphous PCMO material, crystallizing the amorphous PCMO material, and removing a portion of the crystalline PCMO material. A semiconductor structure including the crystalline PCMO material is also disclosed where the crystalline PCMO material has a thickness of less than about 50 nm. A method of forming a semiconductor device structure is also disclosed. 1. A semiconductor device structure , comprising:{'sub': 1-x', 'x', '3, 'a crystalline PrCaMnO(PCMO) material on a substrate, the crystalline PCMO material formed by a process comprising{'sub': 1-x', 'x', '3, 'forming an amorphous PrCaMnO(PCMO) material on a substrate, wherein x is a number from about 0.05 to about 0.95;'}crystallizing the amorphous PCMO material; andremoving a portion of the crystalline PCMO material such that a thickness of the crystalline PCMO material is less than about 50 nm.2. The semiconductor device structure of . further comprising at least one of an electrode claim 1 , a through-wafer interconnect claim 1 , a line claim 1 , a trace claim 1 , a wire claim 1 , and a via in or on the substrate.3. The semiconductor device structure of claim 1 , wherein the crystalline PCMO material comprises a thickness of between about 5 nm and about 35 nm.4. The semiconductor device structure of claim 1 , wherein the crystalline PCMO material comprises PrCaMnO claim 1 , PrCaMnO claim 1 , or PrCaMnO.5. The semiconductor device structure of claim 1 , wherein crystallizing the amorphous PCMO material comprises heating the amorphous PCMO material to a temperature of between about 400° C. and about 500° C.6. The semiconductor device structure of claim 1 , wherein the crystalline PCMO material comprises a thickness of about 10 nm.7. The semiconductor device structure of claim 1 , wherein the crystalline PCMO material comprises a layer of PCMO material.8. The semiconductor device structure of claim 1 , wherein the crystalline PCMO ...

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Номер записи: 22
30-05-2013 дата публикации

EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR ELEMENT, SEMICONDUCTOR ELEMENT, PN JUNCTION DIODE, AND METHOD FOR MANUFACTURING AN EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR ELEMENT

Номер: US20130134439A1
Автор: ICHIMURA Mikiya, MIYOSHI Makoto, Sugiyama Tomohiko, TANAKA Mitsuhiro
Принадлежит: NGK Insulators, Ltd.

Provided is an epitaxial substrate for use in a semiconductor element, having excellent characteristics and capable of suitably suppressing diffusion of elements from a cap layer. An epitaxial substrate for use in a semiconductor element, in which a group of group-III nitride layers are laminated on a base substrate such that a (0001) crystal plane of the group of group-III nitride layers is substantially in parallel with a substrate surface of the base substrate, includes: a channel layer made of a first group-III nitride having a composition of InAlGaN (x1+y1+z1=1, z1>0); a barrier layer made of a second group-III nitride having a composition of InAlN (x2+y2=1, x2>0, y2>0); an anti-diffusion layer made of AlN and having a thickness of 3 nm or more; and a cap layer made of a third group-III nitride having a composition of InAlGaN (x3+y3+z3=1, z3>0). 1. An epitaxial substrate for use in a semiconductor element , in which a group of group-III nitride layers are laminated on a base substrate such that a (0001) crystal plane of said group of group-III nitride layers is substantially in parallel with a substrate surface of said base substrate , said epitaxial substrate comprising:{'sub': x1', 'y1', 'z1, 'a channel layer made of a first group-III nitride having a composition of InAlGaN (x1+y1+z1=1, z1>0);'}{'sub': x2', 'y2, 'a barrier layer made of a second group-III nitride having a composition of InAlN (x2+y2=1, x2>0, y2>0);'}an anti-diffusion layer made of AlN and having a thickness of 3 nm or more; and{'sub': x3', 'y3', 'z3, 'a cap layer made of a third group-III nitride having a composition of InAlGaN (x3+y3+z3=1, z3>0).'}2. The epitaxial substrate according to claim 1 , whereina band gap of said second group-III nitride is larger than a band gap of said first group-III nitride.3. The epitaxial substrate according to claim 1 , wherein{'sub': x2', 'y2, 'said second group-III nitride is InAlN (x2+y2=1, 0.14≦x2≦0.24),'}{'sub': y3', 'z3, 'said third group-III nitride is ...

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Номер записи: 23
30-05-2013 дата публикации

MANUFACTURING METHODS FOR LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICES

Номер: US20130137224A1
Автор: Grote Bernhard H., Khan Tahir A., Khemka Vishnu K., Zhu Ronghua
Принадлежит: Freescale Semiconductor, Inc.

Fabrication processes for semiconductor devices are presented here. The device includes a support substrate, a buried oxide layer overlying the support substrate, a first semiconductor region located above the buried oxide layer and having a first conductivity type. The device also includes second, third, fourth, and fifth semiconductor regions. The second semiconductor region is located above the first semiconductor region, and it has a second conductivity type. The third semiconductor region is located above the second semiconductor region, and it has the first conductivity type. The fourth semiconductor region is located above the third semiconductor region, and it has the second conductivity type. The fifth semiconductor region extends through the fourth semiconductor region and the third semiconductor region to the second semiconductor region, and it has the second conductivity type. 1. A method of fabricating a semiconductor device on a semiconductor-on-insulator substrate comprising a support layer , a buried insulator layer overlying the support layer , and a layer of semiconductor material overlying the buried insulator layer , the method comprising:forming epitaxially grown semiconductor material overlying the layer of semiconductor material, the epitaxially grown semiconductor material having a first conductivity type, and at least a portion of the epitaxially grown semiconductor material serving as a first semiconductor region of the semiconductor device;forming a second semiconductor region in the epitaxially grown semiconductor material, the second semiconductor region located above the first semiconductor region and having a second conductivity type;forming a third semiconductor region in the epitaxially grown semiconductor material, the third semiconductor region located above the second semiconductor region and having the first conductivity type;forming a fourth semiconductor region in the epitaxially grown semiconductor material, the fourth ...

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Номер записи: 24
06-06-2013 дата публикации

MANUFACTURING METHOD FOR CRYSTALLINE SEMICONDUCTOR FILM, SEMICONDUCTOR DEVICE, AND DISPLAY DEVICE

Номер: US20130140573A1
Автор: NAKAMURA Yoshinobu
Принадлежит:

An object is to form a crystalline semiconductor film including a plurality of semiconductor regions with different average grain sizes by a simple manufacturing process. 1. A manufacturing method for a crystalline semiconductor film , to form crystalline semiconductor films including a plurality of semiconductor regions with different average grain sizes on an insulating substrate , the method comprising:a step of depositing a metal film on the insulating substrate;a step of patterning the metal film to form a first metal pattern and a second metal pattern with a smaller area than that of the first metal pattern;a step of depositing an insulating film so as to coat the first and second metal patterns;a step of depositing an amorphous semiconductor film on the insulating substrate;a first crystallization step of crystallizing the amorphous semiconductor film, to form a first crystalline semiconductor film; anda second crystallization step of crystallizing the first crystalline semiconductor film, to form a second crystalline semiconductor film, whereinthe second crystalline semiconductor film includesa first semiconductor region located above the first metal pattern and having substantially the same average grain size as an average grain size of the first crystalline semiconductor film, anda second semiconductor region located above the second metal pattern and having a larger average grain size than the average grain size of the first semiconductor region.2. The manufacturing method for a crystalline semiconductor film according to claim 1 , wherein the second crystallization step includes a step of irradiating the first crystalline semiconductor film with a laser beam.3. The manufacturing method for a crystalline semiconductor film according to claim 1 , wherein the first metal pattern includes a third metal pattern claim 1 , and a fourth metal pattern surrounding the third metal pattern.4. The manufacturing method for a crystalline semiconductor film according to ...

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Номер записи: 25
06-06-2013 дата публикации

Lateral Transistor Component and Method for Producing Same

Номер: US20130140632A1
Автор: Bertrams Thomas, Dahl Claus, FEICK Henning, LANDGRAF Erhard, Pribil Andreas
Принадлежит: INFINEON TECHNOLOGIES AG

A transistor component includes an active transistor region arranged in the semiconductor body. And insulation region surrounds the active transistor region in the semiconductor body in a ring-shaped manner. A source zone, a drain zone, a body zone and a drift zone are disposed in the active transistor region. The source zone and the drain zone are spaced apart in a lateral direction of the semiconductor body and the body zone is arranged between the source zone and the drift zone and the drift zone is arranged between the body zone and the drain zone. A gate and field electrode is arranged over the active transistor region. The dielectric layer has a first thickness in in a region near the body zone and a second thickness in a region near the drift zone. 1. A transistor component comprising:a semiconductor body;an active transistor region arranged in the semiconductor body;an insulation region surrounding the active transistor region in the semiconductor body in a ring-shaped manner;a source zone, a drain zone, a body zone and a drift zone in the active transistor region, wherein the source zone and the drain zone are spaced apart in a lateral direction of the semiconductor body and the body zone is arranged between the source zone and the drift zone and the drift zone is arranged between the body zone and the drain zone;a gate and field electrode that is arranged over the active transistor region, that overlaps the insulation region at least in a region near the drain zone and that is insulated from the active transistor region by a dielectric layer, the dielectric layer having a first thickness in in a region near the body zone and a second thickness in a region near the drift zone, the second thickness being greater than the first thickness, and wherein the gate and field electrode has a first contact opening above the drain zone; anda drain electrode making contact with the drain zone through the first contact opening.2. The transistor component as claimed in ...

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Номер записи: 26
06-06-2013 дата публикации

PSEUDO-SUBSTRATE FOR USE IN THE PRODUCTION OF SEMICONDUCTOR COMPONENTS AND METHOD FOR PRODUCING A PSEUDO-SUBSTRATE

Номер: US20130143038A1
Автор: Leuther Arnulf, Lösch Rainer, Tessmann Axel
Принадлежит: FRAUNHOFER-GESELLSCHAFT ZUR FORDERUNG DER ANGEWANDTEN FORSCHUNG E.V.

A pseudo-substrate () for use in the production of semiconductor components, having a carrier substrate () with a crystalline structure and a first buffer (), which is arranged on a surface of the carrier substrate (), if appropriate on further intervening intermediate layers, wherein the first buffer () is embodied as a single layer or as a multilayer system and includes, at least at the surface facing away from the carrier substrate (), arsenic (As) and at least one of the elements aluminum (Al) and indium (In). The invention is characterized in that a second buffer () is additionally arranged on a side of the first buffer () facing away from the carrier substrate (), if appropriate on further intervening intermediate layers, said second buffer being embodied as a single layer or as a multilayer system, wherein the second buffer () is embodied such that it includes, at a first surface facing the first buffer () arsenic and at least one of the elements aluminum and indium and comprises, at a second surface facing away from the first buffer () antimony (Sb) and at least one of the elements aluminum and indium, and wherein the second buffer is embodied with a decreasing proportion of arsenic and with an increasing proportion of antimony in each case proceeding from the first surface towards the second surface. The invention furthermore relates to a method for producing a pseudo-substrate (). 1111. A pseudo-substrate ( , ) for use in production of semiconductor components , comprising{'b': 2', '12', '3', '13, 'a carrier substrate (, ) having a crystalline structure, and a first buffer (, ) which is arranged on a surface of the carrier substrate, or on further intermediate layers lying therebetween,'}{'b': 3', '13', '2', '12, 'the first buffer (, ) being formed as a single layer or as a multilayer system and comprising arsenic (As) and at least one of the elements aluminum (Al) and indium (In) at least on a surface facing away from the carrier substrate (, ),'}{'b': 4 ...

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Номер записи: 27
13-06-2013 дата публикации

SOLID, MULTI-STATE MOLECULAR RANDOM ACCESS MEMORY

Номер: US20130148413A1
Автор: DE RUITER Graham, VAN DER BOOM Milko E.
Принадлежит: Yeda Research and Development Co. Ltd

A solid-state, multi-valued, molecular random access memory (RAM) device, comprising an electrically, optically and/or magnetically addressable unit, a memory reader, and a memory writer. The addressable unit comprises a conductive substrate; one or more layers of electrochromic, magnetic, redox-active, and/or photochromic materials deposited on the conductive substrate; and a conductive top layer deposited on top the one or more layers. The memory writer applies a plurality of predetermined values of potential biases or optical signals or magnetic fields to the unit, wherein each predetermined value applied results in a uniquely distinguishable optical, magnetic and/or electrical state of the unit, thus corresponding to a unique logical value. The memory reader reads the optical, magnetic and/or electrical state of the unit. 1. A solid-state , multi-valued , molecular random access memory (RAM) device , comprising: a. a conductive substrate;', 'b. one or more layers of electrochromic, magnetic, redox-active, and/or photochromic materials deposited on said conductive substrate;', 'c. a conductive top layer deposited on top of said one or more layers of (b);, '(i) an electrically, optically and/or magnetically addressable unit, comprising(ii) a memory writer that applies a plurality of predetermined values (1) of potential biases to said one or more layers of electrochromic, or redox-active materials; or (2) of optical signals to said one or more layers of photochromic materials; or (3) of magnetic fields to said one or more layers of magnetic materials; to the unit, wherein each predetermined value applied results in a uniquely distinguishable (1) optical state of said one or more layers of electrochromic, redox-active or photochromic materials; (2) magnetic state of said one or more layers of magnetic materials; or (3) electrical state of said one or more layers of electrochromic or redox-active materials; of said unit, and thus corresponds to a unique logical ...

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Номер записи: 28
13-06-2013 дата публикации

SEMICONDUCTOR DEVICE WITH FERRO-ELECTRIC CAPACITOR

Номер: US20130149796A1
Автор: Nakamura Ko, Wang Wensheng
Принадлежит: FUJITSU SEMICONDUCTOR LIMITED

A semiconductor device has a ferro-electric capacitor with small leak current and less process deterioration even upon miniaturization. The semiconductor device includes: a semiconductor element formed in a semiconductor substrate; lamination of an interlayer insulating film and a lower insulating shielding film having a hydrogen/moisture shielding function, the lamination being formed covering the semiconductor element; a conductive adhesion enhancing film formed above the lower insulating shielding film; and a ferro-electric capacitor including a lower electrode formed above the conductive adhesion enhancing film, a ferro-electric film formed on the lower electrode and being disposed within the lower electrode as viewed in plan, and an upper electrode formed on the ferro-electric film and being disposed within the ferro-electric film as viewed in plan, wherein the conductive adhesion enhancing film has a function of improving adhesion of the lower electrode and reducing leak current of the ferro-electric capacitor. 111.-. (canceled)12. A method for manufacturing a semiconductor device comprising steps of:(a) depositing an insulating oxygen barrier layer and an interlayer insulating film on a semiconductor substrate formed with a transistor;(b) forming an insulating hydrogen diffusion preventive film above said interlayer insulating film;(c) forming a conductive adhesion enhancing film containing Ti above said insulating hydrogen diffusion preventive film;(d) forming a ferro-electric capacitor including a lamination of a lower electrode, a ferro-electric film and an upper electrode, with an upper layer not protruding outside a lower layer, above said conductive adhesion enhancing film; and(e) performing annealing in an oxygen-containing atmosphere after said step (d).13. The method for manufacturing a semiconductor device according to claim 12 , wherein said step (b) forms claim 12 , by physical deposition or chemical deposition claim 12 , a film made of at least ...

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Номер записи: 29
20-06-2013 дата публикации

Transistor, Method for Fabricating the Transistor, and Semiconductor Device Comprising the Transistor

Номер: US20130153913A1
Автор: Liang Qingqing, Zhong Huicai, Zhu Huilong
Принадлежит:

A transistor, a method for fabricating a transistor, and a semiconductor device comprising the transistor are disclosed in the present invention. The method for fabricating a transistor may comprise: providing a substrate and forming a first insulating layer on the substrate; defining a first device area on the first insulating layer; forming a spacer surrounding the first device area on the first insulating layer; defining a second device area on the first insulating layer, wherein the second device area is isolated from the first device area by the spacer; and forming transistor structures in the first and second device area, respectively. The method for fabricating a transistor of the present invention greatly reduces the space required for isolation, significantly decreases the process complexity, and greatly reduces fabricating cost. 1. A method for fabricating a transistor , comprising:providing a substrate and forming a first insulating layer on the substrate;defining a first device area on the first insulating layer;forming a spacer surrounding the first device area on the first insulating layer;defining a second device area on the first insulating layer, wherein the second device area is isolated from the first device area by the spacer; andforming transistor structures in the first and second device area, respectively.2. The method according to claim 1 , wherein the step of defining a first device area on the first insulating layer comprises:sequentially depositing a first semiconductor layer and a first mask layer on the first insulating layer; andpatterning the first semiconductor layer and the first mask layer to define the first device area.3. The method according to claim 2 , wherein the step of patterning the first semiconductor layer and the first mask layer comprises:applying a photoresist layer onto the first mask layer;forming a patterned photoresist layer by photolithography; andetching away a portion of the first mask layer and a portion of the ...

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Номер записи: 30
20-06-2013 дата публикации

Semiconductor Device

Номер: US20130153968A1
Автор: Heringa Anco, Mueller Markus
Принадлежит:

A semiconductor device and a method of making the same. The device includes a semiconductor substrate having an AlGaN layer on a GaN layer. The device also includes first contact and a second contact. The average thickness of the AlGaN layer varies between the first contact and the second contact, for modulating the density of an electron gas in the GaN layer between the first contact and the second contact. 1. A semiconductor device comprising:a semiconductor substrate including an AlGaN layer on a GaN layer;a first contact, anda second contact,wherein the average thickness of the AlGaN layer varies between the first contact and the second contact, for modulating the density of an electron gas in the GaN layer between the first contact and the second contact.2. The device of claim 1 , wherein at least part of an upper surface of the AlGaN layer includes a plurality of recesses for varying an average thickness of the AlGaN layer.3. The device of claim 2 , wherein a density of the recesses varies for varying the average thickness of the AlGaN layer.4. The device of claim 2 , wherein the depth of the recesses is between 30% and 100% of the local thickness of the AlGaN layer.5. The device of claim 2 , wherein the recesses are arranged in a regular array.6. The device of claim 2 , wherein the recesses comprise grooves.7. The device of claim 1 , wherein the average thickness T of the AlGaN layer between the first contact and the second contact is in the range 10 nm Подробнее

Номер записи: 31
20-06-2013 дата публикации

METHODS OF FORMING A SEMICONDUCTOR DEVICE

Номер: US20130157416A1
Автор: Hebert Francois, Hoopingarner Kevin, Jerome Rick Carlton, McLachlan Craig
Принадлежит: INTERSIL AMERICAS INC.

A method and structure for a semiconductor device, the device including a handle wafer, a diamond layer formed directly on a front side of the handle wafer, and a thick oxide layer formed directly on a back side of the handle wafer, the oxide of a thickness to counteract tensile stresses of the diamond layer. Nitride layers are formed on the outer surfaces of the diamond layer and thick oxide layer and a polysilicon is formed on outer surfaces of the nitride layers. A device wafer is bonded to the handle wafer to form the semiconductor device. 1. A method of forming a semiconductor device , comprising:on a device wafer, depositing a thin nitride layer between a diamond layer and the device wafer, wherein the thin nitride layer comprises a thickness of about 500 Å to about 3000 Å;depositing a polysilicon layer on the device wafer;planarizing the polysilicon on an active side of the device wafer; andattaching the planarized side of the device wafer to a handle wafer to form the semiconductor device.2. The method of claim 1 , wherein the thin nitride layer is deposited to thickness of about 1000 Å.3. The method of claim 1 , further comprising:depositing polysilicon on the handle wafer side of the semiconductor device; andpolishing a device side of the semiconductor device.4. The method of claim 3 , wherein polishing comprises polishing the device side of the semiconductor device to within about 0.1 to about 100 μm of a diamond-silicon interface of the device wafer.6. The method of claim 5 , wherein growing the pad oxide comprises growing to a thickness of about 650 Å.7. The method of claim 5 , wherein depositing the first nitride layer comprises depositing to a thickness of about 500 to about 3000 Å.8. The method of claim 7 , wherein depositing the first nitride layer comprises depositing to a thickness of about 1200 Å.9. The method of claim 5 , wherein growing the diamond layer comprises growing to a thickness of about 1.5 μm.10. The method of claim 5 , wherein ...

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Номер записи: 32
20-06-2013 дата публикации

SUBSTRATE PROCESSING APPARATUS, METHOD OF PROCESSING SUBSTRATE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20130157474A1
Автор: Fukuda Masanao, Megawa Yasuhiro, Minami Masayoshi, SASAKI Takafumi, YUASA Kazuhiro
Принадлежит: HITACHI KOKUSAI ELECTRIC INC.

An oxygen-containing gas and a hydrogen-containing gas are supplied into a pre-reaction chamber heated to a second temperature and having the pressure set to less than an atmospheric pressure, and a reaction is induced between both gases in the pre-reaction chamber to generate reactive species, and the reactive species are supplied into the process chamber and exhausted therefrom, in which a substrate heated to the first temperature is housed and the pressure is set to less than the atmospheric pressure, and processing is applied to the substrate by the reactive species, with the second temperature set to be not less than the first temperature at this time. 1. A substrate processing apparatus , comprising:a process chamber configured to house a substrate therein;a first heating source configured to heat a substrate in the process chamber to a first temperature;a pre-reaction chamber in which a reaction is induced among a plurality of kinds of gases;a second heating source configured to heat the pre-reaction chamber to a second temperature;an oxygen-containing gas supply system configured to supply an oxygen-containing gas into the pre-reaction chamber;a hydrogen-containing gas supply system configured to supply a hydrogen-containing gas into the pre-reaction chamber;a connection part configured to connect the pre-reaction chamber and the process chamber;a pressure adjusting part configured to adjust a pressure in the process chamber and the pre-reaction chamber to a pressure of less than an atmospheric pressure; anda control part configured to control the first heating source, the second heating source, the oxygen-containing gas supply system, the hydrogen-containing gas supply system, and the pressure adjusting part, so that the oxygen-containing gas and the hydrogen-containing gas are supplied into the pre-reaction chamber heated to the second temperature and having the pressure set to less than the atmospheric pressure, and a reaction is induced between both ...

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Номер записи: 33
27-06-2013 дата публикации

ELECTRO-OPTIC DISPLAYS, AND COMPONENTS FOR USE THEREIN

Номер: US20130161663A1
Автор: Amundson Karl R., Chen Yu, Drzaic Paul S., Duthaler Gregg M., KAZLAS PETER T., Ritenour Andrew P.
Принадлежит: E INK CORPORATION

An electro-optic display comprises a substrate (), non-linear devices () disposed substantially in one plane on the substrate (), pixel electrodes () connected to the non-linear devices (), an electro-optic medium () and a common electrode () on the opposed side of the electro-optic medium () from the pixel electrodes (). The moduli of the various parts of the display are arranged so that, when the display is curved, the neutral axis or neutral plane lies substantially in the plane of the non-linear devices (). 1. A backplane for an electro-optic display , the backplane comprising a plurality of pixel electrodes , and a ring diode associated with each pixel electrode , each ring diode comprising at least one organic layer.2. A backplane according to further comprising at least one column electrode in electrical contact with a plurality of the ring diodes claim 1 , the column electrode being narrower than the layer of each ring diode in immediate contact with the column electrode.3. An electro-optic display comprising a backplane according to and a layer of electro-optic medium disposed adjacent the backplane such that by varying the voltages on the pixel electrodes claim 1 , the optical state of the electro-optic medium can be varied claim 1 , the electro-optic medium having a threshold for switching.4. A backplane for an electro-optic display claim 1 , the backplane comprising a plurality of pixel electrodes claim 1 , a diode associated with each pixel electrode claim 1 , and at least one column electrode in electrical contact with a plurality of the diodes claim 1 , the column electrode being narrower than the layer of each diode in immediate contact therewith.5. A backplane according to wherein the layer of each diode in immediate contact with the column electrode is organic.6. A backplane according to wherein at least one diode is a metal-insulator-metal diode.7. An electro-optic display comprising a backplane according to and a layer of electro-optic medium ...

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Номер записи: 34
27-06-2013 дата публикации

Buried Power Grid Designs and the Methods for Forming Buried Power Grids in CMOS Technologies for Improved Radiation Hardness

Номер: US20130161758A1
Автор: Rockett Leonard Richard
Принадлежит:

Buried power grids are designed as a fine mesh-type pattern of heavily doped diffusion regions with neutral epitaxial region cores to allow the uninterrupted electrical continuity of the epitaxial substrate, thus avoiding floating substrate effects. The buried power grids are formed beneath the epitaxial substrate surface and are powered via electrical contact to adjacent well regions. The buried power grids, when powered, form strongly reverse-biased buried pn junction regions that restrict radiation induced excess charge collection volumes and draw excess charge away from sensitive circuit nodes The method for forming buried power grids requires no uniquely complex process steps and no critical mask alignments to the CMOS devices on the epitaxial top surface. Buried power grids provide enhanced protection to sensitive circuit nodes against logic upsets due to single-particle and prompt dose radiation events and thereby improve the radiation hardness and decreases the latchup susceptibility of CMOS circuits. 1. A semiconductor device comprising:a heavily doped substrate semiconductor material of first conductivity type; andan epitaxial layer of lightly doped semiconductor material of first conductivity type formed on the heavily doped substrate material having an first impurity concentration to function as the common substrate node of a plurality of first conductivity type CMOS transistors to be built on its surface and with an epitaxial layer thickness to fully contain the subsequent formation of well regions within the epitaxial layer; andfirst well regions of second conductivity type formed within the epitaxial layer that have a second impurity concentration greater than the first impurity concentration of the epitaxial layer and which function as the common substrate nodes of a plurality of complementary second conductivity type CMOS transistors to be built on the surface of the first well regions and with shallow well depth that supports the integrity of each ...

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Номер записи: 35
27-06-2013 дата публикации

METHOD, APPARATUS FOR HOLDING AND TREATMENT OF A SUBSTRATE

Номер: US20130164939A1
Автор: Lackner Gerald, Maier Christian, Santos Rodriguez Francisco Javier
Принадлежит: INFINEON TECHNOLOGIES AG

Some embodiments discussed relates to an apparatus for holding a substrate, comprising a body with a surface for a semiconductor wafer to rest on, with the surface having a first surface area on which a first area of the semiconductor wafer can rest, and a second surface area on which a second area of the semiconductor wafer can rest, wherein the second surface area protrudes with respect to the first surface area. 1. A method comprising:placing a semiconductor wafer in contact with a substrate holder at a first location and a second location of the substrate holder, wherein the second location projects with respect to the first location; andprocessing the semiconductor wafer.2. The method of claim 1 , further comprising producing a reduced pressure between the semiconductor wafer and the substrate holder.3. The method of claim 1 , further comprising moving the second location with respect to the first location until the first location is in contact with the semiconductor wafer and the second location is in contact with the semiconductor wafer.4. The method of claim 1 , further comprising forcing the second location away from the first location.5. The method of claim 4 , wherein forcing the second location away from the first location further comprises forcing the second location away from the first location with springs.6. The method of claim 1 , further comprising pressing a contact needle in a direction of the semiconductor wafer.7. The method of claim 1 , further comprising pressing a plurality of contact needles in a direction of the semiconductor wafer.8. The method of claim 1 , wherein placing the semiconductor wafer in contact with the substrate holder further comprises placing the semiconductor wafer in contact with the substrate holder at a first surface area and a second surface area of the substrate holder claim 1 , wherein the second surface area projects with respect to the first surface area.9. The method of claim 1 , wherein processing the ...

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Номер записи: 36
27-06-2013 дата публикации

Substrate Processing Apparatus and Method of Manufacturing Semiconductor Device

Номер: US20130164943A1
Автор: KOSHI Yasunobu, Suzaki Kenichi, Yoshino Akihito
Принадлежит: HITACHI KOKUSAI ELECTRIC INC.

The substrate processing apparatus includes a reaction chamber configured to accommodate a substrate; a first gas supply unit configured to supply a first process gas containing a silicon element to the substrate; a second gas supply unit configured to supply a second process gas containing a silicon element and a chlorine element to the substrate; an exhaust unit configured to exhaust the first process gas and the second process gas; a cleaning gas bypass supply unit configured to supply a cleaning gas to the exhaust unit; a cleaning monitoring unit installed in the exhaust unit; a gas flow rate control unit configured to adjust an amount of the cleaning gas supplied; and a main control unit configured to control the gas flow rate control unit in response to a signal received from the cleaning gas monitoring unit. 1. A substrate processing apparatus comprising:a reaction chamber configured to accommodate a substrate;a first gas supply unit configured to supply a first process gas containing a silicon element to the substrate;a second gas supply unit configured to supply a second process gas containing a silicon element and a chlorine element to the substrate;an exhaust unit configured to exhaust the first process gas and the second process gas;a cleaning gas bypass supply unit configured to supply a cleaning gas to the exhaust unit;a cleaning monitoring unit installed in the exhaust unit;a gas flow rate control unit configured to adjust an amount of the cleaning gas supplied; anda main control unit configured to control the gas flow rate control unit in response to a signal received from the cleaning gas monitoring unit.2. The apparatus according to claim 1 , wherein the cleaning monitoring unit comprises a temperature monitoring unit configured to measure a temperature of the exhaust unit.3. The apparatus according to claim 1 , wherein the main control unit controls the gas flow rate control unit and the exhaust unit to close a main valve of the exhaust unit and ...

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Номер записи: 37
27-06-2013 дата публикации

Methods Of Forming Openings And Methods Of Patterning A Material

Номер: US20130164944A1
Автор: Sipani Vishal, Yang Ming-Chuan, Zhou Baosuo
Принадлежит: MICRON TECHNOLOGY, INC.

Some embodiments include methods of forming openings. For instance, a construction may have a material over a plurality of electrically conductive lines. A plurality of annular features may be formed over the material, with the annular features crossing the lines. A patterned mask may be formed over the annular features, with the patterned mask leaving segments of the annular features exposed through a window in the patterned mask. The exposed segments of the annular features may define a plurality of openings, and such openings may be transferred into the material to form openings extending to the electrically conductive lines. 122-. (canceled)23. A method of patterning a material , comprising:forming a first patterned mask over the material, the first patterned mask comprising a plurality of spaced-apart first features, the spaced-apart first features having lateral peripheries; the first features being parallel to one another and being spaced from one another by a first distance;forming spacers around the lateral peripheries of the spaced apart first features;the spacers and first features together forming spaced apart second features of a second patterned mask; the second features being spaced from one another by a second distance which is less than the first distance;forming a third patterned mask over the second patterned mask; the third patterned mask having a trench extending therethrough to exposed segments of the second features; the second and third patterned masks together defining a plurality of openings; andtransferring the openings into the material.24. The method of wherein the spacers comprise silicon dioxide; and wherein one of the first and second patterned masks comprises photoresist.25. The method of wherein the material is an oxide-containing material.26. The method of wherein the material is a carbon-containing material.27. The method of wherein the transferring of the openings into the material forms contact openings that extend through the ...

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Номер записи: 38
04-07-2013 дата публикации

NITRIDE BASED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20130168688A1
Автор: KIM Ki Se, LEE Jae Hoon
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A nitride based semiconductor device includes a first metallic junction layer, a Schottky junction layer on the first metallic junction layer, a first group III nitride semiconductor layer on the Schottky junction layer, a first insulating pattern layer on the first group III nitride semiconductor layer, the first insulating layer pattern including curved protrusions, a second group III nitride semiconductor layer laterally grown on the first group III nitride semiconductor layer, a first type group III nitride semiconductor layer on the second group III nitride semiconductor layer, the first type group III nitride semiconductor layer being simultaneously doped with aluminum (Al) and silicon (Si), an ohmic junction layer formed on the first type group III nitride semiconductor layer, a second metallic junction layer on the ohmic junction layer, and a metallic supporting substrate on the second metallic junction layer. 1. A nitride based semiconductor device , comprising:a first metallic junction layer;a Schottky junction layer on the first metallic junction layer;a first group III nitride semiconductor layer on the Schottky junction layer;a first insulating pattern layer on the first group III nitride semiconductor layer, the first insulating pattern layer including curved protrusions;a second group III nitride semiconductor layer laterally grown on the first group III nitride semiconductor layer that is exposed through the first insulating pattern layer;a first type group III nitride semiconductor layer on the second group III nitride semiconductor layer, the first type group III nitride semiconductor layer being simultaneously doped with aluminum (Al) and silicon (Si);an ohmic junction layer on the first type group III nitride semiconductor layer;a second metallic junction layer on the ohmic junction layer; anda metallic supporting substrate on the second metallic junction layer.2. The nitride based semiconductor device as claimed in claim 1 , wherein the second ...

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Номер записи: 39
04-07-2013 дата публикации

POLYCRYSTALLINE ALUMINUM NITRIDE BASE MATERIAL FOR CRYSTAL GROWTH OF GaN-BASE SEMICONDUCTOR AND METHOD FOR MANUFACTURING GaN-BASE SEMICONDUCTOR USING THE SAME

Номер: US20130168692A1
Автор: Komorita Hiroshi, Nakayama Noritaka, Takanami Kentaro
Принадлежит:

There is provided a polycrystalline aluminum nitride substrate that is effective in growing a GaN crystal. The polycrystalline aluminum nitride base material for use as a substrate material for grain growth of GAN-base semiconductors, contains 1 to 10% by weight of a sintering aid component and has a thermal conductivity of not less than 150 W/m·K, the substrate having a surface free from recesses having a maximum diameter of more than 200 μm. 1. A polycrystalline aluminium nitride base material for use as a substrate material for grain growth of GaN-base semiconductors , the polycrystalline aluminium nitride base material containing 1 to 10% by weight of a sintering aid component and having a thermal conductivity of not less than 150 W/m·K , and the substrate having a surface free from recesses having a maximum diameter of more than 200 μm.2. The polycrystalline aluminum nitride base material according to claim 1 , wherein the sintering aid component comprises one or more materials selected from the group consisting of rare earth elements claim 1 , rare earth element oxides claim 1 , and rare earth element-aluminum oxides.3. The polycrystalline aluminum nitride substrate according to claim 1 , wherein the recesses are any one of pores claim 1 , traces after dropping of AlN crystal grains claim 1 , and traces after dropping of the sintering aid component.4. The polycrystalline aluminum nitride substrate according to claim 1 , wherein the maximum diameter of the recesses is not more than 50 μm.5. The polycrystalline aluminum nitride substrate according to claim 1 , which has a surface roughness (Ra) of not more than 0.1 μm.6. The polycrystalline aluminum nitride base material according to claim 1 , which comprises an aluminum nitride crystal and a grain boundary phase claim 1 , grains of the aluminum nitride crystal having a mean diameter of not more than 7 μm.7. The polycrystalline aluminum nitride base material according to claim 1 , wherein the substrate has a ...

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Номер записи: 40
04-07-2013 дата публикации

PROTECTIVE-FILM-ATTACHED COMPOSITE SUBSTRATE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20130168693A1
Автор: Hachigo Akihiro, Matsubara Hideki, Satoh Issei, Yamamoto Yoshiyuki, Yoshida Hiroaki
Принадлежит: Sumitomo Electric Industries, Ltd.

A protective-film-attached composite substrate includes a support substrate, an oxide film disposed on the support substrate, a semiconductor layer disposed on the oxide film, and a protective film protecting the oxide film by covering a portion that is a part of the oxide film and covered with none of the support substrate and the semiconductor layer. A method of manufacturing a semiconductor device includes the steps of: preparing the protective-film-attached composite substrate; and epitaxially growing, on the semiconductor layer of the protective-film-attached composite substrate, at least one functional semiconductor layer causing an essential function of a semiconductor device to be performed. Thus, there are provided a protective-film-attached composite substrate having a large effective region where a high-quality functional semiconductor layer can be epitaxially grown, and a method of manufacturing a semiconductor device in which the protective-film-attached composite substrate is used. 1. A protective-film-attached composite substrate comprising: a support substrate; an oxide film disposed on said support substrate; a semiconductor layer disposed on said oxide film; and a protective film protecting said oxide film by covering a portion that is a part of said oxide film and covered with none of said support substrate and said semiconductor layer.2. The protective-film-attached composite substrate according to claim 1 , wherein said oxide film is at least one selected from the group consisting of TiOfilm claim 1 , SrTiOfilm claim 1 , indium tin oxide film claim 1 , antimony tin oxide film claim 1 , ZnO film claim 1 , and GaOfilm.3. The protective-film-attached composite substrate according to claim 2 , wherein at least one of said support substrate and said semiconductor layer is formed of a group III nitride.4. The protective-film-attached composite substrate according to claim 1 , wherein at least one of said support substrate and said semiconductor layer ...

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Номер записи: 41
04-07-2013 дата публикации

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF PROCESSING SUBSTRATE, SUBSTRATE PROCESSING APPARATUS, AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM

Номер: US20130171838A1
Автор: Okuda Kazuyuki
Принадлежит: HITACHI KOKUSAI ELECTRIC INC.

Provided is a method of manufacturing a semiconductor device capable of forming a nitride layer having high resistance to hydrogen fluoride at low temperatures. The method includes forming a nitride film on a substrate by performing a cycle a predetermined number of times, the cycle including supplying a source gas to the substrate, supplying a plasma-excited hydrogen-containing gas to the substrate, supplying a plasma-excited or thermally excited nitriding gas to the substrate, and supplying at least one of a plasma-excited nitrogen gas and a plasma-excited rare gas to the substrate. 1. A method of manufacturing a semiconductor device , the method comprising forming a nitride film on a substrate by performing a cycle a predetermined number of times , the cycle including:(a) supplying a source gas to the substrate;(b) supplying a plasma-excited hydrogen-containing gas to the substrate;(c) supplying a plasma-excited or thermally excited nitriding gas to the substrate; and(d) supplying at least one of a plasma-excited nitrogen gas and a plasma-excited rare gas to the substrate.2. The method of claim 1 , wherein the step (b) is performed during one of a time period after the step (a) and a time period after the step (c) claim 1 , andthe step (d) is performed during one of the time period after the step (a) and the time period after the step (c) other than the time period where the step (b) is performed.3. The method of claim 1 , wherein the step (b) is performed during one of a time period after the step (a) where a supply of the plasma-excited or thermally excited nitriding gas is suspended and a time period after the step (c) where a supply of the source gas is suspended claim 1 , andthe step (d) is performed during one of the time period after the step (a) where the supply of the plasma-excited or thermally excited nitriding gas is suspended and the time period after the step (c) where the supply of the source gas is suspended other than the time period where the ...

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Номер записи: 42
11-07-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE

Номер: US20130177997A1
Автор: Wang Wensheng
Принадлежит: FUJITSU SEMICONDUCTOR LIMITED

An upper electrode of a ferroelectric capacitor has a first layer formed of a first oxide expressed by a chemical formula AO(A: metal, O: oxygen) using a stoichiometric composition parameter x, and expressed by a chemical formula AOusing a actual composition parameter x, and a second layer formed of a second oxide, formed on the first layer, expressed by a chemical formula BO(B: metal) using a stoichiometric composition parameter y and expressed by a chemical formula BOusing a actual composition parameter y, which includes at least one of stone-wall crystal and column crystal. 1. A method of manufacturing a semiconductor device , comprising:forming a lower electrode over a semiconductor substrate;forming a ferroelectric film on the lower electrode;forming a first conductive oxide film on the ferroelectric film; andforming a second conductive oxide film on the first conductive oxide film;wherein the first conductive oxide film is formed under a condition that a rate of an oxygen flow rate to a an inert gas flow rate is smaller than a rate of an oxygen flow rate to a an inert gas flow rate to form the second conductive oxide film, andthe second conductive oxide film is formed under a condition that a temperature of the semiconductor substrate is controlled within a range in which at least one of stone-wall microcrystal oxide and column microcrystal oxide is formed.2. The method of claim 1 , whereinforming a third layer, which is formed of one of noble metal, alloy including noble metal, and oxide of at least one of noble metal and alloy including noble metal, on the second conductive oxide film.3. The method of claim 1 , whereinafter forming the ferroelectric film but before forming the first conductive oxide film,annealing the ferroelectric film at a first temperature in an atmosphere including inert gas and oxidizing gas; andcrystallizing the ferroelectric film by annealing the ferroelectric film at a second temperature higher than the first temperature in an ...

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Номер записи: 43
18-07-2013 дата публикации

LASER MICRO/NANO PROCESSING SYSTEM AND METHOD

Номер: US20130183833A1
Автор: Cao Hongzhong, Chen Shu, Dong Xianzi, Duan Xuanming, Zhao Zhensheng
Принадлежит: Technical Institute of Physics and Chemistry of the Chinese Academy of Sciences

A laser micro/nano processing system () comprises: a laser light source used to provide a first laser beam having a first wavelength and a second laser beam having a second wavelength different from the first wavelength, with the pulse width of the first laser beam being in the range from a nanosecond to a femtosecond; an optical focusing assembly used to focus the first laser beam and the second laser beam to the same focal point; and a micro mobile platform () controlled by a computer. Also disclosed are a method for micro/nano-processing photosensitive materials with a laser and a method for fabricating a device with a micro/nano structure using laser two-photon direct writing technology. In the system and methods, spatial and temporal overlapping of two laser beams is utilized, so as to obtain a micro/nano structure with a processing resolution higher than that of a single laser beam, using an average power lower than that of a single laser beam. 1. A laser micro/nano fabrication system , comprising:a laser light source for providing a first laser beam having a first wavelength and a second laser beam having a second wavelength being different from the first wavelength, the first laser beam having a pulse width in range of nanosecond to femtosecond;an optical focusing assembly for focusing the first laser beam and the second laser beam to a same focal point; anda computer controlled micromovement stage.2. The laser micro/nano fabrication system of claim 1 , wherein the first laser beam has a repetition frequency in range of 1 Hz-200 MHz claim 1 , and a wavelength in range of 157 nm-1064 nm.3. The micro/nano fabrication system of claim 1 , whereinThe second laser beam has a pulse width in range of nanosecond to femtosecond, andthe system further comprises a optical delay assembly for adjusting the optical path of the first laser beam or the optical path of the second laser beam such that the lag between the times when the first laser beam and the second laser ...

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Номер записи: 44
25-07-2013 дата публикации

Asymmetrical RF Drive for Electrode of Plasma Chamber

Номер: US20130186859A1
Автор: CHOI Soo Young, KUDELA Jozef, SORENSEN Carl A., WHITE John M.
Принадлежит: Applied Materials, Inc. a corporation of the State of Delaware, U.S.A.

RF power is coupled to one or more RF drive points (-) on an electrode (-) of a plasma chamber such that the level of RF power coupled to the RF drive points (--) on the half () of the electrode that is closer to the workpiece passageway () exceeds the level of RF power coupled to the RF drive points (-), if any, on the other half () of the electrode. Alternatively, RF power is coupled to one or more RF drive points on an electrode of a plasma chamber such that the weighted mean of the drive point positions is between the center () of the electrode and the workpiece passageway. The weighted mean is based on weighting each drive point position by the time-averaged level of RF power coupled to that drive point position. The invention offsets an increase in plasma density that otherwise would exist adjacent the end of the electrode closest to the passageway. 19-. (canceled)10. Apparatus for coupling RF power to a plasma chamber comprising:a plasma chamber having a workpiece passageway;an electrode positioned so as to couple electrical power from the electrode to a plasma within the plasma chamber, wherein a first half of the electrode is closer to the workpiece passageway than a second half of the electrode; andone or more RF power supplies;wherein the first half of the electrode includes one or more RF drive points that are connected to receive RF power from the one or more RF power supplies; andwherein the second half of the electrode includes no RF drive points that are connected to receive RF power.11. The apparatus of claim 10 , wherein the electrode further comprises:an RF drive point, located at the center of the electrode, connected to receive RF power from the one or more RF power supplies.12. The apparatus of claim 10 , wherein the electrode further comprises:one or more RF drive points that are connected to receive RF power from the one or more RF power supplies and that are positioned on the geometric boundary between the first and second halves of the ...

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Номер записи: 45
25-07-2013 дата публикации

LIQUID PROCESSING APPARATUS, LIQUID PROCESSING METHOD, AND STORAGE MEDIUM

Номер: US20130189852A1
Автор: Okada Soichiro, Yoshida Yuichi, Yoshihara Kousuke
Принадлежит: TOKYO ELECTRON LIMITED

A solvent such as PGMEA is coated on a wafer in advance to easily spread resist liquid onto the wafer on a spin chuck. Before coating, the solvent supplied from a solvent supply source is stored in a distill tank first, the solvent is heated by a heating unit to be evaporated, and the evaporated solvent is cooled by a cooler, thereby performing the purification of the solvent by distillation. Therefore, particles among the solvent are removed. The purified solvent is stored in a storage tank first, and then supplied to a solvent nozzle above the spin chuck from a solvent supplying line. And then, the solvent is coated on the wafer by ejecting the solvent from the solvent nozzle to the wafer. Further, the distill tank is cleaned periodically to suppress the increase of the concentration of the particles in the solvent. 1. A liquid processing apparatus comprising:a substrate holding unit configured to hold a substrate horizontally;a processing liquid nozzle configured to perform a liquid processing with respect to the substrate horizontally held by the substrate holding unit by supplying a processing liquid from a processing liquid supply source;an evaporating unit configured to evaporate the processing liquid supplied from the processing liquid supply source to obtain vapor;a cooling unit configured to cool and liquefy the vapor of the processing liquid obtained from the evaporating unit;a storage tank configured to store the processing liquid obtained by the cooling of the cooling unit; anda liquid sending mechanism configured to send the processing liquid within the storage tank to the processing liquid nozzle.2. The liquid processing apparatus of claim 1 , further comprising a resist nozzle configured to supply resist liquid with respect to the substrate held by the substrate holding unit claim 1 ,wherein the processing liquid is a solvent that is ejected to the substrate before supplying the resist liquid to the substrate.3. The liquid processing apparatus of ...

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Номер записи: 46
01-08-2013 дата публикации

Plasma processing device

Номер: US20130192759A1
Автор: Akinori Ebe, Yuichi Setsuhara
Принадлежит: EMD Corp, Osaka University NUC

A plasma processing device according to the present invention includes a plasma processing chamber, a plasma producing chamber communicating with the plasma processing chamber, a radio-frequency antenna for producing plasma, a plasma control plate for controlling the energy of electrons in the plasma, as well as an operation rod and a moving mechanism for regulating the position of the plasma control plate. In this plasma processing device, the energy distribution of the electrons of the plasma produced in the plasma producing chamber can be controlled by regulating the distance between the radio-frequency antenna 16 and the plasma control plate by simply moving the operation rod in its longitudinal direction by the moving mechanism. Therefore, a plasma process suitable for the kind of gas molecules to be dissociated and/or their dissociation energy can be easily performed.

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Номер записи: 47
01-08-2013 дата публикации

Method for Stressing a Thin Pattern and Transistor Fabrication Method Incorporating Said Method

Номер: US20130196456A1
Автор: François Andrieu, Jean-Charles Barbe, Simeon MORVAN
Принадлежит: Commissariat a lEnergie Atomique et aux Energies Alternatives CEA

A method for stressing a pattern having a pattern surface, in a layer of semiconductive material that can be silicon on the surface of a stack of layers generated on the surface of a substrate, said stack comprising at least one stress layer of alloy Si x Ge y with x and y being molar fractions, and a buried layer of silicon oxide, comprises: etching at the periphery of a surface of dimensions greater than said pattern surface, of the buried layer of silicon oxide and layer of alloy Si x Ge y over a part of the depth of said layer of alloy; the buried layer of silicon oxide being situated between said layer of semiconductive material and said stress layer of alloy Si x Ge y . In a transistor structure, etching at the periphery of said surface obtains a pattern thus defined having dimensions greater than the area of interest situated under the gate of the transistor.

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Номер записи: 48
01-08-2013 дата публикации

Slotted electrostatic shield modification for improved etch and cvd process uniformity

Номер: US20130196510A1
Автор: Andreas Kadavanich, Daniel J. Devine, Rene George, Stephen E. Savas
Принадлежит: Mattson Technology Inc

A more uniform plasma process is implemented for treating a treatment object using an inductively coupled plasma source which produces an asymmetric plasma density pattern at the treatment surface using a slotted electrostatic shield having uniformly spaced-apart slots. The slotted electrostatic shield is modified in a way which compensates for the asymmetric plasma density pattern to provide a modified plasma density pattern at the treatment surface. A more uniform radial plasma process is described in which an electrostatic shield arrangement is configured to replace a given electrostatic shield in a way which provides for producing a modified radial variation characteristic across the treatment surface. The inductively coupled plasma source defines an axis of symmetry and the electrostatic shield arrangement is configured to include a shape that extends through a range of radii relative to the axis of symmetry.

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Номер записи: 49
01-08-2013 дата публикации

OFF-ANGLED HEATING OF THE UNDERSIDE OF A SUBSTRATE USING A LAMP ASSEMBLY

Номер: US20130196514A1
Автор: BALASUBRAMANYAM CHANDRASEKHAR, EWERT Maurice E., KELKAR Umesh M., Ranish Joseph M., SUBRAMANI Anantha
Принадлежит: Applied Materials, Inc.

Disclosed are method and apparatus for treating a substrate. The apparatus is a dual-function process chamber that may perform both a material process and a thermal process on a substrate. The chamber has an annular radiant source disposed between a processing location and a transportation location of the chamber. Lift pins have length sufficient to maintain the substrate at the processing location while the substrate support is lowered below the radiant source plane to afford radiant heating of the substrate. A method of processing a substrate having apertures formed in a first surface thereof includes depositing material on the first surface in the apertures and reflowing the material by heating a second surface of the substrate opposite the first surface. A second material can then be deposited, filling the apertures partly or completely. Alternately, a cyclical deposition/reflow process may be performed. 1. A method of treating a substrate , comprising:positioning a substrate on a substrate support in a processing chamber;depositing a first material over a first surface of the substrate in the processing chamber; andirradiating a second surface of the substrate opposite the first surface in the processing chamber.2. The method of claim 1 , wherein depositing the first material comprises performing a sputtering process.3. The method of claim 1 , further comprising depositing a second material over the first material in the processing chamber.4. The method of claim 1 , wherein irradiating a second surface of the substrate comprises positioning the substrate above the substrate support and energizing a radiant heat source.5. The method of claim 4 , wherein positioning the substrate above the substrate support comprises elevating the substrate with one or more lift pins.6. The method of claim 1 , wherein irradiating the second surface reflows the deposited first material substantially removing the deposited first material from a field region of the substrate surface ...

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Номер записи: 50
08-08-2013 дата публикации

MANUFACTURING METHOD AND FLUID SUPPLY SYSTEM FOR TREATING SUBSTRATE

Номер: US20130199051A1
Автор: Cho Yong-jhin, JUN YONGMYUNG, KIM Kyoungseob, Kim Seokhoon, KO Yongsun, Lee Hyosan, Lee Kuntack, Oh Jung-min
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A method of manufacture and fluid supply system for treating a substrate is provided. The fluid supply system for treating a substrate may include a substrate dry part supplying a dry fluid to dry a rinse solution doped on a substrate; a dry fluid separation part retrieving a mixed fluid that the dry fluid and the rinse solution are mixed with each other during a dry process of the substrate from the substrate dry part and separating the dry fluid from the mixed fluid; and a dry fluid supply part resupplying the dry fluid separated from the dry fluid separation part to the substrate dry part. 1. A fluid supply system for treating a substrate comprising:a process chamber configured to supply a dry fluid to a substrate to dry a rinse solution adhered to the substrate;a dry fluid separation unit configured to receive a mixed fluid comprising a mixture of the dry fluid and the rinse solution from the process chamber and configured to separate at least a portion of the dry fluid from the mixed fluid; anda dry fluid supply part configured to resupply the separated dry fluid to the process chamber.2. The fluid supply system for treating a substrate of claim 1 , wherein the mixed fluid is maintained at a first pressure in the process chamber claim 1 , and wherein the dry fluid separation unit comprises:a first separation part configured to reduce the pressure of the mixed fluid to a second pressure lower than the first pressure to change the phase of the dry fluid included in the mixed fluid to a phase different from the rinse solution and to perform an initial separation of the phase-changed dry fluid from the rinse solution to obtain an initially separated phase-changed dry fluid; anda second separation part configured to receive the initially separated phase-changed dry fluid and to pass the initially separated phase-changed dry fluid through an absorbent to perform a secondary separation of the dry fluid from the rinse solution.3. The fluid supply system for treating a ...

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Номер записи: 51
08-08-2013 дата публикации

SUBSTRATE TREATMENT APPARATUS, SUBSTRATE TREATMENT METHOD, AND NON-TRANSITORY STORAGE MEDIUM

Номер: US20130203189A1
Автор: KANEDA Masatoshi
Принадлежит: TOKYO ELECTRON LIMITED

A substrate treatment apparatus configured such that substrates in a same lot are distributed by a delivery mechanism into a plurality of unit blocks, each unit block including a solution treatment module, an ultraviolet irradiation module, and a substrate carrying mechanism, the apparatus includes: an illuminance detection part that detects an illuminance of a light source of the ultraviolet irradiation module; and a control part that controls, when an illuminance detection value of the ultraviolet irradiation module in one unit block among the plurality of unit blocks becomes a set value or less, the delivery mechanism to stop delivery of a substrate to the one unit block and deliver subsequent substrates to another unit block, and the ultraviolet irradiation module to perform irradiation on substrates which have already been delivered to the one unit block with an irradiation time adjusted to a length according to the illuminance detection value. 1. A substrate treatment apparatus configured such that substrates in a same lot taken out of a carrier are distributed by a delivery mechanism into a plurality of unit blocks for performing a same series of treatments , each unit block comprising a solution treatment module for supplying a treatment solution to a substrate , an ultraviolet irradiation module for irradiating a substrate with an ultraviolet ray , and a substrate carrying mechanism for carrying a substrate between the modules , the apparatus comprising:an illuminance detection part that detects an illuminance of a light source of the ultraviolet irradiation module; anda control part that controls, when an illuminance detection value of the ultraviolet irradiation module in one unit block among the plurality of unit blocks becomes a set value or less, the delivery mechanism to stop delivery of a substrate to the one unit block and deliver subsequent substrates to another unit block, and the ultraviolet irradiation module to perform irradiation on substrates ...

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Номер записи: 52
15-08-2013 дата публикации

THIN FILM DEPOSITION APPARATUS

Номер: US20130206066A1
Автор: CHO Jeen-Seok, HAN Kyung-don
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A thin film deposition apparatus includes a reaction chamber, a main disk installed in the reaction chamber, and a gas discharging unit disposed outside the main disk. The gas discharging unit recollects a gas in the reaction chamber, and includes: a base member that includes an outer sidewall, an inner sidewall, and a lower wall that connects the outer and inner sidewalls, and is ring-shaped with an open upper portion. At least one through hole is formed in the lower wall. A discharge sleeve is configured to be inserted into the through hole, wherein a gas outlet is formed in the discharge sleeve. An upper cover that is ring-shaped covers the open upper portion of the base member. A plurality of gas inlets are formed in the upper cover. 1. A thin film deposition apparatus comprising:a reaction chamber;a main disk installed in the reaction chamber; anda gas discharging unit that is disposed outside the main disk and is configured to recollect a gas in the reaction chamber, a base member that includes an outer sidewall, an inner sidewall, and a lower wall that connects the outer and inner sidewalls, wherein the base member comprises a ring-shaped member including an open upper portion, and at least one through hole is disposed in the lower wall;', 'a discharge sleeve that is inserted into the at least one through hole, wherein a gas outlet is formed in the discharge sleeve; and', 'an upper cover comprising a ring-shaped member covering the open upper portion of the base member, wherein a plurality of gas inlets are formed in the upper cover., 'wherein the gas discharging unit comprises2. The thin film deposition apparatus of claim 1 , wherein the discharge sleeve of the gas discharging unit comprises an inserting portion configured to be inserted into the at least one through hole claim 1 , and a wing portion extending from the inserting portion.3. The thin film deposition apparatus of claim 1 , wherein the upper cover of the gas discharging unit comprises a ...

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Номер записи: 53
15-08-2013 дата публикации

FILM DEPOSITION APPARATUS

Номер: US20130206067A1
Автор: KATO Hitoshi, Miura Shigehiro
Принадлежит: TOKYO ELECTRON LIMITED

A film deposition apparatus includes a first plasma processing unit which performs a plasma process to a substrate at a second process area wherein the first plasma processing unit includes a first surrounding portion for forming a plasma generation space where plasma is generated, provided with a discharge port at a lower end portion, a second process gas supplying unit which supplies a second process gas to a plasma generation space, an activating unit which activates the second process gas in the plasma generation space, and a second surrounding portion provided below the first surrounding portion for forming a guide space which extends from a center portion side to an outer periphery portion side of the turntable so that the plasma discharged from the discharge port is guided to the surface of the turntable. 1. A film deposition apparatus in which a thin film is formed on a substrate by performing a cycle for plural times in which plural kinds of process gases which react with each other are supplied onto the substrate so that a reaction product is stacked on the substrate in a vacuum chamber , comprising:a turntable placed in the vacuum chamber and provided with a substrate mounting area on which a substrate is to be mounted at a surface for rotating the substrate mounting area;a first process gas supplying unit which supplies a first process gas to a first process area;a first plasma processing unit which performs a plasma process to the substrate at a second process area;a separation gas supplying unit which supplies a separation gas to a separation area between the first process area and the second process area for separating atmospheres of the first process area and the second process area;an evacuation port which evacuates the atmosphere of the vacuum chamber; a first surrounding portion for forming a plasma generation space where plasma is generated, provided with a discharge port at a lower end portion,', 'a second process gas supplying unit which ...

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Номер записи: 54
15-08-2013 дата публикации

WIRELESS SWNT SENSOR INTEGRATED WITH MICROFLUIDIC SYSTEM FOR VARIOUS LIQUID SENSING APPLICATIONS

Номер: US20130209991A1
Автор: Dokmeci Mehmet Remzi, Liu Yu, Wang Ming
Принадлежит: NORTHEASTERN UNIVERSITY

Sensors based on single-walled carbon nanotubes (SWNT) are integrated into a microfluidic system outfitted with data processing and wireless transmission capability. The sensors combine the sensitivity, specificity, and miniature size of SWNT-based nanosensors with the flexible fluid handling power of microfluidic “lab on a chip” analytical systems. Methods of integrating the SWNT-based sensor into a microfluidic system are compatible with the delicate nature of the SWNT sensor elements. The sensor devices are capable of continuously and autonomously monitoring and analyzing liquid samples in remote locations, and are applicable to real time water quality monitoring and monitoring of fluids in living systems and environments. The sensor devices and fabrication methods of the invention constitute a platform technology, because the devices can be designed to specifically detect a large number of distinct chemical agents based on the functionalization of the SWNT. The sensors can be combined into a multiplex format that detects desired combinations of chemical agents simultaneously. 2. The sensor device of claim 1 , wherein the electrical property is resistance or capacitance.3. The sensor device of claim 1 , wherein said SWNT are functionalized such that said electrical property changes specifically in the presence of said chemical agent.4. The sensor device of claim 1 , wherein said SWNT are dielectrophoretically assembled.5. The sensor device of claim 1 , comprising a plurality of first and second microelectrode pairs claim 1 , each pair having a gap between the microelectrodes of the pair and having a nanosensor comprising one or more SWNT traversing said gap claim 1 , one end of the SWNT forming an electrical connection with the first microelectrode of the pair and the other end of the SWNT forming an electrical connection with the second microelectrode of the pair claim 1 , and wherein each gap is enclosed by said microfluidic channel.6. The sensor device of that ...

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Номер записи: 55
15-08-2013 дата публикации

APPARATUS AND METHOD FOR THE RAPID THERMAL CONTROL OF A WORK PIECE IN LIQUID OR SUPERCRITICAL FLUID

Номер: US20130210235A1
Автор: Cotte John M., Goldfarb Dario L., McCullough Kenneth J., Moreau Wayne M., Pope Keith R., Simons John P., Taft Charles J.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A surface cleaning apparatus comprising a chamber, and a thermal transfer device. The chamber is capable of holding a semiconductor structure therein. The thermal transfer device is connected to the chamber. The thermal transfer device has a surface disposed inside the chamber for contacting the semiconducting structure and controlling a temperature of the semiconductor structure in contact with the surface. The thermal transfer device has a thermal control module connected to the surface for heating and cooling the surface to thermally cycle the surface. The thermal control module effects a substantially immediate thermal response of the surface when thermally recycling the surface.

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Номер записи: 56
15-08-2013 дата публикации

Multi-Injector Spatial ALD Carousel and Methods of Use

Номер: US20130210238A1
Автор: Yudovsky Joseph
Принадлежит:

A substrate processing chamber and methods for processing multiple substrates is provided and generally includes a plurality of spaced gas distribution assemblies and a substrate support apparatus to rotate substrates along a path adjacent each of the plurality of gas distribution assemblies. Each of the gas distribution assemblies comprises a plurality of elongate gas ports extending in a direction substantially perpendicularly to the path traversed by the substrate. 1. A processing chamber comprising:a plurality of gas distribution assemblies spaced about the processing chamber so that there is a region between each of the gas distribution assemblies; anda substrate support apparatus within the processing chamber, the substrate support apparatus to rotate at least one substrate along a path adjacent each of the plurality of gas distribution assemblies,wherein each of the gas distribution assemblies comprises a plurality of elongate gas ports extending in a direction substantially perpendicularly to the path traversed by the at least one substrate, the plurality of gas ports comprising a first reactive gas port and a second reactive gas port so that a substrate passing the gas distribution assemblies will be subjected to, in order, the first reactive gas port and the second reactive gas port to deposit a layer on the substrate.2. The processing chamber of claim 1 , further comprising a set of first treatment stations positioned between each of the plurality of gas distribution assemblies.3. The processing chamber of claim 2 , wherein each of the first treatment stations providing the same type of treatment.4. The processing chamber of claim 2 , wherein at least one of the set of first treatment stations provides a different type of treatment the at least one other of the set of first treatment stations.5. The processing chamber of claim 2 , wherein each of the first set of treatment stations comprises a plasma treatment station.6. The processing chamber of claim 2 ...

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Номер записи: 57
22-08-2013 дата публикации

METHOD FOR TREATING A SUBSTRATE AND A SUBSTRATE

Номер: US20130214331A1
Автор: DAHL Johnny, Lång Jouko, LAUKKANEN Pekka, PUNKKINEN Marko, TUOMINEN Marjukka, TUOMINEN Veikko, VAYRYNEN Juhani
Принадлежит: TURUN YLIOPISTO

A method for treating a compound semiconductor substrate, in which method in vacuum conditions a surface of an In-containing III-As, III-Sb or III-P substrate is cleaned from amorphous native oxides and after that the cleaned substrate is heated to a temperature of about 250-550° C. and oxidized by introducing oxygen gas onto the surface of the substrate. The invention relates also to a compound semiconductor substrate, and the use of the substrate in a structure of a transistor such as MOSFET. 1. A method for producing a crystalline oxide layer on an In-containing III-As , III-Sb or III-P compound semiconductor substrate , characterized in that in vacuum conditionssurface of an In-containing III-As, III-Sb or III-P substrate is cleaned from amorphous native oxides, andthe cleaned substrate is heated to a temperature of about 250-550° C. and oxidized by introducing oxygen gas onto the surface of the substrate.2. The method according to claim 1 , characterized in that the In-containing III-As claim 1 , III-Sb or III-P substrate is made of InAs claim 1 , InSb claim 1 , InP claim 1 , InGaAs or InGaSb.3. The method according to or claim 1 , characterized in that the substrate is cleaned by argon-ion sputtering and post heating in ultra-high-vacuum (UHV) conditions at least to 400° C. claim 1 , or by pure heating in UHV at around 400-550° C.4. The method according to any of the preceding claims claim 1 , characterized in that the cleaned substrate is covered by tin (Sn) layer.5. The method according to any of the preceding claims claim 1 , characterized in that the cleaned In-containing III-As substrate is heated to a temperature of about 340-400° C.6. The method according to to claim 1 , characterized in that the cleaned In-containing III-Sb substrate is heated to a temperature of about 340-450° C.7. The method according to to claim 1 , characterized in that the cleaned In-containing III-P substrate is heated to a temperature of about 450-500° C.8. The method according ...

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Номер записи: 58
29-08-2013 дата публикации

GRAPHENE-BASED MEMORY DEVICES AND METHODS THEREFOR

Номер: US20130223166A1
Автор: Schuette Franz Michael
Принадлежит: OCZ TECHNOLOGY GROUP INC.

Memory technology adapted to store data in a binary format. Such technology includes a semiconductor memory device having memory cells, each having a substrate and at least three graphene layers that are oriented to define a graphene stack disposed in a plane. The graphene stack of each memory cell is connected to a bit line and to a ground connection so that a conductive path is defined in the plane of the graphene stack. The in-plane conductivity of the graphene stack of each memory cell is altered during programming of the memory cell to define a binary value of bits stored in the memory cell 1. A semiconductor memory device adapted to store data in a binary format , the memory device comprising:a plurality of memory cells, each memory cell having a substrate and at least three graphene layers that are oriented to define a graphene stack disposed in a plane, the graphene stack of each memory cell being connected to a bit line and to a ground connection so that a conductive path is defined in the plane of the graphene stack; andmeans for altering in-plane conductivity of the graphene stack of each of the memory cells during programming of the memory cells to define a binary value of bits stored in the memory cells.2. The semiconductor memory device of claim 1 , wherein the altering means is adapted to apply a programming voltage to the memory cells by connecting a programming voltage source to the bit line.3. The semiconductor memory device of claim 2 , further comprising electrodes adapted to apply electrical fields in orthogonal directions to the planes of the graphene stacks of the memory cells for the purpose of augmenting or counteracting the programming voltage.4. The semiconductor memory device of claim 1 , wherein the altering means is adapted to apply a programming voltage to the memory cells through a voltage connection and a second ground connection that are aligned to have a substantially orthogonal orientation to the conductive path defined by and ...

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Номер записи: 59
05-09-2013 дата публикации

VERSATILE SYSTEM FOR SELF-ALIGNING DEPOSITION EQUIPMENT

Номер: US20130228125A1
Автор: Garcia Martin
Принадлежит: TEXAS INSTRUMENTS INCORPORATED

The present invention provides a system () for aligning a dispensing apparatus () utilized within a semiconductor deposition chamber (). A stationary reference apparatus () is disposed along the bottom of the deposition chamber. A self-alignment support system (), comprising one or more support components (), is intercoupled between the dispensing apparatus and a deposition system exterior component (). The self-alignment support system is adapted to facilitate and secure repositioning of the dispensing apparatus responsive to pressure applied to the dispensing surface () thereof. A non-yielding offset component () is placed upon a first surface () of the stationary reference apparatus. The dispensing surface of the dispensing apparatus is engaged with the offset component, and pressure is applied to the dispensing apparatus via the offset component until a desired alignment is achieved. 1. A method of aligning a dispensing apparatus within a semiconductor deposition system , the method comprising the steps of:providing a dispensing apparatus;providing a stationary reference apparatus;providing a self-alignment support system, coupled to a first surface of and supporting the dispensing apparatus, adapted to facilitate and secure repositioning of the dispensing apparatus responsive to pressure applied thereto;placing a non-yielding offset component upon a first surface of the stationary reference apparatus;engaging a second surface of the dispensing apparatus with the offset component; andapplying pressure to the dispensing apparatus via the offset component.2. The method of claim 1 , wherein the step of placing a non-yielding offset component further comprises placing a single component.3. The method of claim 1 , wherein the step of placing a non-yielding offset component further comprises placing a plurality of components.4. The method of claim 1 , wherein the step of placing a non-yielding offset component further comprises placing a ceramic component.5. The ...

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Номер записи: 60
12-09-2013 дата публикации

Liquid flow control for film deposition

Номер: US20130233395A1
Автор: Dinh Thuc M., Liu Benjamin Y.H., Ma Yamin
Принадлежит:

An apparatus for controlling liquid flow wherein the apparatus comprises an orifice and an adjacent flexible diaphragm separated from each other by a gap through which a liquid flows. The diaphragm is sufficiently flexible to vary the gap thereby controlling the rate of liquid flowing through the orifice or to provide a positive liquid shutoff of liquid flowing through the orifice. A method for controlling liquid flow through the apparatus comprises flexing said diaphragm to vary a size of the gap to control the rate of liquid flowing through the orifice or to provide a positive liquid shutoff of liquid from flowing through the orifice. 1. An apparatus for controlling liquid flow comprising an orifice and an adjacent flexible diaphragm separated from each other by a gap through which a liquid flows , said diaphragm being sufficiently flexible to vary the gap for controlling the rate of liquid flowing through the orifice or to provide a positive liquid shutoff of liquid flowing through the orifice.2. The apparatus of including additionally a flow passageway with an outlet downstream of said orifice to deliver liquid for vaporization and a gas flow passageway directing a gas to flow at a high velocity near said outlet of said flow passageway to reduce the size of liquid drops formed at said outlet.3. The apparatus of said gas flow velocity is higher than 20 meters per second.4. The apparatus of claim 1 , said flexible diaphragm being a metal.5. The apparatus of claim 4 , said diaphragm being stainless steel.6. The apparatus of including a piezoelectric transducer in contact with said flexible diaphragm for controlling the rate of liquid flow.7. The apparatus of wherein the piezoelectric transducer provides a force to the flexible diaphragm for controlling the rate of liquid flow.8. The apparatus of including a spring to exert a force on said flexible diaphragm for positive liquid flow shutoff.9. The apparatus of and further including a piezoelectric transducer in ...

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Номер записи: 61
12-09-2013 дата публикации

METHODS FOR FORMING GROUP III-NITRIDE MATERIALS AND STRUCTURES FORMED BY SUCH METHODS

Номер: US20130234157A1
Автор: Arena Chantal, Bertram, JR. Ronald Thomas, Lindow Ed, Mahajan Subhash, MENG Fanyu
Принадлежит: SOITEC

Embodiments of the invention include methods for forming Group III-nitride semiconductor structure using a halide vapor phase epitaxy (HVPE) process. The methods include forming a continuous Group III-nitride nucleation layer on a surface of a non-native growth substrate, the continuous Group III-nitride nucleation layer concealing the upper surface of the non-native growth substrate. Forming the continuous Group III-nitride nucleation layer may include forming a Group III-nitride layer and thermally treating said Group III-nitride layer. Methods may further include forming a further Group III-nitride layer upon the continuous Group III-nitride nucleation layer. 1. A method of forming a Group III-nitride material on a growth substrate , comprising: depositing a Group III-nitride layer comprising a plurality of wurtzite crystal structures on an upper surface of the non-native growth substrate using a halide vapor phase epitaxy (HVPE) process; and', 'thermally treating the Group III-nitride layer; and, 'forming a Group III-nitride nucleation layer over a surface of a non-native growth substrate, comprisingforming a further Group III-nitride layer over the nucleation layer.2. The method of claim 1 , wherein depositing a Group III-nitride layer comprising a plurality of wurtzite crystal structures on an upper surface of the non-native growth substrate comprises depositing the Group III-nitride layer comprising a plurality of wurtzite crystal structures adjacent to the upper surface of the non-native growth substrate.3. The method of claim 1 , wherein thermally treating the Group III-nitride layer comprises exposing the Group III-nitride layer to a temperature of less than about 900° C. to reduce a concentration of a chlorine species within the Group III-nitride nucleation layer.4. The method of claim 1 , wherein thermally treating the Group III-nitride layer comprises introducing the Group III-nitride layer to at least one getter for chlorine species to reduce a ...

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Номер записи: 62
12-09-2013 дата публикации

MAGNETIC TUNNEL JUNCTION WITH AN IMPROVED TUNNEL BARRIER

Номер: US20130234266A1
Автор: Ducruet Clarisse, Portemont Celine, Prejbeanu Ioan Lucian
Принадлежит: CROCUS TECHNOLOGY SA

The present disclosure concerns a method of fabricating a magnetic tunnel junction suitable for a magnetic random access memory (MRAM) cell and comprising a first ferromagnetic layer, a tunnel barrier layer, and a second ferromagnetic layer, comprising: forming the first ferromagnetic layer; forming the tunnel barrier layer; and forming the second ferromagnetic layer; wherein said forming the tunnel barrier layer comprises depositing a layer of metallic Mg; and oxidizing the deposited layer of metallic Mg such as to transform the metallic Mg into MgO; the step of forming the tunnel barrier layer being performed at least twice such that the tunnel barrier layer comprises at least two layers of MgO. 1. Method of fabricating a magnetic tunnel junction suitable for a magnetic random access memory (MRAM) cell and comprising a first ferromagnetic layer , a tunnel barrier layer , and a second ferromagnetic layer , comprising:forming the first ferromagnetic layer;forming the tunnel barrier layer; andforming the second ferromagnetic layer;said forming the tunnel barrier layer comprises depositing a layer of metallic Mg; and oxidizing the deposited layer of metallic Mg such as to transform the metallic Mg into MgO; the step of forming the tunnel barrier layer being performed more than twice such that the tunnel barrier layer comprises more than two layers of MgO so as to reduce the probability of the barrier layer comprising pinholes which are aligned through all the MgO layers.2. The method according to claim 1 , whereindepositing the layer of metallic Mg further comprises using an inert gas such as to level the deposited layer of metallic Mg.3. The method according to claim 1 , whereinthe thickness of the deposited layer of metallic Mg is comprised between 0 nm and 1.5 nm and preferably between 0.3 nm and 1.2 nm.4. The method according to claim 1 ,further comprising depositing a CoFe layer after said forming the first ferromagnetic layer and prior said forming the second ...

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Номер записи: 63
12-09-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20130234299A1
Автор: MURAKAMI Sadatoshi
Принадлежит: KABUSHIKI KAISHA TOSHIBA

According to one embodiment, a_semiconductor device includes a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked. The semiconductor device includes a mark and a supporting unit. The mark is opened onto a surface of the stacked body. The supporting unit is provided around the mark. The supporting unit extends in a stacked direction of the stacked body. The supporting unit is in contact with at least a plurality of conductive layers. 1. A semiconductor device comprising a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked , comprising:a mark opened onto a surface of the stacked body; anda supporting unit that is provided around the mark and extends in a stacked direction of the stacked body,wherein the supporting unit is in contact with at least a plurality of conductive layers.2. The device according to claim 1 , wherein the supporting unit is provided so as to extend from an upper surface of an uppermost conductive layer to a lower surface of a lowermost conductive layer in the stacked direction.3. The device according to claim 1 , wherein the supporting unit is provided so as to enclose the mark.4. The device according to claim 3 , wherein the supporting unit has a frame shape.5. The device according to claim 1 , wherein a plurality of supporting units are provided around the mark.6. The device according to claim 5 , wherein the plurality of supporting units are disposed so as to enclose the mark.7. The device according to claim 5 , wherein the plurality of supporting units are regularly disposed.8. The device according to claim 5 , wherein the plurality of supporting units have dot shapes.9. The device according to claim 1 , wherein a width dimension of the supporting unit is 100 nm or less.10. The device according to claim 1 , wherein the supporting unit includes a silicon nitride.11. The device according to claim 1 , wherein the mark ...

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Номер записи: 64
12-09-2013 дата публикации

TWO-STEP HYDROGEN ANNEALING PROCESS FOR CREATING UNIFORM NON-PLANAR SEMICONDUCTOR DEVICES AT AGGRESSIVE PITCH

Номер: US20130237039A1
Автор: Bangsaruntip Sarunya, Sleight Jeffrey W.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A two-step hydrogen anneal process has been developed for use in fabricating semiconductor nanowires for use in non-planar semiconductor devices. In the first part of the two-step hydrogen anneal process, which occurs prior to suspending a semiconductor nanowire, the initial roughness of at least the sidewalls of the semiconductor nanowire is reduced, while having at least the bottommost surface of the nanowire pinned to an uppermost surface of a substrate. After performing the first hydrogen anneal, the semiconductor nanowire is suspended and then a second hydrogen anneal is performed which further reduces the roughness of all exposed surfaces of the semiconductor nanowire and reshapes the semiconductor nanowire. By breaking the anneal into two steps, smaller semiconductor nanowires at a tight pitch survive the process and yield. 1. A method of fabricating a non-planar semiconductor device comprising:forming at least one semiconductor nanowire above an insulator layer of a semiconductor-on-insulator substrate, wherein an end segment of said at least one semiconductor nanowire is attached to a first semiconductor-on-insulator pad region and another end segment of said at least one semiconductor nanowire is attached to a second semiconductor-on-insulator pad region, said pad regions are both located atop said insulator layer;performing a first hydrogen anneal on said at least one semiconductor nanowire with at least a bottommost surface of said at least one semiconductor nanowire in direct contact with an uppermost surface of said insulator layer;removing a portion of said insulator layer located beneath said at least one semiconductor nanowire to suspend said at least one semiconductor nanowire above a remaining portion of said insulator layer; andperforming a second hydrogen anneal on said at least one semiconductor nanowire that is suspended above the remaining portion of said insulator layer.2. The method of claim 1 , wherein during said first hydrogen anneal ...

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Номер записи: 65
12-09-2013 дата публикации

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF PROCESSING SUBSTRATE, SUBSTRATE PROCESSING APPARATUS AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM

Номер: US20130237064A1
Автор: KIRIKIHIRA Kaori, ORIHASHI Yugo, SHIMAMOTO Satoshi
Принадлежит: HITACHI KOKUSAI ELECTRIC INC.

A method of manufacturing a semiconductor device, includes: forming a film on a substrate by performing a cycle a predetermined number of times, the cycle including: supplying a raw material gas to a substrate in a process chamber, exhausting the raw material gas remaining in the process chamber through an exhaust line, supplying an amine-based gas; and exhausting the amine-based gas through the exhaust line with the supply of the amine-based gas stopped. A degree of valve opening of an exhaust valve disposed in the exhaust line is changed in multiple steps in the process of exhausting the amine-based gas. 1. A method of manufacturing a semiconductor device , comprising:forming a film on a substrate by performing a cycle a predetermined number of times, the cycle comprising:supplying a raw material gas to a substrate in a process chamber;exhausting the raw material gas remaining in the process chamber through an exhaust line in a state where the supply of the raw material gas is being stopped;supplying an amine-based gas to the substrate in the process chamber; andexhausting the amine-based gas remaining in the process chamber through the exhaust line in a state where the supply of the amine-based gas is being stopped,wherein a degree of valve opening of an exhaust valve disposed in the exhaust line is changed in multiple steps in the act of exhausting the amine-based gas remaining in the process chamber.2. The method of claim 1 , wherein the act of exhausting the amine-based gas remaining in the process chamber includes:exhausting the amine-based gas remaining in the process chamber with the degree of valve opening as a first degree of valve opening; andexhausting the amine-based gas remaining in the process chamber with the degree of valve opening as a second degree of valve opening which is higher than the first degree of valve opening.3. The method of claim 2 , wherein the second degree of valve opening is fully-opened.4. The method of claim 1 , wherein the act ...

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Номер записи: 66
19-09-2013 дата публикации

ARRANGEMENT FOR THE PRODUCTION OF STRUCTURED SUBSTRATES

Номер: US20130239883A1
Автор: BOHNET Hans, THIEL Klaus-Peter
Принадлежит: Centofex Lda & Comandita

An arrangement for producing structured substrates is provided, which includes a device for applying layer systems including a device for applying liquid materials to rotating substrates, a housing, a rotating holder for the substrate to be coated, a feeder for liquid materials to be applied, and a collection device having multiple removal contraptions for liquid materials that do not remain on the substrate. The housing of the device is filled with an inert gas, in particular dried, molecular nitrogen, noble gas, or a mixture thereof. The additional receptacles and conduits of the arrangement for producing structured substrates are gas-tight and are designed such that an inert molecular nitrogen or noble gas atmosphere is created above the liquid contents thereof. The collection device has various collection zones in which different liquid materials can be selectively collected and selectively removed via the associated removal contraption. 1. An arrangement for producing structured substrates with a device for applying layer systems to a substrate , the arrangement comprising:a closed chamber for applying liquid materials to form the layer system;a rotating holder for substrates; anda collecting device surrounding the rotating holder and arranged in the closed chamber, the collecting device adapted to collect liquid materials spun off of the substrate,wherein the collecting device has at least two removal devices configured to remove the liquid collected materials selectively individually or in batches,wherein the collecting device in the chamber surrounds the holder in a ring-shaped manner and has at least two collection zones separated from one another by separating elements to collect the spun-off liquid materials, andwherein the collecting device has at least two wall-shaped separating elements on a side facing the holder, which form at least two ring-shaped channels as collection zones, which are provided with one or more removal devices.2. The arrangement ...

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Номер записи: 67
19-09-2013 дата публикации

Coating treatment method, coating treatment apparatus, and computer-readable storage medium

Номер: US20130239887A1
Автор: Koji Takayanagi, Kousuke Yoshihara, Tomohiro Iseki
Принадлежит: Tokyo Electron Ltd

In a coating step, a substrate is rotated at a high speed, and in that state a resist solution is discharged from a first nozzle to a central portion of the substrate to apply the resist solution over the substrate. Subsequently, in a flattening step, the rotation of the substrate is decelerated and the substrate is rotated at a low speed to flatten the resist solution on the substrate. In this event, the discharge of the resist solution by the first nozzle in the coating step is performed until a middle of the flattening step, and when the discharge of the resist solution is finished in the flattening step, the first nozzle is moved to move a discharge position of the resist solution from the central portion of the substrate. According to the present invention, the resist solution can be applied uniformly within the substrate.

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Номер записи: 68
19-09-2013 дата публикации

STABILIZATION METHOD OF FILM FORMING APPARATUS AND FILM FORMING APPARATUS

Номер: US20130239893A1
Автор: KADONAGA Kentaro, Suzuki Keisuke
Принадлежит: TOKYO ELECTRON LIMITED

A method for stabilizing a film forming apparatus, which can selectively perform a boron-containing nitride film forming process or a non-boron-containing nitride film forming process on at least one target object to be processed in a vacuum-evacuable processing chamber, the method includes performing a heat stabilization process to heat the interior of the processing chamber under an oxygen-containing gas atmosphere, between the boron-containing nitride film forming process and the non-boron-containing nitride film forming process when the non-boron-containing nitride film forming process is performed after the boron-containing nitride film forming process. 1. A method for stabilizing a film forming apparatus which can selectively perform a boron-containing nitride film forming process or a non-boron-containing nitride film forming process on at least one target object to be processed in a vacuum-evacuable processing chamber , the method comprising:performing a heat stabilization process to heat the interior of the processing chamber under an oxygen-containing gas atmosphere, between the boron-containing nitride film forming process and the non-boron-containing nitride film forming process when the non-boron-containing nitride film forming process is performed after the boron-containing nitride film forming process.2. The method of claim 1 , wherein a holding unit configured to hold the target object in the processing chamber is accommodated in the processing chamber.3. The method of claim 2 , wherein a dummy target object is held on the holding unit.4. The method of claim 1 , wherein the oxygen-containing gas includes at least one gas selected from a group consisting essentially of O claim 1 , O claim 1 , HO claim 1 , NO claim 1 , NO claim 1 , NOand CO.5. The method of claim 1 , wherein the boron-containing nitride film includes at least one film selected from a group consisting essentially of a SiNB film claim 1 , a SiBCN film and a BN film.6. The method of claim ...

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Номер записи: 69
19-09-2013 дата публикации

METHODS FOR FABRICATING THIN FILM SOLAR CELLS

Номер: US20130240363A1
Автор: Li Delin
Принадлежит:

The present invention relates to CIGS solar cell fabrication. The invention discloses a method for fabricating CIGS thin film solar cells using a roll-to-roll apparatus. The invention discloses method to fabricate semiconductor thin film Cu(InGa)(SeS)by sequentially electroplating a stack of multiple precursor layers comprising of copper, indium, gallium, and selenium elements or their alloys followed by selenization at a temperature between 450° C. and 700° C. 1. An aqueous solution for electroplating a gallium-selenium alloy film for fabricating a thin-film solar cell , the aqueous solution comprising:gallium ions of a first concentration range from 0.1 Mol to 3.0 Mol;{'b': '0', 'selenium ions of a second concentration range from .05 Mol to 0.2 Mol; and'}a complexing agent;wherein the gallium ions, the selenium ions, and the complexing agent are solute in water of a predetermined amount to yield a pH value within 8 to 14.2. The aqueous solution of wherein the gallium ions are obtained from a gallium salt added into the water claim 1 , the gallium salt being selected from gallium chloride claim 1 , gallium nitride claim 1 , gallium sulfate claim 1 , gallium acetate claim 1 , and gallium nitrate.3. The aqueous solution of wherein the selenium ions are obtained from a compound added into the water claim 1 , the compound being selected from selenium acid (HSeO) claim 1 , selenous acid (HSeO) claim 1 , selenium dioxide (SeO) claim 1 , and selenium trioxide (SeO).4. The aqueous solution of wherein the complexing agent comprises a compound selected from glucoheptonic acid sodium salt (CHNaO) claim 1 , polyethylene glycol (CHO).HO claim 1 , sodium lauryl sulfate (CHSONa) claim 1 , sodium ascorbate (CHONa) claim 1 , sodium salicylic (CHNaO) claim 1 , and glycine (CHNO).5. The aqueous solution of further comprising a dynamic equilibrium state of the first concentration and the second concentration subjected to an electrical bias applied between an anode immersed therein and ...

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Номер записи: 70
19-09-2013 дата публикации

SHOWERHEAD FOR CVD DEPOSITIONS

Номер: US20130240637A1
Автор: Goodlin Brian E., Jiang Qidu
Принадлежит: TEXAS INSTRUMENTS INCORPORATED

A CVD showerhead that includes a circular inner showerhead and at least one outer ring showerhead. At least two process gas delivery tubes are coupled to each showerhead. Also, a dual showerhead that includes a circular inner showerhead and at least one outer ring showerhead where each showerhead is coupled to oxygen plus a gas mixture of lead, zirconium, and titanium organometallics. A method of depositing a CVD thin film on a wafer. Also, a method of depositing a PZT thin film on a wafer. 1. A process of depositing a CVD thin film , comprising:supplying a non-reacting process gas mixture to a mixing chamber of a showerhead through a first process gas delivery tube; andsupplying a reactant gas to said mixing chamber through a second process gas delivery tube.2. The process of where said non-reacting process gas mixture is a mixture of a lead organometallic claim 1 , a zirconium organometallic claim 1 , and a titanium organometallic and where said reactant gas is oxygen.3. A process of depositing a CVD thin film claim 1 , comprising:supplying a non-reacting process gas mixture to a first chamber of a showerhead; andsupplying a reactant gas to a second chamber of said showerhead. This is a divisional of U.S. patent application Ser. No. 13/346,603, filed Jan. 9, 2012, which is a divisional of U.S. application Ser. No. 13/025,035, filed Feb. 10, 2011, which claims the benefit of U.S. Provisional Application 61/325,793, (Texas Instruments Docket Number TI-69353PS, filed Apr. 19, 2010), the contents of which are incorporated by reference.This invention relates to single-wafer processes involving the production of semiconductor devices. More particularly this invention relates to chemical vapor deposition (CVD) processes and equipment.The example embodiments are described with reference to the attached figures, wherein like reference numerals are used throughout the figures to designate similar or equivalent elements. The figures are not drawn to scale and they are ...

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Номер записи: 71
19-09-2013 дата публикации

QUANTUM DOT STRUCTURE, METHOD FOR FORMING QUANTUM DOT STRUCTURE, WAVELENGTH CONVERSION ELEMENT, LIGHT-LIGHT CONVERSION DEVICE, AND PHOTOELECTRIC CONVERSION DEVICE

Номер: US20130240829A1
Автор: Kuramachi Teruhiko
Принадлежит: FUJIFILM Corporation

This quantum dot structure has a matrix layer and a plurality of crystalline quantum dots provided spaced within the matrix layer. The quantum dots are provided at positions that differ in the direction of thickness of the matrix layer. 1. A quantum dot structure forming method of forming crystalline quantum dots in a matrix layer on a substrate by supplying sputtering gas and reactant gas to a chamber in which the substrate and a target are disposed and performing a sputtering , wherein the matrix layer is made of a dielectric or a first nitride semiconductor , the quantum dots are made of a second nitride semiconductor , and the dielectric or the first nitride semiconductor and the second nitride semiconductor is different in composition from each other , the quantum dot structure forming method comprising the steps of:performing a sputtering using a constituent metal element of the second nitride semiconductor constituting the quantum dots as the target and using nitrogen gas as the reactant gas to periodically deposit particulates on the substrate with substantially the same size as the quantum dots in an amorphous state in which a nitrogen ratio is lower than a stoichiometric ratio;forming the matrix layer made of the dielectric or the first nitride semiconductor with a uniform thickness so as to cover the particulates; andalternately repeating the step of depositing the particulates and the step of forming the matrix layer to stack the matrix layer having the particulates therein and form a layered structure, and crystallizing the particulates to form the quantum dots by subjecting the layered structure to a heat treatment in an atmosphere of inert gas.2. The quantum dot structure forming method according to claim 1 , wherein in the step of forming the matrix layer claim 1 , the surface of the matrix layer has a concavo-convex shape which reflects the shapes of the particulates and has a periodic unevenness with substantially the same size as the quantum dots ...

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Номер записи: 72
19-09-2013 дата публикации

Process for production of functional device, process for production of ferroelectric material layer, process for production of field effect transistor, thin film transistor, field effect transistor, and piezoelectric inkjet head

Номер: US20130240871A1
Автор: Eisuke Tokumitsu, Takaaki Miyasako, Tatsuya Shimoda, Toshihiko Kaneda
Принадлежит: JAPAN SCIENCE AND TECHNOLOGY AGENCY

A method of producing a functional device according to the present invention includes, in this order: the functional solid material precursor layer formation step of applying a functional liquid material onto a base material to form a precursor layer of a functional solid material; the drying step of heating the precursor layer to a first temperature in a range from 80° C. to 250° C. to preliminarily decrease fluidity of the precursor layer; the imprinting step of imprinting the precursor layer that is heated to a second temperature in a range from 80° C. to 300° C. to form an imprinted structure on the precursor layer; and the functional solid material layer formation step of heat treating the precursor layer at a third temperature higher than the second temperature to transform the precursor layer into a functional solid material layer.

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Номер записи: 73
19-09-2013 дата публикации

METHOD OF FABRICATING FIN-FIELD EFFECT TRANSISTORS (FINFETS) HAVING DIFFERENT FIN WIDTHS

Номер: US20130244392A1
Автор: Lee ChoongHo, Lee Jongwook, Min Shincheol, OH Chang Woo
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

Provided are methods of forming field effect transistors. The method includes preparing a substrate with a first region and a second region, forming fin portions on the first and second regions, each of the fin portions protruding from the substrate and having a first width, forming a first mask pattern to expose the fin portions on the first region and cover the fin portions on the second region, and changing widths of the fin portions provided on the first region. 1. A method of fabricating an integrated circuit device , the method comprising:forming fin-shaped transistor channel regions protruding from first and second regions of a substrate; andselectively altering respective widths of ones of the fin-shaped transistor channel regions protruding from the first region while maintaining respective widths of ones of the fin-shaped transistor channel regions protruding from the second region.2. The method of claim 1 , wherein selectively altering comprises one of etching or growing a semiconductor layer on sidewalls of the ones of the fin-shaped transistor channel regions protruding from the first region claim 1 , and wherein the respective widths of the ones of the fin-shaped transistor channel regions protruding from the first and second regions are substantially similar prior to selectively altering the respective widths of the ones of the fin-shaped transistor channel regions protruding from the first region.3. The method of claim 2 , wherein claim 2 , after selectively altering the respective widths of the ones of the fin-shaped transistor channel regions protruding from the first region claim 2 , respective heights of the ones of the fin-shaped transistor channel regions protruding from the first and second regions may be substantially similar.4. The method of claim 2 , wherein claim 2 , after selectively altering the respective widths of the ones of the fin-shaped transistor channel regions protruding from the first region claim 2 , surfaces of the first and ...

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Номер записи: 74
19-09-2013 дата публикации

MASKING TECHNIQUES AND CONTACT IMPRINT RETICLES FOR DENSE SEMICONDUCTOR FABRICATION

Номер: US20130244436A1
Автор: Sandhu Gurtej S.
Принадлежит: MICRON TECHNOLOGY, INC.

A reticle comprising isolated pillars is configured for use in imprint lithography. In some embodiments, on a first substrate a pattern of pillars pitch-multiplied in two dimensions is formed in an imprint reticle. The imprint reticle is brought in contact with a transfer layer overlying a series of mask layers, which in turn overlie a second substrate. The pattern in the reticle is transferred to the transfer layer, forming an imprinted pattern. The imprinted pattern is transferred to the second substrate to form densely-spaced holes in the substrate. In other embodiments, a reticle is patterned by e-beam lithography and spacer formations. The resultant pattern of closely-spaced pillars is used to form containers in an active integrated circuit substrate. 1. A method comprising:providing a plurality of mandrels over a partially-formed imprint reticle;forming a first plurality of lines by forming spacers on sidewalls of the mandrels, wherein the spacers define the plurality of lines;forming a second plurality of lines over the first plurality of lines, wherein the second plurality of lines cross the first plurality of lines, as seen in a top down view; andtransferring a pattern defined by the first and the second plurality of lines to the partially-formed imprint reticle to form an array of isolated features in the partially-formed imprint reticle.2. The method of claim 1 , wherein providing the plurality of mandrels comprises photolithographically defining a pattern corresponding to the mandrels in a photoresist layer.3. The method of claim 2 , wherein providing the plurality of mandrels further comprises transferring the pattern corresponding to the mandrels to an underlying temporary layer claim 2 , wherein features in the temporary layer constitute the mandrels.4. The method of claim 1 , wherein forming the first plurality of lines comprises:blanket depositing a layer of spacer material on the mandrels;subjecting the layer of spacer material to a directional ...

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Номер записи: 75
19-09-2013 дата публикации

Method of Fabricating Semiconductor Device

Номер: US20130244445A1
Автор: CHOI Jae-hyoung, Kang Sang-yeol, KIM Youn-soo, LIM Jae-soon, Park Min-Young, Yoo Cha-Young
Принадлежит:

Methods of fabricating a semiconductor device include forming a deposited film on a semiconductor substrate in a process chamber by repeatedly forming unit layers on the semiconductor substrate. The unit layer is formed by forming a preliminary unit layer on the semiconductor substrate by supplying a process material including a precursor material and film-control material into the process chamber, purging the process chamber, forming a unit layer from the preliminary unit layer, and again purging the process chamber. The precursor material includes a central atom and a ligand bonded to the central atom, and the film-control material includes a hydride of the ligand. 1. A method of fabricating a semiconductor device , comprising:forming a deposited film on a semiconductor substrate in a process chamber by repeatedly forming a unit layer on the semiconductor substrate; forming a preliminary unit layer on the semiconductor substrate by supplying a process material including a precursor material and a film-control material into the process chamber, wherein the precursor material includes a central atom and a ligand bonded to the central atom, and the film-control material comprises a hydride of the ligand of the precursor material;', 'firstly purging the process chamber in which the semiconductor substrate having the preliminary unit layer is located;', 'forming the unit layer from the preliminary unit layer in the firstly purged process chamber; and', 'secondly purging the process chamber in which the semiconductor substrate having the unit layer is located., 'wherein forming the unit layer comprises2. The method according to claim 1 , wherein the precursor material is adsorbed onto the semiconductor substrate to form a precursor-adsorbed layer.3. The method according to claim 2 , wherein the film-control material is coordinated to the central atom of the precursor-adsorbed layer to form a more chemically stable material from the precursor-adsorbed layer than the ...

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Номер записи: 76
19-09-2013 дата публикации

AZEOTROPIC COMPOSITIONS COMPRISING METHYL PERFLUOROPENTENE ETHERS FOR CLEANING APPLICATIONS

Номер: US20130244922A1
Автор: Bartelt Joan Ellen, Minor Barbara Haviland
Принадлежит: E I DU PONT DE NEMOURS AND COMPANY

The present disclosure provides azeotropic and azeotrope-like compositions comprised of methylperfluoropentene ethers and at least one of methanol, ethanol, 2-propanol, hexane, heptane, trans-1,2-dichloroethylene, ethyl formate, methyl formate, HFE-7100, HFE-7200 and 1-bromopropane or combinations thereof. The present disclosure also provides for methods of use for the azeotropic and azeotrope-like compositions. 1. An azeotropic or azeotrope-like compositions comprising methyl perfluoropentene ethers and at least one of methanol , ethanol , 2-propanol , hexane , heptane , trans-1 ,2-dichloroethylene , ethyl formate , methyl formate , HFE-7100 , HFE-7200 and 1-bromopropane or combinations thereof.2. An azeotropic or azeotrope-like composition as in claim 1 , wherein the compositions comprises an azeotropic or azeotrope-like composition selected from the group consisting of:about 14 to about 68 percent by weight of methyl perfluoropentene ethers and about 32 to about 86 percent by weight of trans-1,2-dichloroethylene;about 72 to about 95 percent by weight of methyl perfluoropentene ethers and about 5 to about 28 percent by weight methanol;about 72 to about 96 percent by weight of methyl perfluoropentene ethers and about 4 to about 28 percent by weight ethanol;about 70 to about 95 percent by weight of methyl perfluoropentene ethers and about 5 to about 30 percent by weight 2-propanol;about 1 to about 99 percent by weight of methyl perfluoropentene ethers and about 1 to about 9 percent by weight hexane;about 1 to about 15 percent by weight of methyl perfluoropentene ethers and about 85 to about 99 percent by weight n-heptane;about 85 to about 99 percent by weight of methyl perfluoropentene ethers and about 1 to about 15 percent by weight n-heptane;about 1 to about 73 percent by weight of methyl perfluoropentene ethers and about 27 to about 99 percent by weight cyclopentane;about 26 to about 79 percent by weight of methyl perfluoropentene ethers and about 21 to about 74 ...

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Номер записи: 77
26-09-2013 дата публикации

SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SUBSTRATE PROCESSING APPARATUS, AND NON-TRANSITORY RECORDING MEDIUM

Номер: US20130252433A1
Автор: UEDA Tatsushi
Принадлежит: HITACHI KOKUSAI ELECTRIC INC.

A method of manufacturing a semiconductor device includes: accommodating a substrate having an oxide film formed thereon into a processing chamber; supplying a process gas to the substrate; performing a preprocessing step in which the process gas is excited in a state that a pressure within the processing chamber is kept at a first pressure and an electric potential of the substrate is kept at a first electric potential; and performing a main processing step by which the process gas is excited in a state that the pressure within the processing chamber is kept at a second pressure and the electric potential of the substrate is kept at a second electric potential, wherein the first pressure is lower than the second pressure and the first electric potential is lower than the second electric potential. 1. A method of manufacturing a semiconductor device , the method comprising:accommodating a substrate having an oxide film formed thereon into a processing chamber;supplying a process gas to the substrate;performing a preprocessing in which the process gas is excited in a state that a pressure within the processing chamber is kept at a first pressure and an electric potential of the substrate is kept at a first electric potential; andperforming a main processing in which the process gas is excited in a state that the pressure within the processing chamber is kept at a second pressure and the electric potential of the substrate is kept at a second electric potential,wherein the first pressure is lower than the second pressure and the first electric potential is lower than the second electric potential.2. The method of claim 1 , wherein the preprocessing is performed in a state that a first substrate having an oxide film formed thereon is accommodated within the processing chamber and the main processing is performed in a state that a second substrate having an oxide film formed thereon is accommodated within the processing chamber.3. The method of claim 1 , wherein the ...

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Номер записи: 78
03-10-2013 дата публикации

FILM-FORMING APPARATUS AND FILM-FORMING METHOD

Номер: US20130255569A1
Автор: SATO Yuusuke, Yamada Takumi
Принадлежит: NUFLARE TECHNOLOGY, INC

A film-forming apparatus and film-forming method comprising, a chamber, a first gas supply unit supplying a reaction gas for a film-forming process to the chamber, a substrate-supporting portion supporting a substrate placed in the chamber, a heating unit heating the substrate from below the substrate-supporting portion, a rotary drum supporting the substrate-supporting portion on a top thereof, and including the heating unit disposed therein, a rotary shaft disposed in a lower part of the chamber, and rotating the rotary drum, a reflector reflecting heat from the heating unit, surrounding the rotary drum, and being disposed so as to have an upper end higher in height than an upper end of the substrate-supporting portion, and a second gas supply unit supplying a hydrogen gas or an inert gas between the rotary drum and the reflector. 1. A film-forming apparatus comprising:a chamber;a first gas supply unit configured to supply a reaction gas for a film-forming process to the chamber;a substrate-supporting portion configured to support a substrate placed in the chamber;a heating unit configured to heat the substrate from below the substrate-supporting portion;a rotary drum configured to support the substrate-supporting portion on a top thereof, and including the heating unit disposed therein;a rotary shaft disposed in a lower part of the chamber, and configured to rotate the rotary drum;a reflector configured to reflect heat from the heating unit, surrounding the rotary drum, and the reflector disposed so as to have an upper end higher in height than an upper end of the substrate-supporting portion; anda second gas supply unit configured to supply a hydrogen gas or an inert gas between the rotary drum and the reflector.2. The film-forming apparatus according to claim 1 , further comprising:a third gas supply unit configured to supply an etching gas to the chamber; anda control unit configured to control to lower the flow rate of the gas from the second gas supply unit ...

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Номер записи: 79
03-10-2013 дата публикации

CHEMICAL VAPOR DEPOSITION APPARATUS HAVING SUSCEPTOR

Номер: US20130255578A1
Автор: KIM Ki Sung, KIM Sung Tae, Kim Young Sun, RHEE Do Young, SAKONG Tan, YOON Suk Ho
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A chemical vapor deposition (CVD) apparatus including a chamber, a susceptor in the chamber, and a heating chamber may be provided. The susceptor includes a rotor, a rotational shaft coupled to a lower portion of the rotor, a driving device coupled to the rotational shaft, and at least one pocket defined at an upper surface of the rotor. The driving device rotatably drives the rotational shaft. The at least one pocket includes a mounting portion configured to receive a substrate thereon and a protruding portion, e.g., a convex portion, protruding from a bottom surface of the at least one pocket such that the protruding portion is positioned at a region corresponding to the rotational shaft. The heating unit surrounds the rotational shaft and heats the substrate. 1. A chemical vapor deposition (CVD) apparatus comprising:a chamber; a rotor,', 'a rotational shaft coupled to a lower portion of the rotor,', 'a driving device coupled to the rotational shaft, the driving device configured to rotatably drive the rotational shaft, and', a mounting portion configured to receive a substrate thereon, and', 'a protruding portion protruding from a bottom surface of the at least one pocket such that the protruding portion is positioned at a region corresponding to the rotational shaft; and, 'at least one pocket defined at an upper surface of the rotor, the at least one pocket including'}], 'a susceptor in the chamber, the susceptor including,'}a heating unit under the susceptor, the heating unit surrounding the rotational shaft and configured to heat the substrate.2. The CVD apparatus of claim 1 , wherein an interval between the bottom surface of the pocket and the received substrate is smaller at the region corresponding to the rotational shaft than at regions not corresponding to the rotational shaft and being at an inner side of the mounting portion.3. The CVD apparatus of claim 1 , wherein an upper surface of the protruding portion is flat.4. The CVD apparatus of claim 3 , ...

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Номер записи: 80
03-10-2013 дата публикации

METHOD OF MANUFACTURING FERROELECTRIC THIN FILM

Номер: US20130260482A1
Автор: Iida Shintaro, Sakurai Hideaki
Принадлежит: MITSUBISHI MATERIALS CORPORATION

A method of manufacturing a ferroelectric thin film on a lower electrode by electrostatically spraying a ferroelectric thin film-forming electrostatic spray solution so as to coat the electrostatic spray solution on the lower electrode and form a coated film, drying, calcining, and then firing the coated film so as to crystallize the coated film. In this method, the electrostatic spray solution is a mixed solution in which a ferroelectric thin film-forming sol-gel solution and powder having the same composition as the solid content of the sol-gel solution and having a particle diameter that can be ejected from the spout are uniformly mixed, and, when the metallic compound-converted mass of a metallic compound dissolved in the sol-gel solution is represented by A and the mass of the powder is represented by B, a ratio of B with respect to (A+B) is in a range of 5% to 40%. 1. A method of manufacturing a ferroelectric thin film on a lower electrode by electrostatically spraying a ferroelectric thin film-forming electrostatic spray solution from a spout of a capillary toward the lower electrode of a substrate having the lower electrode so as to coat the electrostatic spray solution on the lower electrode and form a coated film , drying , calcining , and then firing the coated film so as to crystallize the coated film ,wherein the electrostatic spray solution is a mixed solution in which a ferroelectric thin film-forming sol-gel solution and powder having the same composition as a solid content of the sol-gel solution and having a particle diameter that can be ejected from the spout are uniformly mixed, andwhen a metallic compound-converted mass of a metallic compound dissolved in the sol-gel solution is represented by A and a mass of the powder is represented by B, a ratio of B with respect to (A+B) is in a range of 5% to 40%.2. An electrostatic spray solution for forming a ferroelectric thin film when electrostatically sprayed from a spout of a capillary ,wherein a ...

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Номер записи: 81
03-10-2013 дата публикации

CONTINUOUS PROCESSING SYSTEM, CONTINUOUS PROCESSING METHOD, AND PROGRAM

Номер: US20130260572A1
Автор: TAKENAGA Yuichi, TOJO Yukio
Принадлежит: TOKYO ELECTRON LIMITED

In a continuous processing system, a controller of a heat treatment apparatus calculates a weight of each layer from input target film thicknesses of a phosphorous-doped polysilicon film (D-poly film) and an amorphous silicon film (a-Si film), and calculates activation energy of stacked films based on the calculated weight and activation energy. The controller prepares a stacked film model based on the calculated activation energy and a relationship of a temperature of each zone and film thicknesses of the D-poly film and the a-Si film, and calculates an optimum temperature of each zone by using the prepared stacked film model. The controller controls power controllers of heaters to set a temperature in a reaction tube to be the calculated temperature of each zone and forms stacked films on a semiconductor wafer by controlling a pressure adjusting unit, flow rate adjusting units, etc. 1. A continuous processing system for forming stacked films by forming a first film on an object and then forming a second film , the continuous processing system comprising:a heating unit which heats an inside of a processing chamber accommodating a plurality of objects;a heat treatment condition storage unit which stores film-forming conditions of the first film and the second film, the film-forming conditions including a temperature in the processing chamber heated by the heating unit;a first model storage unit which stores a first model indicating a relationship between the temperature in the processing chamber and a film thickness of the first film to be formed;a second model storage unit which stores a second model indicating a relationship between the temperature in the processing chamber and a film thickness of the second film to be formed;a weight calculating unit which calculates weights of the first film and the second film, based on target film thicknesses of the first film and the second film;a stacked film model preparing unit which prepares a stacked film model ...

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Номер записи: 82
10-10-2013 дата публикации

PROCESSING METHOD OF STACKED-LAYER FILM AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Номер: US20130267068A1
Автор: Hanaoka Kazuya, Sasagawa Shinya
Принадлежит: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

In a processing method of a stacked-layer film in which a metal film is provided on an oxide insulating film, plasma containing an oxygen ion is generated by applying high-frequency power with power density greater than or equal to 0.59 W/cmand less than or equal to 1.18 W/cmto the stacked-layer film side under an atmosphere containing oxygen in which pressure is greater than or equal to 5 Pa and less than or equal to 15 Pa, the metal film is oxidized by the oxygen ion, and an oxide insulating film containing excess oxygen is formed by supplying oxygen to the oxide insulating film. 1. A method for processing a stacked-layer film comprising a first oxide insulating film and a metal film over the first oxide insulating film , the method comprising the steps of:generating plasma containing an oxygen ion under an atmosphere containing oxygen; andirradiating the stacked-layer film with the oxygen ion so that a metal oxide film is formed by oxidizing the metal film and a second oxide insulating film containing excess oxygen is formed by supplying an oxygen atom to the first oxide insulating film,{'sup': 2', '2, 'wherein the plasma is generated under a pressure greater than or equal to 5 Pa and less than or equal to 15 Pa, and with a power density greater than or equal to 0.59 W/cmand less than or equal to 1.18 W/cm.'}2. The method according to claim 1 ,wherein the metal film is formed of at least one selected from the group consisting of magnesium, aluminum, yttrium, hafnium, and zirconium with a thickness greater than or equal to 3 nm and less than or equal to 15 nm.3. The method according to claim 1 ,wherein an average surface roughness of the metal oxide film is less than or equal to 0.1 nm.4. The method according to claim 1 ,wherein the second oxide insulating film is capable of releasing oxygen by heat treatment.5. A method for manufacturing a semiconductor device claim 1 , comprising the steps of:forming a stacked-layer film comprising a first oxide insulating film ...

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Номер записи: 83
10-10-2013 дата публикации

MOLECULAR LAYER DEPOSITION OF SILICON CARBIDE

Номер: US20130267079A1
Автор: Ingle Nitin K., Mallick Abhijit Basu, Underwood Brian
Принадлежит: Applied Materials, Inc.

Molecular layer deposition of silicon carbide is described. A deposition precursor includes a precursor molecule which contains silicon, carbon and hydrogen. Exposure of a surface to the precursor molecule results in self-limited growth of a single layer. Though the growth is self-limited, the thickness deposited during each cycle of molecular layer deposition involves multiple “atomic” layers and so each cycle may deposit thicknesses greater than typically found during atomic layer depositions. Precursor effluents are removed from the substrate processing region and then the surface is irradiated before exposing the layer to the deposition precursor again. 1. A method of forming a silicon carbide layer on a surface of a substrate positioned in a substrate processing region , the method comprising: (i) irradiating the surface of the substrate,', '(ii) exposing the surface to a silicon-carbon-and-hydrogen-containing precursor comprising a silicon-carbon-and-hydrogen-containing molecule, wherein the silicon-carbon-and-hydrogen-containing molecule has at least two Si—C single-bonds, wherein the step of exposing the surface to a silicon-carbon-and-hydrogen-containing precursor results in growth of a single molecular layer of silicon carbide, and', '(iii) removing process effluents including unreacted silicon-carbon-and-hydrogen-containing precursor from the substrate processing region., 'at least three sequential steps comprising2. The method of claim 1 , further comprising repeating the at least three sequential steps again until the silicon carbide layer reaches a target thickness.3. The method of claim 1 , wherein the step of irradiating the surface comprises shining UV light at the surface of the substrate.4. The method of claim 1 , wherein the step of irradiating the surface comprises flowing gas into and striking a plasma within the substrate processing region.5. The method of claim 1 , wherein the step of exposing the surface to a silicon-carbon-and-hydrogen- ...

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Номер записи: 84
10-10-2013 дата публикации

PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD

Номер: US20130267098A1
Автор: KAWASAKI Hiromichi, MAEDA Kenji, SHIMOMURA Takahiro, Yoshioka Ken
Принадлежит:

A plasma processing apparatus is offered which has evacuable vacuum vessel, processing chamber disposed inside the vacuum vessel and having inside space in which plasma for processing sample to be processed is generated and in which the sample is placed, unit for supplying gas for plasma generation into processing chamber, vacuum evacuation unit for evacuating inside of processing chamber, helical resonator configured of helical resonance coil disposed outside the vacuum vessel and electrically grounded shield disposed outside the coil, RF power supply of variable frequency for supplying RF electric power in given range to the resonance coil, and frequency matching device capable of adjusting frequency of the RF power supply so as to minimize reflected RF power. The resonance coil has electrical length that is set to integral multiple of one wavelength at given frequency. The helical resonance coil has feeding point connected to ground potential using variable capacitive device. 1. A plasma processing apparatus comprising:an evacuable vacuum vessel;a processing chamber disposed inside the vacuum vessel and having an inside space in which a sample to be processed is placed and in which a plasma for processing is generated;a unit for supplying a gas for plasma generation into the processing chamber;a vacuum evacuation unit for evacuating the inside of the processing chamber;a helical resonator configured of a helical resonance coil disposed outside the vacuum vessel and an electrically grounded shield disposed outside the coil;an RF power supply of a variable frequency for supplying RF electric power in a given range to the resonance coil; anda frequency matching device capable of adjusting the frequency of the RF power supply so as to minimize reflected RF electric power;wherein said resonance coil has an electrical length that is set to an integral multiple of one wavelength at said given frequency; andwherein said helical resonance coil has a feeding point ...

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Номер записи: 85
10-10-2013 дата публикации

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS AND EVAPORATION SYSTEM

Номер: US20130267100A1
Автор: TAKAGI Kosuke, Takebayashi Yuji
Принадлежит: HITACHI KOKUSAI ELECTRIC INC.

An amount of particles generated when a source material is used is suppressed. A substrate is loaded into a process chamber, and the source material is sequentially flowed into an evaporator, and a mist filter constituted by assembling a plurality of at least two types of plates including holes disposed at different positions to be evaporated and supplied into the process chamber to process the substrate, and then, the substrate is unloaded from the process chamber. 1. A method of manufacturing a semiconductor device , comprising:(a) loading a substrate into a process chamber;(b) evaporating a source material by sequentially flowing the source to an evaporator and a mist filter comprising one or more first plates and one or more second plates;(c) supplying the source material evaporated in the step (b) into the process chamber to process the substrate; and(d) unloading the substrate from the process chamber,wherein each of the one or more first plates comprises one or more first holes, and each of the one or more second plates comprises one or more second holes disposed at different positions from those of the one or more first holes.2. The method of manufacturing the semiconductor device of claim 1 , wherein the one or more first holes are disposed near an outer circumference of each of the one or more first plates claim 1 , the one or more second holes are disposed near a center of each of the one or more second plates claim 1 , and the one or more first plates and the one or more second plates are alternately disposed claim 1 , andwherein the step (b) comprises evaporating the source material passed through the evaporator by alternately flowing the source material through the one or more first holes and the one or more second holes.3. The method of manufacturing the semiconductor device of claim 1 , wherein the step (b) comprises evaporating the source material sequentially flown through the evaporator and the mist filter by further flowing the source material ...

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Номер записи: 86
17-10-2013 дата публикации

METHODS AND APPARATUS FOR GENERATING AND DELIVERING A PROCESS GAS FOR PROCESSING A SUBSTRATE

Номер: US20130269613A1
Автор: CARLSON DAVID K., SANCHEZ ERROL ANTONIO C.
Принадлежит:

Methods and apparatus for generating and delivering process gases for processing substrates are provided herein. In some embodiments, an apparatus for processing a substrate may include a container comprising a lid, a bottom, and a sidewall, wherein the lid, the bottom, and the sidewall define an open area; a solid precursor collection tray disposed within the open area; a gas delivery tube disposed within the open area and extending toward the solid precursor collection tray to provide a gas proximate the solid precursor collection tray; and a purge flow conduit coupled to the open area. 1. An apparatus for processing a substrate , comprising:a container comprising a lid, a bottom, and a sidewall, wherein the lid, the bottom, and the sidewall define an open area;a solid precursor collection tray disposed within the open area;a gas delivery tube disposed within the open area and extending toward the solid precursor collection tray to provide a gas proximate the solid precursor collection tray; anda purge flow conduit coupled to the open area.2. The apparatus of claim 1 , wherein the apparatus further comprises a precursor delivery tube disposed within the open area and extending toward the solid precursor collection tray.3. The apparatus of claim 2 , wherein the precursor delivery tube further comprises:a first end coupled to an precursor dispenser; anda second end disposed above a storage area of the solid precursor collection tray.4. The apparatus of claim 3 , wherein the precursor dispenser further comprises:a removable hopper comprising a hopper container and least one of a plug valve or a ball valve coupled to a bottom of the hopper container;a fill port, wherein the removable hopper is fitted to the fill port;a rotatable precursor dispenser coupled to the fill port; anda first gas supply coupled to the rotatable precursor dispenser.5. The apparatus of claim 4 , wherein the hopper container is made of quartz.6. The apparatus of claim 4 , wherein the rotatable ...

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Номер записи: 87
17-10-2013 дата публикации

APPARATUS FOR FABRICATING SEMICONDUCTOR DEVICE

Номер: US20130269876A1
Автор: HAN Sung-Ho, HONG Yong-taek, KIM Hee-Seok, KIM Ho-Gon, KIM Ik-Soo, Kim Kyoung-Hwan
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

An apparatus for fabricating a semiconductor device includes a chamber, a processing part inside the chamber, a gas injection pipe connected to the chamber, a gas pumping pipe connected to the chamber, and a baffle assembly embedded in a chamber wall, and the baffle assembly includes a baffle plate having baffle holes, and a baffle guide surrounding an outer surface of the baffle plate. 1. An apparatus for fabricating a semiconductor device , comprising:a chamber;a processing part inside the chamber;a gas injection pipe connected to the chamber;a gas pumping pipe connected to the chamber; anda baffle assembly embedded in a wall of the chamber; wherein the baffle assembly includes:a baffle plate having baffle holes, anda baffle guide surrounding an outer surface of the baffle plate.2. The apparatus as claimed in claim 1 , wherein the baffle plate has a shape of a ring.3. The apparatus as claimed in claim 1 , wherein the baffle holes are arranged along a single horizontal line in the baffle plate.4. The apparatus as claimed in claim 1 , wherein the baffle holes have various sizes.5. The apparatus as claimed in claim 1 , wherein the baffle holes include a recess on a front side of the baffle plate.6. The apparatus as claimed in claim 1 , wherein the baffle plate further includes insertion pins inserted into the respective baffle holes.7. The apparatus as claimed in claim 6 , wherein each of the insertion pins includes:a body having a diameter smaller than that of the respective baffle holes; anda flange having a diameter larger than that of the respective baffle holes.8. The apparatus as claimed in claim 7 , wherein the body has a shape of a cylinder claim 7 , and the flange has a flat zone.9. The apparatus as claimed in claim 8 , wherein the flat zone is inserted into the baffle plate.10. The apparatus as claimed in claim 6 , wherein each of the insertion pins further includes a pin hole in the flange.11. The apparatus as claimed in claim 10 , wherein the pin holes ...

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Номер записи: 88
24-10-2013 дата публикации

SUSCEPTOR ASSEMBLIES FOR SUPPORTING WAFERS IN A REACTOR APPARATUS

Номер: US20130276695A1
Автор: Hamano Manabu, Pitney John Allen
Принадлежит: MEMC ELECTRONIC MATERIALS, INC.

Apparatus and methods for wafer processes such as etching and chemical vapor deposition processes are disclosed. In some embodiments, the apparatus includes a susceptor and a ring disposed beneath the susceptor to influence a thickness of the deposited epitaxial layer. 1. A susceptor assembly for supporting a semiconductor wafer during a wafering process in a reaction apparatus , the susceptor assembly comprising:a susceptor having opposing upper and lower surfaces, the upper surface of the body sized and shaped for supporting a semiconductor wafer therein during the process; anda ring disposed below the lower surface of the susceptor.2. The susceptor assembly of wherein the ring has an outer edge claim 1 , the outer edge being beveled.3. The susceptor assembly of wherein the ring has an outer edge claim 1 , the outer edge being rounded.4. The susceptor assembly of wherein the ring has an outer edge claim 1 , the outer edge having a series of projections and/or notches formed therein.5. The susceptor assembly of claim 1 , wherein the susceptor is generally opaque to absorb radiant heating light produced by high intensity radiant heating lamps.6. The susceptor assembly of claim 1 , wherein the ring is generally transparent material to allow visible and infrared light to pass through the ring.7. The susceptor assembly of claim 1 , wherein the wafering process is epitaxial chemical vapor deposition.8. The susceptor assembly of claim 1 , wherein the susceptor is connected with susceptor supporting members that extend upward from a shaft to support susceptor.9. The susceptor assembly of in claim 1 , wherein the ring is connected through ring supporting members to the susceptor supporting members.10. The susceptor assembly of claim 1 , further comprising a preheat ring spaced radially outward from the susceptor to allow the susceptor to rotate with respect to the preheat ring.11. The susceptor assembly of claim 6 , wherein the preheat ring is generally opaque to absorb ...

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Номер записи: 89
24-10-2013 дата публикации

LIQUID TREATMENT APPARATUS AND METHOD AND NON-TRANSITORY STORAGE MEDIUM

Номер: US20130280425A1
Автор: Yoshida Yuichi, Yoshihara Kousuke
Принадлежит: TOKYO ELECTRON LIMITED

A liquid treatment method includes: supplying a first organic solvent to a substrate with the substrate being held horizontally by a substrate holder; and thereafter supplying a second organic solvent to a substrate held by the substrate holder, the second solvent having a higher cleanliness than the first solvent. 1. A liquid treatment apparatus comprising:a substrate holder configured to hold a substrate horizontally;at least one nozzle configured to supply an organic solvent to a substrate held by the substrate holder;a first organic solvent supply mechanism configured to supply a first solvent to said at least one nozzle;a second organic solvent supply mechanism configured to supply a second solvent to said at least one nozzle, the second solvent having a higher cleanliness than the first solvent; anda controller configured to control the first and second organic solvent supply mechanisms such that said at least one nozzle supplies a substrate with the first organic solvent and then supplies the substrate with the second organic solvent.2. The liquid treatment apparatus according to claim 1 , wherein the controller is configured to control the first and second organic solvent supply mechanisms such that an amount of the second organic solvent supplied to each substrate is less than an amount of the first organic solvent supplied to each substrate.3. The liquid treatment apparatus according to claim 1 , wherein a first nozzle for supplying the first organic solvent and a second nozzle for supplying the second organic solvent are provided as said at least one nozzle.4. The liquid treatment apparatus according to claim 1 , wherein the second organic solvent supply mechanism include a solvent purifying mechanism.5. The liquid treatment apparatus according to claim 4 , wherein the solvent purifying mechanism includes a circulation passage provided therein with a circulation pump and a filter.6. The liquid treatment apparatus according to claim 1 , further comprising: ...

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Номер записи: 90
24-10-2013 дата публикации

METHOD FOR FORMING VAPOR DEPOSITION FILM, AND METHOD FOR PRODUCING DISPLAY DEVICE

Номер: US20130280839A1
Автор: HASHIMOTO Satoshi, INOUE Satoshi, Kawato Shinichi, Sonoda Tohru
Принадлежит: SHARP KABUSHIKI KAISHA

On a surface of a substrate () on which surface a vapor-deposited film is to be formed, a photoresist () is formed so as to have an opening in a sealing region including a display region (R) which sealing region is formed by a sealing resin () of a frame shape. Then, luminescent layers (R, G, and B) having a striped pattern are formed. Subsequently, the photoresist () is removed with the use of an exfoliative solution so as to form the luminescent layers (R, G, and B) patterned with high definition. 1. A method for forming , on a substrate , vapor-deposited films each having a predetermined shape ,the method comprising the steps of:(a) forming, on a surface of the substrate on which surface the vapor-deposited film are to be formed, a pattern film of a predetermined shape which has an opening and which can be peeled off;(b) forming, on the opening and the pattern film, the vapor-deposited films, having a linear shape, that extend in a direction on the substrate and that are provided at certain intervals; and 'in the step (b), the vapor-deposited films are formed by scanning at least one of the substrate and a mask unit with respect to the other,', '(c) peeling the pattern film off from the substrate so that the vapor-deposited films are formed in the predetermined shape,'} 'a predetermined gap being secured between the substrate and the vapor deposition mask of the mask unit.', 'the mask unit including (i) a vapor deposition mask which has a through-hole and is smaller in area than the substrate and (ii) a vapor deposition material supply source, and having (iii) injection holes from which vapor deposition particles supplied from the vapor deposition material supply source are injected, via the vapor deposition mask, towards the surface of the substrate on which surface the pattern film is formed, a relative location of the vapor deposition mask and the injection holes being fixed,'}2. A method for forming , on a substrate , vapor-deposited films each having a ...

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Номер записи: 91
24-10-2013 дата публикации

Method and Apparatus for Wafer Electroless Plating

Номер: US20130280917A1
Автор: Arunagiri Tiruchirapalli, Balisky Todd, Boyd John M., Dordi Yezdi, Owczarz Aleksander, Parks John, Redeker Fritz C., Schoepp Alan M., Thie William, Thomas Clint, Wylie Jacob
Принадлежит:

A semiconductor wafer electroless plating apparatus includes a platen and a fluid bowl. The platen has a top surface defined to support a wafer, and an outer surface extending downward from a periphery of the top surface to a lower surface of the platen. The fluid bowl has an inner volume defined by an interior surface so as to receive the platen, and wafer to be supported thereon, within the inner volume. A seal is disposed around the interior surface of the fluid bowl so as to form a liquid tight barrier when engaged between the interior surface of the fluid bowl and the outer surface of the platen. A number of fluid dispense nozzles are positioned to dispense electroplating solution within the fluid bowl above the seal so as to rise up and flow over the platen, thereby flowing over the wafer when present on the platen. 1. A method for semiconductor wafer electroless plating , comprising:supporting a wafer on a platen;dispensing an electroless plating solution within a liquid retaining volume defined around the platen and at a location below the wafer, wherein the electroless plating solution is dispensed to fill the liquid retaining volume and rise up and flow over a top surface of the wafer in a substantially uniform manner extending inward from a periphery of the top surface of the wafer to a center of the top surface of the wafer;draining the electroless plating solution from the liquid retaining volume so as to remove most of the electroless plating solution from the top surface of the wafer; andrinsing the top surface of the wafer immediately upon draining the electroless plating solution from the liquid retaining volume.2. A method for semiconductor wafer electroless plating as recited in claim 1 , further comprising:lowering the platen into a fluid bowl so as to engage a seal between the platen and the fluid bowl to form the liquid retaining volume defined around the platen and at the location below the wafer.3. A method for semiconductor wafer electroless ...

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Номер записи: 92
31-10-2013 дата публикации

Method For Improving Performance Of A Substrate Carrier

Номер: US20130284091A1
Автор: Mangum Joshua, Quinn William E.
Принадлежит: VEECO INSTRUMENTS INC.

A method of modifying a substrate carrier to improve process performance includes depositing material or fabricating devices on a substrate supported by a substrate carrier. A parameter of layers deposited on the substrate is then measured as a function of their corresponding positions on the substrate carrier. The measured parameter of at least some devices fabricated on the substrate or a property of the deposited layers is related to a physical characteristic of substrate carrier to obtain a plurality of physical characteristics of the substrate carrier corresponding to a plurality of positions on the substrate carrier. The physical characteristic of the substrate carrier is then modified at one or more of the plurality of corresponding positions on the substrate carrier to obtain desired parameters of the deposited layers or fabricated devices as a function of position on the substrate carrier. 140-. (canceled)41. A substrate carrier comprising: a recess that supports a bottom surface of one or more substrates , at least one physical characteristic of localized areas of the recess being modified by first relating a measured parameter of a layer deposited on a top surface of the one or more substrates , which are opposite to the bottom surfaces of the one or more substrates , to the at least one physical characteristic of the recess , and then modifying the at least one physical characteristic of the localized areas of the recess in response to the measured parameter.42. The substrate carrier of wherein the substrate carrier is formed of at least one of graphite claim 41 , SiC claim 41 , metal claim 41 , and ceramic material.43. The substrate carrier of wherein the substrate is formed of at least one of a semiconductor claim 41 , metal claim 41 , and an insulator material.44. The substrate carrier of wherein the relating the measured parameter of the layer deposited on the substrate to the physical characteristic of the recess comprises using a mathematical model ...

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Номер записи: 93
31-10-2013 дата публикации

OPTICS FOR CONTROLLING LIGHT TRANSMITTED THROUGH A CONICAL QUARTZ DOME

Номер: US20130284095A1
Автор: Ranish Joseph M.
Принадлежит:

Embodiments described herein generally relate to apparatus for heating substrates. The apparatus generally include a process chamber having a substrate support therein. A plurality of lamps is positioned to provide radiant energy through an optically transparent dome to a substrate positioned on the substrate support. A light focusing assembly is positioned within the chamber to influence heating and temperature distribution on the substrate and to facilitate formation of a film on a substrate having uniform properties, such as density. The light focusing assembly can include one or more reflectors, light pipes, or refractive lenses. 1. A process chamber , comprising:a chamber body including an optically transparent dome;a substrate support disposed within the chamber body;a plurality of lamps disposed adjacent to the optically transparent dome; anda light focusing assembly positioned within the chamber body between the plurality of lamps and a substrate positioned on the substrate support, the light focusing assembly adapted to influence radiant energy emitted from the plurality of lamps.2. The process chamber of claim 1 , wherein the light focusing assembly comprises a plurality of concentric rings or polygonal approximations to rings.3. The process chamber of claim 2 , wherein at least some of the concentric rings have different heights.4. The process chamber of claim 2 , wherein the concentric rings contain a hollow cavity therein.5. The process chamber of claim 4 , wherein walls of the hollow cavity have a reflective coating thereon.6. The process chamber of claim 5 , wherein the reflective coating comprises silver claim 5 , gold claim 5 , or aluminum.7. The process chamber of claim 4 , wherein the concentric rings each have a thickness within a range of about 2.5 millimeters to about 35 millimeters.8. The process chamber of claim 2 , wherein a support shaft coupled to the substrate support is disposed through a center of an innermost ring of the plurality of ...

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Номер записи: 94
31-10-2013 дата публикации

COOLED REFLECTIVE ADAPTER PLATE FOR A DEPOSITION CHAMBER

Номер: US20130284096A1
Автор: EWERT Maurice E., GOEL ASHISH, SUBRAMANI Anantha
Принадлежит:

In one embodiment, An adapter plate for a deposition chamber is provided. The adapter plate comprises a body, a mounting plate centrally located on the body, a first annular portion extending longitudinally from a first surface of the mounting plate and disposed radially inward from an outer surface of the mounting plate, a second annular portion extending longitudinally from an opposing second surface of the mounting plate and disposed radially inward from the outer surface of the mounting plate, and a mirror-finished surface disposed on the interior of the second annular portion, the mirror-finished surface having an average surface roughness of 6 Ra or less. 1. An adapter plate for a deposition chamber , the adapter plate comprising:a body;a mounting plate centrally located on the body;a first annular portion extending longitudinally from a first surface of the mounting plate and disposed radially inward from an outer surface of the mounting plate;a second annular portion extending longitudinally from an opposing second surface of the mounting plate and disposed radially inward from the outer surface of the mounting plate; anda mirror-finished surface disposed on the interior of the second annular portion, the mirror-finished surface having an average surface roughness of 6 Ra or less.2. The adapter plate of claim 1 , wherein the mirror-finished surface comprises a reflectance of about 70 percent to about 90 percent.3. The adapter plate of claim 2 , wherein the mirror-finished surface is curved.4. The adapter plate of claim 2 , wherein the mirror-finished surface comprises a reflectance of about 85 percent at an angle of incidence of about 85 degrees.5. The adapter plate of claim 2 , wherein the mirror-finished surface comprises a reflectance of about 72 percent.6. The adapter plate of claim 1 , wherein the the body comprises:a first side disposed in a first plane and a second side opposite the first side; anda first sidewall coupled to the first surface, the ...

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Номер записи: 95
31-10-2013 дата публикации

COMPOUND SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME

Номер: US20130285013A1
Автор: An Sung-Jin, Kim Seok-Han, Lee Dong-gun
Принадлежит:

Provided are a compound semiconductor device and a manufacturing method thereof. A substrate and a graphene oxide layer are provided on the substrate. A first compound semiconductor layer is provided on the graphene oxide layer. The first compound semiconductor layer is selectively grown from the substrate exposed by the graphene oxide. 1. A compound semiconductor device , comprising:a substrate;a graphene oxide layer on the substrate; anda first compound semiconductor layer on the graphene oxide layer.2. The compound semiconductor device of claim 1 , wherein the graphene oxide layer includes a plurality of graphene oxide sheets claim 1 , and a portion of a surface of the substrate is exposed between the plurality of the graphene oxide sheets.3. The compound semiconductor device of claim 2 , wherein the first compound semiconductor layer makes a contact with the surface of the substrate exposed between the plurality of the graphene oxide sheets.4. The compound semiconductor device of claim 1 , further comprising:a buffer layer between the substrate and the first compound semiconductor layer, the buffer layer including at least one of AlN, AlGaN, GaN, InGaN, InN or AlGaInN.5. The compound semiconductor device of claim 4 , wherein a thickness of the buffer layer is about 1 nm to about 200 nm.6. The compound semiconductor device of claim 1 , further comprising:a second compound semiconductor layer between the substrate and the graphene oxide layer.7. The compound semiconductor device of claim 6 , wherein the graphene oxide layer includes a plurality of graphene oxide sheets claim 6 , and a portion of a surface of the second compound semiconductor layer is exposed between the plurality of the graphene oxide sheets.8. The compound semiconductor device of claim 1 , wherein the first compound semiconductor layer is a nitride semiconductor layer including at least one of AlN claim 1 , AlGaN claim 1 , GaN claim 1 , InGaN claim 1 , InN or AlGaInN.9. The compound semiconductor ...

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Номер записи: 96
31-10-2013 дата публикации

Metal-Oxide-Semiconductor High Electron Mobility Transistors and Methods of Fabrication

Номер: US20130288461A1
Автор: Dungan Thomas Edward, NIKKEL Philip Gene
Принадлежит:

A method of fabricating Group III-V semiconductor metal oxide semiconductor (MOS) and III-V MOS devices are described. 1. A method of fabricating a semiconductor device , the method comprising:forming a first gate mask;etching a recess in at least one semiconductor layer;atomic layer depositing an oxide layer;forming a second gate mask over the oxide layer; andplating a gate over the oxide layer.2. A method as claimed in claim 1 , further comprising claim 1 , before the forming the second gate mask claim 1 , forming a barrier layer over the oxide layer.3. A method as claimed in claim 2 , further comprising forming a seed layer over the barrier layer.4. A method as claimed in claim 3 , wherein the forming the seed layer further comprises plating the seed layer over the barrier layer.5. A method as claimed in claim 1 , further comprising providing a Group III-V semiconductor substrate and forming a plurality of epitaxial layers over the substrate prior to the forming the first gate mask.6. A method as claimed in claim 5 , wherein the device is a high electron mobility transistor (HEMT) and at least one of the epitaxial layers is a buried channel layer.7. A method as claimed in claim 1 , wherein all steps of the method are carried out at temperatures less than approximately 300° C.8. A method as claimed in claim 1 , wherein the atomic layer deposition is a low temperature (LT) deposition method.9. A method as claimed in claim 8 , wherein the LT deposition is carried out at a temperatures in the range of approximately 25° C. to approximately 150° C.10. A method as claimed in claim 4 , further comprising claim 4 , after the plating the gate claim 4 , removing the second gate mask.11. A method as claimed in claim 10 , wherein the barrier layer and the seed layer are disposed over the first mask layer and the recess claim 10 , and the method further comprises: after removing the second gate mask claim 10 , removing the seed layer and the barrier layer disposed over the ...

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Номер записи: 97
31-10-2013 дата публикации

METHODS AND APPARATUS FOR CONTROLLING SUBSTRATE UNIFORMITY

Номер: US20130288483A1
Автор: Kang Sean S., LUBOMIRSKY DMITRY, NOORBAKHSH HAMID, Quach David H., Sadjadi S.M. Reza, Ye John Zheng
Принадлежит:

A dynamically tunable process kit, a processing chamber having a dynamically tunable process kit, and a method for processing a substrate using a dynamically tunable process kit are provided. The dynamically tunable process kit allows one or both of the electrical and thermal state of the process kit to be changed without changing the phyisical construction of the process kit, thereby allowing plasma properties, and hence processing results, to be easily changed without replacing the process kit. The processing chamber having a dynamically tunable process kit includes a chamber body that includes a portion of a conductive side wall configured to be electrically controlled, and a process kit. The processing chamber includes a first control system operable to control one or both of an electrical and thermal state of the process kit and a second control system operable to control an electrical state of the portion of the side wall. 1. A process kit for a plasma processing chamber , the process kit comprising:a top ring; anda base ring adapted to concentrically support the top ring, the top and base rings having an inside diameter selected to circumscribe a semiconductor wafer, the base ring having a connector configured to couple a signal to the base ring for external control of one or both of a thermal state and an electrical state of the base ring.2. The process kit of claim 1 , wherein the base ring further comprising:a conductive layer coupled to the connector.3. The process kit of claim 1 , further comprising:a heating element coupled to the connector.4. The process kit of claim 3 , wherein the heating element is embedded in the base ring.5. The process kit of claim 1 , wherein the base ring further comprising:a temperature control feature configured to enable the thermal state of the process kit to be controlled.6. The process kit of further comprising:an insulating material disposed on an inside diameter of at least one of the base ring and the top ring.7. The ...

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Номер записи: 98
07-11-2013 дата публикации

METHOD AND DEVICE FOR MEASURING TEMPERATURE OF SUBSTRATE IN VACUUM PROCESSING APPARATUS

Номер: US20130292370A1
Автор: Chen David Zhehao, Lee Steven, Li Yousen
Принадлежит: ADVANCED MICRO-FABRICATION EQUIPMENT INC, SHANGHAI

A method and device for determining temperature of a substrate in a vacuum processing apparatus during a process of the substrate are disclosed, the substrate to be measured is placed on a susceptor in the vacuum processing apparatus for a manufacture process, and the method includes: selecting i wavelengths from radiance emitted from the susceptor through a substrate, where i is a natural number greater than 1; obtaining at least i pieces of radiance corresponding to the selected i wavelengths; and calculating the temperature of the substrate based on the i pieces of radiance and the i wavelengths, by using a mathematical equation: E(λ)=T(d)×M(λ,T), where E(λ) is the ith radiant quantity corresponding to the ith wavelength λ, T(d) is transmittance of the substrate, which is a function of thickness d of a film grown on the substrate, and M(λ,T) is blackbody radiation equation, which is a function of the ith wavelength λand the substrate temperature T. 1. A method for determining temperature of a substrate in a vacuum processing apparatus , the substrate to be measured being placed on a susceptor in the vacuum processing apparatus for a manufacture process , wherein the method comprises:selecting i wavelengths from radiance emitted from the susceptor through a substrate, wherein i is a natural number greater than 1;obtaining at least i pieces of radiance corresponding to the selected i wavelengths; and {'br': None, 'i': E', 'T', 'd', 'M', ',T, 'sub': i', 'i, '(λ)=()×(λ),'}, 'calculating the temperature of the substrate based on the i pieces of radiance and the i wavelengths, by using a mathematical equation{'sub': i', 'i', 'i', 'i', 'i, 'wherein λis the ith wavelength, T is the temperature of the substrate, E(λ) is the ith radiant quantity corresponding to the ith wavelength λ, T(d) is transmittance of the substrate, which is a function of thickness d of a film grown on the substrate, and M(λ,T) is blackbody radiation equation, which is a function of the ith ...

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Номер записи: 99
07-11-2013 дата публикации

High throughput epitaxial liftoff for releasing multiple semiconductor device layers from a single base substrate

Номер: US20130292801A1
Автор: Cheng-Wei Cheng, Kuen-Ting Shiu, Ning Li
Принадлежит: International Business Machines Corp

A semiconductor structure is provided that includes a base substrate, and a multilayered stack located on the base substrate. The multilayered stack includes, from bottom to top, a first sacrificial material layer having a first thickness, a first semiconductor device layer, a second sacrificial material layer having a second thickness, and a second semiconductor device layer, wherein the first thickness is less than the second thickness.

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Номер записи: 100