METHODS OF FORMING INTEGRATED CIRCUIT CAPACITORS HAVING COMPOSITE DIELECTRIC LAYERS THEREIN CONTAINING CRYSTALLIZATION INHIBITING REGIONS

Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers. 1. A method of manufacturing a MIM (metal-insulator-metal) capacitor , comprising:forming a lower electrode using a metal nitride layer;forming a first dielectric film on the lower electrode;forming a crystallization prevention layer on the first dielectric film using a different material from the first dielectric film;forming a second dielectric film on the crystallization prevention layer; andforming a top electrode on the second dielectric film using a metal nitride layer.2. The method of claim 1 , wherein the lower electrode and the top electrode are formed using a metal nitride layer including a titanium nitride layer claim 1 , a tantalum nitride layer and a tungsten nitride layer.3. The method of claim 2 , wherein the lower electrode and the top electrode are formed by CVD (chemical vapor deposition) claim 2 , ALD (atomic layer deposition) or SFD (sequential flow deposition).4. The method of claim 1 , wherein the first dielectric film and the second dielectric film are formed of one selected from high dielectric films including a ...

Methods of Manufacturing Semiconductor Devices

A method of manufacturing a semiconductor device, the method including: preparing a semiconductor substrate including a mold layer and a support layer disposed on the mold layer; forming multiple holes that pass through the mold layer and the support layer; forming multiple bottom electrodes in the holes; exposing at least a portion of the bottom electrodes by removing at least a portion of the mold layer; removing a portion of the bottom electrodes from an exposed surface of the bottom electrodes; and sequentially forming a dielectric layer and a top electrode layer on the bottom electrodes. 1. A method of manufacturing a semiconductor device , the method comprising:forming a plurality of bottom electrodes in a plurality of holes that pass through a mold layer and a support layer;exposing a surface of the plurality of bottom electrodes by removing a portion of the mold layer;removing a portion of ones of the plurality of bottom electrodes from the exposed surface of respective ones of the plurality of bottom electrodes; andsequentially forming a dielectric layer and a top electrode layer on the plurality of bottom electrodes.2. The method according to claim 1 , wherein exposing the portion of the plurality of bottom electrodes by removing the portion of the mold layer comprises performing partial removing operations a plurality of times.3. The method according to claim 1 , wherein removing the portion of the ones of the plurality of bottom electrodes comprises:oxidizing a portion of ones of the plurality of bottom electrodes from each exposed surface of the ones of the plurality of bottom electrodes; andremoving the oxidized portion of the ones of the plurality of bottom electrodes.4. The method according to claim 3 , wherein oxidizing the portion of the ones of the plurality of bottom electrodes is performed in an atmosphere of Oplasma claim 3 , Oplasma claim 3 , O claim 3 , O claim 3 , or HO (vapor) and/or in the air atmosphere.5. The method according to claim 3 ...

Method of Fabricating Semiconductor Device

Methods of fabricating a semiconductor device include forming a deposited film on a semiconductor substrate in a process chamber by repeatedly forming unit layers on the semiconductor substrate. The unit layer is formed by forming a preliminary unit layer on the semiconductor substrate by supplying a process material including a precursor material and film-control material into the process chamber, purging the process chamber, forming a unit layer from the preliminary unit layer, and again purging the process chamber. The precursor material includes a central atom and a ligand bonded to the central atom, and the film-control material includes a hydride of the ligand. 1. A method of fabricating a semiconductor device , comprising:forming a deposited film on a semiconductor substrate in a process chamber by repeatedly forming a unit layer on the semiconductor substrate; forming a preliminary unit layer on the semiconductor substrate by supplying a process material including a precursor material and a film-control material into the process chamber, wherein the precursor material includes a central atom and a ligand bonded to the central atom, and the film-control material comprises a hydride of the ligand of the precursor material;', 'firstly purging the process chamber in which the semiconductor substrate having the preliminary unit layer is located;', 'forming the unit layer from the preliminary unit layer in the firstly purged process chamber; and', 'secondly purging the process chamber in which the semiconductor substrate having the unit layer is located., 'wherein forming the unit layer comprises2. The method according to claim 1 , wherein the precursor material is adsorbed onto the semiconductor substrate to form a precursor-adsorbed layer.3. The method according to claim 2 , wherein the film-control material is coordinated to the central atom of the precursor-adsorbed layer to form a more chemically stable material from the precursor-adsorbed layer than the ...

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A method of manufacturing a semiconductor device includes forming a lower metal layer, forming an interfacial oxide film on the lower metal layer, providing a metal precursor on the interfacial oxide film at a first pressure to adsorb the metal precursor into the interfacial oxide film, performing a first purge process at a second pressure to remove the unadsorbed metal precursor, the second pressure lower than the first pressure, providing an oxidizing gas at the first pressure to react with the adsorbed metal precursor, performing a second purge process at the second pressure to remove the unreacted oxidizing gas and form a dielectric film, and forming an upper metal layer on the dielectric film. 1. A method of manufacturing a semiconductor device , the method comprising:forming a lower metal layer;forming an interfacial oxide film on the lower metal layer;providing a metal precursor on the interfacial oxide film at a first pressure to adsorb the metal precursor into the interfacial oxide film;performing a first purge process at a second pressure to remove the unadsorbed metal precursor, the second pressure lower than the first pressure;providing an oxidizing gas at the first pressure to react with the adsorbed metal precursor;performing a second purge process at the second pressure to remove the unreacted oxidizing gas and form a dielectric film; andforming an upper metal layer on the dielectric film.2. The method of claim 1 , further comprising:performing a first vacuum process at a third pressure lower than the second pressure prior to the providing an oxidizing gas and after the performing a first purge process.3. The method of claim 2 , wherein the providing a metal precursor claim 2 , the performing a first purge process and the performing a first vacuum process are performed sequentially and repeatedly.4. The method of claim 2 , further comprising:performing a second vacuum process at the third pressure after the forming a dielectric film.5. The method of ...

METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING DIELECTRIC LAYER WITH IMPROVED ELECTRICAL CHARACTERISTICS

A semiconductor device having a dielectric layer with improved electrical characteristics and associated methods, the semiconductor device including a lower metal layer, a dielectric layer, and an upper metal layer sequentially disposed on a semiconductor substrate and an insertion layer disposed between the dielectric layer and at least one of the lower metal layer and the upper metal layer, wherein the dielectric layer includes a metal oxide film and the insertion layer includes a metallic material film. 117-. (canceled)18. A method of fabricating a semiconductor device , the method comprising:forming a lower metal layer on a semiconductor substrate;forming an insertion material layer on the lower metal layer, the insertion material layer being substantially oxygen-free as deposited;forming a dielectric layer on the insertion material layer; andforming an upper metal layer on the dielectric layer,wherein the insertion material layer is converted to an insertion layer including a metal oxide, a metal nitride, or a metal oxynitride during the forming of the dielectric layer.19. The method as claimed in claim 18 , wherein the insertion material layer has a lower activation energy than the lower metal layer.20. The method as claimed in claim 19 , wherein the insertion material layer includes a metal film claim 19 , a metal carbide film claim 19 , or a metal nitride film.21. The method as claimed in claim 19 , wherein the insertion material layer includes a zirconium film claim 19 , a zirconium carbide film claim 19 , or a zirconium nitride film.22. The method as claimed in claim 18 , wherein the lower metal layer includes a metal nitride.23. The method as claimed in claim 18 , wherein the insertion layer is formed by an oxidation of the insertion material layer by an Ooxidant during the forming of the dielectric layer.24. The method as claimed in claim 23 , wherein the insertion material layer prevents oxidation of the lower metal layer during forming the dielectric ...

DOOR LOCK DEVICE FOR WASHING MACHINE AND METHOD OF LOCKING WASHING MACHINE DOOR

The present disclosure provides a door lock device for releasably locking a door of a washing machine. The door lock device has first to third latches, and a drive motor and a latch drive mechanism for moving the third latch. The first latch releasably locks the door of the washing machine and is movable in frontward and rearward directions. The movement of the first latch is changed at a change position. The first latch is always biased frontward by a spring. The second latch releasably locks the first latch, which locks the door of the washing machine, at a door locking position. The third latch is moved in a direction perpendicular to the movement direction of the first latch. The third latch restricts the first latch at the door locking position, or unlocks the first latch after pushing the first latch from the door locking position against the spring. 1. A door lock device for releasably locking a door of a washing machine , comprising:a housing;a first latch coupled to the housing to be movable in frontward and rearward directions, the first latch being movable to a door unlocking position where the first latch unlocks the door, a change position located rearward from the door unlocking position, and a door locking position where the first latch locks the door, the door locking position being located between the door unlocking position and the change position;a spring disposed in the housing and biasing the first latch toward the door unlocking position;a second latch releasably locking the first latch at the door locking position;a third latch movably disposed in the housing and releasably locking the first latch, the third latch restricting the first latch at the door locking position and unlocking the first latch after pushing the first latch from the door locking position to the change position against the spring;a drive motor disposed in the housing and driving the third latch; anda latch drive mechanism operably coupled to the drive motor and moving the ...

Semiconductor Devices and Methods of Fabricating the Same

Provided are semiconductor devices and methods of fabricating the same. The methods may include forming a molding layer on a semiconductor substrate. A storage electrode passing through the molding layer is formed. A part of the storage electrode is exposed by partially etching the molding layer. A sacrificial oxide layer is formed by oxidizing the exposed part of the storage electrode. The partially-etched molding layer and the sacrificial oxide layer are removed. A capacitor dielectric layer is formed on the substrate of which the molding layer and the sacrificial oxide layer are removed. A plate electrode is formed on the capacitor dielectric layers.

SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME

Provided are semiconductor devices and methods of fabricating the same. The methods may include forming a molding layer on a semiconductor substrate. A storage electrode passing through the molding layer is formed. A part of the storage electrode is exposed by partially etching the molding layer. A sacrificial oxide layer is formed by oxidizing the exposed part of the storage electrode. The partially-etched molding layer and the sacrificial oxide layer are removed. A capacitor dielectric layer is formed on the substrate of which the molding layer and the sacrificial oxide layer are removed. A plate electrode is formed on the capacitor dielectric layers. 1. A method of fabricating a semiconductor device , comprising:forming a molding layer on a semiconductor substrate;forming a first electrode passing through the molding layer;partially etching the molding layer to expose a part of the first electrode;forming a sacrificial oxide layer by naturally oxidizing the exposed part of the first electrode;removing the partially-etched molding layer and the sacrificial oxide layer;forming a dielectric layer on the substrate of which the molding layer and the sacrificial oxide layer are removed; andforming a second electrode on the dielectric layer.2. The method of claim 1 , wherein forming the sacrificial oxide layer comprises exposing the exposed part of the first electrode to air.3. The method of claim 1 , wherein the first electrode includes a first part having a first width and a second part having a second width that is smaller than the first width claim 1 , and wherein the first part is located distal to the substrate and the second part is located proximal to the substrate.4. The method of claim 3 , wherein the exposed part of the first electrode is the first part of the first electrode claim 3 , and wherein forming the sacrificial oxide layer comprises forming the sacrificial oxide layer on the first part of the first electrode.5. The method of claim 4 , wherein the ...

SEMICONDUCTOR DEVICES INCLUDING CAPACITORS AND METHODS FOR MANUFACTURING THE SAME

The inventive concepts provide semiconductor devices and methods for manufacturing the same in which the method includes forming a capacitor including a bottom electrode, a dielectric layer and a top electrode sequentially stacked on a substrate, and also where formation of the top electrode includes forming a first metal nitride layer on the dielectric layer, and forming a second metal nitride layer on the first metal nitride layer, in which the first metal nitride layer is disposed between the dielectric layer and the second metal nitride layer, and the first metal nitride layer is formed at a temperature lower than a temperature at which the second metal nitride layer is formed. 1. A method for manufacturing a semiconductor device , the method comprising:forming a capacitor including a bottom electrode, a dielectric layer, and a top electrode which are sequentially stacked on a substrate,wherein forming the top electrode comprises:forming a first metal nitride layer on the dielectric layer; andforming a second metal nitride layer on the first metal nitride layer,wherein the first metal nitride layer is disposed between the dielectric layer and the second metal nitride layer, andwherein the first metal nitride layer is formed at a temperature that is lower than a temperature at which the second metal nitride layer is formed.2. The method of claim 1 , wherein the first metal nitride layer and the second metal nitride layer include the same metal element.3. The method of claim 1 , wherein forming the first metal nitride layer comprises: performing a chemical vapor deposition (CVD) process using a first organic metal compound as a precursor in a nitrogen or ammonia gas atmosphere.5. The method of claim 3 , wherein forming the top electrode further comprises:forming a metal oxide layer having conductivity between the dielectric layer and the first metal nitride layer.6. The method of claim 5 , wherein forming the metal oxide layer comprises: performing a chemical ...

SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME

Provided are semiconductor devices and methods of fabricating the same. The methods may include forming a molding layer on a semiconductor substrate. A storage electrode passing through the molding layer is formed. A part of the storage electrode is exposed by partially etching the molding layer. A sacrificial oxide layer is formed by oxidizing the exposed part of the storage electrode. The partially-etched molding layer and the sacrificial oxide layer are removed. A capacitor dielectric layer is formed on the substrate of which the molding layer and the sacrificial oxide layer are removed. A plate electrode is formed on the capacitor dielectric layers. 1. A semiconductor device , comprising:a semiconductor substrate;a storage electrode structure disposed on the semiconductor substrate;a dielectric layer disposed on the storage electrode structure; anda plate electrode disposed on the dielectric layer,wherein the storage electrode structure includes a storage conductive pattern and a core buried structure,wherein the storage conductive pattern comprises a first conductive material and surrounds side and bottom surfaces of the core buried structure, andwherein the core buried structure comprises a core oxide pattern that comprises an oxide of the first conductive material.2. The semiconductor device of claim 1 ,wherein the core buried structure further comprises a core buried pattern on the core oxide pattern, andwherein the core oxide pattern is interposed between the core buried pattern and the storage conductive pattern.3. The semiconductor device of claim 2 , wherein the core buried pattern comprises a metal claim 2 , a metal nitride claim 2 , and/or a metal oxide.4. The semiconductor device of claim 2 , wherein the core buried pattern comprises a second conductive material having a greater hardness than the first conductive material.5. The semiconductor device of claim 1 ,wherein the storage conductive pattern comprises a recessed part of which a top is open, ...

Semiconductor device and method of manufacturing the same

A semiconductor device includes a lower electrode on a substrate, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor dielectric layer. The capacitor dielectric layer includes a base layer on the lower electrode and a dielectric particle layer in at least a portion of the base layer. The base layer includes a first dielectric material, and the dielectric particle layer extends at least partially continuously along a thickness direction of the capacitor dielectric layer and includes a second dielectric material different from the first dielectric material.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a lower electrode on a substrate, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor dielectric layer. The capacitor dielectric layer includes a base layer on the lower electrode and a dielectric particle layer in at least a portion of the base layer. The base layer includes a first dielectric material, and the dielectric particle layer extends at least partially continuously along a thickness direction of the capacitor dielectric layer and includes a second dielectric material different from the first dielectric material.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a lower electrode on a substrate, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor dielectric layer. The capacitor dielectric layer includes a base layer on the lower electrode and a dielectric particle layer in at least a portion of the base layer. The base layer includes a first dielectric material, and the dielectric particle layer extends at least partially continuously along a thickness direction of the capacitor dielectric layer and includes a second dielectric material different from the first dielectric material.

Methods of forming dielectric layers and methods of manufacturing semiconductor devices using the same

To form a dielectric layer, an organometallic precursor is adsorbed on a substrate loaded into a process chamber. The organometallic precursor includes a central metal and ligands bound to the central metal. An inactive oxidant is provided onto the substrate. The inactive oxidant is reactive with the organometallic precursor. An active oxidant is also provided onto the substrate. The active oxidant has a higher reactivity than that of the inactive oxidant.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a lower electrode on a substrate, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor dielectric layer. The capacitor dielectric layer includes a base layer on the lower electrode and a dielectric particle layer in at least a portion of the base layer. The base layer includes a first dielectric material, and the dielectric particle layer extends at least partially continuously along a thickness direction of the capacitor dielectric layer and includes a second dielectric material different from the first dielectric material.

Semiconductor device, method of fabricating the same, semiconductor module, electronic circuit board, and electronic system including the device

Provided are a semiconductor device, a method of fabricating the same, and a semiconductor module, an electronic circuit board, and an electronic system including the device. The semiconductor device includes a lower electrode, a rutile state lower vanadium dioxide layer on the lower electrode, a rutile state titanium oxide on the lower vanadium dioxide layer, and an upper electrode on the titanium oxide layer.

Phase-change memory device

A phase-change memory device, including a lower electrode, a phase-change material pattern electrically connected to the lower electrode, and an upper electrode electrically connected to the phase-change material pattern. The lower electrode may include a first structure including a metal semiconductor compound, a second structure on the first structure, the second structure including a metal nitride material, and including a lower part having a greater width than an upper part, and a third structure including a metal nitride material containing an element X, the third structure being on the second structure, the element X including at least one selected from the group of silicon, boron, aluminum, oxygen, and carbon.

Methods for forming semiconductor devices including thermal processing

Methods for fabricating semiconductor memory devices may include forming a first conductive layer for a first electrode on a semiconductor substrate, forming a dielectric layer on the first conductive layer, and forming a second conductive layer for a second electrode on the dielectric layer. Portions of the second conductive layer and the dielectric layer can be removed, and a thermal process can be performed on the second conductive layer and the dielectric layer. The thermal process can reduce interface stress between the second conductive layer and the dielectric layer and/or cure the dielectric layer. In addition, the dielectric layer may be maintained in an amorphous state during and after the thermal process.

Integrated circuit devices having pad contact plugs in the cell array and peripheral circuit regions of the integrated circuit substrate

Integrated circuit devices, for example, dynamic random access memory (DRAM) devices, are provided including an integrated circuit substrate having a cell array region and a peripheral circuit region. A buried contact plug is provided on the integrated circuit substrate in the cell array region and a resistor is provided on the integrated circuit substrate in the peripheral circuit region. A first pad contact plug is provided on the buried contact plug in the cell array region and a second pad contact plug is provided on the resistor in the peripheral circuit region. An ohmic layer is provided between the first pad contact plug and the buried contact plug and between the second pad contact plug and the resistor. Related methods of fabricating integrated circuit devices are also provided.

Semiconductor device having dielectric layer with improved electrical characteristics and associated methods

A semiconductor device having a dielectric layer with improved electrical characteristics and associated methods, the semiconductor device including a lower metal layer, a dielectric layer, and an upper metal layer sequentially disposed on a semiconductor substrate and an insertion layer disposed between the dielectric layer and at least one of the lower metal layer and the upper metal layer, wherein the dielectric layer includes a metal oxide film and the insertion layer includes a metallic material film.

Methods for forming semiconductor devices including thermal processing

Methods for fabricating semiconductor memory devices may include forming a first conductive layer for a first electrode on a semiconductor substrate, forming a dielectric layer on the first conductive layer, and forming a second conductive layer for a second electrode on the dielectric layer. Portions of the second conductive layer and the dielectric layer can be removed, and a thermal process can be performed on the second conductive layer and the dielectric layer. The thermal process can reduce interface stress between the second conductive layer and the dielectric layer and/or cure the dielectric layer. In addition, the dielectric layer may be maintained in an amorphous state during and after the thermal process.

Metal-insulator-metal capacitors with a chemical barrier layer in a lower electrode and methods of fabricating the same

A metal-insulator-metal (MIM) capacitor includes a lower electrode, a dielectric layer, and an upper electrode. The lower electrode includes a first conductive layer, a chemical barrier layer on the first conductive layer, and a second conductive layer on the chemical barrier layer. The chemical barrier layer is between the first and second conductive layers and is a different material than the first and second conductive layers. The dielectric layer is on the lower electrode. The upper electrode is on the dielectric layer opposite to the lower electrode. The first and second conductive layers can have the same thickness. The chemical barrier layer can be thinner than each of the first and second conductive layers. Related methods are discussed.

Methods of manufacturing semiconductor devices

A method of manufacturing a semiconductor device, the method including: preparing a semiconductor substrate including a mold layer and a support layer disposed on the mold layer; forming multiple holes that pass through the mold layer and the support layer; forming multiple bottom electrodes in the holes; exposing at least a portion of the bottom electrodes by removing at least a portion of the mold layer; removing a portion of the bottom electrodes from an exposed surface of the bottom electrodes; and sequentially forming a dielectric layer and a top electrode layer on the bottom electrodes.

Device and method for opening a door of a refrigerator

Semiconductor device, method of fabricating the same, and semicondutor module, electronic circuit board, and electronic system including the device

Example embodiments relate to a semiconductor device including an oxide dielectric layer and a non-oxide dielectric layer, a method of fabricating the device, and a semiconductor module, an electronic circuit board, and an electronic system including the device. The semiconductor device may include a lower electrode, an oxide dielectric layer disposed on the lower electrode, a non-oxide dielectric layer disposed on the oxide dielectric layer, and an upper electrode disposed on the non-oxide dielectric layer.

Semiconductor device

A semiconductor device includes a substrate, first and second supporter patterns spaced vertically from the substrate, the second supporter pattern being spaced vertically from the first supporter pattern, a lower electrode hole extending vertically on the substrate, a lower electrode inside the lower electrode hole, contacting a sidewall of the first and second supporter patterns, the lower electrode including a first layer along a portion of a sidewall and bottom surface of the lower electrode hole, a second layer between the first layers, and a third layer on an upper surface of the first and second layers, the first and second layers including a material different from the second layer, and a sidewall of at least a portion of the third layer being concave toward the third layer, overlapping the second layer in the vertical direction, and being spaced apart from the second layer in the vertical direction.

1Vorrichtung und Verfahren zum Öffnen einer Tür eines Kühlgerätes

Es werden eine Vorrichtung und ein Verfahren zum Öffnen einer Tür für einen Kühlschrank angegeben. Die Vorrichtung zum Öffnen einer Tür für einen Kühlschrank weit folgendes auf: ein im Inneren des Kühlschranks angebrachtes Gehäuse (1), eine im Inneren des Gehäuses (1) vorgesehene Motoreinheit (9), ein an einer zentralen Ausgangswelle der Motoreinheit (9) angebrachtes Schneckenrad (2), ein mit dem Schneckenrad (2) kämmendes Hilfszahnrad (3), ein Reibungszahnrad (4), das mit dem Hilfszahnrad (3) kämmt und ein Ritzel (11) aufweist, das an einem oberen Ende desselben vorgesehen ist, ein mit dem Ritzel (11) des Reibungszahnrads (4) kämmendes Hauptzahnrad (5), eine Zahnstange (6), deren eine Seite im Inneren des Gehäuses (1) angeordnet ist, um mit dem Hauptzahnrad (5) zu kämmen und deren andere Seite stabförmig ausgebildet an der Außenseite des Gehäuses (1) vorgesehen ist, und eine Signalleiste (24), die an der Zahnstange (6) verschiebbar vorgesehen ist und die an ihrer einen Seite an der Zahnstange (6) angebracht ist und deren andere Seite mit der Innenseite der Kühlschranktür in Kontakt tritt, um die Motoreinheit (9) zu betätigen, wenn eine Absicht zum Öffnen der Kühlschranktür festgestellt wird. Wenn ein Benutzer an dem Griff der Kühlschranktür auch nur leicht zieht oder einen leichten Druck auf diesen ausübt, erfasst die Signalleiste (24) die Intention des Benutzers zum Öffnen der Kühlschranktür und veranlasst die Zahnstange (6), in verschiebbarer Weise mit der Kühlschranktür in Kontakt zu treten, um die Kühlschranktür zu öffnen. Auf diese Weise kann der Benutzer die Tür leicht öffnen, so dass sich die Funktionalität des Kühlschranks verbessern lässt.

共振構造体を有する圧電共振子の形成方法

【課題】共振構造体を有する圧電共振子の形成方法を提供する。 【解決手段】圧電共振子の製造工程を単純化し、そして製造工程において成形体による共振構造体の歩留まりを高める方案を提示する。そのために、基底構造体、保護構造体及び成形体を準備する。前記成形体は選択された２つの面において分極電極をそれぞれに有する。前記成形体は所定方向に沿って一列に整列した分極軸を持つ結晶を有する。前記成形体及び分極電極を所定幅に切断して共振板を形成する。前記共振板上に共振電極を形成する。前記共振電極及び共振板を切断して共振構造体を形成する。そして、前記保護構造体と基底構造体との間に共振構造体を挿入し圧電共振子を形成する。 【選択図】図９

Semiconductor device

A semiconductor device is provided. The semiconductor device comprises a lower electrode, a lower dielectric layer on the lower electrode, an upper electrode on the lower dielectric layer, an upper dielectric layer formed between the lower dielectric layer and the upper electrode, and an interposed electrode film formed between the lower dielectric layer and the upper dielectric layer, wherein the upper dielectric layer includes titanium oxide.

Semiconductor Structures Including Dielectric Layers and Capacitors Including Semiconductor Structures

Semiconductor structures including a first conductive layer; a dielectric layer on the first conductive layer; a second conductive layer on the dielectric layer; and a crystallized seed layer in at least one of a first portion between the first conductive layer and the dielectric layer and a second portion between the dielectric layer and the second conductive layer. Related capacitors and methods are also provided herein.

Semiconductor memory device and method of manufacturing the semiconductor memory device

Example embodiments of the present invention disclose a non-volatile semiconductor memory device, which may include a dielectric layer having an enhanced dielectric constant. A tunnel oxide layer pattern and a floating gate may be sequentially formed on a substrate. A dielectric layer pattern including metal oxide doped with Group III transition metals may be formed on the floating gate using a pulsed laser deposition process. The dielectric layer pattern having an increased dielectric constant may be formed of metal oxide doped with a transition metal such as scandium, yttrium, or lanthanum.

絶縁セラミック基底板を用いたキャップ手段を有する表面実装型共振器及びその形成方法

【課題】キャパシタ及び共振板の上部に良好に積層されるように、絶縁セラミック基底板を用いたキャップ板を有する表面実装型共振器を提供する。 【解決手段】キャパシタ基底板、共振基底板及びキャップ基底板を用意する。前記キャップ基底板は、キャップ端子連結電極及び振動溝を有する。前記振動溝の各々を単位にしてキャップ基底板を切断して、キャップ板を形成する。前記共振基底板は、共振孔と、該共振孔の周囲に共振電極を有する。前記共振電極の各々を単位にして共振基底板を切断して、共振板を形成する。また、前記キャパシタ基底板は、キャパシタ電極、キャパシタ端子連結電極及び他の振動溝を有する。前記他の振動溝の各々を単位にしてキャパシタ基底板を切断して、キャパシタ板を形成する。前記キャパシタ板、共振板及びキャップ板を順に積層して、少なくとも１つの表面実装型共振器を形成することができる。 【選択図】図１

Membrane removal inspection device, membrane removal inspection method, solar cell panel production line and solar cell panel production method

Semiconductor device and method of manufacturing the same

A semiconductor device includes a lower electrode on a substrate, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor dielectric layer. The capacitor dielectric layer includes a base layer on the lower electrode and a dielectric particle layer in at least a portion of the base layer. The base layer includes a first dielectric material, and the dielectric particle layer extends at least partially continuously along a thickness direction of the capacitor dielectric layer and includes a second dielectric material different from the first dielectric material.

Method for manufacturing a capacitor for semiconductor devices

The inventive concepts provide semiconductor devices and methods for manufacturing the same in which the method includes forming a capacitor including a bottom electrode, a dielectric layer and a top electrode sequentially stacked on a substrate, and also where formation of the top electrode includes forming a first metal nitride layer on the dielectric layer, and forming a second metal nitride layer on the first metal nitride layer, in which the first metal nitride layer is disposed between the dielectric layer and the second metal nitride layer, and the first metal nitride layer is formed at a temperature lower than a temperature at which the second metal nitride layer is formed.

Method for manufacturing semiconductor device

A method of manufacturing a semiconductor device includes forming a lower metal layer, forming an interfacial oxide film on the lower metal layer, providing a metal precursor on the interfacial oxide film at a first pressure to adsorb the metal precursor into the interfacial oxide film, performing a first purge process at a second pressure to remove the unadsorbed metal precursor, the second pressure lower than the first pressure, providing an oxidizing gas at the first pressure to react with the adsorbed metal precursor, performing a second purge process at the second pressure to remove the unreacted oxidizing gas and form a dielectric film, and forming an upper metal layer on the dielectric film.

Methods of forming dielectric layers and methods of manufacturing semiconductor devices using the same

To form a dielectric layer, an organometallic precursor is adsorbed on a substrate loaded into a process chamber. The organometallic precursor includes a central metal and ligands bound to the central metal. An inactive oxidant is provided onto the substrate. The inactive oxidant is reactive with the organometallic precursor. An active oxidant is also provided onto the substrate. The active oxidant has a higher reactivity than that of the inactive oxidant.

Semiconductor devices and methods of fabricating the same

Provided are semiconductor devices and methods of fabricating the same. The methods may include forming a molding layer on a semiconductor substrate. A storage electrode passing through the molding layer is formed. A part of the storage electrode is exposed by partially etching the molding layer. A sacrificial oxide layer is formed by oxidizing the exposed part of the storage electrode. The partially-etched molding layer and the sacrificial oxide layer are removed. A capacitor dielectric layer is formed on the substrate of which the molding layer and the sacrificial oxide layer are removed. A plate electrode is formed on the capacitor dielectric layers.