IMPROVEMENTS ON GROWTH FACTORS.

Bottom anti-reflective coating using rapid thermal anneal with oxidizing gas

Etch resistant antireflective coating compositions

POLYMERIC ANTIREFLECTIVE COATINGS DEPOSITED BY PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION

CATHETER SECUREMENT DEVICE

A catheter securement device (100) holds a medical article such as a catheter hub (430) or a connector fitting (300) in position upon the body of a patient and at least inhibits longitudinal movement of the medical article. The securement device (100) includes a retainer (120) and at least one anchor pad (110a, 110b). The retainer (120) forms a central channel (140) into which at least a portion of the medical article is inserted. The retainer (120) includes at least one abutment that can abut against a contact point or surface on the medical article. The abutment, in conjunction with a second abutment and/or a tapering shape of the central channel (120), inhibits motion of the medical article in proximal and distal directions through the central channel (140). For this purpose, the abutment surface(s) can lie either within or outside the channel (140).

Multiple exposure treatment for processing a patterning feature

Composition for forming antireflection film for lithography

With wettable stripping in the middle layer of the semiconductor structure of patterning

Method for manufacturing semiconductor device

Tunable and removable plasma deposited antireflective coatings

POLYMER FOR HIGHER COATING ANTI-REFLECHISSANT, ITS METHOD OF PREPARATION AND COMPOSITION OF HIGHER COATING ANTI-REFLECHISSANT INCLUDING/UNDERSTANDING IT

METHOD FOR FORMING PATTERNS IN A THIN ANTIREFLECTIVE LAYER

L'invention se rapporte au domaine de la fabrication en couches minces des dispositifs électroniques et/ou de MEMS et concerne un procédé amélioré permettant de former un motif dans une couche mince anti-réfléchissante SiARC, comprenant le dopage par implantation de cette couche SiARC recouverte par un motif de résine à travers une couche de protection du motif de résine, puis gravure des zones dopées de la couche SiARC.

REDUCTION OF REFLECTION BY AMORPHOUS CARBON

Composition For Forming Antireflection Film For Lithography

SEMICONDUCTOR PROCESSING METHOD, SEMICONDUCTOR CIRCUITRY, AND GATE STACKS

SEMICONDUCTOR DEVICE AND ITS MANUFACTURE

리소그래피 도포를 위한 소형 분자로부터의 금속-산화물 필름

... 리소그래피 도포를 위한 금속-산화물 필름이 제공된다. 필름은 금속 및 규소 이외의 준금속을 포함하는 금속-산화물 전구체 화합물을 포함하는 조성물로부터 형성된다. 이러한 필름은 쉽게 제조되고, 알콕사이드, 페녹사이드, 카르복실레이트, 베타-디케톤, 및 베타-케토에스테르를 포함하는 다양한 리간드로써 개질될 수 있다.

중합체, 유기막 조성물, 유기막, 및 패턴형성방법

... 화학식 1로 표현되는 부분을 포함하는 중합체, 상기 중합체를 포함하는 유기막 조성물, 상기 유기막 조성물로부터 제조된 유기막, 및 상기 유기막 조성물을 사용하는 패턴형성방법에 관한 것이다. 상기 화학식 1의 정의는 명세서 내에 기재한 바와 같다.

COMPOSITION FOR FORMING ANTIREFLECTION FILM FOR LITHOGRAPHY

A composition for forming an antireflection film, which comprises a compound, an oligomer or a polymer comprising a triazine-trione moiety having a hydroxyalkyl structure as a substitute on a nitrogen atom. The composition can provide an antireflection film which exhibits good absorptivity for a light having a wavelength suitable for use in the production of a semiconductor device, has high antireflection effect, and exhibits a dry etching rate greater than that of a photoresist layer. © KIPO & WIPO 2007 ...

ETCHING METHOD, SUBSTRATE PROCESSING METHOD, PATTERN FORMING METHOD, METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT, AND SEMICONDUCTOR ELEMENT

ANTI-REFLECTIVE COATING COMPOSITIONS FOR USE WITH LOW k DIELECTRIC MATERIALS

Anti-reflective or fill composition which inhibits or blocks via or photoresist poisoning, a method of coating a substrate and curing it, and a cured protective layer derived therefrom comprises a polymer prepared from a first set of recurring monomers containing a ring member reacted with a light attenuating compound, and a second set of recurring monomers having an unreacted ring member. © KIPO & WIPO 2007 ...

A method for fabricating semiconductor device

An antireflective coating composition comprising fused aromatic rings

The present invention relates to an organic spin coatable antireflective coating composition comprising a polymer comprising at least one unit with 3 or more fused aromatic rings in the backbone of the polymer and at least one unit with an aliphatic moeity in the backbone of the polymer. The invention further relates to a process for imaging the present composition.

Plasma etching method, plasma etching apparatus and computer-readable storage medium

Provided are a plasma etching method, a plasma etching apparatus and a computer-readable storage medium capable of plasma-etching a silicon-containing antireflection coating film (Si-ARC) with a high etching rate and a high selectivity while suppressing damage (roughness) of an ArF photoresist. In the plasma etching method, a Si-containing antireflection film 102 located under an ArF photoresist 103 formed on a substrate is etched by plasma of a processing gas while using the ArF photoresist as a mask. A gaseous mixture containing a CF3I gas, an O2 gas, and a CF-based gas and/or a CHF-based gas is used as the processing gas, and a DC voltage is applied to the upper electrode.

Method for manufacturing semiconductor device with four-layered laminate

Disclosed is a laminate used as a foundation layer for a photoresist in a lithography process of semiconductor device production. Also disclosed is a method for manufacturing semiconductor device by using such a laminate. Specifically disclosed is a method for manufacturing a semiconductor device, which comprises a step for forming an organic foundation film (layer A), a silicon-containing hard mask (layer B), an organic antireflective film (layer C) and a photoresist film (layer D) in this order on a semiconductor substrate. The method also comprises a step wherein the photoresist film (layer D) is formed into a resist pattern; the organic antireflective film (layer C) is etched by using the resist pattern; the silicon-containing hard mask (layer B) is etched by using the patterned organic antireflective film (layer C); the organic foundation film (layer A) is etched by using the patterned silicon-containing hard mask (layer B); and the semiconductor substrate is processed by using the ...

Method of fabricating semiconductor device

The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patternable layer over a substrate. The method includes forming a first layer over the patternable layer. The method includes forming a second layer over the first layer. The second layer is substantially thinner than the first layer. The method includes patterning the second layer with a photoresist material through a first etching process to form a patterned second layer. The method includes patterning the first layer with the patterned second layer through a second etching process to form a patterned first layer. The first and second layers have substantially different etching rates during the second etching process. The method includes patterning the patternable layer with the patterned first layer through a third etching process.

A process of imaging a photoresist with multiple antireflective coatings

A process for imaging a photoresist comprising the steps of, (a) forming a stack of multiple layers of organic antireflective coatings on a substrate; (b) forming a coating of a photoresist over the upper layer of the stack of multiple layers of organic antireflective coatings; (c) imagewise exposing the photoresist with an exposure equipment; and, (d) developing the coating with a developer.

Photo mask blank, photo mask and manufacturing method for semiconductor integrated circuit

Provided is a photo mask blank for manufacturing a photo mask suitable for ArF excimer laser, which has a film of multilayer structure on a light-transmissive substrate, and the toppest of the said film is an amorphous structure consisted of a material comprising at least one of chrom, nitrogen, oxygen and carbon.

Simultaneous metal patterning for 3D interconnects

Processing methods may be performed to produce three-dimensional interconnects on a substrate. The methods may include forming a first metal interconnect layer over a semiconductor substrate. The methods may include forming a first dielectric layer over the first metal interconnect layer. The methods may include forming a second metal interconnect layer over the first dielectric layer. The methods may include forming a patterning mask overlying the second metal interconnect layer. The methods may also include simultaneously etching each of the first metal interconnect layer, the first dielectric layer, and the second metal interconnect layer to expose the substrate to produce a multilayer interconnect structure in a first lateral direction.

Apparatus and methods for etching substrates

UNDERLAYER FILM-FORMING COMPOSITION AND PATTERN FORMING PROCESS

Processing system and method for chemically treating a TERA layer

A processing system and method for chemically treating a TERA layer on a substrate. The chemical treatment of the substrate chemically alters exposed surfaces on the substrate. In one embodiment, the system for processing a TERA layer includes a plasma-enhanced chemical vapor deposition (PECVD) system for depositing the TERA layer on the substrate, an etching system for creating features in the TERA layer, and a processing subsystem for reducing the size of the features in the TERA layer.

Method of forming a micro pattern of a semiconductor device

BOTTOM ANTI-REFLECTIVE COATING USING RAPID THERMAL ANNEAL WITH OXIDIZING GAS

A method is provided, the method including forming a gate dielectric layer (110, 410) above a substrate layer (105) and forming a gate conductor layer (115, 415) above the gate dielectric layer (110, 410). The method also comprises forming an inorganic bottom anti-reflective coating layer (120) above the gate conductor layer (115, 415) and treating the inorganic bottom anti-reflective coating layer (120) with an oxidizing treatment (130) during a rapid thermal anneal process.

SEMICONDUCTOR PROCESSING METHODS OF FORMING AND UTILIZING ANTIREFLECTIVE MATERIAL LAYERS, AND METHODS OF FORMING TRANSISTOR GATE STACKS

Selon un mode de réalisation, l'invention concerne un procédé de traitement de semi-conducteur consistant à exposer du silicium, de l'azote, et de l'oxygène sous forme gazeuse à un plasma à densité élevée, pendant le dépôt d'une couche solide contenant le silicium, l'azote, et l'oxygène sur un substrat. Selon un autre mode de réalisation, l'invention concerne un procédé permettant de former un empilement de portes . Selon un autre mode de réalisation, l'invention concerne un procédé de formation d'empilement de portes, consistant a) à former une couche de silicium polycristallin (56) sur un substrat (52); b) à former une couche de siliciure métallique (58) sur ladite couche de silicium polycristallin (56); c) à déposer une couche de matériau antiréfléchissant (60) sur la couche de siliciure métallique (58) à l'aide d'un plasma à densité élevée; d) à former une couche de photorésist (62) sur la couche de matériau antiréfléchissant (60); e) à former des motifs par photolithographie sur la ...

PATTERN FORMING METHOD, RESIST PATTERN, AND PROCESS FOR PRODUCING ELECTRONIC DEVICE

The present invention has an object to provide a pattern forming method capable of providing good DOF and EL, a resist pattern formed by the pattern forming method, and a method for manufacturing an electronic device, including the pattern forming method. The pattern forming method of the present invention includes a step a of coating an active-light-sensitive or radiation-sensitive resin composition onto a substrate to form a resist film, a step b of coating a composition for forming an upper layer film onto the resist film to form an upper layer film on the resist film, a step c of exposing the resist film having the upper layer film formed thereon, and a step d of developing the exposed resist film using a developer to form a pattern, in which the active-light-sensitive or radiation-sensitive resin composition contains a hydrophobic resin.

Method of Forming an Integrated Circuit

A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer.

Antireflective coating layer

Antireflective structures according to the present invention comprise a metal silicon nitride composition in a layer that is superposed upon a layer to be patterned that would other wise cause destructive reflectivity during photoresist patterning. The antireflective structure has the ability to absorb light used during photoresist patterning. The antireflective structure also has the ability to scatter unabsorbed light into patterns and intensities that are ineffective to photoresist material exposed to the patterns and intensities.Preferred antireflective structures of the present invention comprise a semiconductor substrate having thereon at least one layer of a silicon-containing metal or silicon-containing metal nitride. The semiconductor substrate will preferably have thereon a feature size with width dimension less than about 0.5 microns, and more preferably less than about 0.25 microns.One preferred material for the inventive antireflective layer includes metal silicon nitride ternary ...

Method of forming a gate pattern in a semiconductor device

A gate pattern having a critical dimension after an etching process of 60-70nm may be formed using an ArF photoresist as an etching mask by a method including sequentially forming a gate oxide layer, a gate electrode layer, an anti-reflection coating layer, and an ArF photoresist layer on a semiconductor wafer; forming a photoresist pattern by exposing and developing the ArF photoresist layer; etching the anti-reflection coating layer using the photoresist pattern as an etching mask; removing an oxide layer formed during etching of the anti-reflection coating layer; etching the gate electrode layer; and over-etching a remaining gate electrode layer.

Anti-reflective coatings and methods regarding same

A method of forming an anti-reflective coating material layer in the fabrication of integrated circuits includes providing a substrate assembly having a surface and providing an inorganic anti-reflective coating material layer on the substrate assembly surface. The inorganic anti-reflective coating material layer has an associated first etch rate when exposed to an etchant. The method further includes thermally treating the inorganic anti-reflective coating material layer formed thereon such that the thermally treated anti-reflective coating material layer then has an associated second etch rate less than the first etch rate when exposed to the etchant, e.g., the second etch rate is less than 16 Å/minute, the second etch rate is less than 20% of the first etch rate, etc.

Method for critical dimension reduction using conformal carbon films

Embodiments of the disclosure generally provide a method of forming a reduced dimension pattern in a hardmask that is optically matched to an overlying photoresist layer. The method generally comprises of application of a dimension shrinking conformal carbon layer over the field region, sidewalls, and bottom portion of the patterned photoresist and the underlying hardmask at temperatures below the decomposition temperature of the photoresist. The methods and embodiments herein further involve removal of the conformal carbon layer from the bottom portion of the patterned photoresist and the hardmask by an etch process to expose the hardmask, etching the exposed hardmask substrate at the bottom portion, followed by the simultaneous removal of the conformal carbon layer, the photoresist, and other carbonaceous components. A hardmask with reduced dimension features for further pattern transfer is thus yielded.

Antireflective compositions with thermal acid generators

New methods and substrates are provided that include antireflective compositions that comprise one or more thermal acid generators.

Fine Pitch Wire Grid Polarizer

A wire grid polarizer can have a repeated pattern of groups of parallel elongated wires disposed over a substrate. Each group of wires can comprise at least three wires. At least one wire at an interior of each group can be taller than outermost wires of each group. The wires can be a byproduct of an etch reaction.

CVD silicon carbide layer as a BARC and hard mask for gate patterning

A BARC comprising materials having a lower pinhole density than that of silicon oxynitride and materials having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of polysilicon than that of amorphous carbon is employed to reduce deformation of a pattern to be formed in a patternable layer. The patternable layer is formed over a substrate. A multi-layered anti-reflective coating is formed over the patternable layer. A photoresist pattern is formed on the coating. The coating may comprise an amorphous carbon layer formed over the patternable layer and a SiC layer having a lower pinhole density than the pinhole density of SiON formed over the amorphous carbon layer. The coating may also be formed over a polysilicon layer and comprise a thermal expansion buffer layer having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of polysilicon than that of amorphous carbon.

Method for BARC over-etch time adjust with real-time process feedback

A method for determining the anti-reflective coating (or bottom anti-reflective coating) over-etch time adjust with real-time process feedback is presented. The critical dimension CDresist of the patterned photoresist is measured and a first wafer with median values chosen (101) from a lot. A first time t is found (102) and used to form the desired structure. Using the measured critical dimension of the formed structure on the first wafer a second time tlot is found (104). Finally, an over-etch time t(x) is found and used to etch the remaining wafers in the lot (106).

Resist underlayer film forming composition for lithography containing hydrolyzable silane having carbonate skeleton

A method for producing a semiconductor device including: forming an organic underlayer film on a semiconductor substrate; applying the resist underlayer film forming composition onto the organic underlayer film and baking the composition to form a resist underlayer film; applying a resist film forming composition onto the resist underlayer film to form a resist film; exposing the resist film to light; developing the resist film after exposure to obtain a resist pattern; and etching in this order.

DAMASCENE PROCESSING EMPLOYING LOW SI-SION ETCH STOP LAYER/ARC

The dimensional accuracy of trench formation and, hence, metal line width, in damascene technology is improved by employing a low Si-SiON etch stop layer/ARC with reduced etch selectivity with respect to the overlying dielectric material but having a reduced extinction coefficient (k). Embodiments include via first-trench last dual damascene techniques employing a low Si-SiON middle etch stop layer/ARC having an extinction coefficient of about -0.3 to about -0.6, e.g., about -0.35, with reduced silicon and increased oxygen vis--vis a SiON etch stop layer having an extinction coefficient of about -1.1. Embodiments also include removing about 60% to about 90% of the low Si-SiON etch stop layer/ARC during trench formation, thereby reducing capacitance.

COMPOSITION FOR FORMING RESIST UNDERLAYER FILM AND PATTERNING PROCESS

The present invention provides a composition for forming a resist underlayer film, containing an organic solvent and either or both of a compound shown by the following general formula (1) and a condensate of the compound. There can be provided a composition for forming a resist underlayer film that is capable of forming an underlayer film, especially for use in a three-layer resist process, that can reduce reflectance, has high pattern-bend resistance, and prevents line fall and wiggling after etching of a high aspect line especially thinner than 60 nm, and a patterning process using the same. 5. The composition for forming a resist underlayer film according to claim 1 , further comprising a substituted condensate obtained by substituting a part of hydrogen atoms contained in the condensate by a glycidyl group.6. The composition for forming a resist underlayer film according to claim 2 , further comprising a substituted condensate obtained by substituting a part of hydrogen atoms contained in the condensate by a glycidyl group.7. The composition for forming a resist underlayer film according to claim 3 , further comprising a substituted condensate obtained by substituting a part of hydrogen atoms contained in the condensate by a glycidyl group.8. The composition for forming a resist underlayer film according to claim 4 , further comprising a substituted condensate obtained by substituting a part of hydrogen atoms contained in the condensate by a glycidyl group.9. The composition for forming a resist underlayer film according to claim 1 , wherein the composition for forming a resist underlayer film comprises two or more of the compound shown by the general formula (1) claim 1 , the condensate of the compound claim 1 , and a substituted condensate obtained by substituting a part of hydrogen atoms of the condensate by a glycidyl group.10. The composition for forming a resist underlayer film according to claim 2 , wherein the composition for forming a resist underlayer ...

Tunable TiOxNy hardmask for multilayer patterning

Lithographic multilayer structures are disclosed that generally include an organic planarizing layer and a tunable titanium oxynitride layer on the organic planarizing layer, wherein the titanium oxynitride includes TiOxNy, and wherein x is from 2.5 to 3.5 and y is from 0.75 to 1.25. The lithographic multilayer structure further includes a photosensitive resist layer on the titanium oxynitride layer. The tunable titanium oxynitride is configured to function as a hard mask and as an antireflective coating. Also disclosed are methods for patterning the lithographic multilayer structures.

Developer For Lithography

A method for lithography patterning includes forming a material layer over a substrate; exposing a portion of the material layer to a radiation; and removing the exposed portion of the material layer in a developer, resulting in a patterned material layer. The developer comprises water, an organic solvent, and a basic solute. In an embodiment, the basic solute is less than 30% of the developer by weight.

ETCH BACK PROCESS USING NITROUS OXIDE

A method for generating an organic plug within a via is described. The via resides in an integrated circuit (IC) structure having a silicon containing dielectric material. The method for generating the organic plug includes applying an organic compound such as a bottom antireflective coating. The organic compound occupies the via. The method then proceeds to feed a nitrous oxide (N2O) gas into a reactor and generates a plasma in the reactor. A significant portion of the organic compound is removed leaving behind an organic plug to occupy the via. The organic plug is typically generated during dual damascene processing.

Developable bottom antireflective coating composition and pattern forming method using thereof

The present invention relates to a developable bottom antireflective coating (BARC) composition and a pattern forming method using the BARC composition. The BARC composition includes a first polymer having a first carboxylic acid moiety, a hydroxy-containing alicyclic moiety, and a first chromophore moiety; a second polymer having a second carboxylic acid moiety, a hydroxy-containing acyclic moiety, and a second chromophore moiety; a crosslinking agent; and a radiation sensitive acid generator. The first and second chromophore moieties each absorb light at a wavelength from 100 nm to 400 nm. In the patterning forming method, a photoresist layer is formed over a BARC layer of the BARC composition. After exposure, unexposed regions of the photoresist layer and the BARC layer are selectively removed by a developer to form a patterned structure in the photoresist layer. The BARC composition and the pattern forming method are especially useful for implanting levels.

SEMICONDUCTOR DEVICE MANUFACTURING METHOD

There is provided a semiconductor device manufacturing method, including: a film forming process in which, by supplying a solution for modifying a surface layer of a resist to a target object having a resist pattern and allowing the solution to infiltrate into the resist, a film having elasticity and having no compatibility with the resist is formed in the surface layer of the resist; and a heating process in which the target object having the film formed thereon is heated.

Method of forming an integrated circuit

A method of forming an integrated circuit is disclosed. A second material layer is formed on a first material layer. A patterned mask layer having a plurality of first features with a first pitch P1 is formed on the second material layer. The second material layer is etched by using the patterned mask layer as a mask to form the first features in the second material layer. The patterned mask layer is trimmed. A plurality of dopants is introduced into the second material layer not covered by the trimmed patterned mask layer. The trimmed patterned mask layer is removed to expose un-doped second material layer. The un-doped second material layer is selectively removed to form a plurality of second features with a second pitch P2. P2 is smaller than P1.

Multi-layer film stack for extinction of substrate reflections during patterning

A method including introducing a dielectric layer over a substrate between an interconnection line and the substrate, the dielectric layer comprising a plurality of alternating material layers; and patterning an interconnection to the substrate. An apparatus comprising a substrate comprising a plurality of devices formed thereon; and an interlayer dielectric layer comprising a base layer and a cap layer, the cap layer comprising a plurality of alternating material layers overlying the substrate.

Photolithography method and photolithography system

A photolithography method includes dispensing a first liquid onto a first target layer formed over a first wafer through a nozzle at a first distance from the first target layer; capturing an image of the first liquid on the first target layer; patterning the first target layer after capturing the image of the first liquid; comparing the captured image of the first liquid to a first reference image to generate a first comparison result; responsive to the first comparison result, positioning the nozzle and a second wafer such that the nozzle is at a second distance from a second target layer on the second wafer; dispensing a second liquid onto the second target layer formed over the second wafer through the nozzle at the second distance from the second target layer; and patterning the second target layer after dispensing the second liquid.

Semiconductor device and method of manufacture

In a wet etching process to pattern a metal layer such as a p-metal work function layer over a dielectric layer such as a high-k gate dielectric layer, a selectivity of the wet etching solution between the metal layer and the dielectric layer is increased utilizing an inhibitor. The inhibitor includes such inhibitors as a phosphoric acid, a carboxylic acid, an amino acid, or a hydroxyl group.

METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE

In some embodiments, a method of manufacturing an integrated circuit device includes forming a feature structure on a substrate, forming a first hardmask configured to cover the feature structure, forming, on the first hardmask, a second hardmask comprising a plurality of first line portions extending lengthwise in a first horizontal direction and being apart from each other in a second horizontal direction perpendicular to the first horizontal direction, forming, on at least one of the first hardmask and the second hardmask, an etch mask pattern comprising a plurality of second line portions, forming, from the first hardmask, a first hardmask pattern comprising a plurality of third line portions, forming, from the second hardmask, a plurality of second hardmask patterns, and forming a feature pattern comprising a plurality of fourth line portions by etching the feature structure and using the plurality of second hardmask patterns and the first hardmask pattern.

SILICON CARBIDE DEPOSITION METHOD AND USE AS A BARRIER LAYER AND PASSIVATION LAYER

The present invention generally provides an improved process for depositing silicon carbide, using a silane-based material with certain process parameters, onto an electronic device, such as a semiconductor, that is useful for forming a suitable barrier layer, an etch stop, and a passivation layer for IC applications. As a barrier layer, in the preferred embodiment, the particular silicon carbide material is used to reduce the diffusion of copper and may also be used to minimize the contribution of the barrier layer to the capacitive coupling between interconnect lines. It may also be used as an etch stop, for instance, below an intermetal dielectric (IMD) and especially if the IMD is a low k, silane-based IMD. In another embodiment, it may be used to provide a passivation layer, resistant to moisture and other adverse ambient conditions. Each of these aspects may be used in a dual damascene structure.

Dry etching method utilizing (SN)x polymer mask

A dry etching method using no organic resist mask without involving an increase in the number of necessary processes or wafer surface steps. Conventionally, a nitrogen based compound film (6) is formed as a thin anti-reflection film on a gate electrode or aluminum (Al) metallization layer. The nitrogen based compound film (6) thus formed can be used as an etching mask for the material layer by using etching gas capable of forming sulfur (S) in a plasma when dissociated by electric discharges. For instance, a W polycide film (5) masked by a TiON anti-reflection film patterned into a predetermined shape can be etched by S2F2 / H2 mixed gas. In this case, a nitrogen (N) dangling bond formed on the surface of the TiON anti-reflection film (6) combines with sulfur supplied by S2F2 to form a polythiazyl (SN)x coating, which provides the resulting TiON anti-reflection film pattern (6) with a sufficient etching resistance to act as an etching mask. This etching process emits no carbon to the etching ...

METHOD FOR MANUFACTURING INTEGRATED CIRCUIT STRUCTURE

PROBLEM TO BE SOLVED: To provide a method for manufacturing an integrated circuit structure having a semiconductor substrate (40) and depositing a layer (42) to be patterned on the semiconductor substrate (40). SOLUTION: An organic antireflection coating (44) is deposited on the layer (42) to be patterned and an organic photoresist is deposited on it. The photoresist is patterned and developed to form an opening having side walls (52) and to expose a portion of the organic antireflection coating (44). The photoresist (46) and the exposed portion of the antireflection coating (44) absorb inactive molecules. A unidirectional electron-ion bombardment causes desorption of the inactive molecules that gives access of active molecules to the exposed surface of the antireflection coating (44). Bombardment also causes decomposition of the inactive molecules on the exposed surfaces, which produces active atoms. Both processes provide unidirectional removal of the antireflection coating (44) without ...

Verfahren zum thermischen Cracken eines Kohlenwasserstoffgemisches

Verfahren zur Herstellung von Reliefbildern

Developable bottom antireflective coating composition and pattern forming method using thereof

The present invention relates to a developable bottom antireflective coating (BARC) composition and a pattern forming method using the BARC composition. The BARC composition includes a first polymer having a first carboxylic acid moiety, a hydroxy- containing alicyclic moiety, and a first chromophore moiety; a second polymer having a second carboxylic acid moiety, a hydroxy-containing acyclic moiety, and a second chromophore moiety; a crosslinking agent; and a radiation sensitive acid generator. The first and second chromophore moieties each absorb light at a wavelength from 100 nm to 400 nm. In the patterning forming method, a photoresist layer is formed over a BARC layer of the BARC composition. After exposure, unexposed regions of the photoresist layer and the BARC layer are selectively removed by a developer to form a patterned structure in the photoresist layer. The BARC composition and the pattern forming method are especially useful for implanting levels.

Organic anti-reflective coating material and its preparation

Etch process for cd reduction of arc material

PATTERNABLE LOW-K DIELECTRIC INTERCONNECT STRUCTURE WITH A GRADED CAP LAYER AND METHOD OF FABRICATION

Organic anti-reflective polymer and preparation thereof

Photolithography

Photoresist patterning of fine lines and spaces by optical lithography at the metal level is impaired by the existence of standing waves in the photoresist, which are caused by reflections from the metal surface. These reflections can be reduced by interposing a sputtered polysilicon antireflection coating between the metal surface and the photoresist layer to provide optical matching. Optimum thicknesses are determined for the polysilicon layer to achieve minimum reflections. Demonstrations show that polysilicon or aluminium reduces reflectance, gives better line width control and has better gold wire bondability as compared to bare aluminium. ...

OPTICAL LITHOGRAPHIC PROCESSES

Etch process for cd reduction of arc material

Organic Electroluminescent Device

Gaseous phase reaction hydrocarbon cracking methods and apparatus

A gaseous phase reaction method of cracking a hydrocarbon comprises feeding the hydrocarbon in the gaseous phase to a compressing means including at least one movable compressing member, propelling said compressing member through motions which adiabatically compress the geseous hydrocarbon fed to said compressing means, such adiabatic compression being effected in the absence of combustion oxygen and the compression raising the temperature and pressure of the gaseous hydrocarbon to a level sufficient to cause thermal cracking of the hydrocarbon and the formation of cracked hydrocarbon products, and thereafter adiabatically expanding the cracked hydrocarbon products to cool the same and lower the pressure, the cracked hydrocarbon products thereafter being recovered. The hydrocarbon feed may be admixed with steam prior to compression and the energy released by adiabatic expansion of the cracked hydrocarbon products may be used to compress feed hydrocarbon which may be preheated by indirect ...

Semiconductor device and method of manufacture

CHEMICAL EVAPORATION PLASMA-STRENGTHENED POLYMERI ANTI-REFLEX COATINGS, THE BY DEPOSITED

PROCEDURE FOR MANUFACTURING A SILICON NITRIDE LAYER, AS IS USED IT AS ANTIREFLECTION COATING DURING OPTICAL LITHOGRAPHY PROCESSES WITH THE PRODUCTION OF HIGHLY INTEGRATED MONOLITHS.

Catheter securement device

Catheter securement device

PHOTOPATTERNABLE SILICONE POLYAMIC ACID, METHOD OF MAKING AND USE

RD-17,379 use of such silicone polyamic acid, as compared to "Pyralin" polyamic acid, it was found that the problem of premature imidization also occurred during the drying of the applied silicone polyamic acid prior to the spin coating of the photoresist. The work-life of the silicone polyamic acid as well as its usefulness during the development of the applied photoresist also was unsatisfactory. The present invention is based on the discovery that certain silicone polyamic acids, resulting from the use of a siloxane containing norbornane bisanhydride (DiSiAn), shown by Ryang U.S. patent 4,381,396, assigned to the same assignee as the present invention, in combination with benzophenone dianhydride (BTADA) and aryldiamine, have been found to resist excessive imidization during the initial drying step of the silicone polyamic acid after its application to a substrate. Temperatures up to 125.degree.C for a period of 60 minutes can be used to make tack-free silicone polyamic acids which can ...

SELF-LIMITING CYCLIC ETCH METHOD FOR CARBON-BASED FILMS

Method of forming semiconductor device and methods of patterning semiconductor device

REFLECTIVE ANTI-REFLECTING SURFACE TREATMENT

La présente invention a trait à un procédé de photolithographie amélioré, particulièrement adapté aux techniques de lithographie optique à haute résolution utilisant les raies g, h et i du spectre du mercure et les UV à courte longueur d'onde, comprenant, préalablement au dépôt de la résine photosensible sur la couche de matériau à lithographier, la formation d'une couche poreuse anti-réflective au sein même de ladite couche à lithographier et à la surface de celle-ci ...

ANTHRACENYLMETHYL (METH) ACRYLATES, POLYMERS WHICH THEY MAKE IT POSSIBLE TO PREPARE AND COATINGS ANTI-REFLECHISSANTS THE CONTAINER

L'invention concerne des anthracénylméthyl (méth)acrylates répondant à l'une des formules suivantes : (formule chimique 19) (formule chimique 20) L'invention concerne également la préparation de polymères à partir de ces anthracénylméthyl (méth)acrylates, par polymérisation en présence de monomères de type hydroxyalkylacrylate, de monomères de type glycidylacrylate et éventuellement de monomères de type méthylméthacrylate. Enfin, l'invention concerne des revêtement anti-réfléchissants contenant ces polymères et qui sont utilisables pour la fabrication de dispositifs semi-conducteurs.

PROCEEDED OF FORMATION Of a FILM ANTIREFLECHISSANT SION, NON-POLLUTING LIVED PHOTORESISTIVE RESINS FOR U.V. DISTANCE

Le procédé selon l'invention comprend, avant l'introduction du substrat de silicium dans la chambre du réacteur et le dépôt sur le substrat par dépôt chimique en phase vapeur assisté par plasma du film de SiON et le traitement du film déposé pour un plasma d'oxygène, un nettoyage de la chambre du réacteur comportant une étape de purge de la chambre au moyen d'un plasma gazeux exempt d'oxygène suivie d'une étape de dépôt à blanc de SiON par dépôt chimique en phase vapeur assisté par plasma. Application à la fabrication de dispositifs semi-conducteurs.

(GE,SI)NX PREVENTIVE FILM OF REFLECTION AND METHOD FOR FORMING PATTERN BY MAKING USE THEREOF

PURPOSE: A (Ge,Si)Nx preventive film of reflection and a method for forming a pattern by making use thereof provided to prevent a GeNx preventive film from dissolving in water by controlling the water-soluble of the GeNx preventive film of reflection itself. CONSTITUTION: The first material layer(52) is formed on a semiconductor substrate(50) to cover the lower structure including a transistor and so on. In order to form a pattern on the first material layer(52), the second material layer(54) is formed. A preventive film of reflection(56) comprising (Ge,Si)Nx is formed on the second material layer(54) not to reflect light incident on the second material layer(54). A photoresist film(58) is formed on the preventive film of reflection(56). The photoresist film(58) is exposed by making use of a photomask(60), so that a photoresist pattern, which is used as a mask in forming the pattern of the second material layer(54), is formed. COPYRIGHT 2001 KIPO ...

Coating Compositions for Photolithography

... 제 1 일예에서, (a) 기판상에 경화성 조성물을 도포하고; (b) 경화성 조성물 위에 하드 마스크 조성물을 도포하며; (c) 하드 마스크 조성물 위에 포토레지스트 조성물 층을 도포하는 것을 포함하는 방법이 제공되며, 여기서 하나 이상의 조성물이 무회분(ash-free) 공정으로 제거된다. 제 2 일예에서, (a) 기판상에 유기 조성물을 도포하고; (b) 유기 조성물 위에 포토레지스트 조성물을 도포하는 것을 포함하는 방법이 제공되며, 여기서 유기 조성물은 열 및/또는 조사선 처리시 알칼리-가용성 그룹을 생성하는 물질을 포함한다. 관련 조성물이 또한 제공된다.

반도체 디바이스 구조의 상호 연결 구조체의 비아를 클리닝하는 방법

... 반도체 디바이스 구조의 형성 방법이 제공된다. 방법은 기판 위의 제1 유전체층 내에 금속층을 형성하는 단계와 금속층 위에 에칭 정지층을 형성하는 단계를 포함한다. 에칭 정지층은 금속 함유 재료로 제조된다. 방법은 또한 에칭 정지층 위에 제2 유전체층을 형성하는 단계와, 제2 유전체층의 일부를 제거하여 에칭 정지층을 노출시키고 에칭 프로세스에 의해 비아를 형성하는 단계를 포함한다. 방법은 비아 및 제2 유전체층에 대해 플라즈마 클리닝 프로세스를 수행하는 단계를 더 포함하고, 플라즈마 클리닝 프로세스는 질소 가스(N2)와 수소 가스(H2)를 포함하는 플라즈마를 이용하여 수행된다.

Conductive interconnects in an integrated circuit-connection conductive interconnects connection structure and method

CD BIAS LOADING CONTROL WITH ARC LAYER OPEN

A METHOD OF FORMING A TEOS CAP LAYER AT LOW TEMPERATURE AND REDUCED DEPOSITION RATE

The present invention discloses a method for forming a silicon dioxide cap layer for a carbon hard mask layer for the patterning of polysilicon line features having critical dimensions of 50 nm and less. To this end, a low temperature plasma- enhanced CVD process is used, in which the deposition rate is maintained low to provide improved controllability of the layer thickness and, thus, of the optical characteristics of the silicon dioxide layer. © KIPO & WIPO 2007 ...

Self-aligned permanent on-chip interconnect structure formed by pitch splitting

A method of fabricating an interconnect structure is provided. The method includes forming a hybrid photo-patternable dielectric material atop a substrate. The hybrid photo-patternable dielectric material has dual-tone properties with a parabola like dissolution response to radiation. The hybrid photo-patternable dielectric material is then image-wise exposed to radiation such that a self-aligned pitch split pattern forms. A portion of the self-aligned split pattern is removed to provide a patterned hybrid photo-patternable dielectric material having at least one opening therein. The patterned hybrid photo-patternable dielectric material is then converted into a cured and patterned dielectric material having the at least one opening therein. The at least one opening within the cured and patterned dielectric material is then filed with at least an electrically conductive material. Also provided are a hybrid photo-patternable dielectric composition and an interconnect structure.

Method and system for removal of films from peripheral portions of a substrate

A substrate processing apparatus includes an anti-reflection film processing block, a resist film processing block, and a resist cover film processing block. In the processing blocks, an anti-reflection film, a resist film, and a resist cover film are formed on a substrate, respectively. Additionally, a film formed at a peripheral edge of the substrate is removed. The film formed at the peripheral edge of the substrate is removed by supplying a removal liquid capable of dissolving and removing the film to the peripheral edge of the substrate during rotation. When the peripheral edge of the film is removed, the position of the substrate is corrected such that the center of the substrate coincides with the center of a rotation shaft.

Multilayer low reflectivity hard mask and process therefor

A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN).

System and method of vapor deposition

Provided is a system for vapor deposition of a coating material onto a semiconductor substrate. The system includes a chemical supply chamber, a supply nozzle operable to dispense vapor, and a heating element operable to provide heat to a substrate in-situ with the dispensing of vapor. The system may further include reaction chamber(s) and/or mixing chamber(s).

Method and structure for reworking antireflective coating over semiconductor substrate

A method and a structure for reworking an antireflective coating (ARC) layer over a semiconductor substrate. The method includes providing a substrate having a material layer, forming a planarization layer on the material layer, forming an organic solvent soluble layer on the planarization layer, forming an ARC layer on the organic solvent soluble layer, forming a pattern in the ARC layer, and removing the organic solvent soluble layer and the ARC layer with an organic solvent while leaving the planarization layer unremoved. The structure includes a substrate having a material layer, a planarization layer on the material layer, an organic solvent soluble layer on the planarization layer, and an ARC layer on the organic solvent soluble layer.

Self-aligned permanent on-chip interconnect structure formed by pitch splitting

A hybrid photo-patternable dielectric material is provided that has dual-tone properties with a parabola like dissolution response to radiation. In one embodiment, the hybrid photo-patternable dielectric material includes a composition of at least one positive-tone component including a positive-tone polymer, positive-tone copolymer, or blends of positive-tone polymers and/or positive-tone copolymers having one or more acid sensitive positive-tone functional groups; at least one negative-tone component including a negative-tone polymer, negative-tone copolymer, or blends of negative-tone polymers and/or negative-tone copolymers having one or more acid sensitive negative-tone functional groups; at least one photoacid generator; and at least one solvent that is compatible with the positive-tone and negative-tone components.

Patternable low-k dielectric interconnect structure with a graded cap layer and method of fabrication

An interconnect structure is provided that includes at least one patterned and cured low-k material located on a surface of a patterned graded cap layer. The at least one cured and patterned low-k material and the patterned graded cap layer each have conductively filled regions embedded therein. The patterned and cured low-k material is a cured product of a functionalized polymer, copolymer, or a blend including at least two of any combination of polymers and/or copolymers having one or more acid-sensitive imageable groups, and the graded cap layer includes a lower region that functions as a barrier region and an upper region that has antireflective properties of a permanent antireflective coating.

Interconnect structure including a modified photoresist as a permanent interconnect dielectric and method of fabricating same

An interconnect structure is provided that may include at least one cured permanent patterned dielectric material located on a surface of a substrate. The at least one cured permanent patterned dielectric material is a cured product of a patterned photoresist that includes a dielectric enabling element therein. The structure further includes at least one conductively filled region embedded within the at least one cured permanent patterned dielectric material.

Multilayer antireflection coatings, structures and devices including the same and methods of making the same

Multi-layer antireflection coatings, devices including multi-layer antireflection coatings and methods of forming the same are disclosed. A block copolymer is applied to a substrate and self-assembled into parallel lamellae above a substrate. The block copolymer may optionally be allowed to self-assemble into a multitude of domains oriented either substantially parallel or substantially perpendicular to an underlying substrate.

Etch resistant alumina based coatings

Method of forming a protective hard mask layer on a substrate in a semiconductor etch process, comprising the step of applying by solution deposition on the substrate a solution or colloidal dispersion of an alumina polymer, said solution or dispersion being obtained by hydrolysis and condensation of monomers of at least one aluminium oxide precursor in a solvent or a solvent mixture in the presence of water and a catalyst. The invention can be used for making a hard mask in a TSV process to form a high aspect ratio via a structure on a semiconductor substrate.

SELECTIVE DEPOSITION OF CARBON ON PHOTORESIST LAYER FOR LITHOGRAPHY APPLICATIONS

Embodiments disclosed within include a method for etching a hardmask layer includes forming a photoresist layer comprising an organometallic material on a hardmask layer comprising a metal-containing material, exposing the photoresist layer to ultraviolet radiation through a mask having a selected pattern, removing un-irradiated areas of the photoresist layer to pattern the photoresist layer, forming a passivation layer comprising a carbon-containing material selectively on a top surface of the patterned photoresist layer, including selectively depositing passivation material over a top surface of a patterned photoresist layer trimming undesired portions of the passivation material, and etching the hardmask layer exposed by the patterned photoresist layer having the passivation layer formed thereon. 1. A method for etching a hardmask layer , comprising:forming a photoresist layer comprising an organometallic material on the hardmask layer;exposing the photoresist layer to ultraviolet radiation through a mask having a selected pattern;removing un-irradiated areas of the photoresist layer to form a patterned photoresist layer; selectively depositing passivation material over the top surface; and', 'trimming undesired portions of the passivation material; and, 'forming a passivation layer comprising a carbon-containing material selectively on a top surface of the patterned photoresist layer, wherein the forming the passivation layer comprisesetching the hardmask layer exposed by the patterned photoresist layer having the passivation layer formed thereon.2. The method of claim 1 , wherein the organometallic material comprises one or more metal elements and organic ligands.3. The method of claim 2 , wherein the one or more metal elements comprise tin (Sn).4. The method of claim 1 , wherein the trimming the undesired portions comprises exposing the passivation material to a radical etch.5. The method of claim 1 , wherein the forming of the passivation layer comprises: ...

Metal via structure

A semiconductor device includes a stack structure having at least first, second and third interconnect levels. Each interconnect level has a patterned metal conductor including a first metallic material. A via spans the second and third interconnect levels and electrically couples with the patterned metal conductor of the first interconnect level. At least a segment of the super via includes a second metallic material different from the first metallic material.

Photolithography Method and Photolithography System

A photolithography method includes dispensing a first liquid onto a first target layer formed over a first wafer through a nozzle at a first distance from the first target layer; capturing an image of the first liquid on the first target layer; patterning the first target layer after capturing the image of the first liquid; comparing the captured image of the first liquid to a first reference image to generate a first comparison result; responsive to the first comparison result, positioning the nozzle and a second wafer such that the nozzle is at a second distance from a second target layer on the second wafer; dispensing a second liquid onto the second target layer formed over the second wafer through the nozzle at the second distance from the second target layer; and patterning the second target layer after dispensing the second liquid. 1. A photolithography method , comprising:dispensing a first liquid onto a first target layer formed over a first wafer through a nozzle at a first distance from the first target layer;capturing an image of the first liquid on the first target layer;patterning the first target layer after capturing the image of the first liquid;comparing the captured image of the first liquid to a first reference image to generate a first comparison result;responsive to the first comparison result, positioning the nozzle relative to a second wafer such that the nozzle is at a second distance from a second target layer on the second wafer wherein the second distance is different from the first distance;dispensing a second liquid onto the second target layer formed over the second wafer through the nozzle at the second distance from the second target layer; andpatterning the second target layer after dispensing the second liquid.2. The photolithography method of claim 1 , wherein capturing the image of the first liquid is performed during dispensing of the first liquid.3. (canceled)4. The photolithography method of claim 1 , further comprising:curing ...

Lithography Mask and Method

In an embodiment, a photomask includes: a substrate over a first conductive layer, the substrate formed of a low thermal expansion material (LTEM); a second conductive layer over the first conductive layer; a reflective film stack over the substrate; a capping layer over the reflective film stack; an absorption layer over the capping layer; and an antireflection (ARC) layer over the absorption layer, where the ARC layer and the absorption layer have a plurality of openings in a first region exposing the capping layer, where the ARC layer, the absorption layer, the capping layer, and the reflective film stack have a trench in a second region exposing the second conductive layer. 1. A photomask comprising:a first conductive layer;a conductive feature over the first conductive layer, the conductive feature being different from the first conductive layer;a reflective film stack over the conductive feature, the reflective film stack comprising alternating layers of a first material and a second material, the first material having a higher refractive index than the second material; andan absorptive film stack over the reflective film stack, wherein the absorptive film stack has first openings exposing the reflective film stack, and wherein the absorptive film stack and the reflective film stack have a second opening exposing the conductive feature, the second opening surrounding the first openings.2. The photomask of claim 1 , wherein the conductive feature comprises second conductive layers claim 1 , and further comprising:a substrate disposed between the first conductive layer and the second conductive layers, the substrate being a low thermal expansion material (LTEM).3. The photomask of claim 2 , wherein each of the second conductive layers are TaBN claim 2 , TaBO claim 2 , TaBON claim 2 , CrN claim 2 , CrON claim 2 , CrO claim 2 , ITO claim 2 , or TaO.4. The photomask of claim 1 , wherein the conductive feature comprises a second conductive layer claim 1 , the second ...

COMPOSITION FOR FORMING ORGANIC FILM, SUBSTRATE FOR MANUFACTURING SEMICONDUCTOR DEVICE, METHOD FOR FORMING ORGANIC FILM, PATTERNING PROCESS, AND POLYMER

A composition for forming an organic film contains a polymer having a partial structure shown by the following general formula (1) as a repeating unit, and an organic solvent. Each of AR1 and AR2 represents a benzene ring or naphthalene ring which optionally have a substituent; Wrepresents a particular partial structure having a triple bond, and the polymer optionally contains two or more kinds of W; and Wrepresents a divalent organic group having 6 to 80 carbon atoms and at least one aromatic ring. This invention provides: a polymer curable even under film formation conditions in an inert gas and capable of forming an organic film which has not only excellent heat resistance and properties of filling and planarizing a pattern formed in a substrate, but also favorable film formability onto a substrate with less sublimation product; and a composition for forming an organic film, containing the polymer. 3. The composition for forming an organic film according to claim 1 , wherein the polymer has a weight-average molecular weight of 1000 to 5000.4. The composition for forming an organic film according to claim 1 , wherein the organic solvent is a mixture of one or more organic solvents each having a boiling point of lower than 180° C. and one or more organic solvents each having a boiling point of 180° C. or higher.5. The composition for forming an organic film according to claim 1 , further comprising at least one of a surfactant and a plasticizer.6. A substrate for manufacturing a semiconductor device claim 1 , comprising an organic film on the substrate claim 1 , the organic film being formed by curing the composition for forming an organic film according to .7. A method for forming an organic film employed in a semiconductor device manufacturing process claim 1 , the method comprising the steps of:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'spin-coating a substrate to be processed with the composition for forming an organic film according to ; and'}heating ...

Lithography Mask and Method

In an embodiment, a photomask includes: a substrate over a first conductive layer, the substrate formed of a low thermal expansion material (LTEM); a second conductive layer over the first conductive layer; a reflective film stack over the substrate; a capping layer over the reflective film stack; an absorption layer over the capping layer; and an antireflection (ARC) layer over the absorption layer, where the ARC layer and the absorption layer have a plurality of openings in a first region exposing the capping layer, where the ARC layer, the absorption layer, the capping layer, and the reflective film stack have a trench in a second region exposing the second conductive layer. 1. A photomask comprising:a substrate over a first conductive layer, the substrate formed of a low thermal expansion material (LTEM);a second conductive layer over the first conductive layer;a reflective film stack over the substrate;a capping layer over the reflective film stack;an absorption layer over the capping layer; andan antireflection (ARC) layer over the absorption layer, wherein the ARC layer and the absorption layer have a plurality of openings in a first region exposing the capping layer, wherein the ARC layer, the absorption layer, the capping layer, and the reflective film stack have a trench in a second region exposing the second conductive layer.2. The photomask of claim 1 , further comprising:a conductive film stack between the substrate and the reflective film stack, the conductive film stack comprising a plurality of conductive layers, the plurality of conductive layers including the second conductive layer.3. The photomask of claim 2 , wherein a bottommost layer of the reflective film stack physically contacts a topmost layer of the conductive film stack.4. The photomask of claim 1 , wherein a bottommost layer of the reflective film stack physically contacts the substrate.5. The photomask of claim 4 , wherein the second conductive layer is a doped region in a top surface ...

SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD

A substrate processing apparatus includes a spin chuck that holds a substrate, a processing liquid supply unit that supplies a first processing liquid having first specific gravity and a second processing liquid having second specific gravity smaller than the first specific gravity to a surface to be processed of the substrate held by the spin chuck, a collection tank that stores the used first and second processing liquids that have been supplied to the substrate, and a processing liquid separating mechanism that separates the first processing liquid and the second processing liquid based on specific gravity, the first and second processing liquids being stored in the collection tank. 1. A substrate processing apparatus comprising:a substrate holder that holds a substrate;a processing liquid supply unit that supplies a first processing liquid having first specific gravity and a second processing liquid having second specific gravity smaller than the first specific gravity to a surface to be processed of the substrate held by the substrate holder;a storage that stores the used first and second processing liquids that have been supplied to the substrate; anda processing liquid separating mechanism that separates the first processing liquid and the second processing liquid based on specific gravity, the first and second processing liquids being stored in the storage.2. The substrate processing apparatus according to claim 1 , whereinthe processing liquid separating mechanism includesa first discharge pipe provided to discharge the used first processing liquid from the storage,a second discharge pipe provided to discharge the used second processing liquid from the storage,a first discharge valve inserted into the first discharge pipe,a boundary surface detector that detects a boundary surface between the first processing liquid and the second processing liquid that are stored in the storage, anda controller that acquires the boundary surface detected by the boundary ...

METHOD OF FABRICATING A SEMICONDUCTOR STRUCTURE WITH A SELF-ALIGNED CONTACT

A method of fabricating a semiconductor structure includes the following steps: forming a first interlayer dielectric on a substrate; forming a gate electrode on the substrate so that the periphery of the gate electrode is surrounded by the first interlayer dielectric; forming a patterned mask layer comprising at least a layer of organic material on the gate electrode; forming a conformal dielectric layer to conformally cover the layer of organic material; and forming a second interlayer dielectric to cover the conformal dielectric layer. 1. A method of fabricating a semiconductor structure , comprising:forming a dummy gate electrode on the substrate;forming a first interlayer dielectric on a substrate after the step of forming the dummy gate electrode;removing the dummy gate electrode to leave a trench in the first interlayer dielectric;forming a gate electrode in the trench, wherein a periphery of the gate electrode is surrounded by the first interlayer dielectric;forming a hard mask on a top surface of the gate electrode;forming a patterned mask layer comprising at least a layer of organic material on the gate electrode after the step of forming the hard mask;forming a conformal dielectric layer to conformally cover the layer of organic material; andforming a second interlayer dielectric to cover the conformal dielectric layer.2. The method of claim 1 , wherein the step of forming the patterned mask layer comprises:coating a photoresist layer on the first interlayer dielectric; andpatterning the photoresist layer so as to form a patterned photoresist.3. The method of claim 1 , wherein the step of forming the patterned mask layer further comprises:coating an organic dielectric layer on the first interlayer dielectric;coating an anti-reflection layer on the organic dielectric layer;coating a photoresist layer on the anti-reflection layer;patterning the photoresist layer so as to form a patterned photoresist; andetching the anti-reflection layer by using the ...

Photoresist and Method of Manufacture

A system and method for anti-reflective layers is provided. In an embodiment the anti-reflective layer comprises a floating additive in order to form a floating additive region along a top surface of the anti-reflective layer after the anti-reflective layer has dispersed. The floating additive may comprise an additive group which will decompose along with a fluorine unit bonded to the additive group which will decompose. Additionally, adhesion between the middle layer and the photoresist may be increased by applying an adhesion promotion layer using either a deposition process or phase separation, or a cross-linking may be performed between the middle layer and the photoresist. 1. A method of manufacturing a semiconductor device , the method comprising: a group to be decomposed; and', 'a fluorine group bonded to the group to be decomposed; and, 'dispensing an anti-reflective material over a substrate to form an anti-reflective coating layer, the anti-reflective material having a first concentration of a floating additive, wherein the floating additive further comprisesforming a floating region adjacent to a top surface of the anti-reflective coating, the floating region having a second concentration of the floating additive greater than the first concentration.2. The method of claim 1 , wherein the group to be decomposed further comprises an acid labile group.3. The method of claim 1 , wherein the floating region further comprises a catalyst.4. The method of claim 3 , wherein the catalyst is a thermal acid generator.5. The method of claim 4 , further comprising baking the floating region claim 4 , wherein the baking the floating region initiates a reaction between the thermal acid generator and the floating additive which cleaves the group to be decomposed.6. The method of claim 1 , wherein the fluorine group is a substituted fluorine.7. The method of claim 1 , further comprising applying a middle layer to the floating region.8. A method of manufacturing a ...

Spacer Etching Process for Integrated Circuit Design

A method includes forming a first material layer on a substrate and performing a first patterning process using a first layout to form a first plurality of trenches in the first material layer. The method further includes performing a second patterning process using a second layout to form a second plurality of trenches in the first material layer, wherein the second layout a cut pattern for the first layout. The method further includes forming spacer features on sidewalls of both the first and second pluralities of trenches, wherein the spacer features have a thickness and the cut pattern corresponds to a first trench of the second plurality whose width is less than twice the thickness of the spacer features. The method further includes removing the first material layer; forming a second material layer on the substrate and within openings defined by the spacer features; and removing the spacer features. 1. A method , comprising:forming a first material layer on a substrate;performing a first patterning process using a first layout to form a first plurality of trenches in the first material layer, the first layout including a first subset of a target pattern;performing a second patterning process using a second layout to form a second plurality of trenches in the first material layer, the second layout including a second subset of the target pattern and a cut pattern for the first subset;forming spacer features on sidewalls of both the first plurality of trenches and the second plurality of trenches, the spacer features having a thickness, wherein the cut pattern corresponds to a first trench of the second plurality whose width is less than twice the thickness of the spacer features;removing the first material layer;forming a second material layer on the substrate and within openings defined by the spacer features; andremoving the spacer features.2. The method of claim 1 , wherein the forming of the second material layer includes:forming the second material layer by ...

TECHNIQUES FOR REDUCING TIP TO TIP SHORTING AND CRITICAL DIMENSION VARIATION DURING NANOSCALE PATTERNING

A method of forming surface features in a hardmask layer, including etching a first surface feature into the hardmask layer, the first surface feature having a first critical dimension, performing an ion implantation process on the first surface feature to make the first surface feature resistant to subsequent etching processes, etching a second surface feature into the hardmask layer adjacent the first surface feature, wherein the first critical dimension is preserved. 1. A method of forming surface features in a hardmask layer , comprising:etching a first surface feature into the hardmask layer, the first surface feature having a first critical dimension;performing an ion implantation process on the first surface feature to make the first surface feature resistant to subsequent etching processes; andetching a second surface feature into the hardmask layer adjacent the first surface feature, wherein the first critical dimension is preserved.2. The method of claim 1 , wherein the first surface feature and the second surface feature are trenches.3. The method of claim 1 , wherein the first critical dimension is a width of the first surface feature.4. The method of claim 1 , wherein etching the first surface feature into the hardmask layer comprises:performing a photolithography process using a first photoresist layer to etch a trench into a first planarization layer and first bottom antireflective coating (BARC) layer disposed on the hardmask layer; andperforming an ion etching process wherein an ion beam formed of reactive plasma ions is directed into the trench to extend the trench into the hardmask layer.5. The method of claim 4 , further comprising removing the first photoresist layer claim 4 , the first planarization layer claim 4 , and the first BARC layer from the hardmask layer.6. The method of claim 5 , further comprising applying a second BARC layer claim 5 , a second planarization layer claim 5 , and a second photoresist layer atop the hardmask layer.7. ...

Self aligned block masks for implantation control

Methods for doping a semiconductor layer include forming a first mask on a first region of a semiconductor layer. A second region of the semiconductor layer, that is not covered by the first mask, is doped. A second mask is formed on the second region of the semiconductor layer. The first mask is etched away. The first region of the semiconductor layer is doped.

Interconnect structure and manufacturing method for the same

The present disclosure provides an interconnect structure, including a first metal line, a conductive contact over the first metal line, including a first portion, a second portion over the first portion, wherein a bottom width of the second portion is greater than a top width of the first portion, and a third portion over the second portion, wherein a bottom width of the third portion is greater than a top width of the second portion, a sacrificial bilayer, including a first sacrificial layer, wherein a first portion of the first sacrificial layer is under a coverage of a vertical projection area of the first portion of the conductive contact, and a second sacrificial layer over the first sacrificial layer, and a dielectric layer over a top surface of the second sacrificial layer.

SELF-ALIGNED GATE CAP INCLUDING AN ETCH-STOP LAYER

According to embodiments of the present invention, a method of forming a self-aligned contact includes depositing an etch-stop liner on a surface of a gate cap and a contact region. A dielectric oxide layer is deposited onto the etch-stop layer. The dielectric oxide layer and the etch-stop liner are removed in a region above the contact region to form a removed region. A contact is deposited in the etched region. 1. A method of forming a self-aligned contact , the method comprising:depositing an etch-stop liner on a surface of a gate cap and on a contact region;depositing a dielectric oxide layer onto the etch-stop layer;removing the dielectric oxide layer in a region above the contact region;removing the etch-stop layer in the region above the contact region to form a removed region; anddepositing a contact in the etched region.2. The method of claim 1 , wherein depositing an etch-stop liner comprises chemical vapor deposition of the etch-stop liner.3. The method of claim 1 , wherein the etch-stop layer has a thickness of about 5 to about 20 nm.4. The method of claim 1 , wherein the etch-stop layer has a density of greater than or equal to about 2.5 g/cm.5. The method of claim 1 , wherein the etch-stop layer comprises an oxide claim 1 , a nitride claim 1 , an oxynitride claim 1 , a carbide claim 1 , an oxycarbide claim 1 , or a combination comprising at least one of the foregoing.6. The method of claim 1 , wherein the etch-stop layer comprises silicon nitride.7. The method of claim 1 , wherein depositing the dielectric oxide layer comprises chemical vapor deposition or spin coating.8. The method of claim 1 , wherein removing the dielectric oxide layer comprises dry etching the dielectric oxide layer.9. The method of claim 1 , wherein depositing the contact comprises first depositing a liner material and then depositing a conductive material.10. The method of claim 8 , wherein the liner material comprises a metal nitrate and wherein the conductive material comprises ...

METHOD FOR PATTERNING SEMICONDUCTOR DEVICE USING MASKING LAYER

A semiconductor device and method includes a method. The method includes patterning a plurality of first mandrels over a first mask layer. The method further includes forming a first spacer layer on sidewalls and tops of the first mandrels. The method further includes removing horizontal portions of the first spacer layer, with remaining vertical portions of the first spacer layer forming first spacers. The method further includes, after removing the horizontal portions of the first spacer layer, depositing a reverse material between the first spacers. The method further includes patterning the first mask layer using the first spacers and the reverse material in combination as a first etching mask. 1. A method comprising:forming a first mask layer on a substrate;patterning first spacers over the first mask layer;forming an anti-reflective layer over the first spacers;forming an etch stop layer over the anti-reflective layer;forming a second mask layer over the etch stop layer;patterning first openings in the second mask layer, each of the first openings overlying respective pairs of the first spacers;after patterning the first openings, patterning second openings in the second mask layer, each of the second openings overlying respective pairs of the first spacers;extending the first and second openings through the anti-reflective layer and between the respective pairs of the first spacers;forming a reverse material over the second mask layer and in the first and second openings;removing the anti-reflective layer, the etch stop layer, the second mask layer, and portions of the reverse material; andpatterning the first mask layer using the first spacers and remaining portions of the reverse material as a first etching mask.2. The method of claim 1 , wherein the patterning the first spacers comprises:patterning first mandrels over the first mask layer;forming a first spacer layer on sidewalls and tops of the first mandrels;removing horizontal portions of the first ...

DIRECTIONAL DEPOSITION IN ETCH CHAMBER

Methods for forming a vertical growth mask for use in etching applications are described herein. Disclosed embodiments include introducing a tungsten-containing deposition precursor and one or more carrier gases while igniting a plasma to deposit tungsten selectively on field regions of positive features of a patterned etch mask without substantial deposition on sidewalls of the positive features or on an exposed surface of a target layer underlying the patterned etch mask. 1. A method comprising:providing a semiconductor substrate having a patterned etch mask over a target layer, the patterned etch mask comprising spaced apart positive features, each spaced apart positive feature having a field region and sidewalls; anddepositing a vertical growth mask selectively on the field region of the spaced apart positive features relative to the target layer.2. The method of claim 1 , wherein the vertical growth mask includes at least one feature; and wherein critical dimension of the at least one feature of the vertical growth mask is substantially the same as critical dimension of a corresponding spaced apart positive feature of the patterned etch mask.3. The method of claim 1 , further comprising etching the target layer using both the patterned etch mask and the vertical growth mask as a mask.4. The method of claim 3 , wherein the depositing of the vertical growth mask and the etching of the target layer are performed simultaneously.5. The method of claim 1 , wherein size of spaces between spaced apart positive features of the vertical growth mask are substantially the same as size of spaces between the spaced apart positive features of the patterned etch mask.6. A method comprising:providing a semiconductor substrate having a patterned etch mask over a target layer, the patterned etch mask having spaced apart positive features, each spaced apart positive feature having a first critical dimension and a field region and sidewalls, anddepositing a mask on the field region ...

Method of Forming a Flexible Semiconductor Layer and Devices on a Flexible Carrier

A method for fabricating a semiconductor device comprises providing a preformed spalled structure comprising a stressor layer stack on a first surface of a semiconductor substrate; forming an interfacial release layer on an exposed second surface of the semiconductor substrate; adhesively bonding the interfacial release layer to a rigid handle substrate using an epoxy; removing at least a portion of the stressor layer stack from the first surface of the semiconductor substrate; processing the semiconductor substrate; and removing the semiconductor substrate from the interfacial release layer to impart flexibility to the semiconductor substrate. 1. A method for fabricating a semiconductor device , comprising:providing a structure comprising a stressor layer stack on a first surface of a semiconductor substrate;forming an interfacial release layer on an exposed second surface of the semiconductor substrate;adhesively bonding the interfacial release layer to a rigid handle substrate using an epoxy;removing at least a portion of the stressor layer stack from the first surface of the semiconductor substrate;processing the semiconductor substrate by isolating cells in the semiconductor substrate by applying a hardmask to the semiconductor substrate and etching exposed semiconductor substrate down to the epoxy; andremoving the hardmask and applying a pressure-sensitive tape to the semiconductor substrate to remove the semiconductor substrate from the interfacial release layer;2. The method of claim 1 , wherein providing a structure comprising a stressor layer stack comprises forming the stressor layer stack bydepositing an adhesion layer on the semiconductor substrate,depositing a seed layer on the adhesion layer,depositing a stressor layer on the seed layer, andapplying a releasable tape to the stressor layer.3. The method of claim 2 , wherein depositing an adhesion layer on the semiconductor substrate comprises depositing titanium on the semiconductor substrate.4. The ...

Method of Forming a Flexible Semiconductor Layer and Devices on a Flexible Carrier

A method for fabricating a semiconductor device comprises providing a preformed spalled structure comprising a stressor layer stack on a first surface of a semiconductor substrate; forming an interfacial release layer on an exposed second surface of the semiconductor substrate; adhesively bonding the interfacial release layer to a rigid handle substrate using an epoxy; removing at least a portion of the stressor layer stack from the first surface of the semiconductor substrate; processing the semiconductor substrate; and removing the semiconductor substrate from the interfacial release layer to impart flexibility to the semiconductor substrate. 1. A method for fabricating a semiconductor device , comprising:providing a structure comprising a stressor layer stack on a first surface of a semiconductor substrate;forming an interfacial release layer on a second exposed surface of the semiconductor substrate;bonding the interfacial release layer to a rigid handle substrate using an epoxy adhesive;removing at least a portion of the stressor layer stack from the semiconductor substrate;processing the semiconductor substrate;forming a layer comprising a finger/bus metal and an anti-reflective coating on the semiconductor substrate;applying a sacrificial mask to the layer comprising the finger/bus metal and the anti-reflective coating;patterning the layer comprising the finger/bus metal and the anti-reflective coating;removing the sacrificial mask; andremoving the semiconductor substrate from the interfacial release layer using a tape superstrate to impart flexibility to the semiconductor substrate.2. The method of claim 1 , wherein processing the semiconductor substrate comprises one or more of patterning the semiconductor substrate claim 1 , thinning the semiconductor substrate claim 1 , thermally treating the semiconductor substrate claim 1 , and depositing a film on the semiconductor substrate.3. The method of claim 1 , further comprising etching portions of the layer ...

Photoresist Layer and Method

A system and method for middle layers is provided. In an embodiment the middle layer comprises a floating component in order to form a floating region along a top surface of the middle layer after the middle layer has dispersed. The floating component may be a polymer with a floating group incorporated into the polymer. The floating group may comprise a fluorine atom.

METHOD OF MAKING A SEMICONDUCTOR DEVICE USING MULTIPLE LAYER SETS

A method of making a semiconductor device includes forming an intermediate semiconductor device. The intermediate device includes a substrate; and a dielectric layer over the substrate. The intermediate device includes a first layer set, including a silicon-rich photoresist material, over the dielectric layer. The intermediate device includes a second layer set, including a carbon-rich organic material layer, over the first layer set. The method further includes etching the second layer set to form a tapered opening in the second layer set. The method further includes etching the first layer set to form an opening in the first layer set, wherein etching the first layer set comprises removing the carbon-rich organic material layer. The method further includes etching the dielectric layer using the first layer set as a mask to form an opening in the dielectric layer, wherein etching the dielectric layer comprises reducing a thickness of the first layer set. 1. A method of making a semiconductor device , the method comprising: a substrate;', 'a dielectric layer over the substrate;', 'a first layer set over the dielectric layer, wherein the first layer set comprises a silicon-rich photoresist material;', 'a second layer set over the first layer set, wherein the second layer set comprises a plurality of layers including a carbon-rich organic material layer; and, 'forming an intermediate semiconductor device, the intermediate semiconductor device comprisingetching the second layer set to form a tapered opening in the second layer set, the tapered opening having sidewalls at an angle with respect to a top surface of the dielectric layer;etching the first layer set to form an opening in the first layer set, wherein etching the first layer set comprises removing the carbon-rich organic material layer; andetching the dielectric layer using the first layer set as a mask to form an opening in the dielectric layer, wherein etching the dielectric layer comprises reducing a ...

METHOD OF FORMING OVERLAY MARK STRUCTURE

A method of forming an overlay mark structure includes the following steps. An insulation layer is formed on a substrate. A first overlay mark is formed in the insulation layer. A metal layer is formed on the substrate. The metal layer covers the insulation layer and the first overlay mark. The metal layer on the first overlay mark is removed. A top surface of the first overlay mark is lower than a top surface of the insulation layer after the step of removing the metal layer on the first overlay mark. A second overlay mark is formed on the metal layer. In the method of forming the overlay mark structure, the first overlay mark may not be covered by the metal layer for avoiding influences on related measurements, and the second overlay mark may be formed on the metal layer for avoiding related defects generated by the height difference. 1. A method of forming an overlay mark structure , comprising:forming an insulation layer on a substrate;forming a first overlay mark in the insulation layer;forming a metal layer on the substrate, wherein the metal layer covers the insulation layer and the first overlay mark;removing the metal layer on the first overlay mark, wherein a top surface of the first overlay mark is lower than a top surface of the insulation layer after the step of removing the metal layer on the first overlay mark; andforming a second overlay mark on the metal layer.2. The method of forming the overlay mark structure according to claim 1 , wherein a projection pattern of the first overlay mark in a thickness direction of the substrate surrounds at least a part of a projection pattern of the second overlay mark in the thickness direction of the substrate.3. The method of forming the overlay mark structure according to claim 1 , wherein a main region and an overlay mark region are defined on the substrate claim 1 , and the first overlay mark and the second overlay mark are formed on the overlay mark region.4. The method of forming the overlay mark structure ...

METHOD TO IMPROVE FILL-IN WINDOW FOR EMBEDDED MEMORY

Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A plurality of memory cell structures is disposed on the memory region. A plurality of logic devices is disposed on the logic region. A sidewall spacer is disposed along a sidewall surface of the logic devices, but not disposed along a sidewall surface of the memory cell structures. Thus, the inter-layer dielectric (ILD) fill-in window between adjacent memory cell structures is enlarged, compared to the approaches where the sidewall spacer is concurrently formed in both memory region and the logic region. Thereby, voids formation would be reduced or eliminated, and device quality would be improved. 1. An integrated circuit (IC) comprising:a memory region and a logic region integrated in a substrate;a plurality of memory cell structures disposed on the memory region, wherein a memory cell structure of the plurality of memory cell structures comprises a pair of control gate electrodes respectively disposed over the substrate and a pair of select gate electrodes disposed on opposite sides of the pair of control gate electrodes;a plurality of logic devices disposed on the logic region, wherein a logic device of the plurality of logic devices comprises a logic gate electrode separated from the substrate by a logic gate dielectric;a sidewall spacer disposed along a sidewall surface of the logic gate electrode; anda contact etch stop layer (CESL) disposed along a top surface of the substrate, extending upwardly along sidewall surfaces of the pair of select gate electrodes within the memory region, and extending upwardly along a sidewall surface of the sidewall spacer with within the logic region;wherein the contact etch stop layer (CESL) is in direct contact with the sidewall surfaces of the pair of select gate electrodes and separated from the sidewall surface of the logic ...

Polymer for Preparing Resist Underlayer Film, Resist Underlayer Film Composition Containing the Polymer and Method for Manufacturing Semiconductor Device Using the Composition

Provided are a polymer used for a manufacturing process of a semiconductor and a display, a resist underlayer film composition containing the polymer for a manufacturing process of a semiconductor and a display, and a method for manufacturing semiconductor device using the composition, and more specifically, the polymer of the present disclosure simultaneously has optimized etching selectivity, planarization characteristic, and excellent thermal resistance, such that the resist underlayer film composition containing the polymer is usable as a hard mask for a multilayer semiconductor lithography process. 3. The polymer for preparing a resist underlayer film of claim 1 , wherein the polymer has a weight average molecular weight of 500 or more.5. The polymer for preparing a resist underlayer film of claim 2 , wherein Arand Arare each independently phenylene claim 2 , naphthylene claim 2 , biphenylene claim 2 , fluorenylene claim 2 , triphenylene claim 2 , anthrylene claim 2 , pyrenylene claim 2 , chrysenylene or naphthacenylene; Aris trivalent phenylene claim 2 , naphthylene claim 2 , biphenylene claim 2 , fluorenylene claim 2 , triphenylene claim 2 , anthrylene claim 2 , pyrenylene claim 2 , chrysenylene or naphthacenylene; Aris phenyl claim 2 , naphthyl claim 2 , biphenyl claim 2 , fluorenyl claim 2 , triphenyl claim 2 , anthryl claim 2 , pyrenyl claim 2 , chrysenyl or naphthacenyl; R is hydrogen claim 2 , methyl claim 2 , ethyl claim 2 , propyl claim 2 , butyl claim 2 , pentyl claim 2 , hexyl claim 2 , heptyl claim 2 , octyl claim 2 , cyclopropyl claim 2 , cyclobutyl claim 2 , cyclopentyl claim 2 , cyclohexyl claim 2 , cycloheptyl claim 2 , cyclooctyl claim 2 , phenyl claim 2 , naphthyl claim 2 , biphenyl claim 2 , terphenyl claim 2 , fluorenyl claim 2 , phenanthrenyl claim 2 , anthracenyl claim 2 , triphenylenyl claim 2 , pyrenyl claim 2 , chrysenyl claim 2 , naphthacenyl claim 2 , benzyl claim 2 , naphthylmethyl claim 2 , anthrylmethyl claim 2 , pyrenylmethyl ...

Polymer for Preparing Resist Underlayer Film, Resist Underlayer Film Composition Containing the Polymer and Method for Manufacturing Semiconductor Device Using the Composition

Provided are a polymer used for a manufacturing process of a semiconductor and a display, a resist underlayer film composition containing the polymer for a manufacturing process of a semiconductor and a display, and a method for manufacturing semiconductor device using the composition, and more specifically, the polymer of the present disclosure simultaneously has optimized etching selectivity and planarization characteristics, such that the resist underlayer film composition containing the polymer is usable as a hard mask for a multilayer semiconductor lithography process. 3. The polymer for preparing a resist underlayer film of claim 1 , wherein the polymer has a weight average molecular weight of 500 to 50 claim 1 ,000.5. The polymer for preparing a resist underlayer film of claim 2 , wherein Arand Arare each independently phenylene claim 2 , naphthylene claim 2 , biphenylene claim 2 , fluorenylene claim 2 , triphenylene claim 2 , anthrylene claim 2 , pyrenylene claim 2 , chrysenylene or naphthacenylene; Aris a trivalent phenylene claim 2 , naphthylene claim 2 , biphenylene claim 2 , fluorenylene claim 2 , triphenylene claim 2 , anthrylene claim 2 , pyrenylene claim 2 , chrysenylene or naphthacenylene; Aris phenyl claim 2 , naphthyl claim 2 , biphenyl claim 2 , fluorenyl claim 2 , triphenyl claim 2 , anthryl claim 2 , pyrenyl claim 2 , chrysenyl or naphthacenyl; R is hydrogen claim 2 , methyl claim 2 , ethyl claim 2 , propyl claim 2 , butyl claim 2 , pentyl claim 2 , hexyl claim 2 , heptyl claim 2 , octyl claim 2 , cyclopropyl claim 2 , cyclobutyl claim 2 , cyclopentyl claim 2 , cyclohexyl claim 2 , cycloheptyl claim 2 , cyclooctyl claim 2 , phenyl claim 2 , naphthyl claim 2 , biphenyl claim 2 , terphenyl claim 2 , fluorenyl claim 2 , phenanthrenyl claim 2 , anthracenyl claim 2 , triphenylenyl claim 2 , pyrenyl claim 2 , chrysenyl claim 2 , naphthacenyl claim 2 , benzyl claim 2 , naphthylmethyl claim 2 , anthrylmethyl claim 2 , pyrenylmethyl claim 2 , ...

HARDMASK COMPOSITION AND METHOD OF FORMING PATTERNS USING THE HARDMASK COMPOSITION

A hardmask composition includes a polymer including a moiety represented by the following Chemical Formula 1 and a solvent.

Compound for forming organic film, and organic film composition using the same, process for forming organic film, and patterning process

The invention provides a compound for forming an organic film having a partial structure represented by the following formula (vii-2), wherein R 1 represents a linear, branched or cyclic monovalent hydrocarbon group having 1 to 20 carbon atoms, and a methylene group constituting R 1 may be substituted by an oxygen atom; a+b is 1, 2 or 3; c and d are each independently 0, 1 or 2; x represents 0 or 1, when x=0, then a=c=0; L 7 represents a linear, branched or cyclic divalent organic group having 1 to 20 carbon atoms, L 8′ represents the partial structure represented by the following formula (i), 0≦o<1, 0<p≦1 and o+p=1, wherein the ring structures Ar3 represent a substituted or unsubstituted benzene ring or naphthalene ring; R 0 represents a hydrogen atom or a linear, branched or cyclic monovalent organic group having 1 to 30 carbon atoms; and L 0 represents a divalent organic group. There can be provided an organic film composition for forming an organic film having high dry etching resistance as well as advanced filling/planarizing characteristics.

HARDMASK COMPOSITION, HARDMASK LAYER AND METHOD OF FORMING PATTERNS

A hardmask composition, a hardmask layer, and a method of forming patterns, the composition including a solvent; and a polymer that includes a substituted biphenylene structural unit, wherein one phenylene of the biphenylene of the substituted biphenylene structural unit is substituted with at least one of a hydroxy-substituted C6 to C30 aryl group, and a hydroxy-substituted C3 to C30 heteroaryl group. 1. A hardmask composition , comprising:a solvent; anda polymer that includes a substituted biphenylene structural unit,wherein one phenylene of the biphenylene of the substituted biphenylene structural unit is substituted with at least one of a hydroxy-substituted C6 to C30 aryl group, and a hydroxy-substituted C3 to C30 heteroaryl group.2. The hardmask composition as claimed in claim 1 , wherein the one phenylene is substituted with at least one of a hydroxyphenyl group claim 1 , a hydroxynaphthyl group claim 1 , a hydroxybiphenyl group claim 1 , a hydroxydiphenylfluorenyl group claim 1 , a hydroxydinaphthylfluorenyl group claim 1 , a hydroxyanthracenyl group claim 1 , a hydroxyfluoranthenyl group claim 1 , a hydroxyacenaphthylenyl group claim 1 , a hydroxyacenaphthenyl group claim 1 , a hydroxyphenanthrenyl group claim 1 , a hydroxybenzophenanthrenyl group claim 1 , a hydroxypyrenyl group claim 1 , a hydroxytriphenylenyl group claim 1 , a hydroxychrysenyl group claim 1 , a hydroxytetracenyl group claim 1 , a hydroxybenzofluoranthenyl group claim 1 , a hydroxyperlenyl group claim 1 , a hydroxybenzopyrenyl group claim 1 , a hydroxynaphthoanthracenyl group claim 1 , a hydroxypentacenyl group claim 1 , a hydroxybenzoperlenyl group claim 1 , a hydroxydibenzopyrenyl group claim 1 , a hydroxycoronenyl group claim 1 , a hydroxypyridinyl group claim 1 , a hydroxypyrimidinyl group claim 1 , a hydroxy triazinyl group claim 1 , a hydroxypyrrolyl group claim 1 , a hydroxy imidazolyl group claim 1 , a hydroxypyrazolyl group claim 1 , a hydroxyindolo group claim 1 , a ...

METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A BARRIER AND ANTIREFLECTIVE COATING (BARC) LAYER

A method of forming a semiconductor device includes forming a dielectric layer over a substrate. The method includes forming a layer set over the dielectric layer, wherein the layer set comprises a plurality of layers. The method further includes forming a bottom antireflective coating (BARC) layer over the layer set. The method further includes etching the layer set to form a tapered opening in the layer set, wherein etching the layer set comprises etching at least one layer comprising a silicon-rich photoresist material layer and a second material layer different from the silicon-rich photoresist material, and the tapered opening has sidewalls at an angle with respect to a top surface of the dielectric layer. The method further includes etching the dielectric layer using the layer set as a mask to form an opening in the dielectric layer, wherein etching the dielectric layer comprises reducing a thickness of the layer set.

RESIST UNDERLAYER FILM COMPOSTION, PATTERNING PROCESS, AND COMPOUND

The present invention provides a resist underlayer film composition for lithography, containing a compound having an indenofluorene structure. This resist underlayer film composition is excellent in filling property, generates little outgas, and has high heat resistance. 1. A resist underlayer film composition for lithography , comprising a compound having an indenofluorene structure.5. The resist underlayer film composition according to claim 1 , further comprising an organic solvent.6. The resist underlayer film composition according to claim 2 , further comprising an organic solvent.7. The resist underlayer film composition according to claim 3 , further comprising an organic solvent.8. The resist underlayer film composition according to claim 1 , further comprising an acid generator and/or a crosslinking agent.9. The resist underlayer film composition according to claim 2 , further comprising an acid generator and/or a crosslinking agent.10. The resist underlayer film composition according to claim 3 , further comprising an acid generator and/or a crosslinking agent.11. A patterning process for forming a pattern in a substrate by lithography claim 3 , comprising the steps of:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, '(A1) forming a resist underlayer film on the substrate from the resist underlayer film composition according to ;'}(A2) forming a photoresist film on the resist underlayer film;(A3) forming a photoresist pattern by subjecting the photoresist film to exposure and development;(A4) transferring the pattern to the resist underlayer film by dry etching using the photoresist pattern as a mask; and(A5) processing the substrate by using the resist underlayer film having the transferred pattern as a mask.12. A patterning process for forming a pattern in a substrate by lithography claim 3 , comprising the steps of:{'claim-ref': {'@idref': 'CLM-00002', 'claim 2'}, '(A1) forming a resist underlayer film on the substrate from the resist underlayer film ...

METHOD FOR CLEANING VIA OF INTERCONNECT STRUCTURE OF SEMICONDUCTOR DEVICE STRUCTURE

A method for forming the semiconductor device structure is provided. The method includes forming a metal layer in a first dielectric layer over a substrate and forming an etch stop layer over the metal layer. The etch stop layer is made of metal-containing material. The method also includes forming a second dielectric layer over the etch stop layer and removing a portion of the second dielectric layer to expose the etch stop layer and to form a via by an etching process. The method further includes performing a plasma cleaning process on the via and the second dielectric layer, and the plasma cleaning process is performed by using a plasma including nitrogen gas (N) and hydrogen gas (H). 1. A method for forming a semiconductor device structure , comprising:forming a metal layer in a first dielectric layer over a substrate;forming an etch stop layer over the metal layer, wherein the etch stop layer is made of metal-containing material;forming a second dielectric layer over the etch stop layer removing a portion of the second dielectric layer to expose the etch stop layer and to form a via by an etching process; and{'sub': 2', '2, 'performing a plasma cleaning process on the via and the second dielectric layer, wherein the plasma cleaning process is performed by using a plasma comprising nitrogen gas (N) and hydrogen gas (H).'}2. The method for forming the semiconductor device structure as claimed in claim 1 , wherein a ratio of the flow rate of nitrogen gas (N) to the flow rate of hydrogen gas (H) is in a range from about 2/1 to about 4/1.3. The method for forming the semiconductor device structure as claimed in claim 1 , further comprising:after the plasma cleaning process, performing a wet cleaning process on the second dielectric layer.4. The method for forming the semiconductor device structure as claimed in claim 1 , wherein the etching process is performed by using an etch gas comprising fluorine-containing gas.5. The method for forming the semiconductor device ...

Composite Hard Mask Etching Profile for Preventing Pattern Collapse in High-Aspect-Ratio Trenches

High-aspect ratio trenches in integrated circuits are fabricated of composite materials and with trench boundaries having pencil-like etching profiles. The fabrication methods reduce surface tension between trench boundaries and fluids applied during manufacture, thereby avoiding pattern bending, bowing, and collapse. The method, further, facilitates fill-in of trenches with suitable selected materials.

Plasma Pre-Treatment Method To Improve Etch Selectivity And Defectivity Margin

Improved methods are provided for transferring a photoresist pattern onto one or more underlying layers. In the disclosed embodiments, etch selectivity between a photoresist layer and one or more underlying layers is improved by pre-treating the underlying layer(s) with a plasma before the photoresist layer is deposited and patterned to form a photoresist pattern. The plasma modifies the underlying layer(s) by implanting ions into the underlying layer(s) to form a modified layer. When the modified layer is subsequently etched to transfer the photoresist pattern onto the modified layer, the presence of ions within the modified layer increases the etch rate of the modified layer, compared to the etch rate that the underlying layer(s) would have exhibited without plasma pre-treatment. The increased etch rate of the modified layer improves etch selectivity between the photoresist layer and the modified layer and mitigates defects during the photoresist pattern transfer process. 1. A method for processing a substrate , comprising:providing the substrate with at least one underlying layer;pre-treating the at least one underlying layer with a plasma to modify the at least one underlying layer, wherein ions from the plasma are implanted into the at least one underlying layer to form a modified layer;providing a photoresist layer overlying the modified layer;using a lithography technique to form a photoresist pattern in the photoresist layer; andremoving portions of the modified layer exposed by the photoresist pattern to transfer the photoresist pattern onto the modified layer,wherein the pre-treating the underlying layer with the plasma increases a rate at which the modified layer is removed compared to without pre-treatment.2. The method of claim 1 , wherein the plasma is generated from one or more processing gases selected from a group comprising hydrogen (H) claim 1 , helium (He) claim 1 , argon (Ar) claim 1 , nitrogen (N) claim 1 , borane (BH) claim 1 , and phosphine ( ...

Wafer element with an adjusted print resolution assist feature

A wafer element fabrication method is provided. The wafer element fabrication method includes forming a device element on a substrate such that the device element includes an upper surface and a sidewall extending from the upper surface to the substrate. The wafer element fabrication method further includes forming an adjusted print resolution assist feature (APRAF) on the substrate such that the APRAF is smaller than the device element in at least one dimension. In addition, the wafer element fabrication method includes depositing surrounding material, which is different from materials of the APRAF, to surround the APRAF and to lie on the upper surface in abutment with the sidewall of the device element.

NEUTRAL HARD MASK AND ITS APPLICATION TO GRAPHOEPITAXY-BASED DIRECTED SELF-ASSEMBLY (DSA) PATTERNING

A material stack is formed on the surface of a semiconductor substrate. The top layer of the material stack comprises at least an organic planarization layer. A neutral hard mask layer is formed on the top of the organic planarization layer. The neutral hard mask layer is neutral to the block copolymers used for direct self-assembly. A plurality of template etch stacks are then formed on top of the neutral hard mask layer. After formation of the template etch stacks, neutrality recovery is performed on the neutral hard mask layer and the top portions of the template etch stacks, the vertical sidewalls of the template etch stacks being substantially unaffected by the neutrality recovery. A template for DSA is thus obtained. 1. A method of forming a template for the directed self-assembly (DSA) of block copolymers (BCPs) comprising:forming a material stack on a surface of a semiconductor substrate, the top surface of the material stack comprising an organic planarization layer; andforming a neutral hard mask layer on top of the organic planarization layer, the neutral hard mask layer being neutral to the BCPs;forming a plurality of template etch stacks on top of the neutral hard mask layer;performing a neutrality recovery step on the neutral hard mask layer and on the top portions of the plurality of template etch stacks to obtain a template for DSA.2. The method of wherein the neutral hard mask layer is comprised of a nitrogen-doped silicon carbide claim 1 , a nitrogen-doped hydrogenated silicon carbide claim 1 , or combinations thereof.3. The method of wherein the BCPs comprise polystyrene and poly(methylmethacrylate).4. The method of wherein the organic planarization layer comprises spun on carbon.5. The method of wherein the neutrality recovery step comprises forming a recovery neutral hard mask coating on the neutral hard mask layer and the top portions of the plurality of template etch stacks claim 1 , wherein the recovery neutral hard mask can comprise the same ...

METHOD FOR ESTABLISHING MAPPING RELATION IN STI ETCH AND CONTROLLING CRITICAL DIMENSION OF STI

The present invention provides a method for controlling a critical dimension of shallow trench isolations in a STI etch process, comprises the following steps: before the STI etch process, pre-establishing a mapping relation between a post-etch and pre-etch critical dimension difference of a BARC layer and a thickness of the BARC layer; and during the STI etch process after coating the BARC layer, measuring the thickness of the BARC layer and determining a trimming time for a hard mask layer according to a critical dimension difference corresponding to the measured thickness in the mapping relation and a critical dimension of a photoresist pattern, then performing a trimming process for the hard mask layer lasting the trimming time to make a critical dimension of the hard mask layer equal to a required critical dimension of an active area, and etching a substrate to form shallow trenches with a predetermined critical dimension. 1. A method for controlling a critical dimension of shallow trench isolations in a STI etch process , wherein the STI etch process comprises the steps of: forming a hard mask layer on a substrate in which active areas are formed , forming a bottom anti-reflective coating layer on the hard mask layer by spin coating , coating a photoresist on the bottom anti-reflective coating layer and patterning to form a photoresist pattern covering the active areas with a target critical dimension , etching the bottom anti-reflective coating layer and the hard mask layer by using the photoresist pattern as a mask according to an etch process recipe and then removing the photoresist pattern and the bottom anti-reflective coating layer , performing a trimming process to the hard mask layer to form a hard mask pattern having a required post-etch critical dimension which is equal to a critical dimension of the active areas , and etching the substrate by using the hard mask pattern as a mask to form the shallow trenches; the method comprises following two steps ...

COMPOUND FOR FORMING ORGANIC FILM, AND ORGANIC FILM COMPOSITION USING THE SAME, PROCESS FOR FORMING ORGANIC FILM, AND PATTERNING PROCESS

The invention provides a compound for forming an organic film having a partial structure represented by the following formula (ii), 10. The organic film composition according to claim 9 , wherein the composition contains (D) a resin containing an aromatic ring which is different from the polymers (C-1) to (C-4).11. The organic film composition according to claim 10 , wherein (D) the resin containing an aromatic ring contains a naphthalene ring.14. The organic film composition according to claim 9 , wherein the composition further comprises at least one of (E) a compound containing a phenolic hydroxyl group claim 9 , (F) an acid generator claim 9 , (G) a cross-linking agent claim 9 , (H) a surfactant and (I) an organic solvent.15. The organic film composition according to claim 9 , wherein it is used as a resist underlayer film composition or a planarizing composition for manufacturing a semiconductor apparatus.16. A process for forming an organic film which acts as a resist underlayer film or a planarizing film for manufacturing a semiconductor apparatus of a multilayer resist film used in lithography claim 9 , which comprises coating the organic film composition according to on a substrate to be processed claim 9 , and subjecting the composition to heat treatment at a temperature of 100° C. or higher and 600° C. or lower for 10 seconds to 600 seconds to form a cured film.17. A process for forming an organic film which acts as a resist underlayer film or a planarizing film for manufacturing a semiconductor apparatus of a multilayer resist film used in lithography claim 15 , which comprises coating the organic film composition according to on a substrate to be processed claim 15 , and subjecting the composition to heat treatment at a temperature of 100° C. or higher and 600° C. or lower for 10 seconds to 600 seconds to form a cured film.18. A process for forming an organic film which acts as a resist underlayer film or a planarizing film for manufacturing a ...

COMPOSITION FOR FORMING RESIST UNDERLAYER FILM AND METHOD FOR FORMING RESIST PATTERN USING SAME

A method includes applying a composition for forming a resist underlayer film to a substrate having a recess in a surface, and baking the composition for forming a resist underlayer film to form a resist underlayer film for filling at least the recess. The composition for forming a resist underlayer film has a copolymer having a structural unit of following formula (1), a cross-linkable compound, a cross-linking catalyst, and a solvent: 2. The method according to claim 1 , further comprising a step of forming a photoresist pattern on the resist underlayer film.3. The method according to claim 1 , wherein the substrate is a semiconductor substrate having a trench having a width of 0.01 μm to 0.10 μm and an aspect ratio of 5 to 10. The present application is a divisional application of U.S. application Ser. No. 16/081,668 filed Aug. 31, 2018, which in turn is a U.S. national stage application of PCT/JP2017/006882 filed Feb. 23, 2017. Each of the prior applications is incorporated herein by reference in its entirety.The present invention relates to a composition for forming a resist underlayer film that has a high dry etching rate, functions as an anti-reflective coating during exposure, and fills a recess having a narrow space and a high aspect ratio.For example, formation of a fine resist pattern on a substrate by a photolithography technique including an exposure step using a KrF excimer laser or an ArF excimer laser as a light source has been known in manufacture of a semiconductor element. Light of the KrF excimer laser or ArF excimer laser incident to a resist film before formation of a resist pattern (incident light) is reflected on a surface of the substrate to generate a standing wave in the resist film. This standing wave is known to prevent formation of a resist pattern having a desired shape. For suppression of generation of the standing wave, formation of an anti-reflective coating that absorbs incident light between the resist film and the substrate is ...

ETCHING METHOD

A method for selectively etching a first region made of silicon oxide with respect to a second region made of silicon nitride or another material different from that of the first region. The method includes a first step for generating, in a processing container housing a workpiece to be treated, a plasma of a treatment gas including a fluorocarbon gas, an oxygen-containing gas, and an inert gas, and forming a deposit including fluorocarbon on the object to be treated; and a second step for etching the first region with radicals of the fluorocarbon included in the deposit. The first step and the second step are executed repeatedly. 12-. (canceled)3. An etching method comprising:(a) providing a workpiece including a first region and a second region, in which the first region is made of silicon oxide and the second region is made of silicon nitride, in which the second region defines a recess and the first region fills and covers the second region, and in which a mask is located above the first region and the mask has an opening with an opening width larger than an opening width of the recess; and (i) a first step of generating plasma from a processing gas containing a fluorocarbon gas, an oxygen-containing gas, and an inert gas in a processing container accommodating the workpiece to form a deposit containing fluorocarbon on the workpiece;', '(ii) a second step of etching the first region with fluorocarbon radicals contained in the deposit; and', '(iii) wherein the first step and the second step are repeatedly executed., '(b) selectively etching the first region with respect to the second region with a plurality of steps comprising4. The method of claim 3 , wherein the etching of the second step is performed with a substantially oxygen-free processing gas.5. A method comprising:(a) providing a workpiece including a first region and a second region, in which the first region is made of a silicon-containing material and the second region is made of a material other than ...

Method of negative tone development using a copolymer multilayer electrolyte and articles made therefrom

Disclosed herein is a multi-layered article, comprising a substrate; and two or more layers disposed over the substrate, wherein each said layer comprises a block copolymer comprising a first block and a second block, wherein the first block comprises a repeat unit containing a hydrogen acceptor or a hydrogen donor, and the second block comprises a repeat unit containing a hydrogen donor when the repeat unit of the first block contains a hydrogen acceptor, or a hydrogen acceptor when the repeat unit of the first block contains a hydrogen donor; wherein the first block of an innermost of said two or more layers is bonded to the substrate, and the first block of each layer disposed over the innermost layer is bonded to the second block of a respective underlying layer; and wherein the hydrogen donor or hydrogen acceptor of the second block of an outermost said two or more layers is blocked.

INTERCONNECTION STRUCTURE

An interconnection structure fabrication method is provided. The method includes providing a substrate; forming a conductive film with a first thickness and having a first lattice structure and a first grain size, wherein the first thickness is greater than the first grain size; and performing an annealing process to change the first lattice structure of the conductive film to a second lattice structure and to change the first grain size to a second grain size. The second grain size is greater than the first grain size, and the first thickness is greater than or equal to the second grain size. The method also includes etching portion of the conductive film to form at least one conductive layer; etching portion of the conductive layer to form at least one trench having a depth smaller than the first thickness in the conductive layer to form an electrical interconnection wire and conductive vias; and forming a dielectric layer covering the substrate, sidewalls of the conductive layer, and the trench. 118.-. (canceled)19. An interconnection structure , comprising:a substrate including a plurality of conductive structures; each conductive via has a lateral dimension smaller than a grain size of the conductive layer, and', 'each electrical interconnection wire is electrically connected to at least one conductive structure in the substrate; and, 'a conductive layer including a plurality of electrical interconnection wires on the substrate, and conductive vias on each electrical interconnection wire, whereina dielectric layer on the substrate between adjacent electrical interconnection wires and on each electrical interconnection wire to separate conductive vias.20. The interconnection structure according to claim 19 , wherein:the substrate includes a first dielectric layer on a surface of a semiconductor substrate,the plurality of conductive structures are formed in the first dielectric layer, andthe plurality of conductive structures have a top surface coplanar with the ...

METHODS FOR FABRICATING INTEGRATED CIRCUITS USING DIRECTED SELF-ASSEMBLY CHEMOEPITAXY

Methods for directed self-assembly (DSA) using chemoepitaxy in the design and fabrication of integrated circuits are disclosed herein. An exemplary method includes forming an A or B-block attracting layer over a base semiconductor layer, forming a trench in the A or B-block attracting layer to expose a portion of the base semiconductor layer, and forming a neutral brush or mat or SAMs layer coating within the trench and over the base semiconductor layer. The method further includes forming a block copolymer layer over the neutral layer coating and over the A or B-block attracting layer and annealing the block copolymer layer to form a plurality of vertically-oriented, cylindrical structures within the block copolymer layer. 1. A method for directed self-assembly in the fabrication of integrated circuits comprising:forming an A or B-block attracting layer over a base semiconductor layer;forming a trench in the A or B-block attracting layer to expose a portion of the base semiconductor layer;forming a neutral brush or mat or SAMs coating within the trench and over the base semiconductor layer;forming a block copolymer layer over the neutral surface coating and over the A or B-block attracting layer; andannealing the block copolymer layer to form a directed self-assembly nano-pattern within the block copolymer layer.2. The method of claim 1 , wherein forming the A or B-block attracting layer over the base semiconductor layer comprises forming the A or B-block attracting layer over a base semiconductor layer comprising a semiconductor substrate.3. The method of claim 2 , wherein forming the A or B-block attracting layer over the base semiconductor layer comprises forming the A or B-block attracting layer over a base semiconductor layer comprising an organic planarization layer.4. The method of claim 3 , wherein forming the A or B-block attracting layer over the base semiconductor layer comprises forming the A or B-block attracting layer over a base semiconductor layer ...

High Endurance Non-Volatile Memory Cell

The present disclosure relates to a non-volatile memory cell structure, and an associated method. A non-volatile memory cell includes two transistors spaced apart from one another with floating gates connected together by a floating gate bridge. During the operation, the non-volatile memory cell is programmed and erased from one first transistor and read from the other second transistor. Since the floating gates of the two transistors are connected together and insulated from other ambient layers, stored charges can be controlled from the first transistor and affect a threshold of the second transistor. 1. A non-volatile memory cell disposed over a substrate , comprising:a first active region and a second active region separated by a central isolation region in a first direction;first and second peripheral isolation regions disposed about outermost sides of the first and second active regions; the central isolation region and the first and second peripheral isolation regions having a first height above the first and second active regions forming a first recess between the central isolation region and the first peripheral isolation region, and a second recess between the central isolation region and the second peripheral isolation region;first and second floating gates disposed in the first and second recesses respectively; anda floating gate bridge disposed over the central isolation region electrically connecting the first and second floating gates;wherein the first floating gate is disposed abutting a first sidewall of the first peripheral isolation region and the second floating gate is disposed abutting a second sidewall of the second peripheral isolation region.2. The non-volatile memory cell of claim 1 , wherein the floating gate bridge has a second height above the connected first and second floating gates; and the floating gate bridge laterally extends over an edge of the central isolation region along the first direction.3. The non-volatile memory cell of ...

Semiconductor Devices and Methods of Manufacturing

A single layer process is utilized to reduce swing effect interference and reflection during imaging of a photoresist. An anti-reflective additive is added to a photoresist, wherein the anti-reflective additive has a dye portion and a reactive portion. Upon dispensing the reactive portion will react with underlying structures to form an anti-reflective coating between the underlying structure and a remainder of the photoresist. During imaging, the anti-reflective coating will either absorb the energy, preventing it from being reflected, or else modify the optical path of reflection, thereby helping to reduce interference caused by the reflected energy. 1. A method of manufacturing a semiconductor device , the method comprising:applying a photoresist over a conductive material;forming an anti-reflective layer between the photoresist and the conductive material; andimaging the photoresist after the forming the anti-reflective layer.2. The method of claim 1 , wherein the photoresist comprises an anti-reflective molecule.3. The method of claim 2 , wherein the anti-reflective molecule is a thiol.4. The method of claim 2 , wherein the anti-reflective molecule comprises:a dye structure; anda reactive structure.5. The method of claim 4 , wherein the reactive structure is a SH group.6. The method of claim 2 , wherein during the applying the photoresist the anti-reflective molecule has a concentration of between about 0.01%-weight and 0.3%-weight.7. The method of claim 2 , wherein during the applying the photoresist the anti-reflective molecule will react with the conductive material.8. A method of manufacturing a semiconductor device claim 2 , the method comprising:applying a photoresist to a conductive surface;reacting the conductive surface with an anti-reflective additive within the photoresist to form a reacted surface;patterning the photoresist with a patterned energy source;developing the photoresist, the developing the photoresist exposing a portion of the reacted ...

Patterning Process of a Semiconductor Structure with Enhanced Adhesion

A lithography method includes forming a bottom anti-reflective coating (BARC) layer on a substrate, wherein the BARC layer includes an organic polymer and a reactive chemical group having at least one of chelating ligands and capping monomers, wherein the reactive chemical group is bonded to the organic polymer; coating a metal-containing photoresist (MePR) layer on the BARC layer, wherein the MePR being sensitive to an extreme ultraviolet (EUV) radiation; performing a first baking process to the MePR layer and the BARC layer, thereby reacting a metal chemical structure of the MePR layer and the reactive chemical structure of the BARC layer and forming an interface layer between the MePR layer and the BARC layer; performing an exposure process using the EUV radiation to the MePR layer; and developing the MePR layer to form a patterned photoresist layer. 1. A method , comprising:forming a bottom anti-reflective coating (BARC) layer on a substrate, wherein the BARC layer includes an organic polymer and a reactive chemical group having at least one of chelating ligands and capping monomers, wherein the reactive chemical group is bonded to the organic polymer;coating a metal-containing photoresist (MePR) layer on the BARC layer, wherein the MePR being sensitive to an extreme ultraviolet (EUV) radiation;performing a first baking process to the MePR layer and the BARC layer, thereby reacting a metal chemical structure of the MePR layer and the reactive chemical structure of the BARC layer and forming an interface layer between the MePR layer and the BARC layer;performing an exposure process using the EUV radiation to the MePR layer; anddeveloping the MePR layer to form a patterned photoresist layer.2. The method of claim 1 , further comprising performing a first etching process to transfer a pattern of the patterned photoresist layer to an under layer on the substrate.3. The method of claim 1 , wherein the organic polymer includes at least one of Polystyrene (PS) claim 1 ...

PATTERN FORMING METHOD AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

A pattern forming method includes forming a spin on dielectric film on a substrate, washing the spin on dielectric film by using a washing liquid, drying a surface of the spin on dielectric film after the washing, forming a photosensitive film on the dried coating type insulation film, emitting energy rays to a predetermined position of the photosensitive film in order to form a latent image on the photosensitive film, developing the photosensitive film in order to form a photosensitive film pattern which corresponds to the latent image, and processing the spin on dielectric film with the photosensitive film pattern serving as a mask. 120.-. (canceled)21. A semiconductor device manufacturing method comprising:preparing a first substrate above which a first film having a photosensitive film is formed;supplying a first washing liquid to an entire top surface of the first film before using an exposure apparatus, the photosensitive film being a chemically amplified resist film which contains an optical acid generating material;emitting energy rays to the photosensitive film using the exposure apparatus; anddeveloping the photosensitive film in order to form a photosensitive film pattern,wherein a planarization of the photosensitive film above the first substrate is unchanged by the supplying the first washing liquid to the entire top surface of the first film.22. The method according to claim 21 , wherein the exposure apparatus is an immersion type exposure apparatus.23. The method according to claim 22 , wherein the first washing liquid is a pure water.24. The method according to claim 22 , wherein the first film comprises an anti-reflection film below the photosensitive film.25. The method according to claim 22 , further comprising drying the top surface of the first film after the supplying the first washing liquid to the entire top surface of the first film before the using the exposure apparatus.26. The method according to claim 22 , wherein the supplying a first ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A photoresist is exposed to light under a condition that sensitivity of a second portion of the photoresist on a recessed portion of a base layer is higher than sensitivity of a first portion of the photoresist on a projecting portion of the base layer. 1. A method for manufacturing a semiconductor device , comprising the steps of:forming a base layer having a projecting portion, a recessed portion, and a level difference between the projecting portion and the recessed portion;forming a photoresist on the projecting portion and the recessed portion of the base layer to cover the level difference; andexposing light to the photoresist under a condition that sensitivity of a second portion of the photoresist on the recessed portion is higher than sensitivity of a first portion of the photoresist on the projecting portion.2. The method for manufacturing the semiconductor device according to claim 1 , wherein an uppermost layer of the projecting portion is an antireflection film having an attenuation coefficient k value greater than an attenuation coefficient k value of a layer below the uppermost layer of the projecting portion claim 1 , with respect to a wavelength of exposure light used when exposing light to the photoresist.3. The method for manufacturing the semiconductor device according to claim 2 , wherein the attenuation coefficient k value of the antireflection film is more than or equal to 0.5 with respect to the wavelength of the exposure light used when exposing light to the photoresist.4. The method for manufacturing the semiconductor device according to claim 2 , whereinthe projecting portion of the base layer is formed to include a film to be processed, and a hard mask layer made of a material different from a material for the film to be processed, andthe hard mask layer is formed between the film to be processed and the antireflection film.5. The method for manufacturing the semiconductor device according to claim 4 , wherein the step of forming the film ...

METHOD FOR REDUCING CHARGE IN CRITICAL DIMENSION-SCANNING ELECTRON MICROSCOPE METROLOGY

Methods and compositions are provided for reducing or eliminating charge buildup during scanning electron microscopy (SEM) metrology of a critical dimension (CD) in a structure produced by lithography. An under layer is utilized that comprises silicon in the construction of the structure. When the lithography structure comprising the silicon-comprising under layer is scanned for CDs using SEM, the under layer reduces or eliminates charge buildup during SEM metrological observations. 1. A method for reducing charging and/or shrinkage in a surface of interest during measurement of the surface in the manufacture of an integrated device , the method comprising:(a) providing a substrate;(b) positioning a silicon-comprising under layer on the substrate;(c) positioning a patterned photoresist image layer on the under layer;(d) delivering an electron beam to the surface of interest; and(e) measuring the surface of interest with the electron beam, thereby reducing charging and/or shrinkage.2. The method of wherein the surface is lithographically fabricated.3. The method of wherein the silicon-comprising under layer comprises a nondoped or doped conjugated or conducting polymer comprising silicon.4. The method of wherein the silicon-comprising under layer comprises a silicon-containing antireflection coating (SiARC).5. The method of wherein (b) claim 1 , positioning a silicon-comprising under layer on the substrate claim 1 , comprises depositing an organic layer and depositing silicon on the organic layer.6. The method of wherein depositing silicon on the organic layer comprises vapor-depositing silicon on the organic layer or silylating the organic layer.7. The method of wherein the substrate comprises silicon.8. The method of wherein the substrate comprising silicon is a silicon wafer.9. The method of wherein (c) claim 1 , positioning the patterned photoresist image layer on the silicon-comprising under layer claim 1 , comprises spin coating the photoresist image layer on ...

Method and Structure for Gap Filling Improvement

Semiconductor devices having void-free dielectric structures and methods of fabricating same are disclosed herein. An exemplary semiconductor device includes a plurality of fin structures disposed over a substrate having isolation features disposed therein and a plurality of gate structures disposed over the plurality of fin structures. The plurality of gate structures traverse the plurality of fin structures. The semiconductor device further includes a dielectric structure defined between the plurality of fin structures and the plurality of gate structures. The dielectric structure has an aspect ratio of about 5 to about 16. The dielectric structure includes a first dielectric layer disposed over the substrate and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer and the second dielectric layer are disposed on sidewalls of the plurality of fin structures and sidewalls of the plurality of gate structures. 1. A semiconductor device comprising:a plurality of fin structures disposed over a substrate having isolation features disposed therein;a plurality of gate structures disposed over the plurality of fin structures, such that the plurality of gate structures traverse the plurality of fin structures; a first dielectric layer disposed over the substrate, such that the first dielectric layer is disposed on sidewalls of the plurality of fin structures and sidewalls of the plurality of gate structures; and', 'a second dielectric layer disposed on the first dielectric layer, such that the second dielectric layer is disposed on the sidewalls of the plurality of fin structures and the sidewalls of the plurality of gate structures., 'a dielectric structure defined between the plurality of fin structures and the plurality of gate structures, wherein the dielectric structure has an aspect ratio of about 5 to about 16, and further wherein the dielectric structure includes2. The semiconductor device of claim 1 , wherein a sum of a ...

MATERIAL FOR FORMING UNDERLAYER FILM FOR LITHOGRAPHY, COMPOSITION FOR FORMING UNDERLAYER FILM FOR LITHOGRAPHY, UNDERLAYER FILM FOR LITHOGRAPHY AND PRODUCTION METHOD THEREOF, PATTERN FORMING METHOD, RESIN, AND PURIFICATION METHOD

The present embodiment provides a material for forming an underlayer film for lithography, containing at least any of a compound represented by following formula (1) or a resin including a structural unit derived from a compound represented by the following formula (1), 5. The material for forming the underlayer film for lithography according to claim 4 , wherein q in the formula (1-3) is 1.7. The material for forming the underlayer film for lithography according to claim 1 , wherein the compound has a group including an iodine atom.9. A composition for forming an underlayer film for lithography claim 1 , comprising the material for forming the underlayer film for lithography according to claim 1 , and a solvent.10. The composition for forming the underlayer film for lithography according to claim 9 , further comprising an acid generator.11. The composition for forming the underlayer film for lithography according to claim 9 , further comprising a crosslinking agent.12. An underlayer film for lithography claim 9 , formed from the composition for forming the underlayer film for lithography according to .13. A method for producing an underlayer film for lithography claim 9 , comprising forming an underlayer film on a substrate by using the composition for forming the underlayer film for lithography according to .14. A resist pattern forming method comprising{'claim-ref': {'@idref': 'CLM-00009', 'claim 9'}, 'a step of forming an underlayer film on a substrate by using the composition for forming the underlayer film for lithography according to ,'}a step of forming at least one photoresist layer on the underlayer film, anda step of irradiating a predetermined region of the photoresist layer with radiation, and developing it.15. A circuit pattern forming method comprising{'claim-ref': {'@idref': 'CLM-00009', 'claim 9'}, 'a step of forming an underlayer film on a substrate by using the composition for forming the underlayer film for lithography according to ,'}a step of ...

Substrate processing apparatus and substrate processing method

A resist film including a metallic component and a photosensitive material is formed on a surface of a substrate, and then a peripheral portion of the resist film on the substrate is irradiated with light by an edge exposer. Subsequently, development processing is performed with a development liquid from a nozzle on the exposed portion of the resist film. Thus, the part of the resist film formed on the peripheral portion of the substrate is removed. Thereafter, exposure processing is performed on the substrate in an exposure device, so that an exposure pattern is formed on the resist film. Then, a development liquid is supplied to the exposed substrate in a development processing unit, so that development processing is performed on the resist film.

Composition for forming silicon-containing resist underlayer film having carbonyl structure

A composition for forming a resist underlayer film that mask residues after lithography can be removed only with a chemical without etching. A composition for forming a silicon-containing resist underlayer film, that includes a polysiloxane having a unit structure including a carbonyl group-containing functional group, wherein the silicon-containing resist underlayer film is used as a mask layer in a step of removing the mask layer with a hydrogen peroxide-containing chemical after transfer of a pattern to an underlayer by a lithography process. The composition for forming a silicon-containing resist underlayer film, wherein the unit structure including a carbonyl group-containing functional group may include a cyclic acid anhydride group, a cyclic diester group, or a diester group. The polysiloxane may further have a unit structure including an amide group-containing organic group. The amide group may be a sulfonamide group or a diallyl isocyanurate group.

METHOD FOR CRITICAL DIMENSION REDUCTION USING CONFORMAL CARBON FILMS

Embodiments of the disclosure generally provide a method of forming a reduced dimension pattern in a hardmask that is optically matched to an overlying photoresist layer. The method generally comprises of application of a dimension shrinking conformal carbon layer over the field region, sidewalls, and bottom portion of the patterned photoresist and the underlying hardmask at temperatures below the decomposition temperature of the photoresist. The methods and embodiments herein further involve removal of the conformal carbon layer from the bottom portion of the patterned photoresist and the hardmask by an etch process to expose the hardmask, etching the exposed hardmask substrate at the bottom portion, followed by the simultaneous removal of the conformal carbon layer, the photoresist, and other carbonaceous components. A hardmask with reduced dimension features for further pattern transfer is thus yielded. 1. A method of forming a reduced dimension pattern in a hardmask comprising:forming a patterned photoresist layer on a hardmask layer;depositing a conformal carbon layer on the patterned photoresist by a plasma process, wherein the conformal carbon layer is disposed over a field region and sidewalls and a bottom portion of a feature formed in the patterned photoresist;removing the conformal carbon layer from the bottom portion by an etch process to expose a portion of the hardmask layer;etching the exposed portion of the hardmask layer to form a recess in the hardmask layer; andremoving the remaining portions of the conformal carbon layer and patterned photoresist layer simultaneously by a plasma ashing method.2. A method of claim 1 , wherein the hardmask layer comprises a SiON:Hmaterial claim 1 , and wherein the optical properties of the hardmask layer are tuned so that the hardmask layer appears optically flat at the exposure wavelength of the photoresist.3. The method of claim 2 , wherein the photoresist has a refractive index between 1.6 and 1.7 and a ...

BLOCK PATTERNING PROCESS FOR POST FIN

A method of reducing etch time needed for patterning an organic planarization layer (OPL) in a block mask stack so as to minimize damages to gate structures and fin structures in a block mask patterning process is provided. The block mask stack including an OPL, a developable antireflective coating (DARC) layer atop the OPL and a photoresist layer atop the DARC layer is employed to mask one conductivity type of FinFET while exposing the other conductivity type FinFET during source/drain ion implantation. The OPL is configured to have a minimum thickness sufficient to fill in spaces between semiconductor fins and to cover the semiconductor fins. The DARC layer is configured to planarize topography of semiconductor fins so as to provide a planar top surface for the ensuing lithography and etch processes. 1. A method of forming a semiconductor structure comprising:forming a plurality of semiconductor fins on a substrate comprising a buried insulator layer over a handle substrate;forming a gate structure over a portion of each of the plurality of semiconductor fins;forming a contact trench in the substrate, wherein the contact trench extends through the buried insulator layer and into the handle substrate;forming an organic planarization layer (OPL) over the substrate, wherein the OPL is deposited to a minimum thickness sufficient to fill in spaces between the plurality of semiconductor fins and to cover the plurality of semiconductor fins, and the OPL fills in the contact trench, and wherein a top surface of the OPL is non-planar;forming a developable antireflective coating (DARC) layer on the top surface of the OPL, wherein the DARC layer provides a substantially planar top surface;forming a photoresist layer on the top surface of the DARC layer;exposing a portion of the photoresist layer to a radiation, the radiation creating a pattern in exposed portion of the photoresist layer and a portion of the DARC layer underlying the exposed portion of the photoresist layer; ...

GATE CUT IN RMG

A method is presented for performing a gate cut in a field effect transistor (FET) structure. The method includes forming a plurality of fins and at least one insulating pillar over a semiconductor substrate, depositing a first work function metal layer, removing the first work function metal layer from a first set of fins, depositing a second work function metal layer, depositing a conductive material over the second work function metal layer, forming at least one gate trench through the conductive material and adjacent the first set of fins to separate active gate regions, and filling the at least one gate trench with an insulating material. 1. A method for performing a gate cut in a field effect transistor (FET) structure , the method comprising:forming a plurality of fins and at least one insulating pillar over a semiconductor substrate;depositing a first work function metal layer;removing the first work function metal layer from a first set of fins;depositing a second work function metal layer; anddepositing a conductive material over the second work function metal layer,wherein portions of the second work function metal layer are collinear with portions of the first work function metal layer after formation of at least one gate trench.2. The method of claim 1 , further comprising forming the at least one gate trench through the conductive material.3. The method of claim 2 , further comprising forming the at least one gate trench adjacent the first set of fins to separate active gate regions.4. The method of claim 3 , further comprising filling the at least one gate trench with an insulating material.5. The method of claim 4 , further comprising planarizing the insulating material such that the at least one insulating pillar has a same height as the first work function metal layer.6. The method of claim 5 , wherein the first work function metal layer extends over the plurality of fins and extends over the at least one insulating pillar.7. The method of claim 6 ...

GATE CUT IN RMG

A method is presented for performing a gate cut in a field effect transistor (FET) structure. The method includes forming a plurality of fins and at least one insulating pillar over a semiconductor substrate, depositing a first work function metal layer, removing the first work function metal layer from a first set of fins, depositing a second work function metal layer, depositing a conductive material over the second work function metal layer, forming at least one gate trench through the conductive material and adjacent the first set of fins to separate active gate regions, and filling the at least one gate trench with an insulating material. 1. A method for performing a gate cut in a field effect transistor (FET) structure , the method comprising:forming a plurality of fins and at least one insulating pillar over a semiconductor substrate;depositing a first work function metal layer;removing the first work function metal layer from a first set of fins;depositing a second work function metal layer;depositing an organic patterning layer over the second work function metal layer;forming at least one gate trench through the organic patterning layer;filling the at least one gate trench with an insulating material;forming a conductive adhesion liner over the insulating material and the second work function metal layer; anddepositing a conductive material over the conductive adhesion liner.2. The method of claim 1 , further comprising forming a dielectric layer over the plurality of fins and over the at least one insulating pillar before depositing the first work function metal layer.3. The method of claim 2 , further comprising depositing a patterning stack over the organic patterning layer and before forming the at least one gate trench.4. The method of claim 1 , further comprising employing work function metal patterning to remove the first work function metal layer prior to forming the at least one gate trench.5. The method of claim 1 , wherein the conductive ...

SHADOW TRIM LINE EDGE ROUGHNESS REDUCTION

A method for etching an etch layer in a stack over a substrate wherein the etch layer is under a mask layer which is under a patterned organic mask is provided. The stack and substrate is placed on a support in the plasma chamber. A silicon based layer is deposited in situ over the stack. The silicon based layer is etched to form silicon based sidewalls or spacers on sides of the patterned organic mask. The mask layer is selectively etched with respect to the silicon based sidewalls or spacers, wherein the selectively etching the mask layer undercuts the silicon based sidewalls or spacers. The etch layer is selectively etched with respect to the mask layer. The stack and substrate are removed from the support and the plasma chamber. 1. A method for etching an etch layer in a stack over a substrate wherein the etch layer is under a mask layer which is under a patterned organic mask , comprising:placing the stack and substrate on a support in the plasma chamber;in situ depositing a silicon based layer over the stack;etching the silicon based layer to form silicon based sidewalls or spacers on sides of the patterned organic mask;selectively etching the mask layer with respect to the silicon based sidewalls or spacers, wherein the selectively etching the mask layer undercuts the silicon based sidewalls or spacers;selectively etching the etch layer with respect to the mask layer; andremoving the stack and substrate from the support and the plasma chamber.2. The method claim 1 , as recited in claim 1 , wherein the etch layer is silicon or metal based.3. The method claim 2 , as recited in claim 2 , wherein the selectively etching the etch layer simultaneously removes the silicon based sidewalls or spacers.4. The method claim 3 , as recited in claim 3 , wherein mask layer comprises a carbon based material.5. The method claim 4 , as recited in claim 4 , wherein the selective etching of the mask layer comprises;flowing an oxygen based etch gas into the plasma chamber;forming ...

Filling cavities in an integrated circuit and resulting devices

A methodology enabling filling of high aspect ratio cavities, with no voids or gaps, in an IC device and the resulting device are disclosed. Embodiments include providing active area and/or gate contacts in a first ILD; forming selective protective caps on upper surfaces of the contacts; forming a second ILD on upper surfaces of the protective caps and on an upper surface of the first ILD; forming a hard-mask stack on the second ILD; forming, in the second ILD and hard-mask stack, cavities exposing one or more protective caps; removing selective layers in the stack to decrease depths of the cavities; and filling the cavities with a metal layer, wherein the metal layer in one or more cavities connects to an upper surface of the one or more exposed protective caps.

Lithography Method with Surface Modification Layer

A lithography method is provided in accordance with some embodiments. The lithography method includes forming a surface modification layer on a substrate, the surface modification layer including a hydrophilic top surface; coating a photoresist layer on the surface modification layer; and developing the photoresist layer, thereby forming a patterned photoresist layer. 1. A lithography method , comprising:forming a surface modification layer on a substrate, wherein the surface modification layer includes a hydrophilic top surface;coating a photoresist layer on the surface modification layer; anddeveloping the photoresist layer, thereby forming a patterned photoresist layer.2. The method of claim 1 , wherein the surface modification layer includes polymeric molecules each having a hydrophobic backbone and hydrophilic side chains chemically or physically bonded to the hydrophobic backbone.3. The method of claim 2 , wherein the hydrophobic backbone includes a plurality of repeating benzene derivatives each being bonded to a hydrophilic chemical structure R.4. The method of claim 3 , wherein the hydrophilic chemical structure R is selected from the group consisting of CHCHOH claim 3 , CHCHCOOH claim 3 , CHSOH claim 3 , CHPOH claim 3 , CHNH claim 3 , and CHN(CH).7. The method of claim 1 , wherein the surface modification layer includes a block copolymer having a hydrophobic block bonded with a hydrophilic block.9. The method of claim 1 , wherein the surface modification layer includes a hydrophilic chemical group selected from the group consisting of hydroxyl group claim 1 , acid group claim 1 , amine group and a combination thereof.10. The method of claim 1 , wherein the surface modification layer includes a hydrophilic chemical group selected from the group consisting of polyvinylpyrrolidone claim 1 , polyvinylpyridine claim 1 , poly(diallydimethyl ammonium chloride) claim 1 , polyethyleneimine claim 1 , polyacrylamide claim 1 , polyamide claim 1 , a polymer with ...

METHOD OF PROCESSING TARGET OBJECT

A method of processing a target object is provided. The target object has an etching target layer, an organic film on the etching target layer and a mask on the organic film. The organic film includes a first layer and a second layer, the mask is provided on the first layer, the first layer is provided on the second layer, and the second layer is provided on the etching target layer. The method includes generating plasma of a first gas within a processing vessel of a plasma processing apparatus in which the target object is accommodated; etching the first layer with the plasma of the first gas and the mask until the second layer is exposed; and conformally forming a protection film on a side surface of the first layer; and generating plasma of a second gas and removing the mask with the plasma of the second gas. 1. A method of processing a target object having an etching target layer , an organic film provided on the etching target layer and a mask provided on the organic film , the organic film including a first layer and a second layer , the mask being provided on the first layer , the first layer being provided on the second layer , and the second layer being provided on the etching target layer , the method comprising:generating plasma of a first gas within a processing vessel of a plasma processing apparatus in which the target object is accommodated; etching the first layer with the plasma of the first gas and the mask until the second layer is exposed; and conformally forming a protection film on a side surface of the first layer formed by the etching; andgenerating plasma of a second gas within the processing vessel and removing the mask with the plasma of the second gas,wherein the removing of the mask is performed before the etching target layer is etched.2. The method of claim 1 ,wherein the second gas contains any one of a hydrofluorocarbon gas, a fluorocarbon gas and a chlorine gas.3. The method of claim 1 ,wherein the first gas contains a hydrogen gas ...

SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF

A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a base substrate including a device region and a peripheral region. The base substrate includes a base interconnection structure. The method also includes forming a medium layer on the base substrate. In addition, the method includes forming a first trench having a first depth in the peripheral region, and forming a second trench having a second depth in the device region. The second depth is greater than the first depth. Moreover, the method includes forming a first opening in the device region and forming a second opening in the peripheral region. Further, the method includes forming a first interconnection structure by filling the first opening with a conductive material and forming a second interconnection structure by filling the second opening with the conductive material. 1. A method for fabricating a semiconductor structure , comprising:providing a base substrate including a device region and a peripheral region surrounding the device region, wherein the base substrate includes a base interconnection structure formed in each of the device region and the peripheral region;forming a medium layer on the base substrate;forming a first trench having a first depth in the medium layer in the peripheral region;forming a second trench having a second depth in the medium layer in the device region, wherein the second depth is greater than the first depth;forming a first opening exposing the base interconnection structure in the medium layer in the device region and forming a second opening exposing the base interconnection structure in the medium layer in the peripheral region by etching the medium layer at a bottom and a sidewall of the second trench and etching the medium layer at a bottom of the first trench; andforming a first interconnection structure by filling the first opening with a conductive material and forming a second ...

Silicon oxynitride film formation method and substrate equipped with silicon oxynitride film formed thereby

The present invention provides a silicon oxynitride film formation method capable of reducing energy cost, and also provides a substrate equipped with a silicon oxynitride film formed thereby. This method comprises the steps of: casting a film-formable coating composition containing a polysilazane compound on a substrate surface to form a coat; drying the coat to remove excess of the solvent therein; and then irradiating the dried coat with UV light at a temperature lower than 150° C.

Resist Solvents for Photolithography Applications

A method includes providing a photoresist solution that includes a first solvent having a first volume and a second solvent having a second volume, where the first solvent is different from the second solvent and where the first volume is less than the second volume; dispersing the photoresist solution over a substrate to form a film, where the dispersing evaporates a portion of the first solvent and a portion of the second solvent such that a remaining portion of the first solvent is greater than a remaining portion of the second solvent; baking the film; after baking the film, exposing the film to form an exposed film; and developing the exposed film. 1. A method , comprising:providing a photoresist solution, wherein the photoresist solution includes a first solvent having a first volume and a second solvent having a second volume, wherein the first solvent is different from the second solvent, and wherein the first volume is less than the second volume;dispersing the photoresist solution over a substrate to form a film, wherein the dispersing evaporates a portion of the first solvent and a portion of the second solvent such that a remaining portion of the first solvent is greater than a remaining portion of the second solvent;baking the film;after baking the film, exposing the film, resulting in an exposed film; anddeveloping the exposed film.2. The method of claim 1 , wherein the first solvent includes diethylene glycol dimethyl ether claim 1 , triethylene glycol dimethyl ether claim 1 , dimethyl sulfoxide claim 1 , ethylene glycol claim 1 , glycerin claim 1 , hexamethylphosphoramide claim 1 , N-methyl-2-pyrrolidinone claim 1 , benzonitrile claim 1 , 1 claim 1 ,2-dichlorobenzene claim 1 , N claim 1 ,N dimethylacetamide claim 1 , 2-ethoxyethyl ether claim 1 , gamma-butyrolactone claim 1 , 1 claim 1 ,6-di-acetoxyhexane claim 1 , tri(propylene glycol) methyl ether claim 1 , propylene carbonate claim 1 , tetra(ethylene glycol) monomethyl ether claim 1 , or ...

MATERIAL FOR FORMING UNDERLAYER FILM FOR LITHOGRAPHY, COMPOSITION FOR FORMING UNDERLAYER FILM FOR LITHOGRAPHY, UNDERLAYER FILM FOR LITHOGRAPHY, RESIST PATTERN FORMING METHOD, AND CIRCUIT PATTERN FORMING METHOD

The present invention provides a material for forming an underlayer film for lithography, including a cyanic acid ester compound obtained by cyanation of a modified naphthalene formaldehyde resin. 1. A material for forming an underlayer film for lithography , comprising a cyanic acid ester compound obtained by cyanation of a modified naphthalene formaldehyde resin.3. The material for forming the underlayer film for lithography according to claim 1 , wherein the modified naphthalene formaldehyde resin is a resin obtained by modifying a naphthalene formaldehyde resin or a deacetalized naphthalene formaldehyde resin by use of a hydroxy-substituted aromatic compound.4. The material for forming the underlayer film for lithography according to claim 3 , wherein the hydroxy-substituted aromatic compound is at least one selected from the group consisting of phenol claim 3 , 2 claim 3 ,6-xylenol claim 3 , naphthol claim 3 , dihydroxynaphthalene claim 3 , biphenol claim 3 , hydroxyanthracene and dihydroxyanthracene.5. The material for forming the underlayer film for lithography according to claim 1 , wherein a weight average molecular weight of the cyanic acid ester compound is 200 or more and 25000 or less.8. A composition for forming an underlayer film for lithography claim 1 , comprising the material for forming the underlayer film for lithography according to claim 1 , and a solvent.9. The composition for forming the underlayer film for lithography according to claim 8 , further comprising an acid generator.10. The composition for forming the underlayer film for lithography according to claim 8 , further comprising a crosslinking agent.11. An underlayer film for lithography claim 8 , formed using the composition for forming the underlayer film for lithography according to .12. A resist pattern forming method comprising:{'claim-ref': {'@idref': 'CLM-00008', 'claim 8'}, 'a step of forming an underlayer film on a substrate by using the composition for forming the underlayer ...

Stacked structure body and pattern formation method

According to one embodiment, a stacked structure body includes: an underlayer; a mask layer provided on the underlayer; a copolymer-containing layer provided on the mask layer, the copolymer-containing layer containing a metal and carbon, and the copolymer-containing layer including a first copolymer region and a second copolymer region provided on the first copolymer region, and the second copolymer region having a lower proportion of a metal concentration to a carbon concentration than the first copolymer region; and a resist pattern provided on the copolymer-containing layer.

DISPLAY SUBSTRATE AND METHOD FOR PREPARING THE SAME, AND DISPLAY DEVICE

The present disclosure provides a display substrate, a method for preparing the same, and a display device. The display substrate includes: a base substrate; a metal pattern located on the base substrate, and an anti-reflection pattern located on a surface of the metal pattern proximate to the base substrate, in which a difference between a first slope angle of the anti-reflection pattern and a second slope angle of the metal pattern is less than a first threshold, and a distance between a first edge of a side surface of the anti-reflection pattern proximate to the metal pattern and a second edge of a side surface of the metal pattern proximate to the anti-reflection pattern is less than a second threshold. 1. A display substrate , comprising:a base substrate;a metal pattern located on the base substrate; andan anti-reflection pattern located on a surface of the metal pattern proximate to the base substrate,wherein a difference between a first slope angle of the anti-reflection pattern and a second slope angle of the metal pattern is less than a first threshold, and a distance between a first edge of a side surface of the anti-reflection pattern proximate to the metal pattern and a second edge of a side surface of the metal pattern proximate to the anti-reflection pattern is less than a second threshold;the first slope angle is an acute angle formed between the side surface of the anti-reflection pattern and the base substrate, the second slope angle is an acute angle formed between the side surface of the metal pattern and the base substrate, and the first edge and the second edge are located on a same side of the anti-reflection pattern.2. The display substrate of claim 1 , wherein the first threshold is 5° claim 1 , and the second threshold is 10 nm.3. The display substrate of claim 2 , wherein the first slope angle is equal to the second slope angle claim 2 , and the first edge coincides with the second edge.4. The display substrate of claim 1 , wherein the ...

SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first gate stack over the semiconductor substrate. The first gate stack includes a first gate and a second gate over the first gate, and the first gate and the second gate are electrically isolated from each other. The semiconductor device structure includes a ring structure surrounding the first gate stack. The ring structure is made of a conductive material. 1. A semiconductor device structure , comprising:a semiconductor substrate;a gate stack over the semiconductor substrate, wherein the gate stack includes a first gate and a second gate over the first gate, and the first gate and the second gate are electrically isolated from each other; anda ring structure surrounding the gate stack, wherein the ring structure is made of a conductive material.2. The semiconductor device structure as claimed in claim 1 , wherein the second gate is made of the conductive material.3. The semiconductor device structure as claimed in claim 1 , wherein the semiconductor substrate has a first region surrounded by an isolation structure embedded in the semiconductor substrate claim 1 , the gate stack is over the first region claim 1 , and the ring structure surrounds the entire first region.4. The semiconductor device structure as claimed in claim 3 , wherein the semiconductor substrate further has a second region claim 3 , the semiconductor device structure further comprises a third gate over the second region claim 3 , and the ring structure is between the third gate and the gate stack.5. The semiconductor device structure as claimed in claim 4 , wherein the third gate claim 4 , the ring structure claim 4 , and the second gate are made of the conductive material.6. The semiconductor device structure as claimed in claim 4 , wherein a first thickness of the gate stack is greater than a second thickness of the third gate.7. ...

Method for Dopant Implantation of FinFET Structures

The present disclosure is related to a method for implanting dopant elements in a structure comprising a plurality of semiconductor fins separated by field dielectric areas. The method includes depositing an etch stop layer on the fins, depositing a BARC layer on the etch stop layer, depositing a resist layer on the BARC layer, removing a portion of the resist layer by lithography steps to thereby expose an area of the BARC layer, removing the BARC layer in the exposed area by a dry etch process using the remaining resist layer as a mask, implanting dopant elements into the fins present in the area, using the BARC and resist layers as a mask, and removing the remainder of the resist and BARC layers. 1. A method for implanting dopant elements in a structure comprising a plurality of semiconductor fins separated by field dielectric areas , the method comprising:depositing an etch stop layer on the fins;depositing a BARC layer on the etch stop layer;depositing a resist layer on the BARC layer removing a portion of the resist layer by lithography steps, thereby exposing an area of the BARC layer;removing the BARC layer in the exposed area by a dry etch process using the remaining resist layer as a mask;implanting dopant elements into the fins present in the area, using the BARC and resist layers as a mask; andremoving the remainder of the resist and BARC layers.2. The method according to claim 1 , wherein the BARC layer is a planarizing layer.3. The method according to claim 2 , wherein the BARC layer is a non-conformal BARC layer.4. The method according to claim 1 , wherein the etch stop layer is removed in the exposed area before the step of implanting dopant elements.5. The method according to claim 1 , wherein the etch stop layer is not removed in the exposed area before the step of implanting dopant elements claim 1 , and wherein the dopant elements are implanted through the etch stop layer.6. The method according to claim 1 , wherein the etch stop layer is a ...

METHOD FOR ETCHING ORGANIC FILM AND PLASMA ETCHING DEVICE

In a method for etching an organic film according to an embodiment, a target object that has an organic film is set in a processing chamber. Then, a processing gas containing COS gas and Ogas is supplied to the processing chamber and a microwave for plasma excitation is supplied to the inside of the processing chamber to etch the organic film. 1. A method for etching an organic film , comprising:preparing in a processing chamber a target object having an organic film; and{'sub': '2', 'etching the organic film by supplying a processing gas including COS gas and Ogas into the processing chamber and supplying a microwave for plasma excitation into the processing chamber.'}2. The method of claim 1 , wherein the target object includes a substrate and a multilayer film formed on the substrate claim 1 , the multilayer film having a patterned resist film and the organic film formed between the resist film and the substrate.3. The method of claim 2 , wherein in the etching the organic film claim 2 , the processing gas further includes Ngas.4. The method of claim 2 , wherein in the etching the organic film claim 2 , a pressure in the processing chamber is controlled to a range from 20 mTorr to 100 mTorr.5. The method of claim 2 , wherein the multilayer film has a Si anti-reflection coating film provided between the resist film and the organic film claim 2 , andthe method further comprises, before the etching the organic film, etching the Si anti-reflection coating film by supplying a gas including a fluorocarbon-based gas and COS gas into the processing chamber and supplying a microwave into the processing chamber.6. A plasma etching device comprising:a processing chamber;a gas supply unit configured to supply a processing gas into the processing chamber;a microwave generating unit; andan antenna, connected to the microwave generating unit, configured to supply a microwave for plasma excitation into the processing chamber,{'sub': '2', 'wherein the gas supply unit is ...

Lithography Process and Material for Negative Tone Development

The present disclosure provides resist rinse solutions and corresponding lithography techniques that achieve high pattern structural integrity for advanced technology nodes. An example lithography method includes forming a resist layer over a workpiece, exposing the resist layer to radiation, developing the exposed resist layer using a developer that removes an unexposed portion of the exposed resist layer, thereby forming a patterned resist layer, and rinsing the patterned resist layer using a rinse solution. The developer is an organic solution, and the rinse solution includes water. 1. A lithography method comprising:forming a resist layer over a workpiece;exposing the resist layer to radiation;developing the exposed resist layer using a developer that removes an unexposed portion of the exposed resist layer, thereby forming a patterned resist layer; andrinsing the patterned resist layer using a rinse solution,wherein the developer is an organic solution, and wherein the rinse solution includes water.2. The lithography method of claim 1 , wherein during the rinsing the water penetrates into the patterned resist layer such that hydrogen bonds are formed between molecules of the water and polar functional groups of the patterned resist layer.3. The lithography method of claim 1 , wherein the water constitutes between about 5% and about 30% of the rinse solution.4. The lithography method of claim 1 , wherein the rinse solution further includes a dipolar solvent that constitutes between about 5% and about 70% of the rinse solution.5. The lithography method of claim 1 , wherein the rinse solution includes a solvent that has a surface tension lower than about 35 dyn/cm.6. The lithography method of claim 5 , wherein the solvent that has a surface tension lower than about 35 dyn/cm constitutes between about 10% and about 70% of the rinse solution.7. The lithography method of claim 5 , wherein the rinse solution has an overall surface tension greater than about 35 dyn/cm. ...

MASK PATTERN STRUCTURES, METHODS OF FORMING HOLES USING THE SAME, AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME

In a method of forming holes, a plurality of guide patterns physically spaced apart from each other is formed on an object layer. The guide pattern has a ring shape and includes a first opening therein. A self-aligned layer is formed on the object layer and the guide patterns to fill the first opening. Preliminary holes are formed by removing portions of the self-aligned layer which are self-assembled in the first opening and between the guide patterns neighboring each other. The object layer is partially etched through the preliminary holes. 1. A method of forming holes , the method comprising:forming a plurality of guide patterns physically spaced apart from each other on an object layer, each of the guide patterns having a ring shape and including a first opening therein;forming a self-aligned layer on the object layer and the guide patterns to fill the first openings;forming preliminary holes by removing portions of the self-aligned layer which are self-assembled in the first openings and between the guide patterns neighboring each other; andpartially etching the object layer through the preliminary holes.2. The method of claim 1 , wherein:the self-aligned layer is formed using a block copolymer that includes a first polymer unit and a second polymer unit different from each other, andforming the self-aligned layer on the object layer and the guide patterns includes forming a first self-aligned pattern self-assembled at a central portion of each of the first openings and between the guide patterns neighboring each other, and a second self-aligned pattern self-assembled on a remaining portion of the object layer except for a portion of the object layer on which the first self-aligned pattern is formed, the first self-aligned pattern and the second self-aligned pattern including the first polymer unit and the second polymer unit, respectively.3. The method of claim 2 , wherein:the first self-aligned pattern includes a plurality of first pillars, each first pillar ...

METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE

A method for forming a semiconductor device structure is provided. The method includes forming a gate stack and a conductive layer over a semiconductor substrate. The method includes forming a negative photoresist layer to cover the gate stack and a first portion of the conductive layer over the isolation structure and expose a second portion of the conductive layer. The method includes forming a mask layer over the negative photoresist layer and the conductive layer. The mask layer has trenches over the second portion of the conductive layer and an edge portion of the negative photoresist layer, and a thickness of the edge portion decreases in a direction away from the gate stack. 1. A method for forming a semiconductor device structure , comprising:forming a gate stack and a conductive layer over a semiconductor substrate, wherein the semiconductor substrate has a first region and a second region isolated from each other by an isolation structure in the semiconductor substrate, the gate stack is formed over the first region, and the conductive layer is formed over the second region and the isolation structure;forming a negative photoresist layer to cover the gate stack and a first portion of the conductive layer over the isolation structure and expose a second portion of the conductive layer; andforming a mask layer over the negative photoresist layer and the conductive layer, wherein the mask layer has trenches over the second portion of the conductive layer and an edge portion of the negative photoresist layer, and a thickness of the edge portion decreases in a direction away from the gate stack.2. The method for forming a semiconductor device structure as claimed in claim 1 , further comprising:removing the second portion through the trenches after forming the mask layer over the negative photoresist layer and the conductive layer;removing the mask layer; andremoving the negative photoresist layer.3. The method for forming a semiconductor device structure as ...

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Provided is a method for manufacturing a semiconductor device including a film to be treated having a high flatness. A semiconductor substrate having a surface and including a first region and a second region on the surface is prepared, the first region being a region in which a plurality of first level difference portions are formed, the second region being a region in which a plurality of second level difference portions arranged more sparsely than the plurality of first level difference portions are formed, or a region in which no level difference portion is formed. A photosensitive film is formed on a portion of the second region to surround a periphery of the first region as seen in plan view. An applied film having flowability is formed to cover the first region and the photosensitive film. A portion of the applied film at least on the first region is removed. 1. A method for manufacturing a semiconductor device , comprising the steps of:preparing a semiconductor substrate having a main surface and including a first region and a second region on the main surface, the first region being a region in which a plurality of first level difference portions are formed, the second region being a region in which a plurality of second level difference portions arranged more sparsely than the plurality of first level difference portions are formed, or a region in which no level difference portion is formed;forming a photosensitive film at least on a portion of the second region to surround a periphery of the first region as seen in plan view;forming an applied film having flowability to cover the first region and the photosensitive film; andremoving a portion of the applied film at least on the first region.2. The method for manufacturing the semiconductor device according to claim 1 , whereinin the step of preparing the semiconductor substrate, the semiconductor substrate having a coating film formed thereon is prepared, the coating film covering at least the first level ...

SEMICONDUCTOR ARRANGEMENT AND METHOD OF MANUFACTURE

A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer. 1. A semiconductor arrangement , comprising: a first source/drain region;', 'a second source/drain region; and', 'a first gate structure between the first source/drain region and the second source/drain region;, 'a first transistor, comprising a third source/drain region;', 'a fourth source/drain region; and', a first axis disposed at a center of the first gate structure and extending in a direction perpendicular to a direction extending from the first source/drain region to the second source/drain region intersects the second gate structure,', 'a second axis disposed at a center of the second gate structure and extending in a direction perpendicular to a direction extending from the third source/drain region to the fourth source/drain region intersects the first gate structure,', 'the second axis is parallel to the first axis, and', 'the second axis is laterally offset from the first axis in the direction extending from the third source/drain region to the fourth source/drain region., 'a second gate structure between the third source/drain region and the fourth source/drain region, wherein], 'a second transistor, comprising2. The semiconductor arrangement of claim 1 , wherein the second gate structure contacts the first gate structure.3. The semiconductor arrangement of claim 1 , wherein the first source/drain region comprises a first dopant having a first dopant type and the third source/drain region comprises a second ...

Method of forming via hole

The present invention provides a method of forming via holes. First, a substrate is provided. A plurality of first areas is defined on the substrate. A dielectric layer and a blocking layer are formed on the substrate. A patterned layer is formed on the blocking layer such that a sidewall of the blocking layer is completely covered by the patterned layer. The patterned layer includes a plurality of holes arranged in a regular array wherein the area of the hole array is greater than those of the first areas. The blocking layer in the first areas is removed by using the patterned layer as a mask. Lastly, the dielectric layer is patterned to form at least a via hole in the dielectric layer in the first area.

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

In a method of manufacturing a semiconductor device, a photo resist layer is formed over a substrate with underlying structures. The first photo resist layer is exposed to exposure radiation. The exposed first photo resist layer is developed with a developing solution. A planarization layer is formed over the developed photo resist layer. The underlying structures include concave portions, and a part of the concave portions is not filled by the developed first photo resist. 1. A method of manufacturing a semiconductor device , the method comprising:forming a photo resist layer over a substrate with underlying structures;exposing the first photo resist layer to exposure radiation;developing the exposed first photo resist layer with a developing solution; andforming a planarization layer over the developed photo resist layer, wherein:the underlying structures include concave portions, anda part of the concave portions is not filled by the developed first photo resist.2. The method of claim 1 , wherein the planarization layer is made of an organic material.3. The method of claim 1 , wherein the planarization layer is made of photo resist different from the photo resist layer.4. The method of claim 1 , wherein the planarization layer has a different optical property than the photo resist layer.5. The method of claim 1 , wherein the planarization layer is made of a material different from the photo resist layer in at least one selected from the group consisting of a polymer structure claim 1 , an acid labile molecule claim 1 , a photo acid generator (PAG) amount claim 1 , a quencher amount claim 1 , a chromophore claim 1 , a cross linker claim 1 , and a solvent.6. The method of claim 1 , wherein the planarization layer is made of a same material as the photo resist layer.7. The method of claim 1 , wherein the planarization layer is made of a bottom anti-reflective coating material.8. The method of claim 1 , wherein:the substrate includes a first area and a second area,a ...

REFLECTION MODE PHOTOMASK AND FABRICATION METHOD THEREFORE

A method of fabricating a mask blank includes depositing a reflective multilayer over a substrate, depositing a capping layer over the reflective multilayer, depositing an absorber layer over the capping layer, and depositing an anti-reflective coating (ARC) layer over the absorber layer. The ARC layer is a single material film. 1. A method of fabricating a mask blank , the method comprising:depositing a reflective multilayer over a substrate;depositing a capping layer over the reflective multilayer;depositing an absorber layer over the capping layer; anddepositing an anti-reflective coating (ARC) layer over the absorber layer, wherein the ARC layer is a single material film.2. The method of claim 1 , wherein the depositing the ARC layer over the absorber layer comprises:depositing the ARC layer so that a ratio of a thickness of the ARC layer to the absorber layer is in a range from about 0.015 to about 0.075.3. The method of claim 1 , wherein the depositing the ARC layer over the absorber layer comprises:depositing the ARC layer to have a thickness ranging from about 1 nanometer (nm) to about 5 nm.4. The method of claim 1 , further comprising:depositing an etch stop layer over the capping layer, wherein a thickness of the etch stop layer ranges from about 2 nm to about 5 nm.5. The method of claim 4 , wherein the depositing the etch stop layer comprises:depositing the etch stop layer so that a ratio of an etch selectivity of the etch stop layer to that of the capping layer is equal to or smaller than 1:20.6. A method of manufacturing a reticle claim 4 , the method comprising:depositing an absorber layer over a substrate;depositing a hard mask layer over the absorber layer, wherein the hard mask layer includes tantalum;coating a photoresist directly over the hard mask layer; andpatterning the photoresist to expose a portion of the hard mask layer.7. The method of claim 6 , further comprising:performing a first etch process to remove the exposed portion of the hard ...

SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF

Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a base substrate having a first region and a second region; forming a first filling layer on the first region of the base substrate and a first hard mask layer on the first filling layer; performing a first treatment process on the second region of the base substrate using the first hard mask layer and the first filling layer as a mask; forming a second filling layer on the first region of the base substrate and a second mask on at least the second filling layer; removing the first hard mask layer and the first filling layer to expose the first region of the base substrate and to pattern the second hard mask layer on the second filling layer; and performing a second treatment process on the first region of the base substrate. 1. A method for fabricating a semiconductor structure , comprising:providing a base substrate having a first region and a second region;forming a first filling layer on the first region of the base substrate and forming a first hard mask layer on the first filling layer;performing a first treatment process on the second region of the base substrate using the first hard mask layer and the first filling layer as a mask;forming a second filling layer on the second region of the base substrate and forming a second mask on at least the second filling layer;removing the first hard mask layer and the first filling layer to expose the first region of the base substrate and to pattern the second hard mask layer on the second filling layer; andperforming a second treatment process on the first region of the base substrate.2. The method according to claim 1 , wherein:the first hard mask layer is made of a silicon-containing bottom anti-reflective coating material.3. The method according to claim 1 , wherein:the first hard mask layer is formed by at least one of a spin-coating process and a chemical vapor deposition process.4. The method ...

Semiconductor Device and Method of Manufacture

A dielectric layer is formed over a substrate, an anti-reflective layer is formed over the porous dielectric layer, and a first hardmask is formed over the anti-reflective layer. A via opening and a trench opening are formed within the porous dielectric layer using the anti-reflective layer and the first hardmask as masking materials. After the formation of the trench opening and the via opening, the first hardmask is removed. An interconnect is formed within the openings, and the interconnect has a via with a profile angle of between about 70° and about 80° and a depth ratio of between about 65% and about 70%.

PLASMA PROCESSING METHOD AND PLASMA PROCESSING APPARATUS

The present invention provides a plasma processing method and a plasma processing apparatus. The plasma processing method enables consistent processing by realizing a high selectivity and a high etching rate when etching a laminated film using a boron-containing amorphous carbon film, realizes high throughput including prior and post processes by simplifying a mask forming process, and has shape controllability of vertical processing. In the present invention, in a plasma processing method for forming a mask by plasma-etching a laminated film including an amorphous carbon film containing boron, the boron-containing amorphous carbon film is plasma-etched by using a mixed gas of an oxygen gas, a fluorine-containing gas, a halogen gas, and a silicon tetrafluoride gas, or a mixed gas of an oxygen gas, a fluorine-containing gas, a halogen gas, and a silicon tetrachloride gas. 1. A plasma processing method for forming a mask by plasma etching a laminated film having an amorphous carbon film containing boron ,wherein the boron-containing amorphous carbon film is plasma-etched by using a mixed gas of an oxygen gas, a fluorine-containing gas, a halogen gas, and a silicon tetrafluoride gas, or a mixed gas of an oxygen gas, a fluorine-containing gas, a halogen gas, and a silicon tetrachloride gas.2. The plasma processing method according to claim 1 , wherein the fluorine-containing gas is CHFgas claim 1 , CHFgas claim 1 , CHF gas claim 1 , NFgas claim 1 , CFgas claim 1 , or SFgas claim 1 , and{'sub': '2', 'the halogen gas is Clgas, HBr gas, or HI gas.'}3. The plasma processing method according to claim 1 , wherein a flow rate ratio of the halogen gas with respect to the mixed gas is higher than a flow rate ratio of the fluorine-containing gas with respect to the mixed gas.4. The plasma processing method according to claim 1 , wherein the boron-containing amorphous carbon film is plasma-etched by supplying a radio frequency power of 1000 W or more to a sample stand on which a ...

REMOVAL OF TRILAYER RESIST WITHOUT DAMAGE TO UNDERLYING STRUCTURE

A method for semiconductor processing includes removing, from a first region of a semiconductor device, a middle layer and a bottom layer of a trilayer structure including a photoresist layer to expose at least one first structure. A top layer of the trilayer structure in a second region of the semiconductor device is removed during the removal of the bottom layer in the first region. The method further includes, after removing the middle and bottom layers in the first region, filling the first region to protect the at least one first structure. 1. A method for semiconductor processing , comprising:removing, from a first region of a semiconductor device, a middle layer and a bottom layer of a trilayer structure including a photoresist layer to expose at least one first structure, a top layer of the trilayer structure in a second region of the semiconductor device being removed during the removal of the bottom layer in the first region; andafter removing the middle and bottom layers in the first region, filling the first region to protect the at least one first structure.2. The method of claim 1 , further comprising removing claim 1 , prior to removing the middle and bottom layers in the first region claim 1 , the top layer from the first region to expose the middle layer in the first region.3. The method of claim 1 , further comprising removing the middle layer in the second region while the at least one first structure remains protected.4. The method of claim 1 , wherein the trilayer structure includes an organic layer claim 1 , inorganic layer and organic layer claim 1 , respectively claim 1 , for the top layer claim 1 , the middle layer and the bottom layer.5. The method of claim 1 , wherein the middle layer is resistant to etchants employed to etch the top layer and the bottom layer;6. The method of claim 1 , wherein filling the first region includes depositing a planarization layer including a same material as the bottom layer.7. The method of claim 1 , further ...

MULTIPLE PATTERNING SCHEME INTEGRATION WITH PLANARIZED CUT PATTERNING

A method for fabricating a semiconductor device integrating a multiple patterning scheme includes forming a memorization layer over a plurality of mandrels and a plurality of non-mandrels, and applying an exposure scheme to the memorization layer to form at least one mandrel cut pattern and at least one non-mandrel cut pattern. 1. A method for fabricating a semiconductor device integrating a multiple patterning scheme , comprising:forming a memorization layer over a plurality of mandrels and a plurality of non-mandrels; andapplying an exposure scheme to the memorization layer to form at least one mandrel cut pattern and at least one non-mandrel cut pattern.2. The method of claim 1 , further comprising forming the plurality of mandrels from a base structure.3. The method of claim 1 , further comprising forming the plurality of non-mandrels to include a hard mask material having an etch property substantially similar to that of the plurality of mandrels.4. The method of claim 1 , further comprising:forming a spacer layer;performing an etch back of the spacer layer to form gaps between the mandrels;forming the hard mask material in the gaps; andperforming an etch back to form the plurality of non-mandrels.5. The method of claim 1 , wherein the hard mask material includes spin-on-glass (SOG) or spin-on-carbon (SOC).6. The method of claim 1 , wherein applying the exposure scheme to the memorization layer further includes:performing a first lithography exposure to create at least one mandrel cut pattern region;performing a first etch process to remove a first portion of the memorization layer corresponding to the at least one mandrel cut pattern region;performing a second lithography exposure to create at least one non-mandrel cut pattern region;performing a second etch process to remove a second portion of the memorization layer corresponding to the at least one non-mandrel cut pattern region; andforming the cut patterns within the removed portions of the memorization ...

MULTIPLE PATTERNING SCHEME INTEGRATION WITH PLANARIZED CUT PATTERNING

A semiconductor device includes at least one mandrel including a dielectric material, and at least one non-mandrel including a hard mask material having an etch property substantially similar to that of the dielectric material. 1. A semiconductor device comprising:at least one mandrel including a dielectric material; andat least one non-mandrel including a hard mask material having an etch property substantially similar to that of the dielectric material.2. The device of claim 1 , further comprising a hard mask layer claim 1 , wherein the at least one mandrel and the at least one non-mandrel are disposed on the hard mask layer.3. The device of claim 2 , wherein the hard mask layer includes titanium nitride (TiN).4. The device of claim 2 , further comprising a dielectric layer claim 2 , wherein the hardmask layer disposed on the dielectric layer.5. The device of claim 4 , wherein the dielectric layer is an inter-metal dielectric (IMD) layer.6. The device of claim 4 , further comprising a cap layer claim 4 , wherein the dielectric layer is disposed on the cap layer.7. The device of claim 6 , wherein the cap layer is a metal cap layer.8. The device of claim 1 , wherein the dielectric material includes a tetraethyl orthosilicate (TEOS) oxide.9. The device of claim 1 , wherein the hard mask material includes spin-on-glass (SOG) material or a spin-on-carbon (SOC) material.10. The device of claim 9 , wherein the SOG includes a silicon-based SOG material.11. A semiconductor device comprising:a cap layer;a dielectric layer disposed on the cap layer;a hard mask layer disposed on the dielectric layer;at least one mandrel including a dielectric material disposed on the hard mask layer; andat least one non-mandrel including a hard mask material disposed on the hard mask layer, the hard mask material having an etch property substantially similar to that of the dielectric material.12. The device of claim 11 , wherein the hard mask layer includes titanium nitride (TiN).13. The ...

PATTERN FORMING METHOD

A pattern forming method includes forming a guide mask layer including a first feature having a first opening width, a second feature having a second opening width, a third feature having a third opening width. The first width being less than the second width and greater than the third width. A self-organizing material having a phase-separation period is disposed on the guide mask layer to at least partially fill the first, second, and third features. The self-organizing material is process to the cause phase-separation into first and second polymer portions. The first width is greater than the phase-separation period and the third width is less. A masking pattern is formed on the first layer by removing the second polymer portions and leaving the first polymer portions. The masking pattern is then transferred to the first layer. 1. A pattern forming method , comprising:forming a guide mask layer on a first material layer, the guide mask layer including a first pattern feature having a first opening width, a second pattern feature having a second opening width, and a third pattern feature with a third opening width, the first opening width being less than the second opening width and greater than the third opening width;disposing a self-organizing material having a phase-separation period on the guide mask layer to at least partially fill the first, second, and third pattern features in the guide mask layer;processing the self-organizing material disposed on the guide mask layer to cause the self-organizing material to phase separate into first and second polymer portions, the first opening width being greater than or equal to the phase-separation period and the third opening width being less than the phase-separation periodforming a masking pattern on the first material layer by removing the second polymer portions and leaving the first polymer portions; andtransferring the masking pattern to the first material layer.2. The pattern forming method according to claim ...

Semiconductor structure, integrated circuit device, and method of forming semiconductor structure

A semiconductor structure, integrated circuit device, and method of forming semiconductor structure are provided. In various embodiments, the semiconductor structure includes a substrate containing a high topography region and a low topography region, an outer protection wall on an outer peripheral portion of the high topography region next to the low topography region, and an anti-reflective coating over the outer protection wall, the high topography region, and the low topography region.

TREATMENT SOLUTION SUPPLY APPARATUS AND SUBSTRATE TREATMENT SYSTEM

A treatment solution supply apparatus to supply a treatment solution to a treatment solution discharge unit via a supply path that is provided with a filter configured to remove foreign substances in the treatment solution and a tubephragm pump to send the treatment solution, the supply path has an opening/closing valve on an upstream side of the tubephragm pump and the filter, and a suck-back valve on a downstream side of the tubephragm pump and the filter, and includes a control unit to control at least the tubephragm pump, the opening/closing valve, and the suck-back valve, wherein the control unit performs: a control of stopping sending of the treatment solution from the tubephragm pump; and a control of suspending discharge of the treatment solution from the treatment solution discharge unit by operation of the suck-back valve, and then closing the opening/closing valve to stop the discharge. 1. A treatment solution supply apparatus configured to supply a treatment solution to a treatment solution discharge unit via a supply path , the supply path being provided with a filter configured to remove foreign substances in the treatment solution and a tubephragm pump configured to send the treatment solution ,the supply path being provided with an opening/closing valve on an upstream side of the tubephragm pump and the filter, and a suck-back valve on a downstream side of the tubephragm pump and the filter,the treatment solution supply apparatus comprising a control unit configured to control at least the tubephragm pump, the opening/closing valve, and the suck-back valve,wherein the control unit is configured to perform:a control of stopping sending of the treatment solution from the tubephragm pump; anda control of suspending discharge of the treatment solution from the treatment solution discharge unit by operation of the suck-back valve, and then closing the opening/closing valve to stop the discharge.2. The treatment solution supply apparatus according to claim ...

Morphology of Resist Mask Prior to Etching

Embodiments provide a patterning process. A photoresist layer is patterned. At least portions of the photoresist layer are converted from an organic material to an inorganic material by a deposition process of a metal oxide. All or some of the patterned photoresist layer may be converted to a carbon-metal-oxide. A metal oxide crust may be formed over the patterned photoresist layer. After conversion, the patterned photoresist layer is used as an etch mask to etch an underlying layer. 1. A method , comprising:patterning a photoresist layer to form a mask layer, the mask layer comprising an organic material;converting a portion of the mask layer to an inorganic material; andetching a first layer using the mask layer.2. The method of claim 1 , further comprising:before converting the portion of the mask layer, performing a de-scum process, the de-scum process removing material from sidewall portions of the mask layer and removing material from exposed portions of the first layer.3. The method of claim 1 , further comprising:before converting the portion of the mask layer, performing a trim process, the trim process removing material from sidewall surfaces and upper surfaces of the mask layer.4. The method of claim 1 , wherein converting the portion of the mask layer comprises:depositing a metal oxide into the mask layer by an atomic layer deposition (ALD) process.5. The method of claim 1 , wherein converting the portion of the mask layer comprises:altering the mask layer to convert the mask layer to a carbon-metal-oxide material.6. The method of claim 1 , wherein converting the portion of the mask layer comprises:forming a metal oxide crust over the mask layer.7. The method of claim 6 , further comprising:forming a uniform crosslink of a carbon-metal-oxide at an interface of the metal oxide crust and the mask layer.8. The method of claim 1 , wherein converting the portion of the mask layer comprises:forming a carbon-metal-oxide crust at surfaces of the mask layer.9. A ...

Silicon-Containing Layer-Forming Composition, and Method for Producing Pattern-Equipped Substrate Which Uses Same

(where a is an integer of 1 to 5; and a wavy line means that a line which the wavy line intersects is a bond); R2 is each independently a hydrogen atom, a C1-C3 alkyl group, a phenyl group, a hydroxy group, a C1-C3 alkoxy group or a C1-C3 fluoroalkyl group; b is an integer of 1 to 3; m is an integer of 0 to 2; n is an integer of 1 to 3; and a relationship of b+m+n=4 is satisfied.)

SKIP-VIA PROXIMITY INTERCONNECT

A method of forming vias and skip vias is provided. The method includes forming a blocking layer on an underlying layer, and forming an overlying layer on the blocking layer. The method further includes opening a hole in the overlying layer that overlaps the blocking layer, and etching past the blocking layer into the underlying layer to form a second hole that is smaller than the hole in the overlying layer. 1. A method of forming vias and skip vias comprising:forming a blocking layer on an underlying layer;forming an overlying layer on the blocking layer;opening a hole in the overlying layer that overlaps the blocking layer; andetching past the blocking layer into the underlying layer to form a second hole that is smaller than the hole in the overlying layer.2. The method of claim 1 , further comprising filing the hole in the overlying layer and underlying layer with a conductive material to form a via.3. The method of claim 2 , further comprising forming a third hole in the overlying layer and underlying layer that does not intersect the blocking layer.4. The method of claim 3 , wherein the blocking layer is a conductive material selected from the group consisting of copper (Cu) claim 3 , cobalt (Co) claim 3 , aluminum (Al) claim 3 , gold (Au) claim 3 , silver (Ag) claim 3 , tungsten (W) claim 3 , ruthenium (Ru) claim 3 , molybdenum (Mo) claim 3 , tantalum nitride (TaN) claim 3 , titanium nitride (TiN) claim 3 , tantalum carbide (TaC) claim 3 , titanium carbide (TiC)) claim 3 , titanium aluminum (TiAl) claim 3 , graphene claim 3 , carbon nanotubes claim 3 , and combinations thereof.5. The method of claim 3 , wherein the blocking layer includes a plurality of blocking layer sections.6. A method of forming vias and skip vias comprising:forming a patterned resist layer over second metallization layer sections, first metallization layer sections, and an arrangement of conductive lines on a substrate, wherein the patterned resist layer has one or more resist openings ...

EMBEDDED MEMORY WITH IMPROVED FILL-IN WINDOW

Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A memory cell structure is disposed on the memory region. A logic device is disposed on the logic region having a logic gate electrode separated from the substrate by a logic gate dielectric. A sidewall spacer is disposed along a sidewall surface of the logic gate electrode. A contact etch stop layer (CESL) is disposed along an upper surface of the substrate, extending upwardly along and in direct contact with sidewall surfaces of the pair of select gate electrodes within the memory region, and extending upwardly along the sidewall spacer within the logic region. 1. An integrated circuit (IC) comprising:a memory region and a logic region integrated in a substrate;a memory cell structure disposed on the memory region and comprising a pair of control gate electrodes respectively disposed over the substrate and a pair of select gate electrodes disposed on opposite sides of the pair of control gate electrodes;a logic device disposed on the logic region, wherein the logic device comprises a logic gate electrode separated from the substrate by a logic gate dielectric;a sidewall spacer disposed along a sidewall surface of the logic gate electrode; anda contact etch stop layer (CESL) disposed along an upper surface of the substrate, extending upwardly along and in direct contact with sidewall surfaces of the pair of select gate electrodes within the memory region, and extending upwardly along the sidewall spacer within the logic region.2. The IC according to claim 1 , wherein the pair of control gate electrodes and the pair of select gate electrodes comprise polysilicon.3. The IC according to claim 1 , wherein the logic gate electrode comprises polysilicon.4. The IC according to claim 1 , further comprises:an inter-layer dielectric layer disposed on the contact etch stop ...