Антиотражающее оптическое покрытие на основе пористого германия

Изобретение относится к оптической и оптоэлектронной отраслям промышленности и может быть использовано при изготовлении сенсоров изображений, фотодетекторов, солнечных элементов. Антиотражающее оптическое покрытие на основе ионно-имплантированного слоя пористого германия на подложке монокристаллического германия содержит тонкий поверхностный слой пористой структуры германия толщиной 30 нм с ионно-имплантированной примесью индия. Указанный слой выполнен имплантацией подложки монокристаллического германия ионами индия с энергией 5-50 кэВ, дозой облучения 1,0⋅1015-1,8⋅1016 ион/см2 и плотностью тока в ионном пучке 1-15 мкА/см2. Выполненный таким образом слой позволяет предотвратить повышенное отражение от германиевых поверхностей. 2 ил.

ПОДЛОЖКА С МАСКОЙ ДЛЯ ТРАВЛЕНИЯ, ПРОДУКТ, ИЗГОТОВЛЕННЫЙ С ИСПОЛЬЗОВАНИЕМ ПОДЛОЖКИ С МАСКОЙ ДЛЯ ТРАВЛЕНИЯ, СПОСОБ ИЗГОТОВЛЕНИЯ ПОДЛОЖКИ С МАСКОЙ ДЛЯ ТРАВЛЕНИЯ, МАСКА ДЛЯ ТРАВЛЕНИЯ, ПРОДУКТ С НАНЕСЕННЫМ РИСУНКОМ И СПОСОБ ЕГО ИЗГОТОВЛЕНИЯ

... 1. Подложка с маской для травления, содержащая фоточувствительный материал, наносимый на поверхность подложки, причем экспонирование и проявление фоточувствительного материала осуществляют для формирования рисунка в фоторезисте; покрывающую пленку из алмазоподобного углерода, причем покрывающую пленку формируют на поверхности подложки и поверхности рисунка в фоторезисте; рисунок из алмазоподобного углерода, который формируют на поверхности подложки путем отделения покрывающей пленки из алмазоподобного углерода, сформированной на поверхности рисунка в фоторезисте, вместе с рисунком в фоторезисте.2. Подложка с маской для травления по п.1, содержащая, по крайней мере, один из материал, выбранный из группы, включающей Cu, Ag, Al, Au, Pt, Pd, Zn, Mg, Fe, нержавеющую сталь, Ni, Ni-Cr, Sn, Ti, Ti-сплавы, Si, SiO2, стекло, Cr и Мо.3. Подложка с маской для травления по п.1 или 2, содержащая амортизирующий слой, изготовленный из каучука или смолы с буферными свойствами.4. Подложка с маской для травления ...

Verfahren zum Herstellen von Hochfrequenztransistoren

Mikrominiaturisierte, integrierte Halbleiterschaltungsanordnung und Verfahren zu ihrer Herstellung

METHOD OF MAKING A FIELD EFFECT TRANSISTOR WITH INSULATED GATE AND VERY NARROW EFFECTIVE CHANNEL

VERFAHREN ZUM HERSTELLEN VON DYNAMISCHEN HALBLEITER-SPEICHERZELLEN MIT WAHLFREIEM ZUGRIFF (RAM) NACH DER DOPPEL-POLYSILIZIUM-GATE-TECHNOLOGIE

VERFAHREN ZUM HERSTELLEN EINES LATERALTRANSISTORS.

HOCHFREQUENZTRANSISTOR UND VERFAHREN ZU SEINER HERSTELLUNG

Verfahren zur Herstellung einer Halbleitervorrichtung

VERFAHREN ZUR HERSTELLUNG BENACHBARTER MIT DOTIERSTOFFIONEN IMPLANTIERTER WANNEN BEI DER HERSTELLUNG VON HOCHINTEGRIERTEN KOMPLEMENTAEREN MOS-FELDEFFEKTTRANSISTORSCHALTUNGEN

METHOD FOR FORMING SCHOTTKY-BARRIER DIODES

VERFAHREN ZUR HERSTELLUNG VON SOWIE STRUKTUREN FUER VLSI-SCHALTUNGEN MIT HOHER DICHTE

SEMICONDUCTOR MEMORY

VERFAHREN ZUM HERSTELLEN VON HALBLEITERBAUELEMENTEN

Halbleiteranordnung und Verfahren zu seiner Herstellung

SEMICONDUCTOR DEVICES

... 1457800 Semiconductor devices HITACHI Ltd 21 Feb 1974 [24 Feb 1973] 8049/74 Heading H1K MIS device.-An MIS device is made by providing a monocrystalline semiconductor substrate 1, Fig. 1, and a first insulating film 2 covering the substrate 1 and having a hole (3), Fig. 2c, (not shown) exposing the surface of the substrate 1, forming a first conductivity type semiconductor film (4a, 4b) which is monocrystalline in the hole (3) and polycrystalline on the insulating film 2, forming a second insulating film 5 on the semiconductor film (4a, 4b), forming gate electrode material on the second insulating film and removing parts of both to form the gate electrode 7 and to expose parts of the semiconductor film (4a, 4b) on either side of the gate electrode 7, and doping the exposed parts to form second conductivity type first and second regions 8, 9 of monocrystalline semiconductor material forming source and drain regions and third and fourth regions 10a, 10b of polycrystalline semiconductor material ...

SEMICONDUCTOR MANUFACTURING METHOD

Method of forming narrowly spaced flash memory contact openings

A method (210) is provided for creating optical features on a lithography mask for use in patterning a series of openings of an etch mask on a semiconductor device wafer, comprising creating (300,310) a series of optical features spaced on the lithography mask from one another along a first direction, where the individual optical features have first mask feature dimensions along the first direction that are smaller than a desired first dimension for the openings to be patterned in the etch mask.

PRODUCTION OF INTEGRATED MOS CIRCUITS

Semiconductor structures

In a semiconductor structure a masking layer 12 is formed to cover a portion of a surface of a semiconductor 10, a first doped region 36 is formed by ion implantation in a portion of the semiconductor exposed by the masking layer 12, a chemical etchant is brought into contact with the masking layer 12, reducing the area of the masking layer covering the semiconductor and thereby exposing a second, different portion 47 of the semiconductor contiguous to the first exposed portion 36 of the semiconductor, and particles capable of establishing a doped region in the semiconductor layer are introduced by ion implantation into the second exposed portion 47 of the semiconductor to form a second doped region in the semiconductor contiguous to the first doped region, the chemically etched masking layer 12 inhibiting the particles from becoming introduced into the portion of the semiconductor disposed beneath the chemically etched masking layer. With such methods a self- aligned gate region (second ...

FIELD EFFECT TRANSISTORS

Miniature semiconductor device

... 945,741. Semi-conductor devices. TEXAS INSTRUMENTS Inc. Feb. 2, 1960 [Feb. 6, 1959; Feb. 12, 1959], No. 27197/63. Divided out of 945,734. Heading H1K. The subject matter of this Specification is included in Specification 745,734 from which the Specification is divided but the claims relate to a device comprising a monocrystalline semiconductor wafer containing two elongated portions, electrically isolated from each other through the wafer, each having a surface lying on a major face of the wafer and forming a resistive current path substantially parallel to said face between a pair of ohmic contacts attached to opposite ends of said surfaces. Specifications 945,737,945,738,945,739,945,740, 945,742, 945,743, 945,744, 945,745, 945,746, 945,747, 945,748 and 945,749 also are referred to.

Substrate for integrated circuit and forming method thereof

A substrate for an integrated circuit and a forming method thereof are provided. The method includes forming a hard mask layer on a bulk silicon material (1); etching the hard mask layer and the bulk silicon material to form first parts of trenches (4); forming a dielectric film on sidewalls of the trenches; etching the bulk silicon material further, so as to deepen the trenches and form second parts of the trenches; completely oxidizing or nitridizing the bulk silicon material parts positioned between the second parts of trenches and between the second parts of the trenches and the exterior of the bulk silicon substrate; filling the first parts and the second parts of the trenches with dielectric materials (5); and removing the hard mask layer, wherein, the first parts of the trenches is used for achieving shallow trench isolation.

Semiconductor devices and method of making them

... 1,055,724. Semi-conductor devices. RADIO CORPORATION OF AMERICA. March 25, 1964 [April 2, 1963], No. 12712/64. Heading H1K. In a process for diffusing conductivity modifiers into a semi-conductor through apertures in a silicon oxide mask, the mask is removed after the diffusion and the wafer surface then subjected to a cleaning process in which contaminants such as metal ions are removed by a solvent such as hydrogen peroxide. A new oxide mask may be formed, after the cleaning and before depositing metallic electrodes, and left to protect the PN junctions of the completed device. Fig. 9 is a block diagram of the process as used to form a silicon transistor (Fig. 8, not shown). To form a diode, the second diffusion would be omitted. HBr or HNO 3 may replace the HCl in the seventh stage of the process illustrated; and the silicon semi-conductor may be replaced by germanium or a Si-Ge alloy-in which case the silicon oxide coatings would need to be formed by deposition and not by direct oxidation ...

MANUFACTURE OF INTEGRATED CIRCUITS

"Schottky barrier gate field-effect transistor"

In a method of manufacturing a Schottky barrier gate field-effect transistor, an electrically conductive active layer 7 is formed on a semi-insulating semi-conductor substrate 6, two adjacent walls 8, 9 of insulating material are formed on the active layer 7 so as to extend linearly parallel to one another, an ohmic electrode metal is then vacuum-evaporated obliquely with respect to the upstanding surfaces of the two walls 8 and 9 to form ohmic electrodes layers 10, 11 on the active layer 7 in areas except for that lying between the two walls 8, 9, the layer 12 of Schottky barrier metal is subsequently deposited between the two walls 8, 9, whereafter the walls are removed to remove the layers of ohmic electrode metal and Schottky barrier forming metal on the two walls 8, 9. Alternatively the walls are composed of a resist layer and an insulating film, and the resist layer with the electrode metal thereon is removed directly after vacuum-evaporation of the electrode metal. ...

Method of manufacturing an insulated gate field-effect transistor and transistor manufactured using such a method

A method of manufacturing an IGFET device in an entirely self-registering manner, in which on the semi-conductor body a narrow silicon nitride strip is formed which covers only the active region of the body and the width of which is substantially equal to that of the transistors to be manufactured and possibly other circuit elements. This nitride strip is used as a mask for providing the channel stopper zone and as an oxidation mask for providing a first oxide layer. The nitride strip is then etched in which the strip is locally removed over its entire width and only parts remain above the channel region and contact regions which form a second oxidation mask and, in cooperation with the first oxide layer, a doping mask. The source and drain zones of the transistors and possibly further zones, for example underpasses, are formed via said doping mask after which by oxidation a sunken oxide pattern is formed over the whole surface with the exception of the channel regions and the contact regions ...

Method of fabricating semiconductor devices

A semiconductor device is fabricated by forming on the main surface of a semiconductor substrate 1 an inorganic photoresist layer 5 having a first amorphous layer 3, which contains selenium and includes impurity for providing one conductivity type and a second silver or silver containing layer 4 formed on the first layer; exposing the photoresist layer with an exposure pattern; developing the exposed photoresist layer to form a patterned impurity source layer 7; forming a heat resistive overcoating layer to cover the impurity source layer; and whilst it is so covered forming a doped region by diffusing impurity from the impurity source layer into an underlying region of the substrate. The heat resistive overcoating layer may be an insulation layer having a window through which a conductive layer is connected to the doped region. The diffusion of impurity from the impurity source layer into the substrate is accurately controlled without evaporation outside. ...

METHOD FOR MAKING A SEMICONDUCTOR DEVICE

SELF-REGISTERED IGFET STRUCTURE

PROCEDURE FOR THE PRODUCTION OF A SEMICONDUCTOR ARRANGEMENT WITH A SEMICONDUCTOR BODY, SURFACE PARTS OF THE SEMICONDUCTOR BODY BORDERING ZONES OF THE SEMICONDUCTOR BODY DEFINED WITH THAT THE ELECTRICAL CHARACTERISTICS FROM TWO BY MASKS CHANGED

PROCEDURE FOR THE PRODUCTION OF A SEMICONDUCTOR ARRANGEMENT WITH A SEMICONDUCTOR BODY, SURFACE PARTS OF THE SEMICONDUCTOR BODY BORDERING ZONES OF THE HALF OF LEADER BODY DEFINED WITH THAT THE ELECTRICAL CHARACTERISTICS FROM TWO BY MASKS CHANGED

METHOD OF PRODUCING POSITIVE SLOPE STEP CHANGES ON VACUUM DEPOSITED LAYERS

BIPOLAR TRANSISTORS AND METHOD OF MANUFACTURING THE SAME

BIPOLAR TRANSISTORS AND METHOD OF MANUFACTURING THE SAME

In a transistor, around border line of the surface of a base region formed on a semiconductor the surface is formed a base electrode having polycrystalline silicon. An island shape emitter region is formed in the base region and on electrode is formed on the surface of the emitter region. The emitter electrode is electrically isolated from the base electrode by an insulating film extending between the periphery of the emitter region and the base electrode.

SEMICONDUCTOR DEVICE WITH LAYER OF REFRACTORY MATERIAL

The invention relates to a semiconductor device in which a crossing connection is realized by using parts of a layer of refractory conductive material already present for masking as a part of a current conductor separated from a crossing conductor by an insulation layer. The mask of refractory material may also define the regions in which switching transistors are realized. The invention presents important advantages, inter alia in connection with density and crossing connections, in particular in I2L-circuits.

HIGH PERFORMANCE BIPOLAR DEVICE AND METHOD FOR MAKING SAME

HIGH PERFORMANCE BIPOLAR DEVICE AND METHOD FOR MAKING SAME A method for manufacturing a high performance bipolar device and the resulting structure which has a very small emitter-base spacing is described. The small emitter-base spacing, reduces the base resistance compared to earlier device spacing and thereby improves the performance of the bipolar device. The method involves providing a silicon semiconductor body having regions of monocrystalline silicon isolated from one another by isolation regions and a buried subcollector therein. A base region is formed in the isolated monocrystalline silicon. A mask is formed on the surface of the silicon body covering those regions designated to be the emitter and collector reach-through regions. A doped polycrystalline silicon layer is then formed through the mask covering the base region and making ohmic contact thereto. An insulatinq layer is formed over the polysilicon layer. The mask is removed from those regions designated to be the emitter ...

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

PHN 9922 11.11.1981 . Method of manufacturing a semiconductor device. A method of manufacturing an integrated circuit having at least an insulated gate field effect transistor (IGFET). Provided on the silicon surface (2) are successively a gate oxide layer (15) and a doped silicon layer (16) which are patterned by etching by means of a silicon nitride-containing mask (17) which comprises the gate electrode(s) (16A, B) and interconnections (16C). Nitrogen ions are implanted in the surface parts not underlying the mask (17). By thermal oxidation only the edges of the silicon pattern (16) are oxidized. By ion implantation the source and drain zones (23, 24, 27, 28) are formed, the gate electrodes serving as an implantation mask. If desired, the threshold voltage may then be adjusted by ion implantation in the channel region via the gate electrode. The invention is of particular importance for the manufacture of complementary IGFET pairs in which a transistor is provided in a bowl-shaped zone ...

METHOD OF MANUFACTURING A DEVICE IN A SILICON WAFER

A silicon body of a first conductivity type is covered with a sandwich of silicon dioxide, polycrystalline silicon and silicon nitride. Source, drain, and interconnect work sites of the body are exposed by a first photoshaping operation. The work sites are doped forming regions of a second conductivity type. Silicon dioxide is grown over the work sites. A second photoshaping operation provides an opening. The walls of the opening on two opposite sides comprise sides of the sandwich layer as established by the first photoshaping operation and the two remaining walls comprise sides of the silicon dioxide as established by the second photoshaping operation. Silicon nitride is next deposited over the entire wafer which is then photoshaped to define the field regions. The etching process is continued to remove part of the silicon body as well as the sides of those exposed regions. Thereafter, silicon dioxide is grown in the field regions. The remaining silicon nitride layer is removed to reveal ...

METHOD OF MANUFACTURING AN INSULATED GATE FIELD-EFFECT TRANSISTOR USING NARROW SILICON NITRIDE STRIP MASK

PEN.9419 20 A method of manufacturing an IGFET device in an entirely self-registering manner, in which on the semi-conductor body a narrow silicon nitride strip is formed which cover only the active region of the body and the width of which is substantially equal to that of the transistors to be manufactured and possibly other circuit elements. This nitride strip is used as a mask for providing the channel stopper zone and as an oxidation mask for providing a first oxide layer. The nitride strip is then etched in which the strip is locally removed over its entire width and only parts remain above the channel region and contact regions which form a second oxidation mask and, in cooperation with the first oxide layer, a doping mask. The source and drain zones of the transistors and possibly further zones, for example underpasses, are formed via said doping mask after which by oxidation a sunken oxide pattern 18 formed over the whole surface with the exception of the channel regions and the ...

METHOD OF FORMING AN INTEGRATED CIRCUIT REGION THROUGH THE COMBINATION OF ION IMPLANTATION AND DIFFUSION STEPS

A METHOD OF FORMING AN INTEGRATED CIRCUIT REGION THROUGH THE COMBINATION OF ION IMPLANTATION AND DIFFUSION STEPS A region in an integrated circuit substrate is formed by first ion implanting impurities of a selected conductivity-determining type into a semiconductor substrate through at least one aperture in a masking electrically insulative layer, and then diffusing a conductivitydetermining impurity of the same type through the same aperture into said substrate. The method has particular application when the electrically insulative layer is a composite of two layers, e.g., a top layer of silicon nitride and a bottom layer of silicon dioxide and the aperture is thus a pair of registered openings respectively through said silicon nitride and silicon dioxide layers, and the aperture through the silicon dioxide layer has greater lateral dimensions than that in the silicon nitride layer to provide an undercut beneath the silicon nitride ion implantation barrier layer.

PROCESS OF MAKING DUAL WELL CMOS SEMICONDUCTOR STRUCTURE WITH ALIGNED FIELD-DOPINGS USING SINGLE MASKING STEP

PROCESS OF MAKING DUAL WELL CMOS SEMICONDUCTOR STRUCTURE WITH ALIGNED FIELD-DOPINGS USING SINGLE MASKING STEP A process for making a CMOS dual-well semiconductor structure with field isolation doping, wherein only a single lithographic masking step is required for providing self-alignment both of the wells to each other and also of the field isolation doping regions to the wells. The lithographic masking step forms a well mask and defines an oxidation barrier which acts as: an implant mask (absorber) during the ion-implantation of a field dopant of one type; an oxidation barrier over one well during the oxidation of the opposite-type well to form over the one well a sacrificial oxide layer which forms the alignment marks for subsequent formation of the field-doping regions; and a dopant-transmitter during the ion-implanation of an opposite-type field dopant which is simultaneously absorbed by the sacrificial oxide. As a result, there are formed field-doped oxide layers self-aligned to the ...

METHOD OF MANUFACTURING AN FET WHEREIN PART OF A SUNKEN OXIDE LAYER IS REMOVED

HIGH SPEED, HIGH YIELD CMOS/SOS PROCESS

HIGH SPEED HIGH YIELD CMOS/SOS PROCESS The specification discloses a high speed, high yield process for the production of complementary metal-oxide semiconductor devices in silicon on sapphire (CMOS/SOS devices). The process involves providing a wafer comprising a layer of silicon on a sapphire substrate, forming the silicon into several independent islands, masking selected portions of the islands, applying a material to alter the conductivity of the unmasked portions, oxidizing the islands, applying a silicon nitride layer over the surface of the substrate and islands, masking portions of the nitride layer and etching unmasked portions as well as the unmasked oxide layer, applying a second material to the unmasked portions in order to alter the conductivity of the unmasked portions of the islands, oxidizing the islands, selectively masking and etching portions of the oxidized islands, and applying conductors to the exposed portions of the silicon islands to function as contacts. This ...

METHOD OF MANUFACTURING FINE LINE CONDUCTORS ON SEMICONDUCTORS

A method of defining, a fine line low resistivity pattern in a layer of high resistivity polycrystalline semiconductor material present on an insulating layer on the surface of a semiconductor body by lateral impurity diffusion under the edge of a masking layer present on the polycrystalline semiconductor material. The undiffused polycrystalline semiconductor material mayor may not subsequently be removed depending upon the application of the method. In one form the fine line pattern is selectively removed to leave a precisely defined aperture of narrow width in the polycrystalline layer. In one specific embodiment described the method is employed to define high impedance load transistors in a silicon gate integrated circuit. In another specific embodiment described the method is employed to define a compact crossing connection between a polycrystalline silicon line on an oxide layer and an underlying diffused connection region in a silicon gate integrated circuit. Figure 1(c) is suitable ...

METHOD FOR COVERING A FIRST LAYER OR LAYER SEQUENCE SITUATED ON A SUBSTRATE WITH AN ADDITIONAL SECOND LAYER BY A SPUTTERING-ON PROCESS

METHOD OF MAKING SILICONE INTEGRATED CIRCUITS

DUAL RESISTIVITY MOS DEVICES AND METHOD OF FABRICATION

HIGH PERFORMANCE BIPOLAR DEVICE AND METHOD FOR MAKING SAME

THICK OXIDE PROCESS FOR IMPROVING METAL DEPOSITION AND STABILITY OF SEMICONDUCTOR DEVICES

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURED BY MEANS OF THE METHOD

Verfahren zur Herstellung einer elektrischen Glühlampe, deren Kolben auf seiner Innenseite stellenweise mit einem schwarzen Überzug versehen ist

Verfahren zur Erhöhung der Beständigkeit von dihalogentriazingruppenhaltigen Verbindungen

Mit einem Reflexionsschirm versehene, gasgefüllte elektrische Glühlampe

Condensateur

Dispositif semi-conducteur

Verfahren zum Herstellen eines Halbleiterbauelementes mit pn-Übergang und nach diesem Verfahren hergestelltes Halbleiterbauelement

Verfahren zur Herstellung von Halbleiteranordnungen durch Aufwachsen von einkristallinen Schichten

Verfahren zum Herstellen einer Halbleitervorrichtung

Verfahren zum Herstellen von mit Gallium diffundierten Zonen in Halbleiterkristallen

Verfahren zur Herstellung einer Halbleiteranordnung und durch dieses Verfahren hergestellte Halbleiteranordnung

Circuit semi-conducteur microminiature intégré

Circuit microminiature intégré et procédé de fabrication dudit circuit

Dispositif semi-conducteur

Circuit semi-conducteur microminiature intégré

Circuit semi-conducteur microminiature intégré

Circuit semi-conducteur microminiature intégré

Halbleitervorrichtung

Halbleiteranordnung und Verfahren zu deren Herstellung

Selbstausrichtendes Maskierverfahren, insbesondere für Halbleiteroberflächen

PROCEDURE FOR PRODUCING A NARROW GROOVE IN A SUBSTRATE AREA, IN PARTICULAR A SEMICONDUCTOR SUBSTRATE AREA.

PROCEDURE FOR THE PRODUCTION OF AN INTEGRATED CIRCUIT WITH A FIELD-EFFECT TRANSISTOR AND BY A SUCH PROCEDURE MANUFACTURED CIRCUIT.

PROCEDURE FOR MANUFACTURING A SEMICONDUCTOR DEVICE.

MANUFACTORING PROCESS OF JUST BIPOLAR TRANSISTORS OF VERY SMALL DIMENSIONS

MANUFACTORING PROCESS Of a PASTILLE OR SEMICONDUCTOR CHIP

PROCEDE D'OBTENTION D'UNE DIODE DONT LA PRISE DE CONTACT EST AUTO-ALIGNEE A UNE GRILLE

LE PROCEDE SELON L'INVENTION CONSISTE A DEPOSER SUR UN SUBSTRAT SEMI-CONDUCTEUR 9 AU MOINS UNE PREMIERE COUCHE D'UN MATERIAU DIELECTRIQUE 10, 11, A DEPOSER SUR LA DERNIERE COUCHE DIELECTRIQUE 11 UNE PREMIERE COUCHE DE SILICIUM POLYCRISTALLIN 12 POUR FORMER LA GRILLE, PUIS UNE DEUXIEME COUCHE DE SILICIUM POLYCRISTALLIN 13 AU-DESSUS DE LA PREMIERE COUCHE 12, A GRAVER DANS LES COUCHES DE SILICIUM POLYCRISTALLIN 12, 13 L'EMPLACEMENT DE LA DIODE CONTACT JUSQU'A LA MISE A NU DE LA COUCHE DIELECTRIQUE 10, 11, A OXYDER LA DEUXIEME COUCHE DE SILICIUM POLYCRISTALLIN 13 DE MANIERE SUFFISANTE POUR QUE LA COUCHE OXYDEE RECOUVRE ENTIEREMENT LA PREMIERE COUCHE DE SILICIUM POLYCRISTALLIN 13 FORMANT LA GRILLE ET NE RECOUVRE QUE PARTIELLEMENT LA PARTIE MISE A NU DE LA COUCHE DIELECTRIQUE 10, 11, ET A DOPER LA PARTIE DU SUBSTRAT 14 NON RECOUVERTE PAR LA COUCHE D'OXYDE POUR FORMER LA JONCTION DE LA DIODE. APPLICATION : ELEMENTS PHOTOSENSIBLES DES MATRICES A TRANSFERT DE LIGNE.

PROCEDE DE REALISATION SIMULTANEE DE DIFFUSIONS D'ALUMINIUM PROFONDES ET SUPERFICIELLES

LA PRESENTE INVENTION CONCERNE UN PROCEDE DE REALISATION SIMULTANEE DE DIFFUSIONS PROFONDES ET SUPERFICIELLES DANS UN SUBSTRAT DE SILICIUM. CERTAINES ZONES 25 D'UN SUBSTRAT DE SILICIUM SONT COMPLETEMENT MASQUEES PAR UN SANDWICH TRI-COUCHES D'UNE PREMIERE COUCHE DE SILICE THERMIQUE 21, D'UNE SECONDE COUCHE DE NITRURE DE SILICIUM 22 ET D'UNE TROISIEME COUCHE DE SILICE PYROLYTIQUE 23. DANS D'AUTRES ZONES 26, LES SECONDE ET TROISIEME COUCHES 22 ET 23 SONT SUPPRIMEES. DANS D'AUTRES ZONES 27 LES TROIS COUCHES DE PROTECTION SONT SUPPRIMEES. ON OBTIENT AINSI DES DIFFUSIONS PROFONDES AUX EMPLACEMENTS 27 DES DIFFUSIONS SUPERFICIELLES AUX EMPLACEMENTS 26 ET AUCUNE DIFFUSION AUX EMPLACEMENTS 25. APPLICATION NOTAMMENT AUX STTRUCTURES A CAISSONS.

MANUFACTORING PROCESS OF TRANSISTORS

PROGRAMMABLE MEMORY OF READING AND ITS MANUFACTORING PROCESS

ITIF OBTENU

... a. Procédé de fabrication d'un dispositif à transfert de charges et dispositif connu. b. Procédé caractérisé en ce qu'on forme une seconde couche de masquage pour enlever sélectivement la couche de silicium polycristalhn, on diffuse sélectivement une impureté de dopage dans la couche de silicium polycristallin à travers la première couche de masquage, on enlève sélectivement la couche de silicium polycristallin avec une première et une seconde couches de masquage et on forme des ouvertures dans la couche de silicium polycristallin et on diffuse sélectivement une impureté de dopage dans le substrat à travers les ouvertures.

MATRICE A SEMI-CONDUCTEURS POUR MEMOIRE PERMANENTE A CIRCUITS INTEGRES

Matrice à semi-conducteurs pour mémoire permanente intégrée, composée d'éléments comportant une région d'un premier type de conductivité, dans lequel, au moins dans une partie des éléments, une région 5 du second type de conductivité étant prévue dans au moins une partie de ces éléments, ceux-ci étant formés à l'intersection de barres semi-conductrices 2 du premier type de conductivité réalisées dans le substrat, et de barres métalliques 3 disposées sur une couche diélectrique 4 qui isole les barres semi-conductrices des barres métalliques, des fenêtres étant prévues dans la couche diélectrique au-dessus des régions 5 du second type de conductivité, au moins une partie de ces fenêtres comportant des ouvertures 6 assurant le contact électrique entre les régions semi-conductrices 5 du second type de conductivité avec les barres métalliques, ladite matrice étant caractérisée en ce que les régions 5 du second type de conductivité ne sont associées qu'aux éléments, au-dessus desquels sont pratiquées ...

PROCEDE DE FABRICATION DE TRANSISTOR BIPOLAIRE LATERAL AUTO-ALIGNE

PROCEDE DE FABRICATION D'UN TRANSISTOR BIPOLAIRE LATERAL ORIENTE EN SURFACE PRESENTANT UNE BASE DE FAIBLE LARGEUR. ON UTILISE, POUR CETTE FABRICATION, UNE COUCHE DE SILICIUM POLYCRISTALLIN 26 NON DOPE COMME MASQUE D'IMPLANTATION IONIQUE LORS DE L'IMPLANTATION D'IONS POUR LES REGIONS D'EMETTEUR ET DE BASE. POUR FORMER LE MASQUE DE POLYSILICIUM DOPE, ON FORME UNE PREMIERE COUCHE 24 DE MATERIAU DE MASQUE DE DOPAGE SUR LA SURFACE D'UNE SUBSTRAT SEMI-CONDUCTEUR 12, PUIS UNE SECONDE COUCHE DE POLYSILICIUM NON DOPE 26 SUR LA PREMIERE COUCHE 24 ET ENFIN UNE TROISIEME COUCHE 28 DE MATERIAU DE MASQUE DE DOPAGE SUR LA SECONDE COUCHE 26. DES PARTIES DES SECONDE ET TROISIEME COUCHES 26, 28 SONT ELIMINEES ET L'ON DIFFUSE UNE IMPURETE DE DOPAGE DANS LA PARTIE MARGINALE EXPOSEE DE LA SECONDE COUCHE 26. LA TROISIEME COUCHE 28 ET LA PARTIE NON DOPEE DE LA SECONDE COUCHE 26 SONT ALORS ELIMINEES, CE QUI NE LAISSE SUBSISTER QUE LA PARTIE DOPEE DE LA SECONDE COUCHE 26 SUR LA PREMIERE COUCHE 24. APPLICATION A ...

METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

PROCEEDED Of OBTAINING a DIODE WHOSE MAKING OF CONTACT EAST AUTO-ALIGNEE HAS a GRID

Manufacture of semiconductor devices

MANUFACTORING PROCESS OF DEVICES HAS FIELD-EFFECT TRANSISTORS AND DEVICES WHILE RESULTING

PROCEDE DE FABRICATION D'UN INVERSEUR CMOS FORME DE DEUX TRANSISTORS EMPILES ET AUTO-ALIGNES PAR RAPPORT A LA GRILLE DE L'INVERSEUR

L'INVENTION CONCERNE UN PROCEDE DE FABRICATION D'UN INVERSEUR CMOS. CE PROCEDE CONSISTE A RECOUVRIR UN SUBSTRAT EN SILICIUM DE TYPE P 2 D'UNE PREMIERE COUCHE DE SILICE 4, A REALISER SUR LA PREMIERE COUCHE DE SILICE 4, DANS UNE PREMIERE COUCHE DE POLYSILICIUM DE TYPE N 6, LA GRILLE DE L'INVERSEUR, A RECOUVRIR LA PREMIERE COUCHE DE POLYSILICIUM 6 D'UNE SECONDE COUCHE DE SILICE 8, A REALISER SUR LA SECONDE COUCHE DE SILICE 8, DANS UNE SECONDE COUCHE DE POLYSILICIUM DE TYPE N- 10, LE TRANSISTOR MOS A CANAL P, PUIS A REALISER DANS LE SUBSTRAT EN SILICIUM DE TYPE P 2 LE TRANSISTOR MOS A CANAL N DE FACON QUE LES SOURCES 20, 26 ET LES DRAINS 22, 28 DES DEUX TRANSISTORS MOS SOIENT AUTO-ALIGNES PAR RAPPORT A LA GRILLE DE L'INVERSEUR, ET A REALISER LES DIFFERENTS CONTACTS 44 ET CONNEXIONS ELECTRIQUES DE L'INVERSEUR.

TRANSISTORS BIPOLAR AND MANUFACTORING PROCESS

PROCESS the SELF-ALIGNING one OF AREAS DIFFERENTLY DOPEES Of a STRUCTURE OF SEMICONDUCTOR

Device semiconductor and manufactoring process of such a device

METHOD FOR MANUFACTURING A STORAGE CELL A TRANSISTOR HAS

Of a BOX AND POSSIBLY ELECTRIC ZONE MANUFACTORING PROCESS Of INSULATION Of an INTEGRATED CIRCUIT, IN PARTICULAR OF TYPE MOS

METHOD FOR REALIZATION Of a THROAT OR NARROW SLIT IN an AREA OF SUBSTRATE IN PARTICULAR a SEMICONDUCTOR AREA OF SUBSTRATE

PROCESS OF TREATMENT OF ZONES COMPLEMENTARY TO the SURFACE Of a SUBSTRATE AND SEMICONDUCTOR PRODUCT OBTAINED BY THIS PROCESS

L'invention concerne un procédé de traitement d'une portion de la surface (2) d'un substrat selon un premier et un deuxième traitements de surface différents l'un de l'autre et destinés respectivement à un premier groupe de zones (3a) et à un deuxième groupe de zones (3b) de ladite portion de surface (2), ces deux groupes de zones étant complémentaires l'un de l'autre par rapport à ladite portion, le procédé permettant de ne mettre en oeuvre qu'une seule opération de positionnement d'un masque qui différencie les zones des premier et deuxième groupes de zones, en utilisant les mêmes matériaux de protection pour les zones de chaque groupe de zones contre les effets du traitement destiné aux zones de l'autre groupe de zones. Application à l'obtention de produits semi-conducteurs.

Rapid diode, transistor, thyristor and Zener diode mfr. - using a reinforcing layer of polycrystalline silicon

Rapid diode, transistor, thyristor and Zener diode mfr. - using a reinforcing layer of polycrystalline silicon

PROCESS Of AUTOALIGNEMENT OF the ELEMENTS Of a SEMICONDUCTOR DEVICE AND DEVICE CARRIED out FOLLOWING THIS PROCESS

Method of pitch dimension shrinkage

An embodiment of the disclosure includes a method of pitch reduction. A substrate is provided. A first material layer is formed over the substrate. A second material layer is formed on the first material layer. A hardmask layer is formed on the second material layer. A first imaging layer is formed on the hardmask layer. The first imaging layer is patterned to form a plurality of first features over the hardmask layer. The hardmask layer is etched utilizing the first imaging layer as a mask to form the first features in the hardmask layer. The first imaging layer is removed to expose the etched hardmask layer and a portion of a top surface of the second material layer. A second imaging layer is formed and the process is repeated, such that first and second features are alternating with a pitch substantially half the original pitch.

Apparatus and method for conformal mask manufacturing

A manufacturing process technology creates a pattern on a first layer using a focused ion beam process. The pattern is transferred to a second layer, which may act as a traditional etch stop layer. The pattern can be formed on the second layer without irradiation by light through a reticle and without wet chemical developing, thereby enabling conformal coverage and very fine critical feature control. Both dark field patterns and light field patterns are disclosed, which may enable reduced or minimal exposure by the focused ion beam.

Method of manufacturing a semiconductor device

A method of manufacturing a semiconductor device includes: forming a thin film on a substrate; forming a resist mask which forms a photoresist mask having an elliptical hole pattern on the thin film; shrinking a hole size of the second pattern by forming an insulating film on a side wall of the second pattern of the photoresist layer; and etching the thin film using the insulating film and the photoresist layer which form the second pattern having the shrinked hole size as a mask.

Method for manufacturing porous structure and method for forming pattern

A pattern forming material contains a block copolymer or graft copolymer and forms a structure having micro polymer phases, in which, with respect to at least two polymer chains among polymer chains constituting the block copolymer or graft copolymer, the ratio between N/(Nc−No) values of monomer units constituting respective polymer chains is 1.4 or more, where N represents total number of atoms in the monomer unit, Nc represents the number of carbon atoms in the monomer unit, No represents the number of oxygen atoms in the monomer unit.

Spacer double patterning that prints multiple cd in front-end-of-line

A semiconductor device is formed with sub-resolution features and at least one additional feature having a relatively larger critical dimension using only two masks. An embodiment includes forming a plurality of first mandrels, having a first width, and at least one second mandrel, having a second width greater than the first width, overlying a target layer using a first mask, forming sidewall spacers along the length and width of the first and second mandrels, forming a filler adjacent each sidewall spacer, the filler having the first width, removing the filler adjacent sidewall spacers along the widths of the first and second mandrels using a second mask, removing the sidewall spacers, and etching the target layer between the filler and the first and second mandrels, thereby forming at least two target features with different critical dimensions. Embodiments further include using a third mask to form a semiconductor device having further features with a different critical dimension, but the same pitch, as the sub-resolution features.

Methods Of Forming Patterns, And Methods Of Forming Integrated Circuits

Some embodiments include methods of forming patterns in substrates by utilizing block copolymer assemblies as patterning materials. A block copolymer assembly may be formed over a substrate, with the assembly having first and second subunits arranged in a pattern of two or more domains. Metal may be selectively coupled to the first subunits relative to the second subunits to form a pattern of metal-containing regions and non-metal-containing regions. At least some of the block copolymer may be removed to form a patterned mask corresponding to the metal-containing regions. A pattern defined by the patterned mask may be transferred into the substrate with one or more etches. In some embodiments, the patterning may be utilized to form integrated circuitry, such as, for example, gatelines.

Contact formation method incorporating a preventative etch step for reducing interlayer dielectric material flake defects

Disclosed are embodiments of a contact formation technique that incorporates a preventative etch step to reduce interlayer dielectric material flaking (e.g., borophosphosilicate glass (BPSG) flaking) and, thereby to reduce surface defects. Specifically, contact openings, which extend through a dielectric layer to semiconductor devices in and/or on a center portion of a substrate, can be filled with a conductor layer deposited by chemical vapor deposition (CVD). Chemical mechanical polishing (CMP) of the conductor layer can be performed to complete the contact structures. However, before the CMP process is performed (e.g., either before the contact openings are ever formed or before the contact openings are filled), a preventative etch process can be performed to remove any dielectric material from above the edge portion of the substrate. Removing the dielectric material from above the edge portion of the substrate prior to CMP reduces the occurrence of surface defects caused by dielectric material flaking.

Self aligned triple patterning

Embodiments of the present invention pertain to methods of forming features on a substrate using a self-aligned triple patterning (SATP) process. A stack of layers is patterned near the optical resolution of a photolithography system using a high-resolution photomask. The heterogeneous stacks are selectively etched to undercut a hard mask layer beneath overlying cores. A dielectric layer, which is flowable during formation, is deposited and fills the undercut regions as well as the regions between the heterogeneous stacks. The dielectric layer is anisotropically etched and a conformal spacer is deposited on and between the cores. The spacer is anisotropically etched to leave two spacers between each core. The cores are stripped and the spacers are used together with the remaining hard mask features to pattern the substrate at triple the density of the original pattern.

Methods for Pitch Reduction

An integrated circuit described herein includes a substrate and a plurality of lines overlying the substrate. The lines define a plurality of first trenches and a plurality of second trenches. The plurality of first trenches extend into the substrate a distance different than that of the plurality of second trenches. Adjacent pairs of lines are separated by a first trench in the plurality of first trenches, and each pair of lines comprises a first line and a second line defining a corresponding second trench in the plurality of second trenches.

Concave-convex pattern forming method and magnetic tunnel junction element forming method

A method of forming a concave-convex pattern according to an embodiment includes: forming a guide pattern on a base material, the guide pattern having a convex portion; forming a formative layer on the guide pattern, the formative layer including a stacked structure formed by stacking a first layer and a second layer, the first layer including at least one element selected from a first metal element and a metalloid element, the second layer including a second metal element different from the first metal element; selectively leaving the formative layer only at side faces of the convex portions by performing etching on the formative layer; removing the guide pattern; and forming the concave-convex pattern in the base material by performing etching on the base material, with the remaining formative layer being used as a mask.

Methods of forming fine patterns and methods of fabricating semiconductor devices

Method of forming fine patterns and methods of fabricating semiconductor devices by which a photoresist (PR) pattern may be transferred to a medium material layer with a small thickness and a high etch selectivity with respect to a hard mask to form a medium pattern and the hard mask may be formed using the medium pattern. According to the methods, the PR pattern may have a low aspect ratio so that a pattern can be transferred using a PR layer with a small thickness without collapsing the PR pattern.

Photomask and formation method thereof

A method for forming a photomask includes detecting a defect of the photomask which has a mirror layer formed on a first surface of a substrate, and forming a recess groove on a first layer which is formed on a second surface of the substrate, wherein the coordinate of the recess groove corresponds to the coordinate of the defect.

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device including a plurality of hole patterns is disclosed. The method includes: forming a plurality of first line patterns and a plurality of first space patterns extending in a first direction; forming a plurality of second line patterns and a plurality of second space patterns extending in a second direction, on the plurality of first line patterns and the plurality of first space patterns; forming a plurality of first hole patterns where the plurality of first space patterns and the plurality of second space patterns cross each other; and forming a plurality of second hole patterns where the plurality of first line patterns and the plurality of second line patterns cross each other.

Method of forming photomask using calibration pattern, and photomask having calibration pattern

A method of forming a photomask using a calibration pattern that may exactly transfer a desired pattern to a substrate. The method includes providing one-dimensional calibration design patterns each having first design measures and providing two-dimensional calibration design patterns each having second design measures; obtaining one-dimensional calibration measured patterns using the one-dimensional calibration design patterns and obtaining two-dimensional calibration measured patterns using the two-dimensional calibration design patterns; obtaining first measured measures of the one-dimensional calibration measured patterns and obtaining second measured measures of the two-dimensional calibration measured patterns; establishing a correlation between the first measured measures and the second measured measures; and converting a main measured measure of a main pattern into a corresponding one of the first measured measures using the correlation.

Integrated circuit fabrication methods utilizing embedded hardmask layers for high resolution patterning

Embodiments of a method for fabricating integrated circuits are provided. In one embodiment, the method includes the steps of depositing a dielectric layer over a semiconductor device, forming a plurality of trimmed hardmask structures at predetermined locations over the dielectric layer, embedding the plurality of trimmed hardmask structures in a surrounding hardmask layer, removing the plurality of trimmed hardmask structures to create a plurality of openings through the surrounding hardmask layer, and etching the dielectric layer through the plurality of openings to form a plurality of etch features therein.

Multiple Patterning Method

An integrated circuit memory comprises a set of lines each line having parallel X direction line portions in a first region and Y direction line portions in a second region. The second region is offset from the first region. The lengths of the X direction line portions are substantially longer than the lengths of the Y direction line portions. The X direction and Y direction line portions have respective first and second pitches with the second pitch being at least 3 times larger than the first pitch. Contact pickup areas are at the Y direction line portions. In some examples, the lines comprise word lines or bit lines. The memory can be created using multiple patterning methods to create lines of material and then the parallel X direction line portions and parallel Y direction line portions.

Methods for fabricating semiconductor devices and semiconductor devices using the same

A method for fabricating a fine pattern of a semiconductor device is provided. The method includes forming a base layer, a first mask pattern having identical features of a first width with inclined sidewalls and a second mask pattern having identical features of a second width in sequence on a substrate, wherein a smallest distance between any two adjacent inclined sidewalls is equal to the second width. The base layer is etched by using the first mask pattern as an etch mask to form first openings of the second width and a fill layer is formed covering the substrate. The second mask pattern is removed to form second openings in the fill layer and then the first mask pattern and the base layer are etched through the second openings to form third openings. The fill layer and the first mask pattern are removed to form a pattern of the base layer having identical features of a third width, wherein the third width of the features of the base layer pattern is equal to the second width.

Mask and method of manufacturing array substrate using the same

A mask includes: a substrate that includes a central area and a peripheral area disposed around the central area; and lenses disposed in rows and columns, in the central area and the peripheral area. The lenses of opposing sides of the peripheral area may be disposed in different rows or columns. For a given amount of input light, the lenses of the peripheral area may focus less light on a substrate than the lenses of the central area. The mask may be disposed over the substrate in different positions, and then the substrate may be irradiated through the mask, while the mask is in each of the positions. The peripheral portion of the mask may be disposed over the same area of the substrate, while the mask is in different ones of the positions.

Substrate processing method

The present invention provides a substrate processing method to process a substrate including at least a process layer, an intermediate layer, and a mask layer which are stacked in this order. The mask layer includes an aperture configured to expose a portion of the intermediate layer. The substrate processing method includes a material deposition step of depositing a material on a side surface of the aperture and exposing a portion of the process layer by etching the exposed portion of the intermediate layer by plasma generated from a deposit gas, and an etching step of etching the exposed portion of the process layer.

Method for fabricating carbon hard mask and method for fabricating patterns of semiconductor device using the same

A method for fabricating a carbon hard mask layer includes: loading a substrate with a pattern target layer into a chamber; performing a primary thermal treatment on the substrate; depositing a carbon hard mask layer over the pattern target layer by using C x H y gas to perform the primary thermal treatment; performing a secondary thermal treatment on the substrate on which the carbon hard mask layer is deposited; and performing an oxygen treatment on the carbon hard mask layer.

Shrinkage of Critical Dimensions in a Semiconductor Device by Selective Growth of a Mask Material

In sophisticated semiconductor devices, manufacturing techniques and etch masks may be formed on the basis of a mask layer stack which comprises an additional mask layer, which may receive an opening on the basis of lithography techniques. Thereafter, the width of the mask opening may be reduced by applying a selective deposition or growth process, which thus results in a highly uniform and well-controllable adjustment of the target width of the etch mask prior to performing the actual patterning process, for instance for forming sophisticated contact openings, via openings and the like.

Memory device comprising an array portion and a logic portion

In an embodiment of the present invention, a method comprises patterning a first plurality of semiconductor structures in an array portion of a semiconductor substrate using a first photolithographic mask. The method further comprises patterning a second plurality of semiconductor structures over a logic portion of a semiconductor substrate using a second photolithographic mask. The method further comprises patterning a sacrificial layer over the first plurality of semiconductor structures using the second photolithographic mask. The sacrificial layer is patterned simultaneously with the second plurality of semiconductor structures.

Hardmask materials

Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about −600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of Si x B y C z , Si x B y N z , Si x B y C z N w , B x C y , and B x N y . In some embodiments, a hardmask film includes a germanium-rich GeN x material comprising at least about 60 atomic % of germanium. These hardmasks can be used in a number of back-end and front-end processing schemes in integrated circuit fabrication.

Etch with high etch rate resist mask

A method for etching features into an etch layer is provided. A patterned mask is formed over the etch layer, wherein the patterned mask is of a high etch rate photoresist material, wherein the patterned mask has patterned mask features. A protective layer is deposited on the patterned mask of high etch rate photoresist material by performing a cyclical deposition, wherein each cycle, comprises a depositing phase for depositing a deposition layer over the exposed surfaces, including sidewalls of the patterned mask of high etch rate photoresist material and a profile shaping phase for providing vertical sidewalls. Features are etched into the etch layer using the protective layer as a mask. The protective layer is removed.

Semiconductor device manufacturing apparatus

A semiconductor device manufacturing apparatus includes: a first pattern forming unit for forming a first pattern by patterning a first mask material layer; a boundary layer forming unit for forming a boundary layer at sidewall portions and top portions of the first pattern; a second mask material layer forming unit for forming a second mask material layer so as to cover a surface of the boundary layer; a second mask material removing unit for removing a part of the second mask material layer to expose top portions of the boundary layer; a boundary layer etching unit for forming a second pattern by etching and removing the boundary layer and forming a void between the sidewall portions of the first pattern and the second mask material layer; and a trimming unit for reducing a width of the first pattern and a width of the second pattern to predetermined widths.

Method of fabricating gate elctrode using a treated hard mask

A hard mask layer with a limited thickness is formed over a gate electrode layer. A treatment is provided on the hard mask layer to transform the hard mask layer to be more resistant to wet etching solution. A patterning is provided on the treated hard mask layer and the gate electrode to from a gate structure.

Semiconductor device manufacturing method

In a semiconductor device manufacturing method, on a film to be processed, a mask material film is formed which has pattern openings for a plurality of contact patterns and connection openings for connecting adjacent pattern openings in such a manner that the connection between them is constricted in the middle. Then, a sidewall film is formed on the sidewalls of the individual openings in the mask material film, thereby not only making the diameter of the pattern openings smaller but also separating adjacent pattern openings. Then, the film to be processed is selectively etched with the mask material film and sidewall film as a mask, thereby making contact holes.

Method of forming fine pattern and method of manufacturing semiconductor device

A method of forming a fine pattern and a method of manufacturing a semiconductor device. The method of forming a fine pattern includes: forming a hard mask layer on a to-be-etched layer; forming on the hard mask layer a first mask pattern including a plurality of elongated openings that are arranged at predetermined intervals in a first direction and a second direction different from the first direction and are offset from each other in adjacent columns in the second direction; forming on the hard mask layer a second mask pattern including at least two linear openings that each pass through the elongated openings in the adjacent columns and extend in the first direction; forming a hard mask pattern by etching the hard mask layer by using the second mask pattern as an etch mask; and etching the to-be-etched layer by using the hard mask pattern.

Method of making a semiconductor device

An improved method of making interconnect structures with self-aligned vias in semiconductor devices utilizes sidewall image transfer to define the trench pattern. The sidewall height acts as a sacrificial mask during etching of the via and subsequent etching of the trench, so that the underlying metal hard mask is protected. Thinner hard masks and/or a wider range of etch chemistries may thereby be utilized.

Plasma etching method, control program and computer storage medium

A plasma etching method, for plasma-etching a target substrate including at least a film to be etched, an organic film to become a mask of the to-be-etched film, and a Si-containing film which are stacked in order from bottom, includes the first organic film etching step, the treatment step and the second organic film etching step when the organic film is etched to form a mask pattern of the to-be-etched film. In the first organic film etching step, a portion of the organic film is etched. In the treatment step, the Si-containing film and the organic film are exposed to plasma of a rare gas after the first organic film etching step. In the second organic film etching step, the remaining portion of the organic film is etched after the treatment step.

Photomask making method, photomask blank and dry etching method

A photomask is manufactured by providing a photomask blank comprising a transparent substrate, a phase shift film, and a light-shielding film, the phase shift film and the light-shielding film including silicon base material layers, a N+O content in the silicon base material layer of the phase shift film differing from that of the light-shielding film, and chlorine dry etching the blank with oxygen-containing chlorine gas in a selected O/Cl ratio for selectively etching away the silicon base material layer of the light-shielding film.

Method for Reducing a Minimum Line Width in a Spacer-Defined Double Patterning Process

The invention discloses a method for reducing a minimum line width in a spacer-defined double patterning process of the present invention. In the method, the silicon nitride spacers can be converted into trenches in the interlayer dielectric layer by using a silicon dioxide film as a mask and by means of a chemically mechanical polishing process and an etching process, so that the minimum line width of the trenches can be determined by the width of the silicon nitride spacers, and thus a smaller line width can be achieved and the process can be simple and easy to control.

Apparatus and method for conformal mask manufacturing

A manufacturing process technology creates a pattern on a first layer using a focused ion beam process. The pattern is transferred to a second layer, which may act as a traditional etch stop layer. The pattern can be formed on the second layer without irradiation by light through a reticle and without wet chemical developing, thereby enabling conformal coverage and very fine critical feature control. Both dark field patterns and light field patterns are disclosed, which may enable reduced or minimal exposure by the focused ion beam.

Semiconductor device and method of manufacturing the same

A semiconductor device having a conductive pattern includes a plurality of conductive lines extending in parallel, each having a first region extending in a first direction and a second region coupled to the first region and extending in a second direction crossing the first direction, and a plurality of contact pads, each coupled to a respective conductive line of the second regions, wherein the conductive lines are grouped and arranged in a plurality of groups, the first region of a first group is longer than the first region of a second group, and the second region of the first group and the second region of the second group are spaced apart from each other.

Lithographic Method for Making Networks of Conductors Connected by Vias

A method of lithography for formation of two networks of conductors connected by vias in microelectronic integrated circuits comprises, after formation of a first network of buried conductors under an insulating layer: deposition and etching of a sacrificial layer on a substrate, formation of spacers along all edges of elements of the sacrificial layer; removal of this layer; etching of a masking layer. Then, two successive etchings of the insulating layer are carried out, over two successive depths, one defining the depth of the conductors of the second network, the other defining a complement of depth needed at the desired locations for the vias. One of the etchings is defined by the masking layer and corresponds to the locations of the conductors of the second network; the other is defined both by the spacers and by openings in a layer etched by lithography and corresponds to the locations of the vias. Lastly, following the two etchings, the regions etched into the insulating material of the substrate are filled with a conductive material which forms the conductors and the vias at the same time.

APPARATUS FOR THE DEPOSITION OF A CONFORMAL FILM ON A SUBSTRATE AND METHODS THEREFOR

A method for depositing a conformal film on a substrate in a plasma processing chamber of a plasma processing system, the substrate being disposed on a chuck, the chuck being coupled to a cooling apparatus, is disclosed. The method includes flowing a first gas mixture into the plasma processing chamber at a first pressure, wherein the first gas mixture includes at least carbon, and wherein the first gas mixture has a condensation temperature. The method also includes cooling the chuck below the condensation temperature using the cooling apparatus thereby allowing at least some of the first gas mixture to condense on a surface of the substrate. The method further includes venting the first gas mixture from the processing chamber; flowing a second gas mixture into the plasma processing chamber, the second gas mixture being different in composition from the first gas mixture; and striking a plasma to form the conformal film. 1. An apparatus for depositing a conformal film on a substrate in a plasma processing chamber of a plasma processing system , said substrate being disposed on a chuck , said chuck being coupled to a cooling apparatus , comprising:means of flowing a first gas mixture into said plasma processing chamber at a first pressure, wherein said first gas mixture includes at least carbon, and wherein said first gas mixture has a condensation temperature;means of cooling said chuck below said condensation temperature using said cooling apparatus thereby allowing at least some of said first gas mixture to condense on a surface of said substrate;means of venting said first gas mixture from said processing chamber;means of flowing a second gas mixture into said plasma processing chamber, said second gas mixture being different in composition from said first gas mixture; andmeans of striking a plasma to form said conformal film.2. The apparatus of claim 1 , wherein said second gas mixture is at a second pressure.3. The apparatus of claim 2 , wherein said second ...

PATTERN FORMING METHOD

The invention provides a pattern-formation process comprising a step of providing a substrate material having on a major surface a difficult-to-access recess formed by the presence of a 1mask, a step of using a physical evaporation method to deposit a 2mask-formation material, which is higher than the 1mask in terms of etching resistance, from a side having the 1mask formed on it all over the upper surface of the 1mask and peripherally on a side of the difficult-to-access recess to form the 2mask comprising a series of films, and a step of etching the substrate material via the 1mask and the 2mask, wherein the 2mask-formation step comprises operation of flying the 2mask-formation material by the physical evaporation method vertically to the major surface of the substrate material, and the difficult-to-access recess is sized such that when the 2mask-formation material is flown and deposited by the physical evaporation method vertically to the major surface of the substrate material, the 2mask-formation material cannot substantially reach down to the bottom of the recess. With the inventive process, portions of the difficult-to-access recesses formed by the presence of the etching masks in a site to be etched can be processed by etching even when those recesses are 25 nm or less, and especially 20 nm or less in size. 1. A pattern-formation process , comprising:{'sup': 'st', 'a step of providing a substrate material having on a major surface a difficult-to-access recess formed by the presence of a 1mask,'}{'sup': nd', 'st', 'st', 'nd, 'a step of using a physical evaporation method to deposit a 2mask-formation material, which is higher than said 1mask in terms of etching resistance, all over an upper surface of said 1mask and peripherally on a side of said difficult-to-access recess to form a 2mask comprising a series of films, and'}{'sup': st', 'nd, 'a step of etching said substrate material via said 1mask and said 2mask, wherein{'sup': nd', 'nd, 'said 2mask-formation ...

Multi-layer pattern for alternate ald processes

A method of patterning a substrate. A sacrificial film is formed over a substrate and a pattern created therein. A first spacer layer is conformally deposited over the patterned sacrificial film and at least one horizontal portion of the first spacer layer is removed while vertical portions of the first spacer layer remain. A second spacer layer is conformally deposited over the patterned sacrificial film and the remaining portions of the first spacer layer. At least one horizontal portion of the second spacer layer is removed while vertical portions of the second spacer layer remain. Conformal deposition of the first and second spacer layers is optionally repeated one or more times. Conformal deposition of the first layer is optionally repeated. Then, one of the first or second spacer layers is removed while substantially leaving the vertical portions of the remaining one of the first or second spacer layers.

PROCESS FOR IMPROVING CRITICAL DIMENSION UNIFORMITY OF INTEGRATED CIRCUIT ARRAYS

Methods for patterning integrated circuit (IC) device arrays employing an additional mask process for improving center-to-edge CD uniformity are disclosed. In one embodiment, a repeating pattern of features is formed in a masking layer over a first region of a substrate. Then, a blocking mask is applied over the features in the masking layer. The blocking mask is configured to differentiate array regions of the first region from peripheral regions of the first region. Subsequently, the pattern of features in the array regions is transferred into the substrate. In the embodiment, an etchant can be uniformly introduced to the masking layer because there is no distinction of center/edge in the masking layer. Thus, CD uniformity can be achieved in arrays which are later defined. 1. A method for forming memory device arrays , comprising:forming a repeating pattern of features on a first level extending across two or more array regions of a substrate;applying a protective mask over portions of the repeating pattern, the protective mask covering the two or more array regions and exposing non-array regions within the first region between the array regions, thereby exposing portions of the features in the non-array regions; andremoving the exposed portions of the features in the non-array regions while the protective mask covers the plurality of array regions.2. The method of claim 1 , wherein the protective mask comprises a blocking photoresist.3. The method of claim 1 , wherein the repeating pattern of features are a part of the substrate.4. The method of claim 3 , wherein the part of the substrate comprises a material selected from the group consisting of a metal and a semiconductor.5. The method of claim 1 , wherein the repeating pattern of features comprises amorphous carbon.6. The method of claim 1 , wherein the first layer comprises an oxide.7. The method of claim 1 , wherein the oxide is SiO.8. An intermediate integrated circuit structure claim 1 , comprising:a ...

Package carrier, package carrier manufacturing method, package structure for semiconductor device and manufacturing method thereof

A package substrate including a dielectric layer, a first conductive layer, a second conductive layer and a bonding pad is provided. The dielectric layer has a top surface and a bottom surface. The first conductive layer is embedded into the dielectric layer, and a first surface of the first conductive layer is exposed from the top surface and has the same plane with the top surface. The second conductive layer is embedded into the dielectric layer and contacts the first conductive layer, and a second surface of the second conductive layer is exposed from the bottom surface and has the same plane with the bottom surface. The bonding pad is partially or completely embedded into the first conductive layer and the dielectric layer, so that the periphery of the bonding pad is confined within a cavity by the sidewalls of both the first conductive layer and the dielectric layer.

Pattern forming method and manufacturing method of semiconductor device

A disclosed manufacturing method of a semiconductor device includes laminating a substrate, an etched film, an anti-reflective coating film, and a resist film; forming a pattern made of the resist film using a photolithographic technique; forming the third mask pattern array by a mask pattern forming method; and a seventh step of forming a fourth mask pattern array by processing the etched film using the third mask pattern array.

Reverse Tone STI Formation

A method includes forming a hard mask over a substrate, patterning the hard mask to form a first plurality of trenches, and filling a dielectric material into the first plurality of trenches to form a plurality of dielectric regions. The hard mask is removed from between the plurality of dielectric regions, wherein a second plurality of trenches is left by the removed hard mask. An epitaxy step is performed to grow a semiconductor material in the second plurality of trenches.

Inverse spacer processing

A method includes making a target feature of an integrated circuit by providing a main layer over a substrate, depositing a first mask layer over the main layer, patterning the first mask layer, forming sidewall spacers with a width (w) in adjoining sidewalls of the patterned first mask layer and exposing a top area of the patterned first mask layer, selectively removing the first mask layer and exposing a portion of the main layer between the sidewall spacers, depositing a second mask layer over the main layer between the sidewall spacers, selectively removing the sidewall spacers to form an opening and exposing another portion of the main layer in the opening, etching the main layer through the opening to form the target feature.

Semiconductor device and method of manufacturing semiconductor device

According to one embodiment, there are provided a first shaped pattern in which a plurality of first holes are arranged and of which a width is periodically changed along an arrangement direction of the first holes, a second shaped pattern in which a plurality of second holes are arranged and of which a width is periodically changed along an arrangement direction of the second holes, and slits which are formed along the arrangement direction of the first holes and separate the first shaped pattern and the second shaped pattern.

Silicon-containing resist underlayer film-forming composition and patterning process

The present invention is a silicon-containing resist underlayer film-forming composition containing a condensation product and/or a hydrolysis condensation product of a mixture comprising: one or more kinds of a compound (A) selected from the group consisting of an organic boron compound shown by the general formula (1) and a condensation product thereof and one or more kinds of a silicon compound (B) shown by the general formula (2). Thereby, there can be provided a silicon-containing resist underlayer film-forming composition being capable of forming a pattern having a good adhesion, forming a silicon-containing film which can be used as a dry-etching mask between a photoresist film which is the upperlayer film of the silicon-containing film and an organic film which is the underlayer film thereof, and suppressing deformation of the upperlayer resist during the time of dry etching of the silicon-containing film; and a patterning process. R 1 m0 B(OH) m1 (OR) (3-m0-m1)   (1) R 10 m10 R 11 m11 R 12 m12 Si(OR 13 ) (4-m10-m11-m12)   (2)

Methods of forming patterns of a semiconductor device

Methods of forming patterns of a semiconductor device are provided. The methods may include forming a hard mask film on a semiconductor substrate. The methods may include forming first and second sacrificial film patterns that are spaced apart from each other on the hard mask film. The methods may include forming a first spacer on opposing sidewalls of the first sacrificial film pattern and a second spacer on opposing sidewalls of the second sacrificial film pattern. The methods may include removing the first and second sacrificial film patterns. The methods may include trimming the second spacer such that a line width of the second spacer becomes smaller than a line width of the first spacer. The methods may include forming first and second hard mask film patterns by etching the hard mask film using the first spacer and the trimmed second spacer as an etch mask.

Method for forming fine pattern having variable width and method for manufacturing semiconductor device using the same

A method for forming a fine pattern having a variable width by simultaneously using an optimal focused electron beam and a defocused electron beam in a light exposure process Includes, after forming a first film on a substrate, forming a first film pattern including a first level area and a second level area having different distances from the substrate by changing a profile of an upper surface of the first film. A photoresist film having a first area covering the first level area and a second area covering the second level area is formed. To simultaneously light-expose the first area and the second area with the same width, a light exposure condition, in which an optimal focused electron beam is eradiated on the first area and a defocused electron beam is eradiated on the second area, is applied. A plurality of photoresist patterns continuously extending over the first level area and the second level area with different widths on the first level area and the second level area are formed by developing the light-exposed photoresist film.

Method of manufacturing barrier layer patterns of a semiconductor memory device and structure of barrier layer patterns of semiconductor memory device

A method of manufacturing a semiconductor memory and a structure of the semiconductor memory device, where the semiconductor memory device includes a material layer and a barrier layer. The barrier layer has a structure in which a horizontal cross-section of an upper portion thereof is larger than that of a lower portion thereof so that a fine pattern may be formed on the material layer using the barrier layer pattern without a structural damage or collapse in etching the underlying material layer.

Method for Forming Self-Aligned Trench Contacts of Semiconductor Components and A Semiconductor Component

A method for producing a semiconductor component is described. The method includes providing a semiconductor body having a first surface and being comprised of a first semiconductor material extending to the first surface. At least one trench extends from the first surface into the semiconductor body and includes a gate electrode insulated from the semiconductor body and arranged below the first surface. The method further includes: forming a second insulation layer on the first surface with a recess that overlaps in projection onto the first surface with the conductive region; forming a mask region in the recess; etching the second insulation layer selectively to the mask region and the semiconductor body to expose the semiconductor body at the first surface; depositing a third insulation layer on the first surface; and etching the third insulation layer so that a semiconductor mesa of the semiconductor body arranged next to the a least one trench is exposed at the first surface.

SILICON-CONTAINING COMPOSITION FOR FORMATION OF RESIST UNDERLAYER FILM, WHICH CONTAINS ORGANIC GROUP CONTAINING PROTECTED ALIPHATIC ALCOHOL

Described herein are compositions for forming an underlayer film for a solvent-developable resist. These compositions can include a hydrolyzable organosilane having a silicon atom bonded to an organic group containing a protected aliphatic alcohol group, a hydrolysate of the hydrolyzable organosilane, a hydrolysis-condensation product of the hydrolyzable organosilane, or a combination thereof and a solvent. The composition can form a resist underlayer film including, a hydrolyzable organosilane, a hydrolysate of the hydrolyzable organosilane, a hydrolysis-condensation product of the hydrolyzable organosilane, or a combination thereof, the silicon atom in the silane compound having a silicon atom bonded to an organic group containing a protected aliphatic alcohol group in a ratio of 0.1 to 40% by mol based on the total amount of silicon atoms. Also described is a method for applying the composition onto a semiconductor substrate and baking the composition to form a resist underlayer film. 1. A composition for forming an underlayer film for a solvent-developable resist , the composition comprising:a hydrolyzable organosilane having a silicon atom bonded to an organic group containing a protected aliphatic alcohol group, a hydrolysate of the hydrolyzable organosilane, a hydrolysis-condensation product of the hydrolyzable organosilane, or a combination of these; anda solvent.2. The composition for forming an underlayer film according to claim 1 , wherein the composition for forming a resist underlayer film including claim 1 , as a silane compound claim 1 , the hydrolyzable organosilane claim 1 , a hydrolysate of the hydrolyzable organosilane claim 1 , a hydrolysis-condensation product of the hydrolyzable organosilane claim 1 , or a combination of these contains the silicon atom in the silane compound having a silicon atom bonded to an organic group containing a protected aliphatic alcohol group in a ratio of 0.1 to 40% by mol based on the total amount of silicon atoms.6 ...

Directed assembly of block copolymer films between a chemically patterned surface and a second surface

Provided are methods of fabricating thin film structures that involve assembling block copolymer materials in the presence of condensed phase surfaces on both sides of the thin film, at least one of which is a chemically patterned surface configured to direct the assembly of the block copolymer material. According to various embodiments, the other of the condensed phase surfaces can be a chemically homogenous surface or a chemically patterned surface. Also provided are structures, morphologies, and templates formed in the domain structure of block copolymer materials. In certain embodiments, complex 3-D morphologies and related structures not present in bulk block copolymer materials are provided.

Etching method and etching apparatus

An etching method of etching a periodic pattern formed by self-assembling a first polymer and a second polymer of a block copolymer that is capable of being self-assembled, the etching method includes supplying a high frequency power which is set such that a great amount of ion energy is distributed within a range smaller than ion energy distribution at which an etching yield of the first polymer is generated and larger than or equal to ion energy distribution at which an etching yield of the second polymer is generated, and supplying a predetermined gas, generating plasma from the supplied gas by the high frequency power, and etching the periodic pattern on a processing target object by using the generated plasma.

TREATMENT LIQUID FOR INHIBITING PATTERN COLLAPSE IN MICROSTRUCTURE AND METHOD OF MANUFACTURING MICROSTRUCTURE USING THE SAME

The objects of the present invention are to provide a treatment liquid able to inhibit pattern collapse in a microstructure such as a semiconductor device or a micromachine, as well as a method of manufacturing a microstructure using the same. 1. A treatment liquid for inhibiting pattern collapse in a metal microstructure comprising an alkylphosphonic acid or salt thereof in which said alkyl moiety contains 6 to 18 carbon atoms; water; and a glycol of the following formula (1) or (2):{'br': None, 'sub': 2', '4', 'n, 'sup': '1', 'HO(CHO)R\u2003\u2003(1)'}{'br': None, 'sub': 3', '6', 'm, 'sup': '1', 'HO(CHO)R\u2003\u2003(2)'}{'sup': '1', 'sub': 1', '4, 'wherein Rdenotes a hydrogen atom or a C-Calkyl group, n denotes an integer of 2 to 4, and m denotes an integer of 1 to 3.'}2. The treatment liquid for inhibiting pattern collapse according to claim 1 , wherein the microstructure contains at least one metal selected from among titanium claim 1 , tantalum and aluminum.3. The treatment liquid for inhibiting pattern collapse according to claim 1 , wherein the content of the alkylphosphonic acid is 0.1 ppm to 10 claim 1 ,000 ppm.4. The treatment liquid for inhibiting pattern collapse according to claim 1 , wherein the content of the alkylphosphonic acid is 0.5 ppm to 1 claim 1 ,000 ppm.5. The treatment liquid for inhibiting pattern collapse according to claim 1 , wherein the content of the alkylphosphonic acid is 5 ppm to 800 ppm.6. The treatment liquid for inhibiting pattern collapse according to claim 1 , wherein the content of glycols is 60% by weight to 99% by weight.7. A method of manufacturing a microstructure containing at least one metal selected from among titanium claim 1 , tantalum and aluminum claim 1 , the method comprising: [{'br': None, 'sub': 2', '4', 'n, 'sup': '1', 'HO(CHO)R\u2003\u2003(1)'}, {'br': None, 'sub': 3', '6', 'm, 'sup': '1', 'HO(CHO)R\u2003\u2003(2)'}], 'in rinsing steps following wet-etching or dry-etching, using a treatment liquid for ...

Non-bridging contact via structures in proximity

A first photoresist layer is patterned with a first pattern that includes an opening in a region between areas of two adjacent via holes to be formed. The opening in the first photoresist is transferred into a template layer to form a line trench therein. The lateral dimension of the trench is reduced by depositing a contiguous spacer layer that does not fill the trench completely. An etch-resistant material layer is conformally deposited and fills the trench, and is subsequently recessed to form an etch-resistant material portion filling the trench. A second photoresist layer is applied and patterned with a second pattern, which includes an opening that includes areas of two via holes and an area therebetween. A composite pattern of an intersection of the second pattern and the complement of the pattern of the etch-resistant material portion is transferred through the template layer.

USE OF SURFACTANTS HAVING AT LEAST THREE SHORT-CHAIN PERFLUORINATED GROUPS RF FOR MANUFACTURING INTEGRATED CIRCUITS HAVING PATTERNS WITH LINE-SPACE DIMENSIONS BELOW 50 NM

The use of surfactants A, the 1% by weight aqueous solutions of which exhibit a static surface tension <25 mN/m, the said surfactants A containing at least three short-chain perfluorinated groups Rf selected from the group consisting of trifluoromethyl, pentafluoroethyl, 1-heptafluoropropyl, 2-heptafluoropropyl, heptafluoroisopropyl, and pentafluorosulfanyl; for manufacturing integrated circuits comprising patterns having line-space dimensions below 50 nm and aspect ratios >3; and a photolithographic process making use of the surfactants A in immersion photoresist layers, photoresist layers exposed to actinic radiation, developer solutions for the exposed photoresist layers and/or in chemical rinse solutions for developed patterned photoresists comprising patterns having line-space dimensions below 50 nm and aspect ratios >3. By way of the surfactants A, pattern collapse is prevented, line edge roughness is reduced, watermark defects are prevented and removed and defects are reduced by removing particles. 1. A process for manufacturing an integrated circuit , the process comprising:manufacturing an integrated circuit with a surfactant A,wherein a 1% by weight aqueous solution of the surfactant A has a static surface tension of less than 25 mN/m;the surfactant A comprises at least three short-chain perfluorinated groups Rf selected from the group consisting of trifluoromethyl, pentafluoroethyl, 1-heptafluoropropyl, 2-heptafluoropropyl, and pentafluorosulfanyl; andthe integrated circuits comprises a pattern having a line-space dimension below 50 nm and an aspect ratio of greater than 3.2. The process according to claim 1 , wherein the perfluorinated groups Rf are bonded to the same multi-valent central moiety B.4. The process according to claim 2 , wherein the surfactant A comprises a hydrophobic group D.6. The process according to claim 1 ,wherein manufacturing the integrated circuit with surfactant A comprises manufacturing with the surfactant A in an immersion ...

Process for fabricating a transistor comprising nanoscale semiconductor features using block copolymers

A process for fabricating one transistor, comprising a semiconductor region, comprising a source region, a drain region, and a channel region covered with a gate, comprises: production of an primary etching mask on the surface of the semiconductor region, said mask containing at least one primary aperture; depositing in said primary aperture a block copolymer containing, in alternation, at least first polymer domains and second polymer domains; removing either a series of first polymer domains or a series of second polymer domains in order to create a secondary mask containing secondary apertures; etching said active region through said secondary apertures in order to define nanoscale self-aligned semiconductor features; producing said gate on the surface of said self-aligned semiconductor features.

Method for selectively modifying spacing between pitch multiplied structures

Methods for circuit material processing are provided. In at least one such method, a substrate is provided with a plurality of overlying spacers. The spacers have substantially straight inner sidewalls and curved outer sidewalls. An augmentation material is formed on the plurality of spacers such that the inner or the outer sidewalls of the spacers are selectively expanded. The augmentation material can bridge the upper portions of pairs of neighboring inner sidewalls to limit deposition between the inner sidewalls. The augmentation material is selectively etched to form a pattern of augmented spacers having a desired augmentation of the inner or outer sidewalls. The pattern of augmented spacers can then be transferred to the substrate through a series of selective etches such that features formed in the substrate achieve a desired pitch.

Hardmask materials

Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about −600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of Si x B y C z , Si x B y N z , Si x B y C z N w , B x C y , and B x N y . In some embodiments, a hardmask film includes a germanium-rich GeN x material comprising at least about 60 atomic % of germanium. These hardmasks can be used in a number of back-end and front-end processing schemes in integrated circuit fabrication.

Substrate having etching mask and method for producing same

Provided are a substrate with an etching mask which enables high definition patterning and a method of manufacturing the same. A photosensitive material is applied on a surface of a substrate, exposure and development of the photosensitive material are carried out to form a resist pattern, a DLC coating film is formed on the surface of the substrate and a surface of the resist pattern, and the DLC coating film formed on the resist pattern is separated together with the resist pattern to form a DLC pattern on the surface of the substrate.

Highly ordered arrays of colloidal 2d crystals and methods for producing the same

The present invention relates to highly ordered arrays of colloidal 2D crystals on a substrate and to an improved method for producing the same. The method according to the invention for producing an highly ordered array of colloidal 2D crystals on a substrate comprises the following steps: a) providing a suspension of microspheres comprising poly-N-isopropylamide (polyNIPAM), the microspheres being selected from pure poly-N-isopropylamide (polyNIPAM) hydrogel microspheres, functionalized polyNIPAM microspheres, and polymeric or inorganic beads carrying poly-N-isopropyl-amide (polyNIPAM) hydrogel chains, in an aqueous medium on a substrate, wherein the aqueous medium comprises a mixture of water and a lower alkyl alcohol, b) subjecting the suspension deposited on the substrate after step a) to a shear force, and c) drying the suspension. In a preferred embodiment of the invention, the shear force is generated by applying a pulsed gas stream to the substrate surface. The colloidal 2D crystal arrays obtained by this method have an exceptional high long range order, including monocrystalline domains in the range of square millimetres.

Integrated Circuit Having FinFETS with Different Fin Profiles

An integrated circuit is provided. The integrated circuit includes a substrate, a first FinFET device supported by the substrate, the first FinFET device having a first fin with a non-tiered fin profile, and a second FinFET supported by the substrate, the second FinFET having a second fin with a tiered fin profile.

NANOMETRIC IMPRINT LITHOGRAPHY METHOD

A nanoimprint lithography method, including: pressing a mold in a photosensitive resin to form at least one imprint pattern defined by a stamped area and an adjacent area, the adjacent area being less stamped or not stamped at all, and being thicker than the stamped area; and exposure to a certain amount of sunlight. Respective thicknesses of the two areas are defined such that the two areas absorb a different amount of the sunlight and the amount of sunlight provided by the exposure is predetermined so as to be great enough to activate the resin in whichever of the two areas has the greater absorption, and so as not to be great enough to activate the other of the two areas. 119-. (canceled)20. A nanometric imprint lithography method comprising:a preparation during which a photosensitive resist is disposed on a substrate;at least one pressing a mold in the resist to form in the resist at least one imprint pattern delimited at least partly by two adjacent areas, one of the two areas having a thickness less than a thickness of the other one of the two areas;exposing at least the two areas during which the two areas receive a same insolation dose; andwherein the thicknesses of the two areas are defined so that, to be activated, the resist in one of the two areas requires an insolation dose different from the insolation dose necessary for activating the resist in the other one of the two areas, and the insolation dose afforded by the exposure is determined so as to be sufficiently great to activate the resist in only one of the two areas and so as not to be sufficiently great to activate the other one of the two adjacent areas.21. A method according to claim 20 , wherein the absorption of the insolation dose by the resist according to its thickness defines a substantially sinusoidal curve claim 20 , and wherein the thickness of the resist in one of the two areas corresponds substantially to a maximum of the sinusoidal curve and the thickness of the resist in the other ...

Methods of Manufacturing Semiconductor Devices

Methods of manufacturing semiconductor devices are disclosed. In one embodiment, a material layer is formed over a workpiece. The workpiece includes a first portion, a second portion, and a hard mask disposed between the first portion and the second portion. The material layer is patterned, and first spacers are formed on sidewalls of the patterned material layer. The patterned material layer is removed, and the second portion of the workpiece is patterned using the first spacers as an etch mask. The first spacers are removed, and second spacers are formed on sidewalls of the patterned second portion of the workpiece. The patterned second portion of the workpiece is removed, and the hard mask of the workpiece is patterned using the second spacers as an etch mask. The first portion of the workpiece is patterned using the hard mask as an etch mask.

Substrate processing apparatus and substrate processing method

An underlayer is formed to cover the upper surface of a substrate and a guide pattern is formed on the underlayer. A DSA film constituted by two types of polymers is formed in a region on the underlayer where the guide pattern is not formed. Thermal processing is performed while a solvent is supplied to the DSA film on the substrate. Thus, a microphase separation of the DSA film occurs. As a result, patterns made of the one polymer and patterns made of another polymer are formed. Exposure processing and development processing are performed in this order on the DSA film after the microphase separation such that the patterns made of another polymer are removed.

Methods of fabricating fine patterns and photomask sets used therein

Photo mask sets and methods of fabricating fine patterns are provided. The method includes forming a first layer having a first main pattern part and a first dummy pattern part on a base layer, forming a second layer on the first layer, etching the first layer using the second layer as an etch mask to form a third main pattern part composed of a remaining portion of the first main pattern part and to remove the first dummy pattern part, and removing the second layer. The second layer is formed to have a second main pattern part exposing portions of the first main pattern part and to have a second dummy pattern part exposing the first dummy pattern part.

Method for providing vias

A method for forming via holes in an etch layer disposed below a patterned organic mask with a plurality of patterned via holes is provided. The patterned organic mask is treated by flowing a treatment gas comprising H 2 . A plasma is formed from the treatment gas. The patterned via holes are rounded to form patterned rounded via holes by exposing the patterned via holes to the plasma. The flow of the treatment gas is stopped. The plurality of patterned rounded via holes are transferred into the etch layer.

Coating treatment method and coating treatment apparatus

In the present invention, a masking solution is supplied to an edge portion of a front surface of a substrate rotated around a vertical axis to form a masking film at the edge portion of the substrate, a hard mask solution is supplied to the front surface of the substrate to form a hard mask film on the front surface of the substrate, a hard mask film removing solution dissolving the hard mask film is supplied to the hard mask film formed at the edge portion of the substrate to remove the hard mask film formed at the edge portion of the substrate, and a masking film removing solution dissolving the masking film is supplied to the masking film to remove the masking film at the edge portion of the substrate.

METHODS OF ELIMINATING PATTERN COLLAPSE ON PHOTORESIST PATTERNS

A stabilizing solution for treating photoresist patterns and methods of preventing profile abnormalities, toppling and resist footing are disclosed. The stabilizing solution comprises a non-volatile component, such as non-volatile particles or polymers, which is applied after the photoresist material has been developed. By treating the photoresist with the solution containing a non-volatile component after developing but before drying, the non-volatile component fills the space between adjacent resist patterns and remains on the substrate during drying. The non-volatile component provides structural and mechanical support for the resist to prevent deformation or collapse by liquid surface tension forces. 1. A method of forming a semiconductor device , the method comprising;providing a photoresist layer over a semiconductor substrate;exposing the photoresist layer to a predetermined pattern;developing the photoresist layer with a developing solution to form the predetermined photoresist pattern;displacing at least part of the developing solution with an aqueous polymer solution for stabilizing the predetermined photoresist pattern; anddrying the predetermined photoresist pattern.2. The method of claim 1 , further comprising the step of rinsing the semiconductor substrate after the step of displacing at least part of the developing solution and before the step of drying the predetermined photoresist pattern.3. The method of claim 2 , wherein the step of rinsing the semiconductor substrate comprising supplying a de-ionized water solution to the predetermined photoresist pattern.4. The method of claim 1 , further comprising subjecting the predetermined photoresist pattern to a heat treatment before the step of drying claim 1 , to remove a volatile component of the stabilizing solution and to leave a non-volatile polymer over the semiconductor substrate and between pattern lines of the predetermined photoresist pattern.5. The method of claim 4 , further comprising ...

Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures

Spacers are formed by pitch multiplication and a layer of negative photoresist is deposited on and over the spacers to form additional mask features. The deposited negative photoresist layer is patterned, thereby removing photoresist from between the spacers in some areas. During patterning, it is not necessary to direct light to the areas where negative photoresist removal is desired, and the clean removal of the negative photoresist from between the spacers is facilitated. The pattern defined by the spacers and the patterned negative photoresist is transferred to one or more underlying masking layers before being transferred to a substrate.

Two-step shallow trench isolation (sti) process

An integrated circuit device and a process for making the integrated circuit device. The integrated circuit device including a substrate having a trench formed therein, a first layer of isolation material occupying the trench, a second layer of isolation material formed over the first layer of isolation material, an epitaxially-grown silicon layer on the substrate and horizontally adjacent the second layer of isolation material, and a gate structure formed on the epitaxially-grown silicon, the gate structure defining a channel.

Hardmask layer with alternating nanolayers

A hardmask layer is formed with an increased etch resistance based on alternating nanolayers of TiN with alternating residual stresses. Embodiments include depositing a first nanolayer of TiN, and depositing a second nanolayer of TiN on the first nanolayer, wherein the first and second nanolayers have different residual stresses.

Methods of forming a semiconductor device

A method of forming a semiconductor device includes first preliminary holes over an etch target, the first preliminary holes arranged as a plurality of rows in a first direction, forming dielectric patterns each filling one of the first preliminary holes, sequentially forming a barrier layer and a sacrificial layer on the dielectric patterns, forming etch control patterns between the dielectric patterns, forming second preliminary holes by etching the sacrificial layer, each of the second preliminary holes being in a region defined by at least three dielectric patterns adjacent to each other, and etching the etch target layer corresponding to positions of the first and second preliminary holes to form contact holes.

Photomask and method for forming pattern of semiconductor device using the same

A semiconductor device includes a cell mask pattern disposed in a cell region of a mask substrate and a vernier mask pattern disposed in a vernier region of the mask substrate. The vernier mask pattern includes a variable mask pattern portion to transfer a different shape of pattern depending on the magnitude of exposure energy.

Processes for NAND Flash Memory Fabrication

Narrow word lines are formed in a NAND flash memory array using a double patterning process in which sidewall spacers define word lines. Sidewall spacers also define edges of select gates so that spacing between a select gate and the closest word line is equal to spacing between adjacent word lines.

METHOD FOR POSITIONING SPACERS IN PITCH MULTIPLICATION

Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed mandrels is removed and alternating layers, formed of two mutually selectively etchable materials, are deposited around the remaining spacers. Layers formed of one of the materials are then etched, leaving behind vertically-extending layers formed of the other of the materials, which form a mask pattern. Alternatively, instead of depositing alternating layers, amorphous carbon is deposited around the remaining spacers followed by a plurality of cycles of forming pairs of spacers on the amorphous carbon, removing one of the pairs of spacers and depositing an amorphous carbon layer. The cycles can be repeated to form the desired pattern. Because the critical dimensions of some features in the pattern can be set by controlling the width of the spaces between spacers, exceptionally small mask features can be formed. 1. A method for forming an integrated circuit , comprising:forming a first plurality of mandrels on a first level over a substrate;forming a first plurality of spacers on sidewalls of the first plurality of mandrels;forming a second plurality of mandrels on a second level over the first level;forming a second plurality of spacers on the sidewalls of the second plurality of mandrels, the second plurality of spacers elongated generally parallel to the first plurality of spacers;selectively etching portions of the first and the second pluralities of mandrels to form a pattern defined by spacers of the first and the second pluralities of spacers; andtransferring the pattern to the substrate.2. The method of claim 1 , wherein forming the first plurality of mandrels comprises patterning a carbon-containing layer to define the first plurality of mandrels in the carbon-containing layer.3. The method of claim 2 , wherein the carbon-containing layer is formed of amorphous carbon.4. The method of claim 1 , ...

PATTERN FORMATION METHOD

A pattern formation method comprises a process of forming a resist pattern with an opening that exposes a first region of a glass film arranged on a substrate through a base film; a process of forming a neutralization film above the glass film; a process of forming a directed self-assembly material layer containing a first segment and a second segment above the glass film; a process of microphase separating the directed self-assembly material layer to form a directed self-assembly pattern containing a first part that includes the first segment and a second part that includes the second segment; and a process of removing either the first part or the second part and using the other as a mask to process the base film. 1. A pattern formation method , comprising:forming a first layer on a substrate;forming a second layer on the first layer;forming a resist pattern on the second layer in a line and space pattern, the space pattern having openings that expose a portion of the second layer;removing the resist pattern to form a first region and a second region on the second layer, wherein the first region has a greater hydrophobicity than the second region;forming a directed self-assembly material layer containing a first segment and a second segment on the second layer;microphase separating the directed self-assembly material layer to form a self-assembled pattern containing a first polymer part that includes the first segment and a second polymer part that includes the second segment; andremoving either the first polymer part or the second polymer part using the other as a mask to process the first layer.2. The method of claim 1 , wherein removing the resist pattern comprises oxidizing the resist pattern.3. The method of claim 2 , wherein removing the resist pattern comprises exposing the resist pattern and the second layer to oxygen plasma.4. The method of claim 2 , wherein removing the resist pattern comprises exposing the resist pattern to ozonated water.5. The method ...

CARBON DEPOSITION-ETCH-ASH GAP FILL PROCESS

Techniques, systems, and apparatuses for performing carbon gap-fill in semiconductor wafers are provided. The techniques may include performing deposition-etching operations in a cyclic fashion to fill a gap feature with carbon. A plurality of such deposition-etching cycles may be performed, resulting in a localized build-up of carbon film on the top surface of the semiconductor wafer near the gap feature. An ashing operation may then be performed to preferentially remove the built-up material from the top surface of the semiconductor wafer. Further groups of deposition-etching cycles may then be performed, interspersed with further ashing cycles. 1. A method comprising:a) providing a substrate in a semiconductor process chamber, the substrate having a top surface and at least one gap feature with a gap entry width where the at least one gap feature intersects the top surface;b) performing a deposition process to deposit a carbon film layer on the substrate and on exposed surfaces of the at least one gap feature, wherein the deposition process is performed at least until the deposited carbon film layer causes the gap entry width to be reduced;c) performing an anisotropic etch process on the substrate with a dominant anisotropic axis substantially perpendicular to the substrate at least until the gap entry width increases from the gap entry width at the conclusion of (b);d) performing X additional cycles of (b) and (c), wherein X is a positive integer; ande) performing an ashing process to remove localized build-up of carbon film on the top surface of the substrate adjacent to the at least one gap feature produced as a result of (b) through (d).2. The method of claim 1 , further comprising:f) performing Y additional cycles of (a) through (e), wherein Y is a positive integer.4. The method of claim 2 , wherein:X is between about 1 and 100, and Y is between about 2 and 1000.5. The method of claim 2 , wherein:X is between about 2 and 20, andY is between about 10 to 100.6 ...

Reverse Tone STI Formation

A method includes forming a hard mask over a substrate, patterning the hard mask to form a first plurality of trenches, and filling a dielectric material into the first plurality of trenches to form a plurality of dielectric regions. The hard mask is removed from between the plurality of dielectric regions, wherein a second plurality of trenches is left by the removed hard mask. An epitaxy step is performed to grow a semiconductor material in the second plurality of trenches. 1. A method comprising:forming a pad oxide layer over a semiconductor substrate;forming a hard mask over the pad oxide layer;forming a mandrel layer over the hard mask;performing a first lithography process to pattern the mandrel layer and to form a plurality of mandrels;forming a spacer layer, wherein the spacer layer comprises top portions over the mandrels, and sidewall portions on sidewalls of the mandrels;patterning the spacer layer to leave the sidewall portions of the spacer layer;etching the hard mask and the pad oxide layer to form hard mask patterns and pad oxide patterns, wherein the step of etching is performed using the sidewall portions of the spacer layer as an etching mask;removing the sidewall portions of the spacer layer;filling spaces between the hard mask patterns and the pad oxide patterns with a dielectric material;removing the hard mask patterns and the pad oxide patterns; andperforming an epitaxy to grow a semiconductor material in spaces left by the removed hard mask patterns and the pad oxide patterns.2. The method of claim 1 , wherein the step of patterning the spacer layer comprises two lithography processes.3. The method of claim 1 , wherein the step of filling the spaces comprises a spin-on coating step claim 1 , and a curing step after the spin-on coating step to cure the dielectric material.4. The method of claim 1 , wherein after the step of epitaxy claim 1 , a top surface of the semiconductor material is substantially level with a top surface of the dielectric ...

SELECTIVE DEPOSITION OF CARBON ON PHOTORESIST LAYER FOR LITHOGRAPHY APPLICATIONS

Embodiments disclosed within include a method for etching a hardmask layer includes forming a photoresist layer comprising an organometallic material on a hardmask layer comprising a metal-containing material, exposing the photoresist layer to ultraviolet radiation through a mask having a selected pattern, removing un-irradiated areas of the photoresist layer to pattern the photoresist layer, forming a passivation layer comprising a carbon-containing material selectively on a top surface of the patterned photoresist layer, including selectively depositing passivation material over a top surface of a patterned photoresist layer trimming undesired portions of the passivation material, and etching the hardmask layer exposed by the patterned photoresist layer having the passivation layer formed thereon. 1. A method for etching a hardmask layer , comprising:forming a photoresist layer comprising an organometallic material on the hardmask layer;exposing the photoresist layer to ultraviolet radiation through a mask having a selected pattern;removing un-irradiated areas of the photoresist layer to form a patterned photoresist layer; selectively depositing passivation material over the top surface; and', 'trimming undesired portions of the passivation material; and, 'forming a passivation layer comprising a carbon-containing material selectively on a top surface of the patterned photoresist layer, wherein the forming the passivation layer comprisesetching the hardmask layer exposed by the patterned photoresist layer having the passivation layer formed thereon.2. The method of claim 1 , wherein the organometallic material comprises one or more metal elements and organic ligands.3. The method of claim 2 , wherein the one or more metal elements comprise tin (Sn).4. The method of claim 1 , wherein the trimming the undesired portions comprises exposing the passivation material to a radical etch.5. The method of claim 1 , wherein the forming of the passivation layer comprises: ...

METHOD AND APPARATUS FOR ETCHING TARGET OBJECT

A selectivity can be improved in a desirable manner when etching a processing target object containing silicon carbide. An etching method of processing the processing target object, having a first region containing silicon carbide and a second region containing silicon nitride and in contact with the first region, includes etching the first region to remove the first region atomic layer by atomic layer by repeating a sequence comprising: generating plasma from a first gas containing nitrogen to form a mixed layer containing ions contained in the plasma generated from the first gas in an atomic layer of an exposed surface of the first region; and generating plasma from a second gas containing fluorine to remove the mixed layer by radicals contained in the plasma generated from the second gas. 1. An apparatus for etching a processing target object , the apparatus comprising:a processing vessel;a gas supply unit;a plasma source; anda control unit configured to control the gas supply unit and the plasma source,wherein the control unit is further configured to perform processes comprising:a) preparing a processing target object having a first region as an etching target layer made of a first material containing silicon carbide and a second region as a mask containing silicon nitride;b) removing the first region by using the second region as a mask by repeating a sequence comprising:b-1) forming a layer containing nitrogen in the first region by exposing the processing target object to nitrogen containing plasma;b-2) after the forming of the layer, removing the layer by exposing the processing target object to fluorine containing plasma.2. The apparatus of claim 1 ,wherein the nitrogen containing plasma is generated from a nitrogen-containing gas.3. The apparatus of claim 1 ,{'sub': 2', '2', '2, 'wherein the nitrogen containing plasma is generated from a Ngas or a mixed gas containing a Ngas and an Ogas.'}4. The apparatus of claim 1 ,{'sub': 3', '2', '2, 'wherein the ...

LITHOGRAPHIC COMPOSITIONS AND METHODS OF USE THEREOF

Masking compositions for preventing metal contamination at substrate edges during the manufacture of electronic devices. The masking compositions have a unit of structure (I): Also provided are methods of using the masking compositions for manufacturing electronic devices. 24-. (canceled)5. The composition of claim 1 , wherein the polymer comprises a mixture of polymers each comprising a unit having structure (I).6. The composition of claim 5 , wherein the mixture of polymers comprises a first polymer having an Mw greater than 40000 and a second polymer having an Mw less than 40000.7. The composition of claim 5 , wherein the mixture of polymers comprises a first polymer having an Mw greater than 30000 and a second polymer having an Mw less than 30000.8. The composition of claim 5 , wherein the mixture of polymers comprises a first polymer having an Mw greater than 40000 20000 and a second polymer having an Mw less than 20000.910-. (canceled)11. The composition of claim 1 , wherein X is —SO—.12. The composition of claim 1 , wherein each R claim 1 , each R claim 1 , each Rand each Ris independently selected from the group consisting of H claim 1 , F claim 1 , and (C) alkyl.13. (canceled)14. The composition of claim 1 , wherein each Ris independently selected from the group consisting of H claim 1 , F claim 1 , (C) alkyl claim 1 , and (C) fluorinated alkyl.1516-. (canceled)21. The composition of claim 1 , wherein the organic solvent is selected from the group consisting of anisole claim 1 , cyclohexanone claim 1 , gamma butyro lactone (GBL) claim 1 , N-methyl-2-pyrrolidone claim 1 , di-(C) alkyl ketones claim 1 , (C) alkyl acetates and mixtures thereof.22. The composition claim 1 , wherein the polymer is present in the composition in an amount between 0.1 wt % and 20 wt %.23. The composition of claim 1 , wherein the polymer is present in the composition in an amount between 3 wt % and 15 wt %.24. A method of manufacturing an electronic device comprising the steps of:{' ...

THIN-FILM DEPOSITION METHOD AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

A method of depositing a thin film having a desired etching characteristic while improving a loss amount and loss uniformity of a lower film includes, on the semiconductor substrate and the pattern structure: a first operation of depositing a portion of the thin film by repeating a first cycle comprising (a1) a source gas supply operation, (b1) a reactant gas supply operation, and (c1) a plasma supply operation for a certain number of times; a second operation of depositing a remaining portion of the thin film by repeating a second cycle comprising (a2) a source gas supply operation, (b2) a reactant gas supply operation, and (c2) a plasma supply operation for a certain number of times after the first operation, wherein a supply time of the source gas supply operation (a1) is longer than a supply time of the source gas supply operation (a2). 1. A method of depositing a thin film on a pattern structure of a semiconductor substrate , the method comprising , on the semiconductor substrate and the pattern structure:a first operation of depositing a portion of the thin film by repeating a first cycle comprising a source gas supply operation (a1), a reactant gas supply operation (b1), and a plasma supply operation (c1) for a certain number of times; anda second operation of depositing a remaining portion of the thin film by repeating a second cycle comprising a source gas supply operation (a2), a reactant gas supply operation (b2), and a plasma supply operation (c2) for a certain number of times after the first operation,wherein a supply time of the source gas supply operation (a1) is longer than a supply time of the source gas supply operation (a2).2. The method of claim 1 , wherein the supply time of the source gas supply operation (a1) is two to five times the supply time of the source gas supply operation (a2).3. The method of claim 1 , wherein the supply time of the source gas supply operation (a1) is 0.2 seconds to 1 second.4. The method of claim 1 , wherein the ...

INTEGRATED CIRCUIT FABRICATION

A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width. 1. (canceled)2. A method for integrated circuit fabrication , comprising:forming a plurality of mask lines in a first region of an integrated circuit structure, wherein the mask lines form loops, each loop having looped ends at ends of the loop;depositing a selectively definable material over the integrated circuit structure;patterning the selectively definable material to expose portions of the mask lines between the loop ends, while covering a width of the mask lines at the loop ends, and while defining a plurality of features in a second region of the integrated circuit structure, wherein the patterned selectively definable material and the exposed portions of the mask lines form a mask; andtransferring a pattern defined by the mask to underlying material.3. The method of claim 2 , wherein the selectively definable material comprises photoresist.4. The method of claim 2 , wherein the selectively definable material is disposed on a level above the mask lines claim 2 , further comprising a layer of planarizing material disposed on a same level as the mask lines.5. The method of claim 2 , wherein the first region is an array region.6. The method of claim 5 , wherein the second region is a periphery region.7. The method of ...

COMPOSITION FOR FORMING A COATING TYPE BPSG FILM, SUBSTRATE FORMED A FILM BY SAID COMPOSITION, AND PATTERNING PROCESS USING SAID COMPOSITION

The present invention provides a composition for forming a coating type BPSG film, which comprises: one or more structures comprising a silicic acid represented by the following general formula (1) as a skeletal structure, one or more structures comprising a phosphoric acid represented by the following general formula (2) as a skeletal structure and one or more structures comprising a boric acid represented by the following general formula (3) as a skeletal structure. There can be provided a composition for forming a coating type BPSG film which is excellent in adhesiveness in fine pattern, can be easily wet etched by a peeling solution which does not cause any damage to the semiconductor apparatus substrate, the coating type organic film or the CVD film mainly comprising carbon which are necessary in the patterning process, and can suppress generation of particles by forming it in the coating process. 2. The composition for forming a coating type BPSG film according to claim 1 , wherein the composition comprises claim 1 , a solvent(s) and one or more polymers selected from a hydrolysate claim 1 , a condensate and a hydrolysis condensate of a mixture claim 1 , as Component (A) claim 1 , which comprises one or more silicon compounds represented by the following general formulae (A-1-1) to (A-1-4) claim 1 , and either one of or both of one or more phosphorus compounds represented by the following general formulae (A-2-1) to (A-2-6) and one or more boron compounds represented by the following general formulae (A-3-1) to (A-3-3) claim 1 ,{'br': None, 'sup': 1', '2', '3, 'RRRSiOR\u2003\u2003(A-1-1)'}{'br': None, 'sup': 4', '5, 'sub': '2', 'RRSi(OR)\u2003\u2003(A-1-2)'}{'br': None, 'sup': '6', 'sub': '3', 'RSi(OR)\u2003\u2003(A-1-3)'}{'br': None, 'sub': '4', 'Si(OR)\u2003\u2003(A-1-4)'}{'sup': 1', '2', '3', '4', '5', '6, 'claim-text': [{'br': None, 'sub': '3', 'PX\u2003\u2003(A-2-1)'}, {'br': None, 'sub': '3', 'POX\u2003\u2003(A-2-2)'}, {'br': None, 'sub': 2', '5, 'PO\ ...

SPIN-ON COMPOSITIONS OF SOLUBLE METAL OXIDE CARBOXYLATES AND METHODS OF THEIR USE

The present disclosure relates to spin-on compositions containing at least one metal oxide dicarboxylate and an organic solvent into which the metal oxide dicarboxylate is soluble or colloidally stable. The dicarboxylate is capable of decomposing during heat treatment to give a cured metal oxide film. The present disclosure also relates to method of using the spin-on compositions. 1. A spin-on composition comprising at least one metal oxide dicarboxylate and an organic solvent , where the metal oxide dicarboxylate is soluble or colloidally stable in the solvent , and wherein the metal oxide dicarboxylate is capable of decomposing during heat treatment to give a cured metal oxide film.2. The composition of claim 1 , wherein the carboxylate of the dicarboxylate is selected from a group consisting of a substituted C-Ccarboxylate claim 1 , unsubstituted C-Ccarboxylate claim 1 , saturated C-Ccarboxylate claim 1 , unsaturated C-Ccarboxylate claim 1 , branched C-Ccarboxylate and unbranched C-Ccarboxylate.3. The composition of claim 1 , wherein the carboxylate of the dicarboxylate is propionate.4. The composition of claim 1 , wherein the metal in the metal oxide dicarboxylate is at least one high refractive metal selected from Ti claim 1 , V claim 1 , Cr claim 1 , Zr claim 1 , Nb claim 1 , Mo claim 1 , Ru claim 1 , Rh claim 1 , Hf claim 1 , Ta claim 1 , W claim 1 , Re claim 1 , and Ir.5. The composition of claim 1 , wherein the metal oxide dicarboxylate is a nanoparticle.6. The composition of wherein the carboxylate of the dicarboxylate is propionate.7. The composition of claim 1 , wherein the metal oxide dicarboxylate is zirconium oxide dicarboxylate or titanium oxide dicarboxylate.8. The composition of claim 7 , wherein the carboxylate of the dicarboxylate is propionate.9. The composition of claim 1 , further comprising at least one polymer selected from a group consisting of an organic polymer claim 1 , an inorganic polymer claim 1 , and mixtures thereof.11. A method of ...

Methods and Structures for Protecting One Area While Processing Another Area on a Chip

Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials. 1. A method of protecting a material surface comprising steps ofdepositing a material layer on said material surface, said material layer providing an interface selected from the group consisting of a grain interface and a material interface,lithographically patterning said material layer, andremoving said material layer from said material surface selectively to said material surface.27-. (canceled)8. A method as recited in claim 1 , wherein said depositing step includesdepositing a first layer of polysilicon material,exposing said first layer of polysilicon material to an ambient gas to form a said grain interface, anddepositing a second layer of polysilicon material.9. A method as recited in claim 8 , wherein said ambient gas includes oxygen.10. A method as recited in claim 9 , wherein said first and second layers of polysilicon material have a total thickness of less than 40 nm.11. A method as recited in claim 1 , wherein said depositing step includesdepositing a layer of polysilicon, anddepositing a layer of metal in said layer of polysilicon to form a said material interface.12. A method as recited in claim 11 , wherein said metal is tungsten.13. A method as recited in claim 11 , including the further step of forming a silicide from said layer of metal and said layer of polysilicon.14. A ...

METHOD FOR FORMING TiN AND STORAGE MEDIUM

When forming a TiN film to be formed as a metallic hard mask for etching a film formed on a substrate to be processed, a first step and a second step are repeated a plurality of times to form a TiN film having reduced film stress. In the first step (step 1), the substrate to be processed is conveyed into a processing chamber, TiClgas and a nitriding gas are fed into the processing chamber, the interior of which being kept in a depressurized state during this time, and a plasma from the gases is generated to form a TiN unit film. In the second step (step 2), a nitriding gas is fed into the processing container, a plasma of the gas is generated, and the TiN unit film is subjected to plasma nitriding. 1. A method of forming a TiN film to be used as a metallic hard mask in etching of an etching target film formed on a substrate to be processed , the method comprising:alternately repeating a step of forming a TiN unit film and a step of performing a plasma nitriding process on the TiN unit film to form a TiN film having a reduced film stress,{'sub': 4', '4, 'wherein the step of forming the TiN unit film is performed by loading the substrate to be processed into a processing chamber, supplying TiClgas and a nitriding gas into the processing chamber while maintaining an inside of the processing chamber in a depressurized state, and generating a plasma from the TiClgas and the nitriding gas, and'}wherein the step of performing the plasma nitriding process is performed by supplying a nitriding gas into the processing chamber and generating a plasma from the nitriding gas.2. The method of claim 1 , wherein the TiN film having the reduced stress is formed by reducing a tensile stress of the TiN unit film formed in the step of forming the TiN unit film during the step of performing the plasma nitriding process.3. The method of claim 1 , wherein the number of repeating the step of forming the TiN unit film and the step of performing the plasma nitriding process is set in ...

VACUUM-INTEGRATED HARDMASK PROCESSES AND APPARATUS

Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. For example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as EUV lithography. 1. An apparatus for conducting photoresist-less metal mask formation , the apparatus comprising:a metal-containing film deposition module;a metal-containing film patterning module;a vacuum transfer module connecting the deposition module and the patterning module.2. The apparatus of claim 1 , wherein:the deposition module comprises reactor chamber for depositing a photosensitive metal halide or organometallic compound film; andthe patterning module comprises a photolithography tool with a source of sub-30 nm wavelength radiation.3. The apparatus of claim 1 , wherein the patterning module is a EUV lithography tool.4. The apparatus of claim 1 , wherein the patterning module has a source of a patterning agent selected from the group consisting of photons claim 1 , electrons claim 1 , protons claim 1 , ions and neutral species such that the metal-containing film can be patterned by exposure to the patterning agent.5. The apparatus of claim 1 , further comprising an ingoing load lock for transferring a substrate from the patterning module to the vacuum transfer module claim 1 , and an outgoing load lock for transferring a substrate to the patterning module from the vacuum transfer module; and wherein the outgoing load lock functions as an outgassing module.6. The apparatus of claim 1 , further comprising a controller including instructions for conducting ...

Formation of Antireflective Surfaces

Technologies are described for methods and systems effective for etching nanostructures in a substrate. The methods may comprise depositing a patterned block copolymer on the substrate. The patterned block copolymer may include first and second polymer block domains. The methods may comprise applying a precursor to the patterned block copolymer to generate an infiltrated block copolymer. The precursor may infiltrate into the first polymer block domain and generate a material in the first polymer block domain. The methods may comprise applying a removal agent to the infiltrated block copolymer to generate a patterned material. The removal agent may be effective to remove the first and second polymer block domains from the substrate. The methods may comprise etching the substrate. The patterned material on the substrate may mask the substrate to pattern the etching. The etching may be performed under conditions to produce nanostructures in the substrate.

Mask blank, transfer mask, method for manufacturing transfer mask, and method for manufacturing semiconductor device

A mask blank is provided, by which an alignment mark can be formed between a transparent substrate and a laminated structure of a light semitransmissive film, etching stopper film, and light shielding film during manufacture of a transfer mask. The mask blank 100 comprises a structure in which the light semitransmissive film 2, etching stopper film 3, light shielding film 4, and etching mask film 5 are laminated in said order on the transparent substrate 1; the light semitransmissive film 2 and light shielding film 3 are made of a material which can be dry etched with a fluorine-based gas; the etching stopper film and etching mask film are made of a material containing chromium; and when a thickness of the etching stopper film is Ds, an etching rate of the etching stopper film with respect to an oxygen-containing chlorine-based gas is Vs, a thickness of the etching mask film is Dm, and an etching rate of the etching mask film with respect to the oxygen-containing chlorine-based gas is Vm, a relationship: (Dm/Vm)>(Ds/Vs) is satisfied.

PHOTOMASK BLANK AND PHOTOMASK

A photomask blank for an exposure light of ArF excimer laser, including a transparent substrate and a light-shielding film containing molybdenum, silicon, and nitrogen. The light-shielding film is formed in a single layer or a multilayer composed of a single composition layer or a composition gradient layer, a reflectance of the light-shielding film on a side remote from the substrate is 40% or less, and among the refractive indexes at the surfaces on the substrate side and the side remote from the substrate of all layers, a difference between the highest and lowest refractive indexes is 0.2 or less, and among the extinction coefficients at the surfaces, a difference between the highest and lowest extinction coefficients is 0.5 or less. The light-shielding film assumes a satisfactory and undeteriorated sectional shape of a mask pattern in an etching process in mask processing or defect correcting. 1. A photomask blank comprising:a transparent substrate; anda light-shielding film comprising molybdenum, silicon, and nitrogen, whereinexposure light is ArF excimer laser light,the light-shielding film is formed in a single layer or a multilayer consisting of two or more layers, the layer is composed of a single composition layer having a constant composition in a thickness direction or a composition gradient layer having a continuously varying composition in the thickness direction,a reflectance to the exposure light of the light-shielding film on a side remote from the substrate is 40% or less,in a case where the light-shielding film is a single layer composed of the composition gradient layer in which the composition continuously varies in the thickness direction, a difference of refractive indexes n to the exposure light between a surface on the substrate side and a surface on a side remote from the substrate is 0.2 or less and a difference of extinction coefficients k to the exposure light between a surface on the substrate side and a surface on a side remote from ...

METHODS OF FABRICATING SEMICONDUCTOR DEVICE

A method of fabricating a semiconductor device includes forming a device isolation layer in a substrate to define active regions, forming a conductive layer on the active regions, forming first mask patterns intersecting the active regions on the conductive layer, etching the conductive layer using the first mask patterns as etch masks to form bit lines, growing second mask patterns from top surfaces of the first mask patterns, and performing a patterning process using the second mask patterns as etch masks to form contact holes exposing the active regions between the bit lines. 1. A method of fabricating a semiconductor device , the method comprising:defining active regions by forming a device isolation layer in a substrate;forming a conductive layer on the active regions;forming first mask patterns intersecting the active regions on the conductive layer;forming bit lines by etching the conductive layer using the first mask patterns as etch masks;growing second mask patterns on surfaces of the first mask patterns that are opposite to the substrate; andforming contact holes by performing a patterning process using the second mask patterns as etch masks exposing the active regions between the bit lines.2. The method of claim 1 , further comprising:filling the contact holes with a conductive material; andforming storage node contacts by performing an etch-back process on the conductive material,wherein at least a portion of the second mask patterns is removed during the etch-back process.3. The method of claim 2 , further comprising:forming capacitors on the storage node contacts.4. The method of claim 3 , further comprising:forming landing pads between the storage node contacts and the capacitors.5. The method of claim 1 , wherein a thickness of one or more of the second mask patterns ranges from about 25% to about 50% of a thickness of one or more of the first mask patterns.6. The method of claim 1 , wherein the second mask patterns are locally formed on the ...

ULTRA-CONFORMAL CARBON FILM DEPOSITION LAYER-BY-LAYER DEPOSITION OF CARBON-DOPED OXIDE FILMS

Embodiments of the invention relate to deposition of a conformal carbon-based material. In one embodiment, the method comprises depositing a sacrificial dielectric layer with a predetermined thickness over a substrate, forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate, introducing a hydrocarbon source, a plasma-initiating gas, and a dilution gas into the processing chamber, wherein a volumetric flow rate of hydrocarbon source: plasma-initiating gas: dilution gas is in a ratio of 1:0.5:20, generating a plasma at a deposition temperature of about 300 C to about 500 C to deposit a conformal amorphous carbon layer on the patterned features and the exposed upper surface of the substrate, selectively removing the amorphous carbon layer from an upper surface of the patterned features and the upper surface of the substrate, and removing the patterned features. 1. A method of forming a conformal amorphous carbon layer on a substrate in a processing chamber , comprising:depositing a dielectric layer on a substrate;depositing a sacrificial dielectric layer on an upper surface of the dielectric layer;forming a pattern into the sacrificial dielectric layer by removing portions of the sacrificial dielectric layer to expose portions of the upper surface of the dielectric layer;introducing a hydrocarbon source, a plasma-initiating gas, and a dilution gas into the processing chamber, wherein a volumetric flow rate of hydrocarbon source:plasma-initiating gas:dilution gas is in a ratio of 1:0.5:20;generating a plasma in the processing chamber to deposit a conformal amorphous carbon layer on the portions of the upper surface of the dielectric layer and on remaining portions of the sacrificial dielectric layer;selectively removing the amorphous carbon layer using an anisotropic etching process to expose upper surfaces of the remaining portions of the sacrificial dielectric layer and to expose ...

SEMICONDUCTOR STRUCTURE AND METHODS OF FORMING THE SAME

A semiconductor structure and method of forming the same are provided. The method includes: forming a plurality of mandrel patterns over a dielectric layer; forming a first spacer and a second spacer on sidewalls of the plurality of mandrel patterns, wherein a first width of the first spacer is larger than a second width of the second spacer; removing the plurality of mandrel patterns; patterning the dielectric layer using the first spacer and the second spacer as a patterning mask; and forming conductive lines laterally aside the dielectric layer. 1. A method of forming a semiconductor structure , comprising:forming a plurality of mandrel patterns over a dielectric layer;forming a first spacer and a second spacer on sidewalls of the plurality of mandrel patterns, wherein a first width of the first spacer is larger than a second width of the second spacer;removing the plurality of mandrel patterns;patterning the dielectric layer using the first spacer and the second spacer as a patterning mask; andforming conductive lines laterally aside the dielectric layer.2. The method of claim 1 , wherein patterning the dielectric layer comprises forming a first dielectric pattern defined by the first spacer and a second dielectric pattern defined by the second spacer.3. The method of claim 2 , wherein forming the conductive lines comprises:forming first conductive lines spaced apart by the first dielectric pattern therebetween; andforming second conductive lines spaced apart by the second dielectric pattern therebetween,wherein a first spacing between the first conductive lines is larger than a second spacing between the second conductive lines.4. The method of claim 1 , further comprising forming a hard mask structure between the dielectric layer and the plurality of mandrel patterns claim 1 , wherein patterning the dielectric layer comprises:patterning the hard mask structure to transfer patterns of the first spacer and the second spacer into the hard mask structure, thereby ...

INTEGRATED CIRCUIT FABRICATION

A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width. 1. (canceled)2. A method for integrated circuit fabrication , comprising:forming a plurality of loops of masking material over a substrate;depositing a selectively definable material over the loops; andpatterning the selectively definable material to expose expanses of the loops between ends of the loops,wherein the ends remain covered by the selectively definable material after patterning, wherein an entire width of a portion of the masking material at the ends is covered by the selectively definable material,wherein patterning defines features in the selectively definable material, the features spaced apart from the loops and having a minimum width larger than a minimum width of the masking material forming the loops.3. The method of claim 2 , wherein forming the plurality of loops forms pairs of parallel runs of the masking material claim 2 , each pair of parallel runs joining at the ends of the loops.4. The method of claim 3 , wherein claim 3 , after patterning claim 3 , the selectively definable material extends completely over the ends of at least some of the loops claim 3 , the selectively definable material extending completely from a portion of one run of the masking material to a portion of another claim 3 , ...

METHODS OF REMOVING RESIDUAL POLYMERS FORMED DURING A BORON-DOPED AMORPHOUS CARBON LAYER ETCH PROCESS

Methods for removing residual polymers formed during etching of a boron-doped amorphous carbon layer are provided herein. In some embodiments, a method of etching a feature in a substrate includes: exposing a boron doped amorphous carbon layer disposed on the substrate to a first plasma through a patterned mask layer to etch a feature into the boron doped amorphous carbon layer, wherein the first plasma is formed from a first process gas that reacts with the boron doped amorphous carbon layer to form residual polymers proximate a bottom of the feature; and exposing the residual polymers to a second plasma through the patterned mask layer to etch the residual polymers proximate the bottom of the feature, wherein the second plasma is formed from a second process gas comprising nitrogen (N), oxygen (O), hydrogen (H), and methane (CH). 1. A method of etching a feature in a substrate , comprising:exposing a boron doped amorphous carbon layer disposed on the substrate to a first plasma through a patterned mask layer to etch a feature into the boron doped amorphous carbon layer, wherein the first plasma is formed from a first process gas that reacts with the boron doped amorphous carbon layer to form residual polymers proximate a bottom of the feature; and{'sub': 2', '2', '2', '4, 'exposing the residual polymers to a second plasma through the patterned mask layer to etch the residual polymers proximate the bottom of the feature, wherein the second plasma is formed from a second process gas comprising nitrogen (N), oxygen (O), hydrogen (H), and methane (CH).'}2. The method of claim 1 , wherein the first process gas comprises one of a fluorine-containing gas or a chlorine-containing gas.3. The method of claim 1 , wherein the second plasma forms hydroxylamine (NHOH) to react with the residual polymers proximate the bottom of the feature.4. The method of claim 1 , further comprising forming the first plasma by igniting the first process gas using an RF power source.5. The ...

PATTERN FORMING METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

In a manufacturing method of a semiconductor device according to an embodiment, a processing target film is formed above a substrate. A buffer layer in a polycrystalline state or an amorphous state is formed on the processing target film. A mask material is formed on the buffer layer. The processing target film is etched using the mask material as a mask. The buffer layer has an etching rate smaller than the processing target film. 1. A manufacturing method of a semiconductor device , the method comprising:forming a first film above a substrate;forming a buffer layer in a polycrystalline state or an amorphous state on the first film;forming a mask material on the buffer layer; andetching the first film using the mask material as a mask, whereina grain size of crystals of the mask material is larger than a grain size of crystals of the buffer layer, andthe grain of the mask material is formed through the mask material from a front face to a rear face of the mask material.2. The method of claim 1 , whereinthe mask material has a grain boundary in a film thickness direction of the mask material, andthe buffer layer suppresses etching gas passing through the grain boundary of the mask material from reaching the first film.3. The method of claim 1 , wherein the first film is a silicon dioxide film.4. The method of claim 2 , wherein the first film is a silicon dioxide film.5. The method of claim 1 , wherein the mask material is formed of any of tungsten claim 1 , aluminum claim 1 , titanium claim 1 , and tantalum.6. The method of claim 2 , wherein the mask material is formed of any of tungsten claim 2 , aluminum claim 2 , titanium claim 2 , and tantalum.7. The method of claim 1 , wherein the buffer layer is formed of any of a tungsten nitride claim 1 , a tungsten silicide claim 1 , and an aluminum oxide.8. The method of claim 2 , wherein the buffer layer is formed of any of a tungsten nitride claim 2 , a tungsten silicide claim 2 , and an aluminum oxide.9. The method of ...

Manufacturing Method of Semiconductor Device

According to an embodiment, a manufacturing method of a semiconductor device includes: forming a first film on a processing target by using a first material; forming a second film on the first film by using a second material; selectively removing the second and first films to provide an opening pierced in the second and first films; selectively forming a metal film on an inner surface of the opening in the first film; and processing the processing target by using the metal film as a mask. 1. A manufacturing method of a semiconductor device comprising:forming a first film on a processing target by using a first material;forming a second film on the first film by using a second material;selectively removing the second and first films to provide an opening pierced in the second and first films;selectively forming a metal film on an inner surface of the opening in the first film; andprocessing the processing target by using the metal film as a mask.2. The method of claim 1 ,wherein the first material is a material to which metal atoms of the metal film precipitate, andthe second material is a material to which the metal atoms of the metal film do not precipitate.3. The method of claim 2 ,wherein the first material is carbon (C) or (Si), andthe second material is a silicon oxide film (SiO2).4. The method of claim 1 ,wherein the metal film is formed by electroless plating.5. The method of claim 4 ,wherein the metal film is formed by subjecting palladium (Pd) to electroless plating.6. The method of claim 1 ,wherein the processing target comprises a surface layer made of a material to which metal atoms of the metal film precipitate, andthe method further comprises forming a third film between the processing target and the first film by using a material to which metal atoms of the metal film do not precipitate.7. The method of claim 4 , further comprising:modulating growth selectively of a metal by pretreatment using an SAM before forming the metal film.8. The method of ...

METHOD OF FORMING A PATTERN IN A SEMICONDUCTOR DEVICE AND METHOD OF FORMING A GATE USING THE SAME

A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized. 1. A method of manufacturing a semiconductor device , comprising:forming an object layer on a substrate;forming a first pattern on the object layer in a first region of the substrate, the first pattern having a plurality of spacers that are spaced apart from and parallel with each other;forming a second pattern on the object layer in a second region of the substrate; andpatterning the object layer on the substrate using the first and second patterns as a mask, respectively.2. The method of claim 1 , wherein the object layer includes a conductive layer claim 1 , so that first and second conductive patterns are formed on the substrate corresponding to the first and second patterns claim 1 , respectively.3. The method of claim 1 , wherein forming the first pattern includes:forming a buffer pattern on the object layer;forming the spacers on sidewalls of the buffer pattern; andremoving the buffer pattern from the object layer of the substrate, so that the spacers remain on the object layer and spaced apart from each other.4. The method of claim 3 , wherein forming the buffer pattern includes:forming a buffer layer on the object ...

SELF ALIGNED CONDUCTIVE LINES WITH RELAXED OVERLAY

A method for forming conductive lines comprises forming a hardmask on an insulator layer, a planarizing layer on the hardmask, and a hardmask on the planarizing layer, removing exposed portions of a layer of sacrificial mandrel material to form first and second sacrificial mandrels on the hardmask, and depositing a layer of spacer material in the gap, and over exposed portions of the first and second sacrificial mandrels and the hardmask. Portions of the layer of spacer material are removed to expose the first and second sacrificial mandrels. A filler material is deposited between the first and second sacrificial mandrels. A portion of the filler material is removed to expose the first and second sacrificial mandrels. Portions of the layer of spacer material are removed to expose portions of the hardmask. A trench is formed in the insulator layer, and the trench is filled with a conductive material. 1. A semiconductor structure , comprising:a first hardmask on an insulator layer;a planarizing layer on the first hardmask;a second hardmask on a portion of the planarizing layer;a third hardmask on the planarizing layer and on the second hardmask;sacrificial mandrels on portions of the second hardmask and on portions of the third hardmask;a fourth hardmask on the sacrificial mandrels;spacer material on portions of the second hardmask and on portions of the third hardmask; anda mandrel including the spacer material on the third hardmask; andan organic planarizing layer on the third hardmask, on the spacer material, on the sacrificial mandrels, and on the mandrel including the spacer material.2. The semiconductor structure of claim 1 , wherein the second hardmask is on only a portion of the planarizing layer.3. The semiconductor structure of claim 2 , wherein the sacrificial mandrels are on only portions of the second hardmask and on only portions of the third hardmask.4. (canceled)5. The semiconductor structure of claim 1 , wherein the spacer material is on the third ...