Настройки

Укажите год
-

Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

Подробнее
-

Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

Подробнее

Форма поиска

Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
Ведите корректный номера.
Ведите корректный номера.
Ведите корректный номера.
Ведите корректный номера.
Укажите год
Укажите год
Применить Всего найдено 353. Отображено 100.
21-03-2013 дата публикации

Nitride semiconductor device

Номер: US20130072010A1
Автор: Giichi Marutsuki, Kentaro Watanabe, Shunsuke Minato
Принадлежит: Nichia Corp

A nitride semiconductor device includes a silicon substrate, a nitride semiconductor layer formed on the silicon substrate, and metal electrodes formed in contact with the silicon substrate. The metal electrodes has first metal layers which are formed in a shape of discrete islands and in contact with the silicon substrate, and second metal layers which are in contact with the silicon substrate exposed among the islands of the first metal layers and are formed to cover the first metal layers. Further, the second metal layers are made of a metal capable of forming ohmic contact with silicon, and the first metal layers are made of an alloy containing a metal and silicon, in which the metal is different than that in the second metal layer.

Подробнее
Номер записи: 1
30-05-2013 дата публикации

METHOD FOR FABRICATING BURIED GATES USING PRE LANDING PLUGS

Номер: US20130137258A1
Автор: PARK Jum-Yong, SHIN Jong-Han
Принадлежит: SK HYNIX INC.

A method for fabricating a semiconductor device is provided, the method includes forming a plug conductive layer over an entire surface of a substrate, etching the plug conductive layer to form landing plugs, etching the substrate between the landing plugs to form a trench, forming a gate insulation layer over a surface of the trench and forming a buried gate partially filling the trench over the gate insulation layer. 141-. (canceled)42. A method for fabricating a semiconductor device , comprising:forming a plug conductive layer over an entire surface of a substrate;etching the plug conductive layer to form landing plugs;etching the substrate between the landing plugs to form a trench;forming a gate insulation layer over the etched substrate;forming a buried gate over the gate insulation layer to fill a lower portion of the trench; andforming a sealing layer over the buried gate to fill an upper portion of the trench.43. The method of claim 42 , further comprising:forming a contact hole exposing a surface of each of the landing plugs.44. The method of claim 42 , wherein the sealing layer comprises one selected from the group consisting of an oxide layer claim 42 , a nitride layer and a double-layered structure comprising a nitride layer and an oxide layer.45. The method of claim 42 , wherein the plug conductive layer comprises a metal layer or a polysilicon layer.46. The method of claim 42 , wherein the forming of each of the landing plugs and the trench is performed by using a hard mask layer as an etch barrier.47. A method for fabricating a semiconductor device claim 42 , comprising:forming a device isolation layer in a substrate;forming a plug conductive layer over an entire surface of the substrate;etching the plug conductive layer to form landing plugs;etching the substrate between the landing plugs to form a trench;forming a gate insulation layer over the etched substrate;forming a buried gate over the gate insulation layer to fill a lower portion of the ...

Подробнее
Номер записи: 2
06-06-2013 дата публикации

TRENCH SCHOTTKY DIODE AND MANUFACTURING METHOD THEREOF

Номер: US20130140630A1
Автор: CHEN TZU-HSIUNG
Принадлежит:

A trench Schottky diode and a manufacturing method thereof are provided. The manufacturing method includes the following steps. Firstly, a semiconductor substrate is provided. A multi-trench structure including a wide trench and a plurality of narrow trenches is formed in the semiconductor substrate, a gate oxide layer is formed on a surface of the multi-trench structure, and a polysilicon structure is formed over the gate oxide layer and the first oxide layer. The polysilicon structure is etched to partially expose the first oxide layer and the gate oxide layer on a bottom surface of the wide trench. The semiconductor substrate, the polysilicon structure and the gate oxide layer are partially exposed by a photolithography and etching process. A metal sputtering layer is formed. Afterwards, the metal sputtering layer is etched to expose a part of the second oxide layer. 2. The method as claimed in claim 1 , wherein the semiconductor substrate comprises a heavily-doped (N+ type) silicon layer and a lightly-doped (N type) epitaxial layer.4. The method as claimed in claim 3 , wherein the first photoresist pattern corresponds to a profile of the multi-trench structure.6. The method as claimed in claim 1 , wherein the polysilicon structure is formed on the gate oxide layer and the first oxide layer by a chemical vapor deposition process.9. The method as claimed in claim 8 , wherein the first metal layer is made of titanium claim 8 , and the second metal layer is made of aluminum/silicon/copper alloy.10. The method as claimed in claim 8 , wherein further comprising a step of performing a rapid thermal processing to correct a result of the metal sputtering process.12. The method as claimed in claim 8 , wherein further comprising a step of performing a sintering process to facilitate adhesion of the metal sputtering layer onto the second oxide layer claim 8 , the semiconductor substrate claim 8 , the polysilicon structure and the gate oxide layer.13. A trench Schottky diode ...

Подробнее
Номер записи: 3
06-02-2014 дата публикации

Transistor having replacement metal gate and process for fabricating the same

Номер: US20140035068A1
Автор: Dechao Guo, Keith Kwong Hon Wong
Принадлежит: International Business Machines Corp

A transistor is fabricated by removing a polysilicon gate over a doped region of a substrate and forming a mask layer over the substrate such that the doped region is exposed through a hole within the mask layer. An interfacial layer is deposited on top and side surfaces of the mask layer and on a top surface of the doped region. A layer adapted to reduce a threshold voltage of the transistor and/or reduce a thickness of an inversion layer of the transistor is deposited on the interfacial layer. The layer includes metal, such as aluminum or lanthanum, which diffuses into the interfacial layer, and also includes oxide, such as hafnium oxide. A conductive plug, such as a metal plug, is formed within the hole of the mask layer. The interfacial layer, the layer on the interfacial layer, and the conductive plug are a replacement gate of the transistor.

Подробнее
Номер записи: 4
06-03-2014 дата публикации

OXYGEN SCAVENGING SPACER FOR A GATE ELECTRODE

Номер: US20140065783A1
Автор: Chudzik Michael P., NAIR Deleep R., Narayanan Vijay, Radens Carl J., Shah Jay M.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

At least one layer including a scavenging material and a dielectric material is deposited over a gate stack, and is subsequently anisotropically etched to form a oxygen-scavenging-material-including gate spacer. The oxygen-scavenging-material-including gate spacer can be a scavenging-nanoparticle-including gate spacer or a scavenging-island-including gate spacer. The scavenging material is distributed within the oxygen-scavenging-material-including gate spacer in a manner that prevents an electrical short between a gate electrode and a semiconductor material underlying a gate dielectric. The scavenging material actively scavenges oxygen that diffuses toward the gate dielectric from above, or from the outside of, a dielectric gate spacer that can be formed around the oxygen-scavenging-material-including gate spacer. 1. A method of forming a semiconductor structure comprising:forming a gate stack comprising a gate dielectric and a gate electrode on a semiconductor substrate; andforming an oxygen-scavenging-material-including gate spacer around said gate stack and directly on said semiconductor substrate.2. The method of claim 1 , wherein said gate electrode is not electrically shorted to a semiconductor material located in said semiconductor substrate and contacting said gate dielectric.3. The method of claim 1 , wherein said gate dielectric is formed by depositing a dielectric metal oxide having a dielectric constant greater than 8.0.4. The method of claim 1 , wherein said oxygen-scavenging-material-including gate spacer is formed as a scavenging-nanoparticle-including gate spacer in which nanoparticles comprising a scavenging metal are embedded in a dielectric material.5. The method of claim 1 , wherein said oxygen-scavenging-material-including gate spacer is formed as a scavenging-island-including gate spacer in which multiple scavenging islands that do not contact one another are embedded in a dielectric material layer.6. The method of claim 1 , further comprising ...

Подробнее
Номер записи: 5
01-01-2015 дата публикации

METHODS OF FABRICATING A SEMICONDUCTOR DEVICE INCLUDING FINE PATTERNS

Номер: US20150004774A1
Автор: KANG Chun Soo
Принадлежит:

Methods of fabricating a semiconductor device are provided. The method includes forming active lines in a semiconductor substrate, forming contact lines generally crossing over the active lines, forming line-shaped etch mask patterns generally crossing over the active lines and the contact lines, etching the contact lines exposed by the line-shaped etch mask patterns to form contact separation grooves and to form contact patterns generally remaining at intersections between the line-shaped etch mask patterns and the active lines, etching the active lines exposed by the contact separation grooves to form active separation grooves that generally divide each of the active lines into a plurality of active patterns, forming gates that substantially intersect the active patterns, and forming bit lines electrically connected to the contact patterns. 1. A method of fabricating a semiconductor device , the method comprising:forming a first isolation layer in a semiconductor substrate to define active lines;forming pseudo contact lines generally crossing over the active lines and a first interlayer insulation layer substantially filling spaces between the pseudo contact lines;forming line-shaped etch mask patterns generally crossing over the active lines and the pseudo contact lines;etching the pseudo contact lines exposed by the line-shaped etch mask patterns to form contact separation grooves and to form pseudo contact patterns generally remaining at intersections between the line-shaped etch mask patterns and the active lines;etching the active lines exposed by the contact separation grooves to form active separation grooves that generally divide each of the active lines into a plurality of active patterns;forming a third isolation layer substantially filling the active separation grooves;forming gates that substantially intersect the active patterns;removing the pseudo contact patterns to form contact holes;forming contact patterns substantially filling the contact holes; ...

Подробнее
Номер записи: 6
05-01-2017 дата публикации

METHOD TO IMPROVE RELIABILITY OF REPLACEMENT GATE DEVICE

Номер: US20170005179A1
Автор: Ando Takashi, Cartier Eduard A., Choi Kisik, Narayanan Vijay
Принадлежит:

A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill. 1. A method of fabricating a gate stack for a semiconductor device , said method comprising steps of: depositing a sacrificial layer over a thin metal layer;', 'performing a first rapid thermal anneal of the replacement gate structure at a high temperature of not less than 800° C.;', 'performing a millisecond anneal; and', 'removing the sacrificial layer., 'providing a replacement gate structure by performing step of2. The method of wherein performing the first rapid thermal anneal comprises annealing at a temperature between 800° C. and 1100° C. claim 1 , inclusive.3. The method further comprising claim 1 , after the step of removing the sacrificial layer:removing the thin metal layer;performing a second rapid thermal anneal at a temperature between 400° C. and 800° C., inclusive; andre-depositing a thin metal layer.4. The method of wherein depositing the sacrificial layer comprises depositing a layer selected from poly-crystalline silicon and amorphous silicon. This application is a division of, and claims priority to copending U.S. patent application Ser. No. 14/595,756, filed on Jan. 13, 2015, which was in turn a division of issued U.S. Pat. No. 8,999,831 issued on Apr. 7, 2015, both incorporated by reference in their entirety, and wherein such applications were made by, on behalf of, and/or in connection with the following parties to a joint research agreement: International Business Machines Corporation and GlobalFoundries. The agreement was in effect on and before the date the claimed invention ...

Подробнее
Номер записи: 7
07-01-2016 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20160005739A1
Автор: HAN SHINHEE, LEE KILHO
Принадлежит:

A semiconductor memory device includes a first insulating layer covering a substrate, a first contact plug and a second contact plug each penetrating the first insulating layer, a first data storage element disposed on the first contact plug, and a second data storage element disposed on the second contact plug. The first contact plug includes a vertically extending portion and a horizontally extending portion arranged between the vertically extending portion and the first data storage element, and the second contact plug extends substantially vertically from a top surface of the substrate. The first data storage element is laterally spaced apart from the vertically extending portion when viewed in plan view. The first data storage element is disposed on the horizontally extending portion. 1. A semiconductor memory device comprising:a first insulating layer covering a substrate;a first contact plug and a second contact plug, each penetrating the first insulating layer;a first data storage element disposed on the first contact plug and electrically connected to a portion of the substrate through the first contact plug; anda second data storage element disposed on and overlapping the second contact plug and electrically connected to a portion of the substrate through the second contact plug, a vertically extending portion; and', 'a horizontally extending portion arranged between the vertically extending portion and the first data storage element,, 'wherein the first contact plug compriseswherein the second contact plug vertically extends from a top surface of the substrate,wherein the first data storage element is laterally spaced apart from the vertically extending portion when viewed in plan view, andwherein the first data storage element is disposed on the horizontally extending portion.2. The semiconductor memory device of claim 1 , wherein the first insulating layer includes a recessed region that is disposed in an upper portion of the first insulating layer ...

Подробнее
Номер записи: 8
03-01-2019 дата публикации

PREVENTING THRESHOLD VOLTAGE VARIABILITY IN STACKED NANOSHEETS

Номер: US20190006462A1
Автор: Guillorn Michael A., Loubet Nicolas J.
Принадлежит:

Embodiments are directed to a method of forming a stacked nanosheet and resulting structures having equal thickness work function metal layers. A nanosheet stack is formed on a substrate. The nanosheet stack includes a first sacrificial layer formed on a first nanosheet. A hard mask is formed on the first sacrificial layer and the first sacrificial layer is removed to form a cavity between the hard mask and the first nanosheet. A work function layer is formed to fill the cavity between the hard mask and the first nanosheet. 1. A semiconductor device comprising:a nanosheet stack formed over a substrate, the nanosheet stack comprising a first nanosheet vertically stacked between a top work function layer and a bottom work function layer;a gate formed over a channel region of the nanosheet stack; anda conductive layer formed between the gate and the top work function layer;wherein a thickness of the top work function layer is substantially equal to a thickness of the bottom work function layer.2. The semiconductor device of claim 1 , wherein the conductive layer comprises tungsten or cobalt.3. The semiconductor device of claim 1 , wherein the conductive layer comprises a thickness of about 10 nm.4. The semiconductor device of claim 1 , wherein the nanosheet stack further comprises a plurality of nanosheets alternating with a plurality of sacrificial layers.5. The semiconductor of claim 4 , wherein each pair of adjacent nanosheets is separated by a sacrificial layer.6. The semiconductor of claim 5 , wherein a thickness of each sacrificial layer is substantially equal.7. The semiconductor device of claim 4 , wherein each nanosheet of the nanosheet stack has a thickness of about 4 nm to about 10 nm.8. The semiconductor device of claim 1 , wherein the thickness of the top and bottom work function layers is about 10 nm.9. The semiconductor device of claim 1 , wherein the thickness of the top and bottom work function layers is about 6 nm.10. The semiconductor device of claim ...

Подробнее
Номер записи: 9
21-01-2016 дата публикации

RECESS TECHNIQUE TO EMBED FLASH MEMORY IN SOI TECHNOLOGY

Номер: US20160020219A1
Автор: CHUANG Harry-Hak-Lay, Wu Wei Cheng, YOU Kai-Shyang
Принадлежит:

Some embodiments of the present disclosure provide an integrated circuit arranged on a silicon-on-insulator (SOI) substrate region. The SOI substrate region is made up of a handle wafer region, an oxide layer arranged over the handle wafer region, and a silicon layer arranged over the oxide layer. A recess extends downward from an upper surface of the silicon layer and terminates in the handle wafer region, thereby defining a recessed handle wafer surface and sidewalls extending upwardly from the recessed handle wafer surface to meet the upper surface of the silicon layer. A first semiconductor device is disposed on the recessed handle wafer surface. A second semiconductor device is disposed on the upper surface of the silicon layer. 1. An integrated circuit (IC) comprising:a silicon-on-insulator (SOI) substrate region made up of a handle wafer region, an oxide layer arranged over the handle wafer region, and a silicon layer arranged over the oxide layer;a recess extending downward from an upper surface of the silicon layer and terminating in the handle wafer region, thereby defining a recessed handle wafer surface and sidewalls extending upwardly from the recessed handle wafer surface to meet the upper surface of the silicon layer;a first semiconductor device disposed on the recessed handle wafer surface; anda second semiconductor device disposed on the upper surface of the silicon layer.2. The IC of claim 1 , wherein the first semiconductor device includes a first gate having a first gate top surface and wherein the second semiconductor device includes a second gate having a second gate top surface claim 1 , wherein the first gate top surface is co-planar with the second gate top surface.3. The IC of claim 1 , further comprising: a dielectric spacer arranged on the sidewalls of the recess and extending vertically from over the recessed handle wafer surface past the oxide layer and alongside the silicon layer.4. The IC of claim 1 , wherein the first semiconductor ...

Подробнее
Номер записи: 10
24-04-2014 дата публикации

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH OFFSET SIDEWALL STRUCTURE

Номер: US20140113418A1
Автор: Oda Hidekazu, OTA Kazunobu, Sayama Hirokazu
Принадлежит: RENESAS ELECTRONICS CORPORATION

A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate () in a low-voltage NMOS region (LNR) thereby to form extension layers (). Then, a silicon oxide film (OX) is formed to cover the whole surface of the silicon substrate (). The silicon oxide film (OX) on the side surfaces of gate electrodes (-) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate () in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers () later to be extension layers (). 19-. (canceled)10. A method of manufacturing a semiconductor device including a first n-type MISFET formed in a first region of a semiconductor substrate , a first p-type MISFET formed in a second region of the semiconductor substrate , a second n-type MISFET formed in a third region of the semiconductor substrate and having a thicker gate insulating film than the first n-type MISFET , and a second p-type MISFET formed in a fourth region of the semiconductor substrate and having a thicker gate insulating film than the first p-type MISFET , comprising steps of:(a) forming a gate insulating film of the first n-type MISFET over the first region, and forming a gate insulating film of the first p-type MISFET over the second region;(b) forming a first gate electrode over the gate insulating film of the first n-type MISFET, and forming a second gate electrode over the gate insulating film of the first p-type MISFET;(c) after the step (b), forming first insulating films over side surfaces of the first gate electrode and over side surfaces of the second gate ...

Подробнее
Номер записи: 11
28-01-2021 дата публикации

CELL LAYOUTS FOR MOS-GATED DEVICES FOR IMPROVED FORWARD VOLTAGE

Номер: US20210028279A1
Автор: Akiyama Hidenori, Blanchard Richard A., Rodov Vladimir, Tworzydlo Woytek
Принадлежит:

An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n− epi layer, a p-well, trenched insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The device may be formed of a matrix of cells or may be interdigitated. To turn the device on, a positive voltage is applied to the gate, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for rapidly turning the device off. The p-channel MOSFET may be made a depletion mode device by implanting boron ions at an angle into the trenches to create a p-channel. This allows the IGTO device to be turned off with a zero gate voltage while in a latch-up condition, when the device is acting like a thyristor. 120-. (canceled)21. An electronic device formed as a die comprising:a semiconductor material; one or more trenches in the semiconductor material, the one or more trenches having sidewalls;', 'a first p-type region abutting at least a bottom of the one or more trenches;', 'a plurality of elongated first n-type regions overlying the first p-type region, the first n-type regions abutting the trench sidewalls, wherein each of the first n-type regions is substantially surrounded by a trench, the first n-type regions having a first top surface;', 'a first dielectric layer having an elongated contact opening that exposes portions of the first top surface of the first n-type regions, the contact opening having long sides and short sides, the long sides of the contact opening being substantially perpendicular to the elongated first n-type regions and extending over multiple ones of the first n-type regions;', 'a cathode electrode electrically contacting the first top surface of the first n-type regions through the contact opening;', 'a dielectric layer along the sidewalls of the one or more trenches; and', 'a conductive material at least partially filling ...

Подробнее
Номер записи: 12
19-02-2015 дата публикации

METHOD FOR MANUFACTURING RECTIFIER WITH VERTICAL MOS STRUCTURE

Номер: US20150050791A1
Автор: Chen Mei-Ling, Kuo Hung-Hsin
Принадлежит:

A method for manufacturing a rectifier with a vertical MOS structure is provided. A first multi-trench structure and a first mask layer are formed at a first side of the semiconductor substrate. A second multi-trench structure is formed in the second side of the semiconductor substrate. A gate oxide layer, a polysilicon structure and a metal sputtering layer are sequentially formed on the second multi-trench structure. The rectifier further includes a wet oxide layer and a plurality of doped regions. The wet oxide layer is formed on a surface of the first multi-trench structure and in the semiconductor substrate. The doping regions are formed on a region between the semiconductor substrate and the second multi-trench structure, and located beside the mask layer. The metal sputtering layer is formed on the first mask layer corresponding to the first multi-trench structure. 1. A method for manufacturing a rectifier with a vertical MOS structure , the method comprising steps of:providing a semiconductor substrate;forming a first multi-trench structure and a first mask layer at a first side of the semiconductor substrate;forming a second mask layer on a second side of the semiconductor substrate and the first mask layer;etching the semiconductor substrate according to the second mask layer, thereby forming a second multi-trench structure in the second side of the semiconductor substrate;forming a gate oxide layer on a surface of the second multi-trench structure;forming a polysilicon structure on the gate oxide layer and the second mask layer;etching the polysilicon structure, and performing a wet dip etch to thin the second mask layer;performing an ion implantation process to dope a region between the semiconductor substrate and the second multi-trench structure, thereby forming a plurality of doped regions in the semiconductor substrate;removing the second mask layer;forming a metal sputtering layer on the doped regions, the gate oxide layer, the polysilicon structure ...

Подробнее
Номер записи: 13
14-02-2019 дата публикации

Manufacturing method of integrated circuit

Номер: US20190051530A1
Автор: Chao-Sheng Cheng
Принадлежит: United Microelectronics Corp

A manufacturing method of an integrated circuit includes following steps. A dummy gate with a first mask structure formed thereon and a semiconductor gate with a second mask structure formed thereon are formed on a substrate. A top surface of the semiconductor gate is lower than a top surface of the dummy gate. A first removing process is performed to remove the first mask structure and a part of the second mask structure. A dielectric layer is formed covering the dummy gate, the semiconductor gate, and the second mask structure. A second removing process is performed to remove the dielectric layer above the dummy gate. The dummy gate is removed for forming a trench. A metal gate structure is formed in the trench. The semiconductor gate is covered by the second mask structure during the second removing process and the step of removing the dummy gate.

Подробнее
Номер записи: 14
15-05-2014 дата публикации

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20140134835A1
Автор: Kamo Yoshitaka, KURAHASHI Kenichiro, YAMAMOTO Yoshitsugu
Принадлежит: Mitsubishi Electric Corporation

A method of manufacturing a semiconductor device includes forming a first layer on a semiconductor layer, forming a second layer on the first layer, forming a patterned mask on the second layer, etching and removing a portion of the second layer that is not covered by the patterned mask, wet etching the first layer to a width which is less than the width of the patterned mask, after the wet etching, forming an insulating layer on the semiconductor layer, removing the first layer and the second layer to form an opening in the insulating layer, and forming a gate electrode on a surface of the semiconductor layer exposed through the opening. 1. A method of manufacturing a semiconductor device , comprising:forming a first layer on a semiconductor layer;forming a second layer on said first layer;forming a patterned mask on said second layer, wherein said patterned mask has a width and covers a portion of said second layer;etching and removing the portion of said second layer that is not covered by said patterned mask;wet etching said first layer to a width which is less than the width of said patterned mask;after said wet etching, forming an insulating layer on said semiconductor layer;removing said first layer and said second layer to form an opening in said insulating layer; andforming a gate electrode on a surface of said semiconductor layer exposed through the opening, wherein in said wet etching, etching said first layer is faster than etching said second layer.2. The method according to claim 1 , wherein:said first layer is SiO;said second layer is SIN; anda solution containing hydrofluoric acid is used in said wet etching.3. A method of manufacturing a semiconductor device claim 1 , comprising:forming a Si oxide layer on a semiconductor layer;forming a patterned mask on said Si oxide layer;ashing a portion of said Si oxide layer exposed by said patterned mask to form an oxygen-rich portion in said Si oxide layer so that a bottom portion of said Si oxide layer is ...

Подробнее
Номер записи: 15
03-03-2016 дата публикации

SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME

Номер: US20160064516A1
Автор: CHANG CHIA-DER, HUNG Chung-Wei, LEE MING-CHANG, Lu Chih-Hung, SUN Chung-Tsun
Принадлежит:

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate stack positioned over the semiconductor substrate. The semiconductor device structure includes spacers positioned over sidewalls of the gate stack. The semiconductor device structure includes a first protective layer positioned between the gate stack and the spacers and between the spacers and the semiconductor substrate. The semiconductor device structure includes a second protective layer positioned between the spacers and the first protective layer. The first protective layer and the second protective layer include different materials. 1. A semiconductor device structure , comprising:a semiconductor substrate;a gate stack positioned over the semiconductor substrate;spacers positioned over sidewalls of the gate stack;a first protective layer positioned between the gate stack and the spacers and between the spacers and the semiconductor substrate; anda second protective layer positioned between the spacers and the first protective layer, wherein the first protective layer and the second protective layer comprise different materials.2. The semiconductor device structure as claimed in claim 1 , wherein the first protective layer comprises oxide.3. The semiconductor device structure as claimed in claim 1 , wherein the second protective layer comprises nitride or carbide.4. The semiconductor device structure as claimed in claim 1 , wherein the first protective layer conformally covers the sidewalls of the gate stack and a top surface of the semiconductor substrate.5. The semiconductor device structure as claimed in claim 4 , wherein the second protective layer conformally covers the first protective layer.6. The semiconductor device structure as claimed in claim 1 , wherein a first thickness of the first protective layer ranges from about 5 Å to about 15 Å.7. The semiconductor device structure as claimed in claim 1 , wherein a second thickness ...

Подробнее
Номер записи: 16
08-03-2018 дата публикации

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Номер: US20180068845A1
Автор: HAGIWARA Takuya
Принадлежит:

The reliability of a semiconductor device is improved. In a manufacturing method, a film to be processed is formed over a circular semiconductor substrate, and a resist layer whose surface has a water-repellent property is formed thereover. Subsequently, the water-repellent property of the resist layer in the outer peripheral region of the circular semiconductor substrate is lowered by selectively performing first wafer edge exposure on the outer peripheral region of the semiconductor substrate, and then liquid immersion exposure is performed on the resist layer. Subsequently, second wafer edge exposure is performed on the outer peripheral region of the circular semiconductor substrate, and then the resist layer, on which the first wafer edge exposure, the liquid immersion exposure, and the second wafer edge exposure have been performed, is developed, so that the film to be processed is etched by using the developed resist layer. 1(a) providing a semiconductor substrate whose outer periphery is approximately circular;(b) forming a first insulating film over the semiconductor substrate;(c) forming a resist layer over the first insulating film;(d) irradiating first exposure light to a part of the resist layer which is located in a region having a first width from the outer periphery of the semiconductor substrate;(e) irradiating third exposure light to a part of the resist layer which is located in a region having a second width being larger than the first width from the outer periphery of the semiconductor substrate;(f) after the steps (d) and (e), performing liquid immersion exposure in which the resist layer is irradiated with second exposure light;(g) after the step (f), forming a resist pattern including a first pattern by removing the resist layer located in a region irradiated with the second exposure light and the third exposure light;(h) after the step (g), etching the first insulating film such that the first insulating film has the first pattern;(i) after ...

Подробнее
Номер записи: 17
28-02-2019 дата публикации

MIS CONTACT STRUCTURE WITH METAL OXIDE CONDUCTOR

Номер: US20190067439A1
Автор: Clifton Paul A., Goebel Andreas
Принадлежит:

An electrical contact structure (an MIS contact) includes one or more conductors (M-Layer), a semiconductor (S-Layer), and an interfacial dielectric layer (I-Layer) of less than 4 nm thickness disposed between and in contact with both the M-Layer and the S-Layer. The I-Layer is an oxide of a metal or a semiconductor. The conductor of the M-Layer that is adjacent to and in direct contact with the I-Layer is a metal oxide that is electrically conductive, chemically stable and unreactive at its interface with the I-Layer at temperatures up to 450° C. The electrical contact structure has a specific contact resistivity of less than or equal to approximately 10-10Ω-cmwhen the doping in the semiconductor adjacent the MIS contact is greater than approximately 2×10cmand less than approximately 10Ω-cmwhen the doping in the semiconductor adjacent the MIS contact is greater than approximately 10cm. 1. An electrical contact structure including a conductor; a semiconductor and an interfacial dielectric layer disposed between and in contact with both the conductor and the semiconductor , wherein the conductor is a conductive metal oxide , and the interfacial dielectric layer has a thickness in the range 0.2 nm to 4 nm and comprises one of: WO3 , TiO2 , MgO , Al2O3 , HfO2 , ZrO2 , Ta2O5 , V2O5 , BaZrO3 , La2O3 , Y2O3 , HfSiO4 , ZrSiO4 , CoO , NiO , GaO , SrTiO3 , or (Ba ,Sr)TiO3.2. The electrical contact structure of claim 1 , wherein the conductive metal oxide has a thickness in the range 0.5 nm to 3 nm and comprises one of: WO2 claim 1 , (Nb claim 1 ,Sr)TiO3 claim 1 , (Ba claim 1 ,Sr)TiO3 claim 1 , SrRuO3 claim 1 , MoO2 claim 1 , OsO2 claim 1 , RhO2 claim 1 , RuO2 claim 1 , IrO2 claim 1 , ReO3 claim 1 , ReO2 claim 1 , LaCuO3 claim 1 , Ti2O3 claim 1 , TiO claim 1 , V2O3 claim 1 , VO claim 1 , Fe3O4 claim 1 , ZnO claim 1 , indium tin oxide (ITO) claim 1 , aluminum-doped zinc-oxide (AZO) claim 1 , InSnO claim 1 , or CrO2.3. The electrical contact structure of claim 1 , wherein a ...

Подробнее
Номер записи: 18
05-06-2014 дата публикации

SEMICONDUCTOR DEVICE WITH A SILICON DIOXIDE GATE INSULATION LAYER IMPLANTED WITH A RARE EARTH ELEMENT AND METHODS OF MAKING SUCH A DEVICE

Номер: US20140151818A1
Автор: Flachowsky Stefan, Hoentschel Jan
Принадлежит: GLOBALFOUNDRIES INC.

One illustrative method disclosed herein includes forming a gate insulation layer on a semiconducting substrate, performing an ion implantation process to implant a rare earth element into the gate insulation layer, and forming a silicon-containing gate electrode above the gate insulation layer comprising the implanted rare earth element. One illustrative device disclosed herein includes a gate insulation layer positioned on a semiconducting substrate, wherein the gate insulation layer is comprised of silicon dioxide and a rare earth element, and a silicon-containing gate electrode positioned on the gate insulation layer. 1. A method of forming a transistor , comprising:forming a gate insulation layer on a semiconducting substrate;performing an ion implantation process to implant a rare earth element into said gate insulation layer; andforming a silicon-containing gate electrode above said gate insulation layer comprising said implanted rare earth element.2. The method of claim 1 , wherein said rare earth element is one of hafnium claim 1 , zirconium claim 1 , lanthanum or tantalum.3. The method of claim 1 , wherein said ion implantation process is performed at an energy level less than 1 keV.4. The method of claim 1 , wherein said ion implantation process is performed using a dose of said rare earth element of about 1e-1eatoms/cm.5. The method of claim 1 , wherein forming said gate insulation layer comprises performing a thermal oxidation process to form a gate insulation layer comprised of silicon dioxide on said semiconducting substrate.6. The method of claim 1 , wherein said silicon-containing gate electrode is comprised of polysilicon or amorphous silicon.7. The method of claim 1 , wherein said gate insulation layer comprising said implanted rare earth element has a k value of 5 or greater.8. The method of claim 1 , wherein forming said silicon-containing gate electrode comprises:depositing a layer of silicon-containing material on said gate insulation layer; ...

Подробнее
Номер записи: 19
12-06-2014 дата публикации

Buried word line structure and method of forming the same

Номер: US20140159140A1
Автор: Inho Park, Lars Heineck
Принадлежит: Nanya Technology Corp

A method of forming a buried word line structure is provided. A first mask layer, an interlayer and a second mask layer are sequentially formed on a substrate, wherein the second mask layer has a plurality of mask patterns and a plurality of gaps arranged alternately, and the gaps includes first gaps and second gaps arranged alternately. A dielectric pattern is formed in each first gap and spacers are simultaneously formed on sidewalls of each second gap, wherein a first trench is formed between the adjacent spacers and exposes a portion of the first mask layer. The mask patterns are removed to form second trenches. An etching process is performed by using the dielectric patterns and the spacers as a mask, so that the first trenches are deepened to the substrate and the second trenches are deepened to the first mask layer.

Подробнее
Номер записи: 20
22-03-2018 дата публикации

MIS CONTACT STRUCTURE WITH METAL OXIDE CONDUCTOR

Номер: US20180083115A1
Автор: Clifton Paul A., Goebel Andreas
Принадлежит:

An electrical contact structure (an MIS contact) includes one or more conductors (M-Layer), a semiconductor (S-Layer), and an interfacial dielectric layer (I-Layer) of less than 4 nm thickness disposed between and in contact with both the M-Layer and the S-Layer. The I-Layer is an oxide of a metal or a semiconductor. The conductor of the M-Layer that is adjacent to and in direct contact with the I-Layer is a metal oxide that is electrically conductive, chemically stable and unreactive at its interface with the I-Layer at temperatures up to 450° C. The electrical contact structure has a specific contact resistivity of less than or equal to approximately 10-10Ω-cmwhen the doping in the semiconductor adjacent the MIS contact is greater than approximately 2×10cmand less than approximately 10Ω-cmwhen the doping in the semiconductor adjacent the MIS contact is greater than approximately 10cm. 1. An electrical contact structure , comprising a conductor; a semiconductor layer; and an interfacial dielectric layer disposed between and in contact with both the conductor and the semiconductor layer , wherein the conductor is a conductive metal oxide and the interfacial dielectric layer comprises a plurality of oxide layers , wherein at least one of the oxide layers of the interfacial dielectric layer is an oxide of a metal or an oxide of a semiconductor.2. The electrical contact structure of claim 1 , wherein the electrical contact structure has a specific contact resistivity of less than or equal to approximately 10-10Ω-cm3. The electrical contact structure of claim 2 , wherein at least one of the oxide layers of the interfacial dielectric layer comprises a material that would be an insulator or a semiconductor in its bulk state.4. The electrical contact structure of claim 2 , wherein at least one of the oxide layers of the interfacial dielectric layer has a thickness in the range 0.2 nm to 4 nm and the conductive metal oxide layer has a thickness in the range 0.5 nm to 3 nm.5 ...

Подробнее
Номер записи: 21
23-03-2017 дата публикации

ETCHING METHOD AND METHOD OF FABRICATING A SEMICONDUCTOR DEVICE USING THE SAME

Номер: US20170084719A1
Автор: Bae Sang Won, Baek Jae-Jik, Choi Wonsang, KIM Hoyoung
Принадлежит:

The present disclosure relates to an etchant, a method of making an etchant, an etching method and a method of fabricating a semiconductor device using the same. The etching method includes supplying an etchant on an etch-target layer to etch the etch-target layer in a wet etch manner. The etchant contains a basic compound and a sugar alcohol, and the basic compound contains ammonium hydroxide or tetraalkyl ammonium hydroxide. In the etchant, the sugar alcohol has 0.1 to 10 parts by weight for every 100 parts by weight of the basic compound. 1. A method of manufacturing a semiconductor device , comprising:supplying an etchant on an etch-target layer on a semiconductor substrate to etch the etch-target layer with a wet etch process,wherein the etchant comprises a basic compound and a sugar alcohol,wherein the basic compound comprises ammonium hydroxide or tetraalkyl ammonium hydroxide, andwherein, in the etchant, the sugar alcohol has 0.1 to 10 parts by weight for every 100 parts by weight of the basic compound.2. The method of claim 1 , wherein the etch-target layer is polysilicon.3. The method of claim 1 , wherein the sugar alcohol is at least one selected from the group consisting of sorbitol claim 1 , glycerol claim 1 , erythritol claim 1 , threitol claim 1 , arabitol claim 1 , xylitol claim 1 , ribitol claim 1 , mannitol claim 1 , galactitol claim 1 , fucitol claim 1 , iditol claim 1 , inositol claim 1 , volemitol claim 1 , maltitol claim 1 , lactitol claim 1 , maltotritol claim 1 , maltotetraitol claim 1 , and polyglycitol.5. The method of claim 1 , wherein the etchant is prepared by:mixing the basic compound with the sugar alcohol to prepare an etchant mixture; andmixing the etchant mixture with water of 60-100° C.7. The method of claim 6 , wherein the sacrificial gate pattern comprises polysilicon.8. The method of claim 6 , wherein claim 6 , in the etchant claim 6 , for every 100 parts by weight of the basic compound claim 6 , the sugar alcohol has 0.1 to 10 ...

Подробнее
Номер записи: 22
02-04-2015 дата публикации

Semiconductor Device and Method of Manufacturing

Номер: US20150091023A1
Автор: BOETTCHER Tim, Fischer Jan
Принадлежит:

A diode comprising a reduced surface field effect trench structure, the reduced surface field effect trench structure comprising at least two trenches formed in a substrate and separated from one another by a joining region of the substrate, the joining region comprising an electrical contact and a layer of p-doped semiconductor material. 1. A diode comprising a reduced surface field effect trench structure , the reduced surface field effect trench structure comprising at least two trenches formed in a substrate and separated from one another by a joining region of the substrate , the joining region comprising an electrical contact and a layer of p-doped semiconductor material.2. The diode of claim 1 , wherein the joining region further comprises a layer of n-doped semiconductor material.3. The diode of claim 2 , wherein the layer of p-doped semiconductor material and the layer of n-doped semiconductor material have a combined thickness of no more than 40 nm.4. The diode of claim 1 , wherein the layer of p-doped semiconductor material comprises one or more of p-doped silicon germanium claim 1 , p-doped silicon claim 1 , p-doped silicon germanium carbide claim 1 , and p-doped silicon carbide.5. The diode of claim 2 , wherein the layer of p-doped semiconductor material comprises p-doped silicon germanium and the layer of n-doped semiconductor material comprises n-doped silicon germanium.6. The diode of claim 1 , wherein the electrical contact comprises one or more of a metal claim 1 , an alloy claim 1 , and a silicide.7. The diode of claim 1 , wherein the substrate comprises monocrystalline silicon and each trench comprises polycrystalline silicon separated from the monocrystalline silicon by a layer of silicon oxide.8. The diode of claim 7 , wherein the monocrystalline silicon and polycrystalline silicon each have an upper surface claim 7 , and wherein the upper surface of the polycrystalline silicon is positioned below the upper surface of the monocrystalline ...

Подробнее
Номер записи: 23
19-06-2014 дата публикации

SIDEWALL-FREE CESL FOR ENLARGING ILD GAP-FILL WINDOW

Номер: US20140170846A1
Автор: Chung Han-Pin, Hsieh Bor Chiuan, Tao Hun-Jan, WANG Shiang-Bau
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

An integrated circuit structure includes a first gate strip; a gate spacer on a sidewall of the first gate strip; and a contact etch stop layer (CESL) having a bottom portion lower than a top surface of the gate spacer, wherein a portion of a sidewall of the gate spacer has no CESL formed thereon. 1. A method comprising:providing a first gate strip over a substrate and having a gate spacer on a sidewall of the first gate strip;forming a contact etch stop layer (CESL) over the gate strip and on a first sidewall of the gate spacer, a second sidewall of the gate spacer is opposite the first sidewall of the gate spacer and nearest the first gate strip, wherein a top portion of the CESL extends over the gate strip and a bottom portion of the CESL extends over the substrate, and wherein a sidewall portion of the CESL is disposed on the first sidewall of the gate spacer;etching the CESL and removing at least a sidewall portion of the CESL on a first sidewall of the gate spacer; andforming an inter-layer dielectric (ILD) over and contacting the CESL;wherein the CESL comprises a material having a high etch selectivity with respect to the ILD;wherein, after the etching, the bottom portion of the CESL is lower than a top surface of the gate spacer; andwherein, after the etching, a top surface of the bottom portion of the CESL is higher than a bottom surface of the gate spacer.2. The method of claim 1 , wherein the forming the CESL comprises using a deposition process with a low frequency energy to form the CESL claim 1 , wherein the low frequency energy has a frequency lower than about 900 kHz.3. The method of claim 1 , wherein the forming the CESL comprises using a deposition process with a high frequency energy and a low frequency energy to form the CESL claim 1 , wherein the high frequency energy has a frequency higher than about 900 kHz and the low frequency source has a frequency of about 350 kHz or lower.4. The method of claim 3 , wherein the ratio of a power of the high ...

Подробнее
Номер записи: 24
03-07-2014 дата публикации

METHOD FOR FABRICATING ARRAY SUBSTRATE

Номер: US20140187001A1
Автор: GUO Jian
Принадлежит: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.

Disclosed is a method for fabricating an array substrate, comprising: forming a pattern layer comprising a gate and a gate connection on a substrate; sequentially forming an insulation layer film and an active layer film on the substrate, and forming a pattern of a gate insulation layer having a first via hole and a pattern of an active layer through a single patterning process, wherein the first via hole is located above the gate connection; sequentially forming a transparent conductive film and a metal film on the substrate, and forming a pattern layer comprising a first electrode and a pattern layer comprising a data line, a source, a drain and a TFT channel through a single patterning process. 1. A method for fabricating an array substrate , comprising:forming a pattern layer comprising a gate and a gate connection on a substrate;sequentially forming an insulation layer film and an active layer film on the substrate, and forming a pattern of a gate insulation layer having a first via hole and a pattern of an active layer through a single patterning process, wherein the first via hole is located above the gate connection;sequentially forming a transparent conductive film and a metal film on the substrate, and forming a pattern layer comprising a first electrode and a pattern layer comprising a data line, a source, a drain and a TFT channel through a single patterning process.2. The method of claim 1 , further comprising:forming a pattern comprising a passivation layer on the substrate having the pattern layer comprising the first electrode and the pattern layer comprising the data line, the source, the drain and the TFT channel formed thereon;forming a pattern layer comprising a second electrode on the substrate having the pattern comprising the passivation layer formed thereon.3. The method of claim 1 , wherein forming the pattern of the gate insulation layer having the first via hole and the pattern of the active layer through a single patterning process ...

Подробнее
Номер записи: 25
21-04-2016 дата публикации

Forming Conductive STI Liners for FinFETs

Номер: US20160111526A1
Автор: Jean-Pierre Colinge
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An integrated circuit device, and a method of forming, including a semiconductor substrate, isolation regions extending into the semiconductor substrate, a semiconductor strip, and a semiconductor fin overlapping and joined to the semiconductor strip is provided. A first dielectric layer and a second dielectric layer are disposed on opposite sidewalls of the semiconductor strip. The integrated circuit device further includes a first conductive liner and a second conductive liner, wherein the semiconductor strip, the first dielectric layer, and the second dielectric layer are between the first conductive liner and the second conductive line. The first conductive liner and the second conductive liner are between, and in contact with, sidewalls of a first portion and a second portion of the isolation regions.

Подробнее
Номер записи: 26
30-04-2015 дата публикации

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME

Номер: US20150115375A1
Автор: YOO Jae-Hyun
Принадлежит:

A semiconductor device includes a gate insulation layer pattern, a lower gate electrode, an upper gate electrode, and a first inner spacer. The gate insulation layer pattern is formed on a substrate. The lower gate electrode is formed on the gate insulation layer pattern. The upper gate electrode is formed on the lower gate electrode and has a width that gradually increases from a bottom portion toward a top portion thereof. The width of the bottom portion of the upper gate electrode is smaller than a width of a top surface of the lower gate electrode. The first inner spacer surrounds a sidewall of the upper gate electrode. 1. A semiconductor device , comprising:a gate insulation layer pattern on a substrate;a lower gate electrode on the gate insulation layer pattern;an upper gate electrode on the lower gate electrode, the upper gate electrode having a width that gradually increases from a bottom portion toward a top portion thereof, the width of the bottom portion of the upper gate electrode being smaller than a width of a top surface of the lower gate electrode; anda spacer on a sidewall of the upper gate electrode.2. The semiconductor device of claim 1 , further comprising a high-k dielectric layer pattern on the gate insulation layer pattern claim 1 , the high-k dielectric layer pattern surrounding a bottom and a sidewall of the lower gate electrode.3. The semiconductor device of claim 2 ,wherein the spacer comprises a first inner spacer,wherein the semiconductor device further comprises a second inner spacer on the gate insulation layer pattern, andwherein the second inner spacer is on an outer sidewall of the high-k dielectric layer pattern.4. The semiconductor device of claim 2 , wherein the width of the top portion of the upper gate electrode is substantially equally wide as a width of a bottom portion of the high-k dielectric layer pattern.5. The semiconductor device of claim 1 , wherein the width of the top surface of the lower gate electrode is ...

Подробнее
Номер записи: 27
03-05-2018 дата публикации

PREVENTING THRESHOLD VOLTAGE VARIABILITY IN STACKED NANOSHEETS

Номер: US20180122899A1
Автор: Guillorn Michael A., Loubet Nicolas J.
Принадлежит:

Embodiments are directed to a method of forming a stacked nanosheet and resulting structures having equal thickness work function metal layers. A nanosheet stack is formed on a substrate. The nanosheet stack includes a first sacrificial layer formed on a first nanosheet. A hard mask is formed on the first sacrificial layer and the first sacrificial layer is removed to form a cavity between the hard mask and the first nanosheet. A work function layer is formed to fill the cavity between the hard mask and the first nanosheet. 1. A method for forming a semiconductor device , the method comprising:forming a nanosheet stack on a substrate, the nanosheet stack comprising a first sacrificial layer on a first nanosheet;forming a hard mask directly on a surface of the first sacrificial layer;forming a first doping region against a first end of the nanosheet stack, and forming a second doping region against a second end of the nanosheet stack opposite the first end;completely removing the first sacrificial layer to form a cavity between the hard mask and the first nanosheet; andforming a work function layer to fill the cavity between the hard mask and the first nanosheet.2. The method of further comprising:forming a gate over a channel region of the nanosheet stack; andforming a gate contact on the gate.3. The method of further comprising replacing the hard mask with a conductive layer.4. The method of claim 3 , wherein the conductive layer comprises tungsten or cobalt.5. The method of claim 1 , wherein the nanosheet stack further comprises a plurality of nanosheets alternating with a plurality of sacrificial layers such that each pair of adjacent nanosheets is separated by a sacrificial layer.6. The method of claim 5 , wherein each nanosheet of the nanosheet stack has a thickness of about 4 nm to about 10 nm.7. The method of claim 5 , wherein a thickness of each sacrificial layer of the nanosheet stack is substantially equal.8. The method of claim 7 , wherein the thickness ...

Подробнее
Номер записи: 28
12-05-2016 дата публикации

Method of manufacturing thin-film transistor, thin-film transistor, and display apparatus including the same

Номер: US20160133725A1
Автор: Hyunduck CHO, Youngjun Chung
Принадлежит: Samsung Display Co Ltd

A method of manufacturing a thin-film transistor (TFT) having uniform performance in terms of threshold voltage and the like, the TFT, and a display apparatus including the same are disclosed. The method includes: (i) forming a polysilicon layer having a source region, a drain region, and a channel region between the source region and the drain region; (ii) doping a central region in the channel region with a first impurity except for peripheral portions; and (iii) doping the source region and the drain region with a second impurity of a conductivity type that is different from that of the first impurity.

Подробнее
Номер записи: 29
07-08-2014 дата публикации

FINFET STRUCTURE AND METHOD TO ADJUST THRESHOLD VOLTAGE IN A FINFET STRUCTURE

Номер: US20140217504A1
Автор: Cartier Eduard A., Greene Brian J., Guo Dechao, Wang Gan, Wang Yanfeng, Wong Keith Kwong Hon
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

FinFET structures and methods of manufacturing the FinFET structures are disclosed. The method includes performing an oxygen anneal process on a gate stack of a FinFET structure to induce Vt shift. The oxygen anneal process is performed after sidewall pull down and post silicide. 1. A method comprising:forming a plurality of fin structures on an insulator layer;forming a gate stack wrapping around the plurality of fin structures, the gate stack comprising a high-k dielectric material deposited on the plurality of fin structures; andadjusting a Vt threshold of the gate stack by subjecting the high-k dielectric material to an oxygen anneal process.2. The method of claim 1 , wherein the oxygen anneal process is a lateral oxygen diffusion process performed at about 400° C. to about 500° C.3. The method of claim 1 , wherein the Vt threshold is shifted in a range from 0 to 400 mV.4. The method of claim 1 , wherein the gate stack includes the formation of a sidewall spacer on sidewalls of the gate stack claim 1 , the sidewall spacer is formed over the high-k dielectric material.5. The method of claim 4 , further comprising pulling down the sidewall spacer on the gate stack to expose at least the high-k dielectric material such that the high-k dielectric material is subjected to the oxygen anneal process.6. The method of claim 5 , wherein the pulling down is performed by an etching process prior to the oxygen anneal process.7. The method of claim 6 , further comprising fabricating an upper portion of the sidewall spacer on the gate stack after the oxygen anneal process claim 6 , by depositing spacer material on sidewalls of the gate stack.8. The method of claim 1 , wherein the oxygen anneal process fills in oxygen vacancies in the high-k dielectric material claim 1 , resulting in threshold voltage shift of the gate stack.9. The method of claim 1 , wherein the oxygen anneal process is self-limiting and avoids introduction of extra variability.10. The method of claim 1 , ...

Подробнее
Номер записи: 30
01-09-2022 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME

Номер: US20220278507A1
Автор: YAMAGUCHI Tsutomu
Принадлежит: Mitsubishi Electric Corporation

An insulating film () having an opening () is formed on a contact layer (). A shape stabilization layer () having an inclined surface () is formed on the contact layer () in a peripheral portion of the opening (). An underlying metal () covers an upper surface of the contact layer () exposed through the opening () and the inclined surface (). A plating () is formed on the underlying metal (). 12.-. (canceled)3. A semiconductor device comprising:a contact layer,an insulating film formed on the contact layer and having an opening;a shape stabilization layer having an inclined surface formed on the contact layer in a peripheral portion of the opening;an underlying metal covering an upper surface of the contact layer exposed through the opening and the inclined surface; anda plating formed on the underlying metal,wherein a material of the shape stabilization layer is different from a material of the contact layer, andthe material of the shape stabilization layer is a semiconductor.4. (canceled)5. The semiconductor device according to claim 3 , wherein the contact layer is an InGaAs layer.6. The semiconductor device according to claim 3 , wherein the inclined surface has a curved surface.78.-. (canceled)9. A method for producing a semiconductor device comprising:forming a shape stabilization layer on a contact layer;etching the shape stabilization layer to form an inclined surface and to expose a part of an upper surface of the contact layer;forming an insulating film on the shape stabilization layer;forming an opening in the insulating film;forming an underlying metal covering an upper surface of the contact layer exposed through the opening and the inclined surface; andforming a plating on the underlying metal by electrolytic plating,wherein the inclined surface is formed in a peripheral portion of the opening,a material of the shape stabilization layer is different from a material of the contact layer,the shape stabilization layer is selectively etched with respect to ...

Подробнее
Номер записи: 31
19-05-2016 дата публикации

FinFETs with Different Fin Height and EPI Height Setting

Номер: US20160141205A1
Автор: CHIANG Hung-Li, Lai Wei-Jen, LEE Tsung-Lin, YEH Chih Chieh, YUAN Feng
Принадлежит:

An integrated circuit structure includes a first semiconductor strip, first isolation regions on opposite sides of the first semiconductor strip, and a first epitaxy strip overlapping the first semiconductor strip. A top portion of the first epitaxy strip is over a first top surface of the first isolation regions. The structure further includes a second semiconductor strip, wherein the first and the second semiconductor strips are formed of the same semiconductor material. Second isolation regions are on opposite sides of the second semiconductor strip. A second epitaxy strip overlaps the second semiconductor strip. A top portion of the second epitaxy strip is over a second top surface of the second isolation regions. The first epitaxy strip and the second epitaxy strip are formed of different semiconductor materials. A bottom surface of the first epitaxy strip is lower than a bottom surface of the second epitaxy strip. 1. A method comprising:forming a first recess between two portions of a first plurality of shallow trench isolation (STI) regions;performing a first epitaxy to grow a first epitaxy strip in the first recess, wherein the first epitaxy strip is over and contacting a first semiconductor strip portion of a semiconductor substrate;forming a second recess between additional two portions of a second plurality of STI regions;performing a second epitaxy to grow a second epitaxy strip in the second recess, wherein the first epitaxy strip is over and contacting a second semiconductor strip portion of the semiconductor substrate; andrecessing the first plurality of STI regions and the second plurality of STI regions to form a second semiconductor fin and a second semiconductor fin, respectively, wherein the first plurality of STI regions is recessed to a first depth smaller than a height of the first epitaxy strip, and the second plurality of STI regions is recessed to a second depth greater than a height of the second epitaxy strip.2. The method of claim 1 , ...

Подробнее
Номер записи: 32
07-08-2014 дата публикации

METHOD OF LASER IRRADIATION, LASER IRRADIATION APPARATUS, AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

Номер: US20140220768A1
Автор: MORIWAKA Tomoaki, Tanaka Koichiro
Принадлежит: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

If an optical path length of an optical system is reduced and a length of a laser light on an irradiation surface is increased, there occurs curvature of field which is a phenomenon that a convergent position deviates depending on an incident angle or incident position of a laser light with respect to a lens. To avoid this phenomenon, an optical element having a negative power such as a concave lens or a concave cylindrical lens is inserted to regulate the optical path length of the laser light and a convergent position is made coincident with a irradiation surface to form an image on the irradiation surface. 1. (canceled)2. A method of manufacturing a semiconductor device comprising:homogenizing an energy distribution of a laser beam along a first direction perpendicular to a propagation direction of the laser beam by utilizing at least a first cylindrical lens array and a second cylindrical lens array;homogenizing an energy distribution of the laser beam along a second direction perpendicular to the propagation direction of the laser beam by utilizing at least a third cylindrical lens array and a fourth cylindrical lens array, wherein the second direction is perpendicular to the first direction;condensing the laser beam along a third direction perpendicular the first direction by utilizing at least a doublet cylindrical lens;irradiating a semiconductor film with the condensed laser beam to increase crystallinity of the semiconductor film while changing a relative location of the semiconductor film with respect to the condensed laser beam; andpatterning the semiconductor film into a plurality of semiconductor layers,wherein each of the first cylindrical lens array and the second cylindrical lens array has a longitudinal direction along the second direction, andwherein each of the third cylindrical lens array and the fourth cylindrical lens array has a longitudinal direction along the first direction.3. The method according to claim 2 , further comprising steps of: ...

Подробнее
Номер записи: 33
28-05-2015 дата публикации

Antifuse of semiconductor device and method of fabricating the same

Номер: US20150147859A1
Автор: Yeong Eui Hong
Принадлежит: SK hynix Inc

An antifuse of a semiconductor device and a method of fabricating the same capable of causing an antifuse to stably operate by rupturing the antifuse at a specific point and stabilizing a current level when rupturing the antifuse are provided. The antifuse may include: a device isolation layer defining a first active region in a semiconductor substrate; a first and second junction regions provided in the first active region; a second active region formed over the first junction region; a gate insulating layer formed over the first active region and the second active region; and a gate electrode formed over the gate insulating layer.

Подробнее
Номер записи: 34
14-08-2014 дата публикации

METHODS OF FORMING A SEMICONDUCTOR DEVICE BY PERFORMING A WET ACID ETCHING PROCESS WHILE PREVENTING OR REDUCING LOSS OF ACTIVE AREA AND/OR ISOLATION REGIONS

Номер: US20140227869A1
Автор: Haussdoerfer Bastian, Lenski Markus, Pakfar Ardechir, Reimer Berthold
Принадлежит: GLOBALFOUNDRIES INC.

One method disclosed includes forming a sidewall spacer proximate a gate structure, forming a sacrificial layer of material above a protective cap layer, the sidewall spacer and a substrate, forming a sacrificial protection layer above the sacrificial layer, reducing a thickness of the sacrificial protection layer such that its upper surface is positioned at a level that is below the upper surface of the protective cap layer, performing a first etching process to remove a portion of the sacrificial layer and thereby expose the protective cap layer for further processing, performing a wet acid etching process that includes diluted HF acid in the etch chemistry to remove the protective cap layer and performing at least one process operation to remove at least one of the reduced-thickness sacrificial protection layer or the sacrificial layer from above the surface of the substrate. 1. A method , comprising:forming a gate structure of a transistor above a surface of a semiconductor substrate, said gate structure being comprised of at least one layer of metal, a silicon-containing layer of material positioned above said at least one layer of metal and a protective cap layer positioned above said silicon-containing layer of material;forming a sidewall spacer proximate said gate structure;after forming said sidewall spacer, forming a sacrificial layer of material above said protective cap layer, above said sidewall spacer and above said substrate;forming a sacrificial protection layer above said sacrificial layer;reducing a thickness of said sacrificial protection layer such that, after said reduction, an upper surface of said reduced-thickness sacrificial protection layer is positioned at a level that is below a level of an upper surface of said protective cap layer;with said reduced-thickness sacrificial protection layer in position, performing a first etching process to remove said sacrificial layer from above said protective cap layer to thereby expose said protective ...

Подробнее
Номер записи: 35
16-05-2019 дата публикации

Semiconductor device and manufacturing method thereof

Номер: US20190148490A1
Автор: Ka-Hing Fung, Kuo-Cheng Ching, Ying-Keung Leung
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device includes first channel layers disposed over a substrate, a first source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the first channel layers, a gate electrode layer disposed on the gate dielectric layer and wrapping each of the first channel layers, and a liner semiconductor layer disposed between the first channel layers and the first source/drain region.

Подробнее
Номер записи: 36
01-06-2017 дата публикации

Semiconductor device and manufacturing method thereof

Номер: US20170154958A1
Автор: Ka-Hing Fung, Kuo-Cheng Ching, Ying-Keung Leung
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device includes first channel layers disposed over a substrate, a first source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the first channel layers, a gate electrode layer disposed on the gate dielectric layer and wrapping each of the first channel layers, and a liner semiconductor layer disposed between the first channel layers and the first source/drain region.

Подробнее
Номер записи: 37
14-05-2020 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

Номер: US20200152529A1
Автор: Akino Masaru, Sakurai Hitomi
Принадлежит: ABLIC Inc.

In a manufacturing step in which a structure of target of screening is formed on a semiconductor substrate in the middle of manufacturing process before a semiconductor device is finished, screening of potential defects of a gate insulating film is performed for each wafer at one time so that the semiconductor device is caused to appear as an initial defective product when the finished semiconductor device is subjected to an electrical characteristic test. Provided are a semiconductor device, and a method of manufacturing a semiconductor device which enables reliable screening of potential defects in a short period of time. 1. A method of manufacturing a semiconductor device , the semiconductor device having a gate insulating film and a gate electrode film on a semiconductor substrate of a wafer , the method comprising:forming a first gate insulating film on the semiconductor substrate of the wafer;forming a first gate electrode film on an entire surface of the semiconductor substrate of the wafer, the semiconductor substrate of the wafer including the first gate insulating film;screening, after the forming a first gate electrode film, the first gate insulating film by generating a potential difference between the first gate electrode film which is formed on the entire surface of the semiconductor substrate of the wafer, and a back surface of the semiconductor substrate of the wafer to apply an electric field to the first gate insulating film;determining the semiconductor substrate of the wafer which has been subjected to the screening;patterning the first gate electrode film after the determining the semiconductor substrate;removing, after the patterning the first gate electrode film, the first gate insulating film which is formed on the entire surface of the semiconductor substrate of the wafer from at least a region in which a second gate insulating film is to be formed;forming, after removing the first gate insulating film, the second gate insulating film on the ...

Подробнее
Номер записи: 38
14-05-2020 дата публикации

MIS CONTACT STRUCTURE WITH METAL OXIDE CONDUCTOR

Номер: US20200152758A1
Автор: Clifton Paul A., Goebel Andreas
Принадлежит:

An electrical contact structure (an MIS contact) includes one or more conductors (M-Layer), a semiconductor (S-Layer), and an interfacial dielectric layer (I-Layer) of less than 4 nm thickness disposed between and in contact with both the M-Layer and the S-Layer. The I-Layer is an oxide of a metal or a semiconductor. The conductor of the M-Layer that is adjacent to and in direct contact with the I-Layer is a metal oxide that is electrically conductive, chemically stable and unreactive at its interface with the I-Layer at temperatures up to 450° C. The electrical contact structure has a specific contact resistivity of less than or equal to approximately 10-10Ω-cmwhen the doping in the semiconductor adjacent the MIS contact is greater than approximately 2×10cmand less than approximately 10Ω-cmwhen the doping in the semiconductor adjacent the MIS contact is greater than approximately 10cm. 1. An electrical junction structure , comprising a conductor; a semiconductor layer; and an interfacial dielectric layer disposed between and in contact with both the conductor and the semiconductor layer , wherein the conductor is a conductive metal oxide and the interfacial dielectric layer comprises a metal oxide and modifies a Schottky barrier height of the electrical junction structure relative to a barrier height of the electrical junction structure that would occur in the absence of the interfacial dielectric layer.2. The electrical junction structure of claim 1 , wherein an interface between the conductor and the interfacial dielectric layer is a thermally stable interface up to a temperature of 450° C.3. The electrical junction structure of claim 2 , wherein the interfacial dielectric layer has a thickness in the range 0.2 nm to 4 nm and comprises one of: WO claim 2 , TiO claim 2 , MgO claim 2 , AlO claim 2 , HfO claim 2 , ZrO claim 2 , TaO claim 2 , VO claim 2 , BaZrO claim 2 , LaO claim 2 , YO claim 2 , HfSiO claim 2 , ZrSiO claim 2 , CoO claim 2 , NiO claim 2 , GaO claim ...

Подробнее
Номер записи: 39
16-06-2016 дата публикации

CMOS GATE CONTACT RESISTANCE REDUCTION

Номер: US20160172378A1
Автор: Chou Anthony I., Kumar Arvind, Lee Sungjae
Принадлежит: GLOBALFOUNDRIES INC.

A gate contact with reduced contact resistance is provided by increasing contact area between the gate contact and a gate conductive portion of a gate structure. The gate contact forms a direct contact with a topmost surface and at least portions of outermost sidewalls of a portion of the gate conductive portion, thus increasing the contact area between the gate contact and the gate structure. The gate contact area of the present application can be further increased by completely surrounding a portion of the gate conductive portion of the gate structure with the gate contact. 1. A semiconductor structure comprising:a substrate comprising a first device region and a second device region separated from one another by an insulating region;at least one gate structure overlying at least one channel portion of each of the first device region and the second device region, wherein the at least one gate structure comprises a gate spacer, a U-shaped gate dielectric laterally surrounded by the gate spacer, and a gate conductive portion in contact with the U-shaped gate dielectric; anda gate contact contacting a portion of the at least one gate structure located in the insulating region, wherein the gate contact is in direct contact with a topmost surface and at least portions of outermost sidewalls of the gate conductive portion.2. The semiconductor structure of claim 1 , wherein the gate contact is in contact with the topmost surface and entire outermost sidewalls of the gate conductive portion.3. The semiconductor structure of claim 1 , wherein the gate contact completely surrounds the gate conductive portion such that the gate contact is in direct contact with the topmost surface claim 1 , the outermost sidewalls and a bottommost surface of the gate conductive portion.4. The semiconductor structure of claim 1 , wherein the gate conductive portion comprises a U-shaped first work function metal contacting a portion of the U-shaped gate dielectric claim 1 , a U-shaped second ...

Подробнее
Номер записи: 40
14-06-2018 дата публикации

SEMICONDUCTOR DEVICE WITH CAPPING STRUCTURE AND METHOD OF FORMING THE SAME

Номер: US20180166545A1
Автор: KUO Fang-Ting, Wang Chung-Ming
Принадлежит:

A semiconductor device is provided, which includes a substrate, a shallow trench isolation (STI), a gate dielectric structure, a capping structure and a gate structure. The STI is in the substrate and defines an active area of the substrate. The gate dielectric structure is on the active area. The capping structure is adjacent to the gate dielectric structure and at edges of the active area. The gate structure is on the gate dielectric structure and the capping structure. An equivalent oxide thickness of the capping structure is substantially greater than an equivalent oxide thickness of the gate dielectric structure. 1. A semiconductor device , comprising:a substrate having a top surface;a shallow trench isolation (STI) in the substrate, the STI defining an active area of the substrate and extending downward from the top surface of the substrate;a gate dielectric structure on the top surface of the substrate within the active area;a capping structure on the top surface of the substrate adjacent to the gate dielectric structure and at edges of the active area; anda gate structure crossing the gate dielectric structure and the capping structure;wherein an equivalent oxide thickness of the capping structure is greater than an equivalent oxide thickness of the gate dielectric structure.2. The semiconductor device of claim 1 , wherein the capping structure comprises at least one capping layer.3. The semiconductor device of claim 1 , wherein the gate dielectric structure comprises at least one gate dielectric layer.4. The semiconductor device of claim 1 , wherein the capping structure comprises a plurality of portions claim 1 , and a portioned equivalent oxide thickness of each of the portions of the capping structure is greater than the equivalent oxide thickness of the gate dielectric structure.5. The semiconductor device of claim 1 , wherein the active area is substantially overlapped by the capping structure.6. The semiconductor device of claim 1 , wherein a ...

Подробнее
Номер записи: 41
22-06-2017 дата публикации

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Номер: US20170178897A1
Автор: HAGIWARA Takuya
Принадлежит:

The reliability of a semiconductor device is improved. In a manufacturing method, a film to be processed is formed over a circular semiconductor substrate, and a resist layer whose surface has a water-repellent property is formed thereover. Subsequently, the water-repellent property of the resist layer in the outer peripheral region of the circular semiconductor substrate is lowered by selectively performing first wafer edge exposure on the outer peripheral region of the semiconductor substrate, and then liquid immersion exposure is performed on the resist layer. Subsequently, second wafer edge exposure is performed on the outer peripheral region of the circular semiconductor substrate, and then the resist layer, on which the first wafer edge exposure, the liquid immersion exposure, and the second wafer edge exposure have been performed, is developed, so that the film to be processed is etched by using the developed resist layer. 1. A manufacturing method of a semiconductor device , comprising steps of:(a) providing a semiconductor substrate whose outer periphery is approximately circular;(b) forming a first insulating film over the semiconductor substrate;(c) forming a resist layer over the first insulating film;(d) irradiating first exposure light to a part of the resist layer which is located in a region having a first width from the outer periphery of the semiconductor substrate;(e) irradiating third exposure light to a part of the resist layer which is located in a region having a second width being larger than the first width from the outer periphery of the semiconductor substrate;(f) after the steps (d) and (e), performing liquid immersion exposure in which the resist layer is irradiated with second exposure light;(g) after the step (f), forming a resist pattern including a first pattern by removing the resist layer located in a region irradiated with the second exposure light and the third exposure light;(h) after the step (g) , etching the first insulating ...

Подробнее
Номер записи: 42
30-06-2016 дата публикации

VERTICAL GATE ALL-AROUND TRANSISTOR

Номер: US20160190312A1
Автор: Clevenger Lawrence A., Radens Carl, XU Yiheng, Zhang John H.
Принадлежит:

Vertical GAA FET structures are disclosed in which a current-carrying nanowire is oriented substantially perpendicular to the surface of a silicon substrate. The vertical GAA FET is intended to meet design and performance criteria for the 7 nm technology generation. In some embodiments, electrical contacts to the drain and gate terminals of the vertically oriented GAA FET can be made via the backside of the substrate. Examples are disclosed in which various n-type and p-type transistor designs have different contact configurations. In one example, a backside gate contact extends through the isolation region between adjacent devices. Other embodiments feature dual gate contacts for circuit design flexibility. The different contact configurations can be used to adjust metal pattern density. 1. A vertical field effect transistor , comprising:a silicon substrate having a front surface and a back surface;an epitaxial source region;an epitaxial drain region;a channel located between the source region and the drain region, the channel having a channel axis that is oriented transverse to the front surface of the substrate;a gate that wraps around the channel, the gate configured to control current flow in the channel;a low-k encapsulant, overlying and in contact with the gate; andone or more electrical contacts accessible from the back surface of the substrate.2. An n-type transistor according to wherein the epitaxial source region is made of indium-doped silicon.3. A p-type transistor according to wherein the epitaxial source region is made of silicon germanium.4. The transistor of wherein the channel includes a multi-layer work function material including one or more of titanium claim 1 , tungsten claim 1 , titanium nitride claim 1 , and titanium carbide claim 1 , the channel having a channel length in the range of about 1-100 nm.5. The transistor of wherein the channel includes a III-V semiconductor material.6. The transistor of wherein the low-k encapsulant includes one ...

Подробнее
Номер записи: 43
29-06-2017 дата публикации

TRANSISTOR USING SELECTIVE UNDERCUT AT GATE CONDUCTOR AND GATE INSULATOR CORNER

Номер: US20170186845A1
Автор: Abou-Khalil Michel J., Botula Alan Bernard, Gross Blaine Jeffrey, Jaffe Mark David, Joseph Alvin, Phelps Richard A., SHANK Steven M., Slinkman James Albert
Принадлежит: GLOBALFOUNDRIES INC.

Methods form transistor structures that include, among other components, a substrate having an active region bordered by an isolation region, a gate insulator on the substrate, and a gate conductor on the gate insulator. First and second sections of the gate conductor are within the active region of the substrate, while a third section is in the isolation region of the substrate. The second section of the gate conductor tapers from the width of the first section to the width of the wider third section. The first section and the second section of the gate conductor have undercut regions where the corner of the gate conductor contacts the substrate. The third section of the gate conductor lacks the undercut regions. The gate insulator is relatively thicker in the undercut regions and is relatively thinner where the corner of the gate conductor lacks the undercut regions in the isolation region. 1. A structure comprising:a substrate having an active region bordered by an isolation region;a gate insulator on the substrate; anda gate conductor on and contacting the gate insulator, the gate conductor extends from the active region to the isolation region, the gate conductor has a first section, a second section, and a third section, the second section of the gate conductor is between the first section and the third section of the gate conductor, the first section of the gate conductor is within the active region and has a first width, the third section of the gate conductor is within the isolation region and has a second width that is greater than the first width, the second section of the gate conductor is within the active region and has a tapered width that tapers from the first width to the second width, the first section and the second section of the gate conductor have undercut regions where a corner of the gate conductor contacts the substrate, the third section of the gate conductor lacks the undercut regions, and the gate insulator is relatively thicker in the ...

Подробнее
Номер записи: 44
23-07-2015 дата публикации

Tunnel field-effect transistor

Номер: US20150206958A1
Автор: Amey Mahadev Walke, Anne Vandooren, Krishna Kumar Bhuwalka
Принадлежит: Interuniversitair Microelektronica Centrum vzw IMEC, Taiwan Semiconductor Manufacturing Co TSMC Ltd

A tunnel field-effect transistor (TFET) device is provided comprising a semiconductor substrate and a fin structure disposed thereon. The fin structure comprises a channel region and a source region disposed on the channel region. The TFET further comprises a drain region contacting the channel region, wherein the source region and the drain region are of opposite conductivity type. The TFET also comprises a pocket layer covering a gate interface portion of the source region and contacting at least part of the channel region. The TFET further comprises a gate dielectric layer covering the pocket layer and a gate electrode covering the gate dielectric layer. The gate interface portion of the source region comprises at least three mutually non-coplanar surface segments. A method for manufacturing such a TFET device is also provided.

Подробнее
Номер записи: 45
12-07-2018 дата публикации

METHOD TO IMPROVE RELIABILITY OF REPLACEMENT GATE DEVICE

Номер: US20180197972A1
Автор: Ando Takashi, Cartier Eduard A., Choi Kisik, Narayanan Vijay
Принадлежит:

A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill. 1. A method of fabricating a gate stack for a semiconductor device , said method comprising steps of: forming a dielectric layer over an area vacated by the dummy gate;', 'depositing a metal layer over the dielectric layer;', 'depositing a sacrificial layer over the metal layer;', 'performing a first thermal anneal;', 'removing the sacrificial layer from the metal layer to expose a portion of the thin metal layer directly over a channel region of the semiconductor device; and', 'depositing a metal layer of low resistivity metal on the thin metal layer in the gate stack., 'after removal of a dummy gate, providing a replacement gate structure by performing steps of2. The method of claim 1 , further comprising:performing a second rapid thermal anneal after annealing the structure.3. The method of claim 2 , performing the second rapid thermal anneal comprises performing a millisecond anneal with a laser.4. The method of claim 2 , wherein performing the second rapid thermal anneal comprises performing a millisecond anneal with a flash lamp.5. The method of claim 1 , wherein performing the first rapid thermal anneal comprises annealing at a temperature between 800° C. and 1100° C.6. The method of claim 5 , wherein performing the first rapid thermal anneal further comprises spiking the temperature for a period of time up to five seconds.7. The method of claim 6 , wherein performing the first rapid thermal anneal comprises annealing the structure in ambient nitrogen.8. The method of claim 1 , wherein ...

Подробнее
Номер записи: 46
30-07-2015 дата публикации

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Номер: US20150214367A1
Автор: Chang Che-Cheng, CHANG YUNG JUNG, Chen Chang-Yin, LIN Chih-Han, Lin Jr-Jung
Принадлежит: Taiwan Semiconductor Manufacturing Company Ltd.

The present disclosure provides a semiconductor structure having a semiconductor layer; a gate with a conductive portion and a sidewall spacer; an interlayer dielectric (ILD) surrounding the sidewall spacer; and a nitrogen-containing protection layer, positioning at least on the top surface of the conductive portion of the gate. A top surface of the conductive portion and a top surface of the sidewall spacer are substantially coplanar. The nitrogen-containing protection layer is not covering the sidewall surface of the sidewall spacer. The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming a metal gate structure having a conductive portion and a sidewall spacer surrounded by a first ILD; forming a protection layer over the metal gate structure, and the protection layer is formed to cover at least the conductive portion of the metal gate structure; and forming a second ILD over the metal gate structure. 1. A semiconductor structure , comprising:a semiconductor layer;a gate comprising a conductive portion and a sidewall spacer, wherein a top surface of the conductive portion and a top surface of the sidewall spacer are substantially coplanar, and the gate is positioned over the semiconductor layer;an interlayer dielectric (ILD) surrounding a sidewall surface of the sidewall spacer, positioning over the semiconductor layer; anda nitrogen-containing protection layer, positioning at least on the top surface of the conductive portion of the gate,wherein the nitrogen-containing protection layer is not covering the sidewall surface of the sidewall spacer.2. The semiconductor structure in claim 1 , wherein the protection layer comprises at least one of sulfur nitride claim 1 , silicon nitride claim 1 , silicon oxynitride claim 1 , silicon carbonitride claim 1 , or combinations thereof.3. The semiconductor structure in claim 1 , wherein the protection layer is positioned on the top surface of the conductive portion ...

Подробнее
Номер записи: 47
19-07-2018 дата публикации

TRANSISTOR USING SELECTIVE UNDERCUT AT GATE CONDUCTOR AND GATE INSULATOR CORNER

Номер: US20180204926A1
Автор: Abou-Khalil Michel J., Botula Alan Bernard, Gross Blaine Jeffrey, Jaffe Mark David, Joseph Alvin, Phelps Richard A., SHANK Steven M., Slinkman James Albert
Принадлежит: GLOBALFOUNDRIES INC.

Methods form transistor structures that include, among other components, a substrate having an active region bordered by an isolation region, a gate insulator on the substrate, and a gate conductor on the gate insulator. First and second sections of the gate conductor are within the active region of the substrate, while a third section is in the isolation region of the substrate. The second section of the gate conductor tapers from the width of the first section to the width of the wider third section. The first section and the second section of the gate conductor have undercut regions where the corner of the gate conductor contacts the substrate. The third section of the gate conductor lacks the undercut regions. The gate insulator is relatively thicker in the undercut regions and is relatively thinner where the corner of the gate conductor lacks the undercut regions in the isolation region. 1. A method comprising:doping a substrate to have an active region bordered by an isolation region;doping the active region to have a channel area;growing a gate insulator on and contacting the channel area;patterning a gate conductor on and contacting the gate insulator, the gate insulator is between the gate conductor and the channel area, the gate conductor is patterned to extend from the active region to the isolation region, the gate conductor is patterned to have a first section, a second section, a third section, and a fourth section, the fourth section is perpendicular to the first section, the second section of the gate conductor is between the first section and the third section of the gate conductor, the first section of the gate conductor is within the active region and has a first width, the third section of the gate conductor is within the isolation region and has a second width that is greater than the first width, and the second section of the gate conductor is within the active region and has a tapered width that tapers from the first width to the second width; ...

Подробнее
Номер записи: 48
26-07-2018 дата публикации

METHODS OF MINIMIZING PLASMA-INDUCED SIDEWALL DAMAGE DURING LOW K ETCH PROCESSES

Номер: US20180211845A1
Автор: Hsu Chih-Yu, SHEN Peng, Stafford Nathan
Принадлежит:

Methods for minimizing plasma-induced sidewall damage during low k etch processes are disclosed. The methods etch the low k layers using the plasma activated vapor of an organofluorine compound having a formula selected from the group consisting of N≡C—R; (N≡C—)—(R)—(—C≡N); R[—C═N(R)]; and R—N—H, wherein a=1-2, x=1-2, y=1-2, z=0-1, x+z=1-3, and each R independently has the formula HFCwith a=0-11, b=0-11, and c=0-5. 1. A method for minimizing plasma-induced sidewall damage during a low k etch process to a difference of less than 11 nm before and after a wet or dry clean , the method comprising the steps of:depositing a patterned mask layer on a low k layer, the patterned mask layer having an opening that defines an area to produce an aperture in the low k layer;{'sub': x', 'z', 'y', 'a', 'b', 'c, 'etching the low k layer with a plasma activated vapor of a nitrogen containing etching composition to produce the aperture in the low k layer, the aperture having a first defined sidewall width, wherein the nitrogen containing etching composition comprises an organofluorine compound having a formula selected from the group consisting of N≡C—R; (N≡C—)—(R)—(—C≡N) and R[—C═N(R)], wherein x=1-2, y=1-2, z=0-1, x+z=1-3, and each R independently has the formula HFCwith a=0-11, b=0-11, and c=0-5; and'}removing the plasma-induced sidewall damage from the aperture to produce a second defined sidewall width, a difference between the first and second defined sidewall widths ranging between 0 nm to 11 nm.2. The method of claim 1 , wherein the low k layer comprises pores and a dielectric constant between 2.0 and 3.0 prior to the etching step.3. The method of claim 1 , wherein the mask layer is a titanium nitride claim 1 , amorphous carbon claim 1 , photoresist claim 1 , or silicon nitride layer.4. The method of claim 1 , wherein the difference between the first and second defined sidewall widths ranges between 0.1 nm to 10 nm.5. The method of claim 1 , wherein the difference between the ...

Подробнее
Номер записи: 49
04-08-2016 дата публикации

Process for single diffusion break with simplfied process

Номер: US20160225848A1
Автор: Bingwu Liu, Hui Zang
Принадлежит: Globalfoundries Inc

A method of forming a SDB including a protective layer or bilayer and the resulting device are provided. Embodiments include forming a SDB of oxide in a Si substrate; forming a nitride layer over the Si substrate; forming a photoresist over the SDB and a portion of the nitride layer; removing the nitride layer on opposite sides of the photoresist down to the Si substrate, leaving a portion of the nitride layer only under the photoresist; forming a gate above the SBD and the portion of the nitride layer.

Подробнее
Номер записи: 50
20-08-2015 дата публикации

METHOD TO IMPROVE RELIABILITY OF REPLACEMENT GATE DEVICE

Номер: US20150236135A1
Автор: Ando Takashi, Cartier Eduard A., Choi Kisik, Narayanan Vijay
Принадлежит:

A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill. 1. A method of fabricating a gate stack for a semiconductor device , said method comprising steps of: growing a high-k dielectric layer over an area vacated by the dummy gate;', 'depositing a thin metal layer over the high-k dielectric layer;', 'depositing a sacrificial layer over the thin metal layer;', 'performing a first rapid thermal anneal of the replacement gate structure at a high temperature of not less than 800° C.;', 'performing a millisecond anneal;', 'removing the sacrificial layer; and', 'depositing a metal layer for gap fill., 'after removal of a dummy gate, providing a replacement gate structure by performing steps of2. The method of wherein performing the first rapid thermal anneal comprises annealing at a temperature between 800° C. and 1100° C. claim 1 , inclusive.3. The method of further comprising claim 1 , after the step of removing the sacrificial layer:removing the thin metal layer;performing a second rapid thermal anneal at a temperature between 400° C. and 800° C., inclusive; andre-depositing a thin metal layer over the high-k dielectric layer.4. The method of wherein depositing the sacrificial layer comprises depositing a layer selected from poly-crystalline silicon and amorphous silicon. This application is a division of, and claims priority to copending U.S. patent application Ser. No. 14/595,756, filed on Jan. 13, 2015, which was in turn a division of issued U.S. Pat. No. 8,999,831 issued on Apr. 7, 2015, both incorporated by reference in their entirety, and wherein such ...

Подробнее
Номер записи: 51
27-08-2015 дата публикации

METHOD TO IMPROVE RELIABILITY OF REPLACEMENT GATE DEVICE

Номер: US20150243761A1
Автор: Ando Takashi, Cartier Eduard A., Choi Kisik, Narayanan Vijay
Принадлежит:

A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill. 1. A method of fabricating a gate stack for a FinFET device , said method comprising steps of: growing a high-k dielectric layer over an area vacated by the dummy gate;', 'depositing a thin metal layer over the high-k dielectric layer;', 'depositing a sacrificial layer over the thin metal layer;', 'annealing the replacement gate structure at a high temperature of not less than 800° C.;', 'performing a millisecond anneal;', 'removing the sacrificial layer; and', 'depositing a metal layer of low resistivity metal., 'after removal of a dummy gate, providing a replacement gate structure by performing steps of2. The method of wherein performing the millisecond anneal comprises performing a millisecond anneal with a flash lamp.3. The method of wherein annealing the structure comprises performing a rapid thermal anneal at a temperature between 800° C. and 1100° C. claim 1 , inclusive claim 1 , in ambient nitrogen. This application is a division of, and claims priority to copending U.S. patent application Ser. No. 14/595,756, filed on Jan. 13, 2015, which was in turn a division of issued U.S. Pat. No. 8,999,831 issued on Apr. 7, 2015, both incorporated by reference in their entirety, and wherein such applications were made by, on behalf of, and/or in connection with the following parties to a joint research agreement: International Business Machines Corporation and GlobalFoundries. The agreement was in effect on and before the date the claimed invention was made, and the claimed invention was made as a result ...

Подробнее
Номер записи: 52
27-08-2015 дата публикации

METHOD TO IMPROVE RELIABILITY OF REPLACEMENT GATE DEVICE

Номер: US20150243762A1
Автор: Ando Takashi, Cartier Eduard A., Choi Kisik, Narayanan Vijay
Принадлежит:

A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill. 1. A method of fabricating a gate stack for a FinFET semiconductor device , said method comprising steps of: growing a high-k dielectric layer over the replacement gate structure;', 'depositing a thin metal layer over the high-k dielectric layer;', 'depositing a sacrificial layer over the thin metal layer;', 'performing a first rapid thermal anneal at a high temperature not less than 800° C.;', 'performing a millisecond anneal;', 'removing the sacrificial layer; and', 'depositing a metal layer for gap fill., 'after removal of a dummy gate, providing a replacement gate structure by performing steps of2. The method of further comprising claim 1 , after the step of removing the sacrificial layer:removing the thin metal layer;performing a second rapid thermal anneal at a temperature between 400° C. and 800° C., inclusive; andre-depositing a thin metal layer over the high-k dielectric layer.3. The method of wherein performing the first rapid thermal anneal comprises performing a rapid thermal anneal at a temperature between 800° C. and 1100° C. claim 1 , inclusive claim 1 , in ambient nitrogen. This application is a division of, and claims priority to copending U.S. patent application Ser. No. 14/595,756, filed on Jan. 13, 2015, which was in turn a division of issued U.S. Pat. No. 8,999,831 issued on Apr. 7, 2015, both incorporated by reference in their entirety, and wherein such applications were made by, on behalf of, and/or in connection with the following parties to a joint research agreement: ...

Подробнее
Номер записи: 53
17-08-2017 дата публикации

PHOTOMASK AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME

Номер: US20170236707A1
Автор: KIM Yang-Nam
Принадлежит:

A photomask includes a reticle substrate, a main pattern disposed on the reticle substrate and defining a photoresist pattern realized on a semiconductor substrate, and anti-reflection patterns adjacent to the main pattern. A distance between a pair of the anti-reflection patterns adjacent to each other is a first length, and a width of at least one of the pair of anti-reflection patterns is a second length. A sum of the first length and the second length is equal to or smaller than a minimum pitch defined by resolution of an exposure process. A distance between the main pattern and the anti-reflection pattern nearest to the main pattern is equal to or smaller than the first length. 1. A photomask , comprising:a reticle substrate;a main pattern on the reticle substrate, the main pattern defining a photoresist pattern to be realized on a semiconductor substrate; andanti-reflection patterns adjacent to the main pattern, whereina distance between a pair of the anti-reflection patterns adjacent to each other is a first length,a width of at least one of the pair of anti-reflection patterns is a second length,a sum of the first length and the second length is equal to or smaller than a resolution of an exposure process, anda distance between the main pattern and the anti-reflection pattern nearest to the main pattern is equal to or smaller than the first length.2. The photomask as claimed in claim 1 , wherein a ratio of the second length to the first length ranges from 2:8 to 8:2.3. The photomask as claimed in claim 1 , wherein the anti-reflection patterns are not projected onto the semiconductor substrate in the exposure process.4. The photomask as claimed in claim 3 , wherein the sum of the first length and the second length is smaller than the resolution.5. The photomask as claimed in claim 1 , whereinthe main pattern includes a first portion extending in a first direction,the first portion has a first side parallel to the first direction,at least one of the anti- ...

Подробнее
Номер записи: 54
23-08-2018 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

Номер: US20180240721A1
Автор: Akino Masaru, Sakurai Hitomi
Принадлежит:

In a manufacturing step in which a structure of target of screening is formed on a semiconductor substrate in the middle of manufacturing process before a semiconductor device is finished, screening of potential defects of a gate insulating film is performed for each wafer at one time so that the semiconductor device is caused to appear as an initial defective product when the finished semiconductor device is subjected to an electrical characteristic test. Provided are a semiconductor device, and a method of manufacturing a semiconductor device which enables reliable screening of potential defects in a short period of time. 1. A method of manufacturing a semiconductor device , the semiconductor device having a gate insulating film and a gate electrode film on a semiconductor substrate of a wafer , the method comprising:forming the gate insulating film on the semiconductor substrate of the wafer;forming the gate electrode film on an entire surface of the semiconductor substrate of the wafer, the semiconductor substrate of the wafer including the gate insulating film;screening, after the forming the gate electrode film, the gate insulating film by generating a potential difference between the gate electrode film which is formed on the entire surface of the semiconductor substrate of the wafer, and a back surface of the semiconductor substrate of the wafer to apply an electric field to the gate insulating film;determining the semiconductor substrate of the wafer which has been subjected to the screening; andpatterning the gate electrode film after the determining the semiconductor substrate of the wafer.2. The method of manufacturing a semiconductor device according to claim 1 , further comprising claim 1 , between the forming the gate electrode film and the screening the gate insulating film claim 1 , removing the gate electrode film and the gate insulating film that are formed on the back surface of the semiconductor substrate of the wafer and a peripheral portion of ...

Подробнее
Номер записи: 55
10-09-2015 дата публикации

PLANARIZATION PROCESS

Номер: US20150255293A1
Автор: Zhu Huilong
Принадлежит:

Planarization processing methods are disclosed. In one aspect, the method includes patterning a material layer and planarizing the patterned material layer by using sputtering. Due to the patterning of the material layer, the loading requirements of nonuniformity on a substrate for sputtering the material layer are reduced, compared with that before the patterning. 1. A method of planarizing a material layer formed on a substrate , comprising:patterning the material layer; andplanarizing the patterned material layer by sputtering,wherein the patterning of the material layer results in a loading condition for the sputtering on the material layer having a lower non-uniformity across the substrate than that before the patterning.2. The method of claim 1 , wherein the substrate comprises a plurality of nonuniform features formed thereon claim 1 , and the material layer is formed on the substrate to cover the features.3. The method of claim 1 , wherein the material layer is patterned so that there are protrusions distributed in a substantially uniform manner on the patterned material layer.4. The method of claim 2 , wherein patterning the material layer comprises:coating photoresist on the material layer;patterning the photoresist with a first mask; andpatterning the material layer with the patterned photoresist, wherein the design of the first mask for patterning the photoresist is based on a second mask for forming the features in such a manner that there are protrusions distributed in a substantially uniform way on the patterned material layer.5. The method of claim 1 , wherein the material layer is patterned so that a portion of the material layer which has a relatively high loading condition is at least partly removed.6. The method of claim 2 , wherein patterning the material layer comprises:coating photoresist on the material layer;patterning the photoresist with a first mask, so as to expose at least a portion of a bulge on the material layer caused by the ...

Подробнее
Номер записи: 56
10-09-2015 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20150255553A1
Автор: NIITSUMA Kazunori
Принадлежит:

A semiconductor device having a groove provided in a semiconductor substrate, a gate insulating film provided so as to cover an inside surface of the groove, a first conductive film provided inside the groove in a position in which a first upper end surface is lower than the outer surface of the semiconductor substrate, a second conductive film provided inside the groove in a position that protrudes beyond the first upper end surface and in which a second upper end surface is higher than the outer surface of the semiconductor substrate, and a cap insulating film provided inside the groove so as to cover a protruding part of the second conductive film that protrudes beyond the first upper end surface. 1. A semiconductor device comprising:a groove provided in a semiconductor substrate;a gate insulating film provided in such a way as to cover the inner surfaces of the groove;inside the groove, a first conductive film, of which a first upper end surface is provided in a location that is lower than the surface of the semiconductor substrate;inside the groove, a second conductive film which protrudes from the first upper end surface, and of which a second upper end surface is provided in a location that is higher than the surface of the semiconductor substrate; anda cap insulating film provided in the groove in such a way as to cover the protruding portion of the second conductive film that protrudes from the first upper end surface.2. The semiconductor device of claim 1 , wherein the cap insulating film functions as part of the gate insulating film located on the first upper end surface.3. The semiconductor device of claim 2 , wherein the effective thickness of the gate insulating film in a region in which GIDL occurs is increased by causing the cap insulating film to function as part of the gate insulating film.4. The semiconductor device of claim 1 , wherein increases in the wiring resistance of the second conductive film are suppressed by providing the second upper ...

Подробнее
Номер записи: 57
01-10-2015 дата публикации

METHODS OF FORMING REPLACEMENT GATE STRUCTURES USING A GATE HEIGHT REGISTER PROCESS TO IMPROVE GATE HEIGHT UNIFORMITY AND THE RESULTING INTEGRATED CIRCUIT PRODUCTS

Номер: US20150279742A1
Автор: Cai Xiuyu, Cheng Kangguo, Khakifirooz Ali, Wedlake Michael, Xie Ruilong
Принадлежит: GLOBALFOUNDRIES INC.

One method disclosed includes, among other things, forming a gate registration structure above an isolation region, wherein the gate registration structure comprises a plurality of layers of material, the uppermost layer of which is a polish-stop layer, forming first and second sacrificial gate structures above first and second active regions, respectively, wherein the first and second sacrificial gate structures abut and engage opposite sides of the gate registration structure, and performing at least one first chemical mechanical polishing (CMP) process to remove the gate cap layer so as to thereby expose a sacrificial gate electrode in each of the first and second sacrificial gate structures, wherein the uppermost layer of the gate registration structure serves as a polish-stop layer during the at least one first CMP process. 1. A method , comprising:forming an isolation region in a semiconductor substrate layer so as to thereby define first and second spaced-apart active regions in said semiconductor substrate;forming a gate registration structure above said isolation region, wherein said gate registration structure comprises a plurality of layers of material, the uppermost layer of which is a polish-stop layer;forming a first sacrificial gate structure above said first active region and a second sacrificial gate structure above said second active region, wherein a first end surface of said first sacrificial gate structure abuts and engages a first side surface of said gate registration structure and a second end surface of said second sacrificial gate structure abuts and engages a second, opposite side surface of said gate registration structure; andperforming at least one first chemical mechanical polishing (CMP) process to remove at least a gate cap layer positioned above each of said first and second sacrificial gate structures so as to thereby expose an upper surface of a sacrificial gate electrode in each of said first and second sacrificial gate ...

Подробнее
Номер записи: 58
22-09-2016 дата публикации

INTEGRATED CIRCUITS USING SILICON ON INSULATOR SUBSTRATES AND METHODS OF MANUFACTURING THE SAME

Номер: US20160276210A1
Автор: PURAKH Raj Verma, SEE Guan Huei, TOH Rui Tze, Zhang Shaoqiang
Принадлежит:

Integrated circuits and methods for manufacturing the same are provided. A method for producing an integrated circuit includes forming a deep isolation block in an SOI substrate, where the SOI substrate includes a substrate layer overlying a buried insulator that in turn overlies a carrier wafer. The deep isolation block extends through the substrate layer and contacts the buried insulator. A shallow isolation block is formed in the substrate layer, where the shallow isolation block overlies a portion of the substrate layer. An isolation mask is formed overlying at least a portion of the deep isolation block to form a masked isolation block and an exposed isolation block, where the exposed isolation block includes the shallow isolation block. The exposed isolation block is removed such that a trough is defined in the substrate layer where the shallow isolation block was removed, and a gate is formed within the trough. 1. A method of manufacturing an integrated circuit comprising:forming a deep isolation block in an SOI substrate, wherein the SOI substrate comprises a buried insulator overlying a carrier wafer, a substrate layer overlying the buried insulator, and wherein the deep isolation block extends through the substrate layer and contacts the buried insulator;forming a shallow isolation block in the substrate layer, wherein the shallow isolation block overlies a portion of the substrate layer;forming an isolation mask overlying at least a portion of the deep isolation block to form a masked isolation block and an exposed isolation block, wherein the exposed isolation block comprises the shallow isolation block;removing the exposed isolation block such that a trough is defined in the substrate layer where the shallow isolation block was removed; andforming a gate within the trough.2. The method of wherein:forming the shallow isolation block comprises forming the shallow isolation block between adjacent deep isolation blocks;removing the exposed isolation block ...

Подробнее
Номер записи: 59
01-10-2015 дата публикации

METHODS OF FORMING SEMICONDUCTOR DEVICES USING A LAYER OF MATERIAL HAVING A PLURALITY OF TRENCHES FORMED THEREIN

Номер: US20150279972A1
Автор: JR. William J., Kim Ryan Ryoung-Han, Taylor, Xie Ruilong
Принадлежит: GLOBALFOUNDRIES INC.

One method disclosed includes, among other things, forming a plurality of laterally spaced-apart source/drain trenches and a gate trench in a layer of material above an active region, performing at least one process operation through the spaced-apart source/drain trenches to form doped source/drain regions, forming a gate structure within the gate trench, and forming a gate cap layer above the gate structure positioned within the gate trench. 1. A method of forming a device , comprising:forming a layer of material above at least an entire active region of a semiconductor substrate;forming a plurality of laterally spaced-apart source/drain trenches in said layer of material above said active region;performing at least one process operation through said spaced-apart source/drain trenches to form doped source/drain regions of said device;after forming said doped source/drain regions of said device, forming a gate trench at least partially in said layer of material between said spaced-apart source/drain trenches in said layer of material, wherein portions of said layer of material remain positioned between said source/drain trenches and said gate trench;forming a gate structure within said gate trench; andforming a gate cap layer above said gate structure positioned within said gate trench.2. The method of claim 1 , wherein said device is a FinFET device and wherein said source/drain regions are each comprised of at least one fin.3. The method of claim 1 , wherein said device is a planar device and wherein said source/drain regions are comprised of a substantially uniform layer of semiconductor material having a substantially uniform and planar upper surface.4. The method of claim 1 , wherein said gate structure is comprised of a high-k gate insulation material layer and a layer of conductive material positioned above said high-k gate insulation material layer.5. The method of claim 1 , further comprising forming a conductive source/drain contact structure within each ...

Подробнее
Номер записи: 60
22-09-2016 дата публикации

FORMING LOW PARASITIC TRIM GATE LAST MOSFET

Номер: US20160276466A1
Автор: Leobandung Effendi
Принадлежит:

A method for making a fin MOSFET with substantially reduced parasitic capacitance and/or resistance is provided. The fin MOSFET includes: a patterned fin structure on a substrate, the substrate including a first semiconductor layer; an epitaxy layer covering the substrate and a first portion of the fin structure, the first portion of the fin structure being doped to be integrated with the epitaxy layer, wherein a source and drain region is formed in the epitaxy layer; a metal gate high-k structure covering a second portion of the fin structure; a nitride structure covering the metal gate high-k structure; an oxide spacer structure enclosing the metal gate high-k structure and the nitride structure; and a metal contact structure for the source and drain region. 1. A method for fabricating a fin MOSFET with substantially reduced parasitic capacitance and resistance , comprising: patterning a dummy gate structure covering a first portion of the fin structure;', 'growing an epitaxy layer covering the substrate and a second portion of the fin structure, the second portion of the fin structure not being covered with the dummy gate structure and the second portion of the fin structure being doped to be integrated with the epitaxy layer, wherein a source and drain region is formed in the epitaxy layer;', 'depositing an oxide layer covering the epitaxy layer, a topmost surface of the oxide layer being planarized to be level with a topmost surface of the dummy gate structure;', 'removing the dummy gate structure to form a gate trench structure;', 'undercutting the epitaxy layer under the oxide layer along sidewalls of the gate trench structure to form an undercut structure;', 'forming a metal gate high-k structure by filling the undercut structure and a remaining portion of the gate trench structure with a high-k dielectric material and a metal gate material, a first portion of the metal gate high-k structure that fills the remaining portion of the gate trench structure being ...

Подробнее
Номер записи: 61
22-09-2016 дата публикации

Method and structure of making enhanced utbb fdsoi devices

Номер: US20160276480A1
Автор: Qing Liu, Thomas Skotnicki
Принадлежит: STMicroelectronics Crolles 2 SAS, STMicroelectronics lnc USA

An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material. A gate dielectric is positioned on a top surface and on the exposed side surface of the second layer of semiconductor material. A gate electrode is positioned on the top surface and the exposed side surface of the second layer of semiconductor material.

Подробнее
Номер записи: 62
21-09-2017 дата публикации

Implant Isolated Devices and Method for Forming the Same

Номер: US20170271386A1
Автор: Hsu Tzu-Hsuan, Hsu Wen-I, Kao Min-Feng, Liu Jen-Cheng, Wang Wen-De, Yaung Dun-Nian
Принадлежит:

A device includes a semiconductor substrate and implant isolation region extending from a top surface of the semiconductor substrate into the semiconductor substrate surrounding an active region. A gate dielectric is disposed over an active region of the semiconductor substrate, wherein the gate dielectric extends over the implant isolation region. A gate electrode is disposed over the gate dielectric and an end cap dielectric layer is between the gate dielectric and the gate electrode over the implant isolation region.

Подробнее
Номер записи: 63
18-12-2014 дата публикации

FINFET SPACER ETCH FOR eSiGe IMPROVEMENT

Номер: US20140367751A1
Автор: Khanna Puneet, Yang Hyucksoo, Yu Hong
Принадлежит:

A method for etching FinFET spacers by inserting a Si recess step directly after the traditional spacer ME step and the resulting device are provided. Embodiments include forming a gate on a substrate having a silicon fin, the gate having a nitride cap on an upper surface thereof and an oxide cap on an upper surface of the nitride cap; forming a dielectric layer over the silicon fin and the gate; removing the dielectric layer from an upper surface of the oxide cap and an upper surface of the silicon fin; recessing the silicon fin; and removing the dielectric layer from side surfaces of the silicon fin and the remaining silicon fin. 1. A method comprising:forming a gate on a substrate having a silicon fin, the gate having a nitride cap on an upper surface thereof and an oxide cap on an upper surface of the nitride cap;forming a dielectric layer over the silicon fin and the gate;removing the dielectric layer from an upper surface of the oxide cap and an upper surface of the silicon fin;recessing the silicon fin; andremoving the dielectric layer from side surfaces of the silicon fin and the remaining silicon fin.2. The method according to claim 1 , comprising recessing the silicon fin to a depth of 50 angstroms (Å) to 700 Å.3. The method according to claim 1 , comprising recessing the silicon fin with an etchant selective to oxide and nitride.4. The method according to claim 3 , wherein the etchant comprises of dry etchants including hydrogen bromide (HBr) claim 3 , sulfur hexafluoride (SF) claim 3 , nitrogen trifluoride (NF) claim 3 , carbon tetrafluoride (CF) claim 3 , or other fluorine based chemistries or wet etchants including tetra-methyl-ammonium hydroxide (TMAH) claim 3 , tetra-ethyl-ammonium hydroxide (TEAH) claim 3 , potassium hydroxide (KOH) claim 3 , or ammonium hydroxide (NHOH).5. The method according to claim 1 , comprising removing the dielectric layer from side surfaces of the silicon fin by etching.6. The method according to claim 5 , comprising ...

Подробнее
Номер записи: 64
18-12-2014 дата публикации

REMOVAL OF NITRIDE BUMP IN OPENING REPLACEMENT GATE STRUCTURE

Номер: US20140370697A1
Автор: Chen Tsung-Liang, Khanna Puneet, TAI Hsin-Neng, WANG Huey-Ming
Принадлежит:

Methods for opening polysilicon NFET and PFET gates for a replacement gate process are disclosed. Embodiments include providing a polysilicon gate with a nitride cap; defining PFET and NFET regions of the polysilicon gate, creating a nitride bump on the nitride cap; covering the nitride cap to a top of the nitride bump with a PMD; performing a 1:1 dry etch of the PMD and the nitride bump; and performing a second dry etch, selective to the nitride cap, down to the top surface of the polysilicon gate. Other embodiments include, after creating a nitride bump on the nitride cap, recessing the PMD to expose the nitride cap; covering the nitride cap and the nitride bump with a nitride fill, forming a planar nitride surface; and removing the nitride fill, nitride bump, and nitride cap down to the polysilicon gate. 1. A method comprising:providing a polysilicon gate with a nitride cap on a top surface thereof;defining PFET and NFET regions of the polysilicon gate, creating a nitride bump on a top surface of the nitride cap;covering the nitride cap to a top of the nitride bump with a pre-metal dielectric (PMD);performing a first dry etch comprising a 1:1 dry etch of the PMD and the nitride bump; andperforming a second dry etch, selective to the nitride cap, down to the top surface of the polysilicon gate.2. The method according to claim 1 , wherein the PMD comprises an oxide.3. The method according to claim 2 , wherein the first dry etch comprises a SiCoNi etch claim 2 , a remote plasma dry etch claim 2 , or a reactive ion etch (RIE).4. The method according to claim 3 , comprising performing the first dry etch at an etch rate of 30 to 150 nanometers (nm)/minute.5. The method according to claim 3 , comprising performing the first dry etch to a depth of 30 to 50 nm.6. The method according to claim 1 , wherein the second dry etch comprises a nitride RIE or a remote plasma dry etch.7. The method according to claim 6 , comprising performing the second dry etch at an etch rate of ...

Подробнее
Номер записи: 65
15-10-2015 дата публикации

HIGH VOLTAGE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR INTEGRATED INTO EXTREMELY THIN SEMICONDUCTOR ON INSULATOR PROCESS

Номер: US20150294984A1
Автор: Cheng Kangguo, Doris Bruce B., Khakifirooz Ali, Shahidi Ghavam G.
Принадлежит:

An electrical device including a first semiconductor device in a first region of the SOI substrate and a second semiconductor device is present in a second region of the SOI substrate. The first semiconductor device comprises a first source and drain region that is present in the SOI layer of the SOI substrate, raised source and drain regions on the first source and drain regions, and a first gate structure on a channel region portion of the SOI layer. The second semiconductor device comprises a second source and drain region present in a base semiconductor layer of the SOI substrate and a second gate structure, wherein a gate dielectric of the second gate structure is provided by a buried dielectric layer of the SOI substrate and a gate conductor of the second gate structure comprises a same material as the raised source and drain region. 1. A method of forming a semiconductor device comprising:forming isolation regions through a semiconductor on insulator (SOI) layer of a semiconductor on insulator (SOI) substrate to define a first device region and a second device region in the SOI substrate;forming a first semiconductor device in the first device region, wherein the first semiconductor device includes a first source region and a first drain region that is formed in the SOI layer, raised source and drain regions on the first source and drain regions, and a first gate structure on a channel region portion of the SOI layer; andforming a second semiconductor device in the second device region, wherein the second device includes a second source region and a second drain region that is present in a base semiconductor substrate of the SOI substrate, and a second gate structure including a gate dielectric provided by a buried dielectric layer of the SOI substrate and a gate conductor comprised of a same material as the raised source and drain regions.2. The method of claim 1 , wherein forming the isolation regions comprises:forming trenches through the SOI layer, the ...

Подробнее
Номер записи: 66
15-10-2015 дата публикации

Apparatus and method for manufacturing same

Номер: US20150295033A1
Автор: Mika Yoshida
Принадлежит: Longitude Semiconductor SARL

This apparatus is composed of an insulating film having a high dielectric constant and an electrode film including a metal material, layered in that order on a substrate divided into an active region and an element separation region surrounding the active region, and has a gate structure extending from the active region to the element separation region. The element separation region is provided with: a groove formed in the substrate; a first insulating film covering the side wall face of the groove and embedded in the bottom part of the groove; and a second insulating film covering the first insulating film embedded in the bottom part of the groove and embedded in the top part of the groove.

Подробнее
Номер записи: 67
27-08-2020 дата публикации

Antiferroelectric gate dielectric transistors and their methods of fabrication

Номер: US20200273962A1
Автор: Abhishek A. Sharma, Brian S. Doyle, Gilbert Dewey, Jack T. Kavalieros, Prashant Majhi, Ravi Pillarisetty, Willy Rachmady
Принадлежит: Intel Corp

A transistor, including an antiferroelectric (AFE) gate dielectric layer is described. The AFE gate dielectric layer may be crystalline and include oxygen and a dopant. The transistor further includes a gate electrode on the AFE gate dielectric layer, a source structure and a drain structure on the substrate, where the gate electrode is between the source structure and the drain structure. The transistor further includes a source contact coupled with the source structure and a drain contact coupled with the drain structure.

Подробнее
Номер записи: 68
20-10-2016 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Номер: US20160308031A1
Автор: Li Jhen-Cyuan, LU Shui-Yen
Принадлежит:

A semiconductor device comprises a substrate, a gate structure and a gate spacer. The substrate has a semiconductor fin protruding from a surface of the substrate. The gate structure is disposed on the semiconductor fin. The gate spacer is disposed on sidewalls of the gate structure, wherein the gate spacer comprises a first material layer and a second material layer stacked with each other and both of these two material layers are directly in contact with the gate structure. 1. A semiconductor device , comprising:a substrate, having a semiconductor fin protruding from a surface thereof;a gate structure, disposed on the semiconductor fin; anda gate spacer, disposed on sidewalls of the gate structure, wherein the gate spacer comprises a first material layer and a second material layer stacked with each other and both of the first material layer and the second material layer are directly in contact with the gate structure.2. The semiconductor device according to claim 1 , wherein the gate structure comprises:a high dielectric constant (K) layer, disposed on the semiconductor fin; anda metal gate electrode, disposed on the semiconductor fin.3. The semiconductor device according to claim 1 , wherein the first material layer comprises silicon oxide; and the second material layer comprises silicon nitride.4. The semiconductor device according to claim 1 , wherein the first material layer comprises silicon nitride; and the second material layer comprises silicon oxide.5. The semiconductor device according to claim 1 , wherein the semiconductor fin comprises a step structure. This application is a divisional application of co-pending U.S. application Ser. No. 14/556,690, filed Dec. 1, 2014, which claims the benefit of Taiwan application Serial No. 103136776, filed Oct. 24, 2014. All related applications are incorporated herein by reference in their entirety.1. Technical FieldThe disclosure in generally relates to a semiconductor device and method for fabricating the same, ...

Подробнее
Номер записи: 69
24-09-2020 дата публикации

LONGITUDINAL SILICON INGOT SLICING APPARATUS

Номер: US20200303199A1
Автор: Messinger Samuel
Принадлежит:

The present subject matter discloses a longitudinal silicon ingot slicing apparatus for lateral slicing of cylindrical ingot to maximize resulting chips yield as compared to the conventional transverse slicing of ingot. The resulting rectangular wafers made from lateral slicing of ingot maximizes yield as by the lateral slicing of ingot, overall chips per wafer ratio gets increased as compared to transversal cutting while the said apparatus and method decreases waste due to conflict between chip and wafer geometry. The novel apparatus of longitudinal slicing of cylindrical ingot is comprising of a wire wounded around a wire reels and a plurality of grooved rollers to form a wire raw to slice the cylindrical silicon ingot. A motors are connected with the wire reels and with at least one grooved roller to slide the wire row back and forth to cut the cylindrical ingot. A work feed table is also configured along with the JIG fixture that holds the cylindrical ingot as well as align the wire raw during slicing. 1. An apparatus for longitudinal slicing of a cylindrical ingot to maximize chip yield is comprising of:a wire wounded around at least one wire reel and a plurality of grooved rollers to form a wire raw via at least one wire traverse apparatus, a plurality of fixed guide rollers and at least one dancer roller at one end of the plurality of grooved rollers;the wire is then wounded up by at least one another wire reel via a plurality of guide rollers, at least one dancing roller and at least one another wire traverse apparatus at opposite end of the plurality of grooved rollers;a driving motors connected to both the wire reels and configured to rotate the wire reel in a forward and backward directions;at least one driving motor connected to at least one of the plurality of grooved rollers which is capable of rotating in a forward and backward directions; anda work feed table is configured to support the cylindrical ingot via an ingot mounting block and a slice base ...

Подробнее
Номер записи: 70
02-11-2017 дата публикации

METHOD FOR FORMING PATTERNS OF A SEMICONDUCTOR DEVICE

Номер: US20170316950A1
Автор: BYUN Kyungmun, DO Sinhae, IM Badro
Принадлежит:

A method for forming patterns of a semiconductor device includes sequentially forming a hard mask layer, a sacrificial layer, and an anti-reflection layer on a substrate, the substrate including a cell region and a peripheral circuit region, patterning the sacrificial layer to form a first sacrificial pattern on the cell region and a second sacrificial pattern on the peripheral circuit region, forming spacers covering sidewalls of the first and second sacrificial patterns, and removing the first sacrificial pattern. The anti-reflection layer includes a lower anti-reflection layer and an upper anti-reflection layer which are formed of materials different from each other. In the patterning of the sacrificial layer, the anti-reflection layer is patterned to form a first anti-reflection pattern on the first sacrificial pattern and a second anti-reflection pattern on the second sacrificial pattern. The second anti-reflection pattern remains when the first sacrificial pattern is removed. 1. A method for forming patterns of a semiconductor device , the method comprising:sequentially forming a hard mask layer, a sacrificial layer, and an anti-reflection layer on a substrate, the substrate including a cell region and a peripheral circuit region;patterning the sacrificial layer to form a first sacrificial pattern on the cell region and a second sacrificial pattern on the peripheral circuit region;forming spacers covering sidewalls of the first and second sacrificial patterns; andremoving the first sacrificial pattern,wherein the anti-reflection layer comprises: a lower anti-reflection layer and an upper anti-reflection layer which are formed of materials different from each other,wherein, in the patterning of the sacrificial layer, the anti-reflection layer is patterned to form a first anti-reflection pattern on the first sacrificial pattern and a second anti-reflection pattern on the second sacrificial pattern, andwherein the second anti-reflection pattern remains when the ...

Подробнее
Номер записи: 71
02-11-2017 дата публикации

COMMONLY-BODIED FIELD-EFFECT TRANSISTORS

Номер: US20170316986A1
Автор: Feng Kai D., Pei Chengwen, Wang Ping-Chuan
Принадлежит:

Structures for a commonly-bodied field-effect transistors and methods of forming such structures. The structure includes a body of semiconductor material defined by a trench isolation region in a semiconductor substrate. The body includes a plurality of first sections, a plurality of second sections, and a third section, the second sections coupling the first sections and the third section. The third section includes a contact region used as a common-body contact for at least the first sections. The first sections and the third section have a first height and the second sections have a second height that is less than the first height. 1. A structure comprising:a body of semiconductor material defined by a trench isolation region in a semiconductor substrate, the body including a plurality of first sections, a plurality of second sections, and a third section, the second sections coupling the first sections and the third section, and the third section including a contact region used as a common-body contact for at least the first sections,wherein the first sections and the third section have a first height and the second sections have a second height that is less than the first height, the semiconductor substrate is a silicon-on-insulator substrate that includes a device layer and a buried oxide layer, and the first sections, the second sections, and the third section comprise portions of the device layer.2. The structure of wherein the trench isolation region is comprised of an insulator that is co-planar with the semiconductor material of the first sections and the third section.3. The structure of wherein each of the first sections is associated with one of a corresponding plurality of field-effect transistors.4. The structure of wherein each of the first sections includes a source and a drain of the respective field-effect transistor.5. The structure of further comprising:a gate structure having a portion extending across the first sections between the source and ...

Подробнее
Номер записи: 72
01-11-2018 дата публикации

GATE CUT WITH HIGH SELECTIVITY TO PRESERVE INTERLEVEL DIELECTRIC LAYER

Номер: US20180315606A1
Автор: Greene Andrew M., Jung Ryan O., Xie Ruilong
Принадлежит:

A method for preserving interlevel dielectric in a gate cut region includes recessing a dielectric fill to expose cap layers of gate structures formed in a device region and in a cut region and forming a liner in the recess on top of the recessed dielectric fill. The liner includes a material to provide etch selectivity to protect the dielectric fill. The gate structures in the cut region are recessed to form a gate recess using the liner to protect the dielectric fill from etching. A gate material is removed from within the gate structure using the liner to protect the dielectric fill from etching. A dielectric gap fill is formed to replace the gate material and to fill the gate recess in the cut region. 1. A method for preserving interlevel dielectric in a gate cut region , comprising:forming a liner in a recess on top of a recessed dielectric fill recessed below a top surface of gate structures in a device region and in a cut region, the liner including a material to provide etch selectivity to protect the recessed dielectric fill; andforming a dielectric gap fill to replace a gate material and to fill a gate recess in the cut region using the liner to protect the recessed dielectric fill from being etched.2. The method as recited in claim 1 , wherein forming the liner includes:conformally depositing the liner over the gate structures and on the top of the recessed dielectric fill; andplanarizing the liner to remove the liner over the gate structures.3. The method as recited in claim 1 , wherein forming the liner includes: forming the liner from a material that resists etching during recessing the cap layer and removing the gate material.4. The method as recited in claim 1 , wherein forming the liner includes: forming the liner from TiN.5. The method as recited in claim 1 , further including recessing the gate structures in the cut region by patterning a mask layer to protect the device region and etching a cap layer of the gate structure in the cut region.6. The ...

Подробнее
Номер записи: 73
01-11-2018 дата публикации

Scalable sgt structure with improved fom

Номер: US20180315846A1
Автор: Madhur Bobde, Sik Lui
Принадлежит: Alpha and Omega Semiconductor Cayman Ltd

A shielded gate trench field effect transistor comprises an epitaxial layer above a substrate, a body region, a trench formed in the body region and epitaxial layer and one or more source regions formed in a top surface of the body region and adjacent a sidewall of the trench. A shield electrode is formed in a lower portion of the trench and a gate electrode is formed in an upper portion of the trench above the shield electrode. The shield electrode is insulated from the epitaxial layer by a first dielectric layer. The gate electrode is insulated from the epitaxial layer by the first dielectric layer and insulated from the shield electrode by a second dielectric layer. The first and second dielectric layer has a same thickness.

Подробнее
Номер записи: 74
10-10-2019 дата публикации

ENHANCEMENTS TO CELL LAYOUT AND FABRICATION TECHNIQUES FOR MOS-GATED DEVICES

Номер: US20190312106A1
Автор: Akiyama Hidenori, Blanchard Richard A., Rodov Vladimir, Tworzydlo Woytek
Принадлежит:

An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n− epi layer, a p-well, trenched insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The device may be formed of a matrix of cells or may be interdigitated. To turn the device on, a positive voltage is applied to the gate, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for rapidly turning the device off. The p-channel MOSFET may be made a depletion mode device by implanting boron ions at an angle into the trenches to create a p-channel. This allows the IGTO device to be turned off with a zero gate voltage while in a latch-up condition, when the device is acting like a thyristor. 1. A method for forming an electronic device as a die comprising:providing a trench in a semiconductor material, the trench having sidewalls;implanting dopants of a first conductivity type into a portion of at least one sidewall of the trench at an angle relative to the sidewall so that the dopants are substantially blocked from being implanted into a lower portion of the sidewall, the implanted dopants being for changing a threshold voltage (Vth) of a MOSFET having a channel along the sidewall of the trench;forming a first region of the first conductivity type to abut at least the lower portion of the sidewall;forming a second region of the first conductivity type to abut at least an upper portion of the sidewall such the channel extends between the first region and the second region;providing a dielectric layer along the sidewalls of the trench;at least partially filling the trench with a conductive material to form a vertical gate for the MOSFET, wherein a voltage applied to the gate controls a conductivity of the MOSFET; andforming a vertical, controllable conduction device whose conductivity is controlled by the voltage applied to the gate, ...

Подробнее
Номер записи: 75
14-12-2017 дата публикации

METHOD, APPARATUS AND SYSTEM FOR FABRICATING SELF-ALIGNED CONTACT USING BLOCK-TYPE HARD MASK

Номер: US20170358585A1
Автор: Kim Ryan Ryoung-Han, LIM Kwanyong, Xie Ruilong
Принадлежит: GLOBALFOUNDRIES INC.

At least one method, apparatus and system disclosed herein involves processing a semiconductor wafer using block mask design for manufacturing a finFET device. The gate structure comprising a source structure, and a drain structure of a transistor is formed. The gate structure is surrounded by an inter-layer dielectric (ILD) region. A 1st and a 2nd hard mask (HM) layer is formed above the gate structure and the ILD region. A 1st and 2nd block mask of a 1st and 2nd color are respectively formed. The 1st and 2nd HM layers are selectively etched based on the 1st and 2nd block mask layers for forming spaces for metal deposition. A contact metal deposition process is performed for forming a plurality of contact metal features. The 1st and 2nd HM layers are removed. A 3rd etch process is performed for etching back the contact metal features to form contact metal structures. 1. A method , comprising:forming a gate structure, a source structure, and a drain structure of a transistor, wherein said gate structure is surrounded by an inter-layer dielectric (ILD) region;forming a first hard mask layer above said gate structure and said ILD region;forming a second hard mask layer above said first hard mask layer;forming a first block mask of a first color;forming a second block mask of a second color;etching selectively said first and second hard mask layers based on said first and second block mask layers for forming spaces for metal deposition;performing a contact metal deposition process for forming a plurality of contact metal features;removing said first and second hard mask layers; andperforming a third etch process for etching back the contact metal features to form contact metal structures.2. The method of claim 1 , wherein forming said gate structure comprises:forming a gate structure;forming EPI formations above said source and drain fins;depositing a polysilicon (PC) hard mask layer over said gate structure;depositing an inter-dielectric (ILD) layer above a plurality ...

Подробнее
Номер записи: 76
05-07-2006 дата публикации

반도체 소자의 듀얼 다마신 식각 방법

Номер: KR20060077008A
Автор: 이기민
Принадлежит: 동부일렉트로닉스 주식회사

본 발명은 반도체 소자의 듀얼 다마신 제조 공정에서, 3원 리소그래픽 포토 마스크를 통해 얻어진 단차를 갖는 포토레지스트(PR)를 이용한 듀얼 다마신 식각 방법에 관한 것이다. 본 발명에 따른 반도체 소자의 듀얼 다마신 식각 방법은, a) 트렌치 또는 홀을 형성하고자 하는 절연막 상에 단차가 형성된 포토레지스트를 올려놓는 단계; b) 상기 포토레지스트의 내측 단차에 따라 상기 절연막 두께의 일부를 식각하는 단계; c) 상기 내측 단차가 있는 부분의 포토레지스트를 제거하는 단계; 및 d) 상기 내측 단차가 제거된 포토레지스트를 이용하여 트렌치(trench) 및 홀(hole)을 식각하는 단계를 포함한다. 본 발명에 따르면, 기존의 두개의 마스크를 이용하여 형성시킨 비아/트렌치 듀얼 다마신 공정을 하나의 마스크로 처리함으로써, 공정을 단순화하고, 원가를 절감하며, 환경 친화성을 향상시킬 수 있고, 또한, 두개의 마스크가 아니라 하나의 마스크를 이용함으로써, 마스크의 오정렬(misalign)을 방지할 수 있고, 이에 따라 공정 안정화를 기할 수 있다. 식각, 듀얼 다마신, 포토레지스트, 단차, 3원 리소그래픽

Подробнее
Номер записи: 77
24-04-2013 дата публикации

一种阵列基板的制备方法

Номер: CN103066017A
Автор: 郭建
Принадлежит: Beijing BOE Optoelectronics Technology Co Ltd

本发明实施例提供一种阵列基板的制备方法，涉及显示技术领域，可减少构图工艺次数，从而提升量产产品的产能，降低成本；该方法包括：在基板上形成包括栅电极，栅线引线的图案层；在基板上依次形成绝缘层薄膜和有源层薄膜，通过构图工艺形成带有第一过孔的栅绝缘层的图案以及有源层的图案，其中所述第一过孔位于所述栅线引线上方；在基板上依次形成透明导电薄膜和金属薄膜，通过构图工艺形成包括第一电极的图案层、以及包括数据线、源电极、漏电极和薄膜场效应晶体管TFT沟道的图案层；在基板上形成包括钝化层的图案；在基板上形成包括第二电极的图案层。

Подробнее
Номер записи: 78
09-03-2007 дата публикации

A method for dual damascene etching of semiconductor device

Номер: KR100691964B1
Автор: 이기민
Принадлежит: 동부일렉트로닉스 주식회사

본 발명은 반도체 소자의 듀얼 다마신 제조 공정에서, 3원 리소그래픽 포토 마스크를 통해 얻어진 단차를 갖는 포토레지스트(PR)를 이용한 듀얼 다마신 식각 방법에 관한 것이다. 본 발명에 따른 반도체 소자의 듀얼 다마신 식각 방법은, a) 트렌치 또는 홀을 형성하고자 하는 절연막 상에 단차가 형성된 포토레지스트를 올려놓는 단계; b) 상기 포토레지스트의 내측 단차에 따라 상기 절연막 두께의 일부를 식각하는 단계; c) 상기 내측 단차가 있는 부분의 포토레지스트를 제거하는 단계; 및 d) 상기 내측 단차가 제거된 포토레지스트를 이용하여 트렌치(trench) 및 홀(hole)을 식각하는 단계를 포함한다. 본 발명에 따르면, 기존의 두개의 마스크를 이용하여 형성시킨 비아/트렌치 듀얼 다마신 공정을 하나의 마스크로 처리함으로써, 공정을 단순화하고, 원가를 절감하며, 환경 친화성을 향상시킬 수 있고, 또한, 두개의 마스크가 아니라 하나의 마스크를 이용함으로써, 마스크의 오정렬(misalign)을 방지할 수 있고, 이에 따라 공정 안정화를 기할 수 있다. The present invention relates to a dual damascene etching method using a photoresist (PR) having a step obtained through a ternary lithographic photo mask in a dual damascene manufacturing process of a semiconductor device. A dual damascene etching method of a semiconductor device according to the present invention includes the steps of: a) placing a photoresist having a step formed on an insulating film to form a trench or a hole; b) etching a portion of the thickness of the insulating film according to an inner step of the photoresist; c) removing the photoresist of the inner stepped portion; And d) etching trenches and holes using the photoresist from which the inner step is removed. According to the present invention, by processing a via / trench dual damascene process formed using two existing masks with one mask, the process can be simplified, reduced cost, and improved environmental friendliness. By using one mask instead of two masks, misalignment of the mask can be prevented and thus process stabilization can be achieved. 식각, 듀얼 다마신, 포토레지스트, 단차, 3원 리소그래픽 Etch, Dual Damasin, Photoresist, Step, Three-Way Lithography

Подробнее
Номер записи: 79
11-05-2021 дата публикации

Trench gate structure and method of manufacturing the same

Номер: CN107527800B
Автор: 卞铮
Принадлежит: CSMC Technologies Fab2 Co Ltd

本发明涉及一种沟槽栅极结构及其制造方法。沟槽栅极结构包括衬底，衬底表面的沟槽，衬底上的绝缘衬垫，所述沟槽内表面的栅氧层，以及所述栅氧层上的多晶硅栅极，所述绝缘衬垫通过自身的斜坡结构与所述沟槽邻接，所述多晶硅栅极从沟槽内沿所述斜坡结构延伸至所述绝缘衬垫上，所述绝缘衬垫包括较衬垫的其他部分下凹的多晶硅栅极拉抬区，从沟槽中伸出的所述多晶硅栅极搭在所述多晶硅栅极拉抬区上。本发明沟槽内的多晶硅栅极与延伸至绝缘衬底上的部分相对独立，因此沟槽深度和接触孔深度不会相互构成限制。多晶硅栅极的光刻步骤与器件的多晶硅光刻在同一步中进行，不需要额外增加光刻版(mask)和光刻层次，因此不会造成这方面成本的提高。

Подробнее
Номер записи: 80
09-08-2013 дата публикации

Methods for fabricating semiconductor device with fine pattenrs

Номер: KR20130089120A
Автор: 강춘수
Принадлежит: 에스케이하이닉스 주식회사

반도체 기판에 활성 라인(active line)들을 형성하고, 활성 라인들을 교차하는 콘택 라인(contact line)들의 배열을 형성한 후, 활성 라인에 교차되는 콘택 라인 부분에 중첩되게 콘택 라인들을 교차하는 라인 패턴(line pattern)들을 포함하는 식각 마스크(mask)를 형성하고, 식각 마스크에 노출되는 상기 콘택 라인 부분들을 선택적으로 식각하여 콘택 패턴들 및 사이의 콘택 분리 홈들을 형성하고, 콘택 분리 홈들에 노출되는 활성 라인 부분들을 선택적으로 식각하여 활성 패턴 분리 홈들을 형성하여 개개의 활성 패턴들을 분리하고, 활성 패턴들을 가로지르는 트랜지스터의 게이트(gate)들을 형성하고, 콘택 패턴들에 연결되는 비트 라인(bit line)들을 형성하는 반도체 소자 제조 방법을 제시한다.

Подробнее
Номер записи: 81
02-05-2007 дата публикации

Method for forming a pattern of semiconductor device

Номер: KR100714287B1
Автор: 대 영 서, 상 엽 한
Принадлежит: 주식회사 하이닉스반도체

본 발명은 패턴 밀도가 높은 셀 영역과 상대적으로 패턴 밀도가 낮은 페리 영역 간의 식각 바이어스 차이를 줄이면서, 페리 영역에서 발생하는 붕괴현상을 방지할 수 있는 반도체 소자의 패턴 형성방법을 제공하기 위한 것으로, 이를 위해 본 발명에서는 조밀한 패턴이 형성될 제1 지역과 상기 제1 지역보다 조밀하지 않은 패턴이 형성될 제2 지역이 정의된 기판을 제공하는 단계와, 상기 기판 상에 게이트 절연막, 게이트 전극층, 질화막 계열의 제1 하드마스크 및 금속 계열의 제2 하드마스크를 증착하는 단계와, 상기 제2 하드마스크 상에 상기 제1 지역에서는 패턴 간 간격이 좁고 상기 제2 지역에서는 패턴 간 간격이 넓은 포토레지스트 패턴을 형성하는 단계와, 상기 포토레지스트 패턴을 통해 상기 제2 하드마스크를 식각하여 상기 포토레지스트 패턴과 동일한 제1 하드마스크 패턴을 형성하는 단계와, 상기 포토레지스트 패턴을 제거하는 단계와, 식각 바이어스 조절용 식각공정을 통해 상기 제1 하드마스크를 식각하여 상기 제1 하드마스크 패턴보다 작은 폭을 갖는 제2 하드마스크 패턴을 형성하는 단계와, 상기 제1 하드마스크 패턴을 제거하는 단계와, 상기 제2 하드마스크 패턴을 통해 상기 게이트 전극층을 식각하여 상기 제1 지역 및 상기 제2 지역에서 모두 버티컬한 구조의 게이트 패턴을 형성하는 단계를 포함하는 반도체 소자의 패턴 형성방법을 제공한다. The present invention is to provide a method for forming a pattern of a semiconductor device capable of preventing the collapse phenomenon occurring in the ferry region while reducing the etching bias difference between the cell region having a high pattern density and the ferry region having a relatively low pattern density. To this end, the present invention provides a substrate in which a first region in which a dense pattern is to be formed and a second region in which a pattern less dense than the first region is to be defined are provided, a gate insulating film, a gate electrode layer, Depositing a first hard mask based on the nitride layer and a second hard mask based on the metal layer; and forming a photoresist on the second hard mask in the first region and narrowing the pattern between the patterns in the second region. Forming a pattern, and etching the second hard mask through the photoresist pattern and the photoresist pattern; Forming the same first hard mask pattern, removing the photoresist pattern, and etching the first hard mask through an etching process for adjusting the etching bias to have a second width having a smaller width than that of the first hard mask pattern. Forming a hard mask pattern, removing the first hard mask pattern, and etching the gate ...

Подробнее
Номер записи: 82
18-08-2020 дата публикации

COMPOSITIONS AND METHODS FOR LABELING HYDROCARBON COMPOSITIONS WITH NON-MUTAGENIC DYES

Номер: RU2019104091A
Автор: Майкл ФРИСВЕЛЛ, Томас И. НОВАКОВСКИ, Хареш ДОШИ
Принадлежит: Юнайтед Колор Мэньюфэкчеринг, Инк.

РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 2019 104 091 A (51) МПК C09B 31/068 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ЗАЯВКА НА ИЗОБРЕТЕНИЕ (21)(22) Заявка: 2019104091, 14.07.2017 (71) Заявитель(и): ЮНАЙТЕД КОЛОР МЭНЬЮФЭКЧЕРИНГ, ИНК. (US) Приоритет(ы): (30) Конвенционный приоритет: 15.07.2016 US 62/362,975 (85) Дата начала рассмотрения заявки PCT на национальной фазе: 15.02.2019 R U (43) Дата публикации заявки: 18.08.2020 Бюл. № 23 (72) Автор(ы): ДОШИ Хареш (US), ФРИСВЕЛЛ Майкл (US), НОВАКОВСКИ Томас И. (US) (86) Заявка PCT: (87) Публикация заявки PCT: WO 2018/013904 (18.01.2018) A Адрес для переписки: 129090, Москва, ул. Б.Спасская, 25, строение 3, ООО "Юридическая фирма Городисский и Партнеры" R U (57) Формула изобретения 1. Соединение следующей формулы: A 2 0 1 9 1 0 4 0 9 1 (54) КОМПОЗИЦИИ И СПОСОБЫ МАРКИРОВКИ УГЛЕВОДОРОДНЫХ КОМПОЗИЦИЙ НЕМУТАГЕННЫМИ КРАСИТЕЛЯМИ 2 0 1 9 1 0 4 0 9 1 US 2017/042096 (14.07.2017) в которой R означает метильную группу, этильную группу или изопропильную группу, R1 является метильной группой, этильной группой или изопропильной группой, R2 является алкильной группой, содержащей от 3 до 12 атомов углерода, и n является целым числом от 1 до 3. 2. Соединение по п. 1, причем R является метильной группой. 3. Соединение по п. 1, причем R1 является метильной группой. 4. Соединение по п. 1, причем R является этильной группой или изопропильной группой. 5. Соединение по п. 1, причем R1 является этильной группой или изопропильной Стр.: 1 Стр.: 2 A 2 0 1 9 1 0 4 0 9 1 R U A в которой R и R1 являются метильной группой, этильной группой или изопропильной группой, R2 является алкильной группой, содержащей от 3 до 12 атомов углерода, и n является целым числом от 1 до 3. 2 0 1 9 1 0 4 0 9 1 в которой R означает метильную группу, этильную группу или изопропильную группу, R1 является метильной группой, этильной группой или изопропильной группой, R2 является алкильной группой, содержащей от 3 до 12 атомов углерода, и n является ...

Подробнее
Номер записи: 83
23-09-2003 дата публикации

Epitaxial silicon growth and usage of epitaxial gate insulator for low power, high performance devices

Номер: US6624488B1
Автор: Hyeon-Seag Kim
Принадлежит: Advanced Micro Devices Inc

A method for reducing off-state leakage current of a MOSFET while promoting the formation of an epitaxial gate insulator layer between the substrate and gate stack includes implanting source/drain dopant into the substrate, and then forming a very thin epitaxial Silicon layer on the substrate by, e.g., molecular beam epitaxy. The high-k gate insulator layer is then deposited on the epitaxial layer, without an interfering native oxide or interfacial oxide being formed between the insulator layer and substrate, while establishing a very steep retrograde dopant profile and hence reducing off-state leakage current through the channel region.

Подробнее
Номер записи: 84
08-06-2016 дата публикации

The manufacture method of a kind of semiconducter device

Номер: CN103730342B
Автор: 何有丰, 林静
Принадлежит: Semiconductor Manufacturing International Shanghai Corp

本发明提供一种半导体器件的制造方法，包括：提供半导体衬底，在所述半导体衬底上依次形成界面层、高k介电层、覆盖层和牺牲栅极材料层；执行第一湿法清洗，以去除所述半导体衬底的背面上形成的牺牲栅极材料层；对所述半导体衬底依次进行表面氧化处理和第二湿法清洗，以去除所述第一湿法清洗在位于所述半导体衬底正面的牺牲栅极材料层的表面造成的粒子缺陷。根据本发明，形成的所述牺牲栅极材料层的粒子缺陷会显著减少，从而不会影响实施后续工艺的质量。

Подробнее
Номер записи: 85
13-08-2013 дата публикации

Method of laser irradiation, laser irradiation apparatus, and method of manufacturing a semiconductor device

Номер: US8507334B2
Автор: Koichiro Tanaka, Tomoaki Moriwaka
Принадлежит: Semiconductor Energy Laboratory Co Ltd

If an optical path length of an optical system is reduced and a length of a laser light on an irradiation surface is increased, there occurs curvature of field which is a phenomenon that a convergent position deviates depending on an incident angle or incident position of a laser light with respect to a lens. To avoid this phenomenon, an optical element having a negative power such as a concave lens or a concave cylindrical lens is inserted to regulate the optical path length of the laser light and a convergent position is made coincident with a irradiation surface to form an image on the irradiation surface.

Подробнее
Номер записи: 86
16-07-2019 дата публикации

The method and structure of production enhancing UTBB FDSOI device

Номер: CN106158878B
Автор: T·斯科特尼基, 柳青
Принадлежит: Italy Semiconductor (krol 2) Co, STMicroelectronics lnc USA

本公开涉及制作增强UTBB FDSOI器件的方法和结构。一种集成电路裸片包括具有第一半导体材料层、在第一半导体材料层上的电介质材料层以及在电介质材料层上的第二半导体材料层的衬底。晶体管的延伸沟道区域被定位在第二半导体材料层中，与第二半导体材料层的顶表面、侧表面以及潜在地底表面的部分相互作用。栅极电介质被定位在第二半导体材料层的顶表面上和暴露的侧表面上。栅极电极被定位在第二半导体材料层的顶表面和暴露的侧表面上的栅极电介质上。

Подробнее
Номер записи: 87
25-01-2023 дата публикации

Epitaxial substrate for semiconductor device, semiconductor device, and method for manufacturing epitaxial substrate for semiconductor device

Номер: KR102491830B1
Автор: 미키야 이치무라, 소타 마에하라, 요시타카 구라오카
Принадлежит: 엔지케이 인슐레이터 엘티디

누설 전류가 억제되어 이루어지며 또한 내압이 높은 반도체 소자용의 에피택셜 기판을 제공한다. 반도체 소자용 에피택셜 기판에 있어서, Zn이 도핑된 GaN으로 이루어지는 반절연성의 자립 기판과, 자립 기판에 인접하여 이루어지는 13족 질화물로 이루어지는 버퍼층과, 버퍼층에 인접하여 이루어지는 13족 질화물로 이루어지는 채널층과, 채널층을 사이에 두고서 버퍼층과는 반대쪽에 마련되어 이루어지는 13족 질화물로 이루어지는 장벽층을 포함하고, 자립 기판과 버퍼층으로 이루어지는 제1 영역의 일부가 Si를 1×10 17 cm -3 이상의 농도로 포함하는 제2 영역이고, 제2 영역에 있어서의 Zn의 농도의 최소치가 1×10 17 cm -3 이도록 했다.

Подробнее
Номер записи: 88
28-12-2016 дата публикации

The manufacture method of cmos device

Номер: CN104217999B
Автор: 罗啸, 郭振强, 陈华伦, 陈瑜, 马斌
Принадлежит: Shanghai Huahong Grace Semiconductor Manufacturing Corp

本发明公开了一种CMOS器件的制造方法，包括步骤：形成浅沟槽场氧并隔离出有源区。形成CMOS器件的阱区。在硅衬底的正面依次生长栅氧化层、多晶硅层并对多晶硅层进行掺杂。依次沉积金属硅化钨层和顶层氮化硅层。采用光刻工艺定义出栅极图形，采用较重聚合物方式刻蚀依次对顶层氮化硅层、金属硅化钨层进行干法刻蚀，对多晶硅层进行干法刻蚀工艺形成栅极结构。形成仅覆盖在顶层氮化硅层、金属硅化钨层的侧面的第一介质层侧墙。本发明能够提高CMOS器件的自对准接触孔和栅极之间的击穿电压，提高器件的性能。

Подробнее
Номер записи: 89
07-12-1999 дата публикации

Formation of oxynitride and polysilicon layers in a single reaction chamber

Номер: US5998270A
Автор: Mark C. Gilmer, Mark I. Gardner
Принадлежит: Advanced Micro Devices Inc

A semiconductor device fabrication process in which an oxynitride layer and a polysilicon layer are formed in the same reaction chamber is provided. In accordance with one embodiment of the invention, a semiconductor device is formed by forming, in a reaction chamber, an oxynitride layer on a surface of a substrate and forming, in the same reaction chamber, a polysilicon layer over the oxynitride layer. The oxynitride layer may be used to form a gate oxide and the polysilicon layer used to form a gate electrode.

Подробнее
Номер записи: 90
05-02-2016 дата публикации

Method for transferring highly conductive pedot:pss based electrode

Номер: KR101592371B1
Автор: 김나라, 이광희, 이종훈
Принадлежит: 광주과학기술원

A method for transferring a highly conductive PEDOT:PSS based electrode is provided. The method comprises the following steps of: preparing a thin PEDOT:PSS film processed by a solution containing sulfuric acid or a sulfuric acid derivative wherein the thin PEDOT:PSS film is formed on a base donor material; attaching the thin PEDOT:PSS film to a polymer stamp to separate the thin PEDOT:PSS film from the base donor material; and transferring the thin PEDOT:PSS film, which is separated by being attached to the polymer stamp, on a target base material. According to the present invention, manufactured is a PEDOT:PSS based electrode which obtains processability, a light weight, flexibility, a simple coating process, low production costs, and the like and simultaneously realizes a device performance of high efficiency by preventing damage of a configuration element of a device such as a base material (or substrate) and the like while having high conductivity.

Подробнее
Номер записи: 91
14-01-2010 дата публикации

Transistor device

Номер: US20100006954A1
Автор: Hui-Lan Chang, Shin-Yu Nieh, Tsai-Yu Huang
Принадлежит: Nanya Technology Corp

A transistor device includes a semiconductor substrate, a source doping region and a drain doping region in the semiconductor, a channel region between the source doping region and the drain doping region, a gate stack on the channel region, wherein the gate stack includes an amorphous interfacial layer, a crystalline metal oxide gate dielectric layer and a gate conductor.

Подробнее
Номер записи: 92
26-09-2006 дата публикации

In situ growth of oxide and silicon layers

Номер: US7112538B2
Автор: Armand Ferro, Derrick Foster, Ivo Raaijmakers
Принадлежит: ASM America Inc

A single-wafer, chemical vapor deposition reactor is provided with hydrogen and silicon source gas suitable for epitaxial silicon deposition, as well as a safe mixture of oxygen in a non-reactive gas. Methods are provided for forming oxide and silicon layers within the same chamber. In particular, a sacrificial oxidation is performed, followed by a hydrogen bake to sublime the oxide and leave a clean substrate. Epitaxial deposition can follow in situ. A protective oxide can also be formed over the epitaxial layer within the same chamber, preventing contamination of the critical epitaxial layer. Alternatively, the oxide layer can serve as the gate dielectric, and a polysilicon gate layer can be formed in situ over the oxide.

Подробнее
Номер записи: 93
22-11-2022 дата публикации

Composition for wet Etching of polysilicon and method for manufacturing semiconductor device using the same

Номер: KR102468776B1
Автор: 김호영, 배상원, 백재직, 최원상
Принадлежит: 삼성전자주식회사

본 발명은 폴리실리콘 습식 식각용 조성물 및 이를 이용한 반도체 소자의 제조 방법에 관한 것으로, 보다 상세하게는 염기성 화합물 및 당 알코올을 포함한다. 상기 염기성 화합물은, 암모늄 하이드록사이드 또는 테트라알킬 암모늄 하이드록사이드를 포함하고, 상기 염기성 화합물 100 중량부에 대하여 상기 당 알코올은 0.1 내지 10 중량부를 갖는다. The present invention relates to a polysilicon wet etching composition and a method for manufacturing a semiconductor device using the same, and more particularly, includes a basic compound and a sugar alcohol. The basic compound includes ammonium hydroxide or tetraalkyl ammonium hydroxide, and the sugar alcohol has 0.1 to 10 parts by weight based on 100 parts by weight of the basic compound.

Подробнее
Номер записи: 94
01-12-2010 дата публикации

Graph exposure method, conducting film manufacture method and conducting film

Номер: CN101900950A
Автор: 三桥大助, 松田豊美, 须藤淳, 马场友纪
Принадлежит: Fujifilm Corp

提供了一种图形曝光方法、导电膜制造方法和导电膜，其中，感光材料借助于布置在70至200μm的贴近间隙内的光掩模经受接近式曝光，并且因此而在掩模图形中沿传送方向周期性地曝光以获得导电膜(10)。导电膜(10)具有多个由第一和第二导电金属细线(12a，12b)形成的导电部分(12)和多个开口部分(14)。每个金属细线(12a，12b)的侧面具有从表示金属细线(12a，12b)设计宽度(Wc)的假想线(m)朝向开口部分(14)延伸的鼓出部(26)，并且鼓出部(26)的鼓出量(da)为设计宽度(Wc)的1/25至1/6。

Подробнее
Номер записи: 95
23-08-2018 дата публикации

Epitaxial substrate for semiconductor element, semiconductor element, and manufacturing method of epitaxial substrate for semiconductor element

Номер: JPWO2017077805A1
Автор: 倉岡　義孝, 宗太 前原, 幹也 市村
Принадлежит: NGK Insulators Ltd

リーク電流が抑制されてなり、かつ、耐圧の高い半導体素子用のエピタキシャル基板を提供する。半導体素子用エピタキシャル基板において、ＺｎがドープされたＧａＮからなる半絶縁性の自立基板と、自立基板に隣接してなる、１３族窒化物からなるバッファ層と、バッファ層に隣接してなる、１３族窒化物からなるチャネル層と、チャネル層を挟んでバッファ層とは反対側に設けられてなる、１３族窒化物からなる障壁層と、を備え、自立基板とバッファ層とからなる第１の領域の一部がＳｉを１×１０１７ｃｍ−３以上の濃度で含む第２の領域であり、第２の領域におけるＺｎの濃度の最小値が１×１０１７ｃｍ−３である、ようにした。

Подробнее
Номер записи: 96
30-07-2019 дата публикации

Semiconductor devices and FinFET devices having shielding layers

Номер: US10367078B2
Автор: Che-Hao Chang, Cheng-Hao Hou, Chi-On CHUI, Chia-Yuan Chang, Kuei-Lun Lin, Kun-Yu LEE, Xiong-Fei Yu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Semiconductor devices, FinFET devices and methods of forming the same are disclosed. One of the semiconductor devices includes a substrate and a gate structure over the substrate. The gate structure includes a high-k layer over the substrate, a shielding layer over the high-k layer, and an N-type work function metal layer over the shielding layer. In some embodiments, the shielding layer has a dielectric constant less than a dielectric constant of the high-k layer.

Подробнее
Номер записи: 97
15-12-2016 дата публикации

SELF-ALIGNED BOTTOM-UP-GATE CONTACT AND TOP-DOWN SOURCE-DRAIN CONTACT STRUCTURE IN THE PREMETALIZED DIELECTRIC LAYER OR INTERMEDIATE DIELECTRIC LAYER OF AN INTEGRATED CIRCUIT

Номер: DE102015120483A1
Автор: John H. Zhang
Принадлежит: STMicroelectronics lnc USA

Eine integrierte Schaltung enthält eine Source-Drain-Region, eine Kanalregion, welche der Source-Drain-Region benachbart ist, eine Gate-Struktur, welche sich über die Kanalregion erstreckt und einen Seitenwand-Abstandshalter auf einer Seite der Gate-Struktur, welcher sich über die Source-Drain-Region erstreckt. Es ist eine Dielektrikumsschicht vorgesehen, welche mit dem Seitenwand-Abstandshalter in Kontakt steht und eine obere Fläche aufweist. Die Gate-Struktur enthält eine Gate-Elektrode und einen Gate-Kontakt, welcher sich von der Gate-Elektrode als Vorsprung erstreckt, um die obere Fläche zu erreichen. Die Seitenflächen der Gate-Elektrode und ein Gate-Kontakt fluchten miteinander. Die Gate-Dielektrikumsschicht für den Transistor, welche zwischen der Gate-Elektrode und der Kanalregion liegt, erstreckt sich zwischen der Gate-Elektrode und dem Seitenwand-Abstandshalter und außerdem zwischen dem Gate-Kontakt und dem Seitenwand-Abstandshalter. An integrated circuit includes a source-drain region, a channel region adjacent to the source-drain region, a gate structure extending over the channel region, and a sidewall spacer on a side of the gate structure that extends extends over the source-drain region. A dielectric layer is provided which is in contact with the sidewall spacer and has an upper surface. The gate structure includes a gate electrode and a gate contact extending from the gate electrode as a protrusion to reach the top surface. The side surfaces of the gate electrode and a gate contact are aligned with each other. The gate dielectric layer for the transistor, which is between the gate electrode and the channel region, extends between the gate electrode and the sidewall spacer and also between the gate contact and the sidewall spacer.

Подробнее
Номер записи: 98
31-10-2013 дата публикации

Semiconductor structure and manufacturing method therefor

Номер: WO2013159455A1
Автор: 何卫, 朱慧珑
Принадлежит: 中国科学院微电子研究所

Provided is a manufacturing method for a semiconductor structure, which comprises: providing a single crystal substrate (100) of a first semiconductor material; growing a single crystal epitaxial layer (110) of a second semiconductor material epitaxially on the surface of the substrate (100); forming a shallow trench isolation structure (210) which is filled with a trench insulation substance, penetrates through the epitaxial layer and enters into the substrate at a certain depth; patterning the trench insulation substance in the shallow trench isolation structure (210) and the epitaxial layer (110) to form a pseudo gate electrode; forming a side wall (310) around the pseudo gate electrode, the material of the side wall (310) being different from the trench insulation substance and the second semiconductor material; forming an interlayer dielectric layer (400) which covers the whole semiconductor structure; removing a part of the interlayer dielectric layer (400) to expose the pseudo gate electrode; removing the pseudo gate electrode to form a gate electrode depression (500); and forming a gate dielectric layer (600) and a gate electrode layer (610) in the gate electrode depression (500). The present invention is beneficial for reducing the roughness of the surfaces of both sides of the gate electrode. Also provided is a semiconductor structure which is manufactured according to the abovementioned method.

Подробнее
Номер записи: 99
25-08-2006 дата публикации

In situ growth of oxide and silicon layers

Номер: KR20060093740A
Автор: 데릭 포스터
Принадлежит: 에이에스엠 아메리카, 인코포레이티드

매엽식 웨이퍼 화학증착 리액터(10)는 비반응 가스 내의 산소의 안전한 혼합물(70)은 물론 에피택셜 실리콘 증착에 적합한 수소 및 실리콘 소스가스(72, 72, 86)를 구비한다. 동일 챔버 내에서 산화물층과 실리콘층을 형성하는 방법이 제공된다. 특히, 희생 산화 공정(102)이 행해진 후, 수소 베이킹(104)에 이어져 산화물층을 승화시켜 깨끗한 표면을 형성한다. 에피택셜 증착 공정(106)이 동일한 장소(챔버)에서 뒤따를 수 있다. 보호 산화물이 동일 챔버 내의 에피택셜층 위에 형성되어(108), 중요한 에피택셜층의 오염을 방지할 수 있다. 이에 대한 대안으로, 산화물층(124)이 게이트 유전체로 이용될 수 있고, 폴리실리콘 게이트층(126)이 산화물(124) 위에 동일한 장소(챔버)에서 형성될 수 있다. 매엽식 웨이퍼, 화학증착 리액터, 에피택셜 실리콘 증착, 산화물층, 희생 산화 공정, 챔버, 폴리실리콘 게이트층

Подробнее
Номер записи: 100