Improvements in or relating to methods of providing a semi-conductive body of cadmium-telluride with a tellurium layer

A tellurium layer is formed on a cadmium telluride body by treating it with an oxidizing solution to superficially convert it to Te. The strength of the oxidizing effect which determines whether converversion takes place at all and whether TeO is formed instead depends on the oxidizing substance, solution concentration and acidity, temperature, and duration of treatment. Suitable oxidizing substances are iodine, ferric chloride, hydrogen peroxide, nitric acid and cerium sulphate, preferably acidified with hydrochloric acid. In one example of CdTe plate of P type conductivity is treated with a 0.3 per cent solution of FeCl3 at 70 DEG C. for 5 minutes, and in a further example a plate of N type CdTe crystal is treated at 40 DEG C. with a solution of 20.2 per cent HCl and 3 per cent HNO3. The bodies thus produced may be used to form semiconductor devices (see Group XXXVI). The Specification contains a table showing the oxidizing effect of various oxidizing solutions of different concentrations ...

CORRODE FROM AMORPHOUS SEMICONDUCTOR OXIDES WITH AN ALKALI ETCHING SOLUTION

METHOD OF FORMING OHMIC CONTACTS

A method of forming ohmic contacts with thin film p-type semiconductor Class II B - VI A compounds comprising etching the film surface with an acidic solution, then etching with a strong basic solution and finally depositing a conductive metal layer.

METHOD OF FORMING OHMIC CONTACTS

Verfahren zur Herstellung einer Tellurschicht auf einem aus Cadmiumtellurid bestehenden, halbleitenden Körper

화학기계적연마장치용 캐리어헤드

... 본 발명은 화학기계적연마장치용 캐리어헤드에 관한 것이다. 본 발명에 따른 캐리어헤드는, 베이스와; 기판을 수용하는 외부면과 상기 외부면 반대쪽의 내부면을 포함하는 밑판, 상기 밑판의 가장자리로부터 높이 방향으로 연장되는 외주부, 상기 외주부의 외측으로부터 갈라져 나와 상기 베이스 하부에 연결되는 체결부, 그리고 상기 외주부의 내측으로부터 갈라져 나온 접촉부를 구비한 기판수용부재와; 상기 베이스 하부에 연결되어 상기 접촉부와의 접촉면을 제공하는 접촉대응구조; 및 상기 접촉부가 유체압력에 의해 상기 접촉대응구조에 밀착됨으로써 상기 체결부 및 상기 접촉부를 벽으로 삼아 형성되는 외주부가압챔버를 포함한다.

SEMICONDUCTOR DEVICE

ETCHANT COMPOSITION AND MANUFACTURING METHOD FOR THIN FILM TRANSISTOR USING THE SAME

Semiconductor device and manufacturing method thereof

A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film. Next, in order to further reduce impurities such as moisture or hydrogen in the oxide semiconductor film, oxygen is added to the oxide semiconductor film by an ion implantation method, an ion doping method, or the like, and after that, second heat treatment is performed on the exposed oxide semiconductor film.

PROCESS FOR ANISOTROPIC PLASMA ETCHING OF DIFFERENT SUBSTRATES

The invention concerns a process for producing etched structures in substrates by means of anisotropic plasma etching. An isotropic etching operation and a side wall passivation are carried out in separate and alternating operations. The substrate (2) is a polymer, a metal, or a multi-component system and portions (8) of the side wall passivation layer (6) applied during the side wall passivation are transferred to the exposed lateral surfaces (7') of the side wall (7) during each subsequent etching operations as a result of which the entire process becomes anisotropic.

LIMITED DOSE AND ANGLE DIRECTED BEAM ASSISTED ALE AND ALD PROCESSES FOR LOCALIZED COATINGS ON NON-PLANAR SURFACES

Processes for the localized etching of films on the sidewalls of non-planar 3D features such as a trench or a FinFET array. The etch process has a first step of an angle-directed ion implant beam, with the beam being self-aligned onto a localized region on a sidewall feature, that functionalizes the region for a second step that etches the ion implanted region.

Mask structures for photoetching procedures

A mask structure is described which is extremely useful for use in various photoetching processes where etching rate depends on radiation intensity on the etched surface. Such processes are extremely useful for producing various geometrical patterns on surfaces. The mask is made up of alternate areas of opaque and transparent areas which when introduced into an optical imaging system ordinary aberrations produce a pattern on the surface to be etched with the desired continuous spatial variation of radiation intensity. A particular advantage of the mask structure is that it can easily be made using an Electron Beam Exposure System. The mask is particularly useful for electrochemical photoetching processes carried out on compound semiconductors. The mask structure is usefully used to photoetch integral lenses on light emitting diodes. This photoetching process produces a variety of lens structures on LED devices with great accuracy. Also, a large array of lens structures are produced simultaneously ...

Method for making thin film cadmium telluride and related semiconductors for solar cells

A thin cadmium-telluride semiconductor film for use in solar cells is grown epitaxially on a second semiconductor film, typically tellurium, which may be epitaxial on a substrate semiconductor, typically single-crystal cadmium-telluride. The second semiconductor has a lower resistance to layered cleaving than the desired semiconductor. Application of a strain to the sandwich causes the desired thin CdTe layer to peel off by fracture along the plane of the second semiconductor.

Method for surface treatment of a cadmium zinc telluride crystal

A method for treatment of the surface of a CdZnTe (CZT) crystal that reduces surface roughness (increases surface planarity) and provides an oxide coating to reduce surface leakage currents and thereby, improve resolution. A two step process is disclosed, etching the surface of a CZT crystal with a solution of lactic acid and bromine in ethylene glycol, following the conventional bromine/methanol etch treatment, and after attachment of electrical contacts, oxidizing the CZT crystal surface.

Trockenätzen von Vias in beschichteten integrierten Schaltungen

METHODE ZUM PRÄPARIEREN VON SILIZIUMCARBIDOBERFLÄCHEN FÜR KRISTALLWACHSTUM.

I.R. PHOTODETECTOR INCORPORATING EPITAXIAL C.M.T

A cadmium mercury telluride (C.M.T.) layer (5) is epitaxially grown on a substrate (1, 2) of, for example, cadmium telluride. The substrate (3) is subsequently etched away with a mixture of nitric, hydrofluoric and lactic acids. A thin barrier layer (3) of mercury telluride is provided which is not attacked by the above etching solution. This barrier layer is removed by polishing to leave an optically flat C.M.T. layer which may incorporate a cadmium telluride passivating layer on its surface. ...

Manufacture of etched substrates such as infrared detectors

A narrow and deep aperture (1) is chemically etched in and/or through a body (10) of, for example, cadmium mercury telluride or other infrared-sensitive material. The etchant is constrained and etches faster adjacent to side-walls (4 and 5) of a mask (2) on the body (10); these side-walls (4 and 5) are sufficiently close to each other that the faster etching areas overlap. Typically, apertures or slots (1) having a width (Y2) of about 7 mu m may be etched in this manner through a thickness (Z2) or 5 mu m via windows (3) having width (Y1) of 3 mu m in a photoresist mask (2) of thickness (Z3) of between 4 and 5 mu m.

Semiconductor etching methods

INFRA-RED DETECTORS

ZnSe DIFFRACTION TYPE OPTICAL COMPONENT AND METHOD FOR FABRICATING THE SAME

METHOD OF PREPARING SILICON CARBIDE SURFACES FOR CRYSTAL GROWTH

Method for three dimensional sculpturing of nanowire arrays

METHOD OF PREPARATION Of a LAYER NANOSTRUCTUREE, NANOSTRUCTURE OBTAINED FOLLOWING SUCH a PROCESS.

METHOD FOR LOWERING DARK CONDUCTIVITY OF THIN SEMICONDUCTING FILMS

METHOD FOR STRUCTURING AND TRANSFERRING A MASK IN A SUBSTRATE

Plasma etching of mercury cadmium telluride substrate

L'invention concerne un procédé de gravure d'un substrat de HgCdTe (10) recouvert d'un masque de résist (11) au moyen d'un plasma obtenu à partir d'un gaz de gravure contenant des molécules comportant une ou plusieurs liaisons N-H. Ce procédé peut être utilisé notamment pour former dans le substrat (10) des rainures de séparation (12a, 12b) afin d'améliorer la résolution d'un élément détecteur infrarouge.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

... 전기 특성이 우수하고, 신뢰성이 높은 박막 트랜지스터를 갖는 반도체 장치를 적은 공정으로 제작하는 방법을 제공하는 것을 과제로 한다. In, Ga, 및 Zn을 포함하는 산화물 반도체막 위에 채널 보호층을 형성한 후, n형의 도전형을 갖는 막과, 도전막을 성막하고, 도전막 위에 레지스트 마스크를 형성한다. 이 레지스트 마스크와 함께, 채널 보호층 및 게이트 절연막을 에칭 스토퍼로서 이용하고, 도전막과, n형의 도전형을 갖는 막과, In, Ga, 및 Zn을 포함하는 산화물 반도체막을 에칭하여, 소스 전극층 및 드레인 전극층과, 버퍼층과, 반도체층을 형성한다.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

산화물 소결체, 스퍼터링용 타겟, 및 그것을 이용하여 얻어지는 산화물 반도체 박막

... 본 발명은, 스퍼터링법에 의해 산화물 반도체 박막으로 한 경우에, 저캐리어 농도, 고캐리어 이동도를 얻을 수 있는 산화물 소결체, 및 그것을 이용한 스퍼터링용 타겟을 제공한다. 이 산화물 소결체는, 인듐, 갈륨 및 알루미늄을 산화물로서 함유한다. 갈륨의 함유량이 Ga/(In+Ga) 원자수비로 0.15 이상 0.49 이하이고, 알루미늄의 함유량이 Al/(In+Ga+Al) 원자수비로 0.0001 이상 0.25 미만이다. 이 산화물 소결체를 스퍼터링용 타겟으로서 형성한 결정질의 산화물 반도체 박막은, 캐리어 농도 4.0×1018 cm-3 이하에서, 캐리어 이동도 10 cm2V-1sec-1 이상을 얻을 수 있다.

ETCHING APPARATUS AND ETCHING METHOD

반도체 장치의 제작 방법

... 산화물 반도체를 이용한 반도체 장치에 안정된 전기적 특성을 부여하여, 고신뢰성화하는 것을 목적의 하나로 한다. 제 1 절연막을 형성하고, 제 1 절연막에 산소 도핑 처리를 실시하여 제 1 절연막에 산소 원자를 공급하고, 제 1 절연막상에, 소스 전극 및 드레인 전극, 및 소스 전극 및 드레인 전극과 전기적으로 접속하는 산화물 반도체막을 형성하고, 산화물 반도체막에 열처리를 실시하여 산화물 반도체막중의 수소 원자를 제거하고, 수소 원자가 제거된 산화물 반도체막상에 제 2 절연막을 형성하고, 제 2 절연막상의 산화물 반도체막과 중첩하는 영역에 게이트 전극을 형성하는 반도체 장치의 제작 방법이다.

Semiconductor device and manufacturing method thereof

ZnSe DIFFRACTION TYPE OPTICAL COMPONENT AND METHOD FOR FABRICATING THE SAME

Plasma is generated by an inductive magnetic field generated from a coil and the surface of a ZnSe substrate is etched by that plasma. According to the method, a pattern having an internal angle between the sidewall of the pattern and the surface of the ZnSe substrate of not smaller than 75˚ is obtained. Consequently, a ZnSe diffraction type optical component having enhanced diffraction efficiency and exhibiting excellent performance can be provided.

Infrared imager

An infrared imager, wherein an array of detection devices is formed in a thin layer of HgCdTe, which is bonded to a silicon substrate containing a corresponding array of averaging capacitors with addressing and output connections, and via holes through (or bump bonding pads on) the HgCdTe are used to connect each detection device to its corresponding averaging capacitor. The signal from each detection device is repeatedly averaged into its averaging capacitor, so that the output of each pixel site is sensed as an average over a number of read cycles which provides a greatly improved signal-to-noise ratio.

Method of sequential cleaning and passivating a GaAs substrate using remote oxygen plasma

A processing apparatus and method for depositing a passivating layer on a mercury-cadmium-telluride wafer utilizing a single process chamber to provide oxygen gas to the chamber with the excitation energy being provided by a remotely generated plasma in order to remove any organic residue and then supplying either a sulfide or selenide gas in combination with illuminating the wafer with an in situ generated ultraviolet energy to produce a passivating layer.

SEMICONDUCTOR WAFER AND METHOD FOR MANUFACTURING THEREOF

A semiconductor wafer and method for manufacturing thereof are provided. The semiconductor wafer includes a handling substrate and a silicon layer over the handling substrate and having a {111} facet at an edge of a top surface of the silicon layer. The a defect count on the top surface of the silicon layer is less than about 15 each semiconductor wafer. The method includes the following operations: a semiconductor-on-insulator (SOI) substrate is provided, wherein the SOI substrate has a handling substrate, a silicon layer over the handling substrate, and a silicon germanium layer over the silicon layer; and the silicon germanium layer is etched at a first temperature with hydrochloric acid to expose a first surface of the silicon layer.

SEMICONDUCTOR DEVICE

A transistor includes a multilayer film in which an oxide semiconductor film and an oxide film are stacked, a gate electrode, and a gate insulating film. The multilayer film overlaps with the gate electrode with the gate insulating film interposed therebetween. The multilayer film has a shape having a first angle between a bottom surface of the oxide semiconductor film and a side surface of the oxide semiconductor film and a second angle between a bottom surface of the oxide film and a side surface of the oxide film. The first angle is acute and smaller than the second angle. Further, a semiconductor device including such a transistor is manufactured. 1. A semiconductor device comprising:a glass substrate;a gate electrode with tapered side surfaces over the glass substrate;a first insulating film comprising any one of silicon oxide, silicon nitride, silicon oxynitride, and silicon nitride oxide over the gate electrode;an oxide semiconductor film over and in contact with the first insulating film, the oxide semiconductor film comprising a first oxide film comprising indium and gallium and a second oxide film overlapping with the first oxide film and comprising indium and gallium;a first conductive film over and in contact with a top surface of the second oxide film, the first conductive film being in contact with a side surface of the first oxide film and a side surface of the second oxide film;a second conductive film over and in contact with the top surface of the second oxide film, the second conductive film being in contact with a side surface of the first oxide film and a side surface of the second oxide film;a second insulating film over the oxide semiconductor layer, the first conductive film, and the second conductive film; anda third insulating film over the second insulating film,wherein the second conductive film is electrically connected to a first electrode of a display element via an opening provided in the second insulating film and the third ...

Limited dose and angle directed beam assisted ALE and ALD processes for localized coatings on non-planar surfaces

Processes for the localized etching of films on the sidewalls of non-planar 3D features such as a trench or a FinFET array. The etch process has a first step of an angle-directed ion implant beam, with the beam being self-aligned onto a localized region on a sidewall feature, that functionalizes the region for a second step that etches the ion implanted region.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Provided is a method for manufacturing a semiconductor device with favorable electrical characteristics. The following steps are performed in the following order: forming an oxide semiconductor film over a substrate having a substantially planar surface; selectively etching the oxide semiconductor film to form an oxide semiconductor layer; implanting an oxygen ion on a top surface of the oxide semiconductor layer and a side surface of the oxide semiconductor layer in a cross-section perpendicular to the substantially planar surface in a channel width direction of the oxide semiconductor layer from an angle 0°<θ<90°; forming an insulating layer over the oxide semiconductor layer, and performing heat treatment on the oxide semiconductor layer to diffuse oxygen into the oxide semiconductor layer.

Method for etching films of mercury-cadmium-telluride and zinc sulfid

A film of mercury-cadmium-telluride (HgCdTe) or zinc sulfide (ZnS) is anisotropically etched utilizing a remote plasma and an in situ plasma utilizing a gas mixture which includes a hydrogen containing and/or an alkyl bearing gas providing an anisotropic etch.

THIN FILM TRANSISTOR AND METHOD FOR FABRICATING THE SAME, DISPLAY SUBSTRATE, DISPLAY APPARATUS

The present disclosure provides a thin film transistor, a method for fabricating the same, a display substrate, and a display apparatus, and belongs to the field of display technology. The method includes: forming a metal oxide semiconductor pattern comprising first and second metal oxide semiconductor layers, the second metal oxide semiconductor layer being above the first metal oxide semiconductor layer; depositing a source-drain metal layer on the metal oxide semiconductor pattern; etching the source-drain metal layer and the second metal oxide semiconductor layer to form source and drain electrodes and an active layer of the thin film transistor. The active layer is obtained after removing the second metal oxide semiconductor layer between the source and drain electrodes using a first etchant, and the first etchant has a higher etching rate on the second metal oxide semiconductor layer than on the first metal oxide semiconductor layer.

Thin film transistor substrate

A thin film transistor substrate includes a gate electrode disposed on a substrate; a semiconductor layer disposed on the substrate that partially overlaps the gate electrode and includes an oxide semiconductor material; and a source electrode and a drain electrode disposed on the semiconductor layer, where the drain electrode is spaced apart from the source electrode. The source electrode and the drain electrode each include a barrier layer and a main wiring layer, the a main wiring layer is disposed on the barrier layer, and the barrier layer includes a first metal layer disposed on the semiconductor layer, and a second metal layer disposed on the first metal layer.

Method for making a showerhead

A showerhead is disclosed in this invention. The showerhead includes a bottom portion, at least one plate, and a top portion. The bottom portion includes a plurality of gas tubes which are integratedly formed on the bottom portion. The gas tubes include at least one first gas tube. The at least one plate includes a first plate. The first plate includes a plurality of first openings, wherein the gas tubes pass through the first openings. The top portion is coupled to the bottom portion for forming at least one inner space.

SELECTIVE ETCH FOR II-VI SEMICONDUCTORS

A II-VI semiconductor device is fabricated using a selective etchant in the form of aqueous solution of HX where X is Cl or Br. The II-VI semiconductor device is composed of a number of layers. Selective etching can be enabled by introducing Mg into one of the semiconductor layers. The resultant device may include a semiconductor layer containing Mg.

Verfahren zur Herrstellung einer Halbleitervorrichtung

In einem Verfahren zum Herstellen einer Halbleitervorrichtung wird eine Schottky-Elektrode auf einer oberen Fläche eines Halbleitersubstrates ausgebildet. Ein zweiter Bereich des Halbleitersubstrates wird geätzt, sodass ein erster Bereich höher als ein zweiter Bereich wird, wobei eine ansteigende Fläche zwischen dem ersten Bereich und dem zweiten Bereich ausgebildet wird und eine Außenumfangskante der Schottky-Elektrode an dem ersten Bereich angeordnet ist. Ein Isolierfilm wird auf der oberen Fläche des Halbleitersubstrates ausgebildet, sodass der Isolierfilm sich ringförmig entlang der ansteigenden Fläche erstreckt. Eine Feldplattenelektrode wird ausgebildet. Die Feldplattenelektrode wird mit der Schottky-Elektrode elektrisch verbunden und weist zur oberen Fläche des Halbleitersubstrates über den Isolierfilm innerhalb eines Bereiches, der sich von der Außenumfangskante der Schottky-Elektrode zum zweiten Bereich über die Anstiegsfläche erstreckt.

Verfahren zum Ätzen von Gräben.

Semiconductor etching methods

A method of etching into one or more epitaxial layers of III-V, III-N or II-VI semiconductor material(s) in a semiconductor structure 30 is disclosed. The semiconductor structure is a vertical cavity surface emitting laser (VCSEL, Figure 2), light-emitting diode (LED, Figure 4) or photodiode (Figure 5). The method comprises process steps of establishing a flow of an etch gas mixture through a plasma processing chamber (2, Figure 1) and generating a plasma within the chamber. A radio frequency (RF) bias voltage is simultaneously applied to a support table (14, Figure 1) within the chamber on which the semiconductor structure, carrying a patterned mask 39, is placed. More than 90% of the etch gas mixture consists of a mixture of silicon tetrachloride (SiCl4) and nitrogen (N2). The etch gas mixture may comprise one or more inert gases such as helium, and preferably does not contain more than a trace level of boron trichloride (BCl3). The semiconductor material(s) may be any of GaN, GaAs, AlGaAs ...

INFRA-RED DETECTORS

METHOD OF PREPARING SILICON CARBIDE SURFACES FOR CRYSTAL GROWTH

The invention is a method of forming a substantially planar surface on a monocrystalline silicon carbide crystal by exposing the substantially planar surface to an etching plasma until any surface or subsurface damage caused by any mechanical preparation of the surface is substantially removed. The etch is limited, however, to a time period less than that over which the plasma etch will develop new defects in the surface or aggravate existing ones, and while using a plasma gas and electrode system that do not themselves aggravate or cause substantial defects in the surface.

Plasma treatment device

The problem addressed by the present invention is the provision of a plasma treatment device with which it is possible to easily control the electron energy distribution of plasma in accordance with the type of gas molecules to be dissociated and the dissociation energy thereof. A plasma treatment device (10) according to the present invention comprises: a plasma treatment chamber (11); a plasma production chamber (12) that communicates with the plasma treatment chamber (11); a high-frequency antenna (16) for producing plasma; a plasma control plate (17) for controlling the electron energy of the plasma; and an operation rod (171) and a movement mechanism (172) for adjusting the position of the plasma control plate (17). By means of this plasma treatment device (10), it is possible to control the electron energy distribution of the plasma produced inside the plasma production chamber (12) simply by using the movement mechanism (172) to move the operation rod (171) longitudinally in order ...

Manufacturing method of thin film transistor and manufacturing method of array substrate

Process of application of a layer of tellurium on cadmium a semiconductor telluride body

LIQUID PROCESSING DEVICE

A method for preparing diffractive optical elements for a laser of ZnSe polycrystalline substrate

SEMICONDUCTOR DEVICE

The present invention provides a semiconductor device. The present invention is to provide a method for manufacturing a semiconductor device including a thin film transistor with high reliability and an excellent electric property in few processes. After a channel protection layer is formed on an oxide semiconductor layer containing In, Ga, and Zn, an N-type conductive layer and a conductive layer are formed. A resist mask is formed on the conductive layer. The channel protection layer and a gate insulation layer are used as an etching stopper with the resist mask. The conductive layer, the N-type conductive layer, and the oxide semiconductor layer containing In, Ga, and Zn are etched so that a source electrode layer, a drain electrode layer, a buffer layer, and a semiconductor layer are formed. COPYRIGHT KIPO 2016 ...

Manufacturing method of semiconductor device

Systems and methods for processing substrates

A substrate processing system comprises a first processing module in which a process gas is supplied to a substrate to etch a silicon oxide layer formed on the substrate and a second processing module in which an activated oxygen gas is supplied to the substrate. With the system and a method using the same, the silicon oxide layer can be etched and a condensation layer and/or fumes and/or photoresist residues can be removed in a cost-effective way.

Semiconductor chip-making without scribing

A method for fracturing semiconductor crystal wafers or bars to form individual chips with active devices without the use of mechanical scribing of the crystal. The method involves forming where fracture is desired a shallow trench by etching in the semiconductor wafer or bar, preferably with sharp corners, or providing over where the fracture is desired the edges of a metallization layer, or both. Applying pressure will then cause the crystal to fracture as a result of strains formed in the crystal at the sharp corners or below the metallization edges. The method is particularly suitable for the fabrication of laser chips from compound semiconductors.

METHOD OF VAPOR-PHASE POLISHING A SURFACE OF A SEMICONDUCTOR

Infra-red detector elements

Semiconductor Device and Manufacturing Method Thereof

A semiconductor device includes a substrate, at least one active semiconductor fin, at least one first dummy semiconductor fin, and at least one second dummy semiconductor fin. The active semiconductor fin is disposed on the substrate. The first dummy semiconductor fin is disposed on the substrate. The second dummy semiconductor fin is disposed on the substrate and between the active semiconductor fin and the first dummy semiconductor fin. A top surface of the first dummy semiconductor fin and a top surface of the second dummy semiconductor fin are curved in different directions. 1. A semiconductor device comprising:a substrate;a first active semiconductor fin disposed on the substrate;a first dummy semiconductor fin disposed on the substrate, the first dummy semiconductor fin having a first concave upper surface; anda second dummy semiconductor fin disposed on the substrate, the second dummy semiconductor fin having a second concave upper surface, the first concave upper surface and the second concave upper surface having different curvatures, the second dummy semiconductor fin being disposed between the first active semiconductor fin and the first dummy semiconductor fin, a height of the second dummy semiconductor fin being greater than a height of the first dummy semiconductor fin.2. The semiconductor device of claim 1 , wherein the first dummy semiconductor fin has a first sidewall and a second sidewall opposite the second sidewall claim 1 , the first sidewall of the first dummy semiconductor fin having a first height claim 1 , the second sidewall of the first dummy semiconductor fin having a second height claim 1 , the first height being greater than the second height.3. The semiconductor device of claim 1 , wherein the second dummy semiconductor fin has a first sidewall and a second sidewall opposite the second sidewall claim 1 , the first sidewall of the second dummy semiconductor fin having a first height claim 1 , the second sidewall of the second dummy ...

Thin-film transistor and method for manufacturing the same

According to one embodiment, a thin-film transistor comprises an oxide semiconductor layer formed on a part of a substrate, a first gate insulator film of a silicon dioxide film formed on the oxide semiconductor layer and by the CVD method with a silane-based source gas, a second gate insulator film of a silicon dioxide film formed on the first gate insulator film by the CVD method with a TEOS source gas, and a gate electrode formed on the second gate insulator film.

Thin-film semiconductor device, organic EL display device, and manufacturing methods thereof

A thin-film semiconductor device includes a substrate, a second protection layer, and an oxide semiconductor layer between the substrate and the second protection layer. The second protection layer has provided therein at least one through-hole in which an extraction electrode is embedded, the extraction electrode being electrically connected with the oxide semiconductor layer. The second protection layer has film density of 2.80 g/cm3 to 3.25 g/cm3.

ETCHING OF INDIUM GALLIUM ZINC OXIDE

Indium gallium zinc oxide can be etched by providing a wafer having a layer of indium gallium zinc oxide to a processing chamber, heating the wafer to a first temperature, flowing a first chemical species comprising a fluoride to create a layer of indium gallium zinc oxyfluoride, and removing the layer of indium gallium zinc oxyfluoride by flowing a second chemical species comprising an alkyl aluminum halide, an aluminum alkalide, an organoaluminium compound, a diketone, silicon halide, silane, halogenated silane, or alkyl silicon halide.

半導体装置、モジュール、及び電子機器

INFRARED RAY DETECTING ELEMENT AND METHOD OF MANUFACTURING SAME

Herstellungsverfahren einer Halbleitervorrichtung

Ein Verfahren zum Herstellen einer Halbleitervorrichtung umfasst die folgenden Schritte: Ausbilden eines ersten Isolierfilms über einer ersten Gate-Elektrode, die sich über einem Substrat befindet, während eine Erwärmung bei einer Temperatur von höher als oder gleich 450°C und niedriger als die untere Entspannungsgrenze des Substrats durchgeführt wird, Ausbilden eines ersten Oxidhalbleiterfilms über dem ersten Isolierfilm, Zusetzen von Sauerstoff zu dem ersten Oxidhalbleiterfilm und dann Ausbilden eines zweiten Oxidhalbleiterfilms über dem ersten Oxidhalbleiterfilm, und Durchführen einer ersten Wärmebehandlung, so dass ein Teil von Sauerstoff, der in dem ersten Oxidhalbleiterfilm enthalten ist, auf den zweiten Oxidhalbleiterfilm übertragen wird.

Low damage ion etching of compound semiconductor

A low damage ion etching process for compound semiconductors involves accelerating nitrogen ions towards the semiconductor surface to achieve not only etching but also surface passivation by penetration of some of the nitrogen ions. Preferably, ion generation and acceleration is achieved by an ion source or by electrical and/or magnetic fields in a plasma discharge and the accelerated ion energy is limited to below 1000 eV.

INFRARED DETECTOR MANUFACTURE

IMPROVED METHOD OF FORMING OHMIC CONTACTS

METHOD FOR PREPARING SILICON CARBIDE SURFACES FOR CRYSTAL GROWTH.

PROCESS FOR FABRICATING SEMICONDUCTOR DEVICES

A procedure is described for producing semiconductor devices having damage-free surfaces in electrochemically n-type and intrinsic compound semiconductors. The process involves a photoetching procedure including applying a potential to the compound semiconductor while it is in contact with an electrolytic solution and irradiating the surface to be etched with light in a certain energy range. By suitable adjustment in the potential, electrolytic solution composition and light energy, the etch rate is made proportional to the light intensity. By suitable variation in light intensity and light-ray direction, various geometrical features can be made on the surface of the compound semiconductor. For example, a hole with straight sides can be made in the compound semiconductor by use of a light spot and parallel (collimated) light rays. An advantageous application of this process is the fabrication of a photodiode with a hole in the center for use in bidirectional communication systems and to ...

FABRICATION OF CLEAVED SEMICONDUCTOR LASERS

FABRICATION OF CLEAVED SEMICONDUCTOR LASERS A process is described for making semiconductor lasers with cleaved facets for end mirrors. The process involves electrochemically photoetching slots with deep, narrow cross-sections in a wafer and applying stress to cleave the wafer in the desired place. Extremely short and reproducible semiconductor lasers can be made by this procedure (less than 100, 50 or even 25 .mu.m) which yields extremely useful semiconductor lasers particularly for communication applications. Also, the procedure requires a minimum of skill to produce excellent quality cleaved semiconductor lasers (including short-length lasers) with high yields.

MANUFACTURE OF A GROUP OF INFRA-RED DETECTOR ELEMENTS, AND A GROUP SO MANUFACTURED

... 1 PHB. 32,630. A group of infra-red radiation detector elements are manufactured from a body of infra-red sensitive materials on an insulating substrate using two masking steps which do not require critical alignment even with close spacing between the elements. A first masking layer e.g. of photoresist is formed on the upper surface of at least the body to determine by a lift-off technique a metallization pattern on the body and the substrate. A second masking layer e.g. of photoresist is then provided to determine by ion-bombardment through windows of this layer the desired pattern of elements and their electrodes. The ion-bombardment permits removal of exposed areas of not just the body and metallization pattern but also of a passivating layer on the body surfaces; a closely spaced group of elements and their electrodes can be obtained because the ion-bombardment results in steep sides without significant undercutting.

Etching liquid and etching method for oxide consisting essentially of zinc, tin and oxygen

Metal oxide etchant composition and etching method

ETCHING LIQUID AND ETCHING METHOD FOR OXIDE CONSISTING ESSENTIALLY OF ZINC, TIN AND OXYGEN

반도체 장치의 제작 방법

... 산화물 반도체를 이용한 반도체 장치에 안정된 전기적 특성을 부여하여, 고신뢰성화하는 것을 목적의 하나로 한다. 제 1 절연막을 형성하고, 제 1 절연막에 산소 도핑 처리를 실시하여 제 1 절연막에 산소 원자를 공급하고, 제 1 절연막상에, 소스 전극 및 드레인 전극, 및 소스 전극 및 드레인 전극과 전기적으로 접속하는 산화물 반도체막을 형성하고, 산화물 반도체막에 열처리를 실시하여 산화물 반도체막중의 수소 원자를 제거하고, 수소 원자가 제거된 산화물 반도체막상에 제 2 절연막을 형성하고, 제 2 절연막상의 산화물 반도체막과 중첩하는 영역에 게이트 전극을 형성하는 반도체 장치의 제작 방법이다.

Semiconductor device

A transistor includes a multilayer film in which an oxide semiconductor film and an oxide film are stacked, a gate electrode, and a gate insulating film. The multilayer film overlaps with the gate electrode with the gate insulating film interposed therebetween. The multilayer film has a shape having a first angle between a bottom surface of the oxide semiconductor film and a side surface of the oxide semiconductor film and a second angle between a bottom surface of the oxide film and a side surface of the oxide film. The first angle is acute and smaller than the second angle. Further, a semiconductor device including such a transistor is manufactured.

Metal oxide etching solution and an etching method

The object of the present invention is to provide an etching solution composition for etching a metal oxide containing In and a metal oxide containing Zn and In used as a transparent electrode or an oxide semiconductor of an electronic device such as a semiconductor element or a flat panel display (FPD), the etching solution composition being controllable to give a practical etching rate, having high dissolving power toward Zn, and enabling a long solution life due to suppressed variation of the formulation during use. The object is solved by an etching solution composition that enables microfabrication to be carried out for a metal oxide containing In and a metal oxide containing Zn and In used as a transparent electrode or an oxide semiconductor of an electronic device such as a semiconductor element or an FPD, the composition containing water and at least one type of acid, excluding hydrohalic acids, perhalic acids, etc., having an acid dissociation constant pKan at 25 DEG C. in any ...

Oxide sintered compact, sputtering target, and oxide semiconductor thin film obtained using same

Provided are an oxide sintered compact whereby low carrier density and high carrier mobility are obtained when the oxide sintered compact is used to obtain an oxide semiconductor thin film by a sputtering method, and a sputtering target which uses the oxide sintered compact. This oxide sintered compact contains oxides of indium, gallium, and aluminum. The gallium content is from 0.15 to 0.49 by Ga/(In + Ga) atomic ratio, and the aluminum content is from 0.0001 to less than 0.25 by Al/(In + Ga + Al) atomic ratio. A crystalline oxide semiconductor thin film formed using this oxide sintered compact as a sputtering target is obtained at a carrier density of 4.0 x 1018 cm-3 or less and a carrier mobility of 10 cm2V-1sec-1 or greater.

Process to etch semiconductor materials

The present disclosure describes a method which can selectively etch silicon from silicon/silicon-germanium stacks or silicon-germanium from silicon-germanium/germanium stacks to form germanium-rich channel nanowires. For example, a method can include a multilayer stack formed with alternating layers of a silicon-rich material and a germanium-rich material. A first thin chalcogenide layer is concurrently formed on the silicon-rich material, and a second thick chalcogenide layer is formed on the germanium-rich material. The first chalcogenide layer and the second chalcogenide layer are etched until the first chalcogenide layer is removed from the silicon-rich material. The silicon-rich material and the second chalcogenide layer are etched with different etch rates.

Manufacturing method of semiconductor device

Surface cleaning method of II-VI Group compound semiconductor crystal

A surface cleaning method of II-VI Group compound semiconductor crystal, which is characterized in using an etching agent prepared by saturating an aqueous solution consisting of sulfuric acid and water at a volume ratio of 1~10 to 1 with potassium dichromate, and etching a II-VI Group compound semiconductor crystal in a temperature range of 10~80 DEG C.

Low vapor pressure aerosol-assisted CVD

Systems and methods for processing films on the surface of a substrate are described. The systems possess aerosol generators which form droplets from a condensed matter (liquid or solid) of one or more precursors. A carrier gas is flowed through the condensed matter and push the droplets toward a substrate placed in a substrate processing region. An inline pump connected with the aerosol generator can also be used to push the droplets towards the substrate. A direct current (DC) electric field is applied between two conducting plates configured to pass the droplets in-between. The size of the droplets is desirably reduced by application of the DC electric field. After passing through the DC electric field, the droplets pass into the substrate processing region and chemically react with the substrate to deposit or etch films.

Thin-film transistor and process for manufacture of the thin-film transistor

A thin-film transistor includes an oxidic semiconductor channel, a metallic or oxidic gate, drain and source contacts and at least one barrier layer positioned between the oxidic semiconductor channel and the drain and source contacts to inhibit an exchange of oxygen between the oxidic semiconductor channel and the drain and source contacts. 1. A thin-film transistor , comprising:an oxidic semiconductor channel;metallic or oxidic gate, drain and source contacts; andat least one barrier layer positioned between the oxidic semiconductor channel and the drain and source contacts to inhibit an exchange of oxygen between the oxidic semiconductor channel and the drain and source contacts.2. The thin-film transistor in accordance with claim 1 , wherein the at least one barrier layer is formed from a subtractively structured conductive layer in direct contact with the oxidic semiconductor channel.3. The thin-film transistor in accordance with claim 2 , wherein the drain and source contacts are formed from a material of which the subtractively structured conductive layer is formed.4. The thin-film transistor in accordance with claim 2 , wherein the subtractively structured conductive layer comprises of an oxidic claim 2 , doped semiconductor claim 2 , an oxidic undoped semiconductor or an oxidic claim 2 , doped and undoped semiconductor.5. The thin-film transistor in accordance with claim 4 , wherein the subtractively structured conductive layer at least partially comprises a zinc oxide compound.6. The thin-film transistor in accordance with claim 5 , wherein the zinc oxide compound is an aluminium zinc oxide compound.7. The thin-film transistor in accordance with claim 1 , wherein the at least one barrier layer is formed of an electrical insulator comprising silicon oxide or silicon nitride.8. The thin-film transistor in accordance with claim 1 , wherein the oxidic semiconductor channel comprises a zinc oxide compound.9. The thin-film transistor in accordance with claim 8 , ...

Methods of atomic layer etching (ALE) using sequential, self-limiting thermal reactions

The invention includes a method of promoting atomic layer etching (ALE) of a surface. In certain embodiments, the method comprises sequential reactions with a metal precursor and a halogen-containing gas. The invention provides a solid substrate obtained according to any of the methods of the invention. The invention further provides a porous substrate obtained according to any of the methods of the invention. The invention further provides a patterned solid substrate obtained according to any of the methods of the invention.

Porous silicon carbide (SiC) semiconductor device

A semiconductor device employs at least one layer of semiconducting porous silicon carbide (SiC). The porous SiC layer has a monocrystalline structure wherein the pore sizes, shapes, and spacing are determined by the processing conditions. In one embodiment, the semiconductor device is a p-n junction diode in which a layer of n-type SiC is positioned on a p-type layer of SiC, with the p-type layer positioned on a layer of silicon dioxide. Because of the UV luminescent properties of the semiconducting porous SiC layer, it may also be utilized for other devices such as LEDs and optoelectronic devices.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate, at least one active semiconductor fin, at least one first dummy semiconductor fin, and at least one second dummy semiconductor fin. The active semiconductor fin is disposed on the substrate. The first dummy semiconductor fin is disposed on the substrate. The second dummy semiconductor fin is disposed on the substrate and between the active semiconductor fin and the first dummy semiconductor fin. A top surface of the first dummy semiconductor fin and a top surface of the second dummy semiconductor fin are curved in different directions.

THIN-FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME

According to one embodiment, a thin-film transistor comprises an oxide semiconductor layer formed on a part of a substrate, a first gate insulator film of a silicon dioxide film formed on the oxide semiconductor layer and by the CVD method with a silane-based source gas, a second gate insulator film of a silicon dioxide film formed on the first gate insulator film by the CVD method with a TEOS source gas, and a gate electrode formed on the second gate insulator film.

Tin oxide films in semiconductor device manufacturing

Tin oxide films are used as spacers and hardmasks in semiconductor device manufacturing. In one method, tin oxide layer is formed conformally over sidewalls and horizontal surfaces of protruding features on a substrate. A passivation layer is then formed over tin oxide on the sidewalls, and tin oxide is then removed from the horizontal surfaces of the protruding features without being removed at the sidewalls of the protruding features. The material of the protruding features is then removed while leaving the tin oxide that resided at the sidewalls of the protruding features, thereby forming tin oxide spacers. Hydrogen-based and chlorine-based dry etch chemistries are used to selectively etch tin oxide in a presence of a variety of materials. In another method a patterned tin oxide hardmask layer is formed on a substrate by forming a patterned layer over an unpatterned tin oxide and transferring the pattern to the tin oxide.

Substrate treatment method

A substrate treatment method includes a substrate holding unit which horizontally holds a substrate; a rotating unit which rotates the substrate held by the substrate holding unit about a vertical axis; and a first nozzle having an opposing face to be opposed to a lower surface of the substrate inward of a peripheral portion of the substrate in spaced relation to the lower surface of the substrate during rotation of the substrate by the rotating unit and a treatment liquid spout provided in the opposing face for filling a space defined between the lower surface of the substrate and the opposing face with a treatment liquid spouted from the treatment liquid spout to keep the space in a liquid filled state; wherein the treatment liquid spreads outwardly over the lower surface of the substrate and further, flows around to a peripheral portion of an upper surface of the substrate.

Semiconductor device, method for manufacturing the same, and electronic device

A semiconductor device with reduced parasitic capacitance is provided. A stack is formed on an insulating layer, the stack comprising a first oxide insulating layer, an oxide semiconductor layer over the first oxide insulating layer, and a second oxide insulating layer on the oxide semiconductor layer, a gate electrode layer and a gate insulating layer are formed on the second oxide insulating layer; a first low-resistance region is formed by adding a first ion to the second oxide semiconductor layer using the gate electrode layer as a mask; a sidewall insulating layer is formed on an outer side of the gate electrode layer; a second conductive layer is formed over the gate electrode layer, the sidewall insulating layer, and the second insulating layer; and an alloyed region in the second oxide semiconductor layer is formed by performing heat treatment.

Method for fabricating transistor having hard-mask layer

A method for fabricating a transistor including the following steps is provided. First, a gate electrode is formed on a substrate, and a gate insulating layer is formed on the substrate in sequence, wherein the gate insulating layer covers the substrate and the gate electrode. Next, a patterned channel layer and a hard-mask layer are formed on the gate insulating layer, wherein the patterned channel layer and the hard-mask layer are located above the gate electrode, and the hard-mask layer is disposed on the patterned channel layer. Afterwards, a source and a drain are formed on the gate insulating layer by a wet etchant. The part of the hard-mask layer that is not covered by the source and the drain is removed by the wet etchant until the patterned channel layer is exposed, so as to form a plurality of patterned hard-mask layers.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.

Method for manufacturing semiconductor device and semiconductor device

A minute transistor and the method of manufacturing the minute transistor. A source electrode layer and a drain electrode layer are each formed in a corresponding opening formed in an insulating layer covering a semiconductor layer. The opening of the source electrode layer and the opening of the drain electrode layer are formed separately in two distinct steps. The source electrode layer and the drain electrode layer are formed by depositing a conductive layer over the insulating layer and in the openings, and subsequently removing the part located over the insulating layer by polishing. This manufacturing method allows for the source electrode later and the drain electrode layer to be formed close to each other and close to a channel forming region of the semiconductor layer. Such a structure leads to a transistor having high electrical characteristics and a high manufacturing yield even in the case of a minute structure.

SYSTEMS AND METHODS FOR PROCESSING SUBSTRATES

A substrate processing system comprises a first processing module in which a process gas is supplied to a substrate to etch a silicon oxide layer formed on the substrate and a second processing module in which an activated oxygen gas is supplied to the substrate. With the system and a method using the same, the silicon oxide layer can be etched and a condensation layer and/or fumes and/or photoresist residues can be removed in a cost-effective way. 1. A substrate processing system comprising:a first processing module configured to provide a process gas containing hydrogen fluoride (HF) to a substrate on which a silicon oxide layer is formed, thereby etching the silicon oxide layer formed on the substrate; anda second processing module configured to provide activated oxygen gas to the substrate.2. The system of claim 1 , further comprising:a cassette module configured to receive the substrate;a first transfer module connected to the cassette module and configured to transfer the substrate to or from the cassette module;a second transfer module connected to the first processing module and the second processing module and configured to transfer the substrate to/from the first processing module, the second processing module, or both; anda loadlock module connected to the first and second transfer modules and configured to transfer the substrate from/to the first transfer module to/from the second transfer module.3. The system of claim 1 , wherein the process gas further contains ammonia (NH) gas and an inert gas.4. The system of claim 3 , wherein the inert gas comprises at least one selected from the group consisting of N claim 3 , Ar claim 3 , and He.5. The system of claim 1 , wherein the process gas further contains isopropyl alcohol (IPA).6. The system of claim 1 , wherein the first processing module comprises:a chamber connected to the second transfer module;a susceptor provided in the chamber, being able to move upwardly or downwardly, and configured to allow the ...

Method for manufacturing semiconductor device

In a semiconductor device including a transistor in which an oxide semiconductor layer, a gate insulating layer, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor layer and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive layer and an interlayer insulating layer are stacked to cover the oxide semiconductor layer, the sidewall insulating layers, and the gate electrode layer. Then, parts of the interlayer insulating layer and the conductive layer over the gate electrode layer are removed by a chemical mechanical polishing method, so that a source electrode layer and a drain electrode layer are formed. Before formation of the gate insulating layer, cleaning treatment is performed on the oxide semiconductor layer.

SUBSTRATE PROCESSING METHOD

There is provided a substrate processing method to suppress popping while increasing the throughput in a photoresist removing process. The substrate processing method comprises: loading a substrate, which is coated with photoresist into which a dopant is introduced, into a process chamber; heating the substrate; supplying a reaction gas to the process chamber, wherein the reaction gas contains at least oxygen and hydrogen components, and concentration of the hydrogen component ranges from 60% to 70%; and processing the substrate in a state where the reaction gas is excited into plasma. In the heating of the substrate, the substrate may be heated to 220° C. to 300° C. In the heating of the substrate, the substrate may be heated to 250° C. to 300° C. 1(a) loading into a process chamber a substrate having a photoresist film thereon with a dopant introduced therein;(b) heating the substrate to a first temperature;(c) supplying a first reaction gas containing oxygen and hydrogen components and a dilution gas into the process chamber in a manner that a flow rate of the hydrogen component ranges from 60% to 70% of a total flow rate of the first reaction gas;(d) processing the substrate with the first reaction gas in plasma state to remove at least a portion of the photoresist film;(e) heating the substrate to a second temperature higher than the first temperature;(f) supplying a second reaction gas containing oxygen and hydrogen components and a dilution gas into the process chamber in a manner that a flow rate of the hydrogen component of the second reaction gas is higher than that of the hydrogen component of the first reaction gas; and(g) processing the substrate with the second reaction gas in plasma state to remove a remaining portion of the photoresist film.. A substrate processing method comprising: The present application is continuation application of U.S. patent application Ser. No. 12/632,265, filed on Dec. 7, 2009; which relates to and claims priority under 35 ...

ADAPATIVE ENDPOINT METHOD FOR PAD LIFE EFFECT ON CHEMICAL MECHANICAL POLISHING

The present disclosure provides a chemical mechanical polishing (CMP) system. The CMP system includes a pad designed for wafer polishing, a motor driver coupled with the pad and designed to drive the pad during the wafer polishing, and a controller coupled with the motor driver and designed to control the motor driver. The CMP system further includes an in-situ rate monitor designed to collect polishing data from a wafer on the pad, determine CMP endpoint based on a life stage of the pad, and provide the CMP endpoint to the controller. 1. A chemical mechanical polishing (CMP) system , comprising:a pad designed for wafer polishing;a motor driver coupled with the pad and designed to drive the pad during the wafer polishing;a controller coupled with the motor driver and designed to control the motor driver; andan in-situ rate monitor designed to collect polishing data from a wafer on the pad, determine CMP endpoint based on a life stage of the pad, and provide the CMP endpoint to the controller.2. The CMP system of claim 1 , wherein the in-situ rate monitor includes:a signal module designed to extract a polishing signal from the wafer;a mechanism for applying a ladder coefficient to amplify the polishing signal according to the life stage of the pad;a window module for defining and applying multiple endpoint windows with respective window widths; andan endpoint module for determining the CMP endpoint by applying one of the multiple endpoint windows to the polishing signal according to the life stage of the pad.3. The CMP system of claim 1 , further comprising another pad for wafer polishing and coupled with the in-situ rate monitor.4. A chemical mechanical polishing (CMP) system claim 1 , comprising:a polishing pad configured to polish a wafer;a motor driver coupled with the polishing pad and configured to drive the polishing pad during wafer polishing;an in-situ rate monitor configured to define a time region of pad life for the polishing pad and configured to assign ...

STRIPPER SOLUTIONS EFFECTIVE FOR BACK-END-OF-LINE OPERATIONS

Back end of line (BEOL) stripping solutions which can be used in a stripping process that replaces etching resist ashing process are provided. The stripping solutions are useful for fabricating circuits and/or forming electrodes on semiconductor devices for semiconductor integrated circuits with good efficiency and with low and acceptable metal etch rates. Methods for their use are similarly provided. The preferred stripping agents contain a polar aprotic solvent, water, an amine and a quaternary hydroxide that is not tetramethylammonium hydroxide. Further provided are integrated circuit devices and electronic interconnect structures prepared according to these methods. 2. The stripper solution of claim 1 , wherein the stripper solution additionally contains glycerine and the polar aprotic solvent is selected from the group consisting of dimethyl sulfoxide and 1-formylpiperidine.3. The stripper solution of claim 1 , wherein the aprotic solvent comprises from about 40% to about 90% of the composition; water comprises from about 2% to about 15% of the composition; the quaternary hydroxide comprises from about 1% to about 10% of the composition; and the amine comprises from about 2% to about 60% of the composition.4. The stripper solution of claim 3 , wherein the aprotic solvent is dimethyl sulfoxide.5. The stripper solution of claim 1 , wherein Z is P.6. The stripper solution of claim 3 , wherein said amine is an alkanolamine having at least two carbon atoms claim 3 , at least one amino substituent and at least one hydroxyl substituent claim 3 , the amino and hydroxyl substituents attached to different carbon atoms.7. The stripper solution of claim 3 , wherein the quaternary hydroxide comprises tetrabutyl phosphonium hydroxide claim 3 , tetraphenyl phosphonium hydroxide claim 3 , methyl triphenyl phosphonium hydroxide claim 3 , ethyl triphenyl phosphonium hydroxide claim 3 , propyl triphenyl phosphonium hydroxide claim 3 , butyl triphenyl phosphonium hydroxide claim 3 ...

LIQUID TREATMENT APPARATUS

A liquid treatment apparatus includes a substrate holder () that holds a substrate horizontally and rotates the substrate, a treatment liquid nozzle () that supplies a treatment liquid to the substrate held by the substrate holder, a cup () that is arranged outside of a peripheral edge of the substrate held by the substrate holder and receives the treatment liquid which has been supplied to the substrate by the treatment liquid nozzle, a top plate () that covers the substrate held by the substrate holder from above, a top plate rotation driving mechanism that rotates the top plate, and a liquid receiving member () that surrounds a peripheral edge of the top plate and has a circular liquid receiving space (). 1. A liquid treatment apparatus comprising:a substrate holder that holds a substrate horizontally and rotates the substrate;a treatment liquid nozzle that supplies a treatment liquid to the substrate held by the substrate holder;a liquid receiving cup that is arranged outside a peripheral edge of the substrate held by the substrate holder and receives the treatment liquid which has been supplied to the substrate by the treatment liquid nozzle;a top plate that covers, from above, the substrate held by the substrate holder;a top plate rotation driving mechanism that rotates the top plate; anda liquid receiving member that surrounds a peripheral edge of the top plate and has a circular liquid receiving space.2. The liquid treatment apparatus according to claim 1 , further comprising at least one discharge pipe connected to the liquid receiving space to discharge a fluid within the liquid receiving space.3. The liquid treatment apparatus according to claim 2 , wherein a suctioning mechanism is connected to the discharge pipe.4. The liquid treatment apparatus according to claim 3 , further comprising a flow rectifying plate arranged above the top plate claim 3 , wherein the suctioning mechanism suctions a space located between the top plate and the flow rectifying ...

Plasma processing device

A plasma processing device according to the present invention includes a plasma processing chamber, a plasma producing chamber communicating with the plasma processing chamber, a radio-frequency antenna for producing plasma, a plasma control plate for controlling the energy of electrons in the plasma, as well as an operation rod and a moving mechanism for regulating the position of the plasma control plate. In this plasma processing device, the energy distribution of the electrons of the plasma produced in the plasma producing chamber can be controlled by regulating the distance between the radio-frequency antenna 16 and the plasma control plate by simply moving the operation rod in its longitudinal direction by the moving mechanism. Therefore, a plasma process suitable for the kind of gas molecules to be dissociated and/or their dissociation energy can be easily performed.

APPARATUS AND A METHOD FOR TREATING A SUBSTRATE

A substrate treating method may include jetting a fluid containing an abrasive onto a substrate, and polishing the substrate using the jetted fluid. 19.-. (canceled)10. A substrate treating apparatus comprising:a supporting unit configured to support a substrate;a nozzle unit configured to jet a fluid containing an abrasive onto the substrate; anda supplying unit configured to supply the fluid to the nozzle unit.11. The apparatus of claim 10 , wherein the supplying unit comprises a first storage configured to store a solvent claim 10 , a second storage configured to store the abrasive claim 10 , a first supplying conduit configured to connect the first storage to the nozzle unit claim 10 , and a second supplying conduit configured to connect the second storage to the first supplying conduit.12. The apparatus of claim 11 , wherein the second storage stores a chemical claim 11 , wherein the chemical softens a layer provided on the substrate.13. The apparatus of claim 11 , wherein the second storage stores an additive claim 11 , wherein the additive protects a surface of the substrate or a layer provided on the substrate.14. The apparatus of claim 11 , wherein the supplying unit further comprises valves provided on the first and second supplying conduits and a controller claim 11 , wherein the controller controls the valves to adjust a content of the abrasive in the fluid.15. The apparatus of claim 10 , wherein the nozzle unit includes an end portion through which the fluid is jetted claim 10 , and wherein the end portion of the nozzle unit is located at the same or substantially the same level as a top surface of the substrate and faces a side surface of the supporting unit.16. A substrate treating apparatus comprising:a first module configured to jet a fluid containing an abrasive through a nozzle to a substrate; andan second module configured to transfer the substrate to the first module, wherein the nozzle is positioned over a top surface of the substrate or is ...

SUBSTRATE PROCESSING APPARATUS

A substrate processing apparatus generates an electric field in a processing space between a lower electrode to which a high frequency power is supplied and an upper electrode facing the lower electrode and performs plasma processing on a substrate mounted on the lower electrode by using a plasma generated by the electric field. Distribution of a plasma density in the processing space is controlled by a magnetic field generated by controlling a plurality of electromagnets provided at a top surface of the upper electrode which is provided to be opposite to the processing space. 1. A substrate processing apparatus configured to generate an electric field in a processing space between a lower electrode , to which a high frequency power is supplied , and an upper electrode facing the lower electrode and perform plasma processing on a substrate mounted on the lower electrode by using a plasma generated by the electric field , whereindistribution of a plasma density in the processing space is controlled by a magnetic field generated by controlling a plurality of electromagnets provided at a top surface of the upper electrode which is provided to be opposite to the processing space.2. The substrate processing apparatus of claim 1 , wherein when the distribution of the plasma density is controlled claim 1 , an intensity of the magnetic field in a region claim 1 , where the plasma density is low claim 1 , is controlled to become great.3. The substrate processing apparatus of claim 1 , wherein a frequency of the high frequency power supplied to the lower electrode is about 60 MHz or above.4. The substrate processing apparatus of claim 1 , wherein when the distribution of the plasma density is controlled claim 1 , an intensity of the magnetic field in a region facing a center of the substrate in the processing space is controlled to become small and an intensity of the magnetic field in a region facing a periphery of the substrate is controlled to become great.5. The substrate ...

CONSUMABLE PART FOR USE IN A PLASMA PROCESSING APPARATUS

A method of reusing a consumable part for use in a plasma processing apparatus includes cleaning a surface of the consumable part made of SiC that has been eroded by a first plasma process performed for a specific period of time. The method further includes depositing SiC on the cleaned surface of the eroded consumable part by CVD. The method also includes remanufacturing a consumable part having a predetermined shape by machining the eroded consumable part on which the SiC is deposited for performing a second plasma process on a substrate by using the remanufactured consumable part. 1. A consumable part for reuse in a plasma processing apparatus , the consumable part comprising:a base portion including a part of a first silicon carbide (SiC) formed by depositing SiC by a first chemical vapor deposition (CVD) process, the base portion having been eroded by a first plasma process performed in the plasma processing apparatus; anda remanufactured portion including a part of a second SiC formed by depositing SiC by a second CVD process on a surface of the base portion.2. The consumable part of claim 1 , wherein the first SiC is formed by depositing SiC around a core by the first CVD process claim 1 , the core being formed of graphite or sintered SiC claim 1 , andwherein the base portion is manufactured by machining the first SiC and removing the core such that the base portion includes the part of the first SiC but does not include the core.3. The consumable part of claim 1 , wherein there is no stepped portion at a boundary between the base portion and the remanufactured portion.4. The consumable part of claim 1 , wherein an erosion rate of the base portion is identical to an erosion rate of the remanufactured portion.5. A plasma processing apparatus comprising:a chamber configured to accommodate therein a substrate;a susceptor configured to mount the substrate;a processing gas introducing unit configured to introduce a processing gas into the chamber;a plasma ...

PLASMA CHAMBER TOP PIECE ASSEMBLY

A plasma processing system for processing a substrate is described. The plasma processing system includes a bottom piece including a chuck configured for holding the substrate. The plasma processing system also includes an induction coil configured to generate an electromagnetic field in order to create a plasma for processing the substrate; and an optimized top piece coupled to the bottom piece, the top piece further configured for a heating and cooling system. Wherein, the heating and cooling system is substantially shielded from the electromagnetic field by the optimized top piece, and the optimized top piece can substantially be handled by a single person. 113-. (canceled)14. A top piece for a plasma processing chamber , comprising:a first shelf;a second shelf; anda wall,wherein the wall being disposed between the first shelf and the second shelf, anda cavity being formed between the first shelf and the second shelf and between the wall.15. The top piece of claim 14 , wherein the first shelf is disposed above the second shelf and the first shelf is connected to the wall at a junction.16. The top piece of claim 15 , wherein the cavity comprises a configuration to accommodate a heating and cooling system for a plasma processing chamber.17. The top piece of claim 15 , wherein the cavity comprises a configuration to accommodate a heating and cooling system disposed at the junction.18. The top piece of claim 15 , further comprising RF shielding to shield RF from a heating and cooling system disposed within the cavity.19. The top piece of claim 18 , wherein RF shielding of the heating and cooling system minimizes a distortion of a resulting electric field.20. The top piece of claim 14 , wherein the top piece comprises an inner surface area configured to be exposed to plasma claim 14 , wherein the inner surface area is substantially the same as that of a non-optimized top piece.21. The top piece of claim 14 , wherein the internal shape of the top piece substantially ...

ETCHANT COMPOSITION AND MANUFACTURING METHOD FOR THIN FILM TRANSISTOR USING THE SAME

An etchant composition includes ammonium persulfate (((NH))SO), an azole-based compound, a water-soluble amine compound, a sulfonic acid-containing compound, a nitrate-containing compound, a phosphate-containing compound, a chloride-containing compound, and residual water. 1. An etchant composition comprising:{'sub': 4', '2', '2', '8, 'ammonium persulfate (((NH))SO), an azole-based compound, a water-soluble amine compound, a sulfonic acid-containing compound, a nitrate-containing compound, a phosphate-containing compound, a chloride-containing compound, and residual water.'}2. The etchant composition of claim 1 , further comprising:an assistance oxidizer.3. The etchant composition of claim 2 , whereina content of the assistance oxidizer is about 0.1 wt % to about 2 wt %.4. The etchant composition of claim 3 , wherein{'sub': 3', '4', '3', '3', '4', '2', '2, 'the assistance oxidizer includes one selected from a group consisting of phosphoric acid (HPO), nitric acid (HNO), acetic acid (CHCOOH), perchloric acid (HClO), and hydrogen peroxide (HO).'}5. The etchant composition of claim 1 , whereinthe ammonium persulfate content is about 0.1 wt % to about 20 wt %, the azole-based compound content is about 0.01 wt % to about 2 wt %, the water-soluble amine compound content is about 0.1 wt % to about 5 wt %, the sulfonic acid-containing compound content is about 0.1 wt % to about 10 wt %, and the nitrate-containing compound content is about 0.1 wt % to about 10 wt %.6. The etchant composition of claim 5 , whereinthe phosphate-containing compound content is about 0.1 wt % to about 5 wt %.7. The etchant composition of claim 6 , whereinthe chloride-containing compound content is about 0.001 wt % to about 1 wt %.8. The etchant composition of claim 1 , whereinthe azole-based compound includes one selected from the group consisting of benzotriazole, aminotetrazole, imidazole, and pyrazole.9. The etchant composition of claim 1 , whereinthe water-soluble amine compound includes one ...

ETCHING APPARATUS AND ETCHING METHOD

An etching apparatus includes: a chamber configured to accommodate a substrate to be processed having an etching target film; a gas exhaust mechanism configured to exhaust an inside of the chamber; an etching gas supply mechanism configured to supply an etching gas into the chamber; and a gas cluster generation mechanism configured to generate a gas cluster in the chamber by spraying a cluster gas into the chamber, wherein a gas produced by a reaction when the etching target film is etched with the etching gas is discharged from the chamber by the gas cluster generated by the gas cluster generation mechanism. 1. An etching apparatus , comprising:a chamber configured to accommodate a substrate to be processed having an etching target film;a gas exhaust mechanism configured to exhaust an inside of the chamber;an etching gas supply mechanism configured to supply an etching gas into the chamber; anda gas cluster generation mechanism configured to generate a gas cluster in the chamber by spraying a cluster gas into the chamber,wherein a gas produced by a reaction when the etching target film is etched with the etching gas is discharged from the chamber by the gas cluster generated by the gas cluster generation mechanism.2. The etching apparatus of claim 1 , wherein the etching gas supply mechanism and the gas cluster generation mechanism include a common shower head through which the etching gas is injected into the chamber and the cluster gas is sprayed into the chamber.3. The etching apparatus of claim 1 , wherein the etching target film is a SiN film claim 1 , the etching gas is HF gas claim 1 , and the gas produced by the reaction is NHgas.4. The etching apparatus of claim 1 , wherein the substrate has a laminated film on its surface claim 1 , a layer of the laminated film is the etching target film claim 1 , and the gas produced by the reaction contributes to an etching of a different layer of the laminated film.5. The etching apparatus of claim 4 , wherein the ...

Method for manufacturing semiconductor device

A semiconductor device including an oxide semiconductor with stable electric characteristics and high reliability is provided. An island-shaped oxide semiconductor layer is formed by using a resist mask, the resist mask is removed, oxygen is introduced (added) to the oxide semiconductor layer, and heat treatment is performed. The removal of the resist mask, introduction of the oxygen, and heat treatment are performed successively without exposure to the air. Through the oxygen introduction and heat treatment, impurities such as hydrogen, moisture, a hydroxyl group, or hydride are intentionally removed from the oxide semiconductor layer, whereby the oxide semiconductor layer is highly purified. Chlorine may be introduced to an insulating layer over which the oxide semiconductor layer is formed before formation of the oxide semiconductor layer. By introducing chlorine, hydrogen in the insulating layer can be fixed, thereby preventing diffusion of hydrogen from the insulating layer into the oxide semiconductor layer.

ACTIVE MATRIX SUBSTRATE AND METHOD FOR PRODUCING ACTIVE MATRIX SUBSTRATE

An active matrix substrate includes a thin film transistor having a gate electrode, an oxide semiconductor layer disposed on the gate electrode via a gate insulating layer, and a source electrode and a drain electrode disposed on the oxide semiconductor layer. A plurality of gate bus lines and the gate electrode are made of a first electrically conductive film. At least part of each of the plurality of source bus lines, the source electrode, and the drain electrode have a multilayer structure including a lower layer that is made of a second electrically conductive film and an upper layer that is made of a first transparent electrically conductive film. Between the plurality of source bus lines and the gate insulating layer, a plurality of first oxide strips extending along the first direction are disposed, the first oxide strips being made of the same oxide semiconductor film as the oxide semiconductor layer. Each of the plurality of source bus lines is located on an upper face of the corresponding first oxide strip, and a width of each of the plurality of source bus lines along a second direction is smaller than a width of one corresponding first oxide strip along the second direction. 1. An active matrix substrate having a displaying region that includes a plurality of pixel regions and a non-displaying region excluding the displaying region , the active matrix substrate comprising:a substrate;a plurality of source bus lines extending along the first direction and a plurality of gate bus lines extending along a second direction which intersects the first direction, the source bus lines and the gate bus lines being supported on the substrate; anda thin film transistor disposed in each of the plurality of pixel regions, wherein,each thin film transistor includes a gate electrode, an oxide semiconductor layer disposed on the gate electrode via a gate insulating layer, and a source electrode and a drain electrode being disposed on the oxide semiconductor layer and ...

Field effect transistors with a gated oxide semiconductor source/drain spacer

FETs including a gated oxide semiconductor spacer interfacing with a channel semiconductor. Transistors may incorporate a non-oxide channel semiconductor, and one or more oxide semiconductors disposed proximal to the transistor gate electrode and the source/drain semiconductor, or source/drain contact metal. In advantageous embodiments, the oxide semiconductor is to be gated by a voltage applied to the gate electrode (i.e., gate voltage) so as to switch the oxide semiconductor between insulating and semiconducting states in conjunction with gating the transistor's non-oxide channel semiconductor between on and off states.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a high on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device having a high degree of integration is provided. A semiconductor device including an oxide semiconductor; a second insulator; a second conductor; a third conductor; a fourth conductor; a fifth conductor; a first conductor and a first insulator embedded in an opening portion formed in the second insulator, the second conductor, the third conductor, the fourth conductor, and the fifth conductor; a region where a side surface and a bottom surface of the second conductor are in contact with the fourth conductor; and a region where a side surface and a bottom surface of the third conductor are in contact with the fifth conductor. 1. A semiconductor device comprising:an oxide semiconductor;a first conductor;a second conductor;a third conductor;a fourth conductor;a fifth conductor;a first insulator;a second insulator; anda third insulator,wherein the second insulator is provided with an opening portion penetrating through the second insulator,wherein a region of a bottom surface of the opening portion is in contact with the oxide semiconductor,wherein a region of the first insulator is in contact with a side surface and the bottom surface of the opening portion,wherein a region of the first conductor faces the side surface and the bottom surface of the opening portion with the first insulator positioned therebetween,wherein the second conductor, the third conductor, the fourth conductor, and the fifth conductor are positioned between the oxide semiconductor and the second insulator,wherein a region of a side surface of the second conductor and a bottom surface of the second conductor is in contact with the fourth conductor,wherein a region of a side surface of the third conductor and ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME

According to one embodiment, a semiconductor device includes contact holes passing through a source region of a drain region of an interlayer insulating film and oxide semiconductor layer to reach an insulating substrate, wherein a source electrode and a drain electrode are formed inside the contact holes, respectively. 18-. (canceled).9. A semiconductor device comprising:a support substrate;a metal layer formed on the support substrate;an undercoat layer made of an insulating material and formed to cover the metal layer;a semiconductor layer formed on the undercoat layer, the semiconductor layer including a channel region, and a source region and a drain region disposed at sides of the channel region;a gate insulating film formed on the channel region;a gate electrode formed on the gate insulating film;an interlayer insulating film covering the gate electrode, the semiconductor layer, and the gate insulating film;a source electrode electrically connected with the source region; anda drain electrode electrically connected with the chain region;wherein at least one of the source electrode and the drain electrode contacts the semiconductor layer and passes through the contact hole provided in the interlayer insulating film and the undercoat layer to electrically connect with the metal layer, and the metal layer is opposed to the gate electrode via the undercoat layer, the semiconductor layer, and the gate insulating film.10. The semiconductor device of claim 9 , wherein the metal layer electrically connected with the source electrode and the metal layer electrically connected with the drain electrode are separated.11. The semiconductor device of claim 9 , wherein at least one of the source electrode and the drain electrode contacts a side face of the semiconductor layer to electrically connect with the metal layer.12. The semiconductor device of claim 9 , wherein at least one of the source electrode and the drain electrode passes through the semiconductor layer to ...

ELECTRON BEAM-INDUCED ETCHING

Beam-induced etching uses a work piece maintained at a temperature near the boiling point of a precursor material, but the temperature is sufficiently high to desorb reaction byproducts. In one embodiment, NFis used as a precursor gas for electron-beam induced etching of silicon at a temperature below room temperature.

Semiconductor device, method for manufacturing the same, and electronic device

A semiconductor device with reduced parasitic capacitance is provided. A stack is formed on an insulating layer, the stack comprising a first oxide insulating layer, an oxide semiconductor layer over the first oxide insulating layer, and a second oxide insulating layer on the oxide semiconductor layer; a gate electrode layer and a gate insulating layer are formed on the second oxide insulating layer; a first low-resistance region is formed by adding a first ion to the second oxide semiconductor layer using the gate electrode layer as a mask; a sidewall insulating layer is formed on an outer side of the gate electrode layer; a second conductive layer is formed over the gate electrode layer, the sidewall insulating layer, and the second insulating layer; and an alloyed region in the second oxide semiconductor layer is formed by performing heat treatment.

Design and synthesis of metal oxide surfaces and interfaces with crystallographic control using solid-liquid-vapor etching and vapor-liquid-solid growth

The present invention provides integrated nanostructures comprising a single-crystalline matrix of a material A containing aligned, single-crystalline nanowires of a material B, with well-defined crystallographic interfaces are disclosed. The nanocomposite is fabricated by utilizing metal nanodroplets in two subsequent catalytic steps: solid-liquid-vapor etching, followed by vapor-liquid-solid growth. The first etching step produces pores, or “negative nanowires” within a single-crystalline matrix, which share a unique crystallographic direction, and are therefore aligned with respect to one another. Further, since they are contained within a single, crystalline, matrix, their size and spacing can be controlled by their interacting strain fields, and the array is easily manipulated as a single entity—addressing a great challenge to the integration of freestanding nanowires into functional materials. In the second, growth, step, the same metal nanoparticles are used to fill the pores with single-crystalline nanowires, which similarly to the negative nanowires have unique growth directions, and well-defined sizes and spacings. The two parts of this composite behave synergistically, since this nanowire-filled matrix contains a dense array of well-defined crystallographic interfaces, in which both the matrix and nanowire materials convey functionality to the material. The material of either one of these components may be chosen from a vast library of any material able to form a eutectic alloy with the metal in question, including but not limited to every material thus far grown in nanowire form using the ubiquitous vapor-liquid-solid approach. This has profound implications for the fabrication of any material intended to contain a functional interface, since high interfacial areas and high quality interfacial structure should be expected. Technologies to which this simple approach could be applied include but are not limited to p-n junctions of solar cells, battery ...

DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME

A display device and a method for fabricating the same are provided. The display device comprises pixels connected to scan lines, and to data lines crossing the scan lines, each of the pixels including a light emitting element, and a first transistor configured to control a driving current supplied to the light emitting element according to a data voltage applied from the data line, the first transistor including a first active layer having an oxide semiconductor, and a first oxide layer on the first active layer and having a crystalline oxide containing tin (Sn). 1. A display device comprising pixels connected to scan lines , and to data lines crossing the scan lines , each of the pixels comprising a light emitting element , and a first transistor configured to control a driving current supplied to the light emitting element according to a data voltage applied from the data line , the first transistor comprising a first active layer having an oxide semiconductor , and a first oxide layer on the first active layer and having a crystalline oxide containing tin (Sn).2. The display device of claim 1 , wherein the first oxide layer has a content of the tin in a range of about 1 at. % to about 100 at. % with respect to a content of cations contained in the crystalline oxide.3. The display device of claim 2 , wherein the first oxide layer comprises tin-zinc oxide (TZO) claim 2 , tin-gallium oxide (TGO) claim 2 , indium-tin-zinc oxide (ITZO) claim 2 , indium-tin-gallium oxide (ITGO) claim 2 , or indium-tin-zinc-gallium oxide (ITZGO).4. The display device of claim 3 , wherein the first active layer comprises indium-tin oxide (ITO) claim 3 , indium-tin-gallium oxide (ITGO) claim 3 , indium-gallium-zinc oxide (IGZO) claim 3 , or indium-gallium-zinc-tin oxide (IGZTO).5. The display device of claim 1 , wherein the first transistor comprises a first gate insulating layer on the first active layer claim 1 , and a first gate electrode on the first gate insulating layer and ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Provided is a semiconductor device in which a deterioration in electrical characteristics which becomes more noticeable as miniaturization can be suppressed. The semiconductor device includes a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a source electrode and a drain electrode in contact with each side surface of the first oxide semiconductor film and the second oxide semiconductor film; a first insulating film and a second insulating film over the source electrode and the drain electrode; a third oxide semiconductor film over the second oxide semiconductor film, the source electrode, and the drain electrode; a gate insulating film over the third oxide semiconductor film; and a gate electrode in contact with an upper surface of the gate insulating film and facing an upper surface and the side surface of the second oxide semiconductor film. 1. A semiconductor device comprising:a first insulating film;a first oxide semiconductor film over the first insulating film;a second oxide semiconductor film over the first oxide semiconductor film;a first conductive film and a second conductive film over the first insulating film;a third oxide semiconductor film over the second oxide semiconductor film;a second insulating film over the third oxide semiconductor film; anda third conductive film over the second insulating film,wherein each of the first conductive film and the second conductive film is in contact with a first side surface of the second oxide semiconductor film, andwherein, in a channel width direction, the third conductive film faces a second side surface of the second oxide semiconductor film.2. The semiconductor device according to claim 1 , wherein claim 1 , in the channel width direction claim 1 , the third oxide semiconductor film is in contact with the second side surface of the second oxide semiconductor film.3. The semiconductor device according to claim 1 , wherein ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film. Next, in order to further reduce impurities such as moisture or hydrogen in the oxide semiconductor film, oxygen is added to the oxide semiconductor film by an ion implantation method, an ion doping method, or the like, and after that, second heat treatment is performed on the exposed oxide semiconductor film. 1. (canceled)2. A semiconductor device comprising:a gate electrode;a first insulating film over the gate electrode;an oxide semiconductor layer formed by sputtering over the first insulating film;a source electrode and a drain electrode over the oxide semiconductor layer;a second insulating film over the oxide semiconductor layer, the source electrode, and the drain electrode; anda third insulating film over the second insulating film,wherein a proportion of nitrogen of the third insulating film is higher than a proportion of nitrogen of the second insulating film,wherein a portion of the oxide semiconductor layer located between the source electrode and the drain electrode is thinner than portions of the oxide semiconductor layer below the source electrode and the drain electrode,wherein a superficial portion of at least the portion of the oxide semiconductor layer located between the source electrode and the drain electrode includes a crystal region,wherein a c-axis of the crystal region is aligned in a direction which is substantially perpendicular to a top surface of the oxide semiconductor layer, andwherein the oxide semiconductor layer includes indium, gallium, and zinc.3. The semiconductor device according to claim 2 , wherein the oxide semiconductor layer contains hydrogen at a concentration less than or equal ...

MANUFACTURING METHOD OF OXIDE SEMICONDUCTOR DEVICE

A manufacturing method of an oxide semiconductor device includes the following steps. A first oxide semiconductor layer is formed on a substrate. A gate insulation layer is formed on the first oxide semiconductor layer. A first flattening process is performed on a top surface of the first oxide semiconductor layer before the step of forming the gate insulation layer. A roughness of the top surface of the first oxide semiconductor layer after the first flattening process is smaller than the roughness of the top surface of the first oxide semiconductor layer before the first flattening process. 1. A manufacturing method of an oxide semiconductor device , comprising:forming a first oxide semiconductor layer on a substrate;forming a gate insulation layer on the first oxide semiconductor layer; andperforming a first flattening process on a top surface of the first oxide semiconductor layer before the step of forming the gate insulation layer, wherein a roughness of the top surface of the first oxide semiconductor layer after the first flattening process is smaller than the roughness of the top surface of the first oxide semiconductor layer before the first flattening process, wherein the first flattening process comprises a plasma treatment, a gaseous mixture used in the plasma treatment comprises xenon and hydrogen, and the hydrogen concentration in the gaseous mixture is lower than the xenon concentration in the gaseous mixture.24-. (canceled)5. The manufacturing method of the oxide semiconductor device according to claim 1 , wherein a process temperature of the first flattening process is lower than or equal to 400° C.6. The manufacturing method of the oxide semiconductor device according to claim 1 , further comprising:forming a second oxide semiconductor layer on the substrate before the step of forming the first oxide semiconductor layer, wherein at least a part of the first oxide semiconductor layer is formed on the second oxide semiconductor layer; andperforming ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

An object is to provide a thin film transistor using an oxide semiconductor layer, in which contact resistance between the oxide semiconductor layer and source and drain electrode layers is reduced and electric characteristics are stabilized. Another object is to provide a method for manufacturing the thin film transistor. A thin film transistor using an oxide semiconductor layer is formed in such a manner that buffer layers having higher conductivity than the oxide semiconductor layer are formed over the oxide semiconductor layer, source and drain electrode layers are formed over the buffer layers, and the oxide semiconductor layer is electrically connected to the source and drain electrode layers with the buffer layers interposed therebetween. In addition, the buffer layers are subjected to reverse sputtering treatment and heat treatment in a nitrogen atmosphere, whereby the buffer layers having higher conductivity than the oxide semiconductor layer are obtained. 1. A method for manufacturing a semiconductor device , comprising the steps of:forming a gate electrode layer over a substrate;forming a gate insulating layer over the gate electrode layer;forming a first oxide semiconductor film over the gate insulating layer, using a sputtering method;subjecting the first oxide semiconductor film to heat treatment;forming a second oxide semiconductor film over the first oxide semiconductor film using a sputtering method;subjecting the second oxide semiconductor film to reverse sputtering treatment;subjecting the second oxide semiconductor film to heat treatment in a nitrogen atmosphere;etching the first oxide semiconductor film and the second oxide semiconductor film to form an oxide semiconductor layer and a first buffer layer;forming a conductive film over the oxide semiconductor layer and the first buffer layer;etching the conductive film and the first buffer layer to form source and drain electrode layers, a second buffer layer, and a third buffer layer; ...

THIN FILM TRANSISTOR SUBSTRATE, METHOD OF MANUFACTURING THE SAME, AND DISPLAY APPARATUS HAVING THE SAME

A thin film transistor substrate includes a thin film transistor including a gate electrode, a semiconductor layer, a source electrode and a drain electrode. Each of the source electrode and the drain electrode includes a wire layer and a protective layer. The protective layer includes zinc oxide in an amount greater than about 70% by weight and less than about 85% by weight and indium oxide in an amount greater than about 15% by weight and less than about 30% by weight. 1. A thin film transistor substrate comprising:a base substrate; and a gate electrode on the base substrate;', 'a semiconductor layer on the gate electrode;', 'a source electrode overlapping the semiconductor layer; and', 'a drain electrode overlapping the semiconductor layer and spaced apart from the source electrode,', a wire layer comprising a metal; and', 'a protective layer on the wire layer,', 'wherein the protective layer comprises zinc oxide in an amount greater than about 70% by weight and less than about 85% by weight and indium oxide in an amount greater than about 15% by weight and less than about 30% by weight., 'each of the source electrode and the drain electrode comprising], 'a thin film transistor on the base substrate, the thin film transistor comprising2. The thin film transistor substrate of claim 1 , wherein the semiconductor layer comprises an oxide semiconductor.3. The thin film transistor substrate of claim 2 , wherein the metal comprises copper or a copper alloy.4. The thin film transistor substrate of claim 1 , wherein each of the source electrode and the drain electrode further comprises a barrier layer between the semiconductor layer and the wire layer claim 1 , the barrier layer blocking diffusion of a material included in the wire layer to the semiconductor layer.5. The thin film transistor substrate of claim 4 , wherein the barrier layer comprises at least one of indium-zinc-oxide claim 4 , gallium-zinc oxide and aluminum-zinc oxide.6. A display apparatus comprising:a ...

THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF

A method of manufacturing a thin film transistor, comprising: forming a gate electrode () on a first surface of a substrate (); forming on the first surface of the substrate a gate dielectric layer () covering the gate electrode; forming a metal oxide semiconductor layer () on the gate dielectric layer; processing the metal oxide semiconductor layer to form a channel region () exposed thereon; anode-oxidizing the channel region, such that the channel region has a first carrier concentration; and conducting photolithography and etching the metal oxide semiconductor layer to form an active region, the active region comprising the channel region, and a source region () and a drain region () located at the two sides of the channel region and having a second carrier concentration, the first carrier concentration being lower than the second carrier concentration. The source region, the drain region and the channel region of a thin film transistor manufactured using the above method are located on the same film layer, and the channel region has a carrier concentration lower than the carrier concentration of the source region and the drain region. 1. A method of manufacturing a thin film transistor , comprising:providing a substrate, the substrate comprising a first surface and a second surface opposite to each other;forming a gate electrode on the first surface of the substrate;forming on the first surface of the substrate a gate dielectric layer covering the gate electrode;forming a metal oxide semiconductor layer on the gate dielectric layer;processing the metal oxide semiconductor layer to form a channel region exposed on the metal oxide semiconductor layer;anode-oxidizing the channel region, such that the channel region has a first carrier concentration;conducting photolithography and etching the metal oxide semiconductor layer to form an active region, the active region comprising the channel region, and a source region and a drain region located at the two sides of ...

Method for manufacturing semiconductor device

To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed. 1. (canceled)2. A method for manufacturing a semiconductor device comprising:forming a gate electrode layer over a substrate;forming a gate insulating layer over the gate electrode layer;forming an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer including indium, gallium and zinc;forming an insulating layer over a channel formation region of the oxide semiconductor layer;forming a conductive layer over the oxide semiconductor layer with an oxide including titanium interposed therebetween;forming a resist mask over the conductive layer;etching the conductive layer, the oxide and the oxide semiconductor layer using the resist mask so as to recess the conductive layer from the oxide; andheating the oxide semiconductor layer.3. The method for manufacturing a semiconductor device according to claim 2 , further comprising the step of:performing a plasma treatment to the oxide semiconductor layer,wherein the substrate is kept in a non-bias state in the step of performing the plasma treatment.4. The method for manufacturing a semiconductor device according to claim 2 , wherein the gate insulating layer contains excessive oxygen.5. The method for manufacturing a semiconductor device according to claim 2 , ...

THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF FABRICATING THE SAME

A thin film transistor substrate includes a gate electrode disposed on a substrate; a semiconductor layer disposed on the substrate that partially overlaps the gate electrode and includes an oxide semiconductor material; and a source electrode and a drain electrode disposed on the semiconductor layer, where the drain electrode is spaced apart from the source electrode. The source electrode and the drain electrode each include a barrier layer and a main wiring layer, the a main wiring layer is disposed on the barrier layer, and the barrier layer includes a first metal layer disposed on the semiconductor layer, and a second metal layer disposed on the first metal layer. 1. A method of fabricating a thin film transistor substrate , comprising:forming a gate electrode on a substrate;forming a semiconductor layer that partially overlaps the gate electrode, wherein the semiconductor layer includes an oxide semiconductor material;forming a conductive layer that includes a barrier layer and a main wiring layer on the semiconductor layer;forming a conductive pattern that partially overlaps the gate electrode by etching the semiconductor layer and the conductive layer in a first etching process;etching the main wiring layer in a second etching process wherein a region of the barrier layer that overlaps the gate electrode is exposed; andetching the exposed region of the barrier layer in a third etching process wherein a region of the semiconductor layer that overlaps the gate electrode is exposed,wherein the barrier layer includes a first metal layer disposed on the semiconductor layer and a second metal layer disposed on the first metal layer.2. The method of claim 1 , wherein the third etching process is a dry etching process.3. The method of claim 1 , wherein the first etching process and the second etching process are wet etching processes.4. The method of claim 1 , wherein the first metal layer includes at least one of molybdenum (Mo) claim 1 , a molybdenum alloy (Mo ...

ETCHING SOLUTION AND ETCHING SOLUTION KIT, ETCHING METHOD USING SAME, AND PRODUCTION METHOD FOR SEMICONDUCTOR SUBSTRATE PRODUCT

There is provided an etching solution of a semiconductor substrate that includes a first layer containing germanium (Ge) and a second layer containing a specific metal element other than germanium (Ge), the etching solution selectively removing the second layer and including following specific acid compound 1. An etching solution of a semiconductor substrate that includes a first layer containing germanium (Ge) and a second layer containing a specific metal element other than germanium (Ge) , the etching solution selectively removing the second layer and comprising following specific acid compound.{'sub': 2', '4', '3', '3', '4', '3', '3, 'Specific acid compound: sulfuric acid (HSO), nitric acid (HNO), phosphoric acid (HPO), phosphonic acid (HPO), or organic acid'}2. The etching solution according to claim 1 , wherein the concentration of germanium (Ge) of the first layer is 40% by mass or greater.3. The etching solution according to claim 1 , wherein a metal element constituting the second layer is selected from nickel platinum (NiPt) claim 1 , titanium (Ti) claim 1 , nickel (Ni) claim 1 , and cobalt (Co).4. The etching solution according to claim 1 , wherein the organic acid is organic acid which contains a sulfonic acid group claim 1 , a carboxy group claim 1 , a phosphoric acid group claim 1 , a phosphonic acid group claim 1 , or a hydroxamic acid group.5. The etching solution according to claim 1 , wherein the content of those in a small amount series among the acid compounds is in the range of 0.01% by mass to less than 50% by mass and the content of those in a large amount series among the acid compounds is in the range of 25% by mass to 99% by mass.6. The etching solution according to claim 1 , wherein the second layer is selectively removed with respect to the first layer and/or the following third layer.Third layer: layer containing germanium (Ge) and the specific metal element, which is interposed between the first layer and the second layer7. The etching ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region. 1. (canceled)2. A semiconductor device comprising:a gate electrode over a substrate;a first gate insulating film over the gate electrode, the first gate insulating film comprising silicon nitride;a second gate insulating film over the first gate insulating film, the second gate insulating film comprising silicon oxide; andan oxide semiconductor film including a microcrystal over the second gate insulating film,wherein the oxide semiconductor film comprises indium and zinc,wherein the oxide semiconductor film includes a first region and a second region,wherein the first region has higher crystallinity than the second region, andwherein the second region is located over the first region.3. The semiconductor device according to claim 2 , wherein the oxide semiconductor film further comprises gallium.4. The semiconductor device according to claim 2 , wherein the first gate insulating film and the second gate insulating film each have a thickness of 50 nm to 100 nm.5. The semiconductor device according to claim 2 , wherein the oxide semiconductor film has a thickness of 200 nm or less.6. The semiconductor device according to claim 2 , wherein an amorphous state and a crystalline state exist in the oxide semiconductor film.7. The semiconductor device according to claim 2 , wherein the oxide semiconductor film does not include ...

MANUFACTURE METHOD OF TFT SUBSTRATE AND STURCTURE THEREOF

The present invention provides a manufacture method of an oxide semiconductor TFT substrate, and the method comprises steps of: forming a gate () on a substrate (); deposing a gate isolation layer (); forming an island shaped oxide semiconductor layer (); forming an island shaped photoresistor layer () and an island shaped etching stopper layer (), and the island shaped etching stopper layer () covers a central part () of the island shaped oxide semiconductor layer () and exposes two side parts () of the island shaped oxide semiconductor layer (); implementing ion implantation process to the two side parts () of the island shaped oxide semiconductor layer (); lifting off the island shaped photoresistor layer (); forming a source/a drain (), and the source/the drain () contact the two side parts () of the island shaped oxide semiconductor layer () to establish electrical connections; deposing and patterning a protecting layer (); deposing and patterning a pixel electrode layer (); , implementing anneal process. 1. A manufacture method of an oxide semiconductor TFT substrate , comprising steps of:{'b': '1', 'step , providing a substrate, and deposing and patterning a first metal layer on the substrate to form a gate;'}{'b': '2', 'step , deposing a gate isolation layer on the gate and the substrate;'}{'b': '3', 'step , deposing and patterning an oxide semiconductor layer on the gate isolation layer to form an island shaped oxide semiconductor layer directly over the gate;'}{'b': '4', 'step , sequentially deposing an etching stopper layer, a photoresistor layer on the island shaped oxide semiconductor layer and the gate isolation layer, and then implementing photolithography process to the photoresistor layer to form an island shaped photoresistor layer directly over the island shaped oxide semiconductor layer, and etching the etching stopper layer to form an island shaped etching stopper layer on the island shaped oxide semiconductor layer;'}a width of the island ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region. 1. (canceled)2. A method for manufacturing a semiconductor device , comprising:forming a first conductive film that serves as a first gate electrode;forming a first insulating film over the first conductive film;forming an oxide semiconductor film over the first insulating film;forming a source electrode and a drain electrode by patterning a second conductive film formed over the oxide semiconductor film, whereby a top surface of a first region of the oxide semiconductor film that is located between the source electrode and the drain electrode is etched to have a smaller thickness than a second region of the oxide semiconductor film that is below the source electrode or the drain electrode;forming a second insulating film over the oxide semiconductor film, the source electrode, and the drain electrode; andforming a transparent film over the second insulating film by a sputtering method,wherein the transparent film comprises metal oxide.3. The method according to claim 2 ,wherein the oxide semiconductor film includes indium, zinc, and a metal different from indium and zinc.4. The method according to claim 2 ,wherein the transparent film is a conductive film.5. The method according to claim 2 , further comprising:performing a heat treatment on the oxide semiconductor film.6. The method according to claim 2 ,wherein the ...

SEMICONDUCTOR DEVICE

A transistor includes a multilayer film in which an oxide semiconductor film and an oxide film are stacked, a gate electrode, and a gate insulating film. The multilayer film overlaps with the gate electrode with the gate insulating film interposed therebetween. The multilayer film has a shape having a first angle between a bottom surface of the oxide semiconductor film and a side surface of the oxide semiconductor film and a second angle between a bottom surface of the oxide film and a side surface of the oxide film. The first angle is acute and smaller than the second angle. Further, a semiconductor device including such a transistor is manufactured. 1. A semiconductor device comprising:an insulating surface;a first oxide film over and in contact with the insulating surface, the first oxide film comprising indium;a second oxide film over and in contact with the first oxide film, the second oxide film comprising indium; anda conductive film over and in contact with a top surface of the second oxide film,wherein a length of a side surface of the first oxide film is larger than a length of a side surface of the second oxide film in a cross-sectional view.2. The semiconductor device according to claim 1 , further comprising a gate electrode under the first oxide film.3. The semiconductor device according to claim 1 , further comprising a gate electrode over the second oxide film.4. A semiconductor device comprising:an insulating surface;a first oxide film over and in contact with the insulating surface, the first oxide film comprising indium, gallium and zinc;a second oxide film over and in contact with the first oxide film, the second oxide film comprising indium, gallium and zinc; anda conductive film over and in contact with a top surface of the second oxide film,wherein a length of a side surface of the first oxide film is larger than a length of a side surface of the second oxide film in a cross-sectional view.5. The semiconductor device according to claim 4 , ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

A semiconductor device includes an oxide semiconductor layer, a gate electrode facing the oxide semiconductor layer, a gate insulating layer between the oxide semiconductor layer and the gate electrode, a first barrier layer below the oxide semiconductor layer, and a second barrier layer above the oxide semiconductor layer, the second barrier layer covering a top surface and side surfaces of the oxide semiconductor layer and being in contact with the first barrier layer in a region around the oxide semiconductor layer. 1. A semiconductor device , comprising:an oxide semiconductor layer;a gate electrode facing the oxide semiconductor layer;a gate insulating layer between the oxide semiconductor layer and the gate electrode;a first barrier layer below the oxide semiconductor layer; anda second barrier layer above the oxide semiconductor layer, the second barrier layer covering a top surface and side surfaces of the oxide semiconductor layer and being in contact with the first barrier layer in a region around the oxide semiconductor layer.2. The semiconductor device according to claim 1 , wherein the first barrier layer and the second barrier layer contain nitrogen.3. The semiconductor device according to claim 2 , further comprising:a first oxide layer between the oxide semiconductor layer and the first barrier layer; anda second oxide layer between the oxide semiconductor layer and the second barrier layer.4. The semiconductor device according to claim 3 , wherein:the gate electrode is below the oxide semiconductor layer; andthe gate insulating layer includes the first barrier layer and the first oxide layer.5. The semiconductor device according to claim 4 , wherein:the first oxide layer has substantially the same pattern as that of the oxide semiconductor layer as seen in a plan view; anda region of the first barrier layer exposed from the first oxide layer is thinner than a region of the first barrier layer below the first oxide layer.6. The semiconductor device ...

Semiconductor device and method for manufacturing semiconductor device

A semiconductor device in which the threshold is adjusted is provided. In a transistor including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and an electron trap layer between the gate electrode and the semiconductor, the electron trap layer includes crystallized hafnium oxide. The crystallized hafnium oxide is deposited by a sputtering method using hafnium oxide as a target. When the substrate temperature is Tsub (° C.) and the proportion of oxygen in an atmosphere is P (%) in the sputtering method, P≧45−0.15×Tsub is satisfied. The crystallized hafnium oxide has excellent electron trapping properties. By the trap of an appropriate number of electrons, the threshold of the semiconductor device can be adjusted.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a high on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device having a high degree of integration is provided. A semiconductor device including an oxide semiconductor; a second insulator; a second conductor; a third conductor; a fourth conductor; a fifth conductor; a first conductor and a first insulator embedded in an opening portion formed in the second insulator, the second conductor, the third conductor, the fourth conductor, and the fifth conductor; a region where a side surface and a bottom surface of the second conductor are in contact with the fourth conductor; and a region where a side surface and a bottom surface of the third conductor are in contact with the fifth conductor. 1. A semiconductor device comprising:an oxide semiconductor;a first conductor;a second conductor;a third conductor;a fourth conductor;a fifth conductor;a first insulator;a second insulator; anda third insulator,wherein the second insulator is provided with an opening portion penetrating through the second insulator,whereina region of a bottom surface of the opening portion is in contact with the oxide semiconductor,whereina region of the first insulator is in contact with a side surface and the bottom surface of the opening portion,whereina region of the first conductor faces the side surface and the bottom surface of the opening portion with the first insulator positioned therebetween,whereinthe second conductor, the third conductor, the fourth conductor, and the fifth conductor are positioned between the oxide semiconductor and the second insulator,whereina region of a side surface of the second conductor and a bottom surface of the second conductor is in contact with the fourth conductor,whereina region of a side surface of the third conductor and a ...

Remote Plasma System and Method

A system and method for generating and using plasma is provided. An embodiment comprises a plasma generating unit that comprises beta-phase aluminum oxide. A precursor material is introduced to the plasma generating unit and a plasma is induced from the precursor material. The plasma may be used to deposit or etch materials on a semiconductor substrate. 1. A remote plasma system comprising:an inlet port;an inner housing coupled to the inlet port to generate a plasma, the inner housing comprising beta-phase aluminum oxide; andan outlet port coupled to the inner housing.2. The remote plasma system of claim 1 , further comprising a deposition chamber coupled to the outlet port.3. The remote plasma system of claim 2 , wherein the deposition chamber further comprises a showerhead coupled to the outlet port.4. The remote plasma system of claim 3 , wherein the showerhead is a dual showerhead claim 3 , and wherein the dual showerhead is also coupled to a non-plasma precursor delivery system.5. The remote plasma system of claim 1 , further comprising an etching chamber coupled to the outlet port.6. The remote plasma system of claim 1 , further comprising a magnetic coil around a portion of the inner housing.7. The remote plasma system of claim 1 , wherein the inner housing comprises beta-double aluminum oxide.8. A remote plasma system comprising:a semiconductor processing chamber;a showerhead within the semiconductor processing chamber, the showerhead comprising a plasma inlet to receive a plasma precursor; anda plasma generator coupled to the plasma inlet, the plasma generator comprising a plasma inducing device and an inner housing, the inner housing comprising sodium, aluminum, and oxygen atoms.9. The remote plasma system of claim 8 , wherein the semiconductor processing chamber is a deposition chamber.10. The remote plasma system of claim 8 , wherein the semiconductor processing chamber is an etching chamber.11. The remote plasma system of claim 8 , wherein the plasma ...

CARRIER HEAD FOR CHEMICAL MECHANICAL POLISHING APPARATUS COMPRISING SUBSTRATE RECEIVING MEMBER

A carrier head for a chemical mechanical polishing apparatus comprises: a base; a substrate receiving member comprising a plate portion having an outer surface for receiving a substrate and an inner surface at the back of the outer surface, a perimeter portion extended in a height direction from an edge of the plate portion, a securing portion extended from an outer part of the perimeter portion and connected to a lower part of the base, and a contact portion extended from an inner part of the perimeter portion; a contact coupling structure connected to the lower part of the base to provide a contact surface to the contact portion; and a perimeter portion pressurizing chamber formed by taking the securing portion and the contact portion as chamber walls when the contact portion contacts firmly the contact coupling structure by means of fluid pressure. 1. A carrier head for a chemical mechanical polishing apparatus comprising a substrate receiving member , comprising:a base;a substrate receiving member comprising a plate portion having an outer surface for receiving a substrate and an inner surface at the back of the outer surface, a perimeter portion extended in a height direction from an edge of the plate portion, a securing portion extended from an outer part of the perimeter portion and connected to a lower part of the base, and a contact portion extended from an inner part of the perimeter portion;a contact coupling structure connected to the lower part of the base to provide a contact surface to the contact portion; anda perimeter portion pressurizing chamber formed by taking the securing portion and the contact portion as chamber walls when the contact portion contacts firmly the contact coupling structure by means of fluid pressure,wherein fluid in the perimeter portion pressurizing chamber is prevented from flowing to an inner side surface of the perimeter portion when fluid pressure in the perimeter portion pressurizing chamber is higher than fluid pressure ...

APPARATUS AND METHODS OF ELECTRICALLY CONDUCTIVE OPTICAL SEMICONDUCTOR COATING

A method of coating an optical substrate with a transparent, electrically conductive coating includes depositing a semiconductor coating over a surface of an optical substrate. The semiconductor coating has broadband optical transmittance. Channels are formed in the semiconductor coating. The method includes coating over the semiconductor coating and filling the channels with a doped semiconductor. The doped semiconductor is removed from the semiconductor coating, leaving the doped semiconductor in the channels. 1. A method of coating an optical substrate , comprising:depositing a semiconductor coating over a surface of an optical substrate, wherein the semiconductor coating has broadband optical transmittance;forming channels in the semiconductor coating;coating over the semiconductor coating and at least partially filling the channels with an electrically conductive doped semiconductor;removing at least some of the doped semiconductor from the semiconductor coating, leaving at least some of the doped semiconductor in the channels.2. A method as recited in claim 1 , wherein forming channels includes:applying a photoresist over the semiconductor coating;selectively exposing the photoresist and developing the photoresist in a pattern;etching the semiconductor coating in the pattern; andremoving the photoresist to leave the channels in the pattern on the semiconductor coating.3. A method as recited in claim 2 , wherein the pattern includes a grid.4. A method as recited in claim 1 , further comprising applying a protective coating over the semiconductor coating and doped semiconductor in the channels.5. A method as recited in claim 4 , further comprising depositing a broadband anti-reflection coating over the protective coating.6. A method as recited in claim 1 , further comprising depositing a broadband anti-reflection coating over the semiconductor coating and doped semiconductor in the channels.7. A method as recited in claim 1 , wherein forming the channels ...

Semiconductor device structure with gate spacer having protruding bottom portion and method for forming the same

A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on the sidewall of the gate stack structure, and the gate spacers include a top portion and a bottom portion adjoined to the top portion, and the bottom portion slopes to a top surface of the substrate. The semiconductor device structure further includes an epitaxial structure formed adjacent to the gate spacers, and the epitaxial structure is formed below the gate spacers.

Thin film transistor substrate and method of fabricating the same

A thin film transistor substrate includes a gate electrode disposed on a substrate; a semiconductor layer disposed on the substrate that partially overlaps the gate electrode and includes an oxide semiconductor material; and a source electrode and a drain electrode disposed on the semiconductor layer, where the drain electrode is spaced apart from the source electrode. The source electrode and the drain electrode each include a barrier layer and a main wiring layer, the a main wiring layer is disposed on the barrier layer, and the barrier layer includes a first metal layer disposed on the semiconductor layer, and a second metal layer disposed on the first metal layer.

METAL OXIDE ETCHING SOLUTION AND AN ETCHING METHOD

The object of the present invention is to provide an etching solution composition for etching a metal oxide containing In and a metal oxide containing Zn and In used as a transparent electrode or an oxide semiconductor of an electronic device such as a semiconductor element or a flat panel display (FPD), the etching solution composition being controllable to give a practical etching rate, having high dissolving power toward Zn, and enabling a long solution life due to suppressed variation of the formulation during use. The object is solved by an etching solution composition that enables microfabrication to be carried out for a metal oxide containing In and a metal oxide containing Zn and In used as a transparent electrode or an oxide semiconductor of an electronic device such as a semiconductor element or an FPD, the composition containing water and at least one type of acid, excluding hydrohalic acids, perhalic acids, etc., having an acid dissociation constant pKaat 25° C. in any dissociation stage of no greater than 2.15, and the composition having a pH at 25° C. of no greater than 4, and an etching method using the etching solution composition. 2. The etching solution composition according to claim 1 , wherein the metal oxide further comprises at least one type of element selected from the group consisting of aluminum claim 1 , gallium claim 1 , and tin.3. The etching solution composition according to claim 1 , wherein the acid is a mineral acid claim 1 , a sulfonic acid claim 1 , or oxalic acid.4. The etching solution composition according to claim 3 , wherein the mineral acid is sulfuric acid claim 3 , sulfamic acid claim 3 , peroxomonosulfuric acid claim 3 , phosphoric acid claim 3 , phosphorous acid claim 3 , hypophosphorous acid claim 3 , or nitric acid.5. The etching solution composition according to claim 3 , wherein the sulfonic acid is methanesulfonic acid claim 3 , ethanesulfonic acid claim 3 , para-toluenesulfonic acid claim 3 , camphorsulfonic acid ...

SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF

A semiconductor device includes a fin structure, a two-dimensional (2D) material channel layer, a ferroelectric layer, and a metal layer. The fin structure extends from a substrate. The 2D material channel layer wraps around at least three sides of the fin structure. The ferroelectric layer wraps around at least three sides of the 2D material channel layer. The metal layer wraps around at least three sides of the ferroelectric layer. 1. A semiconductor device , comprising:a fin structure extending from a substrate;a two-dimensional (2D) material channel layer wrapping around at least three sides of the fin structure;a ferroelectric layer wrapping around at least three sides of the 2D material channel layer; anda metal layer wrapping around at least three sides of the ferroelectric layer.2. The semiconductor device of claim 1 , wherein the 2D material channel layer is spaced apart from the fin structure.3. The semiconductor device of claim 1 , further comprising:a 2D material passivation layer between the fin structure and the 2D material channel layer.4. The semiconductor device of claim 3 , wherein the 2D material passivation layer includes boron nitride.5. The semiconductor device of claim 1 , wherein the 2D material channel layer includes transition metal dichalcogenide (TMD) or black phosphorus (BP).6. The semiconductor device of claim 1 , wherein the ferroelectric layer includes hafnium oxide doped with a semiconductor element or a metal element.7. The semiconductor device of claim 1 , wherein the ferroelectric layer contacts the three sides of the 2D material channel layer.8. The semiconductor device of claim 1 , wherein the metal layer contacts the three sides of the ferroelectric layer.9. The semiconductor device of claim 1 , wherein the 2D material channel layer has a metal oxide surface facing away from the fin structure.10. A semiconductor device claim 1 , comprising:a fin structure extending from a substrate;a boron nitride layer wrapping around at least ...

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer. 1. (canceled)2. A method for manufacturing a semiconductor device comprising:forming a semiconductor layer that comprises an oxide semiconductor including indium;processing the semiconductor layer by wet etching to form an island-shaped semiconductor layer;processing the island-shaped semiconductor layer by dry etching to form a recessed portion in the island-shaped semiconductor layer; andperforming oxygen radical treatment on the recessed portion.3. The method for manufacturing a semiconductor device according to claim 2 , wherein the island-shaped semiconductor layer is an In—Ga—Zn—O based non-single-crystal film.4. The method for manufacturing a semiconductor device according to claim 2 , wherein an oxygen content in a gas used in the dry etching is 15 volume % or more.5. The method for manufacturing a semiconductor device according to claim 2 , wherein the oxygen radical treatment is performed under an atmosphere comprising chlorine and fluorine.6. The method for manufacturing a semiconductor device according to claim 2 , further comprising:after forming the recessed portion, performing heat treatment on the island-shaped semiconductor layer at 200° C. to 600° C.7. The method for manufacturing a semiconductor device ...

Semiconductor Device And Manufacturing Method Thereof

Disclosed is a semiconductor device including an oxide semiconductor film. A first oxide semiconductor film with a thickness of greater than or equal to 2 nm and less than or equal to 15 nm is formed over a gate insulating layer. First heat treatment is performed so that crystal growth from a surface of the first oxide semiconductor film to the inside thereof is caused, whereby a first crystal layer is formed. A second oxide semiconductor film with a thickness greater than that of the first oxide semiconductor film is formed over the first crystal layer. Second heat treatment is performed so that crystal growth from the first crystal layer to a surface of the second oxide semiconductor film is caused, whereby a second crystal layer is formed. Further, oxygen doping treatment is performed on the second crystal layer. 1. (canceled)2. A method for manufacturing a semiconductor device , the method comprising the steps of:forming an insulating layer over a substrate; 'forming a stacked oxide semiconductor film over the insulating layer, the stacked oxide semiconductor film comprising a first oxide semiconductor film and a second oxide semiconductor film over the first oxide semiconductor film; and', 'performing a plasma treatment on the insulating layer;'}forming an oxide film over the stacked oxide semiconductor film,wherein the first oxide semiconductor film includes crystals which are c-axis aligned,wherein the second oxide semiconductor film includes crystals which are c-axis aligned, andwherein the oxide film includes one or more elements selected from constituent metal element of the second oxide semiconductor film.3. The method for manufacturing a semiconductor device according to claim 2 , the method further comprising the step of forming an electrode over the oxide film claim 2 ,wherein the electrode overlaps with the first oxide semiconductor film and the second oxide semiconductor film.4. The method for manufacturing a semiconductor device according to claim 2 ...

Method for manufacturing semiconductor device

To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.

SEMICONDUCTOR DEVICE AND DISPLAY DEVICE INCLUDING SEMICONDUCTOR DEVICE

The reliability of a transistor including an oxide semiconductor can be improved by suppressing a change in electrical characteristics. A transistor included in a semiconductor device includes a first oxide semiconductor film over a first insulating film, a gate insulating film over the first oxide semiconductor film, a second oxide semiconductor film over the gate insulating film, and a second insulating film over the first oxide semiconductor film and the second oxide semiconductor film. The first oxide semiconductor film includes a channel region in contact with the gate insulating film, a source region in contact with the second insulating film, and a drain region in contact with the second insulating film. The second oxide semiconductor film has a higher carrier density than the first oxide semiconductor film. 1. A semiconductor device comprising:an oxide semiconductor film;a gate insulating film over the oxide semiconductor film;an oxide conductor over the gate insulating film; anda first insulating film over the oxide semiconductor film and the oxide conductor,wherein the first insulating film is in contact with a top surface of oxide semiconductor film and a side surface of the oxide conductor, andwherein the oxide conductor has a higher carrier density than the oxide semiconductor film.2. The semiconductor device according to claim 1 , wherein the oxide conductor includes at least oxygen claim 1 , In claim 1 , Zn claim 1 , and M (M is Al claim 1 , Ga claim 1 , Y claim 1 , or Sn).3. The semiconductor device according to claim 1 , further comprising a conductive film between the oxide conductor and the first insulating film claim 1 , wherein the first insulating film is in contact with top and side surfaces of the conductive film.4. The semiconductor device according to claim 1 , wherein an upper end portion of the gate insulating film is aligned with a lower end portion of the oxide conductor or positioned outside the lower end portion of the oxide conductor ...

THIN FILM TRANSISTOR PANEL HAVING AN ETCH STOPPER ON SEMICONDUCTOR

A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper. 1. A method for forming a panel comprising a thin film transistor , the method comprising:forming an oxide semiconductor pattern comprising a channel region;forming an etch stopper at a position corresponding to the channel region; andforming a first electrode and a second electrode spaced apart from the first electrode, the channel region configured to connect the first electrode to the second electrode,wherein the etch stopper and the oxide semiconductor pattern are formed using a first mask.2. The method of claim 1 , further comprising:disposing a first conductive layer on a substrate;disposing a first insulating layer on the first conductive layer;disposing an oxide semiconductor layer on the first insulating layer; anddisposing an etch stop layer on the oxide semiconductor layer;wherein the etch stopper and the oxide semiconductor pattern are formed by patterning the etch stop layer and the oxide semiconductor layer using the first mask.3. The method of claim 2 , wherein patterning the etch stop layer and the oxide semiconductor layer comprises forming a photoresist pattern using the first mask.4. The method of claim 3 , wherein patterning the etch stop layer and the oxide semiconductor layer further comprises etching the etch stop layer having the photoresist pattern thereon to form an interim etch stopper.5. The method of claim 4 , wherein patterning the etch stop layer and the oxide semiconductor layer further comprises etching the oxide semiconductor layer having the interim etch stopper thereon to form the oxide semiconductor pattern.6. The method of claim 5 , wherein patterning the etch stop layer and the oxide semiconductor layer ...

ETCHING SOLUTION FOR COPPER/MOLYBDENUM-BASED MULTILAYER THIN FILM

The present invention relates to an etching solution being capable of selectively etching a copper/molybdenum-based multilayer thin film with respect to a semiconductor device having an oxide semiconductor layer and a copper/molybdenum-based multilayer thin film, wherein the etching solution comprises (A) hydrogen peroxide, (B) an inorganic acid containing no fluorine atom, (C) an organic acid, (D) an amine compound having 2 to 10 carbon atoms, and having an amino group and at least one group selected from an amino group and a hydroxyl group, (E) an azole, and (F) a hydrogen peroxide stabilizer, and has a pH of 2.5 to 5, as well as an etching method using the etching solution for selectively etching a copper/molybdenum-based multilayer thin film from a semiconductor device having an oxide semiconductor layer and a copper/molybdenum-based multilayer thin film. 1. An etching solution , comprising:(A) hydrogen peroxide;(B) an inorganic acid comprising no fluorine atom;(C) an organic acid;(D) an amine compound having 2 to 10 carbon atoms, and comprising a first amino group and at least one selected from the group consisting of a second amino group and a hydroxyl group;(E) an azole; and(F) a hydrogen peroxide stabilizer,wherein the etching solution has a pH of 2.5 to 5.2. The etching solution according to claim 1 , wherein the inorganic acid (B) is at least one of sulfuric acid and nitric acid.3. The etching solution according to claim 1 , wherein the organic acid (C) is at least one selected from the group consisting of succinic acid claim 1 , glycolic acid claim 1 , lactic acid claim 1 , malonic acid and malic acid.4. The etching solution according to claim 1 , wherein the amine compound (D) is at least one selected from the group consisting of ethanolamine claim 1 , 1-amino-2-propanol and N claim 1 ,N-diethyl-1 claim 1 ,3-propanediamine.5. The etching solution according to claim 1 , wherein the azole (E) is 5-amino-1H-tetrazole.6. The etching solution according to ...

SEMICONDUCTOR DEVICE STRUCTURE WITH GATE SPACER HAVING PROTRUDING BOTTOM PORTION AND METHOD FOR FORMING THE SAME

A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on the sidewall of the gate stack structure, and the gate spacers include a top portion and a bottom portion adjoined to the top portion, and the bottom portion slopes to a top surface of the substrate. The semiconductor device structure further includes an epitaxial structure formed adjacent to the gate spacers, and the epitaxial structure is formed below the gate spacers. 1. A semiconductor device structure , comprising:a substrate;a gate stack structure formed on the substrate;gate spacers formed on the sidewall of the gate stack structure, wherein the gate spacers comprise a top portion and a bottom portion adjoined to the top portion, and the bottom portion slopes to a top surface of the substrate; andan epitaxial structure formed adjacent to the gate spacers, wherein the epitaxial structure is formed below the gate spacers.2. The semiconductor device structure as claimed in claim 1 , wherein the top portion of the gate spacers has a first outer surface claim 1 , the bottom portion of the gate spacers has a second outer surface claim 1 , an angle between the first outer surface and the second outer surface is in a range from about 90 degrees to about 178 degrees.3. The semiconductor device structure as claimed in claim 1 , wherein the top portion has a uniform thickness.4. The semiconductor device structure as claimed in claim 1 , wherein the bottom portion of the gate spacers has a bottom surface which is in direct contact with the substrate claim 1 , and the bottom surface has a maximum thickness.5. The semiconductor device structure as claimed in claim 4 , wherein the maximum thickness is in a range from about 5 nm to about 12 nm.6. The semiconductor device structure as claimed in claim 1 , wherein the ...

MULTI-FACED COMPONENT-BASED ELECTROMECHANICAL DEVICE

An electromechanical device comprises a substrate structure, a set of electrodes, one or more anchor trenches, and one or more multi-faced components. For example, each of the one or more multi-faced components comprises an isolation region formed on a first portion of the surface of the component, a high resistance region formed on a second portion of the surface of the component, and a low resistance region formed on a third portion of the surface of the component. For example, the synapse device is configured to provide an analog resistive output, ranging between the high resistance region and the low resistance region, from at least one of the set of electrodes in response to a pulsed voltage input to at least another one of the set of electrodes. 1. An electromechanical device , comprising:a substrate structure;a plurality of electrodes formed over the substrate structure;an anchor trench formed adjacent to the plurality of electrodes; anda multi-faced component formed in the anchor trench and in operable proximity with the plurality of electrodes, wherein the multi-faced component comprises an isolation region formed on a first portion of the surface of the multi-faced component, a high resistance region formed on a second portion of the surface of the multi-faced component, and a low resistance region formed on a third portion of the surface of the multi-faced component; andwherein the electromechanical device is configured to provide an analog resistive-response output, ranging between the high resistance region and the low resistance region, from at least one of the plurality of electrodes in response to a control input.2. The device of claim 1 , wherein the plurality of electrodes comprises at least a set of source and drain electrodes and a set of gate electrodes.3. The device of claim 2 , wherein the anchor trench is formed between the set of source and drain electrodes.4. The device of claim 2 , wherein the multi-faced component formed in the anchor ...

TIN OXIDE FILMS IN SEMICONDUCTOR DEVICE MANUFACTURING

Tin oxide film on a semiconductor substrate is etched selectively in a presence of silicon (Si), carbon (C), or a carbon-containing material (e.g., photoresist) by exposing the substrate to a process gas comprising hydrogen (H) and a hydrocarbon. The hydrocarbon significantly improves the etch selectivity. In some embodiments an apparatus for processing a semiconductor substrate includes a process chamber configured for housing the semiconductor substrate and a controller having program instructions on a non-transitory medium for causing selective etching of a tin oxide layer on a substrate in a presence of silicon, carbon, or a carbon-containing material by exposing the substrate to a plasma formed in a process gas that includes Hand a hydrocarbon. 1. A method of processing a semiconductor substrate , the method comprising:(a) providing a semiconductor substrate having an exposed layer of tin oxide;{'sub': '2', '(b) selectively etching the tin oxide in a presence of a material selected from the group consisting of silicon (Si), carbon (C), and a carbon-containing material, by exposing the semiconductor substrate to a plasma formed in a process gas comprising Hand a hydrocarbon.'}2. The method of claim 1 , wherein the carbon-containing material is photoresist.3. The method of claim 1 , wherein the carbon-containing material is photoresist claim 1 , and wherein an etch selectivity for etching tin oxide in the presence of the photoresist is at least 100.4. The method of claim 1 , wherein the semiconductor substrate provided in (a) comprises an exposed patterned layer of photoresist.5. The method of claim 1 , wherein (b) comprises forming a carbon-containing polymer on the semiconductor substrate.6. The method of claim 1 , wherein the process gas comprises at least 50% of Hby volume.7. The method of claim 1 , wherein the hydrocarbon is methane (CH).8. The method of claim 1 , wherein a ratio of Hto hydrocarbon in the process gas is at least 5.9. The method of claim 1 , ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film. Next, in order to further reduce impurities such as moisture or hydrogen in the oxide semiconductor film, oxygen is added to the oxide semiconductor film by an ion implantation method, an ion doping method, or the like, and after that, second heat treatment is performed on the exposed oxide semiconductor film. 1. (canceled)2. A semiconductor device comprising a transistor comprising:a gate electrode;a gate insulating film over the gate electrode;an oxide semiconductor layer over the gate insulating film;a source electrode and a drain electrode electrically connected to the oxide semiconductor layer; andan insulating film over the source electrode and the drain electrode and in contact with the oxide semiconductor layer,wherein the oxide semiconductor layer comprises indium, gallium, and zinc,wherein the insulating film comprises silicon and oxygen,wherein the oxide semiconductor layer comprises a crystal region in which a c-axis of a crystal is aligned in a direction substantially perpendicular to a surface of the oxide semiconductor layer, andwherein a thickness of the oxide semiconductor layer is 5 nm or more and 30 nm or less.3. The semiconductor device according to claim 2 ,wherein a portion of the oxide semiconductor layer between the source electrode and the drain electrode is thinner than portions of the oxide semiconductor layer below the source electrode and the drain electrode, andwherein the portion of the oxide semiconductor layer includes the crystal region.4. The semiconductor device according to claim 2 , further comprising a pixel electrode electrically connected to the source electrode or the drain electrode ...

DOPED ZINC OXIDE AS N+ LAYER FOR SEMICONDUCTOR DEVICES

A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. An n-type layer is formed on or in the p-doped layer. The n-type layer includes ZnO on the p-doped layer to form an electronic device. 1. A semiconductor device , comprising:a substrate;a p-doped layer including a doped InGaAs material on the substrate;an n-type layer formed on or in the p-doped layer, the n-type layer including ZnO to form an electronic device, wherein the n-type layer includes an interface layer formed from materials of the n-type layer and the p-doped layer.2. The semiconductor device as recited in claim 1 , wherein the n-type layer includes doped ZnO deposited by an atomic layer deposition or epitaxially grown by metal organic chemical vapor deposition.3. (canceled)4. The semiconductor device as recited in claim 1 , wherein the n-type layer includes a carrier concentration of about 3×10cm.5. The semiconductor device as recited in claim 1 , wherein the n-type layer forms source and drain regions for a field effect transistor.6. The semiconductor device as recited in claim 1 , wherein the n-type layer forms a diode junction.7. (canceled)8. The semiconductor device as recited in claim 1 , wherein the electronic device includes an on/off ratio of greater than 1×10.9. The semiconductor device as recited in claim 1 , further comprising an aluminum contact layer formed on the n-type layer.10. A semiconductor device claim 1 , comprising:a substrate;a p-doped layer including a doped InGaAs material on the substrate; and{'sup': 21', '−3', '21', '−3, 'a doped ZnO formed as an n-type layer on or in the p-doped layer to form an electronic device, such that the n-type layer includes a carrier concentration of between about 1×10cmto about 5×10cm, wherein the n-type layer includes an interface layer formed from materials of the n-type layer and the p-doped layer.'}11. The semiconductor device as recited in claim 10 , wherein the n-type layer ...

ETCHING SOLUTION FOR AN ALUMINUM OXIDE FILM, AND METHOD FOR MANUFACTURING A THIN-FILM SEMICONDUCTOR DEVICE USING THE ETCHING SOLUTION

An etching solution includes: phosphoric acid having concentration of 30% by weight to 80% by weight; nitric acid having concentration of 10% by weight or less; and surfactant having concentration of 0.0005% by weight to 0.0050% by weight, wherein the etching solution is used for etching an aluminum oxide film having film density of 2.80 g/cmto 3.25 g/cm. 1. An etching solution comprising:phosphoric acid having concentration of 30% by weight to 80% by weight;nitric acid having concentration of 10% by weight or less; andsurfactant having concentration of 0.0005% by weight to 0.0050% by weight, wherein{'sup': 3', '3, 'the etching solution is used for etching an aluminum oxide film having film density of 2.80 g/cmto 3.25 g/cm.'}2. The etching solution of claim 1 , whereinthe phosphoric acid has concentration of 50% by weight to 70% by weight, andthe nitric acid has concentration of 2% by weight to 4% by weight.3. A manufacturing method of a thin-film semiconductor device claim 1 , the manufacturing method comprising:{'sup': 3', '3, 'forming an aluminum oxide film having film density of 2.80 g/cmto 3.25 g/cmabove an oxide semiconductor layer;'}providing a through-hole in the aluminum oxide film by etching the aluminum oxide film with use of an etching solution, the etching solution including phosphoric acid having concentration of 30% by weight to 80% by weight, nitric acid having concentration of 10% by weight or less, and surfactant having concentration of 0.0005% by weight to 0.0050% by weight; andembedding, in the through-hole provided in the aluminum oxide film, an electrode to be electrically connected with the oxide semiconductor layer.4. The manufacturing method of claim 3 , whereinthe phosphoric acid has concentration of 50% by weight to 70% by weight, andthe nitric acid has concentration of 2% by weight to 4% by weight.5. The manufacturing method of claim 3 , further comprising claim 3 , between forming the aluminum oxide film and providing the through-hole in ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film. Next, in order to further reduce impurities such as moisture or hydrogen in the oxide semiconductor film, oxygen is added to the oxide semiconductor film by an ion implantation method, an ion doping method, or the like, and after that, second heat treatment is performed on the exposed oxide semiconductor film. 1. (canceled)2. A method for manufacturing a semiconductor device comprising:forming an oxide semiconductor layer containing indium by sputtering method;forming a conductive film comprising a region in contact with the oxide semiconductor layer; andetching the conductive film for forming a source electrode and a drain electrode and etching a region of the oxide semiconductor layer which is not covered by the source electrode or the drain electrode,wherein the oxide semiconductor layer comprises a region in which a c-axis of a crystal is aligned along a direction perpendicular to a surface of the oxide semiconductor layer.3. The method for manufacturing a semiconductor device according to claim 2 ,wherein the oxide semiconductor layer further comprises gallium and zinc.4. A method for manufacturing a semiconductor device comprising:forming an oxide semiconductor layer containing indium by sputtering method;forming a conductive film comprising a region in contact with the oxide semiconductor layer; andetching the conductive film for forming a source electrode and a drain electrode and etching a region of the oxide semiconductor layer which is not covered by the source electrode or the drain electrode,wherein the oxide semiconductor layer comprises a first region in which a c-axis of a crystal is aligned along a direction ...

FIELD EFFECT TRANSISTOR AND PROCESS OF FORMING THE SAME

A process of forming a field effect transistor (FET) and a FET are disclosed. The process includes steps of forming a nitride semiconductor layer on a substrate; selectively growing an n-region made of oxide semiconductor material on the nitrides semiconductor layer and subsequently depositing oxide film on the n-region; rinsing the oxide film with an acidic solution; forming an opening in the oxide film to expose the oxide semiconductor layer therein; and depositing a metal within the opening such that the metal is in direct contact with the n-region. 1. A process of forming a field effect transistor (FET) , comprising:forming a nitride semiconductor layer on a substrate;{'sup': +', '+, 'selectively growing an n-region made of oxide semiconductor material on the nitride semiconductor layer and depositing oxide film on the n-region;'}rinsing a surface of the oxide film with an acidic solution;{'sup': '+', 'forming an opening in the oxide film, the opening exposing the n-region therein; and'}{'sup': '+', 'depositing a metal within the opening, the metal being in direct contact with the n-region.'}2. The process according to claim 1 ,forming a recess in the nitride semiconductor layer using a photoresist with an opening as a mask;{'sup': '+', 'growing the n-region only within the recess;'}{'sup': '+', 'forming the oxide film onto the n-region; and'}removing the photoresist accompanying with the oxide semiconductor material accumulated onto the photoresist.3. The process according to claim 2 ,{'sup': '+', 'wherein the step of growing the n-region grows the oxide semiconductor material made of zinc oxide (ZnO).'}4. The process according to claim 3 ,{'sup': '+', 'sub': '2', 'wherein the step of growing the n-region uses a pulsed laser deposition (PLD) technique that irradiates a ZnO target with laser beams in oxygen (O) atmosphere at 100° C.'}5. The process according to claim 2 ,wherein the step of forming the oxide film forms one of aluminum oxide (AlO) and zirconium ...

Formation of a high aspect ratio trench in a semiconductor substrate and a bipolar semiconductor device having a high aspect ratio trench isolation region

Disclosed is a trench formation technique wherein a first etch process forms an opening through a semiconductor layer into a semiconductor substrate and then a second etch process expands the portion of the opening within the substrate to form a trench. However, prior to the second etch, a doped region is formed in the substrate at the bottom surface of the opening. Then, the second etch is performed such that an undoped region of the substrate at the sidewalls of the opening is etched at a faster etch rate than the doped region, thereby ensuring that the trench has a relatively high aspect ratio. Also disclosed is a bipolar semiconductor device formation method. This method incorporates the trench formation technique so that a trench isolation region formed around a collector pedestal has a high aspect ratio and, thereby so that collector-to-base capacitance C cb and collector resistance R c are both minimized.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a fin structure disposed over a substrate, a gate structure and a source. The fin structure includes an upper layer being exposed from an isolation insulating layer. The gate structure disposed over part of the upper layer of the fin structure. The source includes the upper layer of the fin structure not covered by the gate structure. The upper layer of the fin structure of the source is covered by a crystal semiconductor layer. The crystal semiconductor layer is covered by a silicide layer formed by Si and a first metal element. The silicide layer is covered by a first metal layer. A second metal layer made of the first metal element is disposed between the first metal layer and the isolation insulating layer. 1. A method of manufacturing a semiconductor device including a FinFET , the method comprising:forming a first fin structure and a second fin structure over a substrate, the first and second fin structures extending in a first direction and protruding from an isolation insulating layer;forming a gate structure over part of the first and second fin structures, the gate structure extending in a second direction perpendicular to the first direction;forming sidewall spacers on both major side surfaces of each of the first and second fin structures not covered by the gate structure;forming first metal layers on the sidewall spacers and second metal layers on the first metal layers, thereby filling a space between the first and second fin structures;after forming the first and second metal layers, removing the sidewall spacers;after removing the sidewall spacers, forming an amorphous layer in contact with the fin structure;forming a recrystallized layer by partially recrystallizing the amorphous layer on the fin structure;removing a remaining amorphous layer which is not recrystallized;after removing the remaining amorphous layer, forming a third metal layer including a metal material having a lower silicide formation temperature ...

Method for the fabrication of thin-film transistors together with other components on a substrate

A method for the fabrication of thin-film transistors together with micromechanical components, other active electrical components or both on an amorphous or polycrystalline substrate includes disposing the thin-film transistors and the other components on different areas of the substrate. 1. A method for the fabrication of thin-film transistors together with micromechanical components , other active electrical components or both on an amorphous or polycrystalline substrate , wherein the thin-film transistors and the other active electrical components are each disposed on different areas of the substrate , the method comprising the stapes of:applying a first layer of an electrode material to the substrate;structuring the first layer into drain and source electrodes in an area of the thin-film transistors and into electrodes in an area of other electrical components;after structuring the first layer, applying a semiconductor layer;structuring the semiconductor layer such that the drain and source electrodes in the area of the transistors and the electrodes in the area of the other electrical components remain at least partially covered by the semiconductor layer, and that micromechanical components in an area of micromechanical components that are subsequently to have cavities remain covered;depositing a dielectric layer;structuring the dielectric layer to a gate dielectric of the thin-film transistors in the area of the transistors, at least partially covering the semiconductor layer above the electrodes in the area of the other electrical components and at least partially removing the semiconductor layer above the micromechanical components in the area of the micromechanical components;applying a second layer of an electrode material;{'b': '102', 'i': 'c', 'structuring the second layer of electrode material into gate electrodes in the area of the transistors, into second electrodes in areas above the semiconductor layer and above the first electrodes () the area of ...

METHOD FOR MANUFACTURING THIN-FILM TRANSISTOR

The present invention provides a method for manufacturing a thin-film transistor. The thin-film transistor has a bottom gate coplanar structure. The method includes the following steps: step (): providing a substrate (); step (): forming a gate terminal () on the substrate (); step (): forming a gate insulator layer () on the gate terminal () and the substrate (); step (): forming a source/drain terminal () on the gate insulator layer () and covering the source/drain terminal () with a photosensitive material layer (); step (): subjecting a surface of the gate insulator layer () to a plasma treatment; step (): removing the photosensitive material layer () located on the source/drain terminal (); and step (): forming an oxide semiconductor layer () on the source/drain terminal () and the gate insulator layer () and patternizing the oxide semiconductor layer (). The present invention applies a plasma treatment to a surface of the gate insulator layer to repair defects on an interface between the gate insulator layer and the oxide semiconductor layer so as to improve the electrical characteristics of the thin-film transistor. 1. A method for manufacturing a thin-film transistor , wherein the thin-film transistor has a bottom gate coplanar structure , the method comprising the following steps:{'b': '1', '() providing a substrate;'}{'b': '2', '() forming a gate terminal on the substrate;'}{'b': '3', '() forming a gate insulator layer on the gate terminal and the substrate;'}{'b': '4', '() forming a source/drain terminal on the gate insulator layer and covering the source/drain terminal with a photosensitive material layer;'}{'b': '5', '() subjecting a surface of the gate insulator layer to a plasma treatment;'}{'b': '6', '() remove the photosensitive material layer located on the source/drain terminal; and'}{'b': '7', '() forming an oxide semiconductor layer on the source/drain terminal and the gate insulator layer and patternizing the oxide semiconductor layer.'}2. The ...

SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF

A semiconductor device includes a fin structure extending along a first direction, a channel layer wrapping around a top surface and opposite sidewalls of the fin structure, a gate stack extending across the channel layer along a second direction perpendicular to the first direction, and a spacer on a top surface of the channel layer and a sidewall of the gate stack when viewed in a cross section taken along the first direction. The channel layer includes a two-dimensional material. The gate stack includes a ferroelectric layer. 1. A semiconductor device comprising:a fin structure extending along a first direction;a channel layer wrapping around a top surface and opposite sidewalls of the fin structure, wherein the channel layer includes a two-dimensional material;a gate stack extending across the channel layer along a second direction perpendicular to the first direction, wherein the gate stack includes a ferroelectric layer; anda spacer on a top surface of the channel layer and a sidewall of the gate stack when viewed in a cross section taken along the first direction.2. The semiconductor device of claim 1 , wherein the gate stack further includes a cap layer on a top surface of the ferroelectric layer and a gate layer on a top surface of the cap layer.3. The semiconductor device of claim 1 , further comprising a passivation layer sandwiched between the fin structure and the channel layer.4. The semiconductor device of claim 1 , further comprising a passivation layer sandwiched between the fin structure and the spacer.5. The semiconductor device of claim 1 , further comprising a source/drain metal layer on a sidewall of the spacer when viewed in the cross section take along the first direction.6. The semiconductor device of claim 1 , further comprising a source/drain metal layer on a sidewall of the channel layer when viewed in a cross section taken along the second direction.7. The semiconductor device of claim 1 , further comprising a source/drain metal layer ...

SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF

A method of fabricating a semiconductor device includes forming a fin structure on a substrate, forming a channel layer on a sidewall and a top surface of the fin structure, and forming a gate stack over the channel layer. The channel layer includes a two-dimensional (2D) material. The gate stack includes a ferroelectric layer. 1. A method of fabricating a semiconductor device , the method comprising:forming a fin structure on a substrate;forming a channel layer on a sidewall and a top surface of the fin structure, wherein the channel layer includes a two-dimensional (2D) material; andforming a gate stack over the channel layer, wherein the gate stack includes a ferroelectric layer.2. The method of claim 1 , further comprising performing a surface treatment on the channel layer before forming the gate stack.3. The method of claim 1 , wherein forming the gate stack comprises:forming a dielectric layer over the fin structure; andannealing the dielectric layer to form the ferroelectric layer.4. The method of claim 3 , further comprising forming a cap layer over the dielectric layer before annealing the dielectric layer.5. The method of claim 1 , wherein forming the gate stack comprises:forming a dielectric layer over the fin structure;doping the dielectric layer with a semiconductor material; andconverting the doped dielectric layer into the ferroelectric layer.6. The method of claim 1 , wherein forming the gate stack comprises:forming a dielectric layer over the fin structure;doping the dielectric layer with metal; andconverting the doped dielectric layer into the ferroelectric layer.7. The method of claim 1 , further comprising;forming a spacer on a sidewall of the gate stack and a top surface of the channel layer.8. The method of claim 7 , further comprising;forming a source/drain metal layer on the spacer.9. The method of claim 8 , further comprising performing a chemical mechanical polish (CMP) process to level the source/drain metal layer with the spacer.10. A ...

ETCHANT AND ETCHING PROCESS FOR OXIDES CONTAINING AT LEAST INDIUM AND GALLIUM

The present invention relates to an etchant and an etching process, which are preferred for use in etching of oxides containing at least indium and gallium, such as an oxide consisting of indium, gallium and oxygen or an oxide consisting of indium, gallium, zinc and oxygen. According to preferred embodiments of the present invention, an etchant comprising sulfuric acid or a salt thereof and a carboxylic acid (except for oxalic acid) or a salt thereof ensures a preferred etching rate, a good residue removal property and low corrosiveness to wiring materials when used in etching of oxides containing at least indium and gallium. Moreover, this etchant not only causes no precipitate but also retains a preferred etching rate even when the concentration of oxides dissolved in the etchant is elevated. 1. An etchant for etching an oxide containing at least indium and gallium , which comprises sulfuric acid or a salt thereof and a carboxylic acid (except for oxalic acid) or a salt thereof.2. The etchant according to claim 1 , wherein the carboxylic acid (except for oxalic acid) or a salt thereof is one or more members selected from the group consisting of acetic acid claim 1 , glycolic acid claim 1 , lactic acid claim 1 , malonic acid claim 1 , maleic acid claim 1 , succinic acid claim 1 , malic acid claim 1 , tartaric acid and citric acid.3. The etchant according to claim 1 , wherein the sulfuric acid or a salt thereof is in a concentration of 0.5% to 20% by mass claim 1 , and the carboxylic acid or a salt thereof is in a concentration of 0.1% to 15% by mass.4. The etchant according to claim 1 , which further comprises a pH adjuster.5. The etchant according to claim 4 , wherein the pH adjuster is one or more members selected from the group consisting of methanesulfonic acid and amidosulfuric acid.6. The etchant according to claim 1 , which has a pH value equal to or less than 1.7. The etchant according to claim 1 , which further comprises a polysulfonic acid compound.8. The ...

ARRAY SUBSTRATE FOR LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

An array substrate for a liquid crystal display device includes a substrate; a semiconductor layer on the substrate; a gate electrode on the semiconductor layer; source and drain electrodes on and in contact with the semiconductor layer; and an oxide layer on the gate electrode, the oxide layer including a plurality of metal atoms, wherein each of the source and drain electrodes includes a pattern of metal substantially made of the plurality of metal atoms. 1. An array substrate for a liquid crystal display device , comprising:a substrate;a semiconductor layer on the substrate;a gate electrode on the semiconductor layer;source and drain electrodes on and in contact with the semiconductor layer; andan oxide layer on the gate electrode, the oxide layer including a plurality of metal atoms,wherein each of the source and drain electrodes includes a pattern of metal substantially made of the plurality of metal atoms.2. The array substrate of claim 1 , wherein the source electrode includes a first source pattern and a second source pattern below the first source pattern claim 1 , and the drain electrode includes a first drain pattern and a second drain pattern below the first drain pattern claim 1 , andwherein the oxide layer is located at the same layer as the second source and drain patterns.3. The array substrate of claim 2 , wherein the first source and drain patterns has a specific resistance less than the second source and drain patterns claim 2 , and has a contact resistance for a conductor greater than the second source and drain patterns.4. The array substrate of claim 2 , wherein the first source and drain patterns are made of one of Cu claim 2 , Au and Mo claim 2 , and the second source and drain patterns are made of one of Al claim 2 , Al alloy claim 2 , Cu claim 2 , Ni claim 2 , Cr claim 2 , Ti claim 2 , Pt claim 2 , Ta claim 2 , Ti alloy claim 2 , Mo and Mo alloy.5. The array substrate of claim 1 , wherein the oxide layer is made of one of AlxOx claim 1 , ...

SAPPHIRE STRUCTURE WITH METAL SUBSTRUCTURE AND METHOD FOR PRODUCING THE SAME

A sapphire structure with a metal substructure is disclosed. The sapphire structure with a metal substructure includes a sapphire structure and a metal substructure. The sapphire structure includes a flat surface and a concave portion on the flat surface. The metal substructure in the concave portion is bonded to an inner surface of the concave portion and includes a surface portion that is substantially flush with the flat surface. 1. A sapphire structure with a metal substructure , comprising:a sapphire structure that includes a flat surface and a concave portion on the flat surface; anda metal substructure in the concave portion, which is bonded to an inner surface of the concave portion and includes a surface portion that is substantially flush with the flat surface of the sapphire structure.2. The sapphire structure with a metal substructure according to claim 1 , wherein the metal substructure contains silver as a main component.3. The sapphire structure with a metal substructure according to claim 2 , wherein the metal substructure contains silicon dioxide.4. The sapphire structure with a metal substructure according to claim 2 , wherein the metal substructure contains copper.5. The sapphire structure with a metal substructure according to claim 2 , wherein the metal substructure contains titanium.6. The sapphire structure with a metal substructure according to claim 5 , wherein the metal substructure comprises a bonding layer bonded to the inner surface of the concave portion of the sapphire structure claim 5 , the bonding layer containing titanium as a main component.7. The sapphire structure with a metal substructure according to claim 1 , wherein the inner surface of the concave portion of the sapphire structure comprises:a bottom surface,a side surface,and a corner between the bottom surface and the side surface, wherein the corner is inclined with respect to the bottom surface and the side surface.8. The sapphire structure with a metal substructure ...

Near-Unity Photoluminescence Quantum Yield in MoS2

Two-dimensional (2D) transition-metal dichalcogenides have emerged as a promising material system for optoelectronic applications, but their primary figure-of-merit, the room-temperature photoluminescence quantum yield (QY) is extremely poor. The prototypical 2D material, MoSis reported to have a maximum QY of 0.6% which indicates a considerable defect density. We report on an air-stable solution-based chemical treatment by an organic superacid which uniformly enhances the photoluminescence and minority carrier lifetime of MoSmonolayers by over two orders of magnitude. The treatment eliminates defect-mediated non-radiative recombination, thus resulting in a final QY of over 95% with a longest observed lifetime of 10.8±0.6 nanoseconds. Obtaining perfect optoelectronic monolayers opens the door for highly efficient light emitting diodes, lasers, and solar cells based on 2D materials. 1. A method of passivating and repairing a 2D transition metal dichalcogenide (TMDC) to enhance the photoluminescence quantum yield (QY) comprising:dissolving bis(trifluoromethane)sulfonimide (TFSI) in 1,2-dichloroethane (DCE) to make a solution;diluting the solution with 1,2-dichlorobenzene (DCB) or DCE to make a TFSI solution;immersing a TMDC sample in the TFSI solution; andannealing the TMDC sample at an elevated temperature.2. The method of claim 1 , wherein the 2D transition metal dichalcogenide is selected from the group consisting of MoS claim 1 , WS claim 1 , MoSe claim 1 , WSe claim 1 , MoTe claim 1 , and WTe.3. The method of claim 1 , further comprising dissolving 20 mg of TFSI in 10 ml of DCE to make a 2 mg/ml solution claim 1 , further diluting the solution with DCB or DCE to make a 0.2 mg/ml TFSI solution claim 1 , immersing the TMDC sample in the 0.2 mg/ml TFSI solution in a tightly closed vial for between approximately 1 min and 20 min claim 1 , preferably 10 min at an elevated temperature of approximately between 90° C. to 110° C. claim 1 , preferably 100° C. claim 1 , ...

LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

Provided are liquid crystal display and the method for manufacturing the same. According to an aspect of the present invention, there is provided a liquid crystal display device, including a first substrate; a gate electrode disposed on the first substrate; a semiconductor pattern layer disposed on the gate electrode; and a source electrode and a drain electrode disposed on the semiconductor pattern layer and facing each other, wherein a diffusion prevention pattern is disposed on the semiconductor pattern layer to prevent diffusion into the semiconductor pattern layer or to maintain uniform thickness of the semiconductor pattern layer. 1. A liquid crystal display device , comprising:a first substrate;a gate electrode disposed on the first substrate;a semiconductor pattern layer disposed on the gate electrode;a diffusion prevention pattern disposed on the semiconductor pattern layer;an ohmic contact layer disposed on the semiconductor pattern layer and exposing a part of the diffusion prevention pattern; anda source electrode and a drain electrode disposed on the ohmic contact layer to overlap the ohmic contact layer and facing each other to be spaced apart from each other.2. The liquid crystal display device of claim 1 ,wherein the ohmic contact layer contains a phosphorus (P) atom.3. The liquid crystal display device of claim 2 ,wherein the concentration of the phosphorus (P) atom is 1.74E+21/cm3 or more.4. The liquid crystal display device of claim 1 ,wherein a channel unit is disposed in the space between the source electrode and the drain electrode spaced apart from each other, andthe diffusion prevention pattern overlaps the channel unit.5. The liquid crystal display device of claim 4 , wherein the height of the semiconductor pattern layer overlapping the channel unit is equal to the height of the semiconductor pattern layer not overlapping the channel unit.6. The liquid crystal display device of claim 1 , wherein the outer end of the diffusion prevention ...

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

A semiconductor device with favorable electrical characteristics is provided. A semiconductor device with stable electrical characteristics is provided. A highly reliable semiconductor device is provided. A semiconductor layer is formed, a gate insulating layer is formed over the semiconductor layer, a metal oxide layer is formed over the gate insulating layer, and a gate electrode which overlaps with part of the semiconductor layer is formed over the metal oxide layer. Then, a first element is supplied through the metal oxide layer and the gate insulating layer to a region of the semiconductor layer that does not overlap with the gate electrode. Examples of the first element include phosphorus, boron, magnesium, aluminum, and silicon. The metal oxide layer may be processed after the first element is supplied to the semiconductor layer. 1. A method of manufacturing a semiconductor device , comprising the steps of:forming a semiconductor layer;forming a gate insulating layer over the semiconductor layer;forming a metal oxide layer over the gate insulating layer;forming, over the metal oxide layer, a gate electrode which overlaps with part of the semiconductor layer; andsupplying a first element through the metal oxide layer and the gate insulating layer to a region, in the semiconductor layer, which does not overlap with the gate electrode,wherein the first element is phosphorus, boron, magnesium, aluminum, or silicon.2. A method of manufacturing a semiconductor device , comprising the steps of:forming a semiconductor layer;forming a gate insulating layer over the semiconductor layer;forming a metal oxide layer over the gate insulating layer;forming, over the metal oxide layer, a gate electrode which overlaps with part of the semiconductor layer;supplying a first element through the metal oxide layer and the gate insulating layer to a region, in the semiconductor layer, which does not overlap with the gate electrode; andprocessing the metal oxide layer into an island ...

SOLUTION FOR ETCHING A THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME

Disclosed herein is an aqueous alkaline etching solution comprising water and an alkaline material being selected from the group consisting of ammonium hydroxide, ammonium phosphate, ammonium carbonate, quaternary ammonium hydroxide, quaternary ammonium phosphate, quaternary ammonium carbonate, an alkali metal hydroxide, an alkaline earth metal hydroxide, or a combination comprising at least one of the foregoing alkaline materials; the aqueous alkaline solution being operative to etch aluminum oxide at a rate greater than or equal to about 2:1 over a rate at which it etches a metal oxide semiconductor to be protected; wherein the aqueous etching solution has a pH of 8 to 13. 1. An aqueous alkaline etching solution comprising:water; and an alkaline material;the alkaline material being selected from the group consisting of ammonium hydroxide, ammonium phosphate, quaternary ammonium hydroxide, quaternary ammonium phosphate, ammonium carbonate, quaternary ammonium carbonate, an alkali metal hydroxide, an alkaline earth metal hydroxide, or a combination comprising at least one of the foregoing alkaline materials; the aqueous alkaline solution being operative to etch aluminum oxide at a rate greater than or equal to about 2:1 over a rate at which it etches a metal oxide semiconductor to be protected; wherein the aqueous etching solution has a pH of 8 to 13.2. The aqueous alkaline etching solution of claim 1 , where the alkaline material is metal ion free.3. The aqueous alkaline etching solution of claim 1 , where the metal oxide semiconductor is selected from the group consisting of zinc oxide claim 1 , indium zinc oxide claim 1 , indium gallium zinc oxide claim 1 , magnesium zinc oxide claim 1 , gallium zinc oxide claim 1 , indium gallium magnesium zinc oxide claim 1 , tin oxide claim 1 , indium oxide claim 1 , gallium oxide claim 1 , copper oxide claim 1 , silver oxide claim 1 , and combinations thereof.4. The aqueous alkaline etching solution of claim 1 , where the ...

3D UTB Transistor Using 2D-Material Channels

A semiconductor device and a method of manufacture are provided. A substrate has a dielectric layer formed thereon. A three-dimensional feature, such as a trench or a fin, is formed in the dielectric layer. A two-dimensional layer, such as a layer (or multilayer) of graphene, transition metal dichalcogenides (TMDs), or boron nitride (BN), is formed over sidewalls of the feature. The two-dimensional layer may also extend along horizontal surfaces, such as along a bottom of the trench or along horizontal surfaces of the dielectric layer extending away from the three-dimensional feature. A gate dielectric layer is formed over the two-dimensional layer and a gate electrode is formed over the gate dielectric layer. Source/drain contacts are electrically coupled to the two-dimensional layer on opposing sides of the gate electrode. 1. A method of forming a semiconductor device , the method comprising:forming a first trench in a first insulating layer;forming a two-dimensional (2D) material layer over the first insulating layer, the 2D material layer covering an upper surface of the first insulating layer, sidewalls of the first trench, and a bottom of the first trench;forming a gate dielectric over a portion of the 2D material layer;forming a first gate electrode over the gate dielectric along a first sidewall of the first trench;forming a source contact to the 2D material layer along the first sidewall of the first trench on a first side of the first gate electrode; andforming a drain contact to the 2D material layer along the first sidewall of the first trench on a second side of the first gate electrode.2. The method of claim 1 , further comprising removing the 2D material layer from the upper surface of the first insulating layer.3. The method of claim 2 , wherein removing the 2D material layer from the upper surface of the first insulating layer is performed at least in part by a CMP process.4. The method of claim 1 , further comprising removing the 2D material layer ...

Transistor with Multi-Metal Gate

A transistor includes a gate electrode with multiple metals distributed along the width of the gate electrode. Each of the metals in the gate electrode has different work functions. Such a compound gate provides higher linearity when, e.g., operated as a radio frequency transistor. 1. A transistor , comprising:a semiconductor structure;a source electrode and a drain electrode arranged on the semiconductor structure; anda gate electrode extending between the source electrode and the drain electrode along a length of the transistor, wherein the gate electrode includes at least two slabs of different metals arranged adjacent to each other along a width of the gate electrode transistor, wherein the different metals of the slabs have different work-functions forming along the length of the transistor at least a first virtual channel having a first gm3 curve and a second virtual having a second gm3 curve in destructive interference with the first gm3 curve.2. The transistor of claim 1 , wherein the semiconductor structure includes a source region claim 1 , a channel region claim 1 , and a drain region claim 1 , wherein the source electrode is deposited on top of the source region claim 1 , wherein the drain electrode is deposited on top of the drain region claim 1 , and wherein the gate electrode is deposited on top of the channel region claim 1 , wherein the source region and the drain region are doped by first impurities having a first conductivity type claim 1 , wherein the channel region is doped by second impurities having a second conductivity type opposite to the first conductivity type.3. The transistor of claim 1 , further comprising:a layer of metal arranged on top of the slabs of different metals.4. The transistor of claim 3 , wherein the slabs do not touch each other.5. The transistor of claim 1 , wherein the slabs have different gate-width.6. The transistor of claim 1 , wherein the slabs touch each other along sides of the slabs forming a gate-length.7. The ...

SUBSTRATE TREATMENT METHOD

A substrate treatment method includes a substrate holding unit which horizontally holds a substrate; a rotating unit which rotates the substrate held by the substrate holding unit about a vertical axis; and a first nozzle having an opposing face to be opposed to a lower surface of the substrate inward of a peripheral portion of the substrate in spaced relation to the lower surface of the substrate during rotation of the substrate by the rotating unit and a treatment liquid spout provided in the opposing face for filling a space defined between the lower surface of the substrate and the opposing face with a treatment liquid spouted from the treatment liquid spout to keep the space in a liquid filled state; wherein the treatment liquid spreads outwardly over the lower surface of the substrate and further, flows around to a peripheral portion of an upper surface of the substrate. 1. A substrate treatment method of treating a peripheral portion of a substrate with a treatment liquid spouted from a first nozzle having an opposing face to be brought into opposed spaced relation to a lower surface of the substrate , the method comprising:a. a rotating step of rotating the substrate about a vertical axis;b. a liquid filling step of supplying the treatment liquid to a space defined between the lower surface of the substrate and the opposing face from a treatment liquid spout provided in the opposing face to keep the space in a liquid filled state, the liquid filling step being performed simultaneously with the rotating step;c. a treatment liquid spreading step of allowing the treatment liquid in the space to be spread outward radially about the vertical axis over a region of the lower surface of the substrate not opposed to the opposing face;d. a step of allowing the treatment liquid to flow around from the lower surface to a peripheral portion of an upper surface of the substrate; ande. a step of controlling a width of the peripheral portion of the upper surface of the ...

THIN FILM TRANSISTOR HAVING THE TAPER ANGLE OF THE ACTIVE PATTERN IS GREATER THAN THE TAPER ANGLE OF THE SOURCE METAL PATTERN

A thin film transistor includes a gate electrode, an active pattern overlapping with the gate electrode and including a semiconductive oxide, and a source metal pattern disposed on the active pattern and including a source electrode and a drain electrode spaced apart from the source electrode. The active pattern underlaps an entire portion of a lower surface of the source metal pattern and minimally protrudes beyond lateral ends of the source metal pattern due to the active pattern having sidewall taper angles that are substantially greater than corresponding and adjacent sidewall taper angles of the overlying source metal pattern. Thus parasitic capacitance may be reduced and performance enhanced. 1. A thin film transistor structure comprising:a gate electrode disposed on a substrate;an active pattern overlapping the gate electrode and comprising a semiconductive oxide; anda source metal pattern disposed on the active pattern and including a source electrode and a drain electrode spaced apart from one another,wherein the active pattern underlaps an entire portion of a lower surface of the source metal pattern, and has a base and a sidewall defining a first taper angle that is greater than a second taper angle defined by and adjacent sidewall and the lower surface of the source metal pattern.2. The thin film transistor structure of claim 1 , wherein the second taper angle of the source metal pattern is between about 50 degrees to about 80 degrees.3. The thin film transistor structure of claim 1 , wherein the first taper angle of the active pattern is between about 70 degrees to about 90 degrees.4. The thin film transistor structure of claim 1 , wherein the active pattern comprises at least one member selected from the group consisting of zinc oxide claim 1 , zinc tin oxide claim 1 , indium zinc oxide claim 1 , indium oxide claim 1 , titanium oxide claim 1 , indium gallium zinc oxide and indium zinc tin oxide.5. The thin film transistor structure of claim 4 , wherein ...

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

A method for manufacturing a semiconductor device includes the steps of forming a first insulating film over a first gate electrode over a substrate while heated at a temperature higher than or equal to 450° C. and lower than the strain point of the substrate, forming a first oxide semiconductor film over the first insulating film, adding oxygen to the first oxide semiconductor film and then forming a second oxide semiconductor film over the first oxide semiconductor film, and performing heat treatment so that part of oxygen contained in the first oxide semiconductor film is transferred to the second oxide semiconductor film. 1. (canceled)2. A method for manufacturing a semiconductor device comprising the steps of:forming a gate electrode over a substrate;forming a first insulating film over the gate electrode while heating the substrate;forming a first oxide semiconductor film over the first insulating film;forming a second oxide semiconductor film over the first oxide semiconductor film;performing a first heat treatment after forming the second oxide semiconductor film;etching part of the first insulating film, part of the first oxide semiconductor film, and part of the second oxide semiconductor film, whereby forming a first gate insulating film having a projection, an etched first oxide semiconductor film, and an etched second oxide semiconductor film; andforming a pair of electrodes over the etched second oxide semiconductor film,wherein a temperature of the first heat treatment is lower than a temperature at which the first insulating film is formed.3. The method according to claim 2 , further comprising the step of adding oxygen to the first oxide semiconductor film after forming the first oxide semiconductor filmwherein the oxygen is added to the first oxide semiconductor film by an ion implantation method, an ion doping method, or a plasma treatment.4. The method according to claim 2 , further comprising the step of forming a third oxide semiconductor film ...

TIN OXIDE FILMS IN SEMICONDUCTOR DEVICE MANUFACTURING

A method of processing a substrate includes: providing a substrate having one or more mandrels comprising a mandrel material, wherein a layer of a spacer material coats horizontal surfaces and sidewalls of the one or more mandrels; and etching and completely removing the layer of the spacer material from the horizontal surfaces of the one or more mandrels and thereby exposing the mandrel material, without completely removing the spacer material residing at the sidewalls of the one or more mandrels. The etching includes exposing the substrate to a plasma formed using a mixture comprising a first gas and a polymer-forming gas, and wherein the etching comprises forming a polymer on the substrate. Polymer-forming gas may include carbon (C) and hydrogen (H). 1. A method of processing a substrate , the method comprising:(a) providing a substrate having one or more mandrels comprising a mandrel material, wherein a layer of a spacer material coats horizontal surfaces and sidewalls of the one or more mandrels; and(b) etching and completely removing the layer of the spacer material from the horizontal surfaces of the one or more mandrels and thereby exposing the mandrel material, without completely removing the spacer material residing at the sidewalls of the one or more mandrels, wherein the etching comprises exposing the substrate to a plasma formed using a mixture comprising a first gas and a polymer-forming gas, and wherein the etching comprises forming a polymer on the substrate.2. The method of claim 1 , wherein the polymer-forming gas comprises carbon (C) and hydrogen (H).3. The method of claim 1 , wherein the polymer-forming gas is a hydrocarbon.4. The method of claim 1 , wherein the polymer-forming gas is methane (CH).5. The method of claim 1 , wherein the first gas comprises one or more compounds comprising hydrogen (H).6. The method of claim 1 , wherein the etching is performed in a plasma processing apparatus claim 1 , the plasma processing apparatus comprising a ...

Multi-Level Cell Thin-Film Transistor Memory and Method of Fabricating the Same

A multi-level cell thin-film transistor memory and a method of fabricating the same, a structure of which memory comprises sequentially from down to top: a gate electrode, a charge blocking layer, a charge trapping layer, a charge tunneling layer, an active region, and source and drain electrodes; wherein- the charge tunneling layer fully encloses the charge trapping layer so as to completely isolate the charge trapping layer from the ambience, which prevents change of physical properties and chemical compositions of the charge trapping layer during the annealing treatment, reduces loss of charges stored in the charge trapping layer, and enhances data retention property and device performance stability; a metal oxide semiconductor thin film is utilized as the charge trapping layer of the memory, which implements multi-level cell storage and improves storage density 1. A multi-level cell thin-film transistor memory , a structure of which memory comprises sequentially from down to top: a gate electrode , a charge blocking layer , a charge trapping layer , a charge tunneling layer , an active region , and source and drain electrodes; the memory is fabricated by annealing treatment;{'sub': 2', '3', '2', '3', '2, 'wherein, the charge tunneling layer fully encloses the charge trapping layer so as to completely isolate the charge trapping layer from the ambience to prevent change of physical properties and chemical compositions of the charge trapping layer during the annealing treatment and reduce loss of charges stored in the charge trapping layer; a material of the charge trapping layer is any one of ZnO, InO, GaO, SnO, InSnO, or IGZO (amorphous indium gallium zinc oxide).'}2. The multi-level cell thin-film transistor memory according to claim 1 , wherein a material of the gate electrode is P-type single crystal silicon wafer claim 1 , glass claim 1 , or PI flexible substrate.3. The multi-level cell thin-film transistor memory according to claim 2 ,wherein a resistivity ...

Metal halide solid-state surface treatment for nanocrystal materials

Methods of treating nanocrystal and/or quantum dot devices are described. The methods include contacting the nanocrystals and/or quantum dots with a solution including metal ions and halogen ions, such that the solution displaces native ligands present on the surface of the nanocrystals and/or quantum dots via ligand exchange.

OXIDE SINTERED BODY, SPUTTERING TARGET, AND OXIDE SEMICONDUCTOR THIN FILM OBTAINED USING SPUTTERING TARGET

Provided is an oxide sintered body that, when used to obtain an oxide semiconductor thin film by sputtering, can achieve a low carrier concentration and a high carrier mobility. Also provided is a sputtering target using the oxide sintered body. The oxide sintered body contains, as oxides, indium, gallium, and at least one positive divalent element selected from the group consisting of nickel, cobalt, calcium, strontium, and lead. The gallium content, in terms of the atomic ratio Ga/(In+Ga), is from 0.20 to 0.45, and the positive divalent element content, in terms of the atomic ratio M/(In+Ga+M), is from 0.0001 to 0.05. The amorphous oxide semiconductor thin film, which is formed using the oxide sintered body as a sputtering target, can achieve a carrier concentration of less than 3.0×10cmand a carrier mobility of at least 10 cmVsec. 1. An oxide sintered body comprising indium , gallium , and a positive divalent element as oxides , whereina gallium content is 0.20 or more and 0.45 or less in terms of Ga/(In+Ga) atomic ratio,the total content of all the positive divalent elements is 0.0001 or more and 0.05 or less in terms of M/(In+Ga+M) atomic ratio,the positive divalent element is one or more selected from the group consisting of nickel, cobalt, calcium, strontium, and lead,the oxide sintered body includes;{'sub': 2', '3, 'an InOphase having a bixbyite-type structure;'}{'sub': 3', '2', '3', '2', '3', '3', '2', '3', '2', '3', '2', '3, 'and a GaInOphase having a β-GaO-type structure as a formed phase other than the InOphase, or a GaInOphase having a β-GaO-type structure and a (Ga, In)Ophase as a formed phase other than the InOphase;'}{'sub': 2', '4', '2', '4', '4', '7', '5', '6', '14', '12', '19', '2', '4', '3', '2', '6', '2', '4, 'and the oxide sintered body is substantially free of a NiGaOphase, a CoGaOphase, a CaGaOphase, a CaGaOphase, a SrGaOphase, a SrGaOphase, a SrGaOphase, and a GaPbOphase, which are a complex oxide composed of the positive divalent element ...

THIN FILM TRANSISTOR SUBSTRATE, METHOD OF MANUFACTURING THE SAME, AND DISPLAY APPARATUS HAVING THE SAME

A thin film transistor substrate includes a thin film transistor including a gate electrode, a semiconductor layer, a source electrode and a drain electrode. Each of the source electrode and the drain electrode includes a wire layer and a protective layer. The protective layer includes zinc oxide in an amount greater than about 70% by weight and less than about 85% by weight and indium oxide in an amount greater than about 15% by weight and less than about 30% by weight. 1. A thin film transistor substrate comprising:a base substrate; and a gate electrode on the base substrate;', 'a semiconductor layer on the gate electrode;', 'a source electrode overlapping the semiconductor layer; and', 'a drain electrode overlapping the semiconductor layer and spaced apart from the source electrode,', a wire layer comprising a metal; and', 'a protective layer on the wire layer,', 'wherein the protective layer comprises zinc oxide in an amount greater than about 70% by weight and less than about 85% by weight and indium oxide in an amount greater than about 15% by weight and less than about 30% by weight., 'each of the source electrode and the drain electrode comprising], 'a thin film transistor on the base substrate, the thin film transistor comprising2. The thin film transistor substrate of claim 1 , wherein the semiconductor layer comprises an oxide semiconductor.3. The thin film transistor substrate of claim 2 , wherein the metal comprises copper or a copper alloy.4. The thin film transistor substrate of claim 1 , wherein each of the source electrode and the drain electrode further comprises a barrier layer between the semiconductor layer and the wire layer claim 1 , the barrier layer blocking diffusion of a material included in the wire layer to the semiconductor layer.5. The thin film transistor substrate of claim 4 , wherein the barrier layer comprises at least one of indium-zinc-oxide claim 4 , gallium-zinc oxide and aluminum-zinc oxide.6. A display apparatus comprising:a ...

Deposition of Highly Crystalline 2D Materials

A method for providing a film of one or more monolayers of transition metal dichalcogenides on a substrate is disclosed. The method includes providing a substrate; depositing at least one monolayer of the transition metal dichalcogenides on the substrate; and selectively removing superficial islands on top of the at least one monolayer by thermal etching. 1. A method for providing a film of one or more monolayers of transition metal dichalcogenides on a substrate , the method comprising:providing a substrate;depositing at least one monolayer of the transition metal dichalcogenides on the substrate; andselectively removing superficial islands on top of the at least one monolayer by thermal etching.2. The method according to wherein the depositing and selectively removing steps are executed at least twice.3. The method according to claim 1 , wherein etchants used for the etching are selected from the group of Cl claim 1 , HCl claim 1 , and CO.4. The method according to claim 1 , wherein the transition metal dichalcogenides are deposited by metal-organic chemical vapor deposition.5. The method according to claim 1 , wherein the substrate is a sapphire substrate.6. The method according to claim 1 , wherein the transition metal dichalcogenide is MoS.7. The method according to claim 1 , wherein the depositing and selective removing steps are performed in a same reactor.8. The method according to claim 1 , wherein the selective removing step is performed at a temperature of at least 500° C.9. The method according to claim 1 , wherein:the substrate is a patterned substrate comprising a first material and a second material;{'b': '120', 'the at least one monolayer of the transition metal dichalcogenides is deposited () on the patterned substrate and the first and second materials are selected such that the deposition is more inhibited on the second material than on the first material; and'}the thermal etching is such that nuclei of the transition metal dichalcogenides on the ...

Display device

A display device that is suitable for increasing in size is achieved. Three or more source lines are provided for each pixel column. Video signals having the same polarity are input to adjacent source lines during one frame period. Dot inversion driving is used to reduce a flicker, crosstalk, or the like.

Nanopore Structure, Ionic Device Using Nanopore Structure and Method of Manufacturing Nanomembrane Structure

A nanopore structure includes an insulating support member including at least one of silicon and a compound containing silicon and in which a micropore that penetrates one side and the other side is formed in a central portion. The nanopore structure also includes a nanopore film including silicon nitride (SiN), disposed on the insulating support member, and in which a nanopore having a size smaller than that of the micropore is formed in a central portion in order to communicate with the micropore. The nanopore film and the insulating support member are attached by a hydrophilic surface processing. 1. A nanopore structure , comprising:an insulating support member comprising at least one of silicon and a compound containing silicon and in which a micropore that penetrates one side and the other side is formed in a central portion; anda nanopore film comprising silicon nitride (SiN), disposed on the insulating support member, and in which a nanopore having a size smaller than that of the micropore is formed in a central portion in order to communicate with the micropore,wherein the nanopore film and the insulating support member are attached by a hydrophilic surface processing.2. The nanopore structure of claim 1 , wherein the nanopore film and the insulating support member are attached under water.3. The nanopore structure of claim 2 , wherein the insulating support member comprises at least one of silicon (Si) claim 2 , silicon oxide (SiO2) claim 2 , silicon nitride (SiN) claim 2 , and polydimethylsiloxane (PDMS).4. The nanopore structure of claim 3 , wherein the insulating support member comprises a silicon oxide substrate and an amorphous silicon layer formed on the silicon oxide substrate claim 3 , andthe nanopore film and the amorphous silicon layer are attached.5. (canceled)6. An ion device using a nanopore claim 3 , the ion device comprising:a chamber comprising a first area and a second area;a first electrode located at the first area;a second electrode ...

Low vapor pressure aerosol-assisted cvd

Systems and methods for processing films on the surface of a substrate are described. The systems possess aerosol generators which form droplets from a condensed matter (liquid or solid) of one or more precursors. A carrier gas is flowed through the condensed matter and push the droplets toward a substrate placed in a substrate processing region. An inline pump connected with the aerosol generator can also be used to push the droplets towards the substrate. A direct current (DC) electric field is applied between two conducting plates configured to pass the droplets in-between. The size of the droplets is desirably reduced by application of the DC electric field. After passing through the DC electric field, the droplets pass into the substrate processing region and chemically react with the substrate to deposit or etch films.

Groove Design for Retaining Ring

An embodiment includes an annular ring having an intended direction of rotation, the ring having a top side and a bottom side, and further having an outer perimeter and an inner perimeter, and a multitude of grooves in the bottom side of the ring, each groove having an entry point at the outer perimeter connected to an exit point at the inner perimeter creating an opening through the ring, and each groove oriented so that an angle of each groove is obtuse, wherein the angle of each groove is defined as an angle between a first ray having an initial point at the entry point and having a direction along the groove towards the exit point, and a second ray having an initial point at the entry point and having a direction tangent to the annular ring at the entry point and opposite the intended direction of rotation. 1. A retaining ring comprising:an annular ring having an intended direction of rotation, the ring having a top side and a bottom side, and the annular ring further having an outer perimeter and an inner perimeter; and a first ray having an initial point at the entry point and having a direction along the groove towards the exit point; and', 'a second ray having an initial point at the entry point and having a direction tangent to the annular ring at the entry point and opposite the intended direction of rotation., 'a multitude of grooves in the bottom side of the ring, each groove having an entry point at the outer perimeter connected to an exit point at the inner perimeter creating an opening through the annular ring, and each groove further oriented so that an angle of each groove is obtuse, wherein the angle of each groove is defined as an angle between2. The retaining ring of claim 1 , wherein the grooves do not penetrate the top side of the annular ring.3. The retaining ring of claim 1 , wherein each groove has a depth of about 3 mm.4. The retaining ring of claim 1 , wherein the angle of each groove is about 135 degrees.5. The retaining ring of claim 1 , ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND DISPLAY UNIT AND ELECTRONIC APPARATUS

Provided is a semiconductor device, including a transistor in which an oxide semiconductor film, a gate insulating film, and a gate electrode are stacked in order, in which the oxide semiconductor film includes a first region portion and a second region portion. The oxide semiconductor film includes indium (In), zinc (Zn), and one or more of tin (Sn), gallium (Ga), and aluminum (Al). The first region portion is located, in a thickwise direction, in vicinity of an interface between the oxide semiconductor film and the gate insulating film, in the oxide semiconductor film. A composition ratio of the one or more of tin, gallium, and aluminum in the first region portion is higher than a composition ratio of the one or more of tin, gallium, and aluminum in the second region portion. 1. A semiconductor device , comprising a transistor in which an oxide semiconductor film , a gate insulating film , and a gate electrode are stacked in order , the oxide semiconductor film including a first region portion and a second region portion ,wherein the oxide semiconductor film includes indium (In), zinc (Zn), and one or more of tin (Sn), gallium (Ga), and aluminum (Al),the first region portion is located, in a thickwise direction, in vicinity of an interface between the oxide semiconductor film and the gate insulating film, in the oxide semiconductor film, anda composition ratio of the one or more of tin, gallium, and aluminum in the first region portion is higher than a composition ratio of the one or more of tin, gallium, and aluminum in the second region portion.2. The semiconductor device according to claim 1 ,wherein the oxide semiconductor film includes a channel region that forms the interface between the oxide semiconductor film and the gate insulating film, andthe first region portion extends over the channel region in an in-plane direction.3. The semiconductor device according to claim 1 ,wherein the oxide semiconductor film includes a channel region that forms the ...

SEMICONDUCTOR DEVICE STRUCTURE WITH GATE SPACER HAVING PROTRUDING BOTTOM PORTION AND METHOD FOR FORMING THE SAME

A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on the sidewall of the gate stack structure, and the gate spacers include a top portion and a bottom portion adjoined to the top portion, and the bottom portion slopes to a top surface of the substrate. The semiconductor device structure further includes an epitaxial structure formed adjacent to the gate spacers, and the epitaxial structure is formed below the gate spacers. 1. A semiconductor device structure , comprising:a first gate stack structure and a second gate stack structure formed on a substrate;first gate spacers formed on sidewalls of the first gate stack structure, wherein the first gate spacers comprise a top portion and a protruding bottom portion directly below the top portion, the top portion and the protruding bottom portion form a recessed corner at a joint of the top portion and the protruding bottom portion, the recessed corner is lower than a top of a gate dielectric layer of the first gate stack structure, and the protruding bottom portion slopes to a top surface of the substrate; andsecond gate spacers formed on sidewalls of the second gate stack structure, wherein the second gate spacers wherein the second gate spacers have a substantially constant thickness along a gate electrode and gate dielectric layer of the second gate stack structure.2. The semiconductor device structure of claim 1 , wherein the first gate spacers and the second gate spacers include a same composition of dielectric material.3. The semiconductor device structure of claim 1 , wherein the top portion of the first gate spacers has a first outer surface claim 1 , the protruding bottom portion of the first gate spacers has a second outer surface claim 1 , an angle between the first outer surface and the second outer ...

Thin-film transistor substrate, liquid crystal display device including the same, and method for producing thin-film transistor substrate

The present invention provides a thin-film transistor substrate including a base substrate and a thin-film transistor, the thin-film transistor including: a gate electrode; a gate insulating layer; a source electrode and a drain electrode; and an oxide semiconductor layer in this order. The source electrode and the drain electrode each include a first conductive layer and a second conductive layer covering the first conductive layer. The second conductive layer contains at least one element selected from the group consisting of molybdenum, tantalum, tungsten, and nickel. The gate insulating layer in a region between the source electrode and the drain electrode has a smaller thickness than in a region below the source electrode and in a region below the drain electrode.

Semiconductor device and method for manufacturing semiconductor device

A semiconductor device including a first oxide including a first region and a second region adjacent to each other and a third region and a fourth region with the first region and the second region sandwiched between the third region and the fourth region, a second oxide over the first region, a first insulator over the second oxide, a first conductor over the first insulator, a second insulator over the second oxide and on side surfaces of the first insulator and the first conductor, a third insulator over the second region and on a side surface of the second insulator, a second conductor over the second region with the third insulator positioned between the second region and the second conductor and on the side surface of the second insulator with the third insulator positioned between the side surface of the second insulator and the second conductor, and a fourth insulator covering the first oxide, the second oxide, the first insulator, the first conductor, the second insulator, the third insulator, and the second conductor and in contact with the third region and the fourth region.

Remote Plasma System and Method

A system and method for generating and using plasma is provided. An embodiment comprises a plasma generating unit that comprises beta-phase aluminum oxide. A precursor material is introduced to the plasma generating unit and a plasma is induced from the precursor material. The plasma may be used to deposit or etch materials on a semiconductor substrate. 1. A method of manufacturing semiconductor devices , the method comprising:introducing a first precursor material into a plasma generation unit, the plasma generation unit comprising beta-phase aluminum oxide;inducing a plasma from the first precursor material; andintroducing the plasma to a semiconductor manufacturing chamber.2. The method of claim 1 , wherein the introducing the plasma to the semiconductor manufacturing chamber further comprises introducing the plasma to a showerhead within the semiconductor manufacturing chamber.3. The method of claim 2 , further comprising introducing a second precursor material to the showerhead at a same time as the plasma.4. The method of claim 3 , further comprising depositing a layer of material onto a substrate using the plasma and the second precursor material.5. The method of claim 1 , further comprising etching a substrate utilizing the plasma.6. The method of claim 1 , further comprising depositing silicon nitride onto a substrate utilizing the plasma.7. A method of manufacturing a semiconductor device claim 1 , the method comprising:introducing a first material into an inlet port of a plasma generation unit, wherein the inlet port is connected to a housing, the housing comprising beta-phase aluminum oxide;applying a voltage pulse to induce the generation of a first plasma from the first material within the housing; andintroducing the first plasma to a semiconductor process chamber through an outlet port of the plasma generation unit.8. The method of claim 7 , wherein the voltage pulse is applied to a first part of a transformer.9. The method of claim 7 , wherein the ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film. Next, in order to further reduce impurities such as moisture or hydrogen in the oxide semiconductor film, oxygen is added to the oxide semiconductor film by an ion implantation method, an ion doping method, or the like, and after that, second heat treatment is performed on the exposed oxide semiconductor film. 1. (canceled)2. A method for manufacturing a semiconductor device , comprising the steps of:forming an oxide semiconductor layer comprising indium over a substrate, wherein the oxide semiconductor layer comprises a crystal region;forming a source electrode and a drain electrode over and in contact with the oxide semiconductor layer, wherein part of the oxide semiconductor layer is not covered by the source electrode and the drain electrode; andremoving an upper surface region and side surface regions of the oxide semiconductor layer at the uncovered part of the oxide semiconductor layer,wherein the crystal region has a c-axis orientation.3. The method according to claim 2 , further comprising the steps of:adding oxygen into the oxide semiconductor layer; andperforming a second heat treatment on the oxide semiconductor layer after adding oxygen.4. The method according to claim 2 , further comprising the step of heating the oxide semiconductor layer claim 2 , wherein a concentration of the oxide semiconductor layer is less than or equal to 5×10/cmafter heating the oxide semiconductor layer.5. The method according to claim 2 , wherein the crystal region has a c-axis which is aligned in a direction substantially perpendicular to a top surface of the oxide semiconductor layer.6. The method according to claim 2 , wherein the ...

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

An interlayer insulating film is formed. Then a first gate electrode and a second gate electrode are buried in the interlayer insulating film. Then, an anti-diffusion film is formed over the interlayer insulating film, over the first gate electrode, and over the second gate electrode. Then, a first semiconductor layer is formed over the anti-diffusion film which is present over the first gate electrode. Then, an insulating cover film is formed over the upper surface and on the lateral side of the first semiconductor layer and over the anti-diffusion film. Then, a semiconductor film is formed over the insulating cover film. Then, the semiconductor film is removed selectively to leave a portion positioned over the second gate electrode, thereby forming a second semiconductor layer. 1. A method of manufacturing a semiconductor device comprising steps of:forming a first interlayer insulating film;burying a first gate electrode and a second gate electrode in the first interlayer insulating film;forming a first gate insulating film and a first semiconductor layer over the first gate electrode;forming an insulating cover film over an upper surface and on a lateral side of the first semiconductor layer;forming a second semiconductor layer over the insulating cover film and over the second gate electrode; andselectively removing the semiconductor layer thereby leaving a portion of the second semiconductor layer that is positioned over the second gate electrode.2. A method of manufacturing a semiconductor device including a first MISFET and a second MISFET , comprising steps of:(a) forming a first interlayer insulating film over the first insulating film;(b) burying a first gate electrode of the first MISFET and a second gate electrode of the second MISFET in the first interlayer insulating film;(c) forming a first insulating film over the first gate electrode, the second electrode and the first interlayer insulating film;(d) forming a first semiconductor layer over the first ...

FIELD EFFECT TRANSISTORS WITH A GATED OXIDE SEMICONDUCTOR SOURCE/DRAIN SPACER

FETs including a gated oxide semiconductor spacer interfacing with a channel semiconductor. Transistors may incorporate a non-oxide channel semiconductor, and one or more oxide semiconductors disposed proximal to the transistor gate electrode and the source/drain semiconductor, or source/drain contact metal. In advantageous embodiments, the oxide semiconductor is to be gated by a voltage applied to the gate electrode (i.e., gate voltage) so as to switch the oxide semiconductor between insulating and semiconducting states in conjunction with gating the transistor's non-oxide channel semiconductor between on and off states. 124-. (canceled)25. A transistor comprising:a source region and a drain region separated by a channel region comprising a semiconductor material;a gate stack over the channel region, the gate stack comprising a gate dielectric layer and at least one gate electrode layer; anda spacer adjacent to a side of the gate stack, the spacer comprising an oxide semiconductor.26. The transistor of claim 25 , further comprisinga contact metallization disposed on the source and drain region; andwherein the oxide semiconductor is disposed between the gate electrode and at least one of the source region, drain region, or contact metallization.27. The transistor of claim 25 , wherein:the oxide semiconductor has a charge carrier density that varies as a function of a voltage on the gate electrode.28. The transistor of claim 27 , wherein the charge carrier density is sufficient to convey a current between the channel semiconductor and at least one of the source and drain regions when the voltage on the gate electrode is sufficient to induce inversion in at least a portion of the channel region.29. The transistor of claim 25 , wherein the oxide semiconductor has a conductivity type thatis the same as that of the source region and drain region.30. The transistor of claim 29 , wherein:the source region and drain region have n-type conductivity type; andthe oxide ...