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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 170184. Отображено 100.
05-01-2012 дата публикации

Copper interconnection structure and method for forming copper interconnections

Номер: US20120003390A1
Автор: Akihiro Shibatomi, Junichi Koike
Принадлежит: Advanced Interconnect Materials LLC

A copper interconnection structure includes an insulating layer, an interconnection body including copper in an opening provided on the insulating layer, and a diffusion barrier layer formed between the insulating layer and the interconnection body. The diffusion barrier layer includes an oxide layer including manganese having a compositional ratio of oxygen to manganese (y/x) less than 2.

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Номер записи: 1
05-01-2012 дата публикации

Wafer dividing method

Номер: US20120003816A1
Автор: Hisaki Ikebata, Kazuya Miyazaki, Makoto Shimotani
Принадлежит: Disco Corp

A method of dividing a wafer having devices formed in a plurality of regions demarcated by a plurality of streets formed in a grid pattern on a surface of the wafer, along the streets and into the individual devices. The wafer dividing method includes the steps of: forming grooves from the face side of the wafer along the streets and in a depth corresponding to the finished thickness of the devices; coating the surface of the wafer with an acrylic liquid resin curable by irradiation with UV rays to fill the grooves with the acrylic liquid resin and disposing a protective film on the acrylic liquid resin; performing irradiation with UV rays from the protective film side so as to cure the acrylic liquid resin; grinding the back side of the wafer so as to expose the grooves on the back side and divide the wafer into the individual devices; adhering the back side of the wafer to a surface of an adhesive tape adhered to an annular frame; and peeling the acrylic resin from the surface of the wafer together with the protective film.

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Номер записи: 2
12-01-2012 дата публикации

Method and apparatus for removing photoresist

Номер: US20120006486A1
Автор: Jaroslaw W. Winniczek, Robert P. Chebi
Принадлежит: Lam Research Corp

A method and apparatus remove photoresist from a wafer. A process gas containing sulfur (S), oxygen (O), and hydrogen (H) is provided, and a plasma is generated from the process gas in a first chamber. A radical-rich ion-poor reaction medium is flown from the first chamber to a second chamber where the wafer is placed. The patterned photoresist layer on the wafer is removed using the reaction medium, and then the reaction medium flowing into the second chamber is stopped. Water vapor may be introduced in a solvation zone provided in a passage of the reaction medium flowing down from the plasma such that the water vapor solvates the reaction medium to form solvated clusters of species before the reaction medium reaches the wafer. The photoresist is removed using the solvated reaction medium.

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Номер записи: 3
12-01-2012 дата публикации

Semiconductor device structures including damascene trenches with conductive structures and related method

Номер: US20120007209A1
Автор: Howard E. Rhodes
Принадлежит: Micron Technology Inc

A method and apparatus for providing a conductive structure adjacent to a damascene conductive structure in a semiconductor device structure. The semiconductor device structure includes an insulation layer with at least one damascene conductive structure formed therein, wherein the at least one damascene conductive structure includes an insulative, protective layer disposed thereon. The insulative material of the protective layer is able to resist removal by at least some suitable etchants for the insulative material of the insulation layer adjacent to the at least one damascene conductive structure. A self-aligned opening is formed by removing a portion of an insulation layer adjacent the at least one damascene conductive structure. The self-aligned opening is then filled with a conductive material to thereby provide another conductive structure adjacent to the at least one damascene conductive structure.

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Номер записи: 4
12-01-2012 дата публикации

Metal wire for a semiconductor device formed with a metal layer without voids therein and a method for forming the same

Номер: US20120007240A1
Автор: Baek Mann Kim, Dong Ha JUNG, Jeong Tae Kim, Soo Hyun Kim, Sun Woo HWANG, Young Jin Lee
Принадлежит: Hynix Semiconductor Inc

A metal wiring of a semiconductor device includes a semiconductor substrate; an insulating layer provided with a damascene pattern formed over the semiconductor substrate; a diffusion barrier layer which contains a RuO 2 layer formed on a surface of the damascene pattern and an Al deposit-inhibiting layer formed on a portion of the RuO 2 layer in both-side upper portion of the damascene pattern; and a wiring metal layer including Al formed on the diffusion barrier layer by MOCVD method in order to fill the damascene pattern.

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Номер записи: 5
12-01-2012 дата публикации

Redistribution layers for microfeature workpieces, and associated systems and methods

Номер: US20120007256A1
Автор: David Pratt
Принадлежит: Micron Technology Inc

Redistribution layers for microfeature workpieces, and associated systems and methods are disclosed. One method for processing a microfeature workpiece system includes positioning a pre-formed redistribution layer as a unit proximate to and spaced apart from a microfeature workpiece having an operable microfeature device. The method can further include attaching the redistribution layer to the microfeature workpiece and electrically coupling the redistribution layer to the operable microfeature device.

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Номер записи: 6
12-01-2012 дата публикации

Semiconductor device with side-junction and method for fabricating the same

Номер: US20120007258A1
Автор: Bong-Seok Jeon, Jae-Geun Oh, Jin-Ku Lee, Mi-Ri Lee, Seung-Joon Jeon
Принадлежит: Hynix Semiconductor Inc

A method for fabricating a semiconductor device includes forming a plurality of bodies that are each isolated from another by a trench and each include a diffusion barrier region with a sidewall exposed to the trench, forming a doped layer gap-filling the trench, forming a sidewall junction at the exposed sidewall of the diffusion barrier region by annealing the doped layer, and forming a conductive line coupled with the sidewall junction to fill the trench.

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Номер записи: 7
19-01-2012 дата публикации

Vertical non-volatile memory device

Номер: US20120012920A1
Автор: Chang-Won Lee, Kyung-tae Jang, Seung-Mok Shin
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A vertical non-volatile memory device includes a semiconductor pattern disposed on a substrate; and a plurality of transistors of first through n-th layers that are stacked on a side of the semiconductor pattern at predetermined distances from each other, wherein the transistors are spaced apart and insulated from one another at the predetermined distances via air gap, where n is a natural number equal to or greater than 2.

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Номер записи: 8
19-01-2012 дата публикации

interconnection structure for n/p metal gates

Номер: US20120012937A1
Автор: Han-Guan Chew, Harry-Hak-Lay Chuang, Lee-Wee Teo, Ming Zhu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The disclosure relates to integrated circuit fabrication, and more particularly to an interconnection structure for N/P metal gates. An exemplary structure for an interconnection structure comprises a first gate electrode having a first portion of a first work-function metal layer under a first portion of a signal metal layer; and a second gate electrode having a second portion of the first work-function metal layer interposed between a second work-function metal layer and a second portion of the signal metal layer, wherein the second portion of the signal metal layer is over the second portion of the first work-function metal layer, wherein the second portion of the signal metal layer and the first portion of the signal metal layer are continuous, and wherein a maximum thickness of the second portion of the signal metal layer is less than a maximum thickness of the first portion of the signal metal layer.

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Номер записи: 9
19-01-2012 дата публикации

Conductive Sidewall for Microbumps

Номер: US20120012998A1
Автор: Arvind Chandrasekaran, Christine S. Hay-Riege, Shiqun Gu
Принадлежит: Qualcomm Inc

Electromigration in microbump connections causes voids in the microbumps, which reduces the lifetime of an integrated circuit containing the microbump. Electromigration lifetime may be increased in microbumps by forming a copper shell around the solder. The copper shell of one microbump contacts the copper shell of a second microbump to enclose the solder of the microbump connection. The copper shell allows higher current densities through the microbump. Thus, smaller microbumps may be manufactured on a smaller pitch without suffering failure from electromigration. Additionally, the copper shell reduces shorting or bridging between microbump connections on a substrate.

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Номер записи: 10
19-01-2012 дата публикации

Support structures for various apparatuses including opto-electrical apparatuses

Номер: US20120015163A1
Автор: Gang He, Melissa Archer, Thomas J. Gmitter
Принадлежит: Awbscqemgk Inc

Present embodiments generally relate to support structures for thin film components and methods for fabricating the support structures. In one embodiment, an apparatus comprises a device structure including portions of an electronic device; a support structure coupled to the device structure; wherein the support structure supplements features of the device structure and the support structure includes: a metal component coupled to the device structure; and a non-metal component coupled to the metal component. The support component can supplement structural and mechanical integrity of the device structure and functional operations of the device structure. In one embodiment, the metal component includes at least one layer of metal material and the non-metal component includes at least one layer of non metal material (e.g., polymeric material, etc.). The metal component can have greater stiffness characteristics with respect to the device structure and the non-metal component can have greater flexibility characteristics with respect to the metal layer component. The support structure can be configured to reflect light towards the device structure. The support structure can also be configured to conduct electricity from the device structure.

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Номер записи: 11
19-01-2012 дата публикации

Method of manufacturing non-volatile memory device

Номер: US20120015512A1
Автор: Choong-ho Lee, Dong-Uk Choi, Hee-Soo Kang, Suk-kang Sung
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A non-volatile memory device includes field insulating layer patterns on a substrate to define an active region of the substrate, upper portions of the field insulating layer patterns protruding above an upper surface of the substrate, a tunnel insulating layer on the active region, a charge trapping layer on the tunnel insulating layer, a blocking layer on the charge trapping layer, first insulating layers on upper surfaces of the field insulating layer patterns, and a word line structure on the blocking layer and first insulating layers.

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Номер записи: 12
26-01-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120018742A1
Автор: Masahiro Nishi
Принадлежит: Sumitomo Electric Device Innovations Inc

A semiconductor device includes a SiC substrate, a semiconductor layer formed on the SiC substrate, a via hole penetrating through the SiC substrate and the semiconductor layer, a Cu pad that is formed on the semiconductor layer and is in contact with the via hole, and a barrier layer covering an upper face and side faces of the Cu pad, and restrains Cu diffusion.

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Номер записи: 13
26-01-2012 дата публикации

Semiconductor-on-insulator (soi) structure with selectively placed sub-insulator layer void(s) and method of forming the soi structure

Номер: US20120018806A1
Автор: Richard Q. Williams, Robert R. Robison, Toshiharu Furukawa
Принадлежит: International Business Machines Corp

Disclosed is a semiconductor-on-insulator (SOI) structure having sub-insulator layer void(s) selectively placed in a substrate so that capacitance coupling between a first section of a semiconductor layer and the substrate will be less than capacitance coupling between a second section of the semiconductor layer and the substrate. The first section may contain a first device on an insulator layer and the second section may contain a second device on the insulator layer. Alternatively, the first and second sections may comprise different regions of the same device on an insulator layer. For example, in an SOI field effect transistor (FET), sub-insulator layer voids can be selectively placed in the substrate below the source, drain and/or body contact diffusion regions, but not below the channel region so that capacitance coupling between the these various diffusion regions and the substrate will be less than capacitance coupling between the channel region and the substrate. Also, disclosed is an associated method of forming such an SOI structure.

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Номер записи: 14
26-01-2012 дата публикации

Stack package and method for manufacturing the same

Номер: US20120018879A1
Автор: Cheol-Ho JOH, Eun-Hye DO, Hee-Min SHIN, Ji-Eun Kim, Kyu-Won Lee
Принадлежит: Hynix Semiconductor Inc

A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.

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Номер записи: 15
26-01-2012 дата публикации

Methods of forming semiconductor elements using micro-abrasive particle stream

Номер: US20120018893A1
Автор: Belgacem Haba, Craig Mitchell, Ilyas Mohammed, Piyush Savalia, Vage Oganesian
Принадлежит: TESSERA RESEARCH LLC

A method of fabricating a microelectronic unit includes providing a semiconductor element having a front surface and a rear surface remote from the front surface, forming at least one first opening extending from the rear surface partially through the semiconductor element towards the front surface by directing a jet of fine abrasive particles towards the semiconductor element, and forming at least one conductive contact and at least one conductive interconnect coupled thereto. The semiconductor element can include a plurality of active semiconductor devices therein. The semiconductor element can include a plurality of conductive pads exposed at the front surface. Each conductive interconnect can extend within one or more of the first openings and can be coupled directly or indirectly to at least one of the conductive pads. Each of the conductive contacts can be exposed at the rear surface of the semiconductor element for electrical connection to an external device.

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Номер записи: 16
26-01-2012 дата публикации

Plasma processing method and storage medium

Номер: US20120021538A1
Автор: Kazuya Dobashi, Sung Tae Lee
Принадлежит: Tokyo Electron Ltd

There is provided a plasma processing method performing a plasma etching process on an oxide film of a target substrate through one or more steps by using a processing gas including a CF-based gas and a COS gas. The plasma processing method includes: performing a plasma etching process on the oxide film of the target substrate according to a processing recipe; measuring a concentration of sulfur (S) remaining on the target substrate (residual S concentration) after the plasma etching process is performed according to the processing recipe; adjusting a ratio of a COS gas flow rate with respect to a CF-based gas flow rate (COS/CF ratio) so as to allow the residual S concentration to become equal to or smaller than a predetermined value; and performing an actual plasma etching process according to a modified processing recipe storing the adjusted COS/CF ratio.

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Номер записи: 17
26-01-2012 дата публикации

Methods Of Forming An Array Of Memory Cells, Methods Of Forming A Plurality Of Field Effect Transistors, Methods Of Forming Source/Drain Regions And Isolation Trenches, And Methods Of Forming A Series Of Spaced Trenches Into A Substrate

Номер: US20120021573A1
Автор: Neal L. Davis, Ranjan Khurana, Richard Housley
Принадлежит: Micron Technology Inc

A method of forming a series of spaced trenches into a substrate includes forming a plurality of spaced lines over a substrate. Anisotropically etched sidewall spacers are formed on opposing sides of the spaced lines. Individual of the lines have greater maximum width than minimum width of space between immediately adjacent of the spacers between immediately adjacent of the lines. The spaced lines are removed to form a series of alternating first and second mask openings between the spacers. The first mask openings are located where the spaced lines were located and are wider than the second mask openings. Alternating first and second trenches are simultaneously etched into the substrate through the alternating first and second mask openings, respectively, to form the first trenches to be wider and deeper within the substrate than are the second trenches. Other implementations and embodiments are disclosed.

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Номер записи: 18
02-02-2012 дата публикации

Composition for metal plating comprising suppressing agent for void free submicron feature filling

Номер: US20120024711A1
Автор: Alexandra Haag, Charlotte Emnet, Cornelia Roeger-Goepfert, Dieter Mayer, Roman Benedikt Raether
Принадлежит: BASF SE

A composition for filling submicrometer sized features having an aperture size of 30 nanometers or less comprising a source of copper ions, and at least one suppressing agent selected from compounds of formula (I) wherein the R1 radicals are each independently selected from a copolymer of ethylene oxide and at least one further C3 to C4 alkylene oxide, said copolymer being a random copolymer. the R2 radicals are each independently selected from R1 or alkyl. X and Y are spacer groups independently, and X for each repeating unit independently, selected from C1 to C6 alkylen and Z—(O—Z)m wherein the Z radicals are each independently selected from C2 to C6 alkylen, n is an integer equal to or greater than 0. m is an integer equal to or greater than 1.

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Номер записи: 19
02-02-2012 дата публикации

Process for electrodeposition of copper chip to chip, chip to wafer and wafer to wafer interconnects in through-silicon vias (tsv) with heated substrate and cooled electrolyte

Номер: US20120024713A1
Автор: Robert F. Preisser
Принадлежит: Individual

Process of electrodepositing a metal in a high aspect ratio via in a silicon substrate to form a through-silicon-via (TSV), utilizing an electrolytic bath including a redox mediator, in an electrolytic metal plating system including a chuck adapted to hold the silicon substrate and to heat the silicon substrate to a first temperature, a temperature control device to maintain temperature of the electrolytic bath at a second temperature, in which the first temperature is maintained in a range from about 30° C. to about 60° C. and the second temperature is maintained at a temperature (a) at least 5° C. lower than the first temperature and (b) in a range from about 15° C. to about 35° C.

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Номер записи: 20
02-02-2012 дата публикации

Soi substrate, method for manufacturing the same, and semiconductor device

Номер: US20120025274A1
Автор: Hideto Ohnuma, Tetsuya Kakehata, Yoichi Iikubo
Принадлежит: Semiconductor Energy Laboratory Co Ltd

An SOI substrate having an SOI layer that can be used in practical applications even when a substrate with low upper temperature limit, such as a glass substrate, is used, is provided. A semiconductor device using such an SOI substrate, is provided. In bonding a single-crystal semiconductor layer to a substrate having an insulating surface or an insulating substrate, a silicon oxide film formed using organic silane as a material on one or both surfaces that are to form a bond is used. According to the present invention, a substrate with an upper temperature limit of 700° C. or lower, such as a glass substrate, can be used, and an SOI layer that is strongly bonded to the substrate can be obtained. In other words, a single-crystal semiconductor layer can be formed over a large-area substrate that is longer than one meter on each side.

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Номер записи: 21
02-02-2012 дата публикации

Semiconductor device and method of manufacturing semiconductor device

Номер: US20120025290A1
Автор: Kazuhiko Takada
Принадлежит: Fujitsu Semiconductor Ltd

A conductive film having a first width in a first direction, an ONO film, and a control gate are formed above a tunnel gate insulating film. With the control gate as a mask, the conductive film is etched to form a floating gate. Then, an inter-layer insulating film is formed. A contact hole whose width in the first direction is larger than the first width is formed in the inter-layer insulating film. Then, sidewall spacer is formed on an inside wall of the contact hole.

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Номер записи: 22
02-02-2012 дата публикации

Method, apparatus, and design structure for silicon-on-insulator high-bandwidth circuitry with reduced charge layer

Номер: US20120025345A1
Автор: Alan B. Botula, Alvin J. Joseph, James A. Slinkman, Randy L. Wolf
Принадлежит: International Business Machines Corp

A method, integrated circuit and design structure includes a silicon substrate layer having trench structures and an ion impurity implant. An insulator layer is positioned on and contacts the silicon substrate layer. The insulator layer fills the trench structures. A circuitry layer is positioned on and contacts the buried insulator layer. The circuitry layer comprises groups of active circuits separated by passive structures. The trench structures are positioned between the groups of active circuits when the integrated circuit structure is viewed from the top view. Thus, the trench structures are below the passive structures and are not below the groups of circuits when the integrated circuit structure is viewed from the top view.

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Номер записи: 23
02-02-2012 дата публикации

Semiconductor device and method of manufacturing semiconductor device

Номер: US20120025395A1
Автор: Shinichi Chikaki, Takahiro Nakayama
Принадлежит: Renesas Electronics Corp, Ulvac Inc

A semiconductor device includes: a first porous layer that is formed over a substrate and includes a SiO 2 skeleton; a second porous layer that is formed immediately above the first porous layer and includes a SiO 2 skeleton; a via wiring that is provided in the first porous layer; and a trench wiring that is buried in the second porous layer. The first porous layer has a pore density x 1 of 40% or below and the second porous layer has a pore density x 2 of (x 1 +5) % or above.

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Номер записи: 24
02-02-2012 дата публикации

Film for flip chip type semiconductor back surface, dicing tape-integrated film for semiconductor back surface, process for producing semiconductor device, and flip chip type semiconductor device

Номер: US20120025400A1
Автор: Fumiteru Asai, Goji Shiga, Naohide Takamoto, Yusuke Komoto
Принадлежит: Nitto Denko Corp

The present invention relates to a film for flip chip type semiconductor back surface to be formed on a back surface of a semiconductor element flip chip-connected onto an adherend, in which the film for flip chip type semiconductor back surface before thermal curing has, at the thermal curing thereof, a volume contraction ratio within a range of 23° C. to 165° C. of 100 ppm/° C. to 400 ppm/° C.

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Номер записи: 25
02-02-2012 дата публикации

Composition for metal plating comprising suppressing agent for void free submicron feature filling

Номер: US20120027948A1
Автор: Alexandra Haag, Charlotte Emnet, Cornelia Roeger-Goepfert, Dieter Mayer, Roman Benedikt Raether
Принадлежит: BASF SE

A composition comprising a source of metal ions and at least one suppressing agent obtainable by reacting a) an amine compound comprising active amino functional groups with b) a mixture of ethylene oxide and at least one compound selected from C3 and C4 alkylene oxides, said suppressing agent having a molecular weight M w of 6000 g/mol or more.

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Номер записи: 26
02-02-2012 дата публикации

Film for flip chip type semiconductor back surface, process for producing strip film for semiconductor back surface, and flip chip type semiconductor device

Номер: US20120028050A1
Автор: Fumiteru Asai, Goji Shiga, Naohide Takamoto
Принадлежит: Nitto Denko Corp

The present invention relates to a film for flip chip type semiconductor back surface to be formed on a back surface of a semiconductor element flip chip-connected onto an adherend, the film for flip chip type semiconductor back surface having a ratio of A/B falling within a range of 1 to 8×10 3 (%/GPa), in which A is an elongation ratio (%) of the film for flip chip type semiconductor back surface at 23° C. before thermal curing and B is a tensile storage modulus (GPa) of the film for flip chip type semiconductor back surface at 23° C. before thermal curing.

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Номер записи: 27
02-02-2012 дата публикации

Method of Controlling Critical Dimensions of Trenches in a Metallization System of a Semiconductor Device During Etch of an Etch Stop Layer

Номер: US20120028376A1
Автор: Johann Steinmetz, Mohammed Radwan
Принадлежит: Globalfoundries Inc

When forming metal lines and vias in complex metallization systems of semiconductor devices, an additional control mechanism for adjusting the final critical dimension may be implemented in the last etch process for etching through the etch stop layer after having patterned the low-k dielectric material. To this end, the concentration of a polymerizing gas may be controlled in accordance with the initial critical dimension obtained after the lithography process, thereby efficiently re-adjusting the final critical dimension so as to be close to the desired target value.

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Номер записи: 28
02-02-2012 дата публикации

Semiconductor device and method of fabricating the same

Номер: US20120028460A1
Автор: Kazuyuki Higashi, Makoto Wada
Принадлежит: Toshiba Corp

A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a first conductive member formed on the semiconductor substrate; a first insulating film formed on the same layer as the first conductive member; a second conductive member formed so as to contact with a portion of an upper surface of the first conductive member; a second insulating film formed on the first insulating film so as to contact with a portion of the upper surface of the first conductive member, and including at least one type of element among elements contained in the first insulating film except Si; and an etching stopper film formed on the second insulating film so as to contact with a portion of a side surface of the second conductive member, and having an upper edge located below the upper surface of the second conductive member.

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Номер записи: 29
02-02-2012 дата публикации

Method of growing electrical conductors

Номер: US20120028474A1
Автор: Juhana Kostamo, Kai-Erik Elers, Pekka J. Soininen, Suvi Haukka
Принадлежит: ASM International NV

A method for forming a conductive thin film includes depositing a metal oxide thin film on a substrate by an atomic layer deposition (ALD) process. The method further includes at least partially reducing the metal oxide thin film by exposing the metal oxide thin film to a reducing agent, thereby forming a seed layer. In one arrangement, the reducing agent comprises one or more organic compounds that contain at least one functional group selected from the group consisting of —OH, —CHO, and —COOH. In another arrangement, the reducing agent comprises an electric current.

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Номер записи: 30
09-02-2012 дата публикации

Metal semiconductor alloy structure for low contact resistance

Номер: US20120032275A1
Автор: Balasubramanian S. Haran, Sivananda K. Kanakasabapathy
Принадлежит: International Business Machines Corp

Contact via holes are etched in a dielectric material layer overlying a semiconductor layer to expose the topmost surface of the semiconductor layer. The contact via holes are extended into the semiconductor material layer by continuing to etch the semiconductor layer so that a trench having semiconductor sidewalls is formed in the semiconductor material layer. A metal layer is deposited over the dielectric material layer and the sidewalls and bottom surface of the trench. Upon an anneal at an elevated temperature, a metal semiconductor alloy region is formed, which includes a top metal semiconductor alloy portion that includes a cavity therein and a bottom metal semiconductor alloy portion that underlies the cavity and including a horizontal portion. A metal contact via is formed within the cavity so that the top metal semiconductor alloy portion laterally surrounds a bottom portion of a bottom portion of the metal contact via.

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Номер записи: 31
09-02-2012 дата публикации

N-well/p-well strap structures

Номер: US20120032276A1
Автор: Andy Lee, Bradley Jensen, Dustin Do, Giles V. Powell, Swee Aun Lau, Thomas H. White, Wuu-Cherng Lin
Принадлежит: Altera Corp

Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.

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Номер записи: 32
09-02-2012 дата публикации

Method for fabrication of a semiconductor device and structure

Номер: US20120032294A1
Автор: Brian Cronquist, Deepak C. Sekar, Israel Beinglass, Jan Lodewijk de Jong, Zvi Or-Bach
Принадлежит: Monolithic 3D Inc

A semiconductor device comprising: a first single crystal silicon layer comprising first transistors, first alignment mark, and at least one metal layer overlying said first single crystal silicon layer, wherein said at least one metal layer comprises copper or aluminum more than other materials; a second layer overlying said at least one metal layer, said second layer comprising second transistors, second alignment mark, and a through via through said second layer, wherein said through via is a part of a connection path between said first transistors and said second transistors, wherein alignment of said through via is based on said first alignment mark and said second alignment mark and effected by a distance between said first alignment mark and said second alignment mark.

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Номер записи: 33
09-02-2012 дата публикации

Semiconductor device and method for producing such a device

Номер: US20120032295A1
Автор: Carsten Von Koblinski, Francisco Javier Santos Rodriguez, Friedrich Kroener
Принадлежит: INFINEON TECHNOLOGIES AG

A semiconductor device and method for producing such a device is disclosed. One embodiment provides a semiconductor functional wafer having a first and second main surface. Component production processes are performed for producing a component functional region at the first main surface, wherein the component production processes produce an end state that is stable up to at least a first temperature. A carrier substrate is fitted to the first main surface. Access openings are produced to the first main surface. At least one further component production process is performed for producing patterned component functional regions at the first main surface of the functional wafer in the access openings. The end state produced in this process is stable up to a second temperature, which is less than the first temperature.

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Номер записи: 34
09-02-2012 дата публикации

Semiconductor device, electronic apparatus, and method of manufacturing semiconductor device

Номер: US20120032298A1
Автор: Hideki Fujii, Kenji Furuya, Yuichi Miyagawa
Принадлежит: Renesas Electronics Corp

A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.

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Номер записи: 35
09-02-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120032323A1
Автор: Akihiro Osaki, Atsushi Ishii, Masahiko Fujisawa, Masahiro Matsumoto
Принадлежит: Renesas Electronics Corp

A preferred aim of the invention is to provide technique for improving reliability of semiconductor devices when using a low-dielectric-constant film having a lower dielectric constant than a silicon oxide film to a part of an interlayer insulating film. More specifically, to achieve the preferred aim, an interlayer insulating film IL 1 forming a first fine layer is formed of a middle-Young's-modulus film, and thus it is possible to separate an integrated high-Young's-modulus layer (a semiconductor substrate 1 S and a contact interlayer insulating film CIL) and an interlayer insulating film (a low-Young's-modulus film; a low-dielectric-constant film) IL 2 forming a second fine layer not to let them directly contact with each other, and stress can be diverged. As a result, film exfoliation of the interlayer insulating film IL 2 formed of a low-Young's-modulus film can be prevented and thus reliability of semiconductor devices can be improved.

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Номер записи: 36
09-02-2012 дата публикации

Semiconductor device

Номер: US20120032325A1
Автор: Osamu Miyata, Shingo Higuchi
Принадлежит: ROHM CO LTD

There is provided a semiconductor device with which stress can be prevented from locally concentrating on an external connecting terminal on a post and thus damages of the external connecting terminal can be prevented. The semiconductor device includes a semiconductor chip, a sealing resin layer stacked on a surface of the semiconductor chip, and the post which penetrates the sealing resin layer in a stacking direction of the semiconductor chip and the sealing resin layer, protrudes from the sealing resin layer, and has a periphery of the protruding portion opposedly in contact with a surface of the sealing resin layer in the stacking direction.

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Номер записи: 37
09-02-2012 дата публикации

Self-aligned permanent on-chip interconnect structure formed by pitch splitting

Номер: US20120032336A1
Автор: Qinghuang Lin
Принадлежит: International Business Machines Corp

A method of fabricating an interconnect structure is provided. The method includes forming a hybrid photo-patternable dielectric material atop a substrate. The hybrid photo-patternable dielectric material has dual-tone properties with a parabola like dissolution response to radiation. The hybrid photo-patternable dielectric material is then image-wise exposed to radiation such that a self-aligned pitch split pattern forms. A portion of the self-aligned split pattern is removed to provide a patterned hybrid photo-patternable dielectric material having at least one opening therein. The patterned hybrid photo-patternable dielectric material is then converted into a cured and patterned dielectric material having the at least one opening therein. The at least one opening within the cured and patterned dielectric material is then filed with at least an electrically conductive material. Also provided are a hybrid photo-patternable dielectric composition and an interconnect structure.

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Номер записи: 38
09-02-2012 дата публикации

Methods of fabricating semiconductor devices having various isolation regions

Номер: US20120034757A1
Автор: Eunkee Hong, Gil-heyun Choi, Ha-Young YI, Hong-Gun Kim, Jun-Won Lee, Yong-Soon Choi
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of fabricating a semiconductor device includes forming a first trench and a second trench in a semiconductor substrate, forming a first insulator to completely fill the first trench, the first insulator covering a bottom surface and lower sidewalls of the second trench and exposing upper sidewalls of the second trench, and forming a second insulator on the first insulator in the second trench.

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Номер записи: 39
09-02-2012 дата публикации

Apparatus for manufacturing a semiconductor device

Номер: US20120034779A1
Автор: Kazuhiro Kubota, Ryuichi Asako, Satoru Shimura, Seiichi Takayama
Принадлежит: Individual

In a semiconductor device manufacturing method, an etching mask ( 75 b ) having a predetermined opening pattern is formed on an etching target film ( 74 ) disposed on a target object. Then, an etching process is performed on the etching target film ( 74 ) through the opening pattern of the etching mask ( 75 b ) within a first process chamber, thereby forming a groove or hole ( 78 a ) in the etching target film. Then, the target object treated by the etching process is transferred from the first process chamber to a second process chamber, within a vacuum atmosphere. Then, a silylation process is performed on a side surface of the groove or hole ( 78 a ), which is an exposed portion of the etching target film ( 74 ), within the second process chamber.

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Номер записи: 40
16-02-2012 дата публикации

Method for molecular adhesion bonding at low pressure

Номер: US20120038027A1
Автор: Marcel Broekaart
Принадлежит: Soitec SA

The present invention relates to a method for molecular adhesion bonding between at least a first wafer and a second wafer involving aligning the first and second wafers, placing the first and second wafers in an environment having a first pressure (P 1 ) greater than a predetermined threshold pressure; bringing the first wafer and the second wafer into alignment and contact; and initiating the propagation of a bonding wave between the first and second wafer after the wafers are aligned and in contact by reducing the pressure within the environment to a second pressure (P 2 ) below the threshold pressure. The invention also relates to the three-dimensional composite structure that is obtained by the described method of adhesion bonding.

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Номер записи: 41
16-02-2012 дата публикации

Method to fabricate thin metal via interconnects on copper wires in mram devices

Номер: US20120040531A1
Автор: Guomin Mao
Принадлежит: MagIC Technologies Inc

A scheme for forming a thin metal interconnect is disclosed that minimizes etch residues and provides a wet clean treatment for via openings. A single layer interlayer dielectric (ILD), BARC, and photoresist layer are successively formed on a substrate having a copper layer that is coplanar with a dielectric layer. In one embodiment, the ILD is silicon nitride with 100 to 600 Angstrom thickness. After a via opening is formed in a photoresist layer above the copper layer, a first RIE process including BARC main etch and BARC over etch steps is performed. Then a second RIE step transfers the opening through the ILD to uncover the copper layer. Photoresist and BARC are stripped with oxygen plasma and a low DC bias. Wet cleaning may involve a first ST250 treatment, ultrasonic water treatment, and then a third ST250 treatment. A bottom electrode layer may be deposited in the via opening.

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Номер записи: 42
23-02-2012 дата публикации

Semiconductor device and method for forming the same

Номер: US20120043592A1
Автор: Chao Zhao, Huilong Zhu, Wenwu Wang
Принадлежит: Institute of Microelectronics of CAS

The present invention provides a semiconductor device. The semiconductor device comprises contact plugs that comprise a first contact plug formed by a first barrier layer arranged on the source and drain regions and a tungsten layer arranged on the first barrier layer; and second contact plugs comprising a second barrier layer arranged on both of the metal gate and the first contact plug and a conductive layer arranged on the second barrier layer. The conductivity of the conductive layer is higher than that of the tungsten layer. A method for forming the semiconductor device is also provided. The present invention provides the advantage of enhancing the reliability of the device when using the copper contact technique.

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Номер записи: 43
23-02-2012 дата публикации

Mechanisms for forming copper pillar bumps using patterned anodes

Номер: US20120043654A1
Автор: Chih-Wei Lin, Chung-Shi Liu, Ming-Da Cheng, Wen-Hsiung LU
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The mechanisms of preparing bump structures described by using patterned anodes may simplify bump-making process, reduce manufacturing cost, and improve thickness uniformity within die and across the wafer. In addition, the mechanisms described above allow forming bumps with different heights to allow bumps to be integrated with elements on a substrate with different heights. Bumps with different heights expand the application of copper post bumps to enable further chip integration.

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Номер записи: 44
23-02-2012 дата публикации

Interconnects with improved tddb

Номер: US20120043659A1
Автор: Jing Hui Li, Lawrence A. Clevenger, Wu Ping Liu
Принадлежит: GLOBALFOUNDRIES SINGAPORE PTE LTD, International Business Machines Corp

A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A first upper etch stop layer is formed on the dielectric layer. The first upper etch stop layer includes a first dielectric material. The dielectric layer and first upper etch stop layer are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The interconnect and first upper etch stop layer have coplanar top surfaces. A second upper etch stop layer is formed over the coplanar top surfaces. The second upper etch stop layer includes a second material having sufficient adhesion with the first material to reduce diffusion of the conductive material.

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Номер записи: 45
23-02-2012 дата публикации

Semiconductor device manufacturing method

Номер: US20120045882A1
Автор: Seiji Inumiya, Tomonori Aoyama
Принадлежит: Toshiba Corp

A semiconductor device manufacturing method includes: removing an insulating film on a semiconductor substrate by etching and subsequently oxidizing a surface of the semiconductor substrate by using a liquid oxidation agent without exposing this surface to an atmosphere, thereby forming a first insulating film containing an oxide of a constituent element of the semiconductor substrate on the surface of the semiconductor substrate; forming a second insulating film containing an aluminum oxide on the first insulating film; forming a third insulating film containing a rare earth oxide on the second insulating film; forming a high-k insulating film on the third insulating film; introducing nitrogen into the high-k insulating film to thereby make it a fourth insulating film; and conducting heat treatment to change the first through third insulating films into a insulating film made of a mixture containing aluminum, a rare earth element, the constituent element of the semiconductor substrate, and oxygen.

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Номер записи: 46
23-02-2012 дата публикации

Method of making interconnect structure

Номер: US20120045893A1
Автор: Heinrich Koerner
Принадлежит: Individual

One or more embodiments relate to a method of forming a semiconductor device having a substrate, comprising: providing a Si-containing layer; forming a barrier layer over the Si-containing layer, the barrier layer comprising a compound including a metallic element; forming a metallic nucleation_seed layer over the Si-containing layer, the nucleation_seed layer including the metallic element; and forming a metallic interconnect layer over the nucleation_seed layer, wherein the barrier layer and the nucleation_seed layer are formed without exposing the semiconductor device substrate to the ambient atmosphere.

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Номер записи: 47
01-03-2012 дата публикации

Electronic device, manufacturing method of electronic device, and sputtering target

Номер: US20120049183A1
Автор: Shunpei Yamazaki
Принадлежит: Semiconductor Energy Laboratory Co Ltd

A film formation is performed using a target in which a material which is volatilized more easily than gallium when heated at 400° C. to 700° C., such as zinc, is added to gallium oxide by a sputtering method with high mass-productivity which can be applied to a large-area substrate, such as a DC sputtering method or a pulsed DC sputtering method. This film is heated at 400° C. to 700° C., whereby the added material is segregated in the vicinity of a surface of the film. Another portion of the film has a decreased concentration of the added material and a sufficiently high insulating property; therefore, it can be used for a gate insulator of a semiconductor device, or the like.

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Номер записи: 48
01-03-2012 дата публикации

Vertical gated access transistor

Номер: US20120049246A1
Автор: Werner Juengling
Принадлежит: Micron Technology Inc

A method of forming an apparatus includes forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a substrate. At least one of the shallow trenches is positioned between two deep trenches. The shallow trenches and the deep trenches are parallel to each other. A layer of conductive material is deposited over the first region and a second region of the substrate. The layer of conductive material is etched to define lines separated by gaps over the first region of the substrate, and active device elements over the second region of the substrate. The second region of the substrate is masked and the lines are removed from the first region of the substrate. Elongate trenches are etched where the lines were removed while the second region of the substrate is masked.

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Номер записи: 49
01-03-2012 дата публикации

Semiconductor devices and method of manufacturing the same

Номер: US20120049267A1
Автор: Young Kyun Jung
Принадлежит: Hynix Semiconductor Inc

A semiconductor device includes a pipe channel layer formed over a substrate, a first vertical channel layer formed over the pipe channel layer to couple the pipe channel layer to a bit line, a second vertical channel layer formed over the pipe channel layer to couple the pipe channel layer to a source line, a multi-layer comprising a charge trap layer and formed to surround the first vertical channel layer, the second vertical channel layer, and the pipe channel layer, an insulating barrier layer formed to surround the multi-layer, a plurality of first conductive layers formed between the pipe channel layer and the bit line, wherein the first vertical channel layer passes through the first conductive layers, and a plurality of second conductive layers formed between the pipe channel layer and the source line, wherein the second vertical layer passes through the second conductive layers.

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Номер записи: 50
01-03-2012 дата публикации

Semiconductor chips and methods of forming the same

Номер: US20120049349A1
Автор: Donghyeon Jang, Ho-Jin Lee, Hogeon SONG, Jung-Hwan Kim, Minseung Yoon, SeYoung JEONG
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Provided is a semiconductor chip including a back side insulation structure. The semiconductor chip may include a semiconductor layer including an active surface and an inactive surface facing each other; the insulating layer includes a first surface adjacent to the inactive surface and a second surface facing the first surface. The insulating layer is disposed on the inactive surface of the semiconductor layer. A penetrating electrode fills a hole penetrating the semiconductor layer and the insulating layer. The through electrode comprises a protrusive portion protruding from the second surface of the insulating layer.

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Номер записи: 51
01-03-2012 дата публикации

Semiconductor Device and Semiconductor Process for Making the Same

Номер: US20120049358A1
Автор: Bin-Hong Cheng
Принадлежит: Advanced Semiconductor Engineering Inc

The present invention relates to a semiconductor device and a semiconductor process for making the same. The semiconductor device of the present invention includes a semiconductor substrate, at least one conductive via and at least one insulation ring. The semiconductor substrate has a first surface. The conductive via is disposed in the semiconductor substrate. Each conductive via has a conductor and an insulation wall disposed the peripheral of the conductor, and the conductive via is exposed on the first surface of the semiconductor substrate. The insulation ring is disposed the peripheral of the conductive via, and the depth of the insulation ring is smaller than that of the insulation wall. Since the insulation ring is disposed the peripheral of the conductive via, the insulation ring can protect the end of the conductive via from being damaged. Furthermore, the size of the insulation ring and the conductive via is larger than the conventional conductive via, the semiconductor device of the invention can utilize surface finish layer, RDL or UBM to easily connect the other semiconductor device.

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Номер записи: 52
01-03-2012 дата публикации

Interconnect Structure for Semiconductor Devices

Номер: US20120049371A1
Автор: Hui-Lin Chang, Hung Chun Tsai, Syun-Ming Jang, Yung-Cheng Lu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, a conductive layer is located within a dielectric layer and a top surface of the conductive layer has either a recess, a convex surface, or is planar. An alloy layer overlies the conductive layer and is a silicide alloy having a first material from the conductive layer and a second material of germanium, arsenic, tungsten, or gallium.

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Номер записи: 53
01-03-2012 дата публикации

Buffer Layer to Enhance Photo and/or Laser Sintering

Номер: US20120049384A1
Автор: Mohshi Yang, Peter B. Laxton, Zvi Yaniv
Принадлежит: Ishihara Chemical Co Ltd

Conductive lines are deposited on a substrate to produce traces for conducting electricity between electronic components. A patterned metal layer is formed on the substrate, and then a layer of material having a low thermal conductivity is coated over the patterned metal layer and the substrate. Vias are formed through the layer of material having the low thermal conductivity thereby exposing portions of the patterned metal layer. A film of conductive ink is then coated over the layer of material having the low thermal conductivity and into the vias to thereby coat the portions of the patterned metal layer, and then sintered. The film of conductive ink coated over the portion of the patterned metal layer does not absorb as much energy from the sintering as the film of conductive ink coated over the layer of material having the low thermal conductivity. The layer of material having the low thermal conductivity may be a polymer, such as polyimide.

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Номер записи: 54
01-03-2012 дата публикации

Method for fabricating semiconductor device

Номер: US20120052643A1
Автор: Baek-Mann Kim
Принадлежит: Individual

A method for fabricating a semiconductor device includes forming junction area for a bit line contact (BLC) and a junction area for a storage node contact (SNC) by performing ion implantation in a substrate having a buried gate; forming a first insulation pattern having an opening to expose the junction areas; forming a buffer layer to fill the openings; forming a second insulation pattern over the first insulation pattern after filling the openings, wherein the second insulation pattern has openings to expose the buffer layer in an area of the buffer layer that lies over the junction area for the SNC; and forming an SNC to fill the opening of the second insulation patterns.

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Номер записи: 55
01-03-2012 дата публикации

Methods of selectively forming a material

Номер: US20120052681A1
Автор: Eugene P. Marsh
Принадлежит: Micron Technology Inc

Methods for depositing a material, such as a metal or a transition metal oxide, using an ALD (atomic layer deposition) process and resulting structures are disclosed. Such methods include treating a surface of a semiconductor structure periodically throughout the ALD process to regenerate a blocking material or to coat a blocking material that enables selective deposition of the material on a surface of a substrate. The surface treatment may reactivate a surface of the substrate toward the blocking material, may restore the blocking material after degradation occurs during the ALD process, and/or may coat the blocking material to prevent further degradation during the ALD process. For example, the surface treatment may be applied after performing one or more ALD cycles. Accordingly, the presently disclosed methods enable in situ restoration of blocking materials in ALD process that are generally incompatible with the blocking material and also enables selective deposition in recessed structures.

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Номер записи: 56
01-03-2012 дата публикации

Cleaning solution and damascene process using the same

Номер: US20120052686A1
Автор: An-Chi Liu, Tien-Cheng Lan
Принадлежит: United Microelectronics Corp

A cleaning solution is provided. The cleaning solution includes a fluorine containing compound, an inorganic acid, a chelating agent containing a carboxylic group and water for balance. The content of the fluorine containing compound is 0.01-0.5 wt % of. The content of the inorganic acid is 1-5 wt %.

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Номер записи: 57
08-03-2012 дата публикации

Substrate processing method and system

Номер: US20120055401A1
Автор: Shigeki Tozawa
Принадлежит: Tokyo Electron Ltd

A substrate processing method includes a first step of subjecting a target substrate to a gas process within an atmosphere containing a fluorine-containing process gas, thereby forming a fluorine-containing reaction product on a surface of the target substrate. The method further includes a second step of subjecting the target substrate treated by the gas process to a heating process and a gas process within an atmosphere containing a reactive gas that reacts with fluorine.

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Номер записи: 58
08-03-2012 дата публикации

Pseudo buried layer and manufacturing method of the same, deep hole contact and bipolar transistor

Номер: US20120056247A1
Автор: Donghua Liu, Wensheng QIAN
Принадлежит: Individual

The present invention discloses a pseudo buried layer, a deep hole contact and a bipolar transistor, and also discloses a manufacturing method of a pseudo buried layer, including: etching a silicon substrate to form an active region and shallow trenches; sequentially implanting phosphorous ion and arsenic ion into the bottom of the shallow trenches to form phosphorus impurity regions and arsenic impurity regions; conducting thermal annealing to the phosphorus impurity regions and arsenic impurity regions. The implantation of the pseudo buried layer, adopting phosphorous with rapid thermal diffusion and arsenic with slow thermal diffusion, can improve the impurity concentration on the surface of the pseudo buried layers, reduce the sheet resistance of the pseudo buried layer, form a good ohmic contact between the pseudo buried layer and a deep hole and reduce the contact resistance, and improve the frequency characteristic and current output of triode devices.

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Номер записи: 59
08-03-2012 дата публикации

Method for producing bonded wafer

Номер: US20120058622A1
Автор: Makoto Kawai, Shoji Akiyama, Yuji Tobisaka
Принадлежит: Shin Etsu Chemical Co Ltd

When a thermal expansion coefficient of a handle substrate is higher than that of a donor substrate, delamination is provided without causing a crack in the substrates. A method for producing a bonded wafer, with at least the steps of: implanting ions into a donor substrate ( 3 ) from a surface thereof to form an ion-implanted interface ( 5 ); bonding a handle substrate ( 7 ) with a thermal expansion coefficient higher than that of the donor substrate ( 3 ) onto the ion-implanted surface of the donor substrate to provide bonded substrates, subjecting the bonded substrates to a heat treatment to provide an assembly ( 1 ), and delaminating the donor substrate ( 3 ) of the assembly ( 1 ) at the ion-implanted interface wherein the assembly ( 1 ) has been cooled to a temperature not greater than room temperature by a cooling apparatus ( 20 ), so that a donor film is transferred onto the handle substrate ( 7 ).

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Номер записи: 60
15-03-2012 дата публикации

Semiconductor chip, stacked chip semiconductor package including the same, and fabricating method thereof

Номер: US20120061834A1
Автор: Tae Min Kang
Принадлежит: Hynix Semiconductor Inc

A semiconductor chip includes a silicon wafer formed with a via hole, a metal wire disposed in the via hole, and a filler that exposes a part of an upper portion of the metal wire while filing the via hole.

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Номер записи: 61
15-03-2012 дата публикации

Contact formation method incorporating a preventative etch step for reducing interlayer dielectric material flake defects

Номер: US20120064714A1
Автор: Brian M. Czabaj, Jeffrey P. Gambino, Molly J. Leitch, Polina A. Razina, Thomas J. DUNBAR, Yoba Amoah
Принадлежит: International Business Machines Corp

Disclosed are embodiments of a contact formation technique that incorporates a preventative etch step to reduce interlayer dielectric material flaking (e.g., borophosphosilicate glass (BPSG) flaking) and, thereby to reduce surface defects. Specifically, contact openings, which extend through a dielectric layer to semiconductor devices in and/or on a center portion of a substrate, can be filled with a conductor layer deposited by chemical vapor deposition (CVD). Chemical mechanical polishing (CMP) of the conductor layer can be performed to complete the contact structures. However, before the CMP process is performed (e.g., either before the contact openings are ever formed or before the contact openings are filled), a preventative etch process can be performed to remove any dielectric material from above the edge portion of the substrate. Removing the dielectric material from above the edge portion of the substrate prior to CMP reduces the occurrence of surface defects caused by dielectric material flaking.

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Номер записи: 62
15-03-2012 дата публикации

Plasma etching apparatus, plasma etching method, and semiconductor device manufacturing method

Номер: US20120064726A1
Автор: Jun Hashimoto, Masaru Sasaki, Shota Yoshimura, Tetsuya Nishizuka, Toshihisa Nozawa, Toshihisa Ozu
Принадлежит: Tokyo Electron Ltd

There is provided a plasma etching apparatus provided for performing an etching in a desirable shape. The plasma etching apparatus includes a processing chamber 12 for performing a plasma process on a target substrate W; a gas supply unit 13 for supplying a plasma processing gas into the processing chamber 12; a supporting table positioned within the processing chamber 12 and configured to support the target substrate thereon; a microwave generator 15 for generating a microwave for plasma excitation; a plasma generation unit for generating plasma within the processing chamber 12 by using the generated microwave; a pressure control unit for controlling a pressure within the processing chamber 12; a bias power supply unit for supplying AC bias power to the supporting table 14; and a control unit for controlling the AC bias power by alternately repeating supply and stop of the AC bias power.

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Номер записи: 63
22-03-2012 дата публикации

Monolithic magnetic induction device

Номер: US20120068301A1
Автор: Johnny Kin On Sin, Ron Shu Yuen Hui, Rongxiang Wu
Принадлежит: Hong Kong University of Science and Technology HKUST

Providing for a monolithic magnetic induction device having low DC resistance and small surface area is described herein. By way of example, the magnetic induction device can comprise a substrate (e.g., a semiconductor substrate) having trenches formed in a bottom layer of the substrate, and holes formed in the substrate between the trenches and an upper layer of the substrate. Additionally, the magnetic induction device can comprise a conductive coil embedded or deposited within the trenches. The magnetic induction device can further comprise a set of conductive vias formed in the holes that electrically connect the bottom layer of the substrate with the upper layer. Further, one or more integrated circuit components, such as active devices, can be formed in the upper layer, at least in part above the conductive coil. The vias can be utilized to connect to integrated circuit components with the conductive coil, where suitable.

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Номер записи: 64
22-03-2012 дата публикации

Interconnect structure with a planar interface between a selective conductive cap and a dielectric cap layer

Номер: US20120068344A1
Автор: Elbert E. Huang, Griselda Bonilla, Lawrence A. Clevenger, Satyanarayana V. Nitta, Shom Ponoth
Принадлежит: International Business Machines Corp

A selective conductive cap is deposited on exposed metal surfaces of a metal line by electroless plating selective to exposed underlying dielectric surfaces of a metal interconnect structure. A dielectric material layer is deposited on the selective conductive cap and the exposed underlying dielectric layer without a preclean. The dielectric material layer is planarized to form a horizontal planar surface that is coplanar with a topmost surface of the selective conductive cap. A preclean is performed and a dielectric cap layer is deposited on the selective conductive cap and the planarized surface of the dielectric material layer. Because the interface including a surface damaged by the preclean is vertically offset from the topmost surface of the metal line, electromigration of the metal in the metal line along the interface is reduced or eliminated.

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Номер записи: 65
22-03-2012 дата публикации

Structure for nano-scale metallization and method for fabricating same

Номер: US20120068346A1
Автор: Charles W. Koburger, III, Chih-Chao Yang, David V. Horak, Elbert E. Huang, Shom Ponoth, Sivananda K. Kanakasabapathy
Принадлежит: International Business Machines Corp

A method for forming structure aligned with features underlying an opaque layer is provided for an interconnect structure, such as an integrated circuit. In one embodiment, the method includes forming an opaque layer over a first layer, the first layer having a surface topography that maps to at least one feature therein, wherein the opaque layer is formed such that the surface topography is visible over the opaque layer. A second feature is positioned and formed in the opaque layer by reference to such surface topography.

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Номер записи: 66
22-03-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120069530A1
Автор: Kazushige Kanda, Satoshi Inoue, Yuui Shimizu
Принадлежит: Toshiba Corp

According to one embodiment, a semiconductor device includes a stacked chip includes semiconductor chips which are stacked, the semiconductor chips comprises semiconductor substrates and through electrodes formed in the semiconductor substrates, respectively, the through electrodes being electrically connected, and deactivating circuits provided in the semiconductor chips, respectively, and configured to deactivate a failed semiconductor chip.

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Номер записи: 67
22-03-2012 дата публикации

Atomic layer deposition of a copper-containing seed layer

Номер: US20120070981A1
Автор: James M. Blackwell, John Plombon, Patricio Romero, Scott B. Clendenning
Принадлежит: Intel Corp

The present disclosure relates to the field of microelectronic device fabrication and, more particularly, to the formation of copper-containing seed layers for the fabrication of interconnects in integrated circuits. The copper-containing seed layers may be formed in an atomic layer deposition process with a copper pre-cursor and organometallic co-reagent.

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Номер записи: 68
22-03-2012 дата публикации

Semiconductor device having decreased contact resistance

Номер: US20120070987A1
Автор: David Wu, Donna Michael, MARK Michael, Zhonghai Shi
Принадлежит: Globalfoundries Inc

Semiconductor devices having improved contact resistance and methods for fabricating such semiconductor devices are provided. These semiconductor devices include a semiconductor device structure and a contact. The contact is electrically and physically coupled to the semiconductor device structure at both a surface portion and a sidewall portion of the semiconductor device structure.

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Номер записи: 69
29-03-2012 дата публикации

Methods for discretized processing and process sequence integration of regions of a substrate

Номер: US20120074096A1
Автор: Alexander Gorer, David E. Lazovsky, Thomas R. Boussie, Tony P. Chiang
Принадлежит: Individual

The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.

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Номер записи: 70
29-03-2012 дата публикации

Methods for Controlling Bevel Edge Etching in a Plasma Chamber

Номер: US20120074099A1
Автор: Andrew D. Bailey, III, George Stojakovic, Olivier Rigoutat, Tong Fang, Yunsang Kim
Принадлежит: Lam Research Corp

Methods for bevel edge etching are provided. One example method is for etching a film on a bevel edge of a substrate in a plasma etching chamber. The method includes providing the substrate on a substrate support in the plasma etching chamber. The plasma etching chamber has a top edge electrode and a bottom edge electrode disposed to surround the substrate support. Then flowing an etching process gas through a plurality of edge gas feeds disposed along a periphery of the gas delivery plate. The periphery of the gas deliver plate is oriented above the substrate support and the bevel edge of the substrate, and the flowing is further directed to a space between the top edge electrode and bottom edge electrode. And, flowing a tuning gas through a center gas feed of the gas delivery plate.

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Номер записи: 71
29-03-2012 дата публикации

Power Semiconductor Device Having Gate Electrode Coupling Portions for Etchant Control

Номер: US20120074472A1
Автор: Koichiro Sakanishi, Koji Fujishima, Tsuyoshi Kachi
Принадлежит: Renesas Electronics Corp

A general insulated gate power semiconductor active element with many gate electrodes arranged in parallel has a laminated structure including a barrier metal film and a thick aluminum electrode film formed over the gate electrodes via an interlayer insulating film. When the aluminum electrode film is embedded in between the gate electrodes in parallel, voids may be generated with the electrodes. Such voids allow the etchant to penetrate in wet etching, which may promote the etching up to a part of the electrode film in an active cell region which is to be left. Thus, an insulated gate power semiconductor device is provided to include gate electrodes protruding outward from the inside of the active cell region, and a gate electrode coupling portion for coupling the gate electrodes outside the active cell region. The gate electrode coupling portion is covered with a metal electrode covering the active cell region.

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Номер записи: 72
29-03-2012 дата публикации

Semiconductor package with through electrodes and method for manufacturing the same

Номер: US20120074529A1
Автор: Jin-Ho Bae, Ki-Young Kim, Myung-Geun PARK
Принадлежит: Hynix Semiconductor Inc

A semiconductor package may include a substrate with a first surface over which bond fingers are formed. At least two semiconductor chips may be stacked on the first surface of the substrate and each chip may have via holes. The semiconductor chips may be stacked such that the respective via holes expose the respective bond fingers of the substrate. Through electrodes may be formed in the via holes. The through electrodes may comprise carbon nanotubes grown from the exposed bond fingers of the substrate, where the through electrodes may be electrically connected with the semiconductor chips.

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Номер записи: 73
29-03-2012 дата публикации

Semiconductor structure and method for making same

Номер: US20120074572A1
Автор: Andreas STUECKJUERGEN, Juergen Foerster, Thomas Fischer, Werner Robl
Принадлежит: INFINEON TECHNOLOGIES AG

One or more embodiments relate to a method for making a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a separation layer over the barrier layer; forming a conductive layer over the separation layer; and wet etching the conductive layer.

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Номер записи: 74
29-03-2012 дата публикации

Semiconductor structure having a through substrate via (tsv) and method for forming

Номер: US20120074583A1
Автор: Thuy B. Dao
Принадлежит: Individual

A structure having a substrate includes an opening in the substrate having depth from a top surface of the substrate to a bottom surface of the substrate. A conductive material fills the opening. The opening has a length direction and a width direction and a first and second feature. The first feature and the second feature are spaced apart by a first length. The first feature has first width as a maximum width of the first feature, and the second feature has a second width as the maximum width of the second feature. The opening has a minimum width between the first feature and the second feature that is no more than one fifth the first length. The first width and the second width are each at least twice the minimum width.

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Номер записи: 75
29-03-2012 дата публикации

Manufacturing method of thin film semiconductor substrate

Номер: US20120077331A1
Автор: Takeshi Matsumoto, Toshiyuki Sameshima, Yuko Fujimoto, Yutaka Inouchi
Принадлежит: Nissin Ion Equipment Co Ltd, Tokyo University of Agriculture and Technology NUC

A manufacturing method of a thin film semiconductor substrate includes implanting ions at a specified depth into a semiconductor substrate, forming a bubble layer in the semiconductor substrate by vaporizing the ions through heating, bonding an insulating substrate onto the semiconductor substrate, and cleaving the semiconductor substrate along the bubble layer to form a semiconductor thin film on a side of the insulating substrate. At the forming, the semiconductor substrate is heated at a temperature in a temperature range of approximately 1000° C. to 1200° C. for a duration in a range of approximately 10 μs to 100 ms. The heating of the semiconductor substrate is performed by using, for example, a light beam.

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Номер записи: 76
29-03-2012 дата публикации

Method of and apparatus for active energy assist baking

Номер: US20120077339A1
Автор: Chia Cheng Chou, Chung-Chi Ko, Joung-Wei Liou, Keng-Chu Lin, Mei-Ling Chen, Shwang-Ming Jeng
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method of and apparatus for forming interconnects on a substrate includes etching patterns in ultra-low k dielectric and removing moisture from the ultra-low k dielectric using active energy assist baking. During active energy assist baking, the ultra-low k dielectric is heated and exposed to light having only wavelengths greater than 400 nm for about 1 to about 20 minutes at a temperature of about 300 to about 400 degrees Celsius. The active energy assist baking is performed after wet-cleaning or after chemical mechanical polishing, or both.

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Номер записи: 77
29-03-2012 дата публикации

Systems and methods for selective tungsten deposition in vias

Номер: US20120077342A1
Автор: Juwen Gao, Michal Danek, Rajkumar Jakkaraju, Wei Lei
Принадлежит: Novellus Systems Inc

A method for processing a substrate includes providing a substrate including a metal layer, a dielectric layer arranged on the metal layer, and at least one of a via and a trench formed in the dielectric layer; depositing a metal using chemical vapor deposition (CVD) during a first deposition period, wherein the first deposition period is longer than a first nucleation period that is required to deposit the metal on the metal layer; stopping the first deposition period prior to a second nucleation delay period, wherein the second nucleation period is required to deposit the metal on the dielectric layer; performing the depositing and the stopping N times, where N is an integer greater than or equal to one; and after the performing, depositing the metal using CVD during a second deposition period that is longer than the second nucleation delay period.

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Номер записи: 78
05-04-2012 дата публикации

Device

Номер: US20120080796A1
Автор: Makoto Wada, Yuichi Yamazaki
Принадлежит: Toshiba Corp

According to one embodiment, a device includes an insulating layer with a first trench, a first interconnect layer in the first trench, the first interconnect layer including copper and includes a concave portion, and a first graphene sheet on an inner surface of the concave portion.

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Номер записи: 79
05-04-2012 дата публикации

Off-chip vias in stacked chips

Номер: US20120080807A1
Автор: Belgacem Haba, David Ovrutsky, Ilyas Mohammed, Laura Wills Mirkarimi, Vage Oganesian
Принадлежит: Tessera LLC

A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements.

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Номер записи: 80
05-04-2012 дата публикации

Sapphire wafer dividing method

Номер: US20120083059A1
Автор: Hiroumi Ueno, Hitoshi Hoshino, Takashi Okamura, Yuji Nitta
Принадлежит: Disco Corp

A sapphire wafer dividing method including a cut groove forming step of forming a plurality of cut grooves on the back side of a sapphire wafer along a plurality of crossing division lines formed on the front side where a light emitting layer is formed, a modified layer forming step of forming a plurality of modified layers inside the sapphire wafer along the division lines, and a dividing step of dividing the sapphire wafer into individual light emitting devices along the modified layers as a division start point, thereby chamfering the corners of the back side of each light emitting device owing to the formation of the cut grooves in the cut groove forming step.

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Номер записи: 81
05-04-2012 дата публикации

Method for manufacturing a semiconductor device having an interconnect structure and a reinforcing insulating film

Номер: US20120083115A1
Автор: Tatsuya Usami
Принадлежит: Renesas Electronics Corp

A semiconductor device includes in an interconnect structure which includes a first interconnect made of a copper-containing metal, a first Cu silicide layer covering the upper portion of the first interconnect, a conductive first plug provided on the upper portion of the Cu silicide layer and connected to the first interconnect, a Cu silicide layer covering the upper portion of the first plug, a first porous MSQ film provided over the side wall from the first interconnect through the first plug and formed to cover the side wall of the first interconnect, the upper portion of the first interconnect, and the side wall of the first plug, and a first SiCN film disposed under the first porous MSQ film to contact with the lower portion of the side wall of the first interconnect and having the greater film density than the first porous MSQ film.

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Номер записи: 82
05-04-2012 дата публикации

Method Of Forming Hardened Porous Dielectric Layer And Method Of Fabricating Semiconductor Device Having Hardened Porous Dielectric Layer

Номер: US20120083117A1
Автор: Byung-hee Kim, Gil-heyun Choi, Jang-Hee Lee, Jong-min Baek, Kyoung-Hee Kim, Kyu-hee Han, Sang-don Nam, Sang-hoon Ahn
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Example embodiments relate to a method of forming a hardened porous dielectric layer. The method may include forming a dielectric layer containing porogens on a substrate, transforming the dielectric layer into a porous dielectric layer using a first UV curing process to remove the porogens from the dielectric layer, and transforming the porous dielectric layer into a crosslinked porous dielectric layer using a second UV curing process to generate crosslinks in the porous dielectric layer.

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Номер записи: 83
12-04-2012 дата публикации

Semiconductor device and method of forming the same

Номер: US20120086060A1
Автор: Koji Taniguchi
Принадлежит: Elpida Memory Inc

A semiconductor device includes a semiconductor substrate, a gate electrode, a dummy gate electrode, and a first impurity diffusion region. The semiconductor substrate has first and second grooves. The gate electrode is in the first groove. The dummy gate electrode is in the second groove. The dummy gate electrode has a first top surface. The first impurity diffusion region in the semiconductor substrate is positioned between the first and second grooves. The first top surface is positioned at a lower level than a bottom of the first impurity diffusion region.

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Номер записи: 84
12-04-2012 дата публикации

Package systems and manufacturing methods thereof

Номер: US20120086127A1
Автор: Chia-Pao SHU, Chun-Wen Cheng, Hsin-Ting HUANG, Jung-Huei Peng, Kuei-Sung CHANG, Shang-Ying Tsai
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A package system includes a first substrate. A second substrate is electrically coupled with the first substrate. At least one electrical bonding material is disposed between the first substrate and the second substrate. The at least one electrical bonding material includes a eutectic bonding material. The eutectic bonding material includes a metallic material and a semiconductor material. The metallic material is disposed adjacent to a surface of the first substrate. The metallic material includes a first pad and at least one first guard ring around the first pad.

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Номер записи: 85
12-04-2012 дата публикации

Method for molecular bonding of silicon and glass substrates

Номер: US20120088350A1
Автор: Daniel Delprat, Sebastien Kerdiles
Принадлежит: Soitec SA

The present invention concerns a method for bonding a first substrate having a first surface to a second substrate having a second surface. This method includes the steps of holding the first substrate by at least two support points, positioning the first substrate and the second substrate so that the first surface and the second surface face each other, deforming the first substrate by applying between at least one pressure point and the two support points a strain toward the second substrate, bringing the deformed first surface and the second surface into contact, and progressively releasing the strain to facilitate bonding of the substrates while minimizing or avoiding the trapping of air bubbles between the substrates.

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Номер записи: 86
12-04-2012 дата публикации

Technique for forming metal lines in a semiconductor by adapting the temperature dependence of the line resistance

Номер: US20120088365A1
Автор: Eckhard Langer, Matthias Lehr, Moritz Andreas Meyer
Принадлежит: Advanced Micro Devices Inc

By moderately introducing defects into a highly conductive material, such as copper, the resistance versus temperature behavior may be significantly modified so that enhanced electromigration behavior and/or electrical performance may be obtained in metallization structures of advanced semiconductor devices. The defect-related portion of the resistance may be moderately increased so as to change the slope of the resistance versus temperature curve, thereby allowing the incorporation of impurity atoms for enhancing the electromigration endurance while not unduly increasing the overall resistance at the operating temperature or even reducing the corresponding resistance at the specified operating temperature. Thus, by appropriately designing the electrical resistance for a target operating temperature, both the electromigration behavior and the electrical performance may be enhanced.

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Номер записи: 87
19-04-2012 дата публикации

Semiconductor device, method for forming the same, and data processing system

Номер: US20120091520A1
Автор: Nobuyuki Nakamura
Принадлежит: Elpida Memory Inc

A semiconductor device includes a semiconductor substrate, a first interlayer insulating film over the semiconductor substrate, a first interconnect over the first interlayer insulating film, and a via plug penetrating the semiconductor substrate and the first interlayer insulating film. The via plug is coupled to the first interconnect.

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Номер записи: 88
19-04-2012 дата публикации

Semiconductor component with marginal region

Номер: US20120091564A1
Автор: Anton Mauder, Hans-Joachim Schulze, Hans-Joerg Timme
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A semiconductor wafer is disclosed. One embodiment provides at least two semiconductor components each having an active region, and wherein at least one zone composed of porous material is arranged between the active regions of the semiconductor components.

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Номер записи: 89
19-04-2012 дата публикации

Method for manufacturing wiring, thin film transistor, light emitting device and liquid crystal display device, and droplet discharge apparatus for forming the same

Номер: US20120094412A1
Автор: Klyofumi Ogino, Osamu Nakamura
Принадлежит: Semiconductor Energy Laboratory Co Ltd

As a semiconductor device, specifically, a pixel portion included in a semiconductor device is made to have higher precision and higher aperture ratio, it is required to form a smaller wiring in width. In the case of forming a wiring by using an ink-jet method, a dot spreads on a wiring formation surface, and it is difficult to narrow width of a wiring. In the present invention, a photocatalytic substance typified by TiO 2 is formed on a wiring formation surface, and a wiring is formed by utilizing photocatalytic activity of the photocatalytic substance. According to the present invention, a narrower wiring, that is, a smaller wiring in width than a diameter of a dot formed by an ink-jet method can be formed.

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Номер записи: 90
19-04-2012 дата публикации

Pass-through 3d interconnect for microelectronic dies and associated systems and methods

Номер: US20120094443A1
Автор: David S. Pratt, Dewali Ray, Kyle K. Kirby
Принадлежит: Micron Technology Inc

Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a substrate, a metal substrate pad, and a first integrated circuit electrically coupled to the substrate pad. A pass-through 3D interconnect extends between front and back sides of the substrate, including through the substrate pad. The pass-through interconnect is electrically isolated from the substrate pad and electrically coupled to a second integrated circuit of a second microelectronic die attached to the back side of the substrate. In another embodiment, the first integrated circuit is a first memory device and the second integrated circuit is a second memory device, and the system uses the pass-through interconnect as part of an independent communication path to the second memory device.

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Номер записи: 91
19-04-2012 дата публикации

Two silicon-containing precursors for gapfill enhancing dielectric liner

Номер: US20120094468A1
Автор: Hiroshi Hamana, Paul Edward Gee, Shankar Venkataraman, Sidharth Bhatia
Принадлежит: Applied Materials Inc

Aspects of the disclosure pertain to methods of depositing silicon oxide layers on substrates. In embodiments, silicon oxide layers are deposited by flowing a silicon-containing precursor having a Si—O bond, an oxygen-containing precursor and a second silicon-containing precursor, having both a Si—C bond and a Si—N bond, into a semiconductor processing chamber to form a conformal liner layer. Upon completion of the liner layer, a gap fill layer is formed by flowing a silicon-containing precursor having a Si—O bond, an oxygen-containing precursor into the semiconductor processing chamber. The presence of the conformal liner layer improves the ability of the gap fill layer to grow more smoothly, fill trenches and produce a reduced quantity and/or size of voids within the silicon oxide filler material.

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Номер записи: 92
26-04-2012 дата публикации

Method for modifying the crystalline structure of a copper element

Номер: US20120097296A1
Автор: Léa Di Cioccio, Maurice Rivoire, Pierric Gueguen
Принадлежит: Commissariat a lEnergie Atomique et aux Energies Alternatives CEA

A method for modifying crystalline structure of a copper element with a planar surface, including: a) producing a copper standard having large grains, wherein the standard includes a planar surface, b) reducing roughness of the planar surfaces to a roughness of less than 1 nm, c) cleaning the planar surfaces, d) bringing the two planar surfaces into contact, and e) annealing.

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Номер записи: 93
26-04-2012 дата публикации

Contact-hole forming method

Номер: US20120097639A1
Автор: Kazuya Mitsudome
Принадлежит: Sharp Corp

A contact hole forming method according to the present invention includes a process (a) of forming an insulating film on a substrate and a process (b) of forming a contact hole in the insulating film by etching. Here, the process (a) includes steps of (a 1 ) placing the substrate between a pair of electrodes, (a 2 ) supplying a first reaction gas between the pair of electrodes having the substrate placed therebetween in the step (a 1 ), (a 3 ) raising an RF output supplied between the pair of electrodes to a prescribed set value after the step (a 2 ) so as to generate a plasma, and (a 4 ) supplying a second reaction gas that forms the insulating film after the step (a 3 ).

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Номер записи: 94
26-04-2012 дата публикации

Semiconductor component with isolation trench intersections

Номер: US20120098084A1
Автор: Ralf Lerner, Uwe Eckoldt
Принадлежит: Individual

A semiconductor component with straight insulation trenches formed in a semiconductor material providing semiconductor areas laterally insulated from each other. Each insulation trench has a uniform width along its longitudinal direction represented by a central line. The semiconductor component has an intersecting area into which at least three of the straight insulation trenches lead. A center of the intersecting area is defined as a point of intersection of the continuations of the center lines. A central semiconductor area disposed in the intersecting area is connected with one of the semiconductor areas and contains the center of the intersecting area.

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Номер записи: 95
26-04-2012 дата публикации

Chip package and manufacturing method thereof

Номер: US20120098109A1
Автор: Dongkyun Ko, Jaesun An, Jung Lee
Принадлежит: Individual

A chip package including a shielding layer having a plurality of conductive connectors for better electromagnetic interferences shielding is provided. The conductive connectors can be flexibly arranged within the molding compound for better shielding performance. The shielding layer having the conductive connectors functions as the EMI shield and the shielding layer is electrically grounded within the package structure.

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Номер записи: 96
26-04-2012 дата публикации

Conductive feature for semiconductor substrate and method of manufacture

Номер: US20120098121A1
Автор: Hsien-Wei Chen, Ying-Ju Chen
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A conductive feature on a semiconductor component is disclosed. A first passivation layer is formed over a substrate. A bond pad is formed over the first passivation layer. A second passivation layer overlies the first passivation layer and the bond pad. The second passivation layer has a first opening overlying the bond pad and a plurality of second openings exposing a top surface of the first passivation layer. A buffer layer overlies the second passivation layer and fills the plurality of second openings. The buffer layer has a third opening overlapping the first opening and together exposes a portion the bond pad. The combined first opening and third opening has sidewalls. An under bump metallurgy (UBM) layer overlies the sidewalls of the combined first opening and third opening, and contacts the exposed portion of the bond pad. A conductive feature overlies the UBM layer.

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Номер записи: 97
26-04-2012 дата публикации

Power/ground layout for chips

Номер: US20120098127A1
Автор: Albert Wu, Chuan-Cheng Cheng, Chung Chyung Han, Sehat Sutardja, Shuhua Yu, Weidan Li
Принадлежит: MARVELL WORLD TRADE LTD

Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.

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Номер записи: 98
26-04-2012 дата публикации

Chip structure and process for forming the same

Номер: US20120098128A1
Автор: Ching-Cheng Huang, Jin-Yuan Lee, Mou-Shiung Lin
Принадлежит: Megica Corp

A chip with a metallization structure and an insulating layer with first and second openings over first and second contact points of the metallization structure, a first circuit layer connecting the first and second contact points and comprising a first trace portion, first and second via portions between the first trace portion and the first and second contact points, the first circuit layer comprising a copper layer and a first conductive layer under the copper layer and at a sidewall of the first trace portion, and a second circuit layer comprising a second trace portion with a third via portion at a bottom thereof, wherein the second circuit layer comprises another copper layer and a second conductive layer under the other copper layer and at a sidewall of the second trace portion, and a second dielectric layer comprising a portion between the first and second circuit layers.

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Номер записи: 99
26-04-2012 дата публикации

Processes for fabricating heterostructures

Номер: US20120100691A1
Автор: Bruce Faure
Принадлежит: Soitec SA

The invention relates to a process for fabricating a heterostructure. This process comprises heating an intermediate heterostructure. The intermediate heterostructure comprises a crystalline strain relaxation layer interposed directly between a first substrate and a strained layer of crystalline semiconductor material. The process further comprises causing plastic deformation of the crystalline strain relaxation layer and elastic deformation of the strained layer of crystalline semiconductor material to at least partially relax the strained layer of crystalline semiconductor material.

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Номер записи: 100