VERFAHREN ZUM ABLÖSEN VON ETIKETTEN OHNE ABDECKBAND

Verfahren zur Bildung einer Isolationsschicht einer Halbleitereinrichtung

Verfahren, bei dem eine Isolationsschicht in ersten und zweiten Isolationsbereichen (53, 54) in einem Halbleitersubstrat (50) einer Halbleitereinrichtung gebildet wird, wobei der zweite Isolationsbereich (54) weiter ist als der erste Isolationsbere ich (53), mit folgenden Schritten: - Bildung einer ersten Isolationsschicht (51) und einer zweiten Isolationsschicht (52) auf dem Halbleitersubstrat (50); - Strukturieren der ersten Isolationsschicht (51) und der zweiten Isolationsschicht (52), wobei eine erste Ausnehmung (53a) im ersten Isolationsbereich (53) und eine Mehrzahl von zweiten Ausnehmungen (54a) im zweiten Isolationsbereich (54) gebildet werden; - gleichzeitige Bildung der ersten Ausnehmung (53a) und der zweiten Ausnehmungen (54a) unter Verwendung der strukturierten Isolationsschichten (51, 52) als Maske; - Bildung einer dritten Ausnehmung (56), die tiefer ist als die erste Ausnehmung (53a), im Zentralbereich der ersten Ausnehmung (53a) im ersten Isolationsbereich (53); - Durchführung ...

METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE HAVING TRENCH MEMORY CAPACITOR

Verfahren zum Ausbilden von Aussparungen in einem Halbleiterbauelement und mit dem Verfahren hergestelltes Bauelement

Verfahren zum Herstellen wenigstens einer Aussparung (12) in einem Halbleiterbauelement (1, 10) mit den Schritten:Aufbringen wenigstens einer Maske (20) auf dem Halbleiterbauelement (1, 10),Ausbilden wenigstens eines Gitters (22) mit mehreren Gitteröffnungen (26) in der Maske (20) über der auszubildenden Aussparung (12), wobei die Gitteröffnungen (26) in Abhängigkeit von der Ätzrate und/oder Dimensionierung der auszubildenden Aussparung (12) ausgebildet sind,wobei für eine breitere Aussparung (12) und/oder eine randnahe Aussparung (12) ein Gitter (22) mit kleineren Gitteröffnungen (26) und für eine schmälere Aussparung (12) und/oder eine Aussparung (12) im Innenbereich des Halbleiterbauelements (1, 10) ein Gitter (22) mit größeren Gitteröffnungen (26) über der auszubildenden Aussparung (12) in der Maske (20) ausgebildet wird;Ausbilden der Aussparung (12) unterhalb des Gitters (22).

A method of manufacturing semiconductor devices

Trench filling methods

Double trench for isolation of semiconductor devices

PRETREATMENT OF A WAFER FOR THE REDUCTION OF THE SEPARATION RATE OF SILICON DIOXIDE ON SILICON NITRIDE COMPARED WITH THEIR SEPARATION RATE ON A SILICON SUBSTRATE

SEMICONDUCTOR ARRANGEMENT ALSO IN THE SEMICONDUCTOR OF SUNK LAYER FROM INSULATING MATERIAL AND PROCEDURE FOR THEIR PRODUCTION

Structure for use in producing semiconductor devices with buried contacts and method for its preparation

HIGH PERFORMANCE BIPOLAR DEVICE AND METHOD FOR MAKING SAME

HIGH PERFORMANCE BIPOLAR DEVICE AND METHOD FOR MAKING SAME A method for manufacturing a high performance bipolar device and the resulting structure which has a very small emitter-base spacing is described. The small emitter-base spacing, reduces the base resistance compared to earlier device spacing and thereby improves the performance of the bipolar device. The method involves providing a silicon semiconductor body having regions of monocrystalline silicon isolated from one another by isolation regions and a buried subcollector therein. A base region is formed in the isolated monocrystalline silicon. A mask is formed on the surface of the silicon body covering those regions designated to be the emitter and collector reach-through regions. A doped polycrystalline silicon layer is then formed through the mask covering the base region and making ohmic contact thereto. An insulatinq layer is formed over the polysilicon layer. The mask is removed from those regions designated to be the emitter ...

HIGH PERFORMANCE BIPOLAR DEVICE AND METHOD FOR MAKING SAME

SEMICONDUCTOR ISOLATION STRUCTURES AND METHOD OF MANUFACTURING SAME

Method of Making Integrated Circuits

HALBLEITERANORDNUNG UND VERFAHREN ZU DEREN HERSTELLUNG.

Used for integrating capacitor of the FinFET structure and method

Semiconductor device and manufacturing method thereof

半导体集成电路装置的制造方法

... 提供一种在一次PR中完成为形成三沟道的埋入扩散层离子注入和为在一个芯片内形成两种不同膜厚的栅极氧化膜的氧化膜蚀刻的制造方法，可以降低成本，并使电路高速化。在形成栅极的区域在硅氧化膜上在给定宽度内形成抗蚀剂掩模，隔着上述抗蚀剂掩模以给定的注入能量进行离子注入，形成埋入N型层，在给定范围内的抗蚀剂掩模的正下方也形成埋入N型层。抗蚀剂掩模作为掩模，蚀刻除去氧化膜，并在其上形成栅极氧化膜。 ...

SEMICONDUCTOR DEVICE MANUFACTURE

SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF

ISOLATION METHOD FOR SEMICONDUCTOR DEVICE

PURPOSE: An isolation method for a semiconductor device is provided to prevent adjacent gate lines from being short-circuited in forming a gate by preventing a recessed portion on a field oxide layer formed in a trench, and to prevent a latch-up phenomenon and degradation of an isolation characteristic. CONSTITUTION: A mask layer exposing a field region is formed on a semiconductor substrate(31). The first trench having a broad area and a high aspect ratio and the second trench having a small area and a low aspect ratio are formed in the exposed field region of the semiconductor substrate where the mask layer is not formed. A filling oxide material(41) is deposited to fill the mask layer, the first trench and the second trench by a deposition method including a sputtering characteristic while a void(43) is formed in a portion under the second trench. The filling oxide material is etched back to remain only inside the first and second trenches and to form a field oxide layer. COPYRIGHT 2001 ...

METHOD FOR ISOLATING SEMICONDUCTOR DEVICE

PURPOSE: An isolation method of semiconductor device using STI(shallow trench isolation) is provided to easily achieve a global planarization by effectively filling an insulating layer to a trench using a plasma CVD(chemical vapor deposition). CONSTITUTION: A pad oxide, a first, a second and a third insulating layers are sequentially formed on a semiconductor substrate(100). By etching the insulating layers and the pad oxide, the third, the second and the first insulating patterns(106a,104a) and the pad oxide pattern(102a) are formed. A trench is then formed by etching the exposed substrate(100). A fourth insulating layer(114) is effectively filled into the trench by using plasma CVD for enabling deposition and etching simultaneously to form a protrusion. After forming a mask layer made of a polysilicon, the protrusion of the fourth insulating(114) and the mask layer are polished in order to form a mask pattern(116a). The exposed fourth insulating layer(114) is then etched using the mask ...

Trench Isolation Structure and Method for Fabricating the Same

METAL GATE CMOS AND METHOD OF MANUFACTURING THE SAME

NON-VOLATILE MEMORY DEVICE HAVING SELF-ALIGNED GATE CONDUCTIVE LAYER TO CONTROL STRICTLY PARAMETERS, AND METHOD FOR FABRICATING THE SAME

PURPOSE: A non-volatile memory device having a self-aligned gate conductive layer and a method for fabricating the same are provided to obtain a stability and to reduce a manufacturing cost by using a thermal processed device isolation layer patterns as a mold and forming a first conductive layer pattern . CONSTITUTION: Trench mask patterns are formed on a semiconductor substrate(10). Trenches(12) defining an active region are formed on the semiconductor substrate between the trench mask patterns. Device isolation layer patterns are formed to fill an empty space between the trench mask patterns and the trenches(35'). An active region is exposed by removing the trench mask patterns. A gate dielectric (40) and a first conductive layer are sequentially stacked on the active region between the device isolation layer patterns. A thermal process step making the device isolation layer patterns compact is further performed before the active region is exposed. © KIPO 2006 ...

DEVICE ISOLATION STRUCTURE OF SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF CAPABLE OF IMPROVING DEVICE ISOLATION EFFECT

PURPOSE: A device isolation structure of a semiconductor device and its fabricating method are provided to improve device isolation effect by differentiating a depth of an isolation layer according to a voltage to be used. CONSTITUTION: A cell region, a low voltage region, and a high voltage region are defined on a semiconductor substrate(50). A cell trench isolation layer(72a) is formed on the cell region. A low voltage trench isolation layer(72b) is formed in the low voltage region. The low voltage trench isolation layer is deeper than the cell trench isolation layer. A first high voltage trench isolation layer(72c) is formed on the high voltage region. The first high voltage trench isolation layer is deeper than the low voltage trench isolation layer. A second high voltage trench isolation layer(72d) is formed in the high voltage region. The second high voltage trench isolation layer is deeper than the low voltage trench isolation layer and shallower than first high voltage trench isolation ...

SIC MOSFET DEVICE FOR DECREASING ELECTRIC FIELD OF BOTTOM OXIDE LAYER AND METHOD FOR MANUFACTURING SAME

The present invention relates to a silicon carbide (SiC) MOSFET device for decreasing an electric field of a bottom oxide layer and a method for manufacturing the same. The SiC MOSFET device includes a first conductive SiC substrate, a first conductive epitaxial layer grown on the first conductive SiC substrate, a second conductive body layer deposited on the first conductive epitaxial substrate, a first trench structure passing through the second conductive body layer, and formed through partial etching to the first conductive epitaxial layer, a trench bottom layer formed on a bottom surface of the first trench structure, a gate electrode deposited to surround an internal side of the first trench structure including the trench bottom layer, a source electrode deposited on an upper end of the second conductive body layer except the first trench structure; and a drain electrode deposited on a lower end of the first conductive SiC substrate. The trench bottom layer is made of a high K material ...

TRENCH ISOLATION STRUCTURE HAVING SECOND ISOLATION PATTERN WITH HIGH ETCHING SELECTIVITY AND FORMING METHOD THEREOF

PURPOSE: A trench isolation structure and a method for forming the same are provided to restrain the generation of voids by using a second isolation pattern having high etch selectivity. CONSTITUTION: A trench(104) is formed in a substrate(100). A first isolation pattern(106a) is formed at the sidewalls and the bottom of the trench. A first subsidiary trench(107) is formed in the trench. A second isolation pattern(108) having a relatively high etch selectivity compared to the first isolation trench is partially filled in the first subsidiary trench. A second subsidiary trench is formed in the trench due to the second isolation pattern. A third isolation pattern(110a) is entirely filled in the second subsidiary trench. © KIPO 2007 ...

MANUFACTURING METHOD OF TRENCH ISOLATION STRUCTURE

The present invention relates to a manufacturing method of a trench isolation structure. The method comprises the following steps of: providing a substrate; forming a patterned mask layer on the substrate; performing a first etching step on the substrate to form a trench in the substrate by using the patterned mask layer; forming a dielectric material in the trench and on the patterned mask layer, wherein the dielectric material on the patterned mask layer has a first height; performing an etch back step to reduce the dielectric material on the patterned mask layer to a second height; and performing a planarization process to remove the dielectric material on the patterned mask layer. A polishing pad is used during the planarization process and a first pressure and a second pressure are applied to a center part and a surrounding part of the polishing pad, respectively, wherein the second pressure is greater than the first pressure. COPYRIGHT KIPO 2018 ...

METHOD OF FORMING AN INTEGRATED CIRCUIT DEVICE USING DUMMY FEATURES AND STRUCTURE THEREOF

A method for forming an integrated circuit device having dummy features (14) and the resulting structure are disclosed. One embodiment comprises a first active feature (25) separated from a substantially smaller second active feature (12) by a dummy- available region void of active features. Within the dummy-available region and in close proximity to the second active feature exists a dummy feature (14). © KIPO & WIPO 2007 ...

SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING DISHING OF LAMINATED PLANARIZED SURFACES BY USING DUMMY PATTERNS

PURPOSE: A semiconductor device is provided to prevent dishing of laminated planarized surfaces by using dummy patterns being offset with a half of a pitch. CONSTITUTION: A semiconductor device comprises a semiconductor substrate provided with semiconductor elements on a primary surface, a first pattern formed on the primary surface or a layer thereof, and a second pattern formed on the first pattern. A first dummy pattern(DL) is included in the first pattern and a second dummy pattern(Ds) is included in the second pattern. The first and second dummy patterns are formed on a scribe region(SR) of the semiconductor substrate. The second dummy pattern is formed on a space with respect to the first dummy pattern in a plane. The first and second dummy patterns are offset with a half of a pitch. © KIPO 2006 ...

Dielectric deposition and etch back processes for bottom up gapfill

Methods to reduce film cracking in a dielectric layer are described. The methods may include the steps of depositing a first dielectric film on a substrate and removing a top portion of the first dielectric film by performing an etch on the film. The methods may also include depositing a second dielectric film over the etched first film, and removing a top portion of the second dielectric film. In addition, the methods may include annealing the first and second dielectric films to form the dielectric layer, where the removal of the top portions from the first and the second dielectric films reduces a stress level in the dielectric layer.

Semiconductor device and method for manufacturing the same

A semiconductor device including a cell region and a peripheral region, the semiconductor device comprising: a guard ring region provided between the cell region and the peripheral region, the guard ring region having a barrier structure.

A NEW METHOD FOR PRE-STI-CMP PLANARIZATION USING POLY-SI THERMAL OXIDATION

PROCESS FOR FORMING ISOLATION TRENCHES IN A SEMICONDUCTOR SUBSTRATE

In a process for forming planar, dielectric filled, narrow and wide trenches in integrated circuit devices, following the formation of the trenches (2, 3) in the substrate (1), successive layers of conformal silicon nitride (15), conformal polysilicon (14), and relatively conformal CVD oxide (16) are formed to the relative depth of the trenches (2, 3). A photoresist mask (22) is then first selectively formed over the central regions of the wide trenches (3) and then used as a mask during the anisotropic etch of exposed oxide. The underlying polysilicon layer (14) serves as an oxide etchant stop, and also provides the material from which the next successive oxidation partially fills the previously etched regions with thermal silicon dioxide. A further layer of oxide is then formed by poly deposition and oxidation. The nitride layer (13) underlying the polysilicon layer prevents oxidation of the substrate. Fabrication is concluded with a planarization to the level of the active regions (8 ...

SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE

A semiconductor device manufacturing method comprises a step (A) of preparing a substrate provided with a semiconductor layer having a major surface and an element isolation structure (STI) formed in an isolation region (70) dividing the major surface into element active regions (50, 60), a step (B) of growing an epitaxial layer containing Si and Ge on the selected element active region (50) out of the element active regions (50, 60) in the major surface of the semiconductor layer, and a step (C) of fabricating transistors in the element active region (50) where the epitaxial layer is formed out of the element active regions (50, 60) and in an element active region (A2) where no epitaxial layer is formed. The step (A) includes a sub-step (a1) of forming dummy regions (80) surrounded by the element isolation structure (STI) in the isolation region (70). The step (B) includes a sub-step (b1) of growing a layer of the same material as the epitaxial layer on a selected region of the dummy regions ...

Shallow trench isolation recess process flow for vertical field effect transistor fabrication

A semiconductor device includes structures formed in first and second regions of a semiconductor substrate. The structures in the first region are spaced with a pitch P. The first and second regions are separated by an isolation region with spacing S, wherein S is greater than P. A first insulating layer is deposited and recessed to a target depth in the first region, and to a second depth in the isolation region. The second depth is lower than the target depth. A first etch stop layer is formed over the recessed first insulating layer, and a second insulating layer is formed over the first etch stop layer to increase a level of insulating material in the isolation region to the same target depth in the first device region. The recessed first insulating layer, first etch stop layer, and second insulating layer form a uniform thickness shallow trench isolation layer.

Method for manufacturing device isolation film of semiconductor device

A method for manufacturing device isolation film of semiconductor device is disclosed. The method utilizes a plasma oxidation of a liner nitride film exposed by etching a liner oxide the film in peripheral region prior to the formation of device isolation film to prevent the generation of a electron trap which causes trapping of electrons at the interface of the oxide film and the nitride film resulting in a HEIP phenomenon.

Semiconductor device

A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation portion) extending below the surface of the SOI layer, and the SOI layer under the partial isolation insulating film is of greater thickness than the isolation portion.

Dry-etching method

A dry-etching method using an apparatus where a wafer is placed on either of a pair of opposed electrodes provided in an etching chamber, and high-frequency power is supplied to both the opposed electrodes to effect a plasma etching. The plasma etching uses a gas containing at least Cl2 and HBr. Trenches 104a, 104b are formed, as shown in FIG. 1B, in a silicon wafer 101 shown in FIG. 1A through a mask layer such as a nitride silicon layer 103. While adjusting the high-frequency power supplied to the opposed electrode where the wafer is placed, the shape of the sidewalls 105a, 105b of the trenches 104a, 104b is controlled. Thus, the trenches can have desired shapes even if the widths of the trenches are different.

METHODS FOR FILLING SHALLOW TRENCH ISOLATIONS HAVING HIGH ASPECT RATIOS

A method of forming an isolation trench for an integrated circuit on a semiconductor substrate includes providing a semiconductor substrate having a pad oxide layer, a nitride layer, and a patterned photoresist layer, and removing portions of the nitride layer, pad oxide layer, and semiconductor substrate to form a trench. After the trench is formed, the patterned photoresist is removed and a first fill layer is formed inside of the trench. The first fill layer is then etched back using a wet spin etch, and a second fill layer is subsequently formed over the first fill layer.

Isolation trench fabrication process

Two steps of planarizing are performed during isolation trench fabrication resulting in a more uniform planarization of an integrated circuit substrate. A protective layer deposition and a planarizing step are performed prior to a final planarizing step. Applying protective material fills in a portion of recesses in a dielectric layer overlying isolation trench areas. A first global planarization process eliminates narrower recesses and shallows out deeper recesses without causing dishing in the dielectric material. Much of the protective material is removed by the first global planarization process. The remaining protective material is stripped. A final global planarization process then is performed which removes dielectric material outside of the trench areas. A well-defined border of the trenches results.

Tapered groove IC isolation

A semiconductor device and the method of manufacturing the same are disclosed, the semiconductor device having a plurality of elements isolated by a groove having a gentle slope at the upper side wall, and a steep slope at the lower side wall. This groove provides low steps on its mouth and occupies a small area on the substrate, thus enabling an extremely high-density integrated circuit to be formed.

Semiconductor device including resistors isolated and equdistant from diffusion regions

In a semiconductor substrate, at least one diffusion region exists between resistors on an element isolation layer, and the resistors and the diffusion regions are arranged such that all distances between the respective resistors and the diffusion regions around the corresponding resistors are equal.

Semiconductor device and method for manufacturing same

A hard mask material film is formed on a semiconductor substrate and a recess is formed immediately below an opening in an upper surface of the semiconductor substrate. Next, a p-type region is formed immediately below the recess by implanting impurities into an imaging region using the hard mask material film as a mask. Moreover, a trench is formed by further processing the recess in a processing region. A half-buried dielectric film and a STI are formed by burying a dielectric material in the recess and the trench to remove the hard mask material film. Next, two electrodes are formed so as to overlap the half-buried dielectric film and the STI, respectively, and impurities are implanted into the imaging region using one electrode and the half-buried dielectric film as a mask, and hence a n-type region constituting a photodiode is formed in a region being in contact with the p-type region in the semiconductor substrate.

Semiconductor device

A dummy active region is formed in which abrading processes are averaged. A semiconductor device is characterized in that an active region for forming an actual device, a device separation region being formed by a trench, and a dummy active region formed substantially in a rectangular shape are included, and the length of the short side of the dummy active region is less than 1 mum.

Method of manufacturing a semiconductor integrated circuit device that includes forming dummy patterns in an isolation region prior to filling with insulating material

A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film. The method may also include the step of forming dummy patters in a relatively large isolation region of isolation ...

Semiconductor device and method for manufacturing the same

A semiconductor device including a source region and a drain region spaced from each other by a predetermined interval and formed on a main surface of a semiconductor substrate. A gate electrode is formed on the semiconductor substrate. A trench is filled with insulation material and formed in the main surface of the semiconductor substrate between a location under the gate electrode and at least one of the source region and the drain region with a predetermined depth. An LDD is formed along the trench and has an impurity concentration that is lower than that of the source region and the drain region.

Semiconductor device with self-aligned junction contact hole and method of fabricating the same

A plurality of trenches for defining active regions are formed in a semiconductor substrate, using a plurality of trench masks. A gap fill insulating layer is formed on the resulting structure to fill a gap region bounded by the trench and the trench masks. Next, the trench mask and the gap fill insulating layer are patterned to form a trench mask pattern and a gap fill insulating pattern for defining a slit-type opening, extending across and exposes the active region. A gate pattern is formed in the slit-type opening and the trench mask pattern is removed to form a contact opening exposing the active region. Next, a contact plug is formed to fill the contact opening. Here, the contact opening is self-alignedly formed using an etch selectivity between the trench mask and the gap fill insulating layer. The resulting contact opening is a vacancy in a rectangular parallelepiped shape.

Semiconductor device and method for manufacturing the same

A method for manufacturing a semiconductor substrate including a mask aligning trench. The method includes forming the mask aligning trench and an element partitioning trench. The element partitioning and mask aligning trenches are filled with insulation. The insulation in the element partitioning trench is masked and the insulation in the mask aligning trench is etched. As a result, a residue of the insulation in the mask aligning trench is below the upper edge of the mask aligning trench. The mask aligning trench is easily detected. Thus, positioning a patterning mask on the substrate can be performed accurately.

Formation of semiconductor devices with dual trench isolations

A method for fabricating a semiconductor device with dual trench isolations includes forming a deep trench located between a first region associated with a first array of transistors and a second region associated with a second array of transistors, forming a first shallow trench located between transistors of the first array and a second shallow trench located between transistors of the second array, and forming, by a single dielectric material fill process, a deep trench isolation (DTI) region in the deep trench, a first shallow trench isolation (STI) region in the first shallow trench, and a second STI region in the second shallow trench.

Method of doping sidewall of isolation trench

A method of doping sidewalls of an isolation trench is provided. A substrate having a trench thereon is provided. A blocking layer is formed within the trench such that the top surface of the blocking layer is lower than the top surface of the substrate. A sidewall doping process is performed to form a doped region in the substrate at the upper trench sidewall. The blocking layer is removed from the trench. Because the blocking layer prevent dopants from reaching the bottom half of the trench during the sidewall doping process, junction leakage at the bottom section of the trench is prevented.

Method for forming isolation layer of semiconductor device

A method for forming an isolation layer of a semiconductor device is disclosed, which comprises the steps of: etching a silicon substrate having a cell region and a peripheral circuit region, forming a first trench having a first size in the cell region, and forming a second trench having a second size, which is larger than the first size of the first trench, in the peripheral circuit region; forming a sidewall oxide layer on surfaces of the first trench and the second trench; sequentially depositing a liner nitride layer and a liner oxide layer on a resultant substrate inclusive of the sidewall oxide layer; performing a plasma pre-heating process using O₂+He with respect to the resultant substrate in an HDP CVD process chamber and selectively oxidizing a portion of the liner nitride layer remaining on a bottom of the second trench in the peripheral circuit region; continuously depositing an HDP oxide layer on the resultant substrate having been subjected to the plasma pre-heating ...

Dishing-Free Gap-Filling with Multiple CMPs

A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed.

Method of planarizing a film layer

A method of fabricating a semiconductor device is disclosed. The method includes forming a first flowable-material (FM) layer over a substrate. A top surface of the first FM layer in a first region is higher than a top surface of the first FM layer in a second region. The method also includes forming a sacrificial plug to cover the first FM layer in the first region, forming a second FM layer over the sacrificial plug in the first region and over the first FM layer in the second region, performing a first recessing process such that the second FM layer is removed in the first region and performing a second recessing process on the second FM layer in the second region while the first FM layer is protected by the sacrificial plug in the first region.

SIMPLIFIED METHOD OF PATTERNING FIELD DIELECTRIC REGIONS IN A SEMICONDUCTOR DEVICE

Isolation regions are formed with greater accuracy and consistency by forming an oxide-silicon nitride stack and then depositing an antireflective layer, of silicon oxime, on the silicon nitride layer before patterning. Embodiments also include depositing the silicon nitride layer and the silicon oxime layer in the same tool.

ISOLATION PILLAR FIRST GATE STRUCTURES AND METHODS OF FORMING SAME

A method of forming isolation pillars for a gate structure, the method including: providing a preliminary structure including a substrate having a plurality of fins thereon, an STI formed between adjacent fins, an upper surface of the STIs extending higher than an upper surface of the fins, and a hardmask over the upper surface of the fins and between adjacent STIs; forming a first trench in a first selected STI and between adjacent fins in a gate region, and forming a second trench in a second selected STI and between adjacent fins in a TS region; and filling the first and second trenches with an isolation fill thereby forming a first isolation pillar in the gate region and a second isolation pillar in the TS region, the first and second isolation pillars extending below the upper surface of the STIs.

SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME

Semiconductor devices and methods of forming the same are provided. The methods may implanting dopants into a substrate to form a preliminary impurity region and heating the substrate to convert the preliminary impurity region into an impurity region. Heating the substrate may be performed at an ambient temperature of from about 800° C. to about 950° C. for from about 20 min to about 50 min. The method may also include forming first and second trenches in the impurity region to define an active tin and forming a first isolation layer and a second isolation layer in the first and second trenches, respectively. The first and second isolation layers may expose opposing sides of the active fin. The method may further include forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin and forming a gate electrode traversing the active fin ...

Method of manufacturing solid-state image sensor

A method of manufacturing a solid-state image sensor having a pixel region and a peripheral circuit region, includes forming an oxide film on a semiconductor substrate, forming an insulating film on the oxide film, forming a first opening in the insulating film and the oxide film in the peripheral circuit region, forming a trench in the semiconductor substrate in the peripheral circuit region by etching the semiconductor substrate through the first opening using the insulating film as a mask, forming a second opening in the insulating film to penetrate through the insulating film in the pixel region and to reach a predetermined depth of the oxide film, and forming insulators in the trench and the second opening.

Semiconductor device and method of fabricating the same

A semiconductor device includes a semiconductor substrate of a first conduction type, a first well of a second conduction type formed on the semiconductor substrate, a plurality of second wells of the first conduction type provided in the first well for forming memory cells and a peripheral circuit respectively, each second well having a first depth, a first trench isolating region formed so as to isolate an element within the second well for the memory cells and having a first depth, a guard-ring diffusion region of the first conduction type provided in the vicinity of a peripheral edge of each second well for the memory cells and doped with a high density impurity so as to encompass a forming region of the memory cells, a second trench isolating region formed so that a p-n junction of each second well terminates on a bottom thereof in the vicinity of an outside of the guard-ring diffusion region, the second trench isolating region having a second depth larger than the first depth of each ...

Trench formation method for releasing a thin-film substrate from a reusable semiconductor template

A method is provided for fabricating a thin-film semiconductor substrate by forming a porous semiconductor layer conformally on a reusable semiconductor template and then forming a thin-film semiconductor substrate conformally on the porous semiconductor layer. An inner trench having a depth less than the thickness of the thin-film semiconductor substrate is formed on the thin-film semiconductor substrate. An outer trench providing access to the porous semiconductor layer is formed on the thin-film semiconductor substrate and is positioned between the inner trench and the edge of the thin-film semiconductor substrate. The thin-film semiconductor substrate is then released from the reusable semiconductor template.

Semiconductor device and method of producing the same

In a semiconductor device having element isolation made of a trench-type isolating oxide film 13, large and small dummy patterns 11 of two types, being an active region of a dummy, are located in an isolating region 10, the large dummy patterns 11b are arranged at a position apart from actual patterns 9, and the small dummy patterns 11a are regularly arranged in a gap at around a periphery of the actual patterns 9, whereby uniformity of an abrading rate is improved at a time of abrading an isolating oxide film 13a is improved, and surface flatness of the semiconductor device becomes preferable.

High breakdown voltage LDMOS device

A multi-region (81, 83) lateral-diffused-metal-oxide-semiconductor (LDMOS) device (40) has a semiconductor-on-insulator (SOI) support structure (21) on or over which are formed a substantially symmetrical, laterally internal, first LDMOS region (81) and a substantially asymmetric, laterally edge-proximate, second LDMOS region (83). A deep trench isolation (DTI) wall (60) substantially laterally terminates the laterally edge-proximate second LDMOS region (83). Electric field enhancement and lower source-drain breakdown voltages (BVDSS) exhibited by the laterally edge-proximate second LDMOS region (83) associated with the DTI wall (60) are avoided by providing a doped SC buried layer region (86) in the SOI support structure (21) proximate the DTI wall (60), underlying a portion of the laterally edge-proximate second LDMOS region (83) and of opposite conductivity type than a drain region (31) of the laterally edge-proximate second LDMOS region (83).

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become source wires or drain wires are formed on an interlayer insulation film of the first layer over the high voltage resistant MISFET. At this moment, when a distance from an interface between a semiconductor substrate and a gate insulation film to an upper portion of the gate electrode is defined as a, and a distance from the upper portion of the gate electrode to an upper portion of the interlayer insulation film on which the wires are formed is defined as b, a relation of a>b is established. In such a high voltage resistant MISFET structured in this manner, the wires are arranged so as not to be overlapped planarly with the gate electrode of the high voltage resistant MISFET.

Semiconductor device and method of providing regions of low substrate capacitance

A semiconductor device ( 2 ) includes a semiconductor substrate ( 12 ) having a surface ( 13 ) formed with a first recessed region ( 20 ). A first dielectric material ( 60 ) is deposited in the first recessed region and formed with a second recessed region ( 76 ), and a second dielectric material ( 100 ) is grown over the first dielectric material to seal the second recessed region.

TESTING STRUCTURE FOR AN INTEGRATED CHIP HAVING A HIGH-VOLTAGE DEVICE

Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first deep trench isolation (DTI) structure in a substrate. A dielectric structure is over the substrate. An interconnect structure is in the dielectric structure. The interconnect structure includes a lower interconnect structure and an upper interconnect structure that are electrically coupled together. The upper interconnect structure includes a plurality of conductive plates. The plurality of conductive plates are vertically stacked and electrically coupled together. A back-side through substrate via (BTSV) is in the substrate and the dielectric structure. The BTSV extends from a conductive feature of the lower interconnect structure through the dielectric structure and the substrate. The conductive feature of the lower interconnect structure is at least partially laterally within a perimeter of the DTI structure. The BTSV is within the perimeter of the DTI structure.

SEMICONDUCTOR STRUCTURE WITH JUNCTION LEAKAGE REDUCTION

An LDMOS device comprises a well region, first and second implant regions, a gate electrode, first and second source/drain regions, a first STI region, and a first DTI region. The well region is in a substrate and of a first conductivity type. The first implant region is in the substrate and of a second conductivity type. The second implant region is in the well region and of the first conductivity type. The gate electrode extends from above the well region to above the first implant region. The first and second source/drain regions are respectively in the first and second implant regions. The first STI region laterally extends from the second implant region to directly below the gate electrode. The first DTI region extends downwards from a bottom surface of the first STI region into the well region. The first DTI region vertically overlaps with the gate electrode.

SEMICONDUCTOR DEVICE WITH FLOWABLE LAYER

The present application discloses a semiconductor device with the flowable layer. The semiconductor device includes a substrate, a first isolation layer positioned in the substrate, a first treated flowable layer positioned between the first isolation layer and the substrate, a second isolation layer positioned in the substrate, and a second treated flowable layer positioned between the second isolation layer and the substrate. A width of the first isolation layer is greater than a width of the second isolation layer, and a depth of the first isolation layer is less than a depth of the second isolation layer.

METHOD FOR FORMING AND FILLING ISOLATION TRENCHES

A method for forming isolation trenches for semiconductor devices forms, in a substrate, a plurality of trenches (30 and 32) having different widths including widths above a threshold size (30) and widths below a threshold size (32). The plurality of trenches have a same first depth (D1). A masking layer (52) is deposited in the plurality of trenches, the masking layer has a thickness sufficient to both line the trenches with the widths above the threshold size and completely fill the trenches with the widths below the threshold size. A portion of the substrate (16) is exposed at a bottom of the trenches with the widths above the threshold size by etching the masking layer. The plurality of trenches are etched to extend the trenches with the widths above the threshold size to a greater depth (D2).

半導体デバイスの絶縁

半導体素子の形成方法

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

PROBLEM TO BE SOLVED: To provide, for example, a fin-type semiconductor device and a method of manufacturing the same. SOLUTION: A multilayer structure 104 is formed so as to include a first layer 108 formed on a semiconductor substrate 102, a second layer 110 formed on the first layer, and a third layer 112 formed on the second layer. A plurality of fins 202 is formed on the semiconductor substrate, and a part of the multilayer structure 204 is formed on the fin, by removing an upper part of the semiconductor substrate and the multilayer structure. An isolation material 300 whose top surface is aligned with a top surface of the multilayer structure is formed between the fins 206. An upper part of the third layer and the isolation material are etched so that the second layer is exposed, and the second layer and a part of the remaining isolation material are etched so that the first layer is exposed. COPYRIGHT: (C)2012,JPO&INPIT ...

Verfahren zum Ausbilden von Isolationsgebieten eines Halbleiterbauelements und Halbleiterbauelemente

Verfahren zum Ausbilden von isolierenden Gebieten eines Halbleiterbauelements (300, 400), wobei das Verfahren umfaßt: Bereitstellen eines Werkstücks (302, 402), wobei das Werkstück mindestens ein erstes Gebiet (307, 407) und mindestens ein zweites Gebiet (310, 410) aufweist, wobei das mindestens eine erste Gebiet (307, 407) mindestens einen aktiven Bereich für hohe Spannung (308, 408) umfaßt, wobei das zweite Gebiet (310, 410) mindestens einen aktiven Bereich für niedrige Spannung (312, 412) umfaßt, wobei das Werkstück eine obere Oberfläche aufweist; Strukturieren des ersten Gebiets (307, 407) mit mindestens einem Tiefgraben (314, 414), wobei der Tiefgraben Seitenwände, einen Boden und eine erste Tiefe (d2) im Werkstück aufweist; Ausbilden einer ersten isolierenden Schicht (316, 416) über den Seitenwänden und dem Boden des mindestens einen Tiefgrabens (314, 414); Abscheiden eines halbleitenden Materials (318, 418) in dem mindestens einen Tiefgraben (314, 414) über der ersten isolierenden ...

Feldeffekttrasistor und Verfahren zu seiner Herstellung

Feldeffekttransistor, insbesondere MIS-Feldeffekttransistor, mit: a) einem Sourcegebiet und einem Draingebiet, b) einem Kanalgebiet (8), das zwischen dem Sourcegebiet und dem Draingebiet angeordnet ist, c) einer Gatelektrode (11), die elektrisch isoliert vom Kanalgebiet über dem Kanalgebiet angeordnet ist, d) einer Grabenisolation (3), die das Kanalgebiet (8) seitlich begrenzt, e) wobei zumindest ein Teilgebiet (8a, 8b) des Kanalgebiets (8) einen Teil (6) der Grabenisolation (3) überdeckt.

Verfahren zur Herstellung einer Halbleiteranordnung mit Grabenstruktur für Element Isolationszonen

Insulation film formation method for semiconductor component

The method involves depositing on a substrate an insulation film, and a recess is formed in an insulation region. Several recesses are in a second insulation region such that the insulation film is exposed to a photolithographic process only once. A third recess, deeper than the first one, is formed in the centre section of the first recess. The three recesses are filled with insulation material, or with a thermal oxidation layer. Pref. the second recesses are narrower than the first one. Typically the substrate is processed by RIE or CDE for forming the first and second recesses, and the second insulation film is formed by CVD.

Struktur und Verfahren für FinFET-Vorrichtung mit asymmetrischem Kontakt

Die vorliegende Offenbarung stellt eine Ausführungsform einer Halbleiterstruktur bereit. Die Halbleiterstruktur weist einen aktiven Bereich vom Fin-Typ, der aus einem Halbleitersubstrat extrudiert wird; einen Gate-Stapel, der auf dem aktiven Bereich vom Fin-Typ angeordnet ist; ein Source/Drain-Merkmal, das im aktiven Bereich vom Fin-Typ ausgebildet ist und auf einer Seite des Gate-Stapels angeordnet ist; ein längliches Kontaktmerkmal, das auf dem Source/Drain-Merkmal aufsitzt; und eine dielektrische Materialschicht auf, die an den Seitenwänden des länglichen Kontaktmerkmals angeordnet ist und frei von den Enden des länglichen Kontaktmerkmals ist.

MAKING SEMICONDUCTOR DEVICE

Method for forming field oxide in semiconductor device

In a method for forming field oxide films in a semiconductor device, a first insulating film (13) is formed on a semiconductor substrate (11) followed by the deposition of a second insulating film (15) on the first film. The first film is an oxide, and the second a nitride. The structure is etched to form narrow trenches (17) and a wide trench (18). A third insulating film (19) of oxide is formed on the surfaces of the trenches through thermal oxidation. The exposed surfaces of the third and the second films are surface treated such that the oxide film (19) has a positive potential. This positive potential allows a fourth insulating layer (23), for example, an ozone-TEOS film, to be deposited at a slow rate over the nitride film (13) but at a high rate over the oxide film (19). Thus, a blanket (23) of ozone-TEOS film may be deposited over the resulting structure until the upper surface of the fourth film is higher than the height of the second film. The fourth film is then thermally treated ...

Trench isolation

A semiconductor device (e.g. MOSFET or IGBT) comprises active and termination regions (1,2) formed in a semiconductor substrate (4). The substrate (4) has an upper surface and a termination including a trench (12) extending into the substrate (4) from the upper surface within the termination region (1). Termination trench (12) is at least partly filled with an insulating material (13) which extends from the termination trench (12) to overlie adjacent regions of the device above the surface. A channel stop region (11) extends laterally from a side wall of the termination trench (12) into the substrate (4).

Two layer filling for high aspect ratio trenches

In a method for filling a recess having a high aspect ratio, such as a shallow trench isolation structure, a flowable layer 51, 52 is deposited in the recess to reduce the aspect ratio, and the recess is subsequently filled by another material. Prior to deposition of the other material, none of the flowable layer 51, 52 is on the sidewalls of the upper part of the trench. The flowable layer may be prevented from forming on the upper sidewalls of the trench by depositing a dewetting layer 30 and/or a layer 100 to increase the aspect ratio at the top of the trenches 110. Alternatively or additionally etching may be used to remove flowable oxide at the upper surface of the wafer 10 and around the edges of the recesses.

Method for forming field oxide film in semiconductor device

PROCEDURE FOR SMOOTHING TOPOLOGIES FOR INTEGRATED CIRCUITS

PROCEDURE FOR THE PRODUCTION OF AMONG THEMSELVES SELBSTALIGNIERTEN DITCHES USING A MASK.

HALBLEITERANORDNUNG MIT IN DEM HALBLEITER VERSENKTER SCHICHT AUS ISOLIERMATERIAL UND VERFAHREN ZU DEREN HERSTELLUNG

ROTATION SHEAR STRESS FOR CHARGE CARRIER MOBILITY MODIFICATION

PROCEDURE FOR THE TRAINING OF MASK OPENINGS WITH THE PRODUCTION OF SEMICONDUCTOR ARRANGEMENTS.

DUAL TRENCH ISOLATION FOR A PHASE-CHANGE MEMORY CELL AND METHOD OF MAKING SAME

METHOD OF MANUFACTURING AN OXIDE BEAM

SEMICONDUCTOR DEVICE

METHOD FOR FORMING AN INSULATOR BETWEEN LAYERS OF CONDUCTIVE MATERIAL

A method for forming an insulator between conductive layers, such as highly doped polycrystalline silicon, that involves first forming a conductive layer of, for example, polycrystalline silicon on a silicon body having substantially horizontal and substantially vertical surfaces. A conformal insulator layer is formed on the substantially horizontal and substantially horizontal and vertical surfaces. Reactive ion etching removes the insulator from the horizontal layer and provides a narrow dimensioned insulator on the vertical surfaces silicon body. Another conductive layer, which may be polycrystalline silicon, is formed over the insulator. The vertical layer dimension is adjusted depending upon the original thickness of the conformal insulator layer applied.

TWO MASK TECHNIQUE FOR PLANARIZED TRENCH OXIDE ISOLATION OF INTEGRATED DEVICES

Semiconductor device and method of manufacturing the same

The invention is directed to reduction of a manufacturing cost and enhancement of a breakdown voltage of a PN junction portion abutting on a guard ring. An N- type semiconductor layer is formed on a front surface of a semiconductor substrate, and a P type semiconductor layer is formed thereon. An insulation film is formed on the P type semiconductor layer. Then, a plurality of grooves, i.e., a first groove, a second groove and a third groove are formed from the insulation film to the middle of the N- type semiconductor layer in the thickness direction thereof. The plurality of grooves is formed so that one of the two grooves next to each other among these, that is closer to an electronic device, i.e., to an anode electrode, is formed shallower than the other located on the outside of the one. Then, an insulating material is deposited in the first groove, the second groove and the third groove. The lamination body of the semiconductor substrate and the layers laminated thereon is then diced ...

Compound semiconductor device and manufacture method thereof

The invention provides a compound semiconductor device and a manufacture method thereof. The invention provides an AlGaN/GaN HEMT, including a compound semiconductor stack structure; an element isolation structure which demarcates an element region on the compound semiconductor stack structure; a first insulating film which is formed on the element region and is not formed on the element isolation structure; a second insulating film which is formed on at least the element isolation structure and is higher in hydrogen content than the first insulating film; and a gate electrode which is formed on the element region of the compound semiconductor stack structure via the second insulating film.

半导体集成电路器件和制造半导体集成电路器件的方法

... 在半导体衬底上形成使第一井形成区和第二井形成区露出的光致抗蚀剂图形，它被用作掩模，把杂质掺入半导体衬底，由此形成埋置n井，并进一步被用作掩模，把杂质掺入半导体衬底，由此以自对准方式在埋置n井上形成浅p井。接着，去除光致抗蚀剂图形。此后，在半导体衬底主表面上形成使第一井形成区的外围区和第三井形成区露出的光致抗蚀剂图形，并被用作掩模，把杂质掺入半导体衬底，由此形成浅p井。 ...

具应变通道的互补式金氧半导体及其制作方法

The CMOS includes a semiconductor substrate, multiple trench isolation zones on the substrate, a bedding layer of nitride, an ion planted bedding layer of nitride, an N type channel transistor and a P type channel transistor. Driving zone including one N type driving zone and one P type driving zone is defined between two adjacent trench isolation zones. Bedding layers of nitride are setup between two sides of N type driving zone and substrate in compliance. Ion planted bedding layer of nitride are setup between two sides of P type driving zone and substrate in compliance. N type channel transistor is above N type driving zone and P type channel transistor is above P type driving zone.

Methods of fabricating semiconductor devices having various isolation regions

A method of fabricating a semiconductor device includes forming a first trench and a second trench in a semiconductor substrate, forming a first insulator to completely fill the first trench, the first insulator covering a bottom surface and lower sidewalls of the second trench and exposing upper sidewalls of the second trench, and forming a second insulator on the first insulator in the second trench.

Vertical gated access transistor

A method of forming an apparatus includes forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a substrate. At least one of the shallow trenches is positioned between two deep trenches. The shallow trenches and the deep trenches are parallel to each other. A layer of conductive material is deposited over the first region and a second region of the substrate. The layer of conductive material is etched to define lines separated by gaps over the first region of the substrate, and active device elements over the second region of the substrate. The second region of the substrate is masked and the lines are removed from the first region of the substrate. Elongate trenches are etched where the lines were removed while the second region of the substrate is masked.

Semiconductor device and method of fabricating the same

A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate in which a multi-depth trench is formed, the multi-depth trench including a shallow trench and a deep trench arranged below the shallow trench, a first dielectric material formed in partial area of the multi-depth trench, the first dielectric material including a slope in the shallow trench that extends upward from a corner where a bottom plane of the shallow trench and a sidewall of the deep trench meets, the slope being inclined with respect to the bottom plane of the shallow trench, and a second dielectric material formed in areas of the multi-depth trench in which the first dielectric material is absent.

Memory device and method of fabricating the same

A memory device includes a mesa structure and a word line. The mesa structure, having two opposite side surfaces, includes at least one pair of source/drain regions and at least one channel base region corresponding to the pair of source/drain regions formed therein. The word line includes two linear sections and at least one interconnecting portion. Each linear section extends on the respective side surface of the mesa structure, adjacent to the channel base region. The at least one interconnecting portion penetrates through the mesa structure, connecting the two linear sections.

Method for forming fine pattern of semiconductor device

A method for forming fine pattern includes sequentially forming a first thin film and a second thin film over a target layer for patterning, forming a partition over the second thin film, removing the partition after forming spacers on sidewalls of the partition, forming first pattern of the second thin film by etching the second thin film of a first region and the second thin film of a second region while exposing the spacers, forming second pattern of the second thin film by using the spacers as masks and etching the first pattern of the second thin film in the first region, forming first thin film pattern by using the first and second patterns of the second thin film as masks in the first and second regions and etching the first thin film, and etching the pattern target layer.

Method for manufacturing semiconductor device

A method includes forming first insulating films on first and second faces of a substrate, removing the first insulating film on the second face, forming polysilicon films on the first insulating film on the first face and the second face, forming second insulating films on the polysilicon films on the first face and the second face, etching the second insulating film on the first face using a mask including an opening, removing the second insulating films on the first face and the second face, removing the polysilicon film on the side of the first face and forming a passivation film which protects the polysilicon film on the side of the second face so that the polysilicon film on the side of the second face is not removed in the polysilicon film removing step, after the polysilicon film forming step and before the polysilicon film removing step.

Methods for fabricating semiconductor devices and semiconductor devices using the same

A method for fabricating a fine pattern of a semiconductor device is provided. The method includes forming a base layer, a first mask pattern having identical features of a first width with inclined sidewalls and a second mask pattern having identical features of a second width in sequence on a substrate, wherein a smallest distance between any two adjacent inclined sidewalls is equal to the second width. The base layer is etched by using the first mask pattern as an etch mask to form first openings of the second width and a fill layer is formed covering the substrate. The second mask pattern is removed to form second openings in the fill layer and then the first mask pattern and the base layer are etched through the second openings to form third openings. The fill layer and the first mask pattern are removed to form a pattern of the base layer having identical features of a third width, wherein the third width of the features of the base layer pattern is equal to the second width.

Mechanisms of doping oxide for forming shallow trench isolation

The embodiments described provide mechanisms for doping oxide in the STIs with carbon to make etch rate in the narrow and wide structures equal and also to make corners of wide STIs strong. Such carbon doping can be performed by ion beam (ion implant) or by plasma doping. The hard mask layer can be used to protect the silicon underneath from doping. By using the doping mechanism, the even surface topography of silicon and STI enables patterning of gate structures and ILD0 gapfill for advanced processing technology.

Post cmp planarization by cluster ion beam etch

The embodiments of mechanisms described enables improved planarity of substrates, which is crucial for patterning and device yield improvement. Chemical-mechanical polishing (CMP) is used to remove film to planarize the substrate before the final thickness is reached or before all removal film is polished. The substrate is then measured for its topography and film thickness. The topography and thickness data are used by the gas cluster ion beam (GOB) etch tool to determine how much film to remove on a particular location. GOB etch enables removal of final layer to meet the requirements of substrate uniformity and thickness target. The mechanisms enable improved planarity to meet the requirement of advanced processing technologies.

Nonvolatile semiconductor memory device and method for manufacturing the same

A device isolation film has a first height in a first area and a second height higher than the first height in a second area. The first area includes a first end of a dummy memory transistor facing a memory string and a part of a device isolation film adjacent thereof. The second area includes a second end of the dummy memory transistor facing a select transistor and a part of the device isolation film adjacent thereof.

Semiconductor device and manufacturing method of the semiconductor device

A semiconductor device includes a semiconductor substrate, a device region including first and second parts, first and second gate electrodes formed in the first and the second parts, first and second source regions, first and second drain regions, first, second, third, and fourth embedded isolation film regions formed under the first source, the first drain, the second source, and the second drain regions, respectively. Further, the first drain region and the second source region form a single diffusion region, the second and the third embedded isolation film regions form a single embedded isolation film region, an opening is formed in a part of the single diffusion region so as to extend to the second and the third embedded isolation film regions, and the opening is filled with an isolation film.

Semiconductor structure and method for manufacturing the same

A semiconductor structure and a method for manufacturing the same are disclosed. The method comprises: disposing a first dielectric material layer on a first semiconductor layer and defining openings in the first dielectric material layer; epitaxially growing a second semiconductor layer on the first semiconductor layer via the openings defined in the first dielectric material layer, wherein the second semiconductor layer and the first semiconductor layer comprise different materials from each other; and forming plugs of a second dielectric material in the second semiconductor layer at positions where the openings are defined in the first dielectric material layer and also at middle positions between adjacent openings. According to embodiments of the disclosure, defects occurring during the heteroepitaxial growth can be effectively suppressed.

Semiconductor device and method for forming the same

A semiconductor device and a method for forming the same are disclosed. In a method for forming the semiconductor substrate including a cell region and a peripheral region, a guard pattern defined by an epitaxial growth layer located at the edge part between the cell region and the peripheral region is formed. As the guard pattern is not damaged by an oxidation process, a bias leakage path between an N-well bias and a P-well bias of the peripheral region is prevented from occurring Reliability of a gate oxide film may be increased, resulting in an increased production yield of the semiconductor device and implementation of stable voltage and current characteristics.

Dummy cell pattern for improving device thermal uniformity

A dummy cell pattern includes a dummy diffusion pattern disposed within a predetermined region A; a trench isolation pattern encompassing the dummy diffusion pattern in the predetermined region A; a first dummy gate pattern disposed on the dummy diffusion pattern with two ends of the first dummy gate pattern extending above the trench isolation pattern, thereby forming overlapping areas C 1 and C 2; and a second dummy gate pattern directly on the trench isolation pattern forming an overlapping area C therebetween, wherein the combination of C 1, C 2 and C is about 5%-20% of the predetermined region A.

Semiconductor device and method of manufacturing semiconductor device

A semiconductor device includes a first device isolation insulating film defining a first region, a first conductive layer of a first conductivity type formed in the first region, a semiconductor layer formed above the semiconductor substrate and including a second conductive layer of the first conductivity type connected to the first conductive layer and a third conductive layer of the first conductivity type connected to the first conductive layer, a second device isolation insulating film formed in the semiconductor layer and isolating the second conductive layer and the third conductive layer from each other, a gate insulating film formed above the second conductive layer, and a gate electrode formed above the gate insulating film and electrically connected to the first conductive layer via the third conductive layer.

Reverse Tone STI Formation

A method includes forming a hard mask over a substrate, patterning the hard mask to form a first plurality of trenches, and filling a dielectric material into the first plurality of trenches to form a plurality of dielectric regions. The hard mask is removed from between the plurality of dielectric regions, wherein a second plurality of trenches is left by the removed hard mask. An epitaxy step is performed to grow a semiconductor material in the second plurality of trenches.

METHODS FOR FABRICATING SEMICONDUCTOR DEVICES

Provided are methods for fabricating a semiconductor device. The methods include forming a hard mask pattern on a semiconductor substrate, forming a first trench having a first width and a second trench having a second width on the semiconductor substrate using the hard mask pattern as a mask, forming an oxide film on the hard mask pattern and the first and second trenches, forming first and second isolation films on the first and second trenches by planarizing the oxide film until the hard mask pattern is exposed, and etching the first isolation film by a first thickness by performing dry cleaning on the semiconductor substrate and etching the second isolation film by a second thickness different from the first thickness. 1. A method for fabricating a semiconductor device , the method comprising:forming a hard mask pattern on a semiconductor substrate;forming a first trench having a first width and a second trench having a second width on the semiconductor substrate using the hard mask pattern as a mask;forming an oxide film on the hard mask pattern and the first and second trenches;forming first and second isolation films on the first and second trenches by planarizing the oxide film to expose the hard mask pattern; andetching the first isolation film by a first thickness by performing a dry cleaning process on the semiconductor substrate and etching the second isolation film by a second thickness that is different from the first thickness of the first isolation film.2. The method of claim 1 , wherein the second width of the second trench is greater than the first width of the first trench claim 1 , and the second thickness of the second isolation film is greater than the first thickness of the first isolation film.3. The method of claim 2 , wherein the etched first and second isolation films have an isotropic etching profile.4. The method of claim 1 , wherein performing the dry etching process on the semiconductor substrate comprises:injecting an etching gas, a ...

Structure and method for reduction of vt-w effect in high-k metal gate devices

A substrate is provided. An STI trench is formed in the substrate. A fill material is formed in the STI trench and then planarized. The substrate is exposed to an oxidizing ambient, growing a liner at a bottom and sidewalls of the STI trench. The liner reduces the Vt-W effect in high-k metal gate devices.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

To provide a semiconductor device provided with an element isolation structure capable of hindering an adverse effect on electric characteristics of a semiconductor element, and a method of manufacturing the same. The thickness of a first silicon oxide film left in a shallow trench isolation having a relatively narrow width is thinner than the first silicon oxide film left in a shallow trench isolation having a relatively wide width. A second silicon oxide film (an upper layer) having a relatively high compressive stress by an HDP-CVD method is more thickly laminated over the first silicon oxide film in a lower layer by a thinned thickness of the first silicon oxide film. The compressive stress of an element isolation oxide film finally formed in a shallow trench isolation having a relatively narrow width is more enhanced. 16-. (canceled)7. A method of manufacturing a semiconductor device comprising the steps of:forming a mask layer for forming a trench in the main surface of a semiconductor substrate;forming a first trench having a first width and a prescribed depth so as to sandwich a first region in the semiconductor substrate, and forming a second trench having a second width narrower than the first width and a prescribed depth so as to sandwich a second region in the semiconductor substrate, by etching the semiconductor substrate using the mask layer as a mask;forming a first insulating film over the semiconductor substrate so as to be embedded in the first trench and the second trench;annealing the first insulating film;removing the first insulating film over the surface of the mask layer so as to be left in the first trench and the second trench;lowering the position of the upper surface of the first insulating film left in the first trench, and lowering the position of the upper surface of the first insulating film left in the second trench than the position of the upper surface of the first insulating film left in the first trench by a wet etching of the ...

Plasma processing method

The present invention provides a plasma processing method in which sideetching and microloading can be suppressed in a plasma processing method of forming trenches with a mask having a minimum opening width of 20 nm or less. The plasma processing method of the present invention is characterized by including the steps of forming trenches by plasma etching, forming a nitride film on sidewalls of trenches using plasma, and forming an oxide film on sidewalls and bottom surfaces of the trenches using plasma.

MEMORY DEVICE AND METHOD OF FABRICATING THE SAME

A memory device includes a mesa structure and a word line. The mesa structure, having two opposite side surfaces, includes at least one pair of source/drain regions and at least one channel base region corresponding to the pair of source/drain regions formed therein. The word line includes two linear sections and at least one interconnecting portion. Each linear section extends on the respective side surface of the mesa structure, adjacent to the channel base region. The at least one interconnecting portion penetrates through the mesa structure, connecting the two linear sections. 1. A method of fabricating a memory device , comprising steps of:filling a first dielectric material in a plurality of deep trenches and shallow trenches to separately form a plurality of deep isolations and a plurality of shallow isolations in a substrate, wherein each shallow trench is formed between two adjacent ones of the plurality of the deep trenches;forming a plurality of depressions transverse to the deep isolations, wherein two adjacent ones of the plurality of depressions define a mesa structure, and the depression is wider than the mesa structure;filling the plurality of depressions with a second dielectric material;removing a portion of the first dielectric material from the shallow trenches and the deep trenches and a portion of the second dielectric material from the depressions;forming a conductive layer in the shallow trenches, the deep trenches and the depressions; andremoving a portion of the conductive layer in the depression to form two word lines.2. The method of claim 1 , wherein the forming of the plurality of deep isolations in the substrate comprises steps of:forming a mask on the substrate, wherein the mask includes a plurality of lines, each having a width, spaced apart by a distance equal to the width;forming first sidewall spacers on sidewalls of the lines of the mask, wherein the sidewall spacers facing each other are spaced by a distance equal to one half of ...

Methods of forming varying depth trenches in semiconductor devices

A method of forming trenches in a semiconductor device includes forming an etchant barrier layer above a first portion of a semiconductor layer. A first trench is etched in a second portion of the semiconductor layer using a first etchant. The second portion of the semiconductor layer is not disposed underneath the etchant barrier layer. The etchant barrier layer is etched through using a second etchant that does not substantially etch the semiconductor layer. A second trench is etched in the first portion of the semiconductor layer using a third etchant. The third etchant also extends a depth of the first trench.

Structure and method for finfet integrated with capacitor

The present disclosure provides one embodiment of a semiconductor structure that includes a semiconductor substrate having a first region and a second region; a shallow trench isolation (STI) feature formed in the semiconductor substrate. The STI feature includes a first portion disposed in the first region and having a first thickness T 1 and a second portion disposed in the second region and having a second thickness T 2 greater than the first depth, the first portion of the STI feature being recessed from the second portion of the STI feature. The semiconductor structure also includes a plurality of fin active regions on the semiconductor substrate; and a plurality of conductive features disposed on the fin active regions and the STI feature, wherein one of the conductive features covers the first portion of the STI feature in the first region.

SOI DEVICE WITH DTI AND STI

A method of forming an SOI structure which includes providing a semiconductor on insulator (SOI) substrate having an SOI layer, an intermediate buried oxide (BOX) layer and a bottom substrate; patterning the SOI layer to form first and second openings in the SOI layer; extending the first openings into the bottom substrate; enlarging the first openings within the bottom substrate; filling the first and second openings with an insulator material to form deep trench isolations (DTIs) from the first openings and shallow trench isolations (STIs) from the second openings; implanting in the bottom substrate between the DTIs to form wells; and forming semiconductor devices in the SOI layer between the DTIs with each semiconductor device being separated from an adjacent semiconductor device by an STI. 1. A method of forming an SOI structure comprising:providing a semiconductor on insulator (SOI) substrate having an SOI layer, an intermediate buried oxide (BOX) layer and a bottom substrate;patterning the SOI layer to form first and second openings in the SOI layer;extending the first openings into the bottom substrate;enlarging the first openings within the bottom substrate;filling the first and second openings with an insulator material to form deep trench isolations (DM) from the first openings and shallow trench isolations (STIs) from the second openings;implanting in the bottom substrate between the DTIs to form wells; andforming semiconductor devices in the SOI layer between the DTIs with each semiconductor device being separated from an adjacent semiconductor device by an STI.2. The method of wherein the SOI substrate is an extremely thin SOI substrate.3. The method of wherein the SOI layer has a thickness of 3 to 15 nanometers.4. The method of wherein the BOX layer has a thickness of 10 to 140 nanometers.5. The method of wherein extending the first openings into the bottom substrate includes etching the BOX layer and the substrate by an etching process that leaves a ...

SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD

A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having a first region and an adjacent second region, and etching the semiconductor substrate to form a plurality of first trenches in the first region and a second trench in the second region. Fins are formed in between the adjacent first trenches. The width of the second trench is greater than the width of the first trench. The method also includes filling the first trenches with a first isolation material to form first insolation structures, and form sidewall spacers inside the second trench. Further, the method includes forming a third trench in the second trench by etching the exposed semiconductor substrate on the bottom of the second trench using the sidewall spacers as an etching mask, and filling the second trench and the third trench using a second isolation material to form a second isolation structure. 1. A method for fabricating a semiconductor structure , comprising:providing a semiconductor substrate having a first region and an adjacent second region;etching the semiconductor substrate to form a plurality of first trenches in the first region and at least a second trench in the second region using a hard mask layer as an etching mask, the width of the second trench being greater than that of the first trench;filling the first trenches and the second trench using a first isolation material to form a plurality of first isolation structures in the first trenches and sidewall spacers in the second trench, respectively, within the same process;etching the exposed semiconductor substrate on the bottom of the second trench to form a third trench using the sidewall spacer as an etching mask; andfilling the second trench and the third trench using a second isolation material to form a second isolation structure.2. The method according claim 1 , wherein the providing the semiconductor substrate further includes: 'wherein the hard mask layer ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Disclosed is a semiconductor device including: a semiconductor substrate; first and second element isolating trenches that are formed in one main surface of the semiconductor substrate separately from each other; a first insulating material that is formed within the first element isolating trench; a plurality of first element formation regions that are surrounded by the first element isolating trench; first semiconductor elements that are respectively formed in the first element formation regions; a second insulating material that is formed within the second element isolating trench; a second element formation region that is surrounded by the second element isolating trench; a second semiconductor element that is formed in the second element formation region; and a stress relaxation structure that is formed between the first element isolating trench and the second element isolating trench. 1. A semiconductor device comprising:a semiconductor substrate;first and second element isolating trenches that are formed in one main surface of the semiconductor substrate separately from each other;a first insulating material that is formed within the first element isolating trench;a plurality of first element formation regions that are surrounded by the first element isolating trench;first semiconductor elements that are respectively formed in the first element formation regions;a second insulating material that is formed within the second element isolating trench;a second element formation region that is surrounded by the second element isolating trench;a second semiconductor element that is formed in the second element formation region; anda stress relaxation structure that is formed between the first element isolating trench and the second element isolating trench.2. The semiconductor device according to claim 1 , wherein the stress relaxation structure includes a trench formed in the one main surface so as to be inclined at an angle θ (0°<θ<90°) with respect to the first ...

Undercut insulating regions for silicon-on-insulator device

A method of making a silicon-on-insulator (SOI) semiconductor device includes etching an undercut isolation trench into an SOI substrate, the SOI substrate comprising a bottom substrate, a buried oxide (BOX) layer formed on the bottom substrate, and a top SOI layer formed on the BOX layer, wherein the undercut isolation trench extends through the top SOI layer and the BOX layer and into the bottom substrate such that a portion of the undercut isolation trench is located in the bottom substrate underneath the BOX layer. The undercut isolation trench is filled with an undercut fill comprising an insulating material to form an undercut isolation region. A field effect transistor (FET) device is formed on the top SOI layer adjacent to the undercut isolation region, wherein the undercut isolation region extends underneath a source/drain region of the FET.

Forming Inter-Device STI Regions and Intra-Device STI Regions Using Different Dielectric Materials

An integrated circuit structure includes a substrate having a first portion in a first device region and a second portion in a second device region; and two insulation regions in the first device region and over the substrate. The two insulation regions include a first dielectric material having a first k value. A semiconductor strip is between and adjoining the two insulation regions, with a top portion of the semiconductor strip forming a semiconductor fin over top surfaces of the two insulation regions. An additional insulation region is in the second device region and over the substrate. The additional insulation region includes a second dielectric material having a second k value greater than the first k value.

SEMICONDUCTOR DEVICE WITH BURIED BITLINE AND METHOD FOR FABRICATING THE SAME

A method for fabricating a semiconductor device includes forming active regions which are separated by a plurality of first trenches, forming supports which fill the first trenches; etching the active regions and defining second trenches which are shallower than the first trenches, forming spacers on sidewalls of the second trenches, etching bottoms of the second trenches and defining third trenches, forming punch-through preventing patterns which fill lower portions of the third trenches, etching sidewalls which are not protected by the punch-through preventing patterns and the spacers, and forming recessed sidewalls which face each other, and forming buried bit lines in the recessed sidewalls. 1. A method for fabricating a semiconductor device , the method comprising:forming active regions on a semiconductor substrate, the active regions being separated by a plurality of first trenches;forming a support in each first trench of the plurality of first trenches;defining, by etching the active regions, second trenches that are shallower than the plurality of first trenches; andforming a pair of buried bit lines in each of the second trenches.2. The method of claim 1 , wherein claim 1 , after forming the pair of buried bit lines claim 1 , the method further comprises:forming, in each of the second trenches, an interlayer dielectric layer defining an air gap.3. The method of claim 1 , wherein forming the supports comprises:forming a dielectric layer on an entire surface to gapfill the first trenches; andplanarizing the dielectric layers.4. The method of claim 1 , wherein defining the second trenches comprises:defining second trenches to divide each of the active regions;forming spacers on sidewalls of the second trenches; andetching bottoms of the second trenches; andforming recessed sidewalls in each of the active regions.5. The method of claim 4 , wherein forming the pair of buried bit lines comprises:forming a conductive layer on a surface defining the second ...

Method of manufacturing solid-state image sensor

A method of manufacturing a solid-state image sensor having a pixel region and a peripheral circuit region, includes forming an oxide film on a semiconductor substrate, forming an insulating film on the oxide film, forming a first opening in the insulating film and the oxide film in the peripheral circuit region, forming a trench in the semiconductor substrate in the peripheral circuit region by etching the semiconductor substrate through the first opening using the insulating film as a mask, forming a second opening in the insulating film to penetrate through the insulating film in the pixel region and to reach a predetermined depth of the oxide film, and forming insulators in the trench and the second opening.

Integrated diode array and corresponding manufacturing method

An integrated diode array and a corresponding manufacturing method are provided. The integrated diode array includes a substrate having an upper side, and a plurality of blocks of several diodes, which are positioned in a planar manner and are suspended at the substrate above a cavity situated below them in the substrate. The blocks are separated from one another by respective gaps, and within a specific block, the individual diodes are electrically insulated from one another by first STI trenches situated between them.

SELECTIVE ETCHES FOR REDUCING CONE FORMATION IN SHALLOW TRENCH ISOLATIONS

Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation. 1. An integrated circuit , comprising:a semiconductor substrate having a surface;a first isolation structure along the surface, the first isolation structure having a first feature dimension and a first sidewall slope;a second isolation structure along the surface, the second isolation structure having a second feature dimension greater than the first feature dimension, the second isolation structure having a second sidewall slope within a 15 degrees of deviation from the first sidewall slope;a transistor structure laterally isolated by the first isolation structure; anda circuit component integrating the second isolation structure.2. The integrated circuit of claim 1 , wherein the circuit component includes at least one of a resistor claim 1 , an inductor claim 1 , or a capacitor.3. The integrated circuit of claim 1 , wherein the circuit component includes a gate structure of a lateral diffused MOS transistor.4. The integrated circuit of claim 1 , wherein the transistor structure includes at least one of a MOS transistor or a bipolar ...

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, and a third region; forming a plurality of spacers on the first region, the second region, and the third region; forming a first patterned mask to cover the spacers on the first region and the second region; and removing the spacers on the third region. 1. A method for fabricating semiconductor device , comprising:providing a substrate having a first region, a second region, and a third region;forming a plurality of spacers on the first region, the second region, and the third region;forming a first patterned mask to cover the spacers on the first region and the second region; andremoving the spacers on the third region.2. The method of claim 1 , further comprising:forming a pad oxide on the substrate;forming a pad nitride on the pad oxide;forming a plurality of mandrels on the pad nitride;forming a cap layer on the mandrels;removing part of the cap layer; andremoving the mandrels for forming the spacers on the first region, the second region, and the third region.3. The method of claim 1 , further comprising:removing the first patterned mask;forming a second patterned mask on the third region;removing part of the substrate to form first fin-shaped structures on the first region and second fin-shaped structures on the second region;forming a third patterned mask on part of the first fin-shaped structures and part of the second fin-shaped structures;removing part of the first fin-shaped structures and part of the second fin-shaped structures; andremoving part of the substrate to form a first base under the first fin-shaped structures, a second base under the second fin-shaped structures, and a first trench between the first base and the second base.4. The method of claim 3 , further comprising:removing the second patterned mask and the third patterned mask;forming a fourth patterned mask on the third region, the ...

UNDERCUT INSULATING REGIONS FOR SILICON-ON-INSULATOR DEVICE

A method of making a silicon-on-insulator (SOI) semiconductor device includes etching an undercut isolation trench into an SOI substrate, the SOI substrate comprising a bottom substrate, a buried oxide (BOX) layer formed on the bottom substrate, and a top SOI layer formed on the BOX layer, wherein the undercut isolation trench extends through the top SOI layer and the BOX layer and into the bottom substrate such that a portion of the undercut isolation trench is located in the bottom substrate underneath the BOX layer. The undercut isolation trench is filled with an undercut fill comprising an insulating material to form an undercut isolation region. A field effect transistor (FET) device is formed on the top SOI layer adjacent to the undercut isolation region, wherein the undercut isolation region extends underneath a source/drain region of the FET. 1. A silicon-on-insulator (SOI) semiconductor device , comprising:an SOI substrate comprising a bottom substrate, a buried oxide (BOX) layer formed on the bottom substrate, and a top SOI layer formed on the BOX layer;a field effect transistor (FET) device located on the top SOI layer; andan undercut isolation region located in the SOI substrate adjacent to the FET device, wherein the undercut isolation region extends through the top SOI layer and the BOX layer and into the bottom substrate underneath the BOX layer, such that a portion of the undercut isolation region is underneath a source/drain region of the FET, wherein the undercut isolation region comprises an undercut fill comprising an oxide material.2. The device of claim 1 , further comprising an oxidized region in the bottom substrate located between the undercut isolation region and the bottom substrate.3. The device of claim 1 , wherein the undercut isolation region further comprises an undercut isolation region liner located between the undercut fill and the bottom substrate.4. The device of claim 3 , wherein the undercut isolation region liner comprises one ...

Semiconductor device and method of manufacturing the same

In an SOI substrate having a semiconductor layer formed on the semiconductor substrate via an insulating layer, a MISFET is formed in each of the semiconductor layer in an nMIS formation region and a pMIS formation region. In power feeding regions, the semiconductor layer and the insulating layer are removed. In the semiconductor substrate, a p-type semiconductor region is formed so as to include the nMIS formation region and one of the power feeding regions, and an n-type semiconductor region is formed so as to include a pMIS formation region and the other one of the power feeding regions. In the semiconductor substrate, a p-type well having lower impurity concentration than the p-type semiconductor region is formed so as to contain the p-type semiconductor region, and an n-type well having lower impurity concentration than the n-type semiconductor region is formed so as to contain the n-type semiconductor region.

Integrated Circuit of Driving Device and Manufacture Method thereof

An integrated circuit for a driving device is disclosed. The integrate circuit includes a substrate comprising a high-voltage area and a low-voltage area; a plurality of first trenches, formed in the high-voltage area; a plurality of first isolations, formed in the plurality of first trenches of the high-voltage area; a plurality of second trenches, formed in the low-voltage area; and a plurality of second isolations, formed in the plurality of second trenches of the low-voltage area; wherein a depth difference exists between each of the plurality of first trenches and each of the plurality of second trenches. 1. An integrated circuit for a driving device , the integrate circuit comprising:a substrate comprising a high-voltage area and a low-voltage area;a plurality of first trenches, formed in the high-voltage area;a plurality of first isolations, formed in the plurality of first trenches of the high-voltage area;a plurality of second trenches, formed in the low-voltage area; anda plurality of second isolations, formed in the plurality of second trenches of the low-voltage area;wherein a depth difference exists between each of the plurality of first trenches and each of the plurality of second trenches.2. The integrated circuit of claim 1 , wherein the plurality of first isolations and the plurality of second isolations are shallow trench isolations (STIs).3. The integrated circuit of claim 1 , wherein the depth difference is between 500 angstroms and 8000 angstroms.4. The integrated circuit of claim 1 , wherein a height difference exists between each of the plurality of first isolations and each of the plurality of second isolations.5. The integrated circuit of claim 4 , wherein the height difference is between 150 angstroms and 450 angstroms.6. The integrated circuit of claim 1 , wherein the high-voltage area comprises a plurality of circuit components operating in a high-voltage range claim 1 , the low-voltage area comprises a plurality of circuit components ...

Fin field effect transistor and method of manufacturing the same

A fin field effect transistor (FinFET) with improved electrical performance and a method of manufacturing the same are disclosed. A FinFET comprises a substrate having a top surface and an insulation. At least a recessed fin is extended upwardly from the top surface of the substrate, and at least a gate stack formed above the substrate, wherein the gate stack is extended perpendicularly to an extending direction of the recessed fin, and the recessed fin is outside the gate stack. The insulation comprises a lateral portion adjacent to the recessed fin, and a central portion contiguous to the lateral portion, wherein a top surface of the lateral portion is higher than a top surface of the central portion. A top surface of the recessed fin is lower than the top surface of the central portion of the insulation.

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE COMPRISING A DEEP TRENCH ISOLATION STRUCTURE AND A TRAP RICH ISOLATION STRUCTURE IN A SUBSTRATE

A method for fabricating semiconductor device comprising the steps of: forming a first trench and a second trench in a substrate; forming a liner in the first trench and the second trench; forming a first patterned mask on the substrate to cover the second trench; removing the liner in the first trench; removing the first patterned mask; and forming an insulating layer in the first trench and the second trench to form a trap rich isolation structure in the first trench and a deep trench isolation structure in the second trench. 1. A method for fabricating semiconductor device , comprising:forming a first trench and a second trench in a substrate;forming a liner in the first trench and the second trench;forming a first patterned mask on the substrate to cover the second trench;removing the liner in the first trench;removing the first patterned mask; andforming an insulating layer in the first trench and the second trench to form a trap rich isolation structure in the first trench and a deep trench isolation structure in the second trench.2. The method of claim 1 , further comprising:forming a mask layer on the substrate; andremoving part of the mask layer and part of the substrate to form a second patterned mask on the substrate and the first trench and the second trench in the substrate.3. The method of claim 2 , wherein the mask layer comprises:a first mask layer on the substrate; anda second mask layer on the first mask layer.4. The method of claim 3 , wherein the first mask layer comprises silicon oxide and the second mask layer comprises silicon nitride.5. The method of claim 1 , further comprising performing an oxidation process to oxidize sidewalls of the first trench and the second trench for forming the liner.6. The method of claim 5 , wherein the liner comprises silicon oxide.7. The method of claim 2 , further comprising:forming the first patterned mask on the second patterned mask;using the first patterned mask as mask to remove the liner in the first ...

SELECTIVE ETCHES FOR REDUCING CONE FORMATION IN SHALLOW TRENCH ISOLATIONS

Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation. 1. A method , comprising:etching a first shallow trench in a first region of a substrate with a first etching parameter includes a first bias power; andetching a second shallow trench in a second region of the substrate outside the first region with a second etching parameter different from the first etching parameter, the second etching parameter includes a second bias power higher than the first bias power.2. The method of claim 1 , wherein:the first etching parameter includes a first silicon selectivity ratio; andthe second etching parameter includes a second silicon selectivity ratio, the second silicon selectivity ratio lower than the first silicon selectivity ratio.3. The method of claim 2 , wherein:the first silicon selectivity ratio is greater than 10; andthe second silicon selectivity ratio is less than 5.4. The method of claim 2 , wherein:the first silicon selectivity ratio defines a first rate of removing a silicon material over removing an etch retardant including at least one of an oxide material, a nitride material, and a ...

Method for forming an integrated circuit and an integrated circuit

A method for forming an integrated circuit (IC) and an IC are disclosed. The method for forming the IC includes: forming an isolation structure separating a memory semiconductor region from a logic semiconductor region; forming a memory cell structure on the memory semiconductor region; forming a memory capping layer covering the memory cell structure and the logic semiconductor region; performing a first etch into the memory capping layer to remove the memory capping layer from the logic semiconductor region, and to define a slanted, logic-facing sidewall on the isolation structure; forming a logic device structure on the logic semiconductor region; and performing a second etch into the memory capping layer to remove the memory capping layer from the memory semiconductor, while leaving a dummy segment of the memory capping layer that defines the logic-facing sidewall.

Structure and Method for FinFET Device with Asymmetric Contact

The present disclosure provides one embodiment of a method of forming an integrated circuit structure. The method includes forming a shallow trench isolation (STI) structure in a semiconductor substrate of a first semiconductor material, thereby defining a plurality of fin-type active regions separated from each other by the STI structure; forming gate stacks on the fin-type active regions; forming an inter-layer dielectric (ILD) layer filling in gaps between the gate stacks; patterning the ILD layer to form a trench between adjacent two of the gate stacks; depositing a first dielectric material layer that is conformal in the trench; filling the trench with a second dielectric material layer; patterning the second dielectric material layer to form a contact opening; and filling a conductive material in the contact opening to form a contact feature. 1. A semiconductor structure , comprising:an active region on a semiconductor substrate;a gate stack disposed on the active region;an elongated contact feature landing on a source/drain feature; anda first dielectric material layer disposed on sidewalls of the contact feature and free from ends of the elongated contact feature, wherein the sidewalls of the elongated contact feature are parallel with the gate stack.2. The semiconductor structure of claim 1 , whereinthe gate stack includes a gate dielectric feature, a gate electrode on the gate dielectric feature, and a spacer on sidewalls of the gate electrode; andthe first dielectric material layer is interposed between the spacer and the contact feature and directly contacts the spacer and the contact feature.3. The semiconductor structure of claim 2 , wherein the gate dielectric feature includes a first high k dielectric material and the first dielectric material layer includes a second high-k dielectric material different from the first high k dielectric material in composition.4. The semiconductor structure of claim 3 , wherein the dielectric material layer is ...

INSULATED GATE TYPE SEMICONDUCTOR DEVICE

An insulating gate type semiconductor device being capable of easily depleting an outer periphery region is provided. The insulating gate type semiconductor device includes: first to fourth outer periphery trenches formed in a front surface of a semiconductor substrate; insulating layers located in the outer periphery trenches; fifth semiconductor regions being of a second conductive type and formed in ranges exposed to bottom surfaces of the outer periphery trenches; and a connection region connecting the fifth semiconductor region exposed to the bottom surface of the second outer periphery trench to the fifth semiconductor region exposed to the bottom surface of the third outer periphery trench. A clearance between the second and third outer periphery trenches is wider than each of a clearance between the first and second outer periphery trenches and a clearance between the third and fourth outer periphery trenches. 1. An insulated gate type semiconductor device , comprising:a semiconductor substrate;a front surface electrode formed on a front surface of the semiconductor substrate; anda rear surface electrode formed on a rear surface of the semiconductor substrate;whereinthe insulated gate type semiconductor device is configured to switch current between the front surface electrode and the rear surface electrode,the insulated gate type semiconductor device further comprises:a first semiconductor region being of a first conductive type and connected to the front surface electrode;a second semiconductor region being of a second conductive type and in contact with the first semiconductor region;a third semiconductor region being of the first conductive type and separated from the first semiconductor region by the second semiconductor region;a plurality of gate trenches formed in the front surface of the semiconductor substrate and penetrating the second semiconductor region to reach the third semiconductor region;gate insulating films and gate electrodes located in ...

METHODS OF FORMING AN ISOLATION STRUCTURE AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING THE SAME

A method of forming an isolation structure, wherein a hard mask is formed on a first region and a second region of a substrate; the substrate is etched using the hard mask as an etching mask to form a plurality of first active patterns in the first region and a plurality of second active patterns in the second region, a first trench between the first active patterns having a first trench width, and a second trench between the second active patterns having a second trench width smaller than the first trench width; a first oxide layer is formed on the hard mask and the first and second trenches; the first oxide layer is conformally formed on an inner wall of the first trench and filling the second trench; a polysilicon layer is conformally formed on the first oxide layer and a spin-on-dielectric (SOD) layer is formed on the polysilicon layer to fill the first trench; and the SOD layer and the polysilicon layer are annealed using an oxygen-containing gas so that the SOD layer and the polysilicon layer are transformed into a second oxide layer and a third oxide layer, respectively, in the first trench, resulting in a semiconductor device with an isolation structure with good isolation characteristics. 1. A method of manufacturing an isolation structure , the method comprising:forming a hard mask on a first region and a second region of a substrate;etching the substrate using the hard mask as an etching mask to form a plurality of first active patterns in the first region and a plurality of second active patterns in the second region, a first trench between the first active patterns having a first trench width, and a second trench between the second active patterns having a second trench width smaller than the first trench width;forming a first oxide layer on the hard mask and on the first and second trenches, the first oxide layer being conformally formed on an inner wall of the first trench and filling the second trench;conformally forming a polysilicon layer on the ...

FINFET DEVICE

The present disclosure provides many different embodiments of a FinFET device that provide one or more improvements over the prior art. In one embodiment, a FinFET includes a semiconductor substrate and a plurality of fins having a first height and a plurality of fin having a second height on the semiconductor substrate. The second height may be less than the first height. 1. A device comprising:a first fin structure disposed over a substrate and having a first height over a surface of the substrate;a dummy semiconductor structure adjacent the first fin structure and disposed over the substrate, wherein the dummy semiconductor structure has a sidewall extending from the surface of the substrate to a second height that is less than the first height;an isolation structure extending from the first fin structure to the dummy semiconductor structure;a source/drain structure disposed over the first fin structure, wherein the source/drain has a bottommost point disposed a first distance from the surface of the substrate; andan interlayer dielectric (ILD) layer disposed over a top surface of the dummy semiconductor structure and the source/drain structure, wherein the interlayer dielectric (ILD) layer at least one region disposed a second distance from the surface of the substrate, wherein the second distance is less than the first distance;and wherein dielectric material from at least one of the ILD layer or the isolation structure at least partially covers the top surface of the dummy semiconductor structure, the top surface of the dummy semiconductor structure facing away from the substrate.2. The device of claim 1 , wherein the ILD layer interfaces a top surface of the dummy semiconductor structure.3. The device of claim 2 , wherein the ILD layer includes a combination of dielectric materials.4. The device of claim 1 , wherein the source/drain structure has a terminus edge over the isolation structure.5. The device of claim 1 , wherein the isolation structure includes a ...

Undercut insulating regions for silicon-on-insulator device

A method of making a silicon-on-insulator (SOI) semiconductor device includes etching an undercut isolation trench into an SOI substrate, the SOI substrate comprising a bottom substrate, a buried oxide (BOX) layer formed on the bottom substrate, and a top SOI layer formed on the BOX layer, wherein the undercut isolation trench extends through the top SOI layer and the BOX layer and into the bottom substrate such that a portion of the undercut isolation trench is located in the bottom substrate underneath the BOX layer. The undercut isolation trench is filled with an undercut fill comprising an insulating material to form an undercut isolation region. A field effect transistor (FET) device is formed on the top SOI layer adjacent to the undercut isolation region, wherein the undercut isolation region extends underneath a source/drain region of the FET.

SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate having a first region and a second region, the first region including memory cells, and the second region including transistors for driving the memory cells, and device isolation regions disposed within the substrate to define active regions of the substrate. The active regions include a first guard active region surrounding the first region, a second guard active region surrounding a portion of the second region, and at least one dummy active region disposed between the first guard active region and the second guard active region. 1. A semiconductor device , comprising:a substrate having a first region and a second region, the first region including memory cells, and the second region including transistors for driving the memory cells; anddevice isolation regions disposed within the substrate to define active regions of the substrate,wherein the active regions include:a first guard active region surrounding the first region;a second guard active region surrounding a portion of the second region; andat least one dummy active region disposed between the first guard active region and the second guard active region,wherein an upper surface of the at least one dummy active region is entirely covered by an insulating layer, andwherein the second guard active region is closest to the first guard active region among the active regions disposed in the second region, except for the at least one dummy active region.2. The semiconductor device of claim 1 , wherein the substrate includes:a first well disposed in the first region, the first well including first conductivity-type impurities; anda second well disposed within the substrate to surround the first well, the second well including the first guard active region, and the second well including second conductivity-type impurities.3. The semiconductor device of claim 1 , wherein the second guard active region surrounds at least a transistor of the second region that is closest to ...

INTEGRATED COMPUTING STRUCTURES FORMED ON SILICON

The present disclosure includes methods of forming, and semiconductor structures for, integrated computing structures formed on silicon. An example method includes forming, on a silicon semiconductor material, an integrated computing structure by forming a number of complementary metal-oxide-semiconductor (CMOS) devices including a plurality of materials, forming a non-volatile memory (NVM) device including a plurality of materials, and forming the plurality of materials of the CMOS devices and the plurality of materials of the NVM device from a plurality of same materials shared at a corresponding plurality of positions within the structure. A particular function is provided by each of the plurality of same materials at the corresponding plurality of positions. 116.-. (canceled)17. A semiconductor structure , comprising:a silicon semiconductor material comprising an integrated computing structure formed thereon; and a p-channel field effect transistor (P-FET) that comprises a plurality of materials of a gate insulator stack and associated components;', 'an n-channel FET (N-FET) that comprises a plurality of materials of a gate insulator stack and associated components; and', 'a non-volatile memory (NVM) device that comprises a plurality of materials of a device stack and associated components;, 'wherein a plurality of devices in the integrated computing structure comprises an interface stabilizing material of the stacks contiguous to the silicon semiconductor material;', 'a metal gate interface component contiguous to the metal gate component and between the interface stabilizing material and the metal gate component; and', 'a dielectric material with a high dielectric constant configured to provide a tunneling function formed contiguous to the interface stabilizing material and between the metal gate interface component and the interface stabilizing material, wherein the dielectric material is different from the interface stabilizing material., 'wherein the ...

Semiconductor device and method of fabricating the same

A semiconductor device and method of fabricating the same are provided. The semiconductor device includes a substrate having a trench and an etching stop layer. The etching stop layer is disposed in the substrate and surrounds the bottom surface and a portion of a sidewall of the trench.

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

A semiconductor device is provided. The semiconductor device includes a semiconductor substrate and a first gate stack. An isolation feature is formed in the semiconductor substrate, and a cell region and a peripheral region adjacent to the cell region are defined in the semiconductor substrate. The first gate stack is disposed on the peripheral region of the semiconductor substrate. The first gate stack includes a first dielectric layer and a gate electrode layer disposed on the first dielectric layer and covering a top surface of the first dielectric layer. The first dielectric layer is disposed on the semiconductor substrate and has a concave profile. 1. A semiconductor device , comprising:a semiconductor substrate in which an isolation feature is formed, wherein a cell region and a peripheral region adjacent to the cell region are defined in the semiconductor substrate; and a first dielectric layer disposed on the semiconductor substrate, wherein the first dielectric layer has a concave profile; and', 'a gate electrode layer disposed on the first dielectric layer and covering a top surface of the first dielectric layer., 'a first gate stack disposed on the peripheral region of the semiconductor substrate, wherein the first gate stack comprises2. The semiconductor device of claim 1 , wherein the first dielectric layer further comprises:a concave dielectric layer disposed on the semiconductor substrate; anda high-k dielectric layer disposed on the concave dielectric layer and conformal to a top surface of the concave dielectric layer.3. The semiconductor device of claim 2 , wherein the concave dielectric layer comprises:two edges portion; anda middle portion disposed between the two edges portion, wherein a thickness of each of the edges portion is greater than a thickness of the middle portion.4. The semiconductor device of claim 1 , further comprising a second gate stack adjacent to the first gate stack in the peripheral region claim 1 , wherein the second gate ...

METHOD FOR DEPOSITING SILICON-FREE CARBON-CONTAINING FILM AS GAP-FILL LAYER BY PULSE PLASMA-ASSISTED DEPOSITION

A film having filling capability is deposited by forming a viscous polymer in a gas phase by striking an Ar, He, or Nplasma in a chamber filled with a volatile hydrocarbon precursor that can be polymerized within certain parameter ranges which define mainly partial pressure of precursor during a plasma strike, and wafer temperature. 1. A method of filling a patterned recess on a surface of a substrate , the method comprising the steps of:(a) providing the substrate in a reaction space;(b) providing a precursor to the reaction space, thereby filling the recess with a gas phase precursor;(c) providing a plasma to the reaction space, thereby forming a viscous material within the recess; and(d) reducing the pressure in the reaction space, thereby causing the viscous material to flow and accumulate at a bottom of the recess;(e) repeating steps (a) through (d), thereby forming deposited material at the bottom of the recess.2. The method of claim 1 , wherein the precursor comprises one or more of a chain and a cyclic hydrocarbon having 2 or more carbons.3. The method of claim 1 , wherein the precursor comprises CxHyNz; wherein x is a natural number of 2 or more claim 1 , y is a natural number claim 1 , and z is 0 or a natural number.4. The method of claim 3 , wherein the precursor is mesitylene (1 claim 3 ,3 claim 3 ,5-trimethyl benzene).5. The method of claim 1 , wherein the temperature within the reaction space is 100° C. or lower.6. The method of claim 1 , wherein in step (c) claim 1 , the plasma is provided for 2.0 seconds or less.7. The method of claim 1 , further comprising the step of:(f) providing one or more of an Ar plasma and a He plasma in an atmosphere substantially devoid of hydrogen, oxygen, and nitrogen.8. The method of claim 7 , wherein steps (b) through (e) are repeated multiple times until a thickness of the deposited material reaches a desired final thickness.9. The method of claim 8 , wherein the desired final thickness is 200 nm or less.10. The method ...

METHOD FOR DEPOSITING SILICON-FREE CARBON-CONTAINING FILM AS GAP-FILL LAYER BY PULSE PLASMA-ASSISTED DEPOSITION

A Si-free C-containing film having filling capability is deposited by forming a viscous polymer in a gas phase by striking an Ar, He, or Nplasma in a chamber filled with a volatile hydrocarbon precursor that can be polymerized within certain parameter ranges which define mainly partial pressure of precursor during a plasma strike, and wafer temperature. 1. A method of filling a patterned recess on a surface of a substrate , the method comprising the steps of:providing a substrate comprising a recess in a reaction space;providing a silicon-free carbon-containing precursor to the reaction space, thereby filling the recesses with a gas phase precursor; andproviding a plasma to the reaction space, thereby forming a viscous material in the recess,wherein the viscous material flows in the recess and accumulates at a bottom of the recess to thereby form deposited material at the bottom of the recess, andwherein the deposited material solidifies.2. The method according to claim 1 , wherein the precursor is provided with a precursor flow as a portion of a total gas flow to the reaction space in a range of about 10% to about 100%.3. The method according to claim 1 , wherein a partial pressure of the precursor in the reaction space is greater than 200 Pa.4. The method according to claim 1 , wherein a temperature of the substrate is between about 50 ° C. to about150° C.5. The method according to claim 1 , wherein a total pressure within the reaction space is greater than 500 Pa.6. The method according to claim 1 , wherein the precursor is polymerized using the plasma.7. The method according to claim 6 , wherein an average chain length of the viscous material is greater than ten times an average chain length of a molecule of the precursor.8. The method according to claim 1 , wherein an amount of material deposited on the bottom is greater than an amount of material deposited on a sidewall of the recess.9. The method according to claim 1 , wherein the precursor comprises an ...

Method for fabricating cmos image sensors and surface treating process thereof

The present invention provides a method for fabricating a CMOS image sensor including a plurality of steps. Firstly, a substrate is provided. Then, a pixel region covering most of the substrate and a logic circuit region on a periphery of the substrate are formed. After that, at least one trench is formed in the pixel region. Next, a deposition process is performed to fill the at least one trench and cover the pixel region. Then, a planarization process is performed to expose a surface of the pixel region. A first treatment on the exposed surface of the pixel region is next performed by applying a first cleaning solution including hydrogen fluoride (HF) and ethylene glycol (EG). Besides, an amount of HF is lesser than that of EG.

Integrated circuit with double isolation of deep and shallow trench-isolation type

A silicon-on-insulator semiconductor substrate supports rows extending in a direction. Each row includes complementary MOS transistors and associated contact regions allowing back gate of the complementary MOS transistors to be biased. All transistors and associated contact regions of a given row are mutually isolated by a first trench isolation. Each row is bordered on opposed edges extending parallel to said direction by corresponding second trench isolations that are shallower than the first trench isolation.

Shallow Trench Isolation Structures in Semiconductor Device and Method for Manufacturing the Same

Shallow trench isolation structures in a semiconductor device and a method for manufacturing the same. The method include steps hereinafter. A substrate is provided with a pad oxide layer and a first patterned photoresist layer thereon. A first trench is formed in the substrate corresponding to the first patterned photoresist layer. A first dielectric layer is deposited in the first trench and on the substrate. A second patterned photoresist layer is provided to form an opening in the first dielectric layer and a second trench in the substrate corresponding to the second patterned photoresist layer. A second dielectric layer is deposited covering the first trench and the second trench in the substrate and the first dielectric layer on the substrate. The second dielectric layer is removing by chemical-mechanical polishing until the first dielectric layer is exposed. The first dielectric layer on the substrate selectively is removed.

METHOD FOR PREPARING SEMICONDUCTOR DEVICE STRUCTURE WITH FINE PATTERNS AT DIFFERENT LEVELS

The present disclosure provides a method for preparing a semiconductor device structure with fine patterns at different levels. The method includes forming a hard mask material over a substrate; etching the hardmask material to form hard mask pillars; forming spacers over sidewall surfaces of the hard mask pillars; etching the hard mask pillars and the target material by using the spacers as a mask to integrally forming a plurality of target structures, a high-level recesses in one of the plurality of target structures and a low-level recess between two target structures; and integrally forming a high-level conductive pattern in the high-level conductive pattern and a low-level conductive pattern in the low-level recess. 1. A method for preparing a semiconductor device structure , comprising:forming a hard mask material over a substrate;etching the hardmask material to form hard mask pillars;forming spacers over sidewall surfaces of the hard mask pillars;etching the hard mask pillars and the target material by using the spacers as a mask to integrally forming a plurality of target structures, a high-level recesses in one of the plurality of target structures and a low-level recess between two target structures; andintegrally forming a high-level conductive pattern in the high-level conductive pattern and a low-level conductive pattern in the low-level recess.2. The method of claim 1 , wherein at least one of the target structure comprises a first portion claim 1 , a second portion claim 1 , and a third portion connected to the first portion and the second portion claim 1 , and the method further comprises: forming a tall air gap between the low-level conductive pattern and the second portion claim 1 , and a short air gap between the high-level conductive pattern and the second portion.3. The method of claim 2 , wherein the tall air gap and the short air gap have spacer profiles in a cross-sectional view.4. The method of claim 2 , further comprising: forming a first ...

DEEP TRENCH PROTECTION

A semiconductor device includes: at least one conductive feature disposed on a substrate; at least one dielectric layer overlying the substrate, a trench structure extending through the at least one dielectric layer; and a protection layer overlaying the trench structure. 1. A method , comprising:forming a first dielectric layer overlaying a substrate;forming a second dielectric layer overlaying the first dielectric layer;forming a deep trench structure extending through the first dielectric layer and the second dielectric layer;depositing a protection layer over the deep trench structure along an interface between the first dielectric layer and the second dielectric layer wherein the protection layer comprises titanium nitride (TiN); andcutting through the protection layer and the substrate.2. The method of claim 1 , further comprising forming the deep trench structure via dry etching.3. The method of claim 2 , further comprising performing wet etching over the protection layer.4. The method of claim 1 , further comprising removing a photoresist deposited in the deep trench structure.5. The method of claim 1 , further comprising removing the protection layer from a bottom of the deep trench structure.6. A method claim 1 , comprising:forming at least one conductive in a substrate;forming at least one dielectric layer over the substrate;forming a trench extending through the at least one dielectric layer and into the substrate, wherein the trench includes a trench structure sidewall extending through the at least one dielectric layer and into the substrate;forming a protection layer over the entirety of the trench structure sidewall, wherein the protection layer comprises titanium nitride (TiN); andforming a singulation sidewall that cuts through the protection layer and the substrate.7. The method of claim 6 , wherein the protection layer comprises a thickness of about 100 Å to about 1000 Å.8. The method of claim 6 , wherein the protection layer extends along and ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device manufacturing method includes: providing a semiconductor substrate, wherein the semiconductor substrate includes an array region and a peripheral region; word line structures and shallow trench isolation structures are formed in the array region, grooves are formed over word line structures, and a shallow trench isolation structure is formed in the peripheral region; depositing at least two insulating layers on a surface of the semiconductor substrate, each of the insulating layer has a different etch rate under a same etching condition; and removing part of the insulating layers located on surfaces of the array region and the peripheral region in sequence, wherein a lower insulating layer in the adjacent insulating layers is an etch stop layer of an upper insulating layer, and keeping all the insulating layers in the grooves located over the word line structures. 1. A method for manufacturing a semiconductor device , comprising:providing a semiconductor substrate, wherein the semiconductor substrate comprises an array region and a peripheral region, word line structures and shallow trench isolation structures are formed in the array region, grooves are formed over word line structures, and a shallow trench isolation structure is formed in the peripheral region;depositing at least two insulating layers on a surface of the semiconductor substrate, and each of the insulating layer has a different etch rate under a same etching condition;removing part of the insulating layers located on surfaces of the array region and the peripheral region in sequence, wherein a lower insulating layer in the adjacent insulating layers is an etch stop layer of the upper insulating layer, and preserving all the insulating layers in the grooves located over the word line structures.2. The method for manufacturing a semiconductor device of claim 1 , wherein a patterned mask layer is formed over the semiconductor substrate claim 1 , the mask layer covers a surface of ...

DEEP TRENCH PROTECTION

A semiconductor device includes: at least one conductive feature disposed on a substrate; at least one dielectric layer overlying the substrate, a trench structure extending through the at least one dielectric layer; and a protection layer overlaying the trench structure. 1. A semiconductor device , comprising:at least one conductive feature disposed on a substrate;at least one dielectric layer overlying the substrate, a trench structure extending through the at least one dielectric layer; anda protection layer overlaying the trench structure.2. The semiconductor device of claim 1 , wherein the protection layer comprises a thickness of about 100 Å to about 1000 Å.3. The semiconductor device of claim 1 , wherein the protection layer comprises at least one of TiN claim 1 , SiC claim 1 , and SiN.4. The semiconductor device of claim 1 , wherein the protection layer extends along at least a sidewall of the trench structure.5. The semiconductor device of claim 1 , comprising a first dielectric layer and a second dielectric layer claim 1 , the protection layer overlying a transition between the first dielectric layer and the second dielectric layer.6. The semiconductor device of claim 1 , further comprising at least one of a source claim 1 , a drain claim 1 , and a gate electrode of a transistor.7. The semiconductor device of claim 1 , further comprising:a conductive structure embedded in the at least one dielectric layer, the conductive structure comprising at least one of a via and a conductive line.8. The semiconductor device of claim 1 , wherein the trench structure at least partially surrounds a first die.9. The semiconductor device of claim 8 , wherein the trench structure further at least partially surrounds a second die.10. The semiconductor device of claim 9 , wherein the trench structure separates a first dielectric layer on the first die from a second dielectric layer on the second die claim 9 , wherein the first dielectric layer and the second dielectric layer ...

INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING INTEGRATED CIRCUIT

An integrated circuit having a plurality of miniaturized transistors, wherein the plurality of transistors include: high concentration transistors which include channel regions having impurity concentrations of a first concentration; and low concentration transistors which include channel regions having impurity concentrations of a second concentration lower than the first concentration. 1. An integrated circuit comprising: high concentration transistors which include channel regions having impurity concentrations of a first concentration; and', 'low concentration transistors which include channel regions having impurity concentrations of a second concentration lower than the first concentration., 'a plurality of miniaturized transistors, the plurality of miniaturized transistors including2. The integrated circuit of claim 1 , wherein the low concentration transistors are used for transistors which are more likely to be affected by a 1/f noise of the integrated circuit claim 1 , among the plurality of transistors claim 1 , than the high concentration transistors.3. The integrated circuit of claim 1 , wherein a shallow trench isolation (STI) structure is used in the plurality of transistors.4. The integrated circuit of further comprising: an operational amplifier claim 1 ,wherein the operational amplifier includes a differential pair, andwherein transistors constituting the differential pair are the low concentration transistors among the plurality of transistors.5. The integrated circuit of claim 4 , wherein the operational amplifier includes a current mirror circuit claim 4 , andwherein transistors constituting the current mirror circuit are the low concentration transistors among the plurality of transistors.6. The integrated circuit of claim 5 , wherein the low concentration transistors constituting the current mirror circuit are enhancement type MOSFETs.7. The integrated circuit of claim 4 , wherein the operational amplifier includes a last stage claim 4 , ...

INTEGRATED SINGLE DIFFUSION BREAK

A methodology for forming a fin field effect transistor (FinFET) includes the co-integration of various isolation structures, including gate cut and shallow diffusion break isolation structures that are formed with common masking and etching steps. Following an additional patterning step to provide segmentation for source/drain conductive contacts, a single deposition step is used to form an isolation dielectric layer within each of gate cut openings, shallow diffusion break openings and cavities over shallow trench isolation between device active areas. 1. A semiconductor device comprising:a plurality of semiconductor fins disposed over a semiconductor substrate, the semiconductor fins each having a source/drain region and a channel region adjacent to the source/drain region;a shallow trench isolation layer disposed over a top surface of the semiconductor substrate and peripheral to lower portions of the fins;a gate stack disposed over the channel regions, wherein the gate stack comprises a gate dielectric layer, a work function metal layer overlying the gate dielectric layer, and a conductive fill layer overlying the work function metal layer;a gate cap disposed over the gate stack; andan isolation dielectric layer extending through the gate stack, wherein the isolation dielectric layer is disposed directly over sidewalls of the conductive fill layer.2. The semiconductor device of claim 1 , wherein the isolation dielectric layer is in direct contact with a portion of the work function metal layer.3. The semiconductor device of claim 1 , wherein a top surface of at least one of the fins is disposed below a top surface of the shallow trench isolation layer and the isolation dielectric is disposed over the top surface of the at least one of the fins.4. The semiconductor device of claim 1 , wherein a top surface of at least one of the fins is disposed below a top surface of the shallow trench isolation layer and the isolation dielectric is spaced away from the top ...

FORMING CONDUCTIVE PLUGS FOR MEMORY DEVICE

Apparatuses and methods with conductive plugs for a memory device are described. An example method includes: forming a plurality of shallow trench isolations elongating from a first surface of a semiconductor substrate toward a second surface of the semiconductor substrate; thinning the semiconductor substrate until first surfaces of the plurality of shallow trench isolations are exposed; forming a plurality of via holes, each via hole of the plurality of via holes through a corresponding one of the plurality of shallow trench isolations; and filling the plurality of via holes with a conductive material to form a plurality of conductive plugs. 1. An apparatus comprising:a substrate including a first region and a second region;a conductive plug disposed through the second region; anda plurality of trenches in the first region, wherein the conductive plug is separated from adjacent ones of the plurality of trenches by a first width, andwherein each of the plurality of trenches is separated from adjacent others of the plurality of trenches by a second width which is smaller than the first width.2. The apparatus of claim 1 , wherein the second region has an area greater than an area of the first region.3. The apparatus of claim 2 , wherein the area of the second region is at least ten times larger than the area of the first region.4. The apparatus of claim 1 , wherein a distance from an outer surface of the conductive plug to an edge of the second region is in a range from about 0.5 um to about 1.5 um.5. The apparatus of claim 1 , wherein the first region and the second region are included in a peripheral region of a memory claim 1 , and wherein the peripheral region is adjacent to at least one memory region including at least one memory cell.6. The apparatus of claim 1 , wherein the adjacent ones of the plurality of trenches to the conductive plug are a first depth claim 1 , and wherein the adjacent others of the plurality of trenches are a second depth different from ...

Isolation scheme for bipolar transistors in bicmos technology

Device structures and design structures for a bipolar junction transistor. The device structure includes a collector region in a substrate, a plurality of isolation structures extending into the substrate and comprised of an electrical insulator, and an isolation region in the substrate. The isolation structures have a length and are arranged with a pitch transverse to the length such that each adjacent pair of the isolation structures is separated by a respective section of the substrate. The isolation region is laterally separated from at least one of the isolation structures by a first portion of the collector region. The isolation region laterally separates a second portion of the collector region from the first portion of the collector region. The device structure further includes an intrinsic base on the second portion of the collector region and an emitter on the intrinsic base. The emitter has a length transversely oriented relative to the length of the isolation structures.

GAPFILL OF VARIABLE ASPECT RATIO FEATURES WITH A COMPOSITE PEALD AND PECVD METHOD

Provided herein are methods and apparatus for filling one or more gaps on a semiconductor substrate. The disclosed embodiments are especially useful for forming seam-free, void-free fill in both narrow and wide features. The methods may be performed without any intervening etching operations to achieve a single step deposition. In various implementations, a first operation is performed using a novel PEALD fill mechanism to fill narrow gaps and line wide gaps. A second operation may be performed using PECVD methods to continue filling the wide gaps. 120.-. (canceled)21. A method of filling a gap on a semiconductor substrate with a dielectric material , comprising:depositing a first silicon-containing film in the gap through a plasma enhanced atomic layer deposition (PEALD) surface reaction using an aminosilane and a co-reactant; anddepositing additional silicon-containing film on the first silicon-containing film through a plasma enhanced chemical vapor deposition (PECVD) gas-phase reaction.22. The method of claim 21 , wherein depositing the first silicon-containing film comprises:(a) introducing a first reactant into a reaction chamber having the substrate therein, and allowing the first reactant to adsorb onto a surface of the substrate, wherein the first reactant is the aminosilane;(b) introducing a second reactant in vapor phase into the reaction chamber; and(c) exposing the substrate surface to plasma to drive a surface reaction between the first and second reactants on the substrate surface to form the first silicon-containing film, wherein the first silicon-containing film lines the gap.23. The method of claim 22 , wherein depositing additional silicon-containing film comprises:(d) introducing at least a third reactant in vapor phase into the reaction chamber; and(e) generating a plasma from at least the third reactant to drive a gas phase reaction, wherein the gas phase reaction produces the additional silicon-containing film.24. The method of claim 23 , ...

METHOD FOR PREPARING SEMICONDUCTOR MEMORY DEVICE WITH AIR GAPS BETWEEN CONDUCTIVE FEATURES

The present disclosure provides a method for preparing a semiconductor memory device with air gaps between conductive features. The method includes forming an isolation layer defining a first active region in a substrate; forming a first doped region in the first active region; forming a first word line buried in a first trench adjacent to the first doped region; and forming a high-level bit line contact positioned on the first doped region; forming a first air gap surrounding the high-level bit line contact. The forming of the first word line comprises: forming a lower electrode structure and an upper electrode structure on the lower electrode structure. The forming of the upper electrode structure comprises: forming a source layer substantially covering a sidewall of the first trench; forming a conductive layer on the source layer; and forming a work-function adjustment layer disposed between the source layer and the conductive layer. 1. A method for preparing a semiconductor memory device , comprising:forming an isolation layer defining a first active region in a substrate;forming a first doped region in the first active region;forming a first word line buried in a first trench adjacent to the first doped region;forming a high-level bit line contact positioned on the first doped region;forming a first air gap surrounding the high-level bit line contact;wherein the forming of the first word line comprises: forming a lower electrode structure and an upper electrode structure on the lower electrode structure;wherein the forming of the upper electrode structure comprises: forming a source layer substantially covering a sidewall of the first trench; forming a conductive layer on the source layer; and forming a work-function adjustment layer disposed between the source layer and the conductive layer.2. The method for preparing a semiconductor memory device of claim 1 , further comprising:forming a second doped region in a second active region of the substrate, the ...

Source/drain structure for semiconductor devices

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, an insulating stack formed over the substrate, a vertical structure formed through the insulating stack, a source/drain region formed over the vertical structure, and an isolation structure formed adjacent to the source/drain region and protruding the insulating stack. The source/drain region can include a first side surface and a second side surface. A lateral separation between the first side surface and the vertical structure can be greater than an other lateral separation between the second side surface and the vertical structure.

TECHNIQUE FOR DEFINING ACTIVE REGIONS OF SEMICONDUCTOR DEVICES WITH REDUCED LITHOGRAPHY EFFORT

In semiconductor devices requiring the formation of fully depleted SOI transistor elements in combination with non-FET elements, such as substrate diodes and the like, the patterning of the active regions may be accomplished on the basis of deep isolation trenches, which may be formed first on the basis of immersion-based lithography, followed by formation of shallow isolation trenches also formed on the basis of immersion lithography. Thereafter, respective openings connecting to the substrate materials may be formed, possibly in combination with isolation trenches of reduced depth compared to the deep isolation trenches, on the basis of non-immersion lithography techniques. In this manner, device scaling for semiconductor devices requiring critical dimensions of 26 nm and less in a planar transistor architecture may be accomplished. 1. A method , comprising:forming a first type of isolation trench so as to delineate active regions for transistor elements in a semiconductor layer along a first lateral direction, said first type of isolation trench extending through said semiconductor layer, a buried insulating layer and into a substrate material;after forming said first type of isolation trench, forming a second type of isolation trench so as to delineate said active regions along a second lateral direction that differs from said first lateral direction, said second type of isolation trench extending to said buried insulating layer; andafter forming said second type of isolation trench, forming an opening so as to expose a portion of said substrate material at a position that is laterally offset from said active region delineated by said first and second types of isolation trench.2. The method of claim 1 , wherein forming an opening so as to expose a portion of said substrate material comprises forming said opening so as to provide an exposed surface of said substrate material for further processing.3. The method of claim 1 , wherein forming an opening so as to ...

Semiconductor structure having a bump and a width of the bump larger than a width of fin shaped structures, and manufacturing method thereof

A semiconductor structure includes a substrate, a plurality of fin shaped structures, a trench, and a first bump. The substrate has a base, and the fin shaped structures protrude from the base. The trench is recessed from the base of the substrate. The first bump is disposed within the trench and protrudes from a bottom surface of the trench. A width of the first bump is larger than a width of each of the fin shaped structures.

LINEARITY AND LATERAL ISOLATION IN A BiCMOS PROCESS THROUGH COUNTER-DOPING OF EPITAXIAL SILICON REGION

Methods for providing improved isolation structures in a SiGe BiCMOS process are provided. In one method, an n-type epitaxial layer is grown over a p-type high-resistivity substrate. A mask covers a first region, and exposes a second region, of the epitaxial layer. A p-type impurity is implanted through the mask, counter-doping the second region to become slightly p-type. Shallow trench isolation (STI) and optional deep trench isolation (DTI) regions are formed through the counter-doped second region, thereby providing an isolation structure. The first region of the epitaxial layer forms a collector region of a heterojunction bipolar transistor. In another method, shallow trenches are etched partially into the epitaxial layer through a mask. A p-type impurity is implanted through the mask, thereby counter-doping thin exposed regions of the epitaxial layer to become slightly p-type. The shallow trenches are filled with dielectric material and a CMP process is performed to form shallow trench isolation regions.

SEMICONDUCTOR STRUCTURE

Semiconductor structures are provided. An exemplary semiconductor structure includes a semiconductor substrate having a first region and a second region and a plurality of first fins on the semiconductor substrate in the first region and a plurality of second fins on the semiconductor substrate in the second region. A first oxide layer is on side surfaces of the plurality of first fins; and a second oxide layer is on side surfaces of the second fins. A corner between a top surface and a side surface of each first fin is a first rounded corner. A corner between a top surface and a side surface of each second fin is a second rounded corner. A radius of curvature of the first rounded corner is different from a radius of curvature of the second corner. 1. A semiconductor structure , comprising:a semiconductor substrate having a first region and a second region and a plurality of first fins on the semiconductor substrate in the first region and a plurality of second fins on the semiconductor substrate in the second region,a first oxide layer on side surfaces of the plurality of first fins; and a corner between a top surface and a side surface of each first fin is a first rounded corner,', 'a corner between a top surface and a side surface of each second fin is a second rounded corner, and', 'a radius of curvature of the first rounded corner is different from a radius of curvature of the second corner., 'a second oxide layer on side surfaces of the second fins, wherein2. The semiconductor structure according to claim 1 , wherein:the first region is used to form memory devices; andthe second region is used to form peripheral devices.3. The semiconductor structure according to claim 1 , wherein:a width of the first fin is greater than a width of the second fin; andthe radius of curvature of the first corner is greater than the radius of curvature of the second corner.4. The semiconductor structure according to claim 1 , wherein:the width of the first fin is in a range of ...

Method for manufacturing semiconductor device

A method includes forming an implanted region in a substrate. The implanted region is adjacent to a top surface of the substrate. A clean treatment is performed on the top surface of the implanted region. The top surface of the implanted region is baked after the clean treatment. An epitaxial layer is formed on the top surface of the substrate. The epitaxial layer is patterned to form a fin.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first trench and a second trench in substrate on the memory region, wherein a width of the second trench is greater than a width of the first trench; forming a first liner, a second liner, and a third liner in the first trench and the second trench; performing a surface treatment process to lower stress of the third liner; and planarizing the third liner, the second liner, and the first liner to form a first isolation structure and a second isolation structure. 1. A method for fabricating semiconductor device , comprising:providing a substrate having a memory region and a periphery region;forming a first trench and a second trench in substrate on the memory region, wherein a width of the second trench is greater than a width of the first trench;forming a first liner, a second liner, and a third liner in the first trench and the second trench;performing a surface treatment process to lower stress of the third liner; andplanarizing the third liner, the second liner, and the first liner to form a first isolation structure and a second isolation structure.2. The method of claim 1 , further comprising:forming the first trench and the second trench on the memory region and a third trench in the substrate on the periphery region, wherein a width of the third trench is greater than a width of the second trench;forming the first liner, the second liner, and the third liner in the first trench, the second trench, and the third trench; andplanarizing the third liner, the second liner, and the first liner to form the first isolation structure, the second isolation structure, and a third isolation structure.3. The method of claim 2 , further comprising;forming a fourth liner on the third liner in the second trench and the third trench;forming a fifth liner on the fourth liner in the second trench and the third trench;forming a sixth ...

THREE-DIMENSIONAL MEMORY DEVICES HAVING ISOLATION STRUCTURE FOR SOURCE SELECT GATE LINE AND METHODS FOR FORMING THE SAME

Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate, a plurality of channel structures each extending vertically through the memory stack, an isolation structure, and an alignment mark. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. An outmost one of the conductive layers toward the substrate is a source select gate line (SSG). The isolation structure extends vertically into the substrate and surrounds at least one of the channel structures in a plan view to separate the SSG and the at least one channel structure. The alignment mark extends vertically into the substrate and is coplanar with the isolation structure. 1. A three-dimensional (3D) memory device , comprising:a substrate;a memory stack on the substrate comprising a plurality of interleaved conductive layers and dielectric layers, an outermost one of the conductive layers toward the substrate being a source select gate line (SSG);a plurality of channel structures each extending vertically through the memory stack;an isolation structure extending vertically into the substrate and surrounding at least one of the channel structures in a plan view to separate the SSG and the at least one channel structure; andan alignment mark extending vertically into the substrate and coplanar with the isolation structure.2. The 3D memory device of claim 1 , wherein the plurality of channel structures are disposed in a core array region and an edge region in a plan view claim 1 , and the at least one channel structure is disposed in the edge region.3. The 3D memory device of claim 2 , wherein the memory stack comprises a staircase structure claim 2 , the edge region is laterally between the staircase structure and the core array region claim 2 , and the at least one channel structure is disposed in an outmost column adjacent to the staircase ...

METHOD OF FABRICATING A FINFET DEVICE

In an embodiment, a method for fabricating a FinFET device includes providing a semiconductor substrate, etching the semiconductor substrate to form dummy fins and active fins. The group of dummy fins is etched through a patterned mask layer. An isolation feature is formed on the semiconductor substrate after etching the first group of dummy fins. 1. A method for fabricating a fin field-effect transistor (FinFET) device , the method comprising:providing a semiconductor substrate;etching the semiconductor substrate to form a first fin structure and a second fins structure;masking the second fin structure;etching the first fin structure while masking the second fin structure, wherein the etching the first fin structure reduces a height of the first fin structure;after the etching, forming an insulating material over the semiconductor substrate in an area previously occupied by the first fin structure.2. The method of claim 1 , wherein the etching the first fin structure includes completely removing the first fin structure.3. The method of claim 1 , wherein the first fin structure has a first height above a surface of the semiconductor substrate before the etching the first fin structure and a second height above the surface of the semiconductor substrate after the etching the first fin structure claim 1 , wherein the first height is greater than the second height and the second height is greater than 0.4. The method of claim 1 , wherein the forming the insulating material includes depositing at least one of silicon oxide claim 1 , silicon nitride claim 1 , and silicon oxynitride.5. The method of claim 1 , further comprising:forming a source/drain structure over the second fin structure.6. The method of claim 5 , wherein the forming the source/drain structure is performed before the etching the first fin structure.7. The method of claim 1 , wherein the forming the insulating material includes depositing the insulating material directly on the first fin structure having ...

Mos transistors in parallel

An electronic chip is provided that includes a plurality of first transistors electrically coupled to one another in parallel. A plurality of first isolating trenches is included in the electronic chip, and the first transistors are separated from one another by the first isolating trenches. Each of the first isolation trenches has a depth and a maximum width, and the depth depends on, or is a function of, the maximum width.

Mos transistors in parallel

An electronic chip includes first transistors connected in parallel so that gates of the first transistors are interconnected, drain areas of the first transistors are interconnected, and source areas of the first transistors are interconnected. The first transistors are separated from one another by first isolating trenches. The chip also includes second transistors and second isolating trenches. The second transistors are separated from one another by the second isolating trenches. The first isolating trenches have a maximum width that is smaller than a maximum width of all the second isolating trenches.

Structure and Process of Integrated Circuit Having Latch-Up Suppression

The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side; a first fin active region extruded from the N-well of the semiconductor substrate; a second fin active region extruded from the P-well of the semiconductor substrate; a first isolation feature formed on the N-well and the P-well and laterally contacting the first and second fin active regions, the first isolation feature having a first width; and a second isolation feature inserted between the N-well and the P-well, the second isolation feature having a second width less than the first width.

Deep Trench Isolations and Methods of Forming the Same

A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.

Method of fabricating optoelectronic integrated circuit substrate

A method of fabricating an optoelectronic integrated circuit substrate includes defining a photonic device region on a first substrate, the photonic device region having a photonic device formed thereon, forming a trench in the photonic device region on a top surface of the first substrate, the trench having a first depth, filling the trench with a dielectric, bonding a second substrate on the first substrate to cover the trench, and thinning the second substrate to a first thickness.

SEMICONDUCTOR DEVICE INCLUDING TRENCH ISOLATION LAYER AND METHOD OF FORMING THE SAME

A semiconductor device includes a plurality of patterns defined between a plurality of trenches and disposed on a substrate. A leaning control layer is disposed on sidewalls and bottoms of the plurality of trenches. A gap-fill insulating layer is disposed on the leaning control layer. At least one of the plurality of trenches has a different depth from one of the plurality of trenches adjacent thereto. 1. A method of forming a semiconductor device , the method comprising:forming, on a substrate, a plurality of trenches defining a plurality of patterns, at least one of the plurality of trenches having a different depth from one of the plurality of trenches adjacent thereto;forming a leaning control layer on side walls and bottoms of the plurality of trenches; andforming a gap-fill insulating layer on the leaning control layer,{'claim-text': ['forming a preliminary liner on the side walls and the bottoms of the plurality of trenches, and', 'oxidizing the preliminary liner using an oxidation process.'], '#text': 'wherein the forming the leaning control layer comprises'}2. The method of claim 1 , wherein the preliminary liner comprises silicon claim 1 , silicon nitride claim 1 , silicon oxynitride claim 1 , or a combination thereof.3. The method of claim 1 , wherein the forming the gap-fill insulating layer comprises:supplying a precursor onto the substrate having the leaning control layer;supplying a first inert gas onto the substrate;supplying an oxidant onto the substrate;supplying a second inert gas onto the substrate;supplying a surface modifier onto the substrate; andsupplying a third inert gas onto the substrate.4. The method of claim 3 , wherein:the precursor comprises silicon (Si) as a central element thereof and comprises amides, alkoxides, halides, or a combination thereof; and{'sub': ['2', '2'], '#text': 'the surface modifier comprises argon (Ar) plasma, oxygen (O) plasma, nitrogen (N) plasma, helium (He) plasma, or a combination thereof.'}5. The method of ...

SILICON-ON-INSULATOR INTEGRATED CIRCUIT DEVICES WITH BODY CONTACT STRUCTURES AND METHODS FOR FABRICATING THE SAME

Silicon-on-insulator integrated circuits including body contact structures and methods for fabricating the same are disclosed. A method for fabricating a silicon-on-insulator integrated circuit includes filling a plurality of first and second shallow isolation trenches with an insulating material to form plurality of first and second shallow trench isolation (STI) structures, the plurality of second shallow isolation trenches having doped regions therebeneath, and forming a gate structure over the semiconductor layer that includes a first portion disposed over and parallel to at least two of the plurality of second STI structures and a second portion disposed in between the at least two of the plurality of second STI structures. The method further includes forming contact plugs to a body contact or gate region of the semiconductor layer. The body contact region includes a portion of the semiconductor layer between at least one of the plurality of first STI structures and at least one of the plurality of second STI structures. 1. A method for fabricating a silicon-on-insulator integrated circuit comprising:providing a silicon-on-insulator substrate that comprises a semiconductor layer disposed over an insulating layer, which in turn is disposed over a substrate;forming a plurality of first shallow isolation trenches completely through the semiconductor layer to expose a portion of the insulating layer therebelow;forming a plurality of second shallow isolation trenches only part-way, but not fully, through the semiconductor layer;subsequent to forming the plurality of second shallow isolation trenches, implanting conductivity-determining ions into the semiconductor layer beneath the plurality of second shallow isolation trenches;subsequent to implanting the conductivity-determining ions, filling the plurality of first and second shallow isolation trenches with an insulating material to form a plurality of first and second shallow trench isolation structures;forming a ...

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Provided is a semiconductor memory device including a substrate, a plurality of first isolation structures, and a plurality of second isolation structures. The substrate includes a periphery region and an array region. The first isolation structures are located in the substrate of the periphery region. The second isolation structures are located in the substrate of the array region. A material of the first isolation structures is different from a material of the second isolation structures. A width of each of the first isolation structures is greater than a width of each of the second isolation structures. 1. A semiconductor memory device , comprising:a substrate, comprising a periphery region and an array region;a plurality of first isolation structures, located over the substrate in the periphery region, wherein each of the first isolation structures comprises a lower structure and an upper structure located over the lower structure, a material of the lower structures comprises a flowable dielectric material, a material of the upper structures comprises a chemical vapor deposition (CVD) oxide, a highest top surface of each of the lower structures is lower than a highest top surface of the substrate, and a distance between the highest top surface of each of the lower structures and the highest top surface of the substrate is at least greater than 500 Å; anda plurality of second isolation structures, located over the substrate in the array region, wherein a width of each of the first isolation structures is greater than a width of each of the second isolation structures.2. The semiconductor memory device according to claim 1 , wherein the width of each of the first isolation structures ranges between 2 μm and 8 μm claim 1 , and the width of each of the second isolation structures ranges between 0.01 μm and 0.03 μm.3. The semiconductor memory device according to claim 1 , wherein an aspect ratio of each of the first isolation structures ranges between 0.04 and 2 ...

Integrated Circuit With a Fin and Gate Structure and Method Making the Same

The present disclosure provides a semiconductor structure. The semiconductor structure includes device fins formed on a substrate; fill fins formed on the substrate and disposed among the device fins; and gate stacks formed on the device fins and the fill fins. The fill fins include a first dielectric material layer and a second dielectric material layer deposited on the first dielectric material layer. The first and second dielectric material layers are different from each other in composition.

Bipolar junction transistor and method for fabricating the same

A method for fabricating bipolar junction transistor (BJT) includes the steps of: providing a substrate having an emitter region, a base region, and a collector region; performing a first implantation process to form a first well region in the base region; and performing a second implantation process to form a second well region in the emitter region. Preferably, the first well region and the second well region comprise different concentration.

Fin field effect transistor (finfet) device structure and method for forming the same

A FinFET device structure and method for forming the same are provided. The method includes forming a plurality of fin structures over a substrate, and the substrate includes a first region and a second region. The method includes forming a plurality of isolation structures surrounding the fin structures, and a top surface of each of the isolation structures is lower than a top surface of each of the fin structures, and the isolation structures include first isolation structures over the first region and second isolation structures over the second region. The method includes forming a mask layer on the first isolation structures to expose the second isolation structures and removing a portion of the second isolation structures, such that a top surface of each of the second isolation structures is lower than a top surface of each of the first isolation structures.

Semiconductor device having noise isolation between power regulator circuit and electrostatic discharge clamp circuit

A semiconductor device includes a P-type substrate, a first isolation region, a plurality of first N-well walls, and an electrostatic discharge (ESD) clamp circuit. The first isolation region is formed within the P-type substrate. The ESD clamp circuit is arranged to discharge ESD current upon detection of an ESD event, and includes a clamping component that is arranged to provide a discharge path for the ESD current. The clamping component is formed on a region wrapped in the first isolation layer and the first N-well walls.

SEMICONDUCTOR DEVICES AND FABRICATION METHODS THEREOF

A semiconductor device is provided. The semiconductor device includes a semiconductor substrate; and a body region and a drift region formed in the semiconductor substrate. The semiconductor device also includes a bulk region and a source region formed in the body region. Further, the semiconductor device includes a drain region and a first shallow trench isolation structure having a ladder-like bottom formed in the drift region. Further, the semiconductor device also includes a gate structure spanning over an edge of the body region and an edge of the drift region formed on the semiconductor substrate and covering a portion of the first shallow trench isolation structure. 1. A method for fabricating a semiconductor device , comprising:providing a semiconductor substrate;forming a plurality of trenches with different depths in the semiconductor substrate;forming a first oxide layer by oxidizing the semiconductor substrate between adjacent trenches;forming a first shallow trench isolation structure by filling the trenches with different depths with dielectric material;forming a body region and a drift region, wherein the first shallow trench isolation structure is in the drift region;forming a bulk region and a source region in the body region and a drain region in the drift region at one side of the first shallow trench isolation structure away from the body region; andforming a gate structure spanning over an edge of the body region and an edge of the drift region and covering a portion of the first shallow trench isolation structure on the semiconductor substrate.2. The method according claim 1 , wherein:the shallow trench isolation structure has a ladder-like bottom3. The method according claim 1 , wherein forming the plurality of trenches further includes:forming a mask layer having a plurality of openings with different widths on the semiconductor substrate; andetching the semiconductor substrate using the mask layer as an etching mask.4. The method according ...

Semiconductor Device and Method

A method for shallow trench isolation structures in a semiconductor device and a semiconductor device including the shallow trench isolation structures are disclosed. In an embodiment, the method may include forming a trench in a substrate; depositing a first dielectric liner in the trench; depositing a first shallow trench isolation (STI) material over the first dielectric liner, the first STI material being deposited as a conformal layer; etching the first STI material; depositing a second STI material over the first STI material, the second STI material being deposited as a flowable material; and planarizing the second STI material such that top surfaces of the second STI material are co-planar with top surfaces of the substrate. 1. A semiconductor device comprising:a fin extending from a semiconductor substrate;a first isolation region on a first side of the fin; and a first liner;', 'a first isolation material over the first liner; and', 'a second isolation material over the first isolation material, wherein a top surface of the first isolation material in the first isolation region is disposed at a different level from a top surface of the first isolation material in the second isolation region, and wherein a top surface of the second isolation material in the first isolation region is disposed at the same level as a top surface of the second isolation material in the second isolation region., 'a second isolation region on a second side of the fin opposite the first side, wherein the first isolation region and the second isolation region comprise25. The semiconductor device of claim 1 , wherein the top surface of the first isolation material in the first isolation region is disposed below the top surface of the second isolation material in the second isolation region by a distance of greater than nm.3. The semiconductor device of claim 1 , wherein the first isolation region has a first width claim 1 , wherein the second isolation region has a second width ...

METHOD TO IMPROVE CHANNEL HOLE UNIFORMITY OF A THREE-DIMENSIONAL MEMORY DEVICE

Methods and structures of a three-dimensional memory device are disclosed. In an example, a method for forming a three-dimensional memory device includes disposing a material layer over a substrate, forming a plurality of channel-forming holes and a plurality of sacrificial holes around the plurality of channel-forming holes in an array-forming region of the material layer, and forming a plurality of semiconductor channels based on the channel-forming holes and at least one gate line slit (GLS) based on at least one of the plurality of sacrificial holes. A location of the at least one GLS overlaps with the at least one of the plurality of sacrificial holes. 1. A method for forming a three-dimensional memory device , comprising:disposing a material layer over a substrate;forming a plurality of channel-forming holes and a plurality of sacrificial holes around the plurality of channel-forming holes in an array-forming region of the material layer; andforming a plurality of semiconductor channels based on the channel-forming holes and at least one gate line slit (GLS) based on at least one of the plurality of sacrificial holes, wherein a location of the at least one GLS overlaps with the at least one of the plurality of sacrificial holes.2. The method of claim 1 , wherein forming the plurality of channel-forming holes and the plurality of sacrificial holes comprises:forming a first patterned photoresist layer over the material layer, wherein the first patterned photoresist layer comprises a plurality of channel-forming openings and a plurality of sacrificial openings; andforming the plurality of channel-forming openings and the plurality of sacrificial openings through the material layer until the substrate is exposed.3. The method of claim 1 , further comprising locating the plurality of sacrificial holes adjacent to boundaries of the array-forming region.4. The method of claim 3 , further comprising forming the plurality of channel-forming holes and the plurality of ...

SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD FOR SAME

The present disclosure relates to the field of semiconductor technologies, and discloses semiconductor apparatus and manufacturing methods for the same. In some implementations, a method may include: providing a substrate structure which includes: a substrate, one or more fins located on the substrate and extending along a first direction, and an isolation region located around one of the fins, an upper surface of the isolation region being lower than an upper surface of the fin, the isolation region including a first isolation region and a second isolation region, where the first isolation region is located on a side surface of the fin that is in the first direction, and the second isolation region is located on a side surface of the fin that is in a second direction that is different from the first direction; forming, on the substrate structure, a sacrificial layer having an opening, the opening exposing an upper surface of the first isolation region and exposing a part, which is located above the first isolation region, of the side surfaces of the fin adjacent to the first isolation region; filling the opening with an insulating material to form a third isolation region on the first isolation region, an upper surface of the third isolation region being higher than the upper surface of the fin; and removing the sacrificial layer. 1. A manufacturing method for a semiconductor apparatus , comprising: a substrate,', 'a fin located on the substrate and extending along a first direction, and', 'an isolation region located around the fin, where an upper surface of the isolation region is lower than an upper surface of the fin, the isolation region comprising a first isolation region and a second isolation region, the first isolation region being located on a side surface of the fin that is in the first direction, and the second isolation region being located on a side surface of the fin that is in a second direction that is different from the first direction;, ' ...

SEMICONDUCTOR DEVICE, RELATED MANUFACTURING METHOD, AND RELATED ELECTRONIC DEVICE

A semiconductor device may include the following elements: a first doped portion; a second doped portion; an enclosing member, which encloses both the first doped portion and the second doped portion; a first barrier, which directly contacts the first doped portion; a second barrier, which directly contacts the second doped portion; a dielectric member, which is positioned between the first barrier and the second barrier and directly contacts each of the first barrier and the second barrier; a third barrier, which directly contacts the first doped portion; and a device component, wherein a portion of the device component is positioned between the dielectric member and the third barrier. 1. A method for manufacturing a semiconductor device , the method comprising:providing a first doped member;providing a first enclosing member that encloses the first doped member;partially removing each of the first enclosing member and the first doped member to form a first trench and a second trench in a second enclosing member and a second doped member, wherein the second enclosing member is a remaining portion of the first enclosing member, and wherein the second doped member is a remaining portion of the first doped member;providing a first barrier material member inside the first trench;providing a second barrier material member inside the second trench;partially removing the first barrier material member for forming a third trench;providing a dielectric member inside the third trench, wherein the dielectric member is positioned between a first barrier and a second barrier, wherein the first barrier and the second barrier are remaining portions of the first barrier material member; andproviding a portion of a device component between the dielectric member and at least a portion of the second barrier material member.2. The method of claim 1 , wherein the second doped member is partially removed for forming the third trench claim 1 , wherein the dielectric member is positioned ...

TRENCH ISOLATION STRUCTURES AND METHODS FOR FORMING THE SAME

A trench isolation structure is provided. The trench isolation structure includes a substrate. A polygonal trench is disposed in the substrate. An insulating material is disposed in the polygonal trench, and a polygon top-side contact structure is disposed in the polygonal trench and surrounded by the insulating material. The polygon top-side contact structure has the same shape as the polygonal trench from a top view. A method for forming the trench isolation structure is also provided. 1. A trench isolation structure , comprising: a first semiconductor layer;', 'an insulating layer disposed on the first semiconductor layer; and', 'a second semiconductor layer disposed on the insulating layer;, 'a substrate, wherein the substrate comprisesa polygonal trench disposed in the substrate;an insulating material disposed in the polygonal trench; anda polygon top-side contact structure disposed in the polygonal trench and surrounded by the insulating material, wherein the polygon top-side contact structure has the same shape as the polygonal trench from a top view, and the polygon top-side contact structure is electrically connected to the first semiconductor layer.2. (canceled)3. The trench isolation structure of claim 1 , wherein the polygonal trench penetrates the second semiconductor layer claim 1 , and the polygonal trench does not penetrate the first semiconductor layer and the insulating layer.4. The trench isolation structure of claim 1 , wherein a thickness of the second semiconductor layer is 3 times to 6 times the width of the polygonal trench.5. The trench isolation structure of claim 1 , wherein the polygon top-side contact structure penetrates the second semiconductor layer and the insulating layer and is in direct contact with a doped region of the first semiconductor layer.6. The trench isolation structure of claim 1 , further comprising:a shallow trench isolation structure disposed in the second semiconductor layer;a first dielectric layer disposed on the ...

Method for improving control gate uniformity during manufacture of processors with embedded flash memory

A method is provided for the manufacture of an integrated semiconductor device that includes an embedded flash memory array formed in a recessed region of a semiconductor substrate, the method includes, prior to formation of floating and control gate stacks of the memory array, depositing a protective layer over layers of gate material, and depositing a self-leveling sacrificial layer over the protective layer to produce a substantially planar upper surface. The sacrificial layer is then etched to a depth that removes the sacrificial layer and leaves a substantially planar face on the protective layer. A photo mask is then deposited on the protective layer and the gate stacks are etched from the layers of gate material.

Semiconductor device including insulating layers and method of manufacturing the same

A semiconductor device includes a trench defining an active region in a substrate, a first insulating layer on a bottom surface and side surfaces of the active region inside the trench, a shielding layer on a surface of the first insulating layer, the shielding layer including a plurality of spaced apart particles, a second insulating layer on the shielding layer and having first charge trapped therein, the plurality of spaced apart particles being configured to concentrate second charge having an opposite polarity to the charge trapped in the second insulating layer, and a gap-fill insulating layer on the second insulating layer in the trench.

Shallow Trench Isolation Structures in Semiconductor Device and Method for Manufacturing the Same

Shallow trench isolation structures in a semiconductor device and a method for manufacturing the same. The method includes steps hereinafter. A substrate is provided with a pad oxide layer and a first patterned photoresist layer thereon. A first trench is formed in the substrate corresponding to the first patterned photoresist layer. A first dielectric layer is deposited in the first trench and on the substrate. A second patterned photoresist layer is provided to form an opening in the first dielectric layer and a second trench in the substrate corresponding to the second patterned photoresist layer. A second dielectric layer is deposited to cover the first trench and the second trench in the substrate and the first dielectric layer on the substrate. The second dielectric layer is removed by chemical-mechanical polishing until the first dielectric layer is exposed. The first dielectric layer on the substrate is selectively removed.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure manufacturing method includes: providing a substrate and etching the substrate to form first trenches; filling each of the first trenches with an oxide layer having a top surface not lower than that of the substrate; etching regions, adjacent to side walls of the first trench, in the oxide layer downwards to form second trenches, wherein a depth of the second trench is less than a depth of the first trench and a width of the second trench is less than half of a width of the first trench; and forming supplementary layers in the second trenches. 1. A manufacturing method of a semiconductor structure , comprising:providing a substrate, and etching the substrate to form first trenches;filling each of the first trenches with an oxide layer having a top surface not lower than a top surface of the substrate;etching regions, adjacent to side walls of the first trench, in the oxide layer downwards to form second trenches, wherein a depth of the second trench is less than a depth of the first trench and a width of the second trench is less than half of a width of the first trench; andforming supplementary layers in the second trenches.2. The manufacturing method of claim 1 , wherein the depth of the first trench is 300-400 nm and the depth of the second trench is 150-200 nm.3. The manufacturing method of claim 1 , wherein the substrate comprises an array and a periphery.4. The manufacturing method of claim 3 , wherein the first trench is formed in the array claim 3 , the width of the first trench is 20-40 nm claim 3 , and the width of the second trench is 5-15 nm.5. The manufacturing method of claim 3 , wherein the first trench is formed in the periphery claim 3 , the width of the first trench is 70-110 nm claim 3 , and the width of the second trench is 30-50 nm.6. The manufacturing method of claim 1 , further comprising: forming a protective layer on the substrate before the first trenches are formed by etching; andetching the protective layer and ...

Gate Electrodes with Notches and Methods for Forming the Same

A device includes a semiconductor substrate, a gate dielectric over the semiconductor substrate, and a gate electrode over the gate dielectric. The gate electrode has a first portion having a first thickness, and a second portion having a second thickness smaller than the first thickness. The device further includes a source/drain region on a side of the gate electrode with the source/drain region extending into the semiconductor substrate, and a device isolation region. The device isolation region has a part having a sidewall contacting a second sidewall of the source/drain region to form an interface. The interface is overlapped by a joining line of the firs portion and the second portion of the gate electrode. 1. A device comprising:a semiconductor substrate;a gate dielectric over the semiconductor substrate;a gate electrode over the gate dielectric, wherein the gate electrode comprises a first portion having a first thickness, and a second portion having a second thickness smaller than the first thickness;a first source/drain region on a side of the gate electrode, wherein the first source/drain region extends into the semiconductor substrate; anda device isolation region comprising a first part, wherein the first part has a first sidewall contacting a second sidewall of the first source/drain region to form an interface, wherein the interface is overlapped by a joining line of the firs portion and the second portion of the gate electrode.2. The device of claim 1 , wherein an entire second portion of the gate electrode overlaps the device isolation region.3. The device of claim 1 , wherein the second thickness is in a range between about 20 percent and about 80 percent of the first thickness.4. The device of further comprising a well region directly underlying the gate dielectric and the first source/drain region claim 1 , wherein the well region and the device isolation region are of a same conductivity type.5. The device of claim 4 , wherein at least a portion ...

Dishing prevention dummy structures for semiconductor devices

In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.

Apparatus with overlapping deep trench and shallow trench and method of fabricating the same with low defect density

An integrated circuit includes a semiconductor substrate that has a top surface. A trench is formed within the substrate, and a conductive filler structure fills the trench. An insulator is located between the semiconductor substrate and the conductive filler. The insulator has a top portion with a top surface at the top surface of the substrate, The insulator further has a bottom portion that forms a corner with the top portion and extends from the corner to a bottom of the trench.

Self-aligned gate endcap (sage) architectures without fin end gap

Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.

Solid-state imaging device, electronic apparatus, and manufacturing method

The present disclosure relates to a solid-state imaging device, an electronic apparatus, and a manufacturing method that are designed to further increase conversion efficiency. A solid-state imaging device includes a pixel in which element separation is realized by a first trench element separation region having a trench structure in a region between an FD unit and an amplifying transistor among element separation elements separating the elements constituting the pixel from one another, and a second trench element separation region having a trench structure in a region other than the region between the FD unit and the amplifying transistor among the element separation regions separating the elements constituting the pixel from one another, and the first trench element separation region is deeper than the second trench element separation region. The present technology can be applied to CMOS image sensors, for example.