Настройки

Укажите год
-

Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

Подробнее
-

Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

Подробнее

Форма поиска

Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
Ведите корректный номера.
Ведите корректный номера.
Ведите корректный номера.
Ведите корректный номера.
Укажите год
Укажите год
Применить Всего найдено 12998. Отображено 100.
19-01-2012 дата публикации

interconnection structure for n/p metal gates

Номер: US20120012937A1
Автор: Han-Guan Chew, Harry-Hak-Lay Chuang, Lee-Wee Teo, Ming Zhu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The disclosure relates to integrated circuit fabrication, and more particularly to an interconnection structure for N/P metal gates. An exemplary structure for an interconnection structure comprises a first gate electrode having a first portion of a first work-function metal layer under a first portion of a signal metal layer; and a second gate electrode having a second portion of the first work-function metal layer interposed between a second work-function metal layer and a second portion of the signal metal layer, wherein the second portion of the signal metal layer is over the second portion of the first work-function metal layer, wherein the second portion of the signal metal layer and the first portion of the signal metal layer are continuous, and wherein a maximum thickness of the second portion of the signal metal layer is less than a maximum thickness of the first portion of the signal metal layer.

Подробнее
Номер записи: 1
09-02-2012 дата публикации

Metal semiconductor alloy structure for low contact resistance

Номер: US20120032275A1
Автор: Balasubramanian S. Haran, Sivananda K. Kanakasabapathy
Принадлежит: International Business Machines Corp

Contact via holes are etched in a dielectric material layer overlying a semiconductor layer to expose the topmost surface of the semiconductor layer. The contact via holes are extended into the semiconductor material layer by continuing to etch the semiconductor layer so that a trench having semiconductor sidewalls is formed in the semiconductor material layer. A metal layer is deposited over the dielectric material layer and the sidewalls and bottom surface of the trench. Upon an anneal at an elevated temperature, a metal semiconductor alloy region is formed, which includes a top metal semiconductor alloy portion that includes a cavity therein and a bottom metal semiconductor alloy portion that underlies the cavity and including a horizontal portion. A metal contact via is formed within the cavity so that the top metal semiconductor alloy portion laterally surrounds a bottom portion of a bottom portion of the metal contact via.

Подробнее
Номер записи: 2
09-02-2012 дата публикации

N-well/p-well strap structures

Номер: US20120032276A1
Автор: Andy Lee, Bradley Jensen, Dustin Do, Giles V. Powell, Swee Aun Lau, Thomas H. White, Wuu-Cherng Lin
Принадлежит: Altera Corp

Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.

Подробнее
Номер записи: 3
03-05-2012 дата публикации

Method for forming a semiconductor device with stressed trench isolation

Номер: US20120108032A1
Автор: Haizhou Yin, Huilong Zhu, Zhijiong Luo
Принадлежит: Institute of Microelectronics of CAS

A method for forming a semiconductor device with stressed trench isolation is provided, comprising: providing a silicon substrate (S 11 ); forming at least two first trenches in parallel on the silicon substrate and forming a first dielectric layer which is under tensile stress in the first trenches (S 12 ); forming at least two second trenches, which have an extension direction perpendicular to that of the first trenches, in parallel on the silicon substrate, and forming a second dielectric layer in the second trenches (S 13 ); and after forming the first trenches, forming a gate stack on a part of the silicon substrate between two adjacent first trenches, wherein the channel length direction under the gate stack is parallel to the extension direction of the first trenches (S 14 ). The present invention supply tensile stress in the channel width direction of a MOS transistor, so as to improve performance of PMOS and/or NMOS transistors.

Подробнее
Номер записи: 4
17-05-2012 дата публикации

Metal gate transistor, integrated circuits, systems, and fabrication methods thereof

Номер: US20120119306A1
Автор: Alex Kalnitsky, Chia-Yi Su, Chien-Chih Ho, Chih-Ping Chao, Chun-Hung Chen, Harry-Hak-Lay Chuang, Hua-Chou Tseng, Jye-Yen Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method of forming an integrated circuit structure includes providing a gate strip in an inter-layer dielectric (ILD) layer. The gate strip comprises a metal gate electrode over a high-k gate dielectric. An electrical transmission structure is formed over the gate strip and a conductive strip is formed over the electrical transmission structure. The conductive strip has a width greater than a width of the gate strip. A contact plug is formed above the conductive strip and surrounded by an additional ILD layer.

Подробнее
Номер записи: 5
31-05-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120135574A1
Автор: Naoyoshi Tamura
Принадлежит: Fujitsu Semiconductor Ltd

Aimed at providing a highly reliable semiconductor device appropriately increased in stress at the channel region so as to improve carrier injection rate, thereby dramatically improved in transistor characteristics, and made adaptable also to recent narrower channel width, and a method of manufacturing the same, and a method of manufacturing the same, a first sidewall composed of a stress film having expandability is formed on the side faces of a gate electrode, a second sidewall composed of a film having smaller stress is formed on the first sidewall, and a semiconductor, which is a SiC layer for example, is formed as being positioned apart from the first sidewall while placing the second sidewall in between.

Подробнее
Номер записи: 6
14-06-2012 дата публикации

Semiconductor device

Номер: US20120146176A1
Автор: Fumio Sasaki, Ryoichi Ohara, Yoshitomo Sagae
Принадлежит: Toshiba Corp

A semiconductor device receiving as input a radio frequency signal having a frequency of 500 MHz or more and a power of 20 dBm or more is provided. The semiconductor device includes: a silicon substrate; a silicon oxide film formed on the silicon substrate; a radio frequency interconnect provided on the silicon oxide film and passing the radio frequency signal; a fixed potential interconnect provided on the silicon oxide film and placed at a fixed potential; and an acceptor-doped layer. The acceptor-doped layer is formed in a region of the silicon substrate. The region is in contact with the silicon oxide film. The acceptor-doped layer is doped with acceptors.

Подробнее
Номер записи: 7
19-07-2012 дата публикации

Fabrication of Semiconductor Architecture Having Field-effect Transistors Especially Suitable for Analog Applications

Номер: US20120181626A1
Автор: Constantin Bulucea
Принадлежит: National Semiconductor Corp

An insulated-gate field-effect transistor ( 220 U) is provided with an empty-well region for achieving high performance. The concentration of the body dopant reaches a maximum at a subsurface location no more than 10 times deeper below the upper semiconductor surface than the depth of one of a pair of source/drain zones ( 262 and 264 ), decreases by at least a factor of 10 in moving from the subsurface location along a selected vertical line ( 136 U) through that source/drain zone to the upper semiconductor surface, and has a logarithm that decreases substantially monotonically and substantially inflectionlessly in moving from the subsurface location along the vertical line to that source/drain zone. Each source/drain zone has a main portion ( 262 M or 264 M) and a more lightly doped lateral extension ( 262 E or 264 E). Alternatively or additionally, a more heavily doped pocket portion ( 280 ) of the body material extends along one of the source/drain zones.

Подробнее
Номер записи: 8
02-08-2012 дата публикации

Semiconductor device and method for manufacturing same

Номер: US20120196411A1
Автор: Ryuta Tsuchiya, Shinichiro Kimura
Принадлежит: Renesas Electronics Corp

A device and a method for manufacturing the same in which with device includes a single crystal semiconductor substrate and an SOI substrate separated from the single crystal semiconductor substrate by a thin buried insulating film and having a thin single crystal semiconductor thin film (SOI layer) in which well diffusion layer regions, drain regions, gate insulating films, and gate electrodes of the SOI-type MISFET and the bulk-type MISFET are formed in the same steps. The bulk-type MISFET and the SOI-type MISFET are formed on the same substrate, so that board area is reduced and a simple process can be realized by making manufacturing steps of the SOI-type MISFET and the bulk-type MISFET common.

Подробнее
Номер записи: 9
16-08-2012 дата публикации

Integrated circuit system with through silicon via and method of manufacture thereof

Номер: US20120205806A1
Автор: Chung Meng Lek, Denise Tan, Jeffrey C. Lam, Liang-Choo Hsia, Pradeep Ramachandramurthy Yelehanka, Thomas Thiam
Принадлежит: GLOBALFOUNDRIES SINGAPORE PTE LTD

A method of manufacture of an integrated circuit system includes: providing a substrate including an active device; forming a through-silicon-via into the substrate; forming an insulation layer over the through-silicon-via to protect the through-silicon-via; forming a contact to the active device after forming the insulation layer; and removing the insulation layer.

Подробнее
Номер записи: 10
27-09-2012 дата публикации

Field effect transistor

Номер: US20120241722A1
Автор: Keiji Ikeda, Toshifumi Irisawa, Toshinori Numata, Tsutomu Tezuka
Принадлежит: Individual

A field effect transistor according to an embodiment includes: a semiconductor layer; a source region and a drain region formed at a distance from each other in the semiconductor layer; a gate insulating film formed on a portion of the semiconductor layer, the portion being located between the source region and the drain region; a gate electrode formed on the gate insulating film; and a gate sidewall formed on at least one of side faces of the gate electrode, the side faces being located on a side of the source region and on a side of the drain region, the gate sidewall being made of a high dielectric material. The source region and the drain region are separately-placed from the corresponding side faces of the gate electrode.

Подробнее
Номер записи: 11
27-09-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120241869A1
Автор: Akihiro Usujima, Shigeo Satoh
Принадлежит: Fujitsu Semiconductor Ltd

A method of manufacturing a semiconductor device includes forming a first and a second isolation insulating film to define a first, a second, a third and a fourth region, forming a first insulating film, implanting a first impurity of a first conductivity type through the first insulating film into the first, the second and the fourth region at a first depth, forming a second insulating film thinner than the first insulating film, implanting a second impurity of a second conductivity type through the second insulating film into the third region at a second depth in the semiconductor substrate, implanting a third impurity of the second conductivity type into the third region at a third depth shallower than the second depth, forming a first transistor of the first conductivity type in the third region, and forming a second transistor of the second conductivity type in the fourth region.

Подробнее
Номер записи: 12
04-10-2012 дата публикации

Semiconductor device

Номер: US20120248543A1
Автор: Takafumi Kuramoto, Yasutaka Nakashiba
Принадлежит: Renesas Electronics Corp

A distance “a” from a first gate electrode of a first transistor of a high-frequency circuit to a first contact is greater than a distance “b” from a second electrode of a second transistor of a digital circuit to a second contact. The first contact is connected to a drain or source of the first transistor, and the second contact is connected to a drain or source of the second transistor.

Подробнее
Номер записи: 13
11-10-2012 дата публикации

Semiconductor device and fabrication method

Номер: US20120256264A1
Автор: Masaki HANEDA, Masanori Terahara, Takayuki Aoyama, Yuka Kase
Принадлежит: Fujitsu Semiconductor Ltd

A semiconductor device includes a semiconductor substrate including a well having a first conductivity type defined by a device isolation region, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film and including a first side surface and a second side surface facing the first side surface, and a first side wall insulating film formed on the first side surface and a second side wall insulating film formed on the second side surface.

Подробнее
Номер записи: 14
18-10-2012 дата публикации

Semiconductor device and method for manufacturing the same

Номер: US20120261759A1
Автор: Haizhou Yin, Huilong Zhu, Qingqing Liang, Zhijiong Luo
Принадлежит: Institute of Microelectronics of CAS

A semiconductor device comprising: a semiconductor substrate; an STI embedded into the semiconductor substrate and having at least a semiconductor opening region; a channel region in the semiconductor opening region; a gate stack comprising a gate dielectric layer and a gate conductive layer and located above the channel region; and source/drain regions located on both sides of the channel region, and comprising first seed layers on opposite sides of the gate stack adjacent to the STI, wherein the upper surface of the STI is higher than or sufficiently closed to the upper surface of the gate dielectric layer. The semiconductor device and the method for manufacturing the same can enhance the stress of the channel region so as to improve device performance.

Подробнее
Номер записи: 15
08-11-2012 дата публикации

Cavity-free interface between extension regions and embedded silicon-carbon alloy source/drain regions

Номер: US20120280251A1
Автор: Abhishek Dube, Viorel Ontalus
Принадлежит: International Business Machines Corp

A gate stack is formed on a silicon substrate, and source/drain extension regions are formed around the gate stack. A dielectric spacer is formed around the gate stack. A pair of trenches is formed around the gate stack and the dielectric spacer by an etch so that sidewalls of the source/drain extension regions are exposed. Within each trench, an n-doped silicon liner is deposited on the sidewalls of the trenches by a first selective epitaxy process so that the interface between the dielectric spacer and the source/drain extension region is covered. Within each trench, an n-doped single crystalline silicon-carbon alloy is subsequently deposited to fill the trench by a second selective epitaxy process. A combination of an n-doped single crystalline silicon liner and an n-doped single crystalline silicon-carbon alloy functions as embedded source/drain regions of an n-type field effect transistor (NFET), which applies a tensile stress to the channel of the transistor.

Подробнее
Номер записи: 16
29-11-2012 дата публикации

Sram cell with different crystal orientation than associated logic

Номер: US20120302013A1
Автор: Theodore W. Houston
Принадлежит: Texas Instruments Inc

An integrated circuit containing logic transistors and an array of SRAM cells in which the logic transistors are formed in semiconductor material with one crystal orientation and the SRAM cells are formed in a second semiconductor layer with another crystal orientation. A process of forming an integrated circuit containing logic transistors and an array of SRAM cells in which the logic transistors are formed in a top semiconductor layer with one crystal orientation and the SRAM cells are formed in an epitaxial semiconductor layer with another crystal orientation. A process of forming an integrated circuit containing logic transistors and an array of SRAM cells in which the SRAM cells are formed in a top semiconductor layer with one crystal orientation and the logic transistors are formed in an epitaxial semiconductor layer with another crystal orientation.

Подробнее
Номер записи: 17
29-11-2012 дата публикации

Method of Protecting STI Structures From Erosion During Processing Operations

Номер: US20120302037A1
Автор: Hans-Juergen Thees, Joerg Radecker, Stephan Kronholz
Принадлежит: Globalfoundries Inc

Generally, the present disclosure is directed to a method of at least reducing unwanted erosion of isolation structures of a semiconductor device during fabrication. One illustrative method disclosed includes forming an isolation structure in a semiconducting substrate and forming a conductive protection ring above plurality isolation structure.

Подробнее
Номер записи: 18
06-12-2012 дата публикации

Well region formation method and semiconductor base

Номер: US20120305941A1
Автор: Haizhou Yin, Huilong Zhu, Zhijong Luo
Принадлежит: Institute of Microelectronics of CAS

A well region formation method and a semiconductor base in the field of semiconductor technology are provided. A method comprises: forming isolation regions in a semiconductor substrate to isolate active regions; selecting at least one of the active regions, and forming a first well region in the selected active region; forming a mask to cover the selected active region, and etching the rest of the active regions, so as to form grooves; and growing a semiconductor material by epitaxy to till the grooves. Another method comprises: forming isolation regions in a semiconductor substrate for isolating active regions; forming well regions in the active regions; etching the active regions to form grooves, such that the grooves have a depth less than or equal to a depth of the well regions; and growing a semiconductor material by epitaxy to till the grooves.

Подробнее
Номер записи: 19
24-01-2013 дата публикации

Metal gate structure of a cmos semiconductor device and method of forming the same

Номер: US20130020651A1
Автор: Bao-Ru Young, Harry Hak-Lay Chuang, Ming Zhu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate, an N-metal gate electrode, and a P-metal gate electrode. The substrate comprises an isolation region surrounding a P-active region and an N-active region. The N-metal gate electrode comprises a first metal composition over the N-active region. The P-metal gate electrode comprises a bulk portion over the P-active region and an endcap portion over the isolation region. The endcap portion comprises the first metal composition and the bulk portion comprises a second metal composition different from the first metal composition.

Подробнее
Номер записи: 20
24-01-2013 дата публикации

Integrated circuit having a stressor and method of forming the same

Номер: US20130020717A1
Автор: Chih-Hsun Lin, Chih-Kang Chao, Ling-Sung Wang, Mei-Hsuan LIN
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An embodiment of the disclosure includes a method of forming a semiconductor structure. A substrate has a region adjacent to a shallow trench isolation (STI) structure in the substrate. A patterned mask layer is formed over the substrate. The patterned mask layer covers the STI structure and a portion of the region, and leaves a remaining portion of the region exposed. A distance between an edge of the remaining portion and an edge of the STI structure is substantially longer than 1 nm. The remaining portion of the region is etched thereby forms a recess in the substrate. A stressor is epitaxially grown in the recess. A conductive plug contacting the stressor is formed.

Подробнее
Номер записи: 21
28-03-2013 дата публикации

Superior Integrity of High-K Metal Gate Stacks by Forming STI Regions After Gate Metals

Номер: US20130075820A1
Автор: Peter Baars, Thilo Scheiper
Принадлежит: Globalfoundries Inc

When forming sophisticated high-k metal gate electrode structures in an early manufacturing stage, superior process robustness, reduced yield loss and an enhanced degree of flexibility in designing the overall process flow may be accomplished by forming and patterning the sensitive gate materials prior to forming isolation regions.

Подробнее
Номер записи: 22
28-03-2013 дата публикации

Method for improving the electromigration resistance in the copper interconnection process

Номер: US20130078798A1
Автор: Lin Chen, Pengfei Wang, Qingqing Sun, Wei Zhang, Wen Yang
Принадлежит: FUDAN UNIVERSITY

The present invention belongs to the technical field of integrated semiconductor circuits, and relates to a method used in a process no greater than 32 nm to improve the electromigration resistance of Cu interconnects. Coating layers on Cu interconnects, such as CuSi 3 , CuGe, and CuSiN, can be prepared by autoregistration, and with the use of new impervious layer materials, the electromigration resistance of Cu interconnects can be largely improved and the high conductivity thereof can be kept, which provides an ideal solution for interconnection process for process nodes no greater than 32 nm.

Подробнее
Номер записи: 23
16-05-2013 дата публикации

Semiconductor process for removing oxide layer

Номер: US20130122684A1
Автор: Chin-Cheng Chien, Ted Ming-Lang Guo, Teng-Chun Hsuan
Принадлежит: United Microelectronics Corp

A semiconductor process for removing oxide layers comprises the steps of providing a substrate having an isolation structure and a pad oxide layer, performing a dry cleaning process and a wet cleaning process to remove said pad oxide layer, forming a sacrificial oxide layer on said substrate, and performing an ion implantation process to form doped well regions on both sides of the isolation structure.

Подробнее
Номер записи: 24
06-06-2013 дата публикации

Metal gate features of semiconductor die

Номер: US20130140641A1
Автор: Harry-Hak-Lay Chuang, Ming Zhu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A CMOS semiconductor die comprises a substrate; an insulation layer over a major surface of the substrate; a plurality of P-metal gate areas formed within the insulation layer collectively covering a first area of the major surface; a plurality of N-metal gate areas formed within the insulation layer collectively covering a second area of the major surface, wherein a first ratio of the first area to the second area is equal to or greater than 1; a plurality of dummy P-metal gate areas formed within the insulation layer collectively covering a third area of the major surface; and a plurality of dummy N-metal gate areas formed within the insulation layer collectively covering a fourth area of the major surface, wherein a second ratio of the third area to the fourth area is substantially equal to the first ratio.

Подробнее
Номер записи: 25
06-06-2013 дата публикации

Localized carrier lifetime reduction

Номер: US20130140667A1
Автор: Alex Kalnitsky, Chih-Wen Yao, Hsiao-Chin Tuan, Jun Cai, Ruey-Hsin Liu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor structure includes a substrate, a first power device and a second power device in the substrate, at least one isolation feature between the first and second power device, and a trapping feature adjoining the at least one isolation feature in the substrate.

Подробнее
Номер записи: 26
20-06-2013 дата публикации

Method for improved mobility using hybrid orientaion technology (HOT) in conjunction with

Номер: US20130157424A1
Автор: Owens Alexander H.
Принадлежит: TEXAS INSTRUMENTS INCORPORATED

A semiconductor apparatus includes a first substrate and a second substrate located over a first portion of the first substrate and separated from the first substrate by a buried layer. The semiconductor apparatus also includes an epitaxial layer located over a second portion of the first substrate and isolated from the second substrate. The semiconductor apparatus further includes a first transistor formed at least partially in the second substrate and a second transistor formed at least partially in or over the epitaxial layer. The second substrate and the epitaxial layer have bulk properties with different electron and hole mobilities. At least one of the transistors is configured to receive one or more signals of at least about 5V. The first substrate could have a first crystalline orientation, and the second substrate could have a second crystalline orientation. 1. A method comprising: a first substrate;', 'a second substrate located over a first portion of the first substrate and separated from the first substrate by a buried layer; and', 'an epitaxial layer located over a second portion of the first substrate and isolated from the second substrate, wherein the second substrate has a higher hole mobility than the epitaxial layer, wherein the epitaxial layer has a higher electron mobility than the second substrate, and wherein the hole and electron mobilities are bulk properties; and, 'obtaining a substrate structure comprising{'b': '5', 'forming first and second transistors, the first transistor formed at least partially in the second substrate, the second transistor formed at least partially in or over the epitaxial layer, at least one of the transistors configured to receive one or more signals of at least about V.'}2. The method of claim 1 , wherein obtaining the substrate structure comprises:removing a portion of second substrate material;forming a spacer on a side of the second substrate; andforming the epitaxial layer in an area where the second ...

Подробнее
Номер записи: 27
27-06-2013 дата публикации

High density butted junction cmos inverter, and making and layout of same

Номер: US20130164891A1
Автор: Andres Bryant, Jeffrey W. Sleight, Josephine B. Chang
Принадлежит: International Business Machines Corp

A method of manufacturing a butted junction CMOS inverter with asymmetric complementary FETS on an SOI substrate may include: forming a butted junction that physically contacts a first drain region of a first FET and a second drain region of a second complementary FET on the SOI substrate, where the butted junction is disposed medially to a first channel region of the first FET and a second channel region of the second complementary FET; implanting a first halo implant on only a source side of the first channel region, to form a first asymmetric FET; and forming a second halo implant on only a source side of the second channel region of the second complementary FET, to form a second asymmetric complementary FET.

Подробнее
Номер записи: 28
11-07-2013 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20130175611A1
Автор: Hidekazu Oda, Hirofumi Shinohara, Hiromasa YOSHIMORI, Toshiaki Iwamatsu
Принадлежит: Renesas Electronics Corp

An area in a top view of a region where a low-voltage field effect transistor is formed is reduced, and an area in a top view of a region where a high-voltage field effect transistor is formed is reduced. An active region where the low-voltage field effect transistors (first nMIS and first pMIS) are formed is constituted by a first convex portion of a semiconductor substrate that projects from a surface of an element isolation portion, and an active region where the high-voltage field effect transistors (second nMIS and second pMIS) are formed is constituted by a second convex portion of the semiconductor substrate that projects from the surface of the element isolation portion, and a trench portion formed in the semiconductor substrate.

Подробнее
Номер записи: 29
01-08-2013 дата публикации

Transistor with counter-electrode connection amalgamated with the source/drain contact

Номер: US20130193494A1
Автор: Maud Vinet, Qing Liu
Принадлежит: Commissariat a lEnergie Atomique et aux Energies Alternatives CEA, STMicroelectronics lnc USA

The field effect device includes an active area made from semi-conducting material and a gate electrode separated from the active area by a dielectric gate material. A counter-electrode is separated from the active area by a layer of electrically insulating material. Two source/drain contacts are arranged on the active area on each side of the gate electrode. One of the source/drain contacts is made from a single material, overspills from the active area and connects the active area with the counter-electrode. The counter-electrode contact is delineated by a closed peripheral insulating pattern.

Подробнее
Номер записи: 30
08-08-2013 дата публикации

Integrated Circuit with Gate Electrode Conductive Structures Having Offset Ends

Номер: US20130200436A1
Автор: Michael C. Smayling, Scott T. Becker
Принадлежит: Individual

A first linear-shaped conductive structure (LSCS) forms gate electrodes of a first p-transistor and a first n-transistor. A second LSCS forms a gate electrode of a second p-transistor. A third LSCS forms a gate electrode of a second n-transistor, and is separated from the second LSCS by a first end-to-end spacing (EES). A fourth LSCS forms a gate electrode of a third p-transistor. A fifth LSCS forms a gate electrode of a third n-transistor, and is separated from the fourth LSCS by a second EES. A sixth LSCS forms gate electrodes of a fourth p-transistor and a fourth n-transistor. An end of the second LSCS adjacent to the first EES is offset from an end of the fourth LSCS adjacent to the second EES, and/or an end of the third LSCS adjacent to the first EES is offset from an end of the fifth LSCS adjacent to the second EES.

Подробнее
Номер записи: 31
08-08-2013 дата публикации

Integrated Circuit with Offset Line End Spacings in Linear Gate Electrode Level

Номер: US20130200462A1
Автор: Michael C. Smayling, Scott T. Becker
Принадлежит: Individual

A first linear-shaped conductive structure (LSCS) forms gate electrodes of a first p-transistor and a first n-transistor. A second LSCS forms a gate electrode of a second p-transistor. A third LSCS forms a gate electrode of a second n-transistor, and is separated from the second LSCS by a first end-to-end spacing (EES). A fourth LSCS forms a gate electrode of a third p-transistor. A fifth LSCS forms a gate electrode of a third n-transistor, and is separated from the fourth LSCS by a second EES. A sixth LSCS forms gate electrodes of a fourth p-transistor and a fourth n-transistor. An end of the second LSCS adjacent to the first EES is offset from an end of the fourth LSCS adjacent to the second EES, and/or an end of the third LSCS adjacent to the first EES is offset from an end of the fifth LSCS adjacent to the second EES.

Подробнее
Номер записи: 32
08-08-2013 дата публикации

Methods for pfet fabrication using apm solutions

Номер: US20130203244A1
Автор: Berthold Reimer, Joanna WASYLUK, Kai Tern Sih, Richard J. Carter, Stephan Kronholz, Yew-Tuck Chow
Принадлежит: Globalfoundries Inc

A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing an integrated circuit comprising a p-type field effect transistor (pFET), recessing a surface region of the pFET using an ammonia-hydrogen peroxide-water (APM) solution to form a recessed pFET surface region, and depositing a silicon-based material channel on the recessed pFET surface region.

Подробнее
Номер записи: 33
15-08-2013 дата публикации

Fabrication method of semiconductor device and fabrication method of dynamic threshold transistor

Номер: US20130210207A1
Автор: Eiji Yoshida, Masahiro Fukuda, Yosuke Shimamune
Принадлежит: Fujitsu Semiconductor Ltd

A method includes: etching a silicon substrate except for a silicon substrate portion on which a channel region is to be formed to form first and second trenches respectively at a first side and a second side of the silicon substrate portion; filling the first and second trenches by epitaxially growing a semiconductor layer having etching selectivity against silicon and further a silicon layer; removing the semiconductor layer selectivity by a selective etching process to form voids underneath the silicon layer respectively at the first side and the second side of the substrate portion; burying the voids at least partially with a buried insulation film; forming a gate insulation film and a gate electrode on the silicon substrate portion; and forming a source region in the silicon layer at the first side of the silicon substrate portion and a drain region at the second side of the silicon substrate portion.

Подробнее
Номер записи: 34
03-10-2013 дата публикации

Integrated circuit structure to resolve deep-well plasma charging problem and method of forming the same

Номер: US20130256801A1
Автор: David Yen, Kuoyuan (Peter) Hsu, Sung-Chieh Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

During various processing operations, ions from process plasma may be transfer to a deep n-well (DNW) formed under devices structures. A reverse-biased diode may be connected to the signal line to protect a gate dielectric formed outside the DNW and is connected to the drain of the transistor formed inside the DNW.

Подробнее
Номер записи: 35
24-10-2013 дата публикации

Semiconductor device

Номер: US20130277738A1
Автор: Hirokazu Sayama
Принадлежит: Renesas Electronics Corp

A semiconductor device is provided, in which work of a parasitic bipolar transistor can be suppressed and a potential difference can be provided between a source region and a back gate region. A high voltage tolerant transistor formed over a semiconductor substrate includes: a well region of a first conductivity type; a first impurity region as the source region; and a second impurity region as a drain region. The semiconductor device further includes a third impurity region and a gate electrode for isolation. The third impurity region is formed, in planar view, between a pair of the first impurity regions, and from which a potential of the well region is extracted. The gate electrode for isolation is formed over the main surface between the first impurity region and the third impurity region.

Подробнее
Номер записи: 36
31-10-2013 дата публикации

Strained structure of semiconductor device and method of making the strained structure

Номер: US20130285153A1
Автор: Cheng-Yi Peng, Chih Chieh Yeh, Clement Hsingjen Wann, FENG Yuan, Tsung-Lin Lee
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An exemplary structure for a field effect transistor (FET) comprises a silicon substrate comprising a first surface; a channel portion over the first surface, wherein the channel portion has a second surface at a first height above the first surface, and a length parallel to first surface; and two source/drain (S/D) regions on the first surface and surrounding the channel portion along the length of the channel portion, wherein the two S/D regions comprise SiGe, Ge, Si, SiC, GeSn, SiGeSn, SiSn, or III-V material.

Подробнее
Номер записи: 37
14-11-2013 дата публикации

Horizontal epitaxy furnace for channel sige formation

Номер: US20130302973A1
Автор: Ines Becker, Joanna WASYLUK, Lindarti Purwaningsih, Stephan Kronholz, Yew Tuck CHOW
Принадлежит: Globalfoundries Inc

A method and apparatus are provided for recessing a channel region of the PFET and epitaxially growing channel SiGe in the recessed region inside of a horizontally oriented processing furnace. Embodiments include forming an n-channel region and a p-channel region in a front side of a wafer and at least one additional wafer, the n-channel and p-channel regions corresponding to locations for forming an NFET and a PFET, respectively; placing the wafers inside a horizontally oriented furnace having a top surface and a bottom surface, with the wafers oriented vertically between the top and bottom surfaces; recessing the p-channel regions of the wafers inside the furnace; and epitaxially growing cSiGe without hole defects in the recessed p-channel regions inside the furnace.

Подробнее
Номер записи: 38
02-01-2014 дата публикации

Cmos devices having strain source/drain regions and low contact resistance

Номер: US20140001561A1
Автор: Alexander Reznicek, Ali Khakifirooz, Kangguo Cheng, Thomas N. Adam
Принадлежит: International Business Machines Corp

A CMOS device structure and method of manufacturing the same are provided. The CMOS device structure includes a substrate having a first region and a second region. The CMOS device structure further includes a first gate formed in the first region overlying a first channel region in the substrate. The CMOS device structure further includes a first pair of source/drain regions formed in the first region on either side of the first channel region. Each region of the pair of source/drain regions has a substantially V-shaped concave top surface.

Подробнее
Номер записи: 39
09-01-2014 дата публикации

Semiconductor device and fabrication process thereof

Номер: US20140008735A1
Автор: Yoshikazu Tsukidate
Принадлежит: Fujitsu Semiconductor Ltd

A disclosed semiconductor device includes a semiconductor substrate including a first area, a gate electrode formed over the first area of the semiconductor substrate, a first active region formed in the first area of the semiconductor substrate at a lateral side of the gate electrode, a first silicide layer formed at least on a sidewall surface of the gate electrode in the first area, the first silicide layer is electrically connected to the first active region.

Подробнее
Номер записи: 40
16-01-2014 дата публикации

Semiconductor device

Номер: US20140015142A1
Автор: Jumpei Sato, Kenichi Abe, Takuya Futatsuyama
Принадлежит: Toshiba Corp

In a semiconductor device, a first contact-diffusion-layer is in a first well to be connected to the first well and extends in a channel width direction of a first transistor in a first well. A second contact-diffusion-layer is in the first well so as to be electrically connected to the first well and extends in a channel-length direction of the first transistor. A first contact on the first contact-diffusion-layer has a shape with a diameter in the channel-width direction larger than that in the channel-length direction when viewed from above the substrate. A second contact on the second contact-diffusion-layer has a shape with a diameter in the channel-width direction smaller than that of the first contact and a diameter in the channel-length direction almost equal to that of the first contact when viewed from above the substrate. A wiring is electrically connected to the first transistor through the second contact.

Подробнее
Номер записи: 41
03-04-2014 дата публикации

Through silicon via and method of fabricating same

Номер: US20140094007A1
Автор: Cornelia Kang-I Tsang, Edmund Juris Sprogis, Paul Stephen Andry
Принадлежит: Ultratech Inc

A through silicon via structure and a method of fabricating the through silicon via. The method includes: (a) forming a trench in a silicon substrate, the trench open to a top surface of the substrate; (b) forming a silicon dioxide layer on sidewalls of the trench, the silicon dioxide layer not filling the trench; (c) filling remaining space in the trench with polysilicon; after (c), (d) fabricating at least a portion of a CMOS device in the substrate; (e) removing the polysilicon from the trench, the dielectric layer remaining on the sidewalls of the trench; (f) re-filling the trench with an electrically conductive core; and after (f), (g) forming one or more wiring layers over the top surface of the substrate, a wire of a wiring level of the one or more wiring levels closest to the substrate contacting a top surface of the conductive core.

Подробнее
Номер записи: 42
10-04-2014 дата публикации

Method for manufacturing a semiconductor device

Номер: US20140099784A1
Автор: Je-Don Kim, Ju-youn Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method for manufacturing a semiconductor device includes forming an insulation film including a trench on a substrate, forming a first metal gate film pattern and a second metal gate film pattern in the trench, redepositing a second metal gate film on the first and second metal gate film patterns and the insulation film, and forming a redeposited second metal gate film pattern on the first and second metal gate film patterns by performing a planarization process for removing a portion of the redeposited second metal gate film so as to expose a top surface of the insulation film, and forming a blocking layer pattern on the redeposited second metal gate film pattern by oxidizing an exposed surface of the redeposited second metal gate film pattern.

Подробнее
Номер записи: 43
13-01-2022 дата публикации

Semiconductor device and method

Номер: US20220013364A1
Автор: Chi On Chui, Tai-Chun Huang, Ting-Gang CHEN, Ya-Lan CHANG, Yung-Cheng Lu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An embodiment includes a method including forming an opening in a cut metal gate region of a metal gate structure of a semiconductor device, conformally depositing a first dielectric layer in the opening, conformally depositing a silicon layer over the first dielectric layer, performing an oxidation process on the silicon layer to form a first silicon oxide layer, filling the opening with a second silicon oxide layer, performing a chemical mechanical polishing on the second silicon oxide layer and the first dielectric layer to form a cut metal gate plug, the chemical mechanical polishing exposing the metal gate structure of the semiconductor device, and forming a first contact to a first portion of the metal gate structure and a second contact to a second portion of the metal gate structure, the first portion and the second portion of the metal gate structure being separated by the cut metal gate plug.

Подробнее
Номер записи: 44
07-01-2016 дата публикации

High Efficiency FinFET Diode

Номер: US20160005660A1
Автор: Chang Sun-Jay, Fan Hsueh-Shih, Hsieh Wen-Hsing, HU Chia-Hsin, Huang Ching-Fang, Liang Min-Chang, Wu Shien-Yang
Принадлежит:

Disclosed are methods to form a FinFET diode of high efficiency, designed to resolve the degradation problem with a conventional FinFET diode arising from reduced active area, and a method of fabrication. The FinFET diode has a doped substrate, two spaced-apart groups of substantially parallel, equally-spaced, elongated semiconductor fin structures, dielectric layers formed between the two groups and among the fin structures for insulation, a plurality of substantially equal-spaced and parallel elongated gate structures perpendicularly traversing both groups of the fin structures, and two groups of semiconductor strips respectively formed lengthwise upon the two groups of the fin structures. The two groups of semiconductor strips are doped to have opposite conductivity types, p-type and n-type. The FinFET diode further has metal contacts formed upon the semiconductor strips. In an embodiment, the semiconductor strips may be integrally formed with the fin structures by epitaxial growth and in-situ doped. 1. A method of forming a semiconductor device , the method comprising:providing a substrate having opposing first and second ends;forming a first and a second groups of one or more substantially equal-spaced, parallel, elongated, and equal numbered semiconductor fin structures upon the substrate adjacent the first and the second ends, respectively, the first and second groups being spaced apart from each other;forming a plurality of dielectric strips to be disposed among the first and the second groups of fin structures for electric insulation from one another;implanting the substrate with a dopant of either a first conductivity type or a second conductivity type opposite the first conductivity type;forming one or more substantially equal-spaced and parallel elongated gate structures formed upon the first and the second groups of fin structures such that each gate structure traverses both the first and the second groups of fin structures perpendicularly;forming a ...

Подробнее
Номер записи: 45
07-01-2021 дата публикации

Method for producing at least one device in compressive strained semiconductor

Номер: US20210005443A1
Автор: Cyrille Le Royer, Fabrice Nemouchi, Loïc Gaben, Nicolas Posseme, Shay REBOH
Принадлежит: Commissariat a lEnergie Atomique et aux Energies Alternatives CEA

Method for producing a semiconductor device, including: producing, on a first region of a surface layer comprising a first semiconductor and disposed on a buried dielectric layer, a layer of a second compressive strained semiconductor along a first direction; etching a trench through the layer of the second semiconductor forming an edge of a portion of the layer of the second semiconductor oriented perpendicularly to the first direction, and wherein the bottom wall is formed by the surface layer; thermal oxidation forming in the surface layer a semiconductor compressive strained portion along the first direction and forming in the trench an oxide portion; producing, through the surface layer and/or the oxide portion, and through the buried dielectric layer, dielectric isolation portions around an assembly formed of the compressive strained semiconductor portion and the oxide portion; and wherein the first semiconductor is silicon, the second semiconductor is SiGe, and said at least one compressive strained semiconductor portion includes SiGe.

Подробнее
Номер записи: 46
04-01-2018 дата публикации

SEMICONDUCTOR CONTACT

Номер: US20180005901A1
Автор: CHI Cheng, Xie Ruilong
Принадлежит:

A method for forming a semiconductor device comprises forming a gate stack on a channel region of a semiconductor, forming a source/drain region adjacent to the channel region, depositing a first insulator layer over the source/drain region, and removing a portion of the first insulator layer to form a first cavity that exposes a portion of the source/drain region. A first conductive material is deposited in the first cavity, and a conductive extension is formed from the first conductive material over the first insulator layer. A protective layer is deposited over the extension and a second insulator layer is deposited over the protective layer. A portion of the second insulator layer is removed to form a second cavity that exposes the protective layer, and an exposed portion of the protective layer is removed to expose a portion of the extension. A second conductive material is deposited in the second cavity. 1. A method for forming a semiconductor device , the method comprising:forming a gate stack on a channel region of a semiconductor, the gate stack including sidewalls extending from a gate stack upper surface to a gate stack base that contacts the channel region, and including gate spacers formed on the sidewalls;forming a source/drain region adjacent to the channel region;depositing a first insulator layer over the source/drain region;removing a portion of the first insulator layer to form a first cavity that exposes a portion of the source/drain region;depositing a first conductive material in the first cavity, the first conductive material including conductive sidewalls extending from a conductive base that contacts the source/drain region to a conductive upper surface, the conductive upper surface being flush with the gate stack upper surface;forming a conductive extension from the first conductive material over the first insulator layer and over the gate spacers;depositing a protective layer over the conductive extension and over the gate stack upper ...

Подробнее
Номер записи: 47
04-01-2018 дата публикации

SEMICONDUCTOR DEVICE INCLUDING DUAL TRENCH EPITAXIAL DUAL-LINER CONTACTS

Номер: US20180005903A1
Автор: Basker Veeraraghavan S., Cheng Kangguo, STANDAERT Theodorus E., Wang Junli
Принадлежит:

A complementary metal-oxide-semiconductor field-effect transistor (CMOS) device includes a first source/drain (S/D) region and a second S/D region different from the first S/D region. A first epitaxy film formed of a first semiconductor material is on the first S/D region. A second epitaxy film formed of a second semiconductor material is on the second S/D region. The CMOS device further includes first and second S/D contact stacks. The first S/D contact stack includes a first contact trench liner having a first inner side wall extending from a first base portion to an upper surface of the first S/D contact stack. The second S/D contact stack includes a second contact trench liner having a second inner side wall extending from a second base portion to an upper surface of the second S/D contact stack. The first inner sidewall directly contacts the second inner sidewall. 1. A method of forming contact trench liners in a complementary metal-oxide-semiconductor field-effect transistor (CMOS) device , the method comprising:forming a first contact trench over a first source/drain (S/D) region of a n-type transistor (NFET);forming a second contact trench over a second S/D region of a p-type transistor (PFET);forming a first epi film on both the first S/D region and the second S/D region;replacing the first epi film with a different second epi film on the first S/D region;depositing a first contact trench liner comprising a first liner material in the first contact trench without depositing the first contact trench liner in the second contact trench, and depositing a first S/D conductive contact material in the first contact trench; andafter depositing the first contact trench liner, depositing a second contact trench liner comprising a second liner material in the second contact trench, and depositing a second S/D conductive contact material in the second contact trench,wherein the second liner material is different from the first liner material.3. The method of claim 2 , ...

Подробнее
Номер записи: 48
04-01-2018 дата публикации

VERTICAL CMOS DEVICES WITH COMMON GATE STACKS

Номер: US20180005904A1
Автор: Lee Choonghyun, OK Injo, Seo Soon-Cheon
Принадлежит:

A semiconductor structure includes a first nanowire of a first material formed on a substrate, at least a second nanowire of a second material different than the first material formed on the substrate and a common gate stack surrounding the first nanowire and the second nanowire. The first nanowire and the second nanowire are vertical with respect to a horizontal plane of the substrate. The first material may be indium gallium arsenide (InGaAs) and the first nanowire may form part of an NFET channel of a CMOS device, while the second material may be germanium (Ge) and the second nanowire may form part of a PFET channel of the CMOS device. 1. A semiconductor structure , comprising:a first nanowire of a first material formed on a substrate;at least a second nanowire of a second material different than the first material formed on the substrate; anda common gate stack surrounding the first nanowire and the second nanowire;wherein the first nanowire and the second nanowire are vertical with respect to a horizontal plane of the substrate.2. The semiconductor structure of claim 1 , wherein the first material comprises a group III-V material and the second material comprises a group II-IV material.3. The semiconductor structure of claim 1 , wherein the first material comprises indium gallium arsenide (InGaAs) and the first nanowire forms at least a portion of a negative field-effect transistor (NFET) channel of a complementary metal-oxide-semiconductor (CMOS) device claim 1 , and the second material comprises germanium (Ge) and the second nanowire forms at least a portion of a positive field-effect transistor (PFET) channel of the CMOS device.4. The semiconductor structure of claim 1 , wherein the first nanowire comprises a first dummy channel surrounded by the first material and the second nanowire comprises a second dummy channel surrounded by the second material claim 1 , the first dummy channel and the second dummy channel comprising a third material different than the ...

Подробнее
Номер записи: 49
04-01-2018 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20180005943A1
Автор: LEE Hyung Jong, YOON Changseop, YOON Kwangsub, YOUN Jongmil
Принадлежит:

A semiconductor device includes a substrate including PMOSFET and NMOSFET regions, a first gate structure extending in a first direction and crossing the PMOSFET and NMOSFET regions, and a gate contact on and connected to the first gate structure, the gate contact being between the PMOSFET and NMOSFET regions, the gate contact including a first sub contact in contact with a top surface of the first gate structure, the first sub contact including a vertical extending portion extending vertically toward the substrate along one sidewall of the first gate structure, and a second sub contact spaced apart from the first gate structure, a top surface of the second sub contact being positioned at a same level as a top surface of the first sub contact. 127.-. (canceled)28. A semiconductor device , comprising:a substrate including an active pattern extending in a first direction;a device isolation layer on the substrate, the device isolation layer defining the active pattern;a first gate structure on the active pattern and the device isolation layer, the first gate structure extending in a second direction crossing the first direction; anda gate contact connected to the first gate structure,wherein a whole of the gate contact vertically overlaps the device isolation layer,wherein the gate contact includes a vertical extending portion extending vertically toward the device isolation layer along one sidewall of the first gate structure, andwherein a bottom surface of the vertical extending portion is spaced apart from a top surface of the device isolation layer.29. The semiconductor device as claimed in claim 28 , wherein the device isolation layer covers a sidewall of a lower portion of the active pattern claim 28 , andwherein an upper portion of the active pattern vertically protrudes with respect to the top surface of the device isolation layer.30. The semiconductor device as claimed in claim 28 , wherein the gate contact further includes:a first portion in contact with a ...

Подробнее
Номер записи: 50
04-01-2018 дата публикации

METHOD FOR CAPPING CU LAYER USING GRAPHENE IN SEMICONDUCTOR

Номер: US20180005952A1
Автор: ZHOU MING
Принадлежит:

An interconnect structure includes a substrate, a dielectric layer on the substrate, a metal interconnect layer in the dielectric layer and in contact with the substrate, the metal interconnect layer having an upper surface flush with an upper surface of the dielectric layer, and a graphene layer on the metal interconnect layer. The graphene layer insulates a metal from air and prevents the metal from being oxidized by oxygen in the air, thereby increasing the queue time for the CMP process and the device reliability. 1. A method of manufacturing an interconnect structure , the method comprising:providing a semiconductor structure comprising a substrate, a dielectric layer on the substrate, and a metal interconnect layer in the dielectric layer and in contact with the substrate; andforming a graphene layer on the metal interconnect layer.2. The method of claim 1 , wherein forming the graphene layer comprises forming an amorphous carbon layer on the dielectric layer claim 1 , the amorphous carbon layer being adjacent to the graphene layer.3. The method of claim 1 , wherein forming the graphene layer comprises introducing methane and a carrier gas into a reaction chamber to form a mixed gas claim 1 , the mixed gas having a volume ratio of methane in a range between 0.1% and 50% claim 1 , at a temperature in a range between 300° C. and 450° C. claim 1 , under a pressure in a range between 0.1 mTorr and 10 Torr claim 1 , and a radio frequency power in a range between 10 W and 1000 W.4. The method of claim 3 , wherein the carrier gas comprises nitrogen claim 3 , or hydrogen claim 3 , or nitrogen and hydrogen.5. The method of claim 1 , further comprising claim 1 , prior to forming the graphene layer: performing a hydrogen plasma cleaning process on an upper surface of the metal interconnect layer.6. The method of claim 5 , wherein performing the hydrogen plasma cleaning process comprises: introducing a hydrogen gas into a reaction chamber at a flow rate in a range between ...

Подробнее
Номер записи: 51
07-01-2021 дата публикации

Integrated iii-v device and driver device packages with improved heat removal and methods for fabricating the same

Номер: US20210005531A1
Автор: Donald Ray Disney
Принадлежит: GlobalFoundries US Inc

Integrated circuits, wafer level integrated III-V device and CMOS driver device packages, and methods for fabricating products with integrated III-V devices and silicon-based driver devices are provided. In an embodiment, an integrated circuit includes a semiconductor substrate, a plurality of transistors overlying the semiconductor substrate, and an interlayer dielectric layer overlying the plurality of transistors with a metallization layer disposed within the interlayer dielectric layer. The plurality of transistors and the metallization layer form a gate driver circuit. The integrated circuit further includes a plurality of vias disposed through the interlayer dielectric layer, a gate driver electrode coupled to the gate driver circuit, a III-V device electrode overlying and coupled to the gate driver electrode, and a III-V device overlying and coupled to the III-V device electrode.

Подробнее
Номер записи: 52
04-01-2018 дата публикации

FIN FIELD EFFECT TRANSISTOR (FET) (FINFET) COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) CIRCUITS EMPLOYING SINGLE AND DOUBLE DIFFUSION BREAKS FOR INCREASED PERFORMANCE

Номер: US20180006035A1
Автор: Liu Yanxiang, RIM Kern, Yuan Jun
Принадлежит:

Fin Field Effect Transistor (FET) (FinFET) complementary metal oxide semiconductor (CMOS) circuits with single and double diffusion breaks for increased performance are disclosed. In one aspect, a FinFET CMOS circuit employing single and double diffusion breaks includes a P-type FinFET that includes a first Fin formed from a semiconductor substrate and corresponding to a P-type diffusion region. The FinFET CMOS circuit includes an N-type FinFET that includes a second Fin formed from the semiconductor substrate and corresponding to an N-type diffusion region. To electrically isolate the P-type FinFET, first and second single diffusion break (SDB) isolation structures are formed in the first Fin on either side of a gate of the P-type FinFET. To electrically isolate the N-type FinFET, first and second double diffusion break (DDB) isolation structures are formed in the second Fin on either side of a gate of the N-type FinFET. 1. A Fin Field Effect Transistor (FinFET) complementary metal oxide semiconductor (CMOS) circuit , comprising:a semiconductor substrate;a P-type FinFET comprising a first Fin formed from the semiconductor substrate and corresponding to a P-type semiconductor material (P-type) diffusion region;an N-type FinFET comprising a second Fin formed from the semiconductor substrate and corresponding to an N-type semiconductor material (N-type) diffusion region;a first single diffusion break (SDB) isolation structure formed in the first Fin on a first side of a gate of the P-type FinFET;a second SDB isolation structure formed in the first Fin on a second side of the gate of the P-type FinFET opposite of the first side of the gate of the P-type FinFET;a first double diffusion break (DDB) isolation structure formed in the second Fin on a first side of a gate of the N-type FinFET; anda second DDB isolation structure formed in the second Fin on a second side of the gate of the N-type FinFET opposite of the first side of the gate of the N-type FinFET.2. The FinFET ...

Подробнее
Номер записи: 53
04-01-2018 дата публикации

FABRICATION OF VERTICAL DOPED FINS FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS

Номер: US20180006036A1
Автор: Cheng Kangguo, Liu Zuoguang, Mehta Sanjay C., Yamashita Tenko
Принадлежит:

A method of forming a fin field effect transistor (finFET) with a doped substrate region, including forming a plurality of vertical fins on a substrate, forming a first dopant source on one or more of the plurality of vertical fins, wherein the first dopant source is not formed on at least one vertical fin, forming a second dopant source on the at least one vertical fin that does not have a first dopant source formed thereon, and heat treating the plurality of vertical fins on the substrate, the first dopant source, and the second dopant source, wherein the heat treatment is sufficient to cause a first dopant from the first dopant source to diffuse into at least a first portion of the substrate, and a second dopant from the second dopant source to diffuse into at least a second portion of the substrate. 1. A method of forming a fin field effect transistor (finFET) with a doped substrate region , comprising:forming a plurality of vertical fins on a substrate;forming a first dopant source on one or more of the plurality of vertical fins, wherein the first dopant source is not formed on at least one vertical fin;forming a second dopant source on the at least one vertical fin that does not have the first dopant source formed thereon;{'sup': 17', '3', '19', '3', '17', '3', '19', '3, 'heat treating the plurality of vertical fins on the substrate, the first dopant source, and the second dopant source, wherein the heat treatment sufficient to cause a first dopant from the first dopant source to diffuse into at least a first portion of the substrate to form a first punch-through stop/well extending about 10 nm to about 30 nm into the substrate from the interface with the first dopant source, and a second dopant from the second dopant source to diffuse into at least a second portion of the substrate to form a second punch-through stop/well extending about 10 nm to about 30 nisi into the substrate from the interface with the second dopant source, wherein the concentration of ...

Подробнее
Номер записи: 54
04-01-2018 дата публикации

SEMICONDUCTOR DEVICE, STATIC RANDOM ACCESS MEMORY CELL AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Номер: US20180006039A1
Автор: KWOK Tsz-Mei, Lee Yi-Jing, Li Kun-Mu, Yu Ming-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A semiconductor device includes a substrate, a first semiconductor fin, a second semiconductor fin, an n-type epitaxy structure, a p-type epitaxy structure, and a plurality of dielectric fin sidewall structures. The first semiconductor fin is disposed on the substrate. The second semiconductor fin is disposed on the substrate and adjacent to the first semiconductor fin. The n-type epitaxy structure is disposed on the first semiconductor fin. The p-type epitaxy structure is disposed on the second semiconductor fin and separated from the n-type epitaxy structure. The dielectric fin sidewall structures are disposed on opposite sides of at least one of the n-type epitaxy structure and the p-type epitaxy structure. 1. A static random access memory (SRAM) cell comprising: a semiconductor fin comprising at least one recessed portion and at least one channel portion;', 'an epitaxy structure over the recessed portion of the semiconductor fin; and', 'a plurality of dielectric fin sidewall structures on opposite sides of the epitaxy structure., 'two pull-up (PU) transistors, two pass-gate (PG) transistors, and two pull-down (PD) transistors, wherein the PU transistors and the PD transistors are configured to form two cross-coupled inverters, the PG transistors are electrically connected to the cross-coupled inverters, and at least one of the PU transistors, the PG transistors, and the PD transistors comprises2. The SRAM cell of claim 1 , wherein the epitaxy structure comprises:a top portion having a first width; anda body portion between the top portion and the semiconductor fin and having a second width shorter than the first width, wherein the dielectric fin sidewall structures are disposed on opposite sides of the body portion of the epitaxy structure, and the top portion of the epitaxy structure is over the dielectric fin sidewall structures.3. The SRAM cell of claim 2 , wherein the semiconductor fin has a third width substantially the same as the second width of the body ...

Подробнее
Номер записи: 55
07-01-2021 дата публикации

INTEGRATED CIRCUIT DEVICE

Номер: US20210005606A1
Автор: Chung Jae-yup, KIM Il-ryong, Kim Ju-Youn, LEE Min-seong, Yeo Kyoung-Hwan, YOON Ji-hoon
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

An integrated circuit device includes a first fin separation insulating portion over the first device region; a pair of first fin-type active regions apart from each other with the first fin separation insulating portion therebetween and collinearly extending in a first horizontal direction; a first dummy gate structure vertically overlapping the first fin separation insulating portion; a second fin separation insulating portion apart from the first fin separation insulating portion and arranged over the second device region; and a plurality of second fin-type active regions apart from each other with the second fin separation insulating portion therebetween in the second device region and collinearly extending in the first horizontal direction, wherein a vertical level of a lowermost surface of the second fin separation insulating portion is equal to or lower than a vertical level of a lowermost surface of the first fin separation insulating portion. 1. An integrated circuit device comprising:a substrate comprising a first device region and a second device region;a first fin separation insulating portion over the first device region, the first fin separation insulating portion having a first vertical length in a vertical view;a pair of first fin-type active regions spaced apart from each other in the first device region with the first fin separation insulating portion therebetween, the pair of first fin-type active regions collinearly extending in a first horizontal direction;a plurality of dummy gate structures extending parallel to each other in a second horizontal direction over the first fin separation insulating portion and the pair of first fin-type active regions, the second horizontal direction crossing the first horizontal direction;a second fin separation insulating portion spaced apart from the first fin separation insulating portion and arranged over the second device region, the second fin separation insulating portion having a second vertical length ...

Подробнее
Номер записи: 56
04-01-2018 дата публикации

STRAINED AND UNSTRAINED SEMICONDUCTOR DEVICE FEATURES FORMED ON THE SAME SUBSTRATE

Номер: US20180006119A1
Автор: Cheng Kangguo, Li Juntao, Xu Peng
Принадлежит:

Embodiments are directed to a method of forming a feature of a semiconductor device. The method includes forming the feature from a semiconductor material having compressive strain that extends throughout a cut region of the feature and throughout a preserve region of the feature. The method further includes converting the cut region of the feature to a dielectric. 1. A method of forming a feature of a semiconductor device , the method comprising:forming the feature from a semiconductor material;wherein the feature comprises a preserve region and a cut region;wherein the feature comprises compressive strain imparted to the feature by the semiconductor material;wherein the compressive strain extends throughout the cut region of the feature and throughout the preserve region of the feature; andconverting the cut region of the feature to a dielectric.2. The method of claim 1 , wherein the feature comprises a fin.3. The method of claim 2 , wherein the preserve region of the fin comprises a channel region of the semiconductor device.4. The method of further comprising forming a gate over the channel region.5. The method of claim 1 , wherein converting the cut region of the feature to a dielectric comprises oxidizing the cut region.6. The method of claim 1 , wherein:the feature is formed on a silicon substrate; andthe semiconductor material comprises silicon germanium.7. The method of claim 1 , wherein:the compressive strain extending throughout the cut region and the preserve region comprises a predetermined percentage of compressive strain; andconverting the cut region of the feature to a dielectric does not reduce the predetermined percentage.8. The method of claim 7 , wherein converting the cut region of the feature to a dielectric increases the predetermined percentage.9. A method of forming features of semiconductor devices claim 7 , the method comprising:forming a first feature on a substrate, wherein the first feature comprises a first semiconductor material ...

Подробнее
Номер записи: 57
07-01-2021 дата публикации

DOPED INSULATOR CAP TO REDUCE SOURCE/DRAIN DIFFUSION FOR GERMANIUM NMOS TRANSISTORS

Номер: US20210005722A1
Автор: Bomberger Cory C., Chouksey Siddharth, Chu-Kung Benjamin, Ghani Tahir, Glass Glenn A., JAMBUNATHAN KARTHIK, Kavalieros Jack T., Murthy Anand S., SUNG Seung Hoon
Принадлежит: Intel Corporation

Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent insulator regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, a dopant-rich insulator cap is deposited adjacent to the source and/or drain regions, to provide dopant diffusion reduction. In some embodiments, the dopant-rich insulator cap is doped with an n-type impurity including Phosphorous in a concentration between 1 and 10% by atomic percentage. In some embodiments, the dopant-rich insulator cap may have a thickness in the range of 10 to 100 nanometers and a height in the range of 10 to 200 nanometers. 125-. (canceled)26. An integrated circuit (IC) comprising:a body of semiconductor material including at least 75% germanium by atomic percentage;a gate structure on the body, the gate structure including a gate dielectric and a gate electrode;a source region and a drain region both adjacent to the gate structure such that the gate structure is between the source and drain regions, at least one of the source region and the drain region including n-type impurity; anda dopant-rich insulator cap region between the at least one of the source region and the drain region and an undoped insulator region, the dopant-rich insulator cap region including the n-type impurity, the dopant-rich insulator cap region distinct from the undoped insulator region.27. The IC of claim 26 , wherein the n-type impurity is phosphorous.28. The IC of claim 26 , wherein the n-type impurity is arsenic.29. The IC of claim 26 , wherein the body further includes at least one of silicon claim 26 , indium claim 26 , gallium claim 26 , arsenic claim 26 , antimony claim 26 , and nitrogen.30. The IC of claim 26 , wherein the germanium concentration of the body is 98 atomic percent or more.31. The IC of claim 26 ...

Подробнее
Номер записи: 58
02-01-2020 дата публикации

Fin Field-Effect Transistor Device And Method

Номер: US20200006077A1
Автор: Chou Hung-Ju, Kuo Jiun-Ming, Li Chun Te, Lin Wei-Ken, Wang Yin
Принадлежит:

A method includes forming a semiconductor capping layer over a first fin in a first region of a substrate, forming a dielectric layer over the semiconductor capping layer, and forming an insulation material over the dielectric layer, an upper surface of the insulation material extending further away from the substrate than an upper surface of the first fin. The method further includes recessing the insulation material to expose a top portion of the first fin, and forming a gate structure over the top portion of the first fin. 1. A Fin Field-Effect Transistor (FinFET) device comprising:a substrate;a fin protruding above the substrate;isolation regions on opposing sides of the fin;a silicon capping layer between the fin and the isolation regions;a first dielectric material between the silicon capping layer and the isolation regions; anda second dielectric material different from the first dielectric material between the first dielectric material and the isolation regions, the second dielectric material comprising an oxide of the first dielectric material.2. The FinFET device of claim 1 , wherein a top portion of the fin distal from the substrate comprises a first semiconductor material claim 1 , and a bottom portion of the fin proximate to the substrate comprises a second semiconductor material different from the first semiconductor material.3. The FinFET device of claim 2 , wherein the first semiconductor material is silicon germanium claim 2 , wherein the bottom portion of the fin and the substrate comprise the second semiconductor material.4. The FinFET device of claim 1 , wherein the first dielectric material comprises silicon nitride claim 1 , and the second dielectric material comprises silicon oxynitride.5. The FinFET device of claim 1 , wherein a ratio between a thickness of the second dielectric material and a thickness of the first dielectric material is about 1:2.6. The FinFET device of claim 1 , wherein the first dielectric material and the second ...

Подробнее
Номер записи: 59
02-01-2020 дата публикации

Method for producing a through semiconductor via connection

Номер: US20200006142A1
Автор: Gaspard Hiblot, Geert Van Der Plas, Stefaan Van Huylenbroeck
Принадлежит: Interuniversitair Microelektronica Centrum vzw IMEC

A method of producing a through semiconductor via (TSV) connection is disclosed. In one aspect, an opening of the TSV is produced for contacting a first semiconductor die bonded to a second die or to a temporary carrier. The first die includes fin-shaped devices in the front end of line of the die. Etching of the TSV opening does not end on a metal pad, but the opening is etched until reaching a well that is formed of material of a first doping type and formed in the first die amid semiconductor material of a second doping type opposite the first. After filling the TSV opening with a conductive material, the TSV connects to a conductor of an intermediate metallization (IM) of the first die through at least one fin extending from the well and connected to the conductor. A package of dies comprising at least one TSV produced by the above method is also disclosed.

Подробнее
Номер записи: 60
02-01-2020 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Номер: US20200006153A1
Автор: Chen Wei-Jen, Lee Kai-Lin, Lee Zhi-Cheng
Принадлежит:

A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; forming a first gate structure and a second gate structure on the first fin-shaped structure; using a patterned mask to remove the first gate structure and part of the first fin-shaped structure to form a first trench; and forming a first dielectric layer in the first trench to form a first single diffusion break (SDB) structure and around the second gate structure. 1. A method for fabricating semiconductor device , comprising:providing a substrate having a first region and a second region;forming a first fin-shaped structure on the first region;forming a first gate structure and a second gate structure on the first fin-shaped structure;using a patterned mask to remove the first gate structure and part of the first fin-shaped structure to form a first trench; andforming a first dielectric layer in the first trench to form a first single diffusion break (SDB) structure and around the second gate structure.2. The method of claim 1 , further comprising:forming the first fin-shaped structure on the first region and a second fin-shaped structure on the second region;removing part of the second fin-shaped structure to form a second trench;forming a second dielectric layer in the second trench; andplanarizing the second dielectric layer to form a second SDB structure.3. The method of claim 2 , wherein the first fin-shaped structure and the second fin-shaped structure are disposed extending along a first direction and the first SDB structure and the second SDB structure are disposed extending along a second direction.4. The method of claim 3 , wherein the first direction is orthogonal to the second direction.5. The method of claim 2 , wherein the first SDB structure and the second SDB structure comprise different materials.6. The method of claim 2 , further comprising:forming the first ...

Подробнее
Номер записи: 61
02-01-2020 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Номер: US20200006154A1
Автор: CHEN I-Sheng, Chen Tzu-Chiang, CHIANG Hung-Li
Принадлежит:

A semiconductor device includes a first plurality of stacked nanowire structures extending in a first direction disposed over a first region of a semiconductor substrate. Each nanowire structure of the first plurality of stacked nanowire structures includes a plurality of nanowires arranged in a second direction substantially perpendicular to the first direction. A nanowire stack insulating layer is between the substrate and a nanowire closest to the substrate of each nanowire structure of the first plurality of stacked nanowire structures. At least one second stacked nanowire structure is disposed over a second region of the semiconductor substrate, and a shallow trench isolation layer is between the first region and the second region of the semiconductor substrate. 1. A semiconductor device , comprising:a first plurality of stacked nanowire structures extending in a first direction disposed over a first region of a semiconductor substrate,wherein each nanowire structure of the first plurality of stacked nanowire structures includes a plurality of nanowires arranged in a second direction substantially perpendicular to the first direction;a nanowire stack insulating layer between the substrate and a nanowire closest to the substrate of each nanowire structure of the first plurality of stacked nanowire structures;at least one second stacked nanowire structure disposed over a second region of the semiconductor substrate; anda shallow trench isolation layer between the first region and the second region of the semiconductor substrate.2. The semiconductor device of claim 1 , wherein there are no shallow trench isolation layers between the stacked nanowire structures of the first plurality of stacked nanowire structures.3. The semiconductor device of claim 1 , wherein the first plurality of stacked nanowire structures are disposed over a common mesa structure.4. The semiconductor device of claim 1 , further comprising a gate structure defining a channel region disposed ...

Подробнее
Номер записи: 62
02-01-2020 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Номер: US20200006155A1
Автор: CHEN Chih-Liang, CHEN I-Sheng, Chen Tzu-Chiang, CHIANG Hung-Li, Chou Lei-Chun
Принадлежит:

A method of manufacturing a semiconductor device includes forming a plurality of fin structures extending in a first direction over a semiconductor substrate. Each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate. An electrically conductive layer is formed between the first regions of a first adjacent pair of fin structures. A gate electrode structure is formed extending in a second direction substantially perpendicular to the first direction over the fin structure second region, and a metallization layer including at least one conductive line is formed over the gate electrode structure. 1. A method of manufacturing a semiconductor device , comprising:forming a plurality of fin structures extending in a first direction over a semiconductor substrate,wherein each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate;forming an electrically conductive layer between the first regions of a first adjacent pair of fin structures;forming a gate electrode structure extending in a second direction substantially perpendicular to the first direction over the fin structure second region; andforming a metallization layer including at least one conductive line over the gate electrode structure.2. The method according to claim 1 , wherein forming a plurality of fin structures comprises forming a nanowire structure in the second region of the fin structure.3. The method according to claim 2 , wherein forming the gate electrode structure comprises:forming a gate dielectric layer over at least one wire of the nanowire structure; andforming a gate electrode layer over the gate dielectric layer,wherein the gate dielectric layer and the gate electrode layer wrap around the at least one wire of the nanowire structure.4. The method according to claim 1 , wherein forming an electrically conductive layer comprises:forming ...

Подробнее
Номер записи: 63
02-01-2020 дата публикации

Nonplanar Device and Strain-Generating Channel Dielectric

Номер: US20200006156A1
Автор: Ching Kuo-Cheng, Fung Ka-Hing, Wu Zhiqiang
Принадлежит:

Various methods are disclosed herein for fabricating non-planar circuit devices having strain-producing features. An exemplary method includes forming a fin structure that includes a first portion that includes a first semiconductor material and a second portion that includes a second semiconductor material that is different than the first semiconductor material. The method further includes forming a masking layer over a source region and a drain region of the fin structure, forming a strain-producing feature over the first portion of the fin structure in a channel region, removing the masking layer and forming an isolation feature over the strain-producing feature, forming an epitaxial feature over the second portion of the fin structure in the source region and the drain region, and performing a gate replacement process to form a gate structure over the second portion of the fin structure in the channel region. 1. A transistor comprising:a fin structure having a first portion disposed between second portions, wherein the first portion and the second portions include a first semiconductor material disposed over a second semiconductor material, wherein the second semiconductor material is different than the first semiconductor material;an isolation feature disposed over sidewalls of the second semiconductor material of the first portion of the fin structure and sidewalls of the second semiconductor material of the second portions of the fin structure;a gate structure disposed over sidewalls and a top surface of the first semiconductor material of the first portion of the fin structure;epitaxial features disposed over a top surface of the first semiconductor material of the second portions of the fin structure; anda strain-producing layer disposed between the isolation feature and the sidewalls of the second semiconductor material of the first portion of the fin structure, wherein the strain-producing layer includes a semiconductor oxide material.2. The transistor of ...

Подробнее
Номер записи: 64
02-01-2020 дата публикации

Methods of Forming Metal Gate Spacer

Номер: US20200006158A1
Автор: Chen Yen-Ming, Chen Yen-Ting, LEE Wei-Yang, Liu Yi-Hsiu, Yang Feng-Cheng
Принадлежит:

A method includes providing dummy gate structures disposed over a device region and over an isolation region adjacent the active region, first gate spacers disposed along sidewalls of the dummy gate structures in the active region, and second gate spacers disposed along sidewalls of the dummy gate structures in the isolation region, removing top portions of the second, but not the first gate spacers, forming a first dielectric layer over the first gate spacers and remaining portions of the second gate spacers, replacing the dummy gate structures with metal gate structures after the forming of the first dielectric layer, removing the first gate spacers after the replacing of the dummy gate structures, and forming a second dielectric layer over top surfaces of the metal gate structures and of the first dielectric layer. 1. A method , comprising:providing dummy gate structures disposed over an active region and over an isolation region adjacent to the active region, a first gate spacer disposed along sidewalls of the dummy gate structures in the active region, and a second gate spacer disposed along sidewalls of the dummy gate structures in the isolation region;removing top portions of the second gate spacer, but not the first gate spacer;forming a first dielectric layer over the first gate spacer and remaining portions of the second gate spacer;after forming the first dielectric layer, replacing the dummy gate structures with metal gate structures;after replacing the dummy gate structures, removing the first gate spacer; andforming a second dielectric layer over top surfaces of the metal gate structures and of the first dielectric layer.2. The method of claim 1 , wherein the first and the second gate spacers include the same composition.3. The method of claim 1 , wherein removing the top portions of the second gate spacer includes:forming a patterned mask over the active region, thereby exposing the isolation region; andselectively etching the top portions of the ...

Подробнее
Номер записи: 65
02-01-2020 дата публикации

Epitaxial Layers in Source/Drain Contacts and Methods of Forming the Same

Номер: US20200006159A1
Автор: Ding-Kang SHIH, Pang-Yen Tsai
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method includes providing a p-type S/D epitaxial feature and an n-type source/drain (S/D) epitaxial feature, forming a semiconductor material layer over the n-type S/D epitaxial feature and the p-type S/D epitaxial feature, processing the semiconductor material layer with a germanium-containing gas, where the processing of the semiconductor material layer forms a germanium-containing layer over the semiconductor material layer, etching the germanium-containing layer, where the etching of the germanium-containing layer removes the germanium-containing layer formed over the n-type S/D epitaxial feature and the semiconductor material layer formed over the p-type S/D epitaxial feature, and forming a first S/D contact over the semiconductor material layer remaining over the n-type S/D epitaxial feature and a second S/D contact over the p-type S/D epitaxial feature. The semiconductor material layer may have a composition similar to that of the n-type S/D epitaxial feature.

Подробнее
Номер записи: 66
02-01-2020 дата публикации

Methods of Forming Contact Features in Field-Effect Transistors

Номер: US20200006160A1
Автор: Chang Shang-Wen, CHIU Yi-Hsun, Lin Yi-Hsiung
Принадлежит:

A method includes forming an interlayer dielectric (ILD) layer over a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature, where the first epitaxial S/D feature is disposed adjacent to the second epitaxial S/D feature, forming a dummy contact feature in the ILD layer over the first epitaxial S/D feature, removing a portion of the dummy contact feature and a portion of the ILD layer disposed above the second epitaxial S/D feature to form a first trench, removing a remaining portion of the dummy contact feature to form a second trench, and forming a metal S/D contact in the first and the second trenches. 1. A method comprising:forming an interlayer dielectric (ILD) layer over a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature, wherein the first epitaxial S/D feature is disposed adjacent to the second epitaxial S/D feature;forming a dummy contact feature in the ILD layer over the first epitaxial S/D feature;removing a portion of the dummy contact feature and a portion of the ILD layer disposed above the second epitaxial S/D feature to form a first trench;removing a remaining portion of the dummy contact feature to form a second trench; andforming a metal S/D contact in the first and the second trenches.2. The method of claim 1 , wherein removing the remaining portion of the dummy contact feature includes selectively etching the dummy contact feature relative to the ILD layer.3. The method of claim 1 , wherein removing the remaining portion of the dummy contact feature exposes the first epitaxial S/D feature claim 1 , such that the metal S/D contact directly contacts the first epitaxial S/D feature but not the second epitaxial S/D feature.4. The method of claim 1 , wherein the dummy contact feature includes a dielectric material different from a dielectric material of the ILD layer.5. The method of claim 4 , wherein the dummy contact feature includes a carbon-containing dielectric material.6. The method of claim 1 , ...

Подробнее
Номер записи: 67
03-01-2019 дата публикации

Production of semiconductor regions in an electronic chip

Номер: US20190006229A1
Автор: Franck Julien
Принадлежит: STMICROELECTRONICS ROUSSET SAS

A method can be used for fabricating first and second semiconductor regions separated by isolating trenches. A semiconductor substrate is covered with a first silicon nitride layer. The first region is covered with a protection layer that can be etched selectively with respect to the silicon nitride. The structure is covered with a second silicon nitride layer. The trenches are etched through the second and first silicon nitride layers and filled with a filling silicon oxide to a level situated above the protection layer. The second silicon nitride layer and the part of the first silicon nitride layer situated on the second region are selectively removed and the protection layer is removed. The filling oxide is selectively etched by wet etching, thus resulting in pits on the surface of the filling oxide around the second region.

Подробнее
Номер записи: 68
02-01-2020 дата публикации

VERTICAL GATE-ALL-AROUND TFET

Номер: US20200006350A1
Автор: Zhang John H.
Принадлежит:

A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes. 1. (canceled)2. A device , comprising:a substrate that includes a first side and a second side facing away from the first side;a doped well extends into the first side of the substrate;a drain region on the first side of the substrate, the drain region is coupled to the doped well;a first dielectric layer;a source region on the first side of the substrate, the source region aligned with the drain region and separated from the drain region by the first dielectric layer, the first dielectric layer being between the source region and the drain region;a gate region on the first side of the substrate, the gate region surrounding the first dielectric layer between the source region and the drain region;a first spacer adjacent to the drain region, the first spacer separates the gate region from the doped well;a contact on the first side of the substrate, the contact aligned with the doped well, the drain region, and the source region; anda second spacer adjacent to the source region, the second spacer ...

Подробнее
Номер записи: 69
03-01-2019 дата публикации

Power Gating for Three Dimensional Integrated Circuits (3DIC)

Номер: US20190006346A1
Автор: Chien-Ju Chao, Chou-Kun LIN, Chung-Hsing Wang, Kuo-Nan Yang, Po-Hsiang Huang, Yen-Hung Lin, Yi-Chuin Tsai
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A device comprises a first interconnect structure over a first active device layer, a first power circuit in the first active device layer, a second active device layer over and in contact with the first interconnect structure, a first switch in the second active device layer, a second interconnect structure over and in contact with the second active device layer, a third active device layer over and in contact with the second interconnect structure, a second power circuit in the third active device layer and a third interconnect structure over and in contact with the third active device layer and connected to a power source, wherein the power source is configured to provide power to the first power circuit through the first switch.

Подробнее
Номер записи: 70
03-01-2019 дата публикации

SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF

Номер: US20190006351A1
Автор: Zhou Fei
Принадлежит:

Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate having at least one diode region; forming at least one first fin on the semiconductor substrate in the diode region; forming a first doped layer containing a first type of doping ions having a first conductivity in the first fin; and forming a second doped layer doped containing a second type of doping ions having a second conductivity opposite to the first conductivity on the first doped layer. A size of an interface between the first doped layer and the second doped layer along a width direction of the first fin is greater than a width of the first fin. 1. A method for fabricating a semiconductor structure , comprising:providing a semiconductor substrate having at least one diode region;forming at least one first fin on the semiconductor substrate in the diode region;forming a first doped layer containing a first type of doping ions having a first conductivity in the first fin; andforming a second doped layer doped containing a second type of doping ions having a second conductivity opposite to the first conductivity on the first doped layer,wherein a size of an interface between the first doped layer and the second doped layer along a width direction of the first fin is greater than a width of the first fin.2. The method according to claim 1 , wherein forming the first doped layer comprises:forming a first epitaxial layer in the first fin; andperforming a first doping process on the first epitaxial layer to dope a first type of doping ions into the first epitaxial layer.3. The method according to claim 2 , wherein:the first epitaxial layer is made of one of silicon, silicon germanium and silicon carbide.4. The method according to claim 2 , wherein forming the first epitaxial layer comprises:forming an opening passing through the first fin along the width direction of the first fin; andforming the first epitaxial layer in the ...

Подробнее
Номер записи: 71
03-01-2019 дата публикации

Mixed P/N MOS Array Layout and Methods of Forming the Same

Номер: US20190006358A1
Автор: HORNG Jaw-Juinn, Lien Bei-Shing
Принадлежит:

A semiconductor structure is disclosed that includes a p-channel metal-oxide semiconductor (PMOS) array having a first set of oxide diffusion layer (OD) structures, an n-channel metal-oxide semiconductor (NMOS) array having a second set of OD structures, and a dummy buffer zone surrounding the PMOS and NMOS arrays. The semiconductor structure has a uniform spacing between OD structures in the first and second sets of OD structures and between the PMOS and NMOS array, such that no dummy buffer zone is included between the PMOS array and the NMOS array. 1. A semiconductor structure comprising:a p-channel metal-oxide semiconductor (PMOS) array having a first set of oxide diffusion layer (OD) structures;an n-channel metal-oxide semiconductor (NMOS) array having a second set of OD structures; anda dummy buffer zone surrounding the PMOS and NMOS arrays;wherein the semiconductor structure has a uniform spacing between OD structures in the first and second sets of OD structures and between the PMOS and NMOS array, such that no dummy buffer zone is included between the PMOS array and the NMOS array.2. The semiconductor structure of claim 1 , wherein each OD structure in the first and second sets of OD structures has a uniform size.3. The semiconductor structure of claim 1 , wherein the PMOS and NMOS arrays include gate structures having a uniform length.4. The semiconductor structure of claim 1 , wherein the PMOS and NMOS arrays include gate structures claim 1 , and the gate structures are uniformly distributed throughout the PMOS and NMOS arrays.5. The semiconductor structure of claim 1 , wherein the dummy buffer zone includes physical layout topologies that are identical to physical layout topologies of at least one of the PMOS array and the NMOS array claim 1 , but are not electrically active.6. The semiconductor structure of claim 1 , wherein the PMOS and NMOS arrays include gate structures claim 1 , and wherein the dummy buffer zone is smaller along edges of the PMOS ...

Подробнее
Номер записи: 72
03-01-2019 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Номер: US20190006360A1
Автор: Chen Yan-Jou, Huang Cheng-Tung, Tung Yen-Wei, Wang Jen-Yu
Принадлежит:

A method for fabricating semiconductor device includes the steps of: forming a first fin-shaped structure on a substrate; forming a first single diffusion break (SDB) structure in the first fin-shaped structure; forming a first gate structure on the first SDB structure and a second gate structure on the first fin-shaped structure; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned mask on the first gate structure; and performing a replacement metal gate (RMG) process to transform the second gate structure into a metal gate. 1. A method for fabricating semiconductor device , comprising:forming a first fin-shaped structure on a substrate;forming a first single diffusion break (SDB) structure in the first fin-shaped structure;forming a first gate structure on the first SDB structure and a second gate structure on the first fin-shaped structure;forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure;forming a patterned mask on the first gate structure; andperforming a replacement metal gate (RMG) process to transform the second gate structure into a metal gate.2. The method of claim 1 , wherein the step of forming the first SDB structure comprises:removing part of the first fin-shaped structure to form a trench for dividing the first fin-shaped structure into a first portion and a second portion; andforming a dielectric layer in the trench to form the first SDB structure.3. The method of claim 2 , wherein the dielectric layer comprises silicon nitride.4. The method of claim 1 , wherein the first fin-shaped structure is disposed extending along a first direction and the first SDB structure is disposed extending along a second direction.5. The method of claim 4 , wherein the first direction is orthogonal to the second direction.6. The method of claim 1 , wherein the substrate comprises a first metal-oxide semiconductor (MOS) region and a second ...

Подробнее
Номер записи: 73
03-01-2019 дата публикации

ENHANCED CHANNEL STRAIN TO REDUCE CONTACT RESISTANCE IN NMOS FET DEVICES

Номер: US20190006363A1
Автор: CHANG Huicheng, CHEN Hou-Yu, Lin Yu-Chang, Lu Yong-Yan, NIEH Chun-Feng
Принадлежит:

A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer. 1. A method of fabricating a fin field-effect transistor (Fin FET) device , the method comprising:forming a first gate structure over a channel region in a first portion of a first fin structure on a semiconductor substrate;forming first source/drain regions on a second portion of the first fin structure on opposing sides of the gate structure;implanting a first dopant in a first region of the first source/drain regions, the first region having a first doping concentration of the first dopant, the first doping concentration being greater than a second doping concentration of a second dopant in a second region of the first source/drain regions; andapplying a thermal anneal operation to at least the first fin structure and the first source/drain regions, the channel region of the first fin structure having greater channel mobility than a channel region of a second fin structure on the substrate.2. The method of claim 1 , further comprising:forming a second gate structure over a channel region in a first portion of a second fin structure on the semiconductor substrate; andforming second source/drain regions on a second portion of the second fin structure on opposing sides of the second gate ...

Подробнее
Номер записи: 74
03-01-2019 дата публикации

EIGHT-TRANSISTOR STATIC RANDOM-ACCESS MEMORY, LAYOUT THEREOF, AND METHOD FOR MANUFACTURING THE SAME

Номер: US20190006372A1
Автор: CHANG George H., HSU Kang-Yu, HU Yao-Chung, LI Kun-Hsi, Lo Kuo-Hung, LU Shau-Wei
Принадлежит:

A Static Random Access Memory (SRAM) cell includes a write port including a first inverter including a first pull-up transistor and a first pull-down transistor, and a second inverter including a second pull-up transistor and a second pull-down transistor and cross-coupled with the first inverter; and a read port including a read pass-gate transistor and a read pull-down transistor serially connected to each. A first doped concentration of impurities doped in channel regions of the second pull-down transistor and the read pull-down transistor is greater than a second doped concentration of the impurities doped in a channel region of the first pull-down transistor, or the impurities are doped in the channel regions of the second pull-down transistor and the read pull-down transistor and are not doped in the channel region of the first pull-down transistor. 1. A Static Random Access Memory (SRAM) cell , comprising:a write port including a first inverter including a first pull-up transistor and a first pull-down transistor, and a second inverter including a second pull-up transistor and a second pull-down transistor and cross-coupled with the first inverter; anda read port including a read pass-gate transistor and a read pull-down transistor serially connected to each, gate electrodes of the read pass-gate transistor, the second pull-down transistor, and the second pull-up transistors being electrically connected to each other,wherein a first doping concentration of impurities doped in channel regions of the second pull-down transistor and the read pull-down transistor is greater than a second doping concentration of the impurities doped in a channel region of the first pull-down transistor, or the impurities are doped in the channel regions of the second pull-down transistor and the read pull-down transistor and are not doped in the channel region of the first pull-down transistor.2. The SRAM cell of claim 1 , wherein:the first and second pass-gate transistors, the ...

Подробнее
Номер записи: 75
03-01-2019 дата публикации

Integrated Circuit Structure and Method with Hybrid Orientation for FinFET

Номер: US20190006391A1
Автор: Chih-Hao Wang, Ching-Wei Tsai, Chung-Cheng Wu, Kuan-Lun Cheng, Min Cao, Tzer-Min Shen, Zhiqiang Wu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a <100> crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a <110> crystalline direction along the first direction.

Подробнее
Номер записи: 76
02-01-2020 дата публикации

VERTICALLY STACKED NFET AND PFET WITH DUAL WORK FUNCTION

Номер: US20200006479A1
Автор: Ando Takashi, Hashemi Pouya, Lee Choonghyun, Reznicek Alexander, Zhang Jingyun
Принадлежит:

A semiconductor structure is provided that includes a pFET device including a first functional gate structure containing at least a p-type work function metal and present on physically exposed surfaces, and between, each Si channel material nanosheet of a first set of vertically stacked and suspended Si channel material nanosheets. The structure further includes an nFET device stacked vertically above the pFET device. The nFET device includes a second functional gate structure containing at least an n-type work function metal present on physically exposed surfaces, and between, each Si channel material nanosheet of a second set of vertically stacked and suspended Si channel material nanosheets. 1. A method of forming a semiconductor structure , the method comprising:forming a vertical stack of a first nanosheet stack of alternating nanosheets of a sacrificial SiGe nanosheet and a Si channel material nanosheet, and a second nanosheet stack of alternating nanosheets of a sacrificial SiGe nanosheet and a Si channel material nanosheet, wherein the vertical stack is present above a semiconductor substrate and beneath a sacrificial gate structure and a dielectric spacer;recessing each sacrificial SiGe nanosheet of the first and second nanosheet stacks;removing the sacrificial gate structure and each recessed sacrificial SiGe nanosheet of the first and second nanosheet stacks to suspend each Si channel material nanosheet and to provide a gate cavity;forming a gate dielectric material in the gate cavity and on physically exposed surfaces of each suspended Si channel material nanosheet;forming a p-type work function metal on the gate dielectric material;removing the p-type work function metal from the gate cavity present below and above each suspended Si channel material nanosheet of the second nanosheet stack; andforming an n-type work function metal in the gate cavity present between and above each suspended Si channel material nanosheet of the second nanosheet stack.2. ...

Подробнее
Номер записи: 77
02-01-2020 дата публикации

SELF-ALIGNED GATE EDGE ARCHITECTURE WITH ALTERNATE CHANNEL MATERIAL

Номер: US20200006487A1
Автор: Baykan Mehmet Onur, BOWONDER Anupama, Ghani Tahir, GUHA BISWAJEET, Hsu William, LIAO Szuya S.
Принадлежит: Intel IP Corporation

Techniques are disclosed for forming integrated circuits configured with self-aligned isolation walls and alternate channel materials. The alternate channel materials in such integrated circuits provide improved carrier mobility through the channel. In an embodiment, an isolation wall is between sets of fins, at least some of the fins including an alternate channel material. In such cases, the isolation wall laterally separates the sets of fins, and the alternate channel material provides improved carrier mobility. For instance, in the case of an NMOS device the alternate channel material is a material optimized for electron flow, and in the case of a PMOS device the alternate channel material is a material optimized for hole flow. 1. An integrated circuit structure , comprising:a first set of one or more fins including a first fin, the first fin comprising a first semiconductor material;a first gate structure over the first set of fins and in contact with the first semiconductor material, the first gate structure having opposing first and second sides;a second set of one or more fins including a second fin, the second fin comprising a second semiconductor material;a second gate structure over the second set of fins and in contact with the second semiconductor material, the second gate structure having opposing first and second sides;a substrate below the fins, the substrate comprising a third semiconductor material compositionally different from the first semiconductor material; andan isolation wall laterally adjacent to the second side of the first gate structure and the first side of the second gate structure, the isolation wall having a first sidewall that is a first distance from a right sidewall of a rightmost fin of the first set of fins, the isolation wall having a second sidewall that is a second distance from a left sidewall of a leftmost fin of the second set of fins;wherein the difference between the first and second distances is 2 nm or less, and the ...

Подробнее
Номер записи: 78
03-01-2019 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20190006486A1
Автор: Cheng Kuan-Lun, Ching Kuo-Cheng, JU Shi-Ning, PAN Kuan-Ting, Wang Chih-hao
Принадлежит:

A semiconductor device has a substrate, a first dielectric fin, and an isolation structure. The substrate has a first semiconductor fin. The first dielectric fin is disposed over the substrate and in contact with a first sidewall of the first semiconductor fin, in which a width of the first semiconductor fin is substantially equal to a width of the first dielectric fin. The isolation structure is in contact with the first semiconductor fin and the first dielectric fin, in which a top surface of the isolation structure is in a position lower than a top surface of the first semiconductor fin and a top surface of the first dielectric fin. 1. A semiconductor device , comprising:a substrate comprising a first semiconductor fin;a first dielectric fin disposed over the substrate and in contact with a first sidewall of the first semiconductor fin, wherein a width of the first semiconductor fin is substantially equal to a width of the first dielectric fin; andan isolation structure in contact with the first semiconductor fin and the first dielectric fin, wherein a top surface of the isolation structure is in a position lower than a top surface of the first semiconductor fin and a top surface of the first dielectric fin.2. The semiconductor device of claim 1 , wherein the top surface of the first semiconductor fin and the top surface of the first dielectric fin are substantially coplanar.3. The semiconductor device of claim 1 , wherein:the first semiconductor fin has a second sidewall connected to the first sidewall; andthe first dielectric fin has a sidewall connected to the second sidewall of the first semiconductor fin, wherein the second sidewall of the first semiconductor fin and the sidewall of the first dielectric fin are substantially coplanar.4. The semiconductor device of claim 1 , wherein the first semiconductor fin comprises a base portion and a protruding portion protruding upward from the base portion claim 1 , and the first dielectric fin is over the base ...

Подробнее
Номер записи: 79
02-01-2020 дата публикации

METHOD AND DEVICE FOR FORMING CUT-METAL-GATE FEATURE

Номер: US20200006531A1
Автор: HSU Ting-Hung, LIN Zhi-Chang, Su Huan-Chieh, Wang Chih-hao, Wu Wei-Hao, Yu Jia-Ni
Принадлежит:

A mask layer is formed over a semiconductor device. The semiconductor device includes: a gate structure, a first layer disposed over the gate structure, and an interlayer dielectric (ILD) disposed on sidewalls of the first layer. The mask layer includes an opening that exposes a portion of the first layer and a portion of the ILD. A first etching process is performed to etch the opening partially into the first layer and partially into the ILD. A liner layer is formed in the opening after the first etching process has been performed. A second etching process is performed after the liner layer has been formed. The second etching process extends the opening downwardly through the first layer and through the gate structure. The opening is filled with a second layer after the second etching process has been performed. 1. A semiconductor device , comprising:a first layer that includes a dielectric material;a gate structure disposed over the first layer, wherein the gate structure is elongated and extends in a first direction; anda dielectric structure that vertically extends into the gate structure, wherein the dielectric structure has a first T-shape profile in a first cross-sectional view taken along the first direction and a second T-shape profile in a second cross-sectional view taken along a second direction different from the first direction.2. The semiconductor device of claim 1 , further including: liners disposed on sidewalls of the dielectric structure.3. The semiconductor device of claim 2 , wherein the liners are disposed on a portion of claim 2 , but not an entirety of claim 2 , the sidewalls of the dielectric structure.4. The semiconductor device of claim 2 , wherein the dielectric structure includes a top portion and a bottom portion disposed below the top portion claim 2 , the top portion having a greater lateral dimension than the bottom portion in both the first direction and in the second direction.5. The semiconductor device of claim 4 , the top ...

Подробнее
Номер записи: 80
02-01-2020 дата публикации

NANOSHEET SUBSTRATE ISOLATION SCHEME BY LATTICE MATCHED WIDE BANDGAP SEMICONDUCTOR

Номер: US20200006569A1
Автор: Lee Choonghyun, Miao Xin, Reznicek Alexander, Zhang Jingyun
Принадлежит:

A thin layer of lattice matched wide bandgap semiconductor material having semi-insulating properties is employed as an isolation layer between the substrate and a vertical stack of suspended semiconductor channel material nanosheets. The presence of such an isolation layer eliminates the parasitic leakage path between the source region and the drain region that typically occurs through the substrate, while not interfering with the CMOS device that is formed around the semiconductor channel material nanosheets. 1. A method of forming a semiconductor structure , the method comprising:forming a nanosheet stack of alternating nanosheets of a sacrificial semiconductor material nanosheet and a semiconductor channel material nanosheet on an isolation layer that is disposed on a substrate, wherein a sacrificial gate structure and a dielectric spacer material layer straddle over the nanosheet stack, and wherein the substrate is composed of a first semiconductor material having a first bandgap, and the isolation layer is composed of a second semiconductor material having a second bandgap that is larger than the first bandgap, and further wherein the second semiconductor material is lattice matched to the first semiconductor material and is doped such that the second semiconductor material has semi-insulating properties;recessing end portions of each of the sacrificial semiconductor material nanosheets to provide a gap between each of the semiconductor channel material nanosheets;forming an inner spacer in each gap;forming a source/drain (S/D) region by epitaxial growth of a semiconductor material on physically exposed sidewalls of each semiconductor channel material nanosheet;removing the sacrificial gate structure and each recessed sacrificial semiconductor material nanosheet; andforming a functional gate structure around exposed surfaces of each semiconductor channel material nanosheet.2. The method of claim 1 , wherein the first semiconductor material is composed of Si ...

Подробнее
Номер записи: 81
08-01-2015 дата публикации

Uniform height replacement metal gate

Номер: US20150008488A1
Автор: Cung D. Tran, Lindsey Hall, Viraj Y. Sardesai
Принадлежит: International Business Machines Corp, STMicroelectronics lnc USA

A method of manufacturing a semiconductor structure includes forming a raised source-drain region in a semiconductor substrate adjacent to a dummy gate and forming a chemical mechanical polish (CMP) stop layer over the gate structure and above a top surface of the semiconductor substrate. A first ILD layer is formed above the CMP stop layer. The first ILD layer is removed to a portion of the CMP stop layer located above the gate structure and a portion of the CMP stop layer located above the gate structure is also removed to expose the dummy gate. The dummy gate is replaced with a metal gate and the metal gate is polished until the CMP stop layer located above the raised source-drain region is reached.

Подробнее
Номер записи: 82
08-01-2015 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

Номер: US20150008530A1
Автор: Hong Hyeong-Sun, HUR Ki-jae, KIM Se-Young, Lim Jun-Hee, PARK Won-kyung
Принадлежит:

A semiconductor device is provided. A cell region is disposed in a substrate. The cell region includes a memory cell. A peripheral region is disposed in the substrate. The peripheral region is adjacent to the cell region. The peripheral region has a trench isolation, a first active region and a second active region. The trench isolation is interposed between the first active region and the second active region. A common gate pattern is disposed on the peripheral region. The common gate pattern extends in a first direction and partially overlaps the first active region, the second active region and the trench isolation. A buried conductive pattern is enclosed by the trench isolation. The buried conductive pattern extends in a second direction crossing the first direction. A top surface of the buried conductive pattern is lower than a bottom surface of the common gate pattern. 1. A semiconductor device , comprising:a substrate including an isolation region, a first region disposed at one side of the isolation region and a second region disposed at an opposite side of the isolation region, the first region and the second region arranged in a first direction;a trench disposed in the isolation region;an insulation layer pattern structure disposed in the trench;a buried conductive pattern enclosed by the insulation layer pattern structure, the buried conductive pattern having a top surface lower than a top surface of the substrate, the buried conductive pattern extended in a second direction crossing the first direction;a first gate insulation layer disposed on the substrate;a common gate pattern disposed on the first gate insulation layer, the common gate pattern extended in the first direction, and the common gate pattern overlapped with the first region, the isolation region and the second region;a first source region and a drain region disposed in upper portions of the first region, the first source region disposed at one side of the common gate pattern, the first ...

Подробнее
Номер записи: 83
20-01-2022 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20220020691A1
Автор: LIM SEUNG MAN, SEO Jae-woo, YOU HYEONGYU, YU JISU
Принадлежит:

Disclosed is a semiconductor device comprising a first logic cell and a second logic cell on a substrate. Each of the first and second logic cells includes a first active region and a second active region that are adjacent to each other in a first direction, a gate electrode that runs across the first and second active regions and extends lengthwise in the first direction, and a first metal layer on the gate electrode. The first metal layer includes a first power line and a second power line that extend lengthwise in a second direction perpendicular to the first direction, and are parallel to each other. The first and second logic cells are adjacent to each other in the second direction along the first and second power lines. The first and second active regions extend lengthwise in the second direction from the first logic cell to the second logic cell. 1. A semiconductor device , comprising: a first active region and a second active region that are adjacent to each other in a first direction;', 'a gate electrode that runs across the first and second active regions and extends lengthwise in the first direction; and', 'a first metal layer on the gate electrode,', 'wherein the first metal layer includes a first power line and a second power line that extend lengthwise in a second direction perpendicular to the first direction, and are parallel to each other,, 'a first logic cell and a second logic cell on a substrate, wherein each of the first and second logic cells includeswherein the first and second logic cells are adjacent to each other in the second direction along the first and second power lines,wherein the first and second active regions extend lengthwise in the second direction from the first logic cell to the second logic cell,wherein the first metal layer of the first logic cell further includes one or more first lower lines aligned on first line tracks between the first and second power lines,wherein the first metal layer of the second logic cell further ...

Подробнее
Номер записи: 84
20-01-2022 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Номер: US20220020745A1
Автор: Chen Yan-Jou, Huang Cheng-Tung, Tung Yen-Wei, Wang Jen-Yu
Принадлежит: UNITED MICROELECTRONICS CORP.

A semiconductor device includes a PMOS region and a NMOS region on a substrate, a first fin-shaped structure on the PMOS region, a first single diffusion break (SDB) structure in the first fin-shaped structure, a first gate structure on the first SDB structure, and a second gate structure on the first fin-shaped structure. Preferably, the first gate structure and the second gate structure are of different materials and the first gate structure disposed directly on top of the first SDB structure is a polysilicon gate while the second gate structure disposed on the first fin-shaped structure is a metal gate in the PMOS region. 1. A semiconductor device , comprising:a substrate comprising a PMOS region and a NMOS region;a first fin-shaped structure on the PMOS region;a first single diffusion break (SDB) structure in the first fin-shaped structure;a first gate structure on the first SDB structure;a second gate structure on the first fin-shaped structure, wherein the first gate structure and the second gate structure are of different materials, the first gate structure disposed directly on top of the first SDB structure is a polysilicon gate while the second gate structure disposed on the first fin-shaped structure is a metal gate in the PMOS region, and the second gate structure comprises a first U-shape high-k dielectric layer;a first source/drain region adjacent to two sides of the second gate structure, wherein the first source/drain region comprises silicon phosphide;a second fin-shaped structure on the NMOS region;a second SDB structure in the second fin-shaped structure;a third gate structure on the second SDB structure and a fourth gate structure on the second fin-shaped structure, wherein the third gate structure and the fourth gate structure are of same material, the third gate structure disposed directly on top of the second SDB structure is a metal gate and the fourth gate structure disposed on the second fin-shaped structure is also a metal gate in the NMOS ...

Подробнее
Номер записи: 85
08-01-2015 дата публикации

DUAL EPI CMOS INTEGRATION FOR PLANAR SUBSTRATES

Номер: US20150011060A1
Автор: Loubet Nicolas, Pranatharthiharan Balasubramanian
Принадлежит:

Silicon germanium regions are formed adjacent gates electrodes over both n-type and p-type regions in an integrated circuit. A hard mask patterned by lithography then protects structures over the p-type region while the silicon germanium is selectively removed from over the n-type region, even under remnants of the hard mask on sidewall spacers on the gate electrode. Silicon germanium carbon is epitaxially grown adjacent the gate electrode in place of the removed silicon germanium, and source/drain extension implants are performed prior to removal of the remaining hard mask over the p-type region structures. 1. A method , comprising:forming silicon germanium (SiGe) regions adjacent gate electrodes over both n-type and p-type regions;forming and patterning a hard mask over structures in the p-type region;selectively removing, relative to a material of the hard mask, the silicon germanium regions adjacent the gate electrode over the n-type region; andepitaxially growing silicon germanium carbon (Si(Ge)(C)) regions adjacent the gate electrode over the n-type region in place of the removed silicon germanium regions.2. The method according to claim 1 , wherein the hard mask comprises silicon nitride (SiN) claim 1 , and wherein remnants of the hard mask remain on spacers adjacent the gate electrode over the n-type region and over the silicon germanium regions when the hard mask is patterned.3. The method according to claim 2 , further comprising removing portions of the silicon germanium regions adjacent the gate electrode over the n-type region and under the hard mask remnants.4. The method according to claim 3 , further comprising epitaxially growing silicon germanium carbon adjacent the gate electrode over the n-type region and under the hard mask remnants.5. The method according to claim 4 , further comprising:after epitaxially growing the silicon germanium carbon regions adjacent the gate electrode over the n-type region and under the hard mask remnants, removing the ...

Подробнее
Номер записи: 86
12-01-2017 дата публикации

Interconnect structures and fabrication method thereof

Номер: US20170011966A1
Автор: Yihua Shen, Yunchu Yu
Принадлежит: Semiconductor Manufacturing International Beijing Corp, Semiconductor Manufacturing International Shanghai Corp

An interconnect structure is provided. The interconnect structure includes a substrate; and at least a first interconnect component having a first contact region and a second interconnect component having a second contact region. The interconnect structure also includes an interlayer dielectric layer formed on the semiconductor substrate at a same layer as the first interconnect component and the second interconnect component. Further, the interconnect structure includes an interconnect line layer electrically connecting the first contact region and the second contact region formed inside the interlayer dielectric layer.

Подробнее
Номер записи: 87
12-01-2017 дата публикации

Methods of manufacturing a semiconductor device

Номер: US20170011967A1
Автор: Eun-Seong LEE, Jae-hyun Yeo, Jae-Suk KWON, Kwang-Woo LEE
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of manufacturing a semiconductor device includes forming a first gate structure on a substrate, the first gate structure including a gate insulation layer, a gate electrode, and a hard mask sequentially stacked on the substrate, forming a preliminary spacer layer on sidewalls of the first gate structure and the substrate, the preliminary spacer layer including silicon nitride, implanting molecular ions into the preliminary spacer layer to form a spacer layer having a dielectric constant lower than a dielectric constant of the preliminary spacer layer, anisotropically etching the spacer layer to form spacers on the sidewalls of the first gate structure, and forming impurity regions at upper portions of the substrate adjacent to the first gate structure.

Подробнее
Номер записи: 88
12-01-2017 дата публикации

METHOD AND STRUCTURE OF THREE DIMENSIONAL CMOS TRANSISTORS WITH HYBRID CRYSTAL ORIENTATIONS

Номер: US20170011972A9
Автор: Yang Xiao (Charles)
Принадлежит: MCube, Inc.

A method for fabricating a three-dimensional integrated circuit device includes providing a first substrate having a first crystal orientation, forming at least one or more PMOS devices overlying the first substrate, and forming a first dielectric layer overlying the one or more PMOS devices. The method also includes providing a second substrate having a second crystal orientation, forming at least one or more NMOS devices overlying the second substrate, and forming a second dielectric layer overlying the one or more NMOS devices. The method further includes coupling the first dielectric layer to the second dielectric layer to form a hybrid structure including the first substrate overlying the second substrate. 1. A method for fabricating a three-dimensional integrated circuit device , the method comprising:providing a first substrate having a first crystal orientation;forming at least one or more PMOS devices overlying the first substrate;forming a first dielectric layer overlying the one or more PMOS devices;providing a second substrate having a second crystal orientation;forming at least one or more NMOS devices overlying the second substrate;forming a second dielectric layer overlying the one or more NMOS devices; andcoupling the first dielectric layer to the second dielectric layer to form a hybrid structure including the first substrate overlying the second substrate.2. The method of wherein the first crystal orientation comprises a (110) crystal orientation or a (111) crystal orientation.3. The method of wherein the second crystal orientation comprises a (100) crystal orientation.4. The method of wherein the coupling of the first and second dielectric layer comprises a covalent claim 1 , eutectic claim 1 , glass frit claim 1 , SOG claim 1 , thermal compression claim 1 , or fusion bonding process.5. The method of further comprising forming one or more trench isolation (STI) oxides formed to isolate adjacent transistors.6. The method of further comprising ...

Подробнее
Номер записи: 89
12-01-2017 дата публикации

SUBSTRATE CONTACT LAND FOR AN MOS TRANSISTOR IN AN SOI SUBSTRATE, IN PARTICULAR AN FDSOI SUBSTRATE

Номер: US20170012043A1
Автор: Athanasiou Sotirios, Galy Philippe
Принадлежит: STMICROELECTRONICS SA

A substrate contact land for a first MOS transistor is produced in and on an active zone of a substrate of silicon on insulator type using a second MOS transistor without any PN junction that is also provided in the active zone. A contact land on at least one of a source or drain region of the second MOS transistor forms the substrate contact land. 1. A method for producing at least one substrate contact land , comprising:producing a first metal oxide semiconductor (MOS) transistor in and on an active zone of a substrate of silicon on insulator type; andproducing in said active zone at least one second MOS transistor without any PN junction having at least first one contact land on at least one of a source region or drain region, said at least one first contact land forming said at least one substrate contact land.2. The method according to claim 1 , further comprising producing in the active zone at least one third MOS transistor without any PN junction claim 1 , the first MOS transistor being bracketed by the second and the third MOS transistors claim 1 , the third MOS transistor having at least one second contact land on at least one of a source or drain region claim 1 , said second contact land forming a second substrate contact land for the first MOS transistor.3. An integrated electronic device claim 1 , comprising:an intrinsic semiconductor film above a buried insulating layer that is situated above a bearer substrate;an insulating region delimiting an active zone in the intrinsic semiconductor film;a first metal oxide semiconductor (MOS) transistor situated in and on a first part of the active zone; andat least one first connection element situated in and on a second part of the active zone, the first connection element being structurally similar to a second MOS transistor without any PN junctions between source/drain regions and a channel region, at least one source or drain contact land of the second MOS transistor forming at least one substrate contact ...

Подробнее
Номер записи: 90
12-01-2017 дата публикации

Low Power Semiconductor Transistor Structure and Method of Fabrication Thereof

Номер: US20170012044A1
Автор: Ranade Pushkar, Shifren Lucian, Sonkusale Sachin R., Thompson Scott E., Zhang Weimin
Принадлежит:

A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVcompared to conventional bulk CMOS and can allow the threshold voltage Vof FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an anaolog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device. 119-. (canceled)20. An integrated circuit having transistor devices of a plurality of device types formed on a substrate , comprising:a first screening layer for a first device type, the first screening layer being positioned below a first gate insulator of the first device type, the first screening layer having a first dopant concentration;a second screening layer for a second device type, the second screening layer being positioned below a second gate insulator of the second device type, the second screening layer having a second dopant concentration;a threshold voltage layer for a third device type, the threshold voltage layer being positioned below a third gate insulator of the third device type, the threshold voltage layer having a third dopant concentration;a first substantially undoped layer for the first device type being positioned above and adjacent to the first screening layer;a second substantially undoped layer for the second device type being positioned above and adjacent to the second screening layer,a shallow trench isolation isolating the first device type, the second device type and the third ...

Подробнее
Номер записи: 91
12-01-2017 дата публикации

SYSTEMS AND METHODS FOR INTEGRATING DIFFERENT CHANNEL MATERIALS INTO A CMOS CIRCUIT BY USING A SEMICONDUCTOR STRUCTURE HAVING MULTIPLE TRANSISTOR LAYERS

Номер: US20170012045A1
Автор: Lin Yi-Tang, Wann Clement Hsingjen
Принадлежит:

A method includes providing a first substrate having first and second regions, fabricating over the first region of the first substrate a channel of a first transistor, providing a second substrate over the second region of the first substrate, fabricating over the second substrate a channel of a second transistor, and forming gates respectively and simultaneously over the channels of the first and second transistors. 1. A method comprising:providing a first substrate having first and second regions;fabricating over the first region of the first substrate a channel of a first transistor;providing a second substrate over the second region of the first substrate;fabricating over the second substrate a channel of a second transistor; andforming gates respectively and simultaneously over the channels of the first and second transistors.2. The method of claim 1 , wherein fabricating the channels of the first and second transistors are such that the channels of the first and second transistors have different channel materials.3. The method of claim 1 , wherein fabricating the channels of the first and second transistors are such that the channels of the first and second transistors are disposed one higher than the other.4. The method of claim 1 , wherein providing the first substrate is such that a first channel material is over the first and second regions of the first substrate claim 1 , the method further comprising transforming the first channel material at the second region of the first substrate to a dielectric.5. The method of claim 4 , wherein transforming the first channel material at the second region of the first substrate includesremoving the first channel material from the second region of the first substrate, anddepositing a dielectric material over the second region of the first substrate.6. The method of claim 5 , further comprising polishing the dielectric material to a height of the first channel material at the first region of the substrate.7. The ...

Подробнее
Номер записи: 92
12-01-2017 дата публикации

TECHNIQUES FOR INTEGRATION OF GE-RICH P-MOS SOURCE/DRAIN CONTACTS

Номер: US20170012124A1
Автор: Ghani Tahir, Glass Glenn A., Mistkawi Nabil G., Murthy Anand S., PANG YING
Принадлежит: Intel Corporation

Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm. 1. A transistor device , comprising:a substrate having a channel region;a gate electrode above the channel region; andsource/drain regions formed on and/or in the substrate and adjacent to the channel region, each of the source/drain regions comprising a p-type germanium (Ge)-rich layer deposited directly on a silicon (Si) surface, wherein the p-type Ge-rich layer comprises at least 50% Ge.2. The device of claim 1 , wherein the Si surface in the source/drain regions is a surface of the substrate.3. The device of claim 1 , wherein the Si surface in the source/drain regions is a surface of a Si cladding layer deposited on a p-type silicon germanium (SiGe) layer.4. The device of claim 3 , wherein the p-type SiGe layer comprises 30-70% Ge.5. The device of claim 1 , wherein the p-type Ge-rich layer comprises silicon germanium (SiGe).6. The device of claim 1 , wherein the p-type Ge-rich layer comprises germanium tin (GeSn) with up to 15% Sn.7. The device of claim 6 , wherein the p-type Ge-rich layer further comprises up to 5% Si.8. The device of ...

Подробнее
Номер записи: 93
14-01-2016 дата публикации

METHOD OF CO-INTEGRATION OF STRAINED SILICON AND STRAINED GERMANIUM IN SEMICONDUCTOR DEVICES INCLUDING FIN STRUCTURES

Номер: US20160013189A1
Автор: Cheng Kangguo, Hashemi Pouya, Khakifirooz Ali, Reznicek Alexander
Принадлежит:

A method of forming a semiconductor device that includes forming an at least partially relaxed semiconductor material, and forming a plurality of fin trenches in the partially relaxed semiconductor material. At least a portion of the plurality of fin trenches is filled with a first strained semiconductor material that is formed using epitaxial deposition. A remaining portion of the at least partially relaxed semiconductor material is removed to provide a plurality of fin structure of the first strained semiconductor material. 1. A method of forming a semiconductor device comprising:forming a plurality of fin trenches in a partially relaxed semiconductor material;filling at least a portion of the plurality of fin trenches with a strained semiconductor material; andremoving a remaining portion of the at least partially relaxed semiconductor material that provides sidewalls of the fin trenches to provide a plurality of fin structures of the strained semiconductor material.2. The method of claim 1 , wherein the at least partially relaxed semiconductor material is silicon germanium (SiGe) that is epitaxially formed on a substrate of silicon (Si).3. The method of claim 2 , wherein the at least partially relaxed semiconductor material is a layered structure of silicon germanium claim 2 , wherein a germanium concentration of layered structure increases with substantially each layer of the layered structure from an interface with the substrate of silicon (Si).4. The method of claim 2 , wherein the at least partially relaxed semiconductor material is formed using a condensation method.5. The method of claim 2 , wherein the at least partially relaxed semiconductor material is 90% relaxed in either a compressive strain or tensile strain direction.6. The method of claim 1 , wherein said forming the plurality of the fin trenches in the partially relaxed semiconductor material comprises a reverse sidewall image transfer (SIT) etch process.7. The method of claim 1 , wherein a pitch ...

Подробнее
Номер записи: 94
14-01-2016 дата публикации

Dual sti integrated circuit including fdsoi transistors and method for manufacturing the same

Номер: US20160013205A1
Автор: Ali Khakifirooz, Bruce Doris, Kangguo Cheng, Laurent Grenouillet, Maud Vinet, Qing Liu, Yannick Le Tiec
Принадлежит: Commissariat a lEnergie Atomique et aux Energies Alternatives CEA, International Business Machines Corp, STMicroelectronics lnc USA

An integrated circuit, including: a first cell, including: FDSOI transistors; a UTBOX layer lying beneath the transistors; a first well lying beneath the insulator layer and beneath the transistors, the first well having a first type of doping; a first ground plane having a second type of doping, located beneath one of the transistors and between the insulator layer and the first well; a first STI separating the transistors and crossing the insulator layer; a first conductive element forming an electrical connection between the first well and the first ground plane, located under the first STI; a second cell including a second well; a second STI separating the cells, crossing the insulator layer and reaching the bottom of the first and second wells.

Подробнее
Номер записи: 95
11-01-2018 дата публикации

FINFET DEVICE

Номер: US20180012809A1
Автор: Chen Kuang-Hsin, Ting Kuo-Chiang, WU Chi-Hsi, YIN Joanna Chaw Yane
Принадлежит:

The present disclosure provides many different embodiments of a FinFET device that provide one or more improvements over the prior art. In one embodiment, a FinFET includes a semiconductor substrate and a plurality of fins having a first height and a plurality of fin having a second height on the semiconductor substrate. The second height may be less than the first height. 1. A device comprising:a first fin structure disposed over a substrate and having a first height over a surface of the substrate;a dummy semiconductor structure adjacent the first fin structure and disposed over the substrate, wherein the dummy semiconductor structure has a sidewall extending from the surface of the substrate to a second height that is less than the first height;an isolation structure extending from the first fin structure to the dummy semiconductor structure;a source/drain structure disposed over the first fin structure, wherein the source/drain has a bottommost point disposed a first distance from the surface of the substrate; andan interlayer dielectric (ILD) layer disposed over a top surface of the dummy semiconductor structure and the source/drain structure, wherein the interlayer dielectric (ILD) layer at least one region disposed a second distance from the surface of the substrate, wherein the second distance is less than the first distance;and wherein dielectric material from at least one of the ILD layer or the isolation structure at least partially covers the top surface of the dummy semiconductor structure, the top surface of the dummy semiconductor structure facing away from the substrate.2. The device of claim 1 , wherein the ILD layer interfaces a top surface of the dummy semiconductor structure.3. The device of claim 2 , wherein the ILD layer includes a combination of dielectric materials.4. The device of claim 1 , wherein the source/drain structure has a terminus edge over the isolation structure.5. The device of claim 1 , wherein the isolation structure includes a ...

Подробнее
Номер записи: 96
11-01-2018 дата публикации

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

Номер: US20180012811A1
Автор: Li Yong
Принадлежит:

Semiconductor devices and fabrication methods thereof are provided. An exemplary fabrication method includes forming an interlayer dielectric layer on a base substrate; forming a plurality of first openings and second openings in the interlayer dielectric layer, one first opening connecting to a second opening, the one first opening being between the second opening and the base substrate; forming a high-K gate dielectric layer on side and bottom surfaces of the first openings and on side surfaces of the second openings; forming a cap layer, containing oxygen ions, on the high-K gate dielectric layer; forming an amorphous silicon layer on the cap layer at least on the bottoms of the first openings; performing a thermal annealing process on the amorphous silicon layer, the cap layer and the high-K dielectric; removing the amorphous silicon layer; and forming a metal layer, in the first openings and the second openings. 1. A method for fabricating a semiconductor device , comprising:forming an interlayer dielectric layer on a base substrate;forming a plurality of first openings and second openings in the interlayer dielectric layer, one first opening connecting to a second opening, the one first opening being between the second opening and the base substrate to expose the base substrate;forming a high-K gate dielectric layer on side and bottom surfaces of the first openings and on side surfaces of the second openings;forming a cap layer, containing oxygen ions, on the high-K gate dielectric layer;forming an amorphous silicon layer on the cap layer at least on the bottoms of the first openings;performing a thermal annealing process on the amorphous silicon layer, the cap layer and the high-K dielectric layer to cause the oxygen ions to diffuse into the high-K dielectric layer;removing the amorphous silicon layer; andforming a metal layer to fill the first openings and the second openings.2. The method according to claim 1 , wherein:the high-K dielectric layer has ...

Подробнее
Номер записи: 97
11-01-2018 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20180012890A1
Автор: HAO Long, Jin Yan, Li Wei, WANG Dejin
Принадлежит:

A manufacturing method of a semiconductor device, comprising the following steps: providing a semiconductor substrate comprising a low-voltage device region and a high-voltage device region; forming first gate oxide layers in a non-gate region of the high-voltage device region and the low-voltage device region and a second gate oxide layer in a gate region of the high-voltage device region; the thickness of the second gate oxide layer is greater than the thickness of the first gate oxide layer; forming a first polysilicon gate and a first sidewall structure on the surface of the first gate oxide layer of the low-voltage device region and a second polysilicon gate and a second sidewall structure on the surface of the second gate oxide layer; the width of the second gate oxide layer is greater than the width of the second polysilicon gate; performing source drain ions injection to form a source drain extraction region; after depositing a metal silicide area block (SAB), performing a photolithographic etching on the metal SAB and forming metal silicide. The above manufacturing method of a semiconductor device simplifies process steps and reduces process cost. The present invention also relates to a semiconductor device. 1. A method of manufacturing a semiconductor device , comprising the steps of:providing a semiconductor substrate comprising a low-voltage device region and a high-voltage device region;forming a first gate oxide layer in a non-gate region of the high-voltage device region and the low-voltage device region, and forming a second gate oxide layer in a gate region of the high-voltage device region; wherein a thickness of the second gate oxide layer is greater than a thickness of the first gate oxide layer;forming a first polysilicon gate and a first sidewall structure on a surface of the first gate oxide layer of the low-voltage device region, and forming a second polysilicon gate and a second sidewall structure on a surface of the second gate oxide layer; ...

Подробнее
Номер записи: 98
11-01-2018 дата публикации

Semiconductor devices

Номер: US20180012967A1
Автор: Dae Lim Kang
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device may include an active fin, an element isolation film on a lower portion of the active fin and a gate structure crossing over the active fin. The gate structure may include first and second sides. The device may also include a source region and a drift region adjacent the first and second sides of the gate structure, respectively. The drift region may have a first impurity concentration. The device may further include a drain region that is in the drift region and may have a second impurity concentration higher than the first impurity concentration, a first trench that is in the drift region and may have a depth less than a height of the active fin, and an upper embedded insulating layer in the first trench. The gate structure may overlap a portion of the drift region and a portion of the first trench.

Подробнее
Номер записи: 99
11-01-2018 дата публикации

DUAL STRESS DEVICE AND METHOD

Номер: US20180012988A1
Автор: ANDERSON Brent A., Bryant Andres, Nowak Edward J.
Принадлежит:

A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure. 1. A semiconductor structure , comprising:semiconductor material having a bend and a trench feature formed at the bend; anda gate structure at least partially disposed in the trench feature,wherein the semiconductor material comprises a fin having a first side and a second side opposite the first side.2. The semiconductor structure of claim 1 , further comprising a second gate structure claim 1 , wherein a first inversion channel region of the gate structure and a second inversion channel region of the second gate structure are at least partially disposed in an area of the fin that has tensile stress induced by the bend.3. The semiconductor structure of claim 2 , wherein the gate structure is included in a first NFET and the second gate structure is included in a second NFET.4. The semiconductor structure of claim 1 , further comprising a second gate structure claim 1 , wherein a first inversion channel region of the gate structure and a second inversion channel region of the second gate structure are at least partially disposed in an area of the fin that has compressive stress induced by the bend.5. The semiconductor structure of claim 4 , wherein the gate structure is included in a first NFET and the second gate structure is included in a second NFET.6. A semiconductor structure claim 4 , comprising:a semiconductor fin having a first side, a second side opposite the first side, and a bend; anda gate structure arranged at the first side of the ...

Подробнее
Номер записи: 100