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Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 251. Отображено 104.
18-04-2017 дата публикации

Field-effect transistor with dual vertical gates

Номер: US0009627531B1
Автор: Hung-Li Chiang, Chih Chieh Yeh, Cheng-Yi Peng, Tzu-Chiang Chen, Yee-Chia Yeo, CHIANG HUNG-LI, YEH CHIH CHIEH, PENG CHENG-YI, CHEN TZU-CHIANG, YEO YEE-CHIA, Chiang Hung-Li, Yeh Chih Chieh, Peng Cheng-Yi, Chen Tzu-Chiang, Yeo Yee-Chia
Принадлежит: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TAIWAN SEMICONDUCTOR MFG CO LTD, Taiwan Semiconductor Manufacturing Company, Ltd.

A semiconductor device includes an n-type vertical field-effect transistor (FET) that includes: a first source/drain feature disposed in a substrate; a first vertical bar structure that includes a first sidewall and a second sidewall disposed over the substrate; a gate disposed along the first sidewall of the first vertical bar structure; a second vertical bar structure electrically coupled to the first vertical bar structure; and a second source/drain feature disposed over the first vertical bar structure; and a p-type FET that includes; a third source/drain feature disposed in the substrate; a third vertical bar structure that includes a third sidewall and a fourth sidewall disposed over the substrate; the gate disposed along the third sidewall of the third vertical bar structure; a fourth vertical bar structure electrically coupled to the third vertical bar structure; and a fourth source/drain feature disposed over the third vertical bar structure.

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Номер записи: 1
06-02-2018 дата публикации

Methods of forming semiconductor devices and structures thereof

Номер: US0009887100B2
Автор: Chia-Cheng Ho, Tzu-Chiang Chen, Tsung-Lin Lee, Wei-Jen Lai, Chih Chieh Yeh, HO CHIA CHENG, CHEN TZU CHIANG, LEE TSUNG LIN, LAI WEI JEN, YEH CHIH CHIEH, Ho Chia-Cheng, Chen Tzu-Chiang, Lee Tsung-Lin, Lai Wei-Jen, Yeh Chih Chieh
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

Methods of forming semiconductor devices and structures thereof are disclosed. In some embodiments, a semiconductor device includes a substrate that includes fins. Gates are disposed over the fins, the gates being substantially perpendicular to the fins. A source/drain region is disposed on each of fins between two of the gates. A contact is coupled to the source/drain region between the two of the gates. The source/drain region comprises a first width, and the contact comprises a second width. The second width is substantially the same as the first width.

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Номер записи: 2
03-08-2017 дата публикации

System and Method for a Field-Effect Transistor with Dual Vertical Gates

Номер: US20170221772A1
Автор: Hung-Li Chiang, Chih Chieh Yeh, Cheng-Yi Peng, Tzu-Chiang Chen, Yee-Chia Yeo, CHIANG HUNG-LI, YEH CHIH CHIEH, PENG CHENG-YI, CHEN TZU-CHIANG, YEO YEE-CHIA, Chiang Hung-Li, Yeh Chih Chieh, Peng Cheng-Yi, Chen Tzu-Chiang, Yeo Yee-Chia
Принадлежит:

A semiconductor device includes an n-type vertical field-effect transistor (FET) that includes: a first source/drain feature disposed in a substrate; a first vertical bar structure that includes a first sidewall and a second sidewall disposed over the substrate; a gate disposed along the first sidewall of the first vertical bar structure; a second vertical bar structure electrically coupled to the first vertical bar structure; and a second source/drain feature disposed over the first vertical bar structure; and a p-type FET that includes; a third source/drain feature disposed in the substrate; a third vertical bar structure that includes a third sidewall and a fourth sidewall disposed over the substrate; the gate disposed along the third sidewall of the third vertical bar structure; a fourth vertical bar structure electrically coupled to the third vertical bar structure; and a fourth source/drain feature disposed over the third vertical bar structure. 1. A method comprising:forming a first material layer that is doped with a first type of dopant over a substrate and forming a second material layer that is doped with a second type of dopant over the substrate, the second type being opposite the first type;patterning the first material layer to form a first vertical bar structure of the first material layer and patterning the second material layer to form a second vertical bar structure of the second material layer;forming a first dielectric layer along a first sidewall of the first vertical bar structure and along a second sidewall of the second vertical bar structure;forming a gate electrode extending from the first dielectric layer formed along the first sidewall of the first vertical bar structure to the first dielectric layer formed along the second sidewall of the second vertical bar structure; andforming a first source/drain feature on a first top surface of the first vertical bar structure and forming a second source/drain feature on a second top surface of ...

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Номер записи: 3
06-03-2018 дата публикации

FinFETs and the methods for forming the same

Номер: US0009911850B2
Автор: Chia-Cheng Ho, Tzu-Chiang Chen, Yi-Tang Lin, Chih-Sheng Chang, HO CHIA CHENG, CHEN TZU CHIANG, LIN YI TANG, CHANG CHIH SHENG, Ho Chia-Cheng, Chen Tzu-Chiang, Lin Yi-Tang, Chang Chih-Sheng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD

A method includes providing a plurality of semiconductor fins parallel to each other, and includes two edge fins and a center fin between the two edge fins. A middle portion of each of the two edge fins is etched, and the center fin is not etched. A gate dielectric is formed on a top surface and sidewalls of the center fin. A gate electrode is formed over the gate dielectric. The end portions of the two edge fins and end portions of the center fin are recessed. An epitaxy is performed to form an epitaxy region, wherein an epitaxy material grown from spaces left by the end portions of the two edge fins are merged with an epitaxy material grown from a space left by the end portions of the center fin to form the epitaxy region. A source/drain region is formed in the epitaxy region.

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Номер записи: 4
25-08-2016 дата публикации

FinFETs and the Methods for Forming the Same

Номер: US20160247920A1
Автор: Chia-Cheng Ho, Tzu-Chiang Chen, Yi-Tang Lin, Chih-Sheng Chang, HO CHIA-CHENG, CHEN TZU-CHIANG, LIN YI-TANG, CHANG CHIH-SHENG, Ho Chia-Cheng, Chen Tzu-Chiang, Lin Yi-Tang, Chang Chih-Sheng
Принадлежит:

A method includes providing a plurality of semiconductor fins parallel to each other, and includes two edge fins and a center fin between the two edge fins. A middle portion of each of the two edge fins is etched, and the center fin is not etched. A gate dielectric is formed on a top surface and sidewalls of the center fin. A gate electrode is formed over the gate dielectric. The end portions of the two edge fins and end portions of the center fin are recessed. An epitaxy is performed to form an epitaxy region, wherein an epitaxy material grown from spaces left by the end portions of the two edge fins are merged with an epitaxy material grown from a space left by the end portions of the center fin to form the epitaxy region. A source/drain region is formed in the epitaxy region. 1. A device , comprising:a plurality of semiconductor fins disposed over a semiconductor substrate, wherein each of the plurality of semiconductor fins are parallel to other ones of the plurality of semiconductor fins, at least one center fin of the plurality of semiconductor fins disposed between at least two edge fins of the plurality of fins, and wherein each of the at least two edge fins comprises two end portions disconnected from each other;a gate stack on a top surface and sidewalls of the at least one center fin; andsource/drain regions each extending over an end portion of the at least one center fin and each extending to over end portions of the least two edge fins.2. The device of claim 1 , wherein each of the source/drain regions are epitaxy regions.3. The device of claim 1 , wherein the gate stack extends between the end portions of at least one of the at least two edge fins.4. The device of claim 1 , further comprising:isolation regions at a surface of the semiconductor substrate, the plurality of semiconductor fins disposed between the isolation regions.5. The device of claim 4 , wherein the source/drain regions each comprise facets that are neither parallel nor perpendicular ...

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Номер записи: 5
21-03-2017 дата публикации

Method of manufacturing a fin-like field effect transistor (FinFET) device

Номер: US0009601598B2
Автор: Tsu-Hsiu Perng, Chih Chieh Yeh, Tzu-Chiang Chen, Chia-Cheng Ho, Chih-Sheng Chang, PERNG TSU-HSIU, YEH CHIH CHIEH, CHEN TZU-CHIANG, HO CHIA-CHENG, CHANG CHIH-SHENG, Perng Tsu-Hsiu, Yeh Chih Chieh, Chen Tzu-Chiang, Ho Chia-Cheng, Chang Chih-Sheng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd., TAIWAN SEMICONDUCTOR MFG CO LTD, TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary FinFET device includes a semiconductor substrate; a fin structure disposed over the semiconductor substrate; and a gate structure disposed over a portion of the fin structure. The gate structure traverses the fin structure and separates a source region and a drain region of the fin structure, the source and drain region defining a channel therebetween. The source and drain region of the fin structure include a strained source and drain feature. The strained source feature and the strained drain feature each include: a first portion having a first width and a first depth; and a second portion disposed below the first portion, the second portion having a second width and a second depth. The first width is greater than the second width, and the first depth is less than the second depth.

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Номер записи: 6
11-07-2013 дата публикации

FinFETs and the Methods for Forming the Same

Номер: US20130175584A1
Автор: Chang Chih-Shen, Chen Tzu-Chiang, Ho Chia-Cheng, Lin Yi-Tang
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A method includes providing a plurality of semiconductor fins parallel to each other, and includes two edge fins and a center fin between the two edge fins. A middle portion of each of the two edge fins is etched, and the center fin is not etched. A gate dielectric is formed on a top surface and sidewalls of the center fin. A gate electrode is formed over the gate dielectric. The end portions of the two edge fins and end portions of the center fin are recessed. An epitaxy is performed to form an epitaxy region, wherein an epitaxy material grown from spaces left by the end portions of the two edge fins are merged with an epitaxy material grown from a space left by the end portions of the center fin to form the epitaxy region. A source/drain region is formed in the epitaxy region. 1. A method comprising: a semiconductor substrate;', 'isolation regions at a surface of the semiconductor substrate;', 'a plurality of semiconductor strips between the isolation regions; and', 'a plurality of semiconductor fins over and aligned to respective ones of the plurality of semiconductor strips, wherein the plurality of semiconductor fins is parallel to each other, and comprises two edge fins and a center fin between the two edge fins;, 'providing a structure comprisingetching a middle portion of each of the two edge fins;forming a gate dielectric on sidewalls of a middle portion of the center fin;forming a gate electrode over the gate dielectric;performing an epitaxy to form an epitaxy region, wherein the epitaxy region extends to over two of the plurality of semiconductor strips underlying the two edge fins, and extends to over one of the plurality of semiconductor strips under the center fin; andforming a source/drain region in the epitaxy region.2. The method of claim 1 , wherein during the step of etching the middle portion of each of the two edge fins claim 1 , opposite end portions of the two edge fins are not etched.3. The method of claim 1 , wherein during the step of ...

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Номер записи: 7
11-07-2013 дата публикации

FINFETS AND THE METHODS FOR FORMING THE SAME

Номер: US20130175638A1
Автор: CHANG Chih-Sheng, Chen Tzu-Chiang, Ho Chia-Cheng, Lin Yi-Tang
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A method includes forming a gate stack including a gate electrode on a first semiconductor fin. The gate electrode includes a portion over and aligned to a middle portion of the first semiconductor fin. A second semiconductor fin is on a side of the gate electrode, and does not extend to under the gate electrode. The first and the second semiconductor fins are spaced apart from, and parallel to, each other. An end portion of the first semiconductor fin and the second semiconductor fin are etched. An epitaxy is performed to form an epitaxy region, which includes a first portion extending into a first space left by the etched first end portion of the first semiconductor fin, and a second portion extending into a second space left by the etched second semiconductor fin. A first source/drain region is formed in the epitaxy region. 1. A method comprising:forming a gate dielectric on sidewalls of a middle portion of a first semiconductor fin;forming a gate electrode over the gate dielectric, wherein the gate electrode comprises a portion over and aligned to the middle portion of the first semiconductor fin, wherein a second semiconductor fin is on a first side of the gate electrode, and does not extend to under the gate electrode, and wherein the first and the second semiconductor fins are spaced apart from each other and parallel to each other;etching a first end portion of the first semiconductor fin and the second semiconductor fin; a first portion extending into a first space left by the etched first end portion of the first semiconductor fin; and', 'a second portion extending into a second space left by the etched second semiconductor fin, wherein the first and the second portions merge with each other to form the first epitaxy region; and, 'performing an epitaxy to form a first epitaxy region, wherein the epitaxy region comprisesforming a first source/drain region in the first epitaxy region.2. The method of further comprising:etching a third semiconductor fin and a ...

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Номер записи: 8
19-12-2013 дата публикации

FinFETs and the Methods for Forming the Same

Номер: US20130334615A1
Автор: CHANG Chih-Sheng, Chen Tzu-Chiang, Ho Chia-Cheng, Lin Yi-Tang
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A method includes forming a gate stack including a gate electrode on a first semiconductor fin. The gate electrode includes a portion over and aligned to a middle portion of the first semiconductor fin. A second semiconductor fin is on a side of the gate electrode, and does not extend to under the gate electrode. The first and the second semiconductor fins are spaced apart from, and parallel to, each other. An end portion of the first semiconductor fin and the second semiconductor fin are etched. An epitaxy is performed to form an epitaxy region, which includes a first portion extending into a first space left by the etched first end portion of the first semiconductor fin, and a second portion extending into a second space left by the etched second semiconductor fin. A first source/drain region is formed in the epitaxy region. 1. A device comprising:a semiconductor substrate having a plurality of semiconductor strips extending therefrom, the plurality of semiconductor strips being parallel to each other;a dielectric layer over the substrate between adjacent ones of the semiconductor strips, the dielectric layer extending to an upper surface of the semiconductor strips;a semiconductor fin extending from at least a first strip of the plurality of semiconductor strips;a gate electrode over the semiconductor fin and on sidewalls of the semiconductor fin, the gate electrode extending over a top surface of the dielectric layer; andsource/drain regions extending over and contacting the first strip and a second strip of the plurality of semiconductor strips on opposing sides of the fin.2. The device of claim 1 , wherein the source/drain regions comprise facets that are neither parallel to claim 1 , nor perpendicular to claim 1 , top surfaces of the dielectric layer.3. The device of wherein a third strip of the plurality of semiconductor strips longitudinally aligned with and separated from the second strip claim 1 , the gate electrode extending between the second strip and ...

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Номер записи: 9
02-01-2020 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Номер: US20200006154A1
Автор: CHEN I-Sheng, Chen Tzu-Chiang, CHIANG Hung-Li
Принадлежит:

A semiconductor device includes a first plurality of stacked nanowire structures extending in a first direction disposed over a first region of a semiconductor substrate. Each nanowire structure of the first plurality of stacked nanowire structures includes a plurality of nanowires arranged in a second direction substantially perpendicular to the first direction. A nanowire stack insulating layer is between the substrate and a nanowire closest to the substrate of each nanowire structure of the first plurality of stacked nanowire structures. At least one second stacked nanowire structure is disposed over a second region of the semiconductor substrate, and a shallow trench isolation layer is between the first region and the second region of the semiconductor substrate. 1. A semiconductor device , comprising:a first plurality of stacked nanowire structures extending in a first direction disposed over a first region of a semiconductor substrate,wherein each nanowire structure of the first plurality of stacked nanowire structures includes a plurality of nanowires arranged in a second direction substantially perpendicular to the first direction;a nanowire stack insulating layer between the substrate and a nanowire closest to the substrate of each nanowire structure of the first plurality of stacked nanowire structures;at least one second stacked nanowire structure disposed over a second region of the semiconductor substrate; anda shallow trench isolation layer between the first region and the second region of the semiconductor substrate.2. The semiconductor device of claim 1 , wherein there are no shallow trench isolation layers between the stacked nanowire structures of the first plurality of stacked nanowire structures.3. The semiconductor device of claim 1 , wherein the first plurality of stacked nanowire structures are disposed over a common mesa structure.4. The semiconductor device of claim 1 , further comprising a gate structure defining a channel region disposed ...

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Номер записи: 10
02-01-2020 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Номер: US20200006155A1
Автор: CHEN Chih-Liang, CHEN I-Sheng, Chen Tzu-Chiang, CHIANG Hung-Li, Chou Lei-Chun
Принадлежит:

A method of manufacturing a semiconductor device includes forming a plurality of fin structures extending in a first direction over a semiconductor substrate. Each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate. An electrically conductive layer is formed between the first regions of a first adjacent pair of fin structures. A gate electrode structure is formed extending in a second direction substantially perpendicular to the first direction over the fin structure second region, and a metallization layer including at least one conductive line is formed over the gate electrode structure. 1. A method of manufacturing a semiconductor device , comprising:forming a plurality of fin structures extending in a first direction over a semiconductor substrate,wherein each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate;forming an electrically conductive layer between the first regions of a first adjacent pair of fin structures;forming a gate electrode structure extending in a second direction substantially perpendicular to the first direction over the fin structure second region; andforming a metallization layer including at least one conductive line over the gate electrode structure.2. The method according to claim 1 , wherein forming a plurality of fin structures comprises forming a nanowire structure in the second region of the fin structure.3. The method according to claim 2 , wherein forming the gate electrode structure comprises:forming a gate dielectric layer over at least one wire of the nanowire structure; andforming a gate electrode layer over the gate dielectric layer,wherein the gate dielectric layer and the gate electrode layer wrap around the at least one wire of the nanowire structure.4. The method according to claim 1 , wherein forming an electrically conductive layer comprises:forming ...

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Номер записи: 11
29-01-2015 дата публикации

METHOD OF MANUFACTURING A FIN-LIKE FIELD EFFECT TRANSISTOR (FINFET) DEVICE

Номер: US20150031182A1
Автор: CHANG Chih-Sheng, Chen Tzu-Chiang, Ho Chai-Cheng, Perng Tsu-Hsiu, YEH Chih Chieh
Принадлежит:

A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary FinFET device includes a semiconductor substrate; a fin structure disposed over the semiconductor substrate; and a gate structure disposed over a portion of the fin structure. The gate structure traverses the fin structure and separates a source region and a drain region of the fin structure, the source and drain region defining a channel therebetween. The source and drain region of the fin structure include a strained source and drain feature. The strained source feature and the strained drain feature each include: a first portion having a first width and a first depth; and a second portion disposed below the first portion, the second portion having a second width and a second depth. The first width is greater than the second width, and the first depth is less than the second depth. 1. A method comprising:forming a fin structure over a substrate;forming a gate structure over a portion of the fin structure;forming spacers on sidewalls of the gate structure;forming dummy spacers adjacent to the spacers;forming a trench having a first profile in the fin structure;thereafter, removing the dummy spacers;modifying the trench having the first profile in the fin structure, such that the trench has a second profile; andepitaxially (epi) growing a semiconductor material in the trench having the second profile.2. The method of wherein:the forming the trench having the first profile in the fin structure includes applying a first etch process to the fin structure to form a trench having a U-shaped profile; andthe modifying the trench having the first profile in the fin structure, such that the trench has the second profile includes applying a second etch process to the fin structure to modify the U-shaped profile of the trench to a T-shaped profile.3. The method of wherein:the removing the dummy spacers includes exposing a portion of the fin structure adjacent to the trench having the first ...

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Номер записи: 12
04-02-2021 дата публикации

MEMORY CELL WITH BUILT-IN AMPLIFYING FUNCTION, MEMORY DEVICE AND METHOD USING THE SAME

Номер: US20210035633A1
Автор: Chen Tzu-Chiang, Chen Yu-Sheng, CHENG Chao-Ching, CHIANG Hung-Li, Wong Hon-Sum Philip
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A memory device that includes at least one memory cell is introduced. Each of the at least one memory cell is coupled to a bit line and a word line. Each of the at least one memory cell includes a memory element and a selector element, in which the memory element is configured to store data of the at least one memory cell. The selector element is coupled to the memory element in series and is configured to select the memory element for a read operation and amplify the data stored in the memory element in the read operation. 1. A memory cell , comprising:a memory element, configured to store data of the memory cell; anda selector element, coupled to the memory element in series, configured to select the memory element for a read operation and amplify the data stored in the memory element in the read operation, wherein the selector element is located inside the memory cell.2. The memory cell of claim 1 , wherein a material of the selector element includes a negative resistance material that has a negative-resistance property claim 1 , and the selector element is configured to amplify the data stored in the memory element based on the negative-resistance property.3. The memory cell of claim 2 , whereinthe selector element includes an ovonic threshold switch that has a threshold voltage and a holding voltage, andan operating voltage of the selector element is selected from a range from the holding voltage to the threshold voltage of the ovonic threshold switch.4. The memory cell of claim 3 , whereinthe negative-resistance property comprises an inverse proportion between a change of a voltage applied to the selector element and a change of a current flowing through the selector element.5. The memory cell of claim 3 , whereinthe selector element is configured to electrically connect the memory element to a bit line during the read operation when the memory element is in a first logic state, andthe selector element is configured to electrically insulate the memory element ...

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Номер записи: 13
04-02-2021 дата публикации

GATE-ALL-AROUND STRUCTURE AND MANUFACTURING METHOD FOR THE SAME

Номер: US20210036119A1
Автор: CHEN I-Sheng, Chen Tzu-Chiang, CHENG Chao-Ching, YANG Yu-Lin
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A gate-all-around structure is provided. The gate-all-around structure includes a plurality of nanostructures stacked over a substrate in a vertically direction, and the nanostructures extends from a gate region to a source/drain (S/D) region. The gate-all-around structure includes a gate structure formed in the gate region around the first nanostructures, and a S/D structure formed in the S/D region. The S/D structure is in direct contact with a top surface of one of the nanostructures 1. A gate-all-around structure , comprising:a plurality of nanostructures stacked over a substrate in a vertically direction, wherein the nanostructures extends from a gate region to a source/drain (S/D) region;a gate structure formed in the gate region around the first nanostructures; anda S/D structure formed in the S/D region, wherein the S/D structure is in direct contact with a top surface of one of the nanostructures.2. The gate-all-around structure of claim 1 , further comprising:an inner spacer between the gate structure and the S/D structure.3. The gate-all-around structure of claim 2 , wherein the inner spacer has a C-shaped structure.4. The gate-all-around structure of claim 1 , further comprising:a isolation layer formed between the substrate and the nanostructures.5. The gate-all-around structure of claim 4 , wherein the isolation layer is in direct contact with the S/D structure.6. The gate-all-around structure of claim 4 , further comprising:an isolation structure formed over the substrate, wherein the isolation layer is higher than a top surface of the isolation structure.7. The gate-all-around structure of claim 1 , further comprising:a fin extended from the substrate, wherein the nanostructure formed over the fin.8. A gate-all-around structure claim 1 , comprising:a plurality of nanostructures stacked over a substrate in a vertically direction;a gate structure formed around the nanostructures;a gate spacer formed on a sidewall of the gate structure; anda S/D ...

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Номер записи: 14
24-02-2022 дата публикации

DATA STORAGE ELEMENT AND MANUFACTURING METHOD THEREOF

Номер: US20220059580A1
Автор: Chen Tzu-Chiang, Chen Yu-Sheng, CHENG Chao-Ching, CHIANG Hung-Li, Chiu Jung-Piao
Принадлежит:

Disclosed herein, in some embodiments, is a memory device. The memory device includes a bottom electrode disposed over a substrate and a top electrode disposed over the bottom electrode. An upper surface of the bottom electrode faces away from the substrate. A bottom surface of the top electrode faces the substrate. A data storage layer is arranged between the bottom electrode and the top electrode. At least a portion of the bottom surface of the top electrode does not overlap with any portion of the top surface of the bottom electrode along a first direction parallel to the bottom surface of the top electrode. Furthermore, at least a portion of the top surface of the bottom electrode does not overlap with any portion of the bottom surface of the top electrode along the first direction. 1. A memory device , comprising:a bottom electrode disposed over a substrate, wherein an upper surface of the bottom electrode faces away from the substrate;a top electrode over the bottom electrode, wherein the top electrode has a bottom surface facing the substrate;a data storage layer arranged between the bottom electrode and the top electrode, wherein at least a portion of the bottom surface of the top electrode does not overlap with any portion of the upper surface of the bottom electrode along a first direction parallel to the bottom surface of the top electrode; andwherein at least a portion of the upper surface of the bottom electrode does not overlap with any portion of the bottom surface of the top electrode along the first direction.2. The memory device of claim 1 , wherein no more than 60% of the surface area of the bottom surface of the top electrode overlap with a portion of the upper surface of the bottom electrode along the first direction.3. The memory device of claim 2 , wherein the bottom surface of the top electrode does not overlap with the upper surface of the bottom electrode along the first direction.4. The memory device of claim 1 , wherein the data storage ...

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Номер записи: 15
06-02-2020 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Номер: US20200043802A1
Автор: CHEN I-Sheng, Chen Tzu-Chiang, CHENG Chao-Ching, CHIANG Hung-Li
Принадлежит:

In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers containing Ge and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A Ge concentration in the first semiconductor layers is increased. A sacrificial gate structure is formed over the fin structure. A source/drain epitaxial layer is formed over a source/drain region of the fin structure. The sacrificial gate structure is removed. The second semiconductor layers in a channel region are removed, thereby releasing the first semiconductor layers in which the Ge concentration is increased. A gate structure is formed around the first semiconductor layers in which the Ge concentration is increased. 1. A method of manufacturing a semiconductor device , comprising:forming a fin structure in which first semiconductor layers containing Ge and second semiconductor layers are alternately stacked over a bottom fin structure;increasing a Ge concentration in the first semiconductor layers;forming a sacrificial gate structure over the fin structure;forming a source/drain epitaxial layer over a source/drain region of the fin structure;removing the sacrificial gate structure;removing the second semiconductor layers in a channel region, thereby releasing the first semiconductor layers in which the Ge concentration is increased; andforming a gate structure around the first semiconductor layers in which the Ge concentration is increased.2. The method of claim 1 , wherein the Ge concentration is increased by oxidizing the first semiconductor layers.3. The method of claim 2 , wherein the Ge concentration is increased by:forming an oxide layer over the fin structure; andperforming a thermal treatment, thereby oxidizing the first semiconductor layers.4. The method of claim 3 , wherein the thermal treatment is performed at 800° C. to 1000° C.5. The method of claim 3 , wherein after the thermal treatment claim 3 , the oxide layer is removed.6. The ...

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Номер записи: 16
06-02-2020 дата публикации

Semiconductor Device and Method

Номер: US20200043803A1
Автор: Chao-Ching Cheng, Chen-Feng Hsu, Chih Chieh Yeh, Tung Ying Lee, Tzu-Chiang CHEN, Yu-Lin Yang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Nanowire devices and fin devices are formed in a first region and a second region of a substrate. To form the devices, alternating layers of a first material and a second material are formed, inner spacers are formed adjacent to the layers of the first material, and then the layers of the first material are removed to form nanowires without removing the layers of the first material within the second region. Gate structures of gate dielectrics and gate electrodes are formed within the first region and the second region in order to form the nanowire devices in the first region and the fin devices in the second region.

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Номер записи: 17
06-02-2020 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20200044060A1
Автор: CHEN I-Sheng, Chen Tzu-Chiang, CHENG Chao-Ching, CHIANG Hung-Li
Принадлежит:

In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A sacrificial gate structure having sidewall spacers is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is removed. The second semiconductor layers are laterally recessed. Dielectric inner spacers are formed on lateral ends of the recessed second semiconductor layers. The first semiconductor layers are laterally recessed. A source/drain epitaxial layer is formed to contact lateral ends of the recessed first semiconductor layer. The second semiconductor layers are removed thereby releasing the first semiconductor layers in a channel region. A gate structure is formed around the first semiconductor layers. 1. A method of manufacturing a semiconductor device , comprising:forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked over a bottom fin structure;forming a sacrificial gate structure having sidewall spacers over the fin structure, the sidewall spacers being formed in a direction perpendicular to a major surface of a semiconductor substrate;removing a source/drain region of the fin structure, which is not covered by the sacrificial gate structure;laterally recessing the second semiconductor layers;forming dielectric inner spacers on lateral ends of the recessed second semiconductor layers;laterally recessing the first semiconductor layers;forming a source/drain epitaxial layer to contact lateral ends of the recessed first semiconductor layer;removing the second semiconductor layers thereby releasing the first semiconductor layers in a channel region; andforming a gate structure around the first semiconductor layers.2. The method of claim 1 , wherein an interface between at least one of the first semiconductor layers and the ...

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Номер записи: 18
06-02-2020 дата публикации

Semiconductor device and manufacturing method thereof

Номер: US20200044061A1
Автор: Chao-Ching Cheng, Hung-Li Chiang, I-Sheng Chen, Tzu-Chiang CHEN
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A sacrificial gate structure having sidewall spacers is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is removed. The second semiconductor layers are laterally recessed. Dielectric inner spacers are formed on lateral ends of the recessed second semiconductor layers. The first semiconductor layers are laterally recessed. A source/drain epitaxial layer is formed to contact lateral ends of the recessed first semiconductor layer. The second semiconductor layers are removed thereby releasing the first semiconductor layers in a channel region. A gate structure is formed around the first semiconductor layers.

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Номер записи: 19
25-02-2021 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Номер: US20210057539A1
Автор: Chen Tzu-Chiang, CHENG Chao-Ching, Chiang Kuo-Cheng, HSU Chen-Feng, Lee Tung Ying, YANG Yu-Lin, YUN Wei-Sheng
Принадлежит:

In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched. 1. A semiconductor device , comprising:semiconductor wires disposed over a substrate;a source/drain epitaxial layer wrapping around a source/drain region of each of the semiconductor wires;a gate dielectric layer disposed on and wrapping around a channel region of each of the semiconductor wires;a gate electrode layer disposed on the gate dielectric layer; andinsulating spacers each disposed between the gate dielectric layer and the source/drain epitaxial layer,wherein an additional insulating spacer is disposed above an uppermost one of the semiconductor wires.2. The semiconductor device of claim 1 , wherein each of the insulating spacers and the additional insulating spacer includes two layers.3. The semiconductor device of claim 2 , wherein the two layers are a first layer and a second layer formed on the first layer claim 2 , and the first layer has a smaller thickness than the second layer.4. The semiconductor device of claim 2 , wherein the insulating spacers and the additional insulating spacer include at least one of SiOC claim 2 , SiOCN and SiCN.5. The semiconductor device of claim 2 , wherein the first layer of the insulating spacers is in contact ...

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Номер записи: 20
13-02-2020 дата публикации

Method of manufacturing a semiconductor device and a semiconductor device

Номер: US20200051869A1
Автор: Hung-Li Chiang, I-Sheng Chen, Tzu-Chiang CHEN
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device includes a first plurality of stacked nanowire structures extending in a first direction disposed over a first region of a semiconductor substrate. Each nanowire structure of the first plurality of stacked nanowire structures includes a plurality of nanowires arranged in a second direction substantially perpendicular to the first direction. A nanowire stack insulating layer is between the substrate and a nanowire closest to the substrate of each nanowire structure of the first plurality of stacked nanowire structures. At least one second stacked nanowire structure is disposed over a second region of the semiconductor substrate, and a shallow trench isolation layer is between the first region and the second region of the semiconductor substrate.

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Номер записи: 21
13-02-2020 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Номер: US20200052086A1
Автор: Chen Tzu-Chiang, CHENG Chao-Ching, Huang Chao-Hsien, Lee Tung Ying, YANG Yu-Lin, Yu Shao-Ming
Принадлежит:

In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. A first insulating layer is formed, in the source/drain space, at least on etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space, thereby forming air gaps between the source/drain epitaxial layer and the first semiconductor layers. 1. A semiconductor device , comprising:semiconductor wires disposed over a substrate, each of the semiconductor wires including a channel region;a source/drain region in contact with the first semiconductor wires;a gate dielectric layer disposed on and wrapping around the channel region of each of the first semiconductor wires;a gate electrode layer disposed on the gate dielectric layer and wrapping around the channel region; and a first insulating layer disposed in a space defined by adjacent first semiconductor wires, the gate dielectric layer and the source/drain region;', 'a second insulating layer disposed on the first insulating layer in the space; and', 'an air gap disposed in the space, wherein:, 'inner spacers each comprisingeach of the inner spacers has a rectangular cross section,the air gap is defined by the source/drain region, the first insulating layer and the second insulating layer, anda lateral end of the first insulating layer is located closer to the source/drain region than a lateral end of the second insulating layer.2. The semiconductor device of claim 1 , wherein the second insulating layer is made of a low-k dielectric material.3. The semiconductor device of claim 2 , wherein the first insulating layer is ...

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Номер записи: 22
13-02-2020 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Номер: US20200052091A1
Автор: Chen Tzu-Chiang, CHENG Chao-Ching, HSU Chen-Feng, Lee Tung Ying, YANG Yu-Lin, YUN Wei-Sheng
Принадлежит:

In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched. 1. A method of manufacturing a semiconductor device , comprising:forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked;forming a sacrificial gate structure over the fin structure;removing first semiconductor layers from a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a source/drain space, wherein the second semiconductor layers remain in the source/drain space;laterally etching the first semiconductor layers through the source/drain space;forming an inner spacer made of a dielectric material on an end of each of the etched first semiconductor layers;forming a source/drain epitaxial layer to wrap around the second semiconductor layers in the source/drain space and to cover the inner spacer; andforming a source/drain contact layer in contact with the source/drain epitaxial layer that wraps around the second semiconductor layers.2. The method of claim 1 , wherein the inner spacer includes two layers.3. The method of claim 1 , wherein the inner spacer is formed by:forming a dielectric layer in the source/drain space; andetching the ...

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Номер записи: 23
13-02-2020 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20200052092A1
Автор: Chen Tzu-Chiang, CHENG Chao-Ching, HSU Chen-Feng, YANG Yu-Lin, YUN Wei-Sheng
Принадлежит:

A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer. 1. A method of manufacturing a semiconductor device , comprising:forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked;forming a sacrificial gate structure over the fin structure;forming gate sidewall spacers on opposing side faces of the sacrificial gate structure;etching a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a source/drain space;forming a source/drain epitaxial layer in the source/drain space;removing the sacrificial gate structure, thereby exposing a part of the fin structure;laterally etching the first semiconductor layers from the exposed fin structure to form recesses under the gate sidewall spacers;forming inner spacers in the recesses; andforming a gate dielectric layer covering the inner spacers and forming a gate electrode layer around the second semiconductor layer,wherein each of the inner spacers has a two-layer structure.2. The method of claim 1 , wherein each of the inner spacers has a curved face in a cross section.3. The method of claim 2 , wherein the curved face is a convex shape toward the source/drain epitaxial layer.4. The method of claim 1 , wherein each of the inner spacers has curved faces claim 1 , one of which is a convex shape toward the source/drain epitaxial layer and the other one of which is convex shape toward the gate electrode in a cross section.5. The method of claim 1 , ...

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Номер записи: 24
13-02-2020 дата публикации

Nanowire Stack GAA Device with Inner Spacer and Methods for Producing the Same

Номер: US20200052131A1
Автор: CHEN I-Sheng, Chen Tzu-Chiang, CHENG Chao-Ching, DIAZ Carlos H.
Принадлежит:

A nanowire FET device includes a vertical stack of nanowire strips configured as the semiconductor body. One or more of the top nanowire strips are receded and are shorter than the rest of the nanowire strips stacked lower. Inner spacers are uniformly formed adjacent to the receded nanowire strips and the rest of the nanowire strips. Source/drain structures are formed outside the inner spacers and a gate structure is formed inside the inner spacers, which wraps around the nanowire strips. 1. A semiconductor device comprising:a substrate;a plurality of nanowire structures over the substrate;a gate structure over the plurality of nanowire structures, wherein the gate structure extends between adjacent ones of the plurality of nanowire structure;upper spacers along sidewalls of the gate structure;source/drain regions on opposing sides of the gate structure, the source/drain regions contacting the plurality of nanowire structures; andinner spacers interposed between the source/drain regions and the gate structure, wherein a surface of the gate structure at an interface between the gate structure and each of the inner spacers is non-planar.2. The semiconductor device of further comprising voids interposed between the source/drain regions and the inner spacers.3. The semiconductor device of claim 1 , wherein the surface of the gate structure at the interface between the gate structure and each of the inner spacers is concave.4. The semiconductor device of claim 1 , wherein the inner spacers are below the upper spacers.5. The semiconductor device of claim 1 , further comprising a fin claim 1 , wherein the plurality of nanowire structures is on the fin.6. The semiconductor device of claim 1 , wherein the source/drain regions comprise an epitaxial layer on the plurality of nanowire structures.7. The semiconductor device of claim 6 , wherein the epitaxial layer extends between adjacent ones of the plurality of nanowire structures.8. The semiconductor device of claim 1 , ...

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Номер записи: 25
10-03-2022 дата публикации

MEMORY CELL WITH BUILT-IN AMPLIFYING FUNCTION, MEMORY DEVICE AND METHOD USING THE SAME

Номер: US20220076741A1
Автор: Chen Tzu-Chiang, Chen Yu-Sheng, CHENG Chao-Ching, CHIANG Hung-Li, Wong Hon-Sum Philip
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A memory device that includes at least one memory cell is introduced. Each of the at least one memory cell is coupled to a bit line and a word line. Each of the at least one memory cell includes a memory element and a selector element, in which the memory element is configured to store data of the at least one memory cell. The selector element is coupled to the memory element in series and is configured to select the memory element for a read operation and amplify the data stored in the memory element in the read operation. 1. A memory cell , comprising:a memory element, configured to store data of the memory cell; anda selector element, coupled to the memory element in series, configured to select the memory element for a read operation and amplify the data stored in the memory element in the read operation, wherein the selector element is located inside the memory cell, whereinthe memory cell includes a stack of a metal pad layer, a memory element layer and a selector element layer,the memory element layer is sandwiched between the metal pad layer and the selector element layer,the stack of the metal pad layer, the memory element layer and the selector element layer is sandwiched between a metal bit line layer and a metal word line layer, andthe metal bit line layer directly contacts the metal pad layer.2. The memory cell of claim 1 , wherein a material of the selector element includes a negative resistance material that has a negative-resistance property claim 1 , and the selector element is configured to amplify the data stored in the memory element based on the negative-resistance property.3. The memory cell of claim 1 , whereinthe selector element includes an ovonic threshold switch that has a threshold voltage and a holding voltage,when a voltage in a range from the holding voltage to the threshold voltage is applied to the memory cell being in a first logic state, a current flowing through the memory element is greater than an operating current of the ...

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Номер записи: 26
20-02-2020 дата публикации

SEMICONDUCTOR DEVICE WITH FIN END SPACER DUMMY GATE AND METHOD OF MANUFACTURING THE SAME

Номер: US20200058763A1
Автор: Chang Kai-Tai, Chen Tzu-Chiang, Ho Chia-Cheng, Lee Tung Ying, LIN Ming-Shiang, Wang Tzu-Chung, YUN Wei-Sheng
Принадлежит:

A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride. 1. A method of manufacturing a semiconductor device , comprising:forming a fin;forming a first isolation insulating layer around a bottom portion of the fin;forming a dummy oxide layer over the fin and the first isolation insulating layer;forming a first dummy structure over the fin and a second dummy structure over an edge region of the fin at an end in a lengthwise direction of the fin;forming sidewall spacer layers on the first and second dummy structures;etching source/drain regions of the fin, which are not covered by the sidewall spacer layers, thereby forming source/drain spaces;forming source/drain epitaxial layers in the source/drain spaces;forming an interlayer dielectric layer over the source/drain epitaxial layers and the first and second dummy structures;removing the first dummy structure thereby forming a first gate space, and at least a part of the second dummy structure thereby forming a second gate space; andforming a metal gate structure in the first gate space and forming a spacer dummy gate layer in the second gate space.2. The method of claim 1 , wherein in the removing at least a part of the second dummy structure claim 1 , only an upper portion of the second dummy structure is removed claim 1 , thereby leaving ...

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Номер записи: 27
20-02-2020 дата публикации

SEMICONDUCTOR DEVICE WITH FIN END SPACER DUMMY GATE AND METHOD OF MANUFACTURING THE SAME

Номер: US20200058784A1
Автор: Chang Kai-Tai, Chen Tzu-Chiang, Ho Chia-Cheng, Lee Tung Ying, LIN Ming-Shiang, Wang Tzu-Chung, YUN Wei-Sheng
Принадлежит:

A semiconductor device includes a plurality of fins on a substrate. A fin liner is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A plurality of polycrystalline silicon layers are formed on the insulating layer. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. One of the polycrystalline silicon layers is formed on a region spaced-apart from the fins. 120-. (canceled)21. A method of manufacturing a semiconductor device , comprising:forming a first isolation insulating layer between fins;forming a sacrificial oxide layer over the fins and the first isolation insulating layer;forming first sacrificial gate layers on the fins and second sacrificial gate layers on edge regions of the fins at an end in a lengthwise direction of the fins;forming sidewall spacer layers on opposing side faces of the first and second sacrificial gate layers;etching source/drain regions of the fins, which are not covered by the sidewall spacer layers and the first and second sacrificial gate layers, thereby forming source/drain spaces;forming source/drain epitaxial layers in the source/drain spaces;forming interlayer dielectric layers on the source/drain epitaxial layers;at least partially removing the second sacrificial gate layers, thereby forming second gate spaces; and 'wherein the second sacrificial gate layers are only partially removed leaving remaining second sacrificial layers and the spacer dummy gate layers are formed on the remaining second sacrificial layers.', 'forming spacer dummy gate layers in the second gate spaces,'}22. (canceled)23. The method of claim 21 , wherein a thickness of the spacer dummy gate layers is smaller than a thickness of the remaining second sacrificial gate layers.24. The method of claim 21 , wherein the second sacrificial gate layers are completely removed to expose the sacrificial oxide layer and the spacer dummy gate layers are formed ...

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Номер записи: 28
04-03-2021 дата публикации

Transistors with Channels Formed of Low-Dimensional Materials and Method Forming Same

Номер: US20210066627A1
Автор: Chao Tzu-Ang, Chen Tzu-Chiang, CHENG Chao-Ching, CHIANG Hung-Li, Li Lain-Jong, LU Chun-Chieh
Принадлежит:

A method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. Remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. A transistor is then formed based on the protruding fin. 1. A method comprising:forming a first low-dimensional layer over an isolation layer;forming a first insulator over the first low-dimensional layer;forming a second low-dimensional layer over the first insulator;forming a second insulator over the second low-dimensional layer;patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin, with remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator being a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively; andforming a transistor based on the protruding fin.2. The method of claim 1 , wherein the forming the first low-dimensional layer comprises growing a carbon nanotube network through an immersion process.3. The method of claim 1 , wherein the forming the first low-dimensional layer comprises growing aligned carbon nanotubes.4. The method of further comprising:forming a catalyst strip, wherein the aligned carbon nanotubes are grown from the catalyst strip.5. The method of claim 1 , wherein the forming the first low-dimensional layer ...

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Номер записи: 29
17-03-2022 дата публикации

METHOD FOR FORMING MULTI-GATE SEMICONDUCTOR DEVICE

Номер: US20220085162A1
Автор: CHEN I-Sheng, Chen Tzu-Chiang, CHENG Chao-Ching, CHIANG Hung-Li, Huang Shih-Syuan
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor structures and method for forming the same are provided. The semiconductor structure includes a substrate and first nanostructures and second nanostructures formed over the substrate. The semiconductor structure further includes a first source/drain structure formed adjacent to the first nanostructures and a second source/drain structure formed adjacent to the second nanostructures. The semiconductor structure further includes a first contact plug formed over the first source/drain structure and a second contact plug formed over the second source/drain structure. In addition, a bottom portion of the first contact plug is lower than a bottom portion of the first nanostructures, and a bottom portion of the second contact plug is higher than a top portion of the second nanostructures. 1. A method for manufacturing a semiconductor structure , comprising:alternately stacking first semiconductor layers and second semiconductor layers over a substrate;patterning the first semiconductor layers and the second semiconductor layers to form a fin structure;recessing the fin structure to form a recess;conformally forming a source/drain semiconductor layer over the recess; andfilling the recess by a conductive material to form a contact plug over the source/drain semiconductor layer.2. The method for manufacturing the semiconductor structure as claimed in claim 1 , wherein a bottom portion of the contact plug is lower than a bottom portion of a topmost layer of the first semiconductor layers.3. The method for manufacturing the semiconductor structure as claimed in claim 2 , wherein the bottom portion of the contact plug is lower than a bottom portion of a bottommost layer of the first semiconductor layers.4. The method for manufacturing the semiconductor structure as claimed in claim 1 , further comprising:removing the second semiconductor layers; andforming a gate structure wrapping around the first semiconductor layers.5. The method for manufacturing the ...

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Номер записи: 30
28-02-2019 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Номер: US20190067113A1
Автор: CHEN Chih-Liang, CHEN I-Sheng, Chen Tzu-Chiang, CHENG Chao-Ching, CHIANG Hung-Li, GUO Ta-Pen, HUANG Szu-Wei, YANG Yu-Lin
Принадлежит:

In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer. 1. A method of manufacturing a semiconductor device , comprising:forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked;forming a sacrificial gate structure over the fin structure;etching the first semiconductor layers at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed;forming a dielectric layer at the first source/drain space, thereby covering the exposed second semiconductor layers;etching the dielectric layer and part of the second semiconductor layers, thereby forming a second source/drain space; andforming a source/drain epitaxial layer in the second source/drain space, wherein:at least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, andat least one of the second semiconductor layers is separated from the source/drain epitaxial layer disposed thereabove by the dielectric ...

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Номер записи: 31
28-02-2019 дата публикации

SEMICONDUCTOR DEVICE STRUCTURE WITH SEMICONDUCTOR WIRE

Номер: US20190067121A1
Автор: CHEN I-Sheng, Chen Tzu-Chiang, CHIANG Hung-Li, HUANG Szu-Wei, Lee Tung-Ying, WEI Huan-Sheng
Принадлежит:

Semiconductor device structures are provided. The semiconductor device structure includes a first semiconductor wire over a semiconductor substrate. The first semiconductor wire has a first width and a first thickness. The semiconductor device structure also includes a first gate stack surrounding the first semiconductor wire. The semiconductor device structure further includes a second semiconductor wire over the semiconductor substrate. The first semiconductor wire and the second semiconductor wire include different materials. The second semiconductor wire has a second width and a second thickness. The first width is greater than the second width. The first thickness is less than the second thickness. In addition, the semiconductor device structure includes a second gate stack surrounding the second semiconductor wire. 1. A semiconductor device structure , comprising:first semiconductor wires vertically arranged over a semiconductor substrate, wherein each of the first semiconductor wires has a first width and a first thickness;a first gate stack surrounding the first semiconductor wires;second semiconductor wires vertically arranged over the semiconductor substrate, wherein the first semiconductor wire and the second semiconductor wire comprise different materials, and each of the second semiconductor wires has a second width and a second thickness, and wherein the first width is greater than the second width, and the first thickness is less than the second thickness; anda second gate stack surrounding the second semiconductor wires.2. The semiconductor device structure as claimed in claim 1 , wherein the first width and the second width are along a [100] crystalline direction.3. The semiconductor device structure as claimed in claim 1 , wherein the first thickness and the second thickness are along a [110] crystalline direction.4. The semiconductor device structure as claimed in claim 1 , wherein the first width is substantially equal to the second thickness.5. ...

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Номер записи: 32
28-02-2019 дата публикации

Semiconductor Device and Method

Номер: US20190067122A1
Автор: Chen Tzu-Chiang, CHENG Chao-Ching, HSU Chen-Feng, Lee Tung Ying, YANG Yu-Lin, YEH Chih Chieh
Принадлежит:

Nanowire devices and fin devices are formed in a first region and a second region of a substrate. To form the devices, alternating layers of a first material and a second material are formed, inner spacers are formed adjacent to the layers of the first material, and then the layers of the first material are removed to form nanowires without removing the layers of the first material within the second region. Gate structures of gate dielectrics and gate electrodes are formed within the first region and the second region in order to form the nanowire devices in the first region and the fin devices in the second region. 1. A method of manufacturing a semiconductor device , the method comprising:forming a first semiconductor layer over both a first region and a second region of a semiconductor substrate, the first semiconductor layer comprising a first material;forming a second semiconductor layer over the first region and the second region;removing the first semiconductor layer from over the first region to form a nanowire channel from the second semiconductor layer, wherein the removing the first semiconductor layer from over the first region does not remove the first semiconductor layer from over the second region; andforming a first gate electrode of a first transistor around the nanowire channel, the first transistor being formed in the first region; andforming a second gate electrode of a second transistor over the first semiconductor layer and the second semiconductor layer in the second region, the second transistor being formed in the second region.2. The method of claim 1 , wherein the removing the first semiconductor layer is performed at least in part with a wet etching process.3. The method of claim 1 , further comprising forming a source/drain region adjacent to the second semiconductor layer prior to the removing the first semiconductor layer.4. The method of claim 1 , further comprising forming a spacer within the first semiconductor layer and between the ...

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Номер записи: 33
28-02-2019 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Номер: US20190067125A1
Автор: CHEN Chih-Liang, CHEN I-Sheng, Chen Tzu-Chiang, CHENG Chao-Ching, CHIANG Hung-Li, GUO Ta-Pen, HUANG Szu-Wei, YANG Yu-Lin
Принадлежит:

In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer. 1. A method of manufacturing a semiconductor device , comprising:forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked and protruding from an isolation insulating layer;forming a sacrificial gate structure over the fin structure;etching the first semiconductor layers at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed;forming a dielectric layer at the first source/drain space, thereby covering the exposed second semiconductor layers;etching the dielectric layer and part of the second semiconductor layers, thereby forming a second source/drain space; andforming a source/drain epitaxial layer in the second source/drain space, wherein:at least one of the second semiconductor layers is in contact with the source/drain epitaxial layer,at least one of the second semiconductor layers is separated from a bottom of the source/ ...

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Номер записи: 34
28-02-2019 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Номер: US20190067418A1
Автор: CHEN I-Sheng, Chen Tzu-Chiang, CHENG Chao-Ching, YANG Yu-Lin
Принадлежит:

In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers, the second semiconductor layer and an upper portion of the fin structure at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, are etched. A dielectric layer is formed over the etched upper portion of the fin structure. A source/drain epitaxial layer is formed. The source/drain epitaxial layer is connected to ends of the second semiconductor wires, and a bottom of the source/drain epitaxial layer is separated from the fin structure by the dielectric layer. 1. A method of manufacturing a semiconductor device , comprising:forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked over a bottom fin structure;forming a sacrificial gate structure over the fin structure;removing by etching the first semiconductor layers, the second semiconductor layers and an upper portion of the bottom fin structure at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure;forming a dielectric layer over the etched upper portion of the bottom fin structure; andforming a source/drain epitaxial layer, wherein:the source/drain epitaxial layer is connected to ends of the second semiconductor layers, anda bottom of the source/drain epitaxial layer is separated from the bottom fin structure by the dielectric layer.2. The method of claim 1 , further comprising claim 1 , after the first semiconductor layers claim 1 , the second semiconductor layers and the upper portion of the bottom fin structure are etched claim 1 , laterally etching the first semiconductor layers.3. The method of claim 2 , wherein the dielectric layer is also formed on laterally etched ends of the first ...

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Номер записи: 35
28-02-2019 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Номер: US20190067441A1
Автор: Chen Tzu-Chiang, CHENG Chao-Ching, Huang Chao-Hsien, Lee Tung Ying, YANG Yu-Lin, Yu Shao-Ming
Принадлежит:

In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. A first insulating layer is formed, in the source/drain space, at least on etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space, thereby forming air gaps between the source/drain epitaxial layer and the first semiconductor layers. 1. A method of manufacturing a semiconductor device , comprising:forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked;forming a sacrificial gate structure over the fin structure;etching a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a source/drain space;laterally etching the first semiconductor layers through the source/drain space, to form recesses;forming a first insulating layer, in the recesses, at least on etched first semiconductor layers;after the first insulating layer is formed, forming the second insulating layer different from the first insulating layer in the recesses on the first insulating layer; andforming a source/drain epitaxial layer in the source/drain space, thereby forming air gaps between the source/drain epitaxial layer and the first semiconductor layers.2. The method of claim 1 , wherein each of the air gaps is defined by the source/drain epitaxial layer and the first and second insulating layers disposed in the recesses.3. The method of claim 2 , wherein the lateral end of one of the first semiconductor layer has a flat surface.4. The method of claim 2 , wherein the lateral ...

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Номер записи: 36
05-03-2020 дата публикации

Semiconductor device structure with semiconductor wire

Номер: US20200075427A1
Автор: Huan-Sheng WEI, Hung-Li Chiang, I-Sheng Chen, Szu-Wei Huang, Tung-Ying Lee, Tzu-Chiang CHEN
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Semiconductor device structures are provided. The semiconductor device structure includes a number of first semiconductor wires over a semiconductor substrate, and the first semiconductor wires are vertically spaced apart from each other. The semiconductor device structure includes a first gate stack partially wrapping the first semiconductor wires, and a spacer element adjacent to the first gate stack. Each of the first semiconductor wires has a first portion directly below the spacer element and a second portion directly below the first gate stack, the first portion has a first width, the second portion has a second width, and the first width is greater than the second width.

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Номер записи: 37
05-03-2020 дата публикации

NANOWIRE STACK GAA DEVICE WITH INNER SPACER AND METHODS FOR PRODUCING THE SAME

Номер: US20200075716A1
Автор: Chen Tzu-Chiang, CHENG Chao-Ching, Lee Tung Ying, Wang Tzu-Chung
Принадлежит:

The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, and a dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile. 1. A device , comprising:a substrate;a channel region including a stack of nanowire structures over the substrate, the stack of nanowire structures including a first nanowire structure that includes a first segment at an edge of the first nanowire structure and a second segment adjacent to the first segment, the second segment having a larger diameter than the first segment;a source/drain structure adjacent to and contacting the first segment of the first nanowire structure;a gate structure wrapping around the first nanowire structure; andan inner spacer structure laterally between the source/drain structure and the gate structure.2. The device of claim 1 , wherein the source/drain structure laterally contacts an edge portion of the first nanowire structure.3. The device of claim 1 , wherein the inner spacer structure is substantially dome-shaped with an apex laterally pointing to the gate structure.4. The device of claim 1 , wherein the inner spacer structure is substantially hat-shaped with a convex top of the hat shape pointing to the gate structure.5. The device of claim 1 , wherein the stack of nanowire structures further includes a second nanowire structure below the first nanowire structure claim 1 , the second nanowire structure including a first segment and a second ...

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Номер записи: 38
05-03-2020 дата публикации

Nanowire Stack GAA Device with Inner Spacer and Methods for Producing the Same

Номер: US20200075718A1
Автор: Chen Tzu-Chiang, CHENG Chao-Ching, Lee Tung Ying, Wang Tzu-Chung
Принадлежит:

The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, and a dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile. 1. A method of forming a semiconductor device , the method comprising:forming alternating layers of first semiconductor layers and second semiconductor layers on a semiconductor substrate, the first semiconductor layers being formed of a first material, the second semiconductor layers being formed of a second materialpatterning the alternating layers to form a fin;forming isolation regions along opposing sides of the fin;forming a sacrificial gate structure over the fin;forming an outer spacer along sidewalls of the sacrificial gate structure;forming a dielectric layer over the fin adjacent the outer spacer;forming a first opening in dielectric layer to the fin;removing first portions of the first semiconductor layers exposed in the first opening, second portions of the first semiconductor layers under the sacrificial gate structure remaining;forming an inner spacer along sidewalls of the second portions of the first semiconductor layers and along sidewalls of the outer spacer;epitaxially growing a source/drain region in the first opening;removing the sacrificial gate structure to form a second opening;removing the second portions of the first semiconductor layers; andforming a gate structure in the second opening.2. The method of claim 1 , wherein the inner spacer comprises a ...

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Номер записи: 39
18-03-2021 дата публикации

FORMING SEMICONDUCTOR STRUCTURES WITH TWO-DIMENSIONAL MATERIALS

Номер: US20210083082A1
Автор: Chen Tzu- Chiang, CHENG Chao-Ching, CHIANG Hung-Li, Li Ming-Yang, LU Chun-Chieh
Принадлежит:

A process is provided to fabricate a finFET device having a semiconductor layer of a two-dimensional “2D” semiconductor material. The semiconductor layer of the 2D semiconductor material is a thin film layer formed over a dielectric fin-shaped structure. The 2D semiconductor layer extends over at least three surfaces of the dielectric fin structure, e.g., the upper surface and two sidewall surfaces. A vertical protrusion metal structure, referred to as “metal fin structure”, is formed about an edge of the dielectric fin structure and is used as a seed to grow the 2D semiconductor material. 1. A structure , comprising:a substrate;a first fin structure of a dielectric material over the substrate, the first fin structure having a first sidewall and a second sidewall extending along a first direction and an upper surface meeting between the first sidewall and the second sidewall;a first metal fin structure laterally contacting an edge surface of the first fin structure in the first direction;a semiconductor layer of a two-dimensional material over at least the first sidewall and the second sidewall of the first fin structure along the first direction, wherein the semiconductor layer is grown using the first metal fin structure as a seed;a gate structure adjacent to a first portion of the semiconductor layer; anda source/drain structure adjacent to a second portion of the semiconductor layer.2. (canceled)3. The structure of claim 1 , wherein the first metal fin structure is shorter than the first fin structure in the first direction.4. The structure of claim 1 , wherein the semiconductor layer at least partially covers the first metal fin structure.5. The structure of claim 1 , wherein the first metal fin structure extends beyond the first fin structure in a second direction that is substantially orthogonal to the first direction.6. The structure of claim 1 , wherein the first metal fin structure is a body contact structure.7. The structure of claim 1 , further ...

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Номер записи: 40
12-03-2020 дата публикации

MULTI-GATE SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

Номер: US20200083327A1
Автор: CHEN I-Sheng, Chen Tzu-Chiang, CHENG Chao-Ching, CHIANG Hung-Li, Huang Shih-Syuan
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor structures and method for forming the same are provided. The semiconductor structure includes a substrate and first nanostructures and second nanostructures formed over the substrate. The semiconductor structure further includes a first source/drain structure formed adjacent to the first nanostructures and a second source/drain structure formed adjacent to the second nanostructures. The semiconductor structure further includes a first contact plug formed over the first source/drain structure and a second contact plug formed over the second source/drain structure. In addition, a bottom portion of the first contact plug is lower than a bottom portion of the first nanostructures, and a bottom portion of the second contact plug is higher than a top portion of the second nanostructures. 1. A semiconductor structure , comprising:a substrate;first nanostructures and second nanostructures formed over the substrate;a first source/drain structure formed adjacent to the first nanostructures;a second source/drain structure formed adjacent to the second nanostructures;a first contact plug formed over the first source/drain structure;a second contact plug formed over the second source/drain structure,wherein a bottom portion of the first contact plug is lower than a bottom portion of the first nanostructures, and a bottom portion of the second contact plug is higher than a top portion of the second nanostructures.2. The semiconductor structure as claimed in claim 1 , wherein the first source/drain structure covers sidewalls of the first nanostructures and extends between neighboring first nanostructures.3. The semiconductor structure as claimed in claim 1 , wherein the second source/drain structure surrounds portions of the second nanostructures.4. The semiconductor structure as claimed in claim 1 , further comprising:a first gate structure surrounding the first nanostructures; anda second gate structure surrounding the second nanostructures,wherein a bottom surface ...

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Номер записи: 41
12-03-2020 дата публикации

GATE-ALL-AROUND STRUCTURE AND MANUFACTURING METHOD FOR THE SAME

Номер: US20200083339A1
Автор: CHEN I-Sheng, Chen Tzu-Chiang, CHENG Chao-Ching, YANG Yu-Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A gate-all-around structure including a first transistor is provided. The first transistor includes a semiconductor substrate having a top surface, and a first nanostructure over the top surface of the semiconductor substrate and between a first source and a first drain. The first transistor also includes a first gate structure around the first nanostructure, and an inner spacer between the first gate structure and the first source, wherein an interface between the inner spacer and the first gate structure is non-flat. The first transistor includes an isolation layer between the top surface of the semiconductor substrate and the first source and the first drain. 1. A gate-all-around structure , comprising: a semiconductor substrate having a top surface;', 'a first nanostructure over the top surface of the semiconductor substrate and between a first source and a first drain;', 'a first gate structure around the first nanostructure;', 'an inner spacer between the first gate structure and the first source, wherein an interface between the inner spacer and the first gate structure is non-flat; and', 'an isolation layer between the top surface of the semiconductor substrate and the first source and the first drain., 'a first transistor, comprising2. The structure of claim 1 , wherein the isolation layer is in contact with the first nanostructure.3. The structure of claim 1 , further comprising:an isolation structure formed over the semiconductor substrate; anda first fin extended above an isolation structure, wherein the first nanostructure is directly over the first fin, and the isolation layer is in direct contact with a top surface of the first fin.4. The structure of claim 1 , wherein the isolation layer is in contact with the first source and the first drain.5. The structure of claim 4 , wherein the isolation layer is in contact with the inner spacer.6. The structure of claim 1 , further comprising: 'a second nanostructure over the top surface of the substrate and ...

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Номер записи: 42
25-03-2021 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20210091229A1
Автор: Chen Tzu-Chiang, CHENG Chao-Ching, CHIANG Hung-Li, LU Chun-Chieh
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A semiconductor device includes a substrate, a first poly-material pattern, a first conductive element, a first semiconductor layer, and a first gate structure. The first poly-material pattern is over and protrudes outward from the substrate, wherein the first poly-material pattern includes a first active portion and a first poly-material portion joined to the first active portion. The first conductive element is over the substrate, wherein the first conductive element includes the first poly-material portion and a first metallic conductive portion covering at least one of a top surface and a sidewall of the first poly-material portion. The first semiconductor layer is over the substrate and covers the first active portion of the first poly-material pattern and the first conductive element. The first gate structure is over the first semiconductor layer located within the first active portion. 1. A semiconductor device , comprising:a substrate;a first poly-material pattern, over and protruding outward from the substrate, wherein the first poly-material pattern comprises a first active portion and a first poly-material portion joined to the first active portion;a first conductive element, over the substrate, wherein the first conductive element comprises the first poly-material portion and a first metallic conductive portion covering the first poly-material portion;a first semiconductor layer, over the substrate and covering the first active portion of the first poly-material pattern and the first conductive element; anda first gate structure, over a portion of the first semiconductor layer located within the first active portion.2. The semiconductor device of claim 1 , wherein a material of the first poly-material portion comprises a polysilicon material claim 1 , a poly-germanium material claim 1 , or a poly-silicon-germanium material claim 1 , and a material of the first metallic conductive portion comprises a metal or a metal silicide claim 1 , andthe first ...

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Номер записи: 43
05-05-2022 дата публикации

Nano Transistors with Source/Drain Having Side Contacts to 2-D Material

Номер: US20220140098A1
Автор: Cai Jin, Chen Tzu-Chiang, CHENG Chao-Ching, CHIANG Hung-Li, Hung Yi-Tse, Li Lain-Jong
Принадлежит:

A method includes forming a first sacrificial layer over a substrate, and forming a sandwich structure over the first sacrificial layer. The sandwich structure includes a first isolation layer, a two-dimensional material over the first isolation layer, and a second isolation layer over the two-dimensional material. The method further includes forming a second sacrificial layer over the sandwich structure, forming a first source/drain region and a second source/drain region on opposing ends of, and contacting sidewalls of, the two-dimensional material, removing the first sacrificial layer and the second sacrificial layer to generate spaces, and forming a gate stack filling the spaces.

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Номер записи: 44
07-04-2016 дата публикации

Methods of Forming Semiconductor Devices and Structures Thereof

Номер: US20160099244A1
Автор: Chen Tzu-Chiang, Ho Chia-Cheng, Lai Wei-Jen, LEE Tsung-Lin, YEH Chih Chieh
Принадлежит:

Methods of forming semiconductor devices and structures thereof are disclosed. In some embodiments, a semiconductor device includes a substrate that includes fins. Gates are disposed over the fins, the gates being substantially perpendicular to the fins. A source/drain region is disposed on each of fins between two of the gates. A contact is coupled to the source/drain region between the two of the gates. The source/drain region comprises a first width, and the contact comprises a second width. The second width is substantially the same as the first width. 15.-. (canceled)6. A method of forming a semiconductor device , the method comprising:forming a sacrificial material over a substrate, the sacrificial material comprising a nitride;patterning the sacrificial material with a pattern to form a plurality of dummy gates;recessing a top portion of the substrate;epitaxially growing a material over the recessed top portion of the substrate, the epitaxially grown material contacting a first sidewall of a first dummy gate of the plurality of dummy gates and a second sidewall of a second dummy gate of the plurality of dummy gates;forming an insulating material over the sacrificial material and the epitaxially grown material;removing the insulating material from over the sacrificial material;removing the sacrificial material;forming a gate dielectric over the substrate and the insulating material;forming a gate material over the gate dielectric;removing the gate material and the gate dielectric from over a top surface of the insulating material;removing the insulating material; andforming a contact in spaces where the insulating material was removed.7. The method according to claim 6 , wherein forming the sacrificial material comprises forming silicon nitride.8. The method according to claim 6 , wherein the substrate comprises a plurality of fins claim 6 , wherein forming the sacrificial material comprises forming the sacrificial material over the plurality of fins of the ...

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Номер записи: 45
19-03-2020 дата публикации

STRUCTURE AND FORMATION METHOD OF HYBRID SEMICONDUCTOR DEVICE

Номер: US20200091151A1
Автор: CHEN I-Sheng, Chen Tzu-Chiang, CHIANG Hung-Li
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A structure and a formation method of hybrid semiconductor devices are provided. The structure includes a substrate and a fin structure over the substrate. The fin structure has a channel height. The structure also includes a stack of nanostructures over the substrate. The channel height is greater than a lateral distance between the fin structure and the stack of the nanostructures. The structure further includes a gate stack over the nanostructures. The nanostructures are separated from each other by portions of the gate stack. 1. A hybrid semiconductor device structure , comprising:a substrate;a fin structure over the substrate, wherein the fin structure has a channel height;a stack of nanostructures over the substrate, wherein the channel height is greater than a lateral distance between the fin structure and the stack of the nanostructures; anda gate stack over the nanostructures, wherein the nanostructures are separated from each other by portions of the gate stack.2. The structure of claim 1 , wherein the stack of the nanostructures has a second channel height substantially equal to the channel height of the fin structure.3. The structure of claim 1 , wherein the fin structure is a portion of a p-type transistor claim 1 , and the stack of the nanostructures is a portion of an n-type transistor.4. The structure of claim 3 , wherein a width of the fin structure is smaller than a width of one of the nanostructures.5. The structure of claim 1 , wherein the fin structure and the substrate are made of different materials.6. The structure of claim 5 , wherein the fin structure is made of SiGe claim 5 , X being less than 0.6.7. The structure of claim 1 , wherein the channel height of the fin structure is greater than 2 times of the lateral distance.8. A method for forming a hybrid semiconductor device structure claim 1 , comprising:providing a substrate having a first region and a second region;epitaxially forming alternating stacked films over the substrate;forming ...

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Номер записи: 46
28-03-2019 дата публикации

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

Номер: US20190097053A1
Автор: Chen Tzu-Chiang, CHENG Chao-Ching, Chiu Jung-Piao, HSU Chen-Feng, YANG Yu-Lin
Принадлежит:

A semiconductor structure includes a substrate, a first fin structure disposed over the substrate, a second fin structure disposed over the substrate, and an isolation structure disposed between the first fin structure and the second fin structure and electrically isolating the first fin structure from the second fin structure. The isolation structure includes a first thickness, a second thickness and a third thickness different from each other. 1. A semiconductor structure comprising:a substrate;a semiconductor layer disposed over a portion of the substrate;a first fin structure disposed over the semiconductor layer and in contact with the semiconductor layer;a second fin structure disposed over the substrate and in contact with the substrate; andan isolation structure disposed between the first fin structure and the second fin structure and electrically isolating the first fin structure from the second fin structure, wherein the isolation structure comprises a first thickness measured from a top surface to a first bottom surface, a second thickness measured from the top surface to a second bottom surface and a third thickness measured from the top surface to a third bottom surface, wherein the first thickness, the second thickness and the third thickness are different from each other, and the first bottom surface, the second bottom surface and the third bottom surface are at different levels.2. The semiconductor structure of claim 1 , wherein the first fin structure comprises a first conductivity type and the second fin structure comprises a second conductivity type different from the first conductivity type.3. The semiconductor structure of claim 1 , wherein the isolation structure comprises a first portion adjacent to the first fin structure claim 1 , a second portion adjacent to the second fin structure and a third portion sandwiched between the first portion and the second portion.4. The semiconductor structure of claim 3 , wherein the first portion comprises ...

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Номер записи: 47
04-04-2019 дата публикации

SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURING THEREOF

Номер: US20190103267A1
Автор: CHEN I-Sheng, Chen Tzu-Chiang, WU Cheng-Hsien
Принадлежит:

A semiconductor substrate includes a first material layer made of a first material and including a plurality of protrusions, and a second material layer made of a second material different from the first material, filling spaces between the plurality of protrusions, and covering the plurality of protrusions. Each of the protrusions includes a tip and a plurality of facets converging at the tip, and adjacent facets of adjacent protrusions are in contact with each other, 1. A semiconductor substrate , comprising:a first material layer made of a first material and including a plurality of protrusions, wherein each of the protrusions includes a tip and a plurality of facets converging at the tip, and adjacent facets of adjacent protrusions are in contact with each other; anda second material layer made of a second material different from the first material, filling spaces between the plurality of protrusions, and covering the plurality of protrusions.2. The semiconductor substrate of claim 1 , wherein the second material layer is in direct contact with the plurality of facets of the plurality of protrusions.3. The semiconductor substrate of claim 1 , wherein:the first material is crystal silicon,each facet is a {111} plane of the crystal silicon, andthe second material is one of germanium, silicon germanium, gallium arsenide, aluminum antimonide, indium aluminum antimonide, indium antimonide, indium arsenide, indium phosphide, and gallium nitride.4. The semiconductor substrate of claim 3 , wherein each protrusion has a pyramid shape.5. The semiconductor substrate of claim 1 , wherein:the plurality of protrusions are arranged in an array in a first direction and in a second direction perpendicular to the first direction, anda pitch of the plurality of protrusions in the first direction and in the second direction is from 50 nm to 1000 nm.6. The semiconductor substrate of claim 1 , wherein:the first material layer is a (001) silicon wafer having the plurality of ...

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Номер записи: 48
04-04-2019 дата публикации

Gate Stacks for Stack-Fin Channel I/O Devices and Nanowire Channel Core Devices

Номер: US20190103472A1
Автор: CHEN I-Sheng, Chen Tzu-Chiang, CHENG Chao-Ching, YEH Chih Chieh, Yu Shao-Ming, YUN Wei-Sheng
Принадлежит:

A semiconductor device includes a substrate; an I/O device over the substrate; and a core device over the substrate. The I/O device includes a first gate structure having an interfacial layer; a first high-k dielectric stack over the interfacial layer; and a conductive layer over and in physical contact with the first high-k dielectric stack. The core device includes a second gate structure having the interfacial layer; a second high-k dielectric stack over the interfacial layer; and the conductive layer over and in physical contact with the second high-k dielectric stack. The first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer. 1. A semiconductor device , comprising:a substrate;an I/O device over the substrate; anda core device over the substrate, an interfacial layer;', 'a first high-k dielectric stack over the interfacial layer; and', 'a conductive layer over and in physical contact with the first high-k dielectric stack,, 'wherein the I/O device includes a first gate structure having the interfacial layer;', 'a second high-k dielectric stack over the interfacial layer; and', 'the conductive layer over and in physical contact with the second high-k dielectric stack, and, 'wherein the core device includes a second gate structure havingwherein the first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer.2. The semiconductor device of claim 1 , wherein the interfacial layer includes silicon dioxide (SiO) having a thickness ranging from 8 to 12 angstroms.3. The semiconductor device of claim 1 , wherein the first high-k dielectric stack is thicker than the second high-k dielectric stack by 5 to 20 angstroms.4. The semiconductor device of claim 1 , wherein the third dielectric layer has a dielectric constant greater than that of silicon dioxide (SiO) and lower than that of the second high-k dielectric stack.5. The semiconductor device of claim 1 , wherein the second high-k ...

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Номер записи: 49
02-06-2022 дата публикации

FeFET OF 3D STRUCTURE FOR CAPACITANCE MATCHING

Номер: US20220173250A1
Автор: CHANG Chih-Sheng, Chen Tzu-Chiang, CHIANG Hung-Li
Принадлежит:

An MFMIS-FET includes a MOSFET having a three-dimensional structure that allows the MOSFET to have an effective area that is greater than the footprint of the MFM or the MOSFET. In some embodiment, the gate electrode of the MOSFET and the bottom electrode of the MFM are united. In some, they have equal areas. In some embodiments, the MFM and the MOSFET have nearly equal footprints. In some embodiments, the effective area of the MOSFET is much greater than the effective area of the MFM. These structures reduce the capacitance ratio between the MFM structure and the MOSFET without reducing the area of the MFM structure in a way that would decrease drain current. 1. A method of manufacturing an integrated circuit (IC) comprising a MFMIS-FET , the method comprising:forming a semiconductor fin over a substrate;forming a dummy gate stack over the semiconductor fin;patterning the dummy gate stack to define a dummy gate;forming a sidewall spacer around the dummy gate; andreplacing the dummy gate with a MFMIS-FET comprising a high-κ dielectric, a metal gate, a ferroelectric layer and a top electrode layer.2. The method of claim 1 , wherein replacing the dummy gate with a MFMIS-FET comprising a high-κ dielectric claim 1 , a metal gate claim 1 , a ferroelectric layer and a top electrode layer comprises:replacing the dummy gate with a high-κ dielectric and a metal gate;recessing the metal gate below a height of the sidewall spacer to form a recess; andforming a ferroelectric layer and a top electrode layer within the recess.3. The method of claim 1 , wherein the dummy gate is formed over a plurality of semiconductor fins.4. The method of claim 1 , further comprising:etching the top electrode layer below a height of the sidewall spacer to form a second recess; andfilling the second recess to form an etch stop layer over the top electrode layer.5. The method of claim 1 , further comprising:before replacing the dummy gate, filling a space around the sidewall spacer with an ...

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Номер записи: 50
11-04-2019 дата публикации

Gate Stacks for Stack-Fin Channel I/O Devices and Nanowire Channel Core Devices

Номер: US20190109204A1
Автор: CHEN I-Sheng, Chen Tzu-Chiang, CHENG Chao-Ching, YEH Chih Chieh, Yu Shao-Ming, YUN Wei-Sheng
Принадлежит:

A method includes providing a substrate; forming a first structure over the substrate, the first structure including a first gate trench and a first channel exposed in the first gate trench; forming a second structure over the substrate, the second structure including a second gate trench and a second channel exposed in the second gate trench; depositing a gate dielectric layer covering surfaces of the first and second channels exposed in the respective first and second gate trenches; recessing the gate dielectric layer in the second gate trench to be lower than the gate dielectric layer in the first gate trench; and forming a gate electrode layer over the gate dielectric layer in the first and second gate trenches. 1. A method , comprising:providing a substrate;forming a first structure over the substrate, the first structure including a first gate trench and a first channel exposed in the first gate trench;forming a second structure over the substrate, the second structure including a second gate trench and a second channel exposed in the second gate trench;depositing a gate dielectric layer covering surfaces of the first and second channels exposed in the respective first and second gate trenches;recessing the gate dielectric layer in the second gate trench to be lower than the gate dielectric layer in the first gate trench; andforming a gate electrode layer over the gate dielectric layer in the first and second gate trenches.2. The method of claim 1 , wherein the depositing of the gate dielectric layer includes depositing a first material layer and a second material layer over the first material layer claim 1 , the first and second material layers including different material compositions.3. The method of claim 2 , wherein the recessing of the gate dielectric layer includes selectively etching the second material layer.4. The method of claim 2 , wherein the second material layer has a dielectric constant lower than that of the first material layer.5. The method ...

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Номер записи: 51
02-04-2020 дата публикации

Semiconductor device and method for manufacturing the same

Номер: US20200105624A1
Автор: Cheng-Hsien Wu, Chih-Chieh Yeh, Chih-Sheng Chang, I-Sheng Chen, Tzu-Chiang CHEN
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device includes a first source/drain feature adjoining first nanostructures, and a first multilayer work function structure surrounding the first nanostructures. The first multilayer work function structure includes a first middle dielectric layer around the first nanostructures and a first metal layer around and in contact with the first middle dielectric layer. The semiconductor device also includes a second source/drain feature adjoining second nanostructures, and a second multilayer work function structure surrounding the second nanostructures. The second multilayer work function structure includes a second middle dielectric layer around the second nanostructures and a second metal layer around and in contact with the second middle dielectric layer. The first middle dielectric layer and the second middle dielectric layer are made of dielectric materials. The second metal layer and the first metal layer are made of the same metal material.

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Номер записи: 52
04-05-2017 дата публикации

Field-Effect Transistor With Dual Vertical Gates

Номер: US20170125585A1
Автор: Chen Tzu-Chiang, CHIANG Hung-Li, PENG Cheng-Yi, YEH Chih Chieh, Yeo Yee-Chia
Принадлежит:

A semiconductor device includes an n-type vertical field-effect transistor (FET) that includes: a first source/drain feature disposed in a substrate; a first vertical bar structure that includes a first sidewall and a second sidewall disposed over the substrate; a gate disposed along the first sidewall of the first vertical bar structure; a second vertical bar structure electrically coupled to the first vertical bar structure; and a second source/drain feature disposed over the first vertical bar structure; and a p-type FET that includes; a third source/drain feature disposed in the substrate; a third vertical bar structure that includes a third sidewall and a fourth sidewall disposed over the substrate; the gate disposed along the third sidewall of the third vertical bar structure; a fourth vertical bar structure electrically coupled to the third vertical bar structure; and a fourth source/drain feature disposed over the third vertical bar structure. 1. A semiconductor device comprising:a first vertical bar structure disposed over a substrate, wherein the first vertical bar structure includes a first sidewall and an opposing second sidewall;a first gate feature disposed along the first sidewall of the first vertical bar structure such that the first gate feature is electrically coupled to the first vertical bar structure;a second vertical bar structure disposed over the substrate, wherein the second vertical bar structure is electrically coupled to the first vertical bar structure and serves as a second gate feature;a first source/drain feature disposed in the substrate below the first vertical bar structure; anda second source/drain feature disposed over the first vertical bar structure.2. The semiconductor device of claim 1 , wherein the second vertical bar structure is positioned opposite the first vertical bar structure from the first gate feature at a distance.3. The semiconductor device of claim 2 , wherein the distance is less than 25 nanometers.4. The ...

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Номер записи: 53
25-08-2022 дата публикации

READ METHOD, WRITE METHOD AND MEMORY CIRCUIT USING THE SAME

Номер: US20220270682A1
Автор: Chen Tzu-Chiang, CHIANG Hung-Li, DIAZ Carlos H., Wang Yih
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A read method and a write method for a memory circuit are provided, wherein the memory circuit includes a memory cell and a selector electrically coupled to the memory cell. The read method includes applying a first voltage to the selector, wherein a first voltage level of the first voltage is larger than a voltage threshold corresponding to the selector; and applying, after the applying of the first voltage, a second voltage to the selector to sense one or more bit values stored in the memory cell, wherein a second voltage level of the second voltage is constant and smaller than the voltage threshold, wherein a first duration of the applying of the first voltage is smaller than a second duration of the applying of the second voltage, wherein the second voltage is applied following the end of the first duration. 1. A read method for a memory circuit , wherein the memory circuit comprises a memory cell and a selector electrically coupled to the memory cell , the method comprising:applying a first voltage to the selector, wherein a first voltage level of the first voltage is larger than a voltage threshold corresponding to the selector; andapplying, after the applying of the first voltage, a read current to the selector to sense one or more bit values stored in the memory cell, wherein a read current level of the read current is constant and greater than a preset current level threshold,wherein a first duration of the applying of the first voltage is smaller than a second duration of the applying of the read current,wherein the read current is applied following an end of the first duration.2. The read method of claim 1 , wherein the first voltage is configured to turn on the selector claim 1 ,wherein in response to the selector is turned on by the applied first voltage, a snapback current corresponding to the first voltage is generated according to a snapback voltage corresponding to the first voltage, wherein a snapback current level of the snapback current is ...

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Номер записи: 54
25-04-2019 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Номер: US20190123163A1
Автор: Chen Tzu-Chiang, CHENG Chao-Ching, Huang Chao-Hsien, Lee Tung Ying, YANG Yu-Lin, Yu Shao-Ming
Принадлежит:

In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. A first insulating layer is formed, in the source/drain space, at least on etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space, thereby forming air gaps between the source/drain epitaxial layer and the first semiconductor layers. 1. A semiconductor device , comprising:first semiconductor wires disposed over a substrate;a first source/drain region in contact with the first semiconductor wires;a gate dielectric layer disposed on and wrapping around each channel region of the first semiconductor wires;a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region;first insulating spacers disposed in spaces, respectively, the spaces being defined by adjacent first semiconductor wires, the gate electrode layer and the first source/drain region; andair gaps disposed in the spaces, respectively.2. The semiconductor device of claim 1 , further comprising second insulating spacers disposed in the spaces claim 1 , respectively.3. The semiconductor device of claim 2 , wherein the air gaps are in contact with the first source/drain region.4. The semiconductor device of claim 2 , wherein the second insulating spacers are made of a low-k dielectric material.5. The semiconductor device of claim 4 , wherein the first insulating spacers are made of at least one selected from the group consisting of SiOand SiN.6. The semiconductor device of claim 1 , wherein each of the first insulating spacers has a V-shape cross section.7. The ...

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Номер записи: 55
25-04-2019 дата публикации

MULTI-GATE SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

Номер: US20190123189A1
Автор: CHEN I-Sheng, Chen Tzu-Chiang, DIAZ Carlos H., WU Cheng-Hsien, Yeh Ling-Yen
Принадлежит:

A multi-gate semiconductor device includes a substrate, a stacked wire structure disposed over the substrate, a gate over the stacked wire structure, and at least a first spacer disposed over two sidewalls of the gate. The gate further includes a gate conductive structure wrapping the stacked wire structure and a gate dielectric layer sandwiched between the gate conductive structure and the stacked wire structure. Further, sidewalls of the gate conductive structure are in contact with the first spacer. 1. A multi-gate semiconductor device comprising:a substrate;a stacked wire structure disposed over the substrate; a gate conductive structure wrapping the stacked wire structure; and', 'a gate dielectric layer sandwiched between the gate conductive structure and the stacked wire structure;, 'a gate over the stacked wire structure, the gate comprisingat least a first spacer disposed over two sidewalls of the gate, wherein sidewalls of the gate conductive structure are in contact with the first spacer; anda second spacer, wherein the first spacer is sandwiched between the second spacer and the sidewall of the gate conductive structure, and the second spacer comprises an air gap.2. The multi-gate semiconductor device of claim 1 , wherein the first spacer comprises a conductive material.36-. (canceled)7. The multi-gate semiconductor device of claim 1 , wherein the gate conductive structure comprises at least a barrier metal layer claim 1 , a work function metal layer claim 1 , and a gap-filling metal layer.8. The multi-gate semiconductor device of claim 7 , wherein the barrier metal layer is in contact with the first spacer.9. (canceled)1020-. (canceled)21. The multi-gate semiconductor device of claim 2 , wherein the first spacer is separated from the stacked wire structure by the gate dielectric layer.22. (canceled)23. A multi-gate semiconductor device comprising:a substrate;a stacked wire structure disposed over the substrate; a gate conductive structure wrapping the ...

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Номер записи: 56
16-04-2020 дата публикации

Gate Stacks for Stack-Fin Channel I/O Devices and Nanowire Channel Core Devices

Номер: US20200119155A1
Автор: CHEN I-Sheng, Chen Tzu-Chiang, CHENG Chao-Ching, YEH Chih Chieh, Yu Shao-Ming, YUN Wei-Sheng
Принадлежит:

A semiconductor device includes a substrate having an I/O region and a core region; a first transistor in the I/O region; and a second transistor in the core region, wherein the first transistor includes a first gate structure having: an interfacial layer; a first high-k region over the interfacial layer; and a conductive layer over the first high-k region, wherein the second transistor includes a second gate structure having: the interfacial layer; a second high-k region over the interfacial layer; and the conductive layer over the second high-k region, and where in the first high-k region is thicker than the second high-k region. 1. A semiconductor device , comprising:a substrate having an I/O region and a core region;a first transistor in the I/O region; anda second transistor in the core region, an interfacial layer;', 'a first high-k region over the interfacial layer; and', 'a conductive layer over the first high-k region,, 'wherein the first transistor includes a first gate structure having the interfacial layer;', 'a second high-k region over the interfacial layer; and', 'the conductive layer over the second high-k region, and, 'wherein the second transistor includes a second gate structure havingwhere in the first high-k region is thicker than the second high-k region.2. The semiconductor device of claim 1 , wherein the first high-k region is thicker than the second high-k region by 5 to 20 angstroms.3. The semiconductor device of claim 1 , wherein the first high-k region and the second high-k region have a substantially same dielectric constant.4. The semiconductor device of claim 1 , wherein the first high-k region includes at least one high-k material that is also included in the second high-k region.5. The semiconductor device of claim 4 , wherein the at least one high-k material includes hafnium oxide.6. The semiconductor device of claim 4 , wherein the at least one high-k material includes hafnium silicon oxide and hafnium oxide.7. The semiconductor ...

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Номер записи: 57
27-05-2021 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Номер: US20210159124A1
Автор: CHEN I-Sheng, Chen Tzu-Chiang, CHENG Chao-Ching, CHIANG Hung-Li
Принадлежит:

In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers containing Ge and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A Ge concentration in the first semiconductor layers is increased. A sacrificial gate structure is formed over the fin structure. A source/drain epitaxial layer is formed over a source/drain region of the fin structure. The sacrificial gate structure is removed. The second semiconductor layers in a channel region are removed, thereby releasing the first semiconductor layers in which the Ge concentration is increased. A gate structure is formed around the first semiconductor layers in which the Ge concentration is increased. 1. A semiconductor device , comprising:semiconductor wires vertically arranged, each of which has a channel region;a source/drain epitaxial layer connected to the semiconductor wires; anda gate structure formed around the semiconductor wires, wherein:{'sub': 1-x', 'x, 'the semiconductor wires are made of SiGe, where 0.45≤x≤0.55.'}2. The semiconductor device of claim 1 , wherein a width of the semiconductor wires is smaller than a thickness of the semiconductor wires.3. The semiconductor device of claim 1 , wherein a thickness of the semiconductor wires is greater than a space between adjacent semiconductor wires.4. The semiconductor device of claim 1 , wherein a cross section of the semiconductor wires has a dog-bone shape or a thread-spool shape.5. The semiconductor device of claim 1 , wherein the semiconductor device is a p-channel field effect transistor.6. The semiconductor device of claim 1 , wherein the source/drain epitaxial layer wraps around source/drain regions of the semiconductor wires.7. The semiconductor device of claim 1 , further comprising dielectric inner spacers disposed between the gate structure and the source/drain epitaxial layer.8. The semiconductor device of claim 7 , further comprising gate sidewall spacers ...

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Номер записи: 58
02-05-2019 дата публикации

GATE-ALL-AROUND STRUCTURE AND MANUFACTURING METHOD FOR THE SAME

Номер: US20190131415A1
Автор: CHEN I-Sheng, Chen Tzu-Chiang, CHENG Chao-Ching, YANG Yu-Lin
Принадлежит:

Present disclosure provides gate-all-around structure including a first transistor. The first transistor includes a semiconductor substrate having a top surface, a first nanowire over the top surface of the semiconductor substrate and between a first source and a first drain, a first gate structure around the first nanowire, an inner spacer between the first gate structure and the first source and first drain, and an isolation layer between the top surface of the semiconductor substrate and the first source and the first drain. Present disclosure also provides a method for manufacturing the gate-all-around structure described herein. 1. A gate-all-around structure , comprising: a semiconductor substrate having a top surface;', 'a first nanowire over the top surface of the semiconductor substrate and between a first source and a first drain;', 'a first gate structure around the first nanowire;', 'an inner spacer between the first gate structure and the first source; and', 'an isolation layer between the top surface of the semiconductor substrate and the first source and the first drain,', 'wherein the inner spacer and the isolation layer are composed of same material., 'a first transistor, comprising2. The structure of claim 1 , wherein the isolation layer is in contact with the first nanowire.3. The structure of claim 2 , wherein a distance between the top surface of the semiconductor substrate and a bottom of the first nanowire is greater than a thickness of the inner spacer.4. The structure of claim 2 , wherein the first nanowire comprises silicon germanium nanowire.5. The structure of claim 1 , wherein the isolation layer is in contact with the first source and the first drain.6. The structure of claim 5 , wherein the isolation layer is in contact with the inner spacer.7. The structure of claim 5 , wherein a distance between the top surface of the semiconductor substrate and a bottom of the first channel is greater than two times of a thickness of the inner ...

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Номер записи: 59
02-05-2019 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Номер: US20190131431A1
Автор: Chen Tzu-Chiang, CHENG Chao-Ching, HSU Chen-Feng, Lee Tung Ying, YANG Yu-Lin, YUN Wei-Sheng
Принадлежит:

In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched. 1. A method of manufacturing a semiconductor device , comprising:forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked over a bottom fin structure;forming a sacrificial gate structure over the fin structure;etching a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a source/drain space;laterally etching the first semiconductor layers through the source/drain space;forming an inner spacer made of a dielectric material on an end of each of the etched first semiconductor layers; andforming a source/drain epitaxial layer in the source/drain space to cover the inner spacer and to fully fill the source/drain space to be in contact with the bottom fin structure,wherein a lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.2. The method of claim 1 , wherein the lateral end of each of the first semiconductor layers has a (111) facet of a semiconductor crystal.3. The method of claim 1 , wherein the first semiconductor layers are laterally etched by wet ...

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Номер записи: 60
08-09-2022 дата публикации

SEMICONDUCTOR DEVICE, INTEGRATED CIRCUIT AND METHODS OF MANUFACTURING THE SAME

Номер: US20220285345A1
Автор: Chen Tzu-Chiang, CHENG Chao-Ching, CHIANG Hung-Li, Chou Ang-Sheng, Hung Yi-Tse
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A semiconductor device includes a gate layer, a channel material layer, a first dielectric layer and source/drain terminals. The gate layer is disposed over a substrate. The channel material layer is disposed over the gate layer, where a material of the channel material layer includes a first low dimensional material. The first dielectric layer is between the gate layer and the channel material layer. The source/drain terminals are in contact with the channel material layer, where the channel material layer is at least partially disposed between the source/drain terminals and over the gate layer, and the gate layer is disposed between the substrate and the source/drain terminals. 1. A semiconductor device , comprising:a gate layer, disposed over a substrate;a channel material layer, disposed over the gate layer, wherein a material of the channel material layer comprises a first low dimensional material;a first dielectric layer, sandwiched between the gate layer and the channel material layer; andsource/drain terminals, in contact with the channel material layer, wherein the channel material layer is at least partially sandwiched between the source/drain terminals and over the gate layer, and the gate layer is disposed between the substrate and the source/drain terminals.2. The semiconductor device of claim 1 , wherein the source/drain terminals penetrate through the channel material layer and stand on the first dielectric layer claim 1 , and sidewalls of the source/drain terminals are in contact with the channel material layer claim 1 ,wherein along a stacking direction of the gate layer and the substrate, the channel material layer is next to the source/drain terminals and overlapped with the gate layer.3. The semiconductor device of claim 2 , further comprising:a second dielectric layer, wherein the channel material layer is sandwiched between the second dielectric layer and the first dielectric layer, and the source/drain terminals penetrate through the second ...

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Номер записи: 61
08-09-2022 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20220285495A1
Автор: Chen Tzu-Chiang, CHENG Chao-Ching, CHIANG Hung-Li, Chou Ang-Sheng, Hung Yi-Tse
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a heat transfer layer disposed over a substrate, a channel material layer, a gate structure and source and drain terminals. The channel material layer has a first surface and a second surface opposite to the first surface, and the channel material layer is disposed on the heat transfer layer with the first surface in contact with the heat transfer layer. The gate structure is disposed above the channel material layer. The source and drain terminals are in contact with the channel material layer and located at two opposite sides of the gate structure. 1. A semiconductor device , comprising:a first heat transfer layer disposed over a substrate;a channel material layer having a first surface and a second surface opposite to the first surface, wherein the channel material layer is disposed on the first heat transfer layer with the first surface in contact with the first heat transfer layer;a gate structure disposed above the channel material layer; andsource and drain terminals in contact with the channel material layer and located at two opposite sides of the gate structure.2. The semiconductor device of claim 1 , wherein the source and drain terminals are located on the first heat transfer layer and penetrate through the channel material layer.3. The semiconductor device of claim 2 , further comprising a second heat transfer layer disposed on the channel material layer and in contact with the second surface of the channel material layer claim 2 , wherein the source and drain terminals penetrate through the second heat transfer layer and the channel material layer.4. The semiconductor device of claim 1 , wherein the source and drain terminals are located directly on the channel material layer.5. The semiconductor device of claim 4 , further comprising a second heat transfer layer disposed on the channel material layer and in contact with the second surface of the ...

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Номер записи: 62
08-09-2022 дата публикации

RESISTIVE MEMORY DEVICES USING A CARBON-BASED CONDUCTOR LINE AND METHODS FOR FORMING THE SAME

Номер: US20220285612A1
Автор: Chen Tzu-Chiang, CHENG Chao-Ching, CHIANG Hung-Li, Li Lain-Jong
Принадлежит:

An array of rail structures is formed over a substrate. Each rail structure includes at least one bit line. Dielectric isolation structures straddling the array of rail structures are formed. Line trenches are provided between neighboring pairs of the dielectric isolation structures. A layer stack of a resistive memory material layer and a selector material layer is formed within each of the line trenches. A word line is formed on each of the layer stacks within unfilled volumes of the line trenches. The word lines or at least a subset of the bit lines includes a carbon-based conductive material containing hybridized carbon atoms in a hexagonal arrangement to provide a low resistivity conductive structure. An array of resistive memory elements is formed over the substrate. A plurality of arrays of resistive memory elements may be formed at different levels over the substrate. 2. The method of claim 1 , wherein the carbon-based conductive material is selected from carbon nanotubes and graphene in sheets or nanoribbons.3. The method of claim 1 , wherein each of the resistive memory material layer and the selector material layer is formed by a conformal deposition process as a respective continuous material layer extending continuously over each rail structure within the array of rail structures and into each of the line trenches.4. The method of claim 1 , wherein each rail structure within the array of rail structures comprises a respective inter-bit-line dielectric rail located between the respective lower bit line and the respective upper bit line.5. The method of claim 1 , wherein the at least one resistive memory array comprises a plurality of resistive memory arrays that are sequentially formed at different levels of metal interconnect structures over the substrate.7. The method of claim 6 , wherein the carbon-based conductive material is selected from carbon nanotubes and graphene in sheets or nanoribbons.8. The method of claim 6 , wherein each layer stack ...

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Номер записи: 63
09-05-2019 дата публикации

Semiconductor device and method for manufacturing the same

Номер: US20190139838A1
Автор: Cheng-Hsien Wu, Chih-Chieh Yeh, Chih-Sheng Chang, I-Sheng Chen, Tzu-Chiang CHEN
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device includes an n-channel, a p-channel, a first gate dielectric layer, a second gate dielectric layer, a second dielectric sheath layer, and a metal gate. The first gate dielectric layer is around the n-channel. The first dielectric sheath layer is around the first gate dielectric layer. The second gate dielectric layer is around the p-channel. The second dielectric sheath layer is around the second gate dielectric layer, in which the first dielectric sheath layer and the second dielectric sheath layer comprise different materials. The metal gate electrode is around the first dielectric sheath layer and the second dielectric sheath layer.

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Номер записи: 64
30-04-2020 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Номер: US20200135587A1
Автор: Chang Kai-Tai, CHEN I-Sheng, Chen Tzu-Chiang, CHENG Chao-Ching, CHIANG Hung-Li
Принадлежит:

In a method of manufacturing a semiconductor device, a fin structure having a lower fin structure and an upper fin structure disposed over the lower fin structure is formed. The upper fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The first semiconductor layers are partially etched to reduce widths of the first semiconductor layers. An oxide layer is formed over the upper fin structure. A sacrificial gate structure is formed over the upper fin structure with the oxide layer. A source/drain epitaxial layer is formed over a source/drain region of the fin structure. The sacrificial gate structure is removed to form a gate space. The oxide layer is removed to expose the second semiconductor layers in the gate space. A gate structure is formed around the second semiconductor layers in the gate space. 1. A method of manufacturing a semiconductor device , comprising:forming a fin structure having a lower fin structure and an upper fin structure disposed over the lower fin structure, the upper fin structure including first semiconductor layers and second semiconductor layers alternately stacked;partially etching the first semiconductor layers to reduce widths of the first semiconductor layers;forming an oxide layer over the upper fin structure;forming a sacrificial gate structure over the upper fin structure with the oxide layer;forming a source/drain epitaxial layer over a source/drain region of the fin structure;removing the sacrificial gate structure to form a gate space;removing the oxide layer to expose the second semiconductor layers in the gate space; andforming a gate structure around the second semiconductor layers in the gate space.2. The method of claim 1 , wherein the oxide layer is formed by thermal oxidation.3. The method of claim 2 , wherein after the thermal oxidation claim 2 , an annealing operation is performed.4. The method of claim 3 , wherein the annealing operation is performed at 800° C. to 1000° ...

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Номер записи: 65
30-04-2020 дата публикации

Structure and formation method of semiconductor device with hybrid fins

Номер: US20200135729A1
Автор: Hung-Li Chiang, I-Sheng Chen, Jin-Aun Ng, Kuo-Cheng Chiang, Tzu-Chiang CHEN
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and an isolation structure over the semiconductor substrate. The semiconductor device structure also includes a first fin structure over the semiconductor substrate and surrounded by the isolation structure and a stack of nanostructures over the first fin structure. The nanostructures are separated from each other. The semiconductor device structure further includes a second fin structure over the semiconductor substrate. The second fin structure has an embedded portion surrounded by the isolation structure and a protruding portion over the isolation structure. The embedded portion is separated from the protruding portion by a distance.

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Номер записи: 66
30-04-2020 дата публикации

ISOLATION STRUCTURES OF SEMICONDUCTOR DEVICES

Номер: US20200135849A1
Автор: CHEN I-Sheng, Chen Tzu-Chiang, CHENG Chao-Ching, CHIANG Hung-Li
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

The structure of a semiconductor device with isolation structures between FET devices and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure on a substrate and forming polysilicon gate structures with a first threshold voltage on first fin portions of the fin structure. The method further includes forming doped fin regions with dopants of a first type conductivity on second fin portions of the fin structure, doping at least one of the polysilicon gate structures with dopants of a second type conductivity to adjust the first threshold voltage to a greater second threshold voltage, and replacing at least two of the polysilicon gate structures adjacent to the at least one of the polysilicon gate structures with metal gate structures having a third threshold voltage less than the first and second threshold voltages 1. A method of fabricating a semiconductor device , the method comprising:forming a fin structure on a substrate;forming polysilicon gate structures with a first threshold voltage on first fin portions of the fin structure;forming doped fin regions with dopants of a first type conductivity on second fin portions of the fin structure;doping at least one of the polysilicon gate structures with dopants of a second type conductivity to adjust the first threshold voltage to a greater second threshold voltage; andreplacing at least two of the polysilicon gate structures adjacent to the at least one of the polysilicon gate structures with high-k metal gate structures having a third threshold voltage less than the first and second threshold voltages.2. The method of claim 1 , wherein the doping comprises ion implanting the dopants of the second type conductivity into the at least one of the polysilicon gate structures.3. The method of claim 1 , wherein the at least one of polysilicon gate structures is interposed between the at least two of the polysilicon gate structures.4 ...

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Номер записи: 67
10-06-2021 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20210175129A1
Автор: CHANG Chih-Sheng, CHEN I-Sheng, Chen Tzu-Chiang, Chui Chi-On, WU Cheng-Hsien, YEH Chih-Chieh, Yeong Sai-Hooi, Young Bo-Feng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers. 1. A semiconductor device , comprising: a first end portion and a second end portion; and', 'a first middle portion laterally between the first end portion and the second end portion, wherein the first end portion and the second end portion are thicker than the first middle portion;, 'a first set of nanostructures stacked over a substrate in a vertical direction, each of the first set of nanostructures comprisinga first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures; anda gate structure around the first plurality of semiconductor capping layers.2. The semiconductor device as claimed in claim 1 , wherein the first plurality of semiconductor capping layers extends from the first end portions to the second end portions of the first set of nanostructures.3. The semiconductor device as claimed in claim 1 , wherein the first plurality of semiconductor capping layers comprises a first semiconductor capping layer claim 1 , the first semiconductor capping layer comprises a first extending portion claim 1 , a second extending portion claim 1 , and a flat portion laterally between the first extending portion and the second extending portion claim 1 , and the first extending portion and the second extending portion protrude from the flat portion.4. The semiconductor device as claimed in ...

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Номер записи: 68
10-06-2021 дата публикации

Nanowire Stack GAA Device with Inner Spacer and Methods for Producing the Same

Номер: US20210175367A1
Автор: CHEN I-Sheng, Chen Tzu-Chiang, CHENG Chao-Ching, DIAZ Carlos H.
Принадлежит:

A nanowire FET device includes a vertical stack of nanowire strips configured as the semiconductor body. One or more of the top nanowire strips are receded and are shorter than the rest of the nanowire strips stacked lower. Inner spacers are uniformly formed adjacent to the receded nanowire strips and the rest of the nanowire strips. Source/drain structures are formed outside the inner spacers and a gate structure is formed inside the inner spacers, which wraps around the nanowire strips. 1. A method of forming a semiconductor device , the method comprising:forming a first fin structure over a substrate, the first fin structure including alternating layers of a first semiconductor material layer and a second semiconductor material layer;forming a gate structure over the first fin structure;forming a receded strip by removing portions of a topmost layer of the second semiconductor material layer on opposing sides of the gate structure;forming receded sacrificial strips by removing portions of the first semiconductor material layers on opposing sides of the gate structure, the receded sacrificial strips each including recessed edge surfaces;forming an inner spacer adjacent to the recessed edge surfaces of the receded sacrificial strips; andepitaxially growing a source/drain structure adjacent to the inner spacer and remaining portions of the alternating layers of the first semiconductor material layer and the second semiconductor material layer.2. The method of claim 1 , wherein the source/drain structure extends around remaining ones of the second semiconductor material layers.3. The method of claim 1 , wherein after epitaxially growing the source/drain structure a void is interposed between the source/drain structure and at least one of the receded sacrificial strips.4. The method of claim 1 , further comprising:removing the gate structure;removing the receded sacrificial strips in a channel region; andforming a replacement gate structure around remaining ones of ...

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Номер записи: 69
31-05-2018 дата публикации

Method of manufacturing a semiconductor device with multilayered channel structure

Номер: US20180151717A1
Автор: Chao-Ching Cheng, Cheng-Hsien Wu, Chih Chieh Yeh, Hung-Li Chiang, I-Sheng Chen, Jung-Piao Chiu, Tsung-Lin Lee, Tzu-Chiang CHEN, Yu-Lin Yang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device includes a fin field effect transistor (FinFET). The FinFET includes a channel disposed on a fin, a gate disposed over the channel and a source and drain. The channel includes at least two pairs of a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. The first semiconductor layer has a different lattice constant than the second semiconductor layer. A thickness of the first semiconductor layer is three to ten times a thickness of the second semiconductor layer at least in one pair.

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Номер записи: 70
16-05-2019 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20190148515A1
Автор: Chen Tzu-Chiang, CHENG Chao-Ching, HSU Chen-Feng, YANG Yu-Lin, YUN Wei-Sheng
Принадлежит:

A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer. 1. A method of manufacturing a semiconductor device , comprising:forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked;forming a sacrificial gate structure over the fin structure;anisotropically etching a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a source/drain space;forming a source/drain epitaxial layer in the source/drain space;removing the sacrificial gate structure, thereby exposing a part of the fin structure;removing the first semiconductor layers from the exposed fin structure;forming recesses toward the source/drain epitaxial layer;forming inner spacers in the recesses; andforming a gate dielectric layer covering the inner spacers and forming a gate electrode layer around the second semiconductor layer, wherein the gate electrode layer is isolated from the source/drain epitaxial layer by the inner spacer and the gate dielectric layer.2. The method of claim 1 , wherein the recesses are formed in a region between the gate electrode layer and the source/drain epitaxial layer.3. The method of claim 1 , wherein the removing the first semiconductor layers is carried out by selective wet etching.4. The method of claim 3 , wherein facets of the recesses are selectively obtained by the selective etching the first semiconductor layers.5. The method of claim 1 , wherein the inner spacer is formed by:forming a ...

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Номер записи: 71
17-06-2021 дата публикации

RESISTIVE MEMORY DEVICES USING A CARBON-BASED CONDUCTOR LINE AND METHODS FOR FORMING THE SAME

Номер: US20210184111A1
Автор: Chen Tzu-Chiang, CHENG Chao-Ching, CHIANG Hung-Li, Li Lain-Jong
Принадлежит:

An array of rail structures is formed over a substrate. Each rail structure includes at least one bit line. Dielectric isolation structures straddling the array of rail structures are formed. Line trenches are provided between neighboring pairs of the dielectric isolation structures. A layer stack of a resistive memory material layer and a selector material layer is formed within each of the line trenches. A word line is formed on each of the layer stacks within unfilled volumes of the line trenches. The word lines or at least a subset of the bit lines includes a carbon-based conductive material containing hybridized carbon atoms in a hexagonal arrangement to provide a low resistivity conductive structure. An array of resistive memory elements is formed over the substrate. A plurality of arrays of resistive memory elements may be formed at different levels over the substrate. 1. A resistive memory device , comprising:an array of rail structures that extend along a first horizontal direction, wherein each of the rail structures comprises at least one bit line;word lines that laterally extend along a second horizontal direction and are laterally spaced apart along the first horizontal direction, wherein each of the word lines includes a respective horizontally-extending portion that overlie the rail structures and a respective row of downward-protruding portions that protrude downward from the respective horizontally-extending portion,wherein a layer stack of a resistive memory material layer and a selector material layer is located between each of the word lines and respective underlying portions of the array of rail structures; andwherein the word lines or at least a subset of the bit lines comprise a carbon-based conductive material containing hybridized carbon atoms in a hexagonal arrangement.2. The resistive memory device of claim 1 , wherein the carbon-based conductive material is selected from carbon nanotubes and graphene in sheets or nanoribbons.3. The ...

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Номер записи: 72
28-08-2014 дата публикации

FinFETs and the Methods for Forming the Same

Номер: US20140239414A1
Автор: Chia-Cheng Ho, Chih-Sheng Chang, Tzu-Chiang CHEN, Yi-Tang LIN
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method includes providing a plurality of semiconductor fins parallel to each other, and includes two edge fins and a center fin between the two edge fins. A middle portion of each of the two edge fins is etched, and the center fin is not etched. A gate dielectric is formed on a top surface and sidewalls of the center fin. A gate electrode is formed over the gate dielectric. The end portions of the two edge fins and end portions of the center fin are recessed. An epitaxy is performed to form an epitaxy region, wherein an epitaxy material grown from spaces left by the end portions of the two edge fins are merged with an epitaxy material grown from a space left by the end portions of the center fin to form the epitaxy region. A source/drain region is formed in the epitaxy region.

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Номер записи: 73
01-07-2021 дата публикации

SEMICONDUCTOR DEVICE STRUCTURE WITH NANOSTRUCTURE AND METHOD FOR FORMING THE SAME

Номер: US20210202731A1
Автор: Chen Tzu-Chiang, CHENG Chao-Ching, CHIANG Hung-Li, Lee Tung-Ying, Lin Yu-Chao
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The semiconductor device structure includes a gate stack over the substrate and surrounding the first nanostructure. The semiconductor device structure includes a first source/drain structure and a second source/drain structure over the substrate. The gate stack is between the first source/drain structure and the second source/drain structure. The semiconductor device structure includes an inner spacer layer covering a sidewall of the first source/drain structure and partially between the gate stack and the first source/drain structure. The first nanostructure passes through the inner spacer layer. The semiconductor device structure includes a dielectric structure over the gate stack and extending into the inner spacer layer. 1. A semiconductor device structure , comprising:a substrate;a first nanostructure over the substrate;a gate stack over the substrate and surrounding the first nanostructure;a first source/drain structure and a second stressor over the substrate, wherein the gate stack is between the first source/drain structure and the second source/drain structure;an inner spacer layer covering a sidewall of the first source/drain structure and partially between the gate stack and the first source/drain structure, wherein the first nanostructure passes through the inner spacer layer; anda dielectric structure over the gate stack and extending into the inner spacer layer.2. The semiconductor device structure as claimed in claim 1 , wherein the first nanostructure is between the first source/drain structure and the second source/drain structure.3. The semiconductor device structure as claimed in claim 1 , wherein the first source/drain structure and the second source/drain structure surround the first nanostructure.4. The semiconductor device structure as claimed in claim 3 , ...

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Номер записи: 74
23-06-2016 дата публикации

SHORT CHANNEL EFFECT SUPPRESSION

Номер: US20160181244A1
Автор: CHANG Chih-Sheng, Chen Tzu-Chiang, CHIANG Hung-Li, Ho Chia-Cheng, Lai Wei-Jen, LEE Tsung-Lin, PENG Cheng-Yi, YANG Yu-Lin, YEH Chih Chieh, Yeo Yee-Chia
Принадлежит:

A method of fabricating a semiconductor device includes forming a plurality of isolation features on a semiconductor substrate, thereby defining a first set of semiconductor features, performing an etching process on the first set of semiconductor features such that larger semiconductor features are etched deeper than smaller semiconductor features, after the etching process, forming anti-punch-through features on surfaces of the exposed features of the first set of semiconductor features, forming a semiconductor layer over the anti-punch-through features, and forming transistors on the semiconductor layer of each of the features of the first set of semiconductor features 1. A method of fabricating a semiconductor device , the method comprising:forming a plurality of isolation features on a semiconductor substrate, thereby defining a first set of semiconductor features;performing an etching process on the first set of semiconductor features such that larger semiconductor features are etched deeper than smaller semiconductor features;after the etching process, forming anti-punch-through features on surfaces of the exposed features of the first set of semiconductor features;forming a semiconductor layer over the anti-punch-through features; andforming transistors on the semiconductor layer of each of the features of the first set of semiconductor features.2. The method of claim 1 , wherein the anti-punch-through features comprise a higher doping concentration than the semiconductor layer.3. The method of claim 1 , wherein forming the semiconductor layer comprises performing an epitaxial growth process to for the semiconductor layer.4. The method of claim 1 , wherein the semiconductor layer comprises silicon germanium at a ratio of silicon to germanium within a range of about 1:0.1-0.9.5. The method of claim 1 , wherein the semiconductor layer is doped with a p-type dopant.6. The method of claim 1 , further comprising:forming a second set of semiconductor features, the ...

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Номер записи: 75
08-07-2021 дата публикации

FeFET OF 3D STRUCTURE FOR CAPACITANCE MATCHING

Номер: US20210210636A1
Автор: CHANG Chih-Sheng, Chen Tzu-Chiang, CHIANG Hung-Li
Принадлежит:

An MFMIS-FET includes a MOSFET having a three-dimensional structure that allows the MOSFET to have an effective area that is greater than the footprint of the MFM or the MOSFET. In some embodiment, the gate electrode of the MOSFET and the bottom electrode of the MFM are united. In some, they have equal areas. In some embodiments, the MFM and the MOSFET have nearly equal footprints. In some embodiments, the effective area of the MOSFET is much greater than the effective area of the MFM. These structures reduce the capacitance ratio between the MFM structure and the MOSFET without reducing the area of the MFM structure in a way that would decrease drain current. 1. An integrated circuit (IC) , comprising:a substrate;a field-effect transistor (FET) comprising a gate electrode and one or more channel regions separated from the gate electrode by an insulator; anda metal-ferroelectric-metal structure (MFM) comprising a top electrode and a bottom electrode separated by a ferroelectric layer;wherein the gate electrode is coupled to or unitary with the bottom electrode;the FET has an effective area related to capacitance of the FET;the FET has a footprint over the substrate; andthe effective area of the FET is greater than the footprint of the FET.2. The IC of claim 1 , wherein:the MFM has an effective area related to capacitance of the MFM;the effective area of the FET is greater than the effective area of the MFM.3. The IC of claim 1 , wherein the gate electrode of the FET is unitary with the bottom electrode of the MFM.4. The IC of claim 1 , wherein:the MFM has a footprint over the substrate;the FET has a footprint over the substrate;the footprint of the MFM is the same as or larger than the footprint of the FET.5. The IC of claim 1 , further comprising a sidewall spacer that surrounds the MFM and the FET.6. The IC of claim 1 , further comprising:a sidewall spacer adjacent the FET;wherein the MFM has a top that is at or below a top of the sidewall spacer.7. The IC of ...

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Номер записи: 76
04-06-2020 дата публикации

SEMICONDUCTOR DEVICE INCLUDING MEMORY CELLS AND METHOD FOR MANUFACTURING THEREOF

Номер: US20200176032A1
Автор: Chen Tzu-Chiang, Chen Yu-Sheng, CHENG Chao-Ching, CHIANG Hung-Li
Принадлежит:

A semiconductor device includes logic circuitry including a transistor disposed over a substrate, multiple layers each including metal wiring layers and an interlayer dielectric layer, respectively, disposed over the logic circuitry, and memory arrays. The multiple layers of metal wiring include, in order closer to the substrate, first, second, third and fourth layers, and the memory arrays include lower multiple layers disposed in the third layer. 1. A semiconductor device , comprising:logic circuitry including a transistor disposed over a substrate;multiple layers each including metal wiring layers and an interlayer dielectric layer, respectively disposed over the logic circuitry; andmemory arrays, wherein:the multiple layers of metal wiring include, in order closer to the substrate, first, second, third and fourth layers, andthe memory arrays include lower multiple layers disposed in the third layer.2. The semiconductor memory device of claim 1 , wherein:the memory arrays include upper multiple layers disposed in the fourth layer.3. The semiconductor memory device of claim 2 , wherein each of the lower multiple layers and the upper multiple layers of the memory arrays includes two memory layers.4. The semiconductor memory device of claim 3 , wherein the two memory layers include two layers of bit lines vertically stacked and word lines crossing the two layers of bit lines.5. The semiconductor memory device of claim 1 , wherein peripheral circuits to operate the memory arrays are disposed below the memory arrays.6. The semiconductor memory device of claim 4 , wherein part of the logic circuitry is disposed below the memory arrays.7. The semiconductor memory device of claim 1 , wherein the memory arrays include phase change memory cells.8. The semiconductor memory device of claim 7 , wherein each of the phase change memory cells includes a phase change memory layer made of one or more selected from the group consisting of Ge claim 7 , Ga claim 7 , Sn and In claim 7 ...

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Номер записи: 77
05-08-2021 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20210242328A1
Автор: Chen Tzu-Chiang, CHENG Chao-Ching, HSU Chen-Feng, YANG Yu-Lin, YUN Wei-Sheng
Принадлежит:

A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer. 1. A semiconductor device , comprising:a plurality of channels made of a semiconductor material disposed over a bottom fin structure;a source/drain epitaxial layer in contact with ends of the plurality of channels; a gate dielectric layer disposed on and wrapping around each of the plurality of channels; and', 'a gate electrode layer disposed on the gate dielectric layer; and, 'a gate structure comprisingdielectric spacers disposed in recesses formed between the source/drain epitaxial layer and the gate structure,wherein an end of each of the dielectric spacers facing the source/drain epitaxial layer is convex toward the source/drain epitaxial layer.2. The semiconductor device of claim 1 , wherein the recesses are formed in a region between the gate electrode layer and the source/drain epitaxial layer.3. The semiconductor device of claim 1 , wherein another end of each of the dielectric spacers facing the gate dielectric layer is concave toward the gate dielectric layer.4. The semiconductor device of claim 1 , wherein the dielectric spacers are in direct contact with the source/drain epitaxial layer.5. The semiconductor device of claim 1 , wherein a semiconductor layer made of a different material than the plurality of channels is disposed between the source/drain epitaxial layer and the end of each of the dielectric spacers.6. The semiconductor device of claim 5 , wherein the plurality of channels are made of Si and the semiconductor layer is ...

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Номер записи: 78
12-08-2021 дата публикации

FORMING SEMICONDUCTOR STRUCTURES WITH TWO-DIMENSIONAL MATERIALS

Номер: US20210249527A1
Автор: Chen Tzu- Chiang, CHENG Chao-Ching, CHIANG Hung-Li, Li Ming-Yang, LU Chun-Chieh
Принадлежит:

A process is provided to fabricate a finFET device having a semiconductor layer of a two-dimensional “2D” semiconductor material. The semiconductor layer of the 2D semiconductor material is a thin film layer formed over a dielectric fin-shaped structure. The 2D semiconductor layer extends over at least three surfaces of the dielectric fin structure, e.g., the upper surface and two sidewall surfaces. A vertical protrusion metal structure, referred to as “metal fin structure”, is formed about an edge of the dielectric fin structure and is used as a seed to grow the 2D semiconductor material. 1. A structure , comprising:a substrate;a first fin structure of a first material over the substrate;a first metal protrusion structure laterally in contact with an edge surface of the first fin structure along a first direction; anda semiconductor layer of a two-dimensional material on the first fin structure, the semiconductor layer being grown using the first metal protrusion structure as a seed.2. The structure of claim 1 , comprising a dielectric layer between the first metal protrusion structure and the substrate.3. The structure of claim 1 , wherein the first metal protrusion structure has a smaller dimension than the first fin structure in the first direction.4. The structure of claim 1 , wherein the semiconductor layer at least partially covers the first metal protrusion structure.5. The structure of claim 1 , wherein the first metal protrusion structure extends beyond the first fin structure in a second direction that is substantially orthogonal to the first direction.6. The structure of claim 1 , wherein the first metal protrusion structure is one or more of tungsten claim 1 , molybdenum claim 1 , or platinum.7. The structure of claim 1 , further comprising a second metal protrusion structure adjacent to a second edge surface of the first fin structure.8. The structure of claim 1 , wherein the semiconductor layer fully covers the first fin structure except for the edge ...

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Номер записи: 79
16-07-2020 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Номер: US20200227534A1
Автор: Chen Tzu-Chiang, CHENG Chao-Ching, Chiang Kuo-Cheng, HSU Chen-Feng, Lee Tung Ying, YANG Yu-Lin, YUN Wei-Sheng
Принадлежит:

In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched. 1. A method of manufacturing a semiconductor device , comprising:forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked;forming a sacrificial gate structure over the fin structure;removing first semiconductor layers from a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a source/drain space, wherein the second semiconductor layers remain in the source/drain space;laterally etching the first semiconductor layers through the source/drain space;forming a first inner spacer made of an oxide material on an end of each of the etched first semiconductor layers by oxidation process;forming a second inner spacer made of a dielectric material over the first inner spacer;forming a source/drain epitaxial layer in the source/drain space and to cover the second inner spacer; andforming a source/drain contact layer in contact with the source/drain epitaxial layer that wraps around the second semiconductor layers.2. The method of claim 1 , wherein an end of the inner spacer facing the end of each of the etched first semiconductor layers has a round ...

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Номер записи: 80
16-07-2020 дата публикации

SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME

Номер: US20200227570A1
Автор: CHEN Hou-Yu, CHEN I-Sheng, Chen Tzu-Chiang, CHENG Chao-Ching, YANG Yu-Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A semiconductor device structure is provided. The semiconductor device structure includes an isolation layer formed over a substrate, and a plurality of nanostructures formed over the isolation layer. The semiconductor device structure includes a gate structure wrapped around the nanostructures, and an S/D structure wrapped around the nanostructures. The semiconductor device structure includes a first oxide layer between the substrate and the S/D structure. The first oxide layer and the isolation layer are made of different materials. The first oxide layer is in direct contact with the isolation layer. 1. A semiconductor device structure , comprising:an isolation layer formed over a substrate;a plurality of nanostructures formed over the isolation layer;a gate structure wrapped around the nanostructures;an S/D structure wrapped around the nanostructures; anda first oxide layer between the substrate and the S/D structure, wherein the first oxide layer and the isolation layer are made of different materials, and the first oxide layer is in direct contact with the isolation layer.2. The semiconductor device structure as claimed in claim 1 , further comprising:an inner spacer between the gate structure and the S/D structure, wherein the inner spacer and the isolation layer are made of the same material.3. The semiconductor device structure as claimed in claim 2 , wherein the inner spacer has a C-shaped structure with a recessed central portion claim 2 , and a second oxide layer is formed in the recessed central portion.4. The semiconductor device structure as claimed in claim 3 , wherein the second oxide layer is in direct contact with the S/D structure.5. The semiconductor device structure as claimed in claim 1 , wherein the first oxide layer is in direct contact with one of the nanostructures.6. The semiconductor device structure as claimed in claim 1 , wherein a top surface of the first oxide layer is higher than a bottommost surface of the nanostructures.7. The ...

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Номер записи: 81
26-08-2021 дата публикации

Low Dimensional Material Device and Method

Номер: US20210265501A1
Автор: CHEN Tse-An, Chen Tzu-Chiang, CHENG Chao-Ching, CHIANG Hung-Li, Hung Yi-Tse, Li Lain-Jong
Принадлежит:

In an embodiment, a device includes: a dielectric fin on a substrate; a low-dimensional layer on the dielectric fin, the low-dimensional layer including a source/drain region and a channel region; a source/drain contact on the source/drain region; and a gate structure on the channel region adjacent the source/drain contact, the gate structure having a first width at a top of the gate structure, a second width at a middle of the gate structure, and a third width at a bottom of the gate structure, the second width being less than each of the first width and the third width. 1. A method comprising:forming a dielectric fin on a substrate;forming a low-dimensional layer on the dielectric fin;forming a first source/drain contact and a second source/drain contact on the low-dimensional layer;growing a first self-assembled spacer and a second self-assembled spacer on the first source/drain contact and the second source/drain contact, respectively, a channel region of the low-dimensional layer disposed between the first self-assembled spacer and the second self-assembled spacer;forming a gate structure on the channel region; andafter forming the gate structure, removing the first self-assembled spacer and the second self-assembled spacer.2. The method of claim 1 , wherein forming the low-dimensional layer comprises:growing a carbon nanotube network by an immersion process;growing aligned carbon nanotubes by decomposing a carbon-containing precursor; ordepositing a plurality of transition metal dichalcogenide (TMD) layers.3. The method of claim 1 , wherein forming the gate structure comprises:depositing a gate dielectric layer on the first self-assembled spacer, the second self-assembled spacer, and the channel region;depositing a gate electrode layer on the gate dielectric layer; andremoving portions of the gate dielectric layer and the gate electrode layer on the first self-assembled spacer and the second self-assembled spacer with an adhesion lithography process.4. The ...

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Номер записи: 82
01-08-2019 дата публикации

Multi-gate semiconductor device and method for forming the same

Номер: US20190237573A1
Автор: Carlos H. Diaz, Cheng-Hsien Wu, I-Sheng Chen, Ling-Yen Yeh, Tzu-Chiang CHEN
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method for forming a multi-gate semiconductor device includes providing a substrate including at least a fin structure and a dummy gate structure over the fin structure and the substrate, disposing a conductive spacer over sidewalls of the dummy gate structure, portions of the fin structure are exposed from the dummy gate structure and the conductive spacer, forming a source/drain region in the portions of the fin structures exposed from the dummy gate structure and the conductive spacer, disposing a dielectric structure over the substrate, removing the dummy gate structure to form a gate trench in the dielectric structure, the conductive spacer is exposed from sidewalls of the gate trench, disposing at least a gate dielectric layer over a bottom of the gate trench, and disposing a gate conductive structure in the gate trench, sidewalls of the gate conductive structure are in contact with the conductive spacer.

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Номер записи: 83
23-09-2021 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Номер: US20210296439A1
Автор: CHEN I-Sheng, Chen Tzu-Chiang, CHENG Chao-Ching, YANG Yu-Lin
Принадлежит:

In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers, the second semiconductor layer and an upper portion of the fin structure at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, are etched. A dielectric layer is formed over the etched upper portion of the fin structure. A source/drain epitaxial layer is formed. The source/drain epitaxial layer is connected to ends of the second semiconductor wires, and a bottom of the source/drain epitaxial layer is separated from the fin structure by the dielectric layer. 1. A semiconductor device , comprising:a bottom fin structure protruding from a substrate;semiconductor channel structures vertically arranged directly above the bottom fin structure, each of which has a channel region;a gate structure disposed around the channel region and disposed directly above the bottom fin structure;a source epitaxial layer and a drain epitaxial layer, connected to ends of the semiconductor channel structures, respectively; andinner spacers disposed between the source epitaxial layer and parts of the gate structure disposed between adjacent semiconductor channel structures and between the drain epitaxial layer and the parts of the gate structure, respectively, wherein:a bottom of the source epitaxial layer is separated from the bottom fin structure by a first dielectric layer and a bottom of the drain epitaxial layer is separated from the bottom fin structure by a second dielectric layer, andthe gate structure is in direct contact with an upper surface of the bottom fin structure and separates the first dielectric layer from the second dielectric layer.2. The semiconductor device of claim 1 , wherein the bottom fin structure includes a first groove below the source epitaxial ...

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Номер записи: 84
14-10-2021 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20210320191A1
Автор: CHEN I-Sheng, Chen Tzu-Chiang, CHENG Chao-Ching, CHIANG Hung-Li
Принадлежит:

In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A sacrificial gate structure having sidewall spacers is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is removed. The second semiconductor layers are laterally recessed. Dielectric inner spacers are formed on lateral ends of the recessed second semiconductor layers. The first semiconductor layers are laterally recessed. A source/drain epitaxial layer is formed to contact lateral ends of the recessed first semiconductor layer. The second semiconductor layers are removed thereby releasing the first semiconductor layers in a channel region. A gate structure is formed around the first semiconductor layers. 1. A semiconductor device , comprising:a plurality of channel layers vertically arranged over a bottom fin structure;a source/drain epitaxial layer connected to ends of the plurality of channel layers;a gate structure having a gate dielectric layer disposed around each of the channel layers, a gate electrode layer disposed on the gate dielectric layer and sidewall spacers; anda plurality of dielectric inner spacers disposed between the gate structure and the source/drain epitaxial layer,wherein each of the ends of each of the plurality of channel layers has a concave shape.2. The semiconductor device of claim 1 , wherein each of the plurality of dielectric inner spacers has at least three planes having one plane and two planes perpendicular to the one plane.3. The semiconductor device of claim 1 , wherein the sidewall spacers are not in contact with the plurality of channel layers.4. The semiconductor device of claim 1 , wherein a dielectric layer made of a same material as the plurality of dielectric inner spacers is disposed between the source/drain epitaxial layer and the bottom fin ...

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Номер записи: 85
15-08-2019 дата публикации

Isolation Manufacturing Method for Semiconductor Structures

Номер: US20190252266A1
Автор: CHANG Chih-Sheng, CHEN I-Sheng, Chen Tzu-Chiang, WU Cheng-Hsien
Принадлежит:

A method of forming a semiconductor device includes providing a semiconductor structure that includes a first semiconductor material extending from a first region to a second region. The method further includes removing a portion of the first semiconductor material in the second region to form a recess, where the recess exposes a sidewall of the first semiconductor material disposed in the first region; forming a dielectric material covering the sidewall; while the dielectric material covers the sidewall, epitaxially growing a second semiconductor material in the second region adjacent the dielectric material; and forming a first fin including the first semiconductor material and a second fin including the second semiconductor material. 1. A method , comprising:providing a semiconductor structure that includes a semiconductor substrate and a first semiconductor material extending from a first region to a second region over the semiconductor substrate, wherein the semiconductor substrate and the first semiconductor material have different crystalline orientations in both the first region and the second region;removing a portion of the first semiconductor material in the second region to form a recess, the recess exposing a sidewall of the first semiconductor material disposed in the first region;forming a dielectric material covering the sidewall; andwhile the dielectric material covers the sidewall, epitaxially growing a second semiconductor material in the second region adjacent the dielectric material, wherein the semiconductor substrate and the second semiconductor material have the same crystalline orientation.2. The method of claim 1 , wherein the forming of the dielectric includes:depositing the dielectric material covering the semiconductor structure in the first and second regions; andremoving a portion of the dielectric material from the second region, wherein another portion of the dielectric material covering the sidewall and a top surface of the first ...

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Номер записи: 86
06-08-2020 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Номер: US20200251555A1
Автор: CHEN I-Sheng, Chen Tzu-Chiang, CHENG Chao-Ching, YANG Yu-Lin
Принадлежит:

In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers, the second semiconductor layer and an upper portion of the fin structure at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, are etched. A dielectric layer is formed over the etched upper portion of the fin structure. A source/drain epitaxial layer is formed. The source/drain epitaxial layer is connected to ends of the second semiconductor wires, and a bottom of the source/drain epitaxial layer is separated from the fin structure by the dielectric layer. 1. A semiconductor device , comprising:semiconductor wires vertically arranged, each of which has a channel region;a gate structure disposed around the channel region, anda source/drain epitaxial layer connected to ends of the semiconductor wires, wherein:the semiconductor wires and the source/drain epitaxial layer are disposed above a bottom fin structure protruding from a substrate,a bottom of the source/drain epitaxial layer is separated from the bottom fin structure by a dielectric layer,the gate structure is separated from the source/drain epitaxial layer by an insulating layer made of a same material as the dielectric layer, andan upper surface of the bottom fin structure is in contact with the dielectric layer and has a groove.2. The semiconductor device of claim 1 , further comprising:an isolation insulating layer in which the bottom fin structure is embedded; andan interlayer dielectric (ILD) layer covering the source/drain epitaxial layer,wherein the dielectric layer is made of a different material than the isolation insulating layer and the ILD layer.3. The semiconductor device of claim 1 , wherein the dielectric layer is made of SiCO or SiOCN.4. The semiconductor device of claim 1 , wherein ...

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Номер записи: 87
22-08-2019 дата публикации

METHOD FOR FORMING SEMICONDUCTOR STRUCTURE

Номер: US20190259877A1
Автор: Chen Tzu-Chiang, CHENG Chao-Ching, Chiu Jung-Piao, HSU Chen-Feng, YANG Yu-Lin
Принадлежит:

A method for forming a semiconductor structure includes receiving a substrate including a dielectric structure; forming a first recess in the substrate; forming a dielectric spacer over a sidewall of the first recess; forming a first semiconductor layer to fill the first recess; removing the dielectric structure to form a second recess over the substrate; and forming a second semiconductor layer to fill the second recess. The dielectric spacer is sandwiched between the first semiconductor layer and the second semiconductor layer. 1. A method for forming a semiconductor structure , comprising:providing a substrate comprising a dielectric structure;forming a first recess in the substrate;forming a dielectric spacer over a sidewall of the first recess;forming a first semiconductor layer to fill the first recess;removing the dielectric structure to form a second recess over the substrate; andforming a second semiconductor layer to fill the second recess, wherein the dielectric spacer is sandwiched between the first semiconductor layer and the second semiconductor layer.2. The method of claim 1 , further comprising removing a portion of the first semiconductor layer to form a first fin structure and removing a portion of the second semiconductor layer to form a second fin structure over the substrate.3. The method of claim 2 , wherein the first fin structure comprises a first conductivity type and the second fin structure comprises a second conductivity type different from the first conductivity type.4. The method of claim 2 , further comprising:forming a third recess in the substrate, wherein the first fin structure and the second fin structure are exposed from the third recess;disposing an insulating material to fill the third recess; andremoving a portion of the insulating material to form an isolation structure in the third recess and to expose the first fin structure and the second fin structure.5. The method of claim 4 , wherein the substrate is exposed in a ...

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Номер записи: 88
29-08-2019 дата публикации

SEMICONDUCTOR DEVICE STRUCTURE WITH SEMICONDUCTOR WIRE

Номер: US20190267292A1
Автор: CHEN I-Sheng, Chen Tzu-Chiang, CHIANG Hung-Li, HUANG Szu-Wei, Lee Tung-Ying, WEI Huan-Sheng
Принадлежит:

Semiconductor device structures are provided. The semiconductor device structure includes first semiconductor wires over a semiconductor substrate. The first semiconductor wires are vertically spaced apart from each other. The semiconductor device structure also includes a gate stack surrounding first portions of the first semiconductor wires, and a spacer element surrounding second portions of the first semiconductor wires. The first portions have a first width and the second portions have a second width. In addition, the semiconductor device structure includes a second semiconductor wire between the second portions. The second semiconductor wire has a third width, and the third width is substantially equal to the second width and greater than the first width. 1. A semiconductor device structure , comprising:first semiconductor wires over a semiconductor substrate, wherein the first semiconductor wires are vertically spaced apart from each other;a gate stack surrounding first portions of the first semiconductor wires, wherein the first portions have a first width;a spacer element surrounding second portions of the first semiconductor wires, wherein the second portions have a second width; anda second semiconductor wire between the second portions, wherein the second semiconductor wire has a third width, and wherein the third width is substantially equal to the second width and greater than the first width.2. The semiconductor device structure as claimed in claim 1 , wherein the first semiconductor wires and the second semiconductor wire comprise different materials.3. The semiconductor device structure as claimed in claim 1 , wherein an interval between the first semiconductor wires is less than a thickness of the first semiconductor wires.4. The semiconductor device structure as claimed in claim 1 , wherein a first cross-sectional area of the first portions of the first semiconductor wires is less than a second cross-sectional area of the second portions of the ...

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Номер записи: 89
25-11-2021 дата публикации

CRYOGENIC INTEGRATED CIRCUITS

Номер: US20210366819A1
Автор: Cai Jin, Chen Tzu-Chiang, Chen Yu-Sheng, CHENG Chao-Ching, CHIANG Hung-Li
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

Cryogenic integrated circuits are provided. A cryogenic integrated circuit includes a thermally conductive base, a data processer, a storage device, a buffer device, a thermally conductive shield and a cooling pipe. The data processer is located on the thermally conductive base. The storage device is located on the thermally conductive base and disposed aside and electrically connected to the data processer. The buffer device is disposed on the data processer. The thermally conductive shield covers the data processer, the storage device and the buffer device. The cooling pipe is located in physical contact with the thermally conductive base and disposed at least corresponding to the data processer. 1. A cryogenic integrated circuit , comprising:a thermally conductive base;a data processer located on the thermally conductive base;a storage device located on the thermally conductive base and disposed aside and electrically connected to the data processer;a buffer device disposed on the data processer;a thermally conductive shield covering the data processer, the storage device and the buffer device; anda cooling pipe located in physical contact with the thermally conductive base and disposed at least corresponding to the data processer.2. The cryogenic integrated circuit of claim 1 , wherein cryogenic integrated circuit is configured to operate at a temperature of about 50K to 273K.3. The cryogenic integrated circuit of claim 1 , wherein the data processer comprises a cryogenic CMOS device.4. The cryogenic integrated circuit of claim 3 , wherein the cryogenic CMOS device comprises:an N-type device having a work function value of 4.25 to 4.30 eV; anda P-type device having a work function value of 5.00 to 5.05 eV.5. The cryogenic integrated circuit of claim 1 , wherein the storage device comprises a RRAM device.6. The cryogenic integrated circuit of claim 1 , wherein the buffer device comprises a MRAM device.7. The cryogenic integrated circuit of claim 1 , wherein the ...

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Номер записи: 90
20-08-2020 дата публикации

SEMICONDUCTOR STRUCTURE WITH EXTENDED CONTACT STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20200266271A1
Автор: CHEN I-Sheng, Chen Tzu-Chiang, CHENG Chao-Ching, CHIANG Hung-Li, Huang Shih-Syuan, Liaw Jhon-Jhy, Lin Ta-Chun, PAN Kuo-Hua, Yeong Sai-Hooi
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

Methods for forming semiconductor structures are provided. The method includes alternately stacking first semiconductor layers and second semiconductor layers over a substrate and patterning the first semiconductor layers and the second semiconductor layers to form a first fin structure. The method further includes forming a first trench in the first fin structure and forming a first source/drain structure in the first trench. The method further includes partially removing the first source/drain structure to form a second trench in the first source/drain structure and forming a first contact in the second trench. 1. A method for manufacturing a semiconductor structure , comprising:alternately stacking first semiconductor layers and second semiconductor layers over a substrate;patterning the first semiconductor layers and the second semiconductor layers to form a first fin structure;forming a first trench in the first fin structure;forming a first source/drain structure in the first trench;partially removing the first source/drain structure to form a second trench in the first source/drain structure; andforming a first contact in the second trench.2. The method for manufacturing the semiconductor structure as claimed in claim 1 , wherein a bottom portion of the second trench is lower than a top surface of one of the first semiconductor layers.3. The method for manufacturing the semiconductor structure as claimed in claim 1 , further comprising:forming a first interlayer dielectric layer over the first source/drain structure;removing the second semiconductor layers of the first fin structure in a first channel region to form first nanostructures from the first semiconductor layers of the first fin structure;forming a first gate structure surrounding the first nanostructures;forming a first contact opening in the first interlayer dielectric layer to expose the first source/drain structure; andetching the first source/drain structure through the first contact opening to ...

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Номер записи: 91
27-09-2018 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20180277448A1
Автор: CHANG Chih-Sheng, CHEN I-Sheng, Chen Tzu-Chiang, WU Cheng-Hsien, YEH Chih-Chieh
Принадлежит:

A semiconductor device includes at least one n-channel, at least one p-channel, at least one first high-k dielectric sheath, at least one second high-k dielectric sheath, a first metal gate electrode and a second metal gate electrode. The first high-k dielectric sheath surrounds the n-channel. The second high-k dielectric sheath surrounds the p-channel. The first high-k dielectric sheath and the second high-k dielectric sheath comprise different high-k dielectric materials. The first metal gate electrode surrounds the first high-k dielectric sheath. The second metal gate electrode surrounds the second high-k dielectric sheath. 1. A semiconductor device , comprising:at least one n-channel;at least one p-channel;at least one first high-k dielectric sheath surrounding the n-channel;at least one second high-k dielectric sheath surrounding the p-channel, the first high-k dielectric sheath and the second high-k dielectric sheath comprising different high-k dielectric materials;a first metal gate electrode surrounding and in contact with the first high-k dielectric sheath; anda second metal gate electrode surrounding and in contact with the second high-k dielectric sheath, wherein the first and second metal gate electrodes are made of the same material.2. (canceled)3. The semiconductor device of claim 1 , wherein the first metal gate electrode and the second metal gate electrode are made of a single metal.4. The semiconductor device of claim 1 , wherein the first high-k dielectric sheath comprises YO claim 1 , LuO claim 1 , LaO claim 1 , SrO claim 1 , Er claim 1 , Sc claim 1 , or combinations thereof.5. The semiconductor device of claim 1 , wherein the second high-k dielectric sheath comprises AlO claim 1 , TiO claim 1 , ZrO claim 1 , MgO claim 1 , or combinations thereof.6. The semiconductor device of claim 1 , wherein the first high-k dielectric sheath is made of LaO claim 1 , and the second high-k dielectric sheath is made of AlO.78-. (canceled)9. The semiconductor ...

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Номер записи: 92
23-12-2021 дата публикации

Memory array with asymmetric bit-line architecture

Номер: US20210399054A1
Автор: Chao-Ching Cheng, Hung-Li Chiang, Jung-Piao Chiu, Tzu-Chiang CHEN, Yu-Sheng Chen
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The present disclosure relates to an integrated circuit. The integrated circuit has a plurality of bit-line stacks disposed over a substrate and respectively including a plurality of bit-lines stacked onto one another. A data storage structure is over the plurality of bit-line stacks and a selector is over the data storage structure. A word-line is over the selector. The selector is configured to selectively allow current to pass between the plurality of bit-lines and the word-line. The plurality of bit-line stacks include a first bit-line stack, a second bit-line stack, and a third bit-line stack. The first and third bit-line stacks are closest bit-line stacks to opposing sides of the second bit-line stack. The second bit-line stack is separated from the first bit-line stack by a first distance and is further separated from the third bit-line stack by a second distance larger than the first distance.

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Номер записи: 93
12-09-2019 дата публикации

Semiconductor Device and Method

Номер: US20190279911A1
Автор: Chen Tzu-Chiang, CHENG Chao-Ching, HSU Chen-Feng, Lee Tung Ying, YANG Yu-Lin, YEH Chih Chieh
Принадлежит:

Nanowire devices and fin devices are formed in a first region and a second region of a substrate. To form the devices, alternating layers of a first material and a second material are formed, inner spacers are formed adjacent to the layers of the first material, and then the layers of the first material are removed to form nanowires without removing the layers of the first material within the second region. Gate structures of gate dielectrics and gate electrodes are formed within the first region and the second region in order to form the nanowire devices in the first region and the fin devices in the second region. 1. A semiconductor device comprising:a substrate with a first region and a second region;a first nanowire and a second nanowire that are disposed over the first region of the substrate, the first nanowire extending further from the substrate than the second nanowire;a gate material between the first nanowire and the second nanowire; a first material located in a first plane with the first nanowire, wherein the first nanowire comprises the first material; and', 'a second material located in a second plane with the gate material, the second material being different from the first material., 'a channel over the second region of the substrate, wherein the channel comprises2. The semiconductor device of claim 1 , further comprising a gate dielectric material in the first region and in the second region claim 1 , wherein the gate dielectric material in the first region is disposed around the first nanowire and the second nanowire.3. The semiconductor device of claim 2 , wherein the gate dielectric material in the second region is disposed along an upper surface of the channel distal to the substrate.4. The semiconductor device of claim 1 , further comprising a first source/drain region and a second source/drain region in the first region of the substrate claim 1 , wherein the first nanowire and the second nanowire are between the first source/drain region and ...

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Номер записи: 94
22-10-2020 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Номер: US20200335400A1
Автор: CHEN Chih-Liang, CHEN I-Sheng, Chen Tzu-Chiang, CHENG Chao-Ching, CHIANG Hung-Li, GUO Ta-Pen, HUANG Szu-Wei, YANG Yu-Lin
Принадлежит:

In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer. 1. A semiconductor device , comprising:a first gate-all-around field effect transistor (GAA FET) disposed over a substrate; anda second GAA FET disposed over the substrate, wherein: semiconductor wires vertically arranged over the substrate;', 'a source/drain epitaxial layer in contact with one or more of the semiconductor wires;', 'a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires; and', 'a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and, 'each of the first GAA FET and the second GAA FET includesin at least one of the first GAA FET and the second GAA FET, at least one of the second semiconductor layers is separated from a bottom of the source/drain epitaxial layer by a dielectric layer.2. The semiconductor device of claim 1 , wherein a number of the semiconductor wires contacting the source/drain epitaxial layer in the first GAA FET is different from a number of the semiconductor wires contacting the source/ ...

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Номер записи: 95
07-11-2019 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20190341469A1
Автор: Chen Tzu-Chiang, CHENG Chao-Ching, HSU Chen-Feng, YANG Yu-Lin, YUN Wei-Sheng
Принадлежит:

A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer. 1. A semiconductor device , comprising:semiconductor wires disposed over a channel region on a substrate;a source/drain epitaxial layer in contact with the semiconductor wires which do not pass through the source/drain epitaxial layer; a gate dielectric layer disposed on and wrapping around the semiconductor wires in the channel region; and', 'a gate electrode layer disposed on the gate dielectric layer and wrapping around the semiconductor wires in the channel region; and, 'a gate structure in the channel region, the gate structure comprisingdielectric spacers disposed in recesses formed between the source/drain epitaxial layer and the gate structure at both ends of the channel region.2. The semiconductor device of claim 1 , wherein the recesses are formed in a region between the gate electrode layer and the source/drain epitaxial layer.3. The semiconductor device of claim 1 , wherein the source/drain epitaxial layer comprises one or more of Si claim 1 , SiGe and SiGeB.4. The semiconductor device of claim 1 , wherein the gate electrode layer comprises one of polysilicon claim 1 , aluminum claim 1 , copper claim 1 , titanium claim 1 , tantalum claim 1 , tungsten claim 1 , cobalt claim 1 , molybdenum claim 1 , tantalum nitride claim 1 , nickel silicide claim 1 , cobalt silicide claim 1 , TiN claim 1 , WN claim 1 , TiAl claim 1 , TiAlN claim 1 , TaCN claim 1 , TaC claim 1 , TaSiN claim 1 , or a combination thereof.5. The semiconductor device of ...

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Номер записи: 96
06-12-2018 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH MULTILAYERED CHANNEL STRUCTURE

Номер: US20180350971A1
Автор: CHEN I-Sheng, Chen Tzu-Chiang, CHENG Chao-Ching, CHIANG Hung-Li, Chiu Jung-Piao, LEE Tsung-Lin, WU Cheng-Hsien, YANG Yu-Lin, YEH Chih Chieh
Принадлежит:

A semiconductor device includes a fin field effect transistor (FinFET). The FinFET includes a channel disposed on a fin, a gate disposed over the channel and a source and drain. The channel includes at least two pairs of a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. The first semiconductor layer has a different lattice constant than the second semiconductor layer. A thickness of the first semiconductor layer is three to ten times a thickness of the second semiconductor layer at least in one pair. 1. A method of forming a semiconductor device including fin field effect transistors (FinFETs) , the method comprising:forming at least two pairs a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer, on a substrate;patterning the at least two pairs of the first and second semiconductor layers and the substrate, thereby forming a channel fin formed by part of the first and second semiconductor layers and a base fin formed by part of the substrate;forming a source and a drain; andforming a gate structure over a channel layer formed by a part of the channel fin, wherein:the first semiconductor layer has a different lattice constant than the second semiconductor layer, anda thickness of the first semiconductor layer is three to ten times a thickness of the second semiconductor layer at least in one pair.2. The method of claim 1 , wherein three pairs of the first semiconductor layer and the second semiconductor layer are formed on the substrate.3. The method of claim 1 , wherein the second semiconductor layer is Si and the first semiconductor layer is SiGe claim 1 , where 0.1 Подробнее

Номер записи: 97
06-12-2018 дата публикации

REFRIGERATING MACHINE WITH DETACHABLE HALL ELEMENT

Номер: US20180351436A1
Автор: Chen Tzu-Chiang
Принадлежит:

A refrigerating machine having a detachable Hall element is provided with a cold heat exchange mechanism. The cold-heat exchange mechanism is driven by a driving assembly to generate a low temperature cooling zone at one end of the cold heat exchange mechanism. The driving assembly is composed of at least one rotor and a stator. After the power is input, the rotor can rotate a shaft to drive the cold-heat exchange mechanism to work. The driving assembly further has at least one Hall element and a circuit board on which the Hall element is mounted. Therefore, when the Hall element is damaged, the circuit board can be easily removed for replacement or repair. 1. A refrigerating machine comprising:a cold-heat exchange mechanism having a power input end;a driving assembly connected to the power input end of the cold heat exchange mechanism;wherein the driving assembly has:a rotor having a magnet and a shaft, wherein the magnet is fixed to one end of the shaft and another end of the shaft is connected to the power input end of the cold-heat exchange mechanism,a cap being a hollow shell and mounted on the cold heat exchange mechanism, wherein one end of the shaft having the magnet fixed thereto is rotatably held inside the cap;a coil assembly having a housing, a coil unit, a plurality of circuit boards and at least one Hall element, wherein the housing is a hollow body and has an opening at one end, each of the circuit boards is disposed inside the housing, the at least one Hall element is connected to the circuit boards and extends downward from the circuit boards, the end having the opening of the housing is fixed to the cold heat exchange mechanism, and the at least one Hall element corresponds in position to the magnet of the rotor.2. The refrigerating machine as claimed in claim 1 , further comprising:a positioning element and a spacer, wherein the positioning element is disposed between the coil unit and the housing to connect and fix the coil unit to the housing, ...

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Номер записи: 98
29-10-2020 дата публикации

HORIZONTAL MEMORY ARRAY STRUCTURE WITH SCAVENGER LAYER

Номер: US20200343446A1
Автор: Chen Tzu-Chiang, Chen Yu-Sheng, CHENG Chao-Ching, CHIANG Hung-Li
Принадлежит:

Various embodiments of the present disclosure are directed towards a resistive random access memory (RRAM) device including a scavenger layer. A bit line overlying a semiconductor substrate. A data storage layer around outer sidewalls and a top surface of the bit line. A word line overlying the data storage layer. A scavenger layer between the word line and the bit line such that a bottom surface of the scavenger layer is aligned with a bottom surface of the bit line. A lateral thickness of the scavenger layer is less than a vertical thickness of the scavenger layer. 1. A resistive random access memory (RRAM) device comprising:a bit line overlying a semiconductor substrate;a data storage layer around outer sidewalls and a top surface of the bit line;a word line overlying the data storage layer; anda scavenger layer between the word line and the bit line, wherein a bottom surface of the scavenger layer is aligned with a bottom surface of the bit line, wherein a lateral thickness of the scavenger layer is less than a vertical thickness of the scavenger layer.2. The RRAM device according to claim 1 , wherein the scavenger layer is configured to collect a reactive species from the data storage layer.3. The RRAM device according to claim 1 , wherein a bottom surface of the word line extends below the top surface of the bit line claim 1 , and wherein the scavenger layer is disposed directly between the word line and the data storage layer such that the data storage layer directly contacts the bit line.4. The RRAM device according to claim 1 , wherein the scavenger layer is configured to direct a maximum electric field between the bit line and the word line to an upper region claim 1 , the upper region is defined between a top surface of the bit line and an inner surface of the word line.5. The RRAM device according to claim 4 , further comprising:an outer scavenger layer directly between the data storage layer and the word line, wherein the outer scavenger layer comprises ...

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Номер записи: 99
14-11-2019 дата публикации

MULTI-GATE SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

Номер: US20190348498A1
Автор: CHEN I-Sheng, Chen Tzu-Chiang, CHENG Chao-Ching, CHIANG Hung-Li, Huang Shih-Syuan
Принадлежит:

A multi-gate semiconductor structure includes a plurality of nanowires, a gate structure disposed over the plurality of nanowires, and source/drain structures at two ends of each of the plurality of nanowires. The source/drain structures include a conductor, and a bottom surface of the conductor is lower than the plurality of nanowires. 2. The multi-gate semiconductor structure of claim 1 , wherein the metal silicide layer is sandwiched between the metal portion and the semiconductor layer.3. The multi-gate semiconductor structure of claim 1 , wherein each of the semiconductor layer and the metal silicide layer substantially includes a U shape.4. The multi-gate semiconductor structure of claim 1 , wherein a top surface of the metal portion is higher than a top surface of the gate structure.5. The multi-gate semiconductor structure of claim 1 , wherein the gate structure comprises a metal gate structure.6. A multi-gate semiconductor device comprising:a plurality of first nanowires and a plurality of second nanowires;a first gate structure disposed over the plurality of first nanowires and a second gate structure disposed over a first portion of the plurality of second nanowires;first source/drain structures disposed at two ends of each of the plurality of first nanowires, the first source/drain structure comprising a conductor, a first semiconductor layer disposed around a bottom and sidewalls of a portion of the conductor, and a first metal silicide layer disposed between the conductor and the first semiconductor layer; andsecond source/drain structures disposed at two ends of each of the first portions of the second nanowires, the second source/drain structure comprising a second portion of the plurality of second nanowires, a second metal silicide layer disposed over the second portions of the second nanowires, and a second semiconductor layer disposed between the second metal silicide layer and the second portions of the second nanowires.7. The multi-gate ...

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Номер записи: 100
21-11-2019 дата публикации

HYBRID SEMICONDUCTOR TRANSISTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SAME

Номер: US20190355724A1
Автор: CHEN I-Sheng, Chen Tzu-Chiang, CHIANG Hung-Li
Принадлежит:

Present disclosure provides a hybrid semiconductor transistor structure, including a substrate, a first transistor on the substrate, a channel of the first transistor including a fin and having a first channel height, a second transistor adjacent to the first transistor, a channel of the second transistor including a nanowire, and a separation laterally spacing the fin from the nanowire. The first channel height is greater than the separation. Present disclosure also provides a method for manufacturing the hybrid semiconductor transistor structure. 17-. (canceled)8. A method for forming a hybrid semiconductor transistor structure , comprising:providing a substrate;epitaxially forming alternating stacked films over the substrate;forming a trench in the alternating stacked films over a first transistor region; andafter forming the trench in the alternating stacked films over the first transistor region, patterning the alternating stacked films over a second transistor region obtaining an alternating stacked fin.9. The method of claim 8 , further comprising:filling the trench over the first transistor region with a material different from that of the substrate;patterning the material over the first transistor region to obtain a fin; andforming a dummy gate orthogonally over the fin.10. The method of claim 9 , wherein the patterning of the alternating stacked films over the second transistor region and the patterning of the material over the first transistor region are performed concurrently.11. The method of claim 9 , further comprising:covering the fin over the first transistor region with a hard mask;releasing a nanowire from the alternating stacked fin; andremoving the hard mask covering the fin.12. The method of claim 8 , wherein the forming of the trench comprises forming a vertical sidewall trench or a tapered trench tapering toward the substrate.13. The method of claim 9 , further comprising:depositing a first dummy oxide layer over the fin after obtaining the ...

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Номер записи: 101
20-12-2018 дата публикации

Isolation Manufacturing Method for Semiconductor Structures

Номер: US20180366375A1
Автор: CHANG Chih-Sheng, CHEN I-Sheng, Chen Tzu-Chiang, WU Cheng-Hsien
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A method of forming a semiconductor device includes providing a semiconductor structure that includes a first semiconductor material extending from a first region to a second region. The method further includes removing a portion of the first semiconductor material in the second region to form a recess, where the recess exposes a sidewall of the first semiconductor material disposed in the first region; forming a dielectric material covering the sidewall; while the dielectric material covers the sidewall, epitaxially growing a second semiconductor material in the second region adjacent the dielectric material; and forming a first fin including the first semiconductor material and a second fin including the second semiconductor material. 1. A method , comprising:providing a semiconductor structure that includes a semiconductor substrate and a first semiconductor material extending from a first region to a second region over the semiconductor substrate, wherein the semiconductor substrate and the first semiconductor material have different crystalline orientations;removing a portion of the first semiconductor material in the second region to form a recess, the recess exposing a sidewall of the first semiconductor material disposed in the first region and a top surface of the semiconductor substrate in the second region;forming a dielectric material covering the sidewall;while the dielectric material covers the sidewall, epitaxially growing a second semiconductor material in the second region adjacent the dielectric material; andforming a first fin including the first semiconductor material and a second fin including the second semiconductor material.2. The method of claim 1 , wherein:the first semiconductor material includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers, the first and second semiconductor layers having different material compositions; andthe second semiconductor material includes a plurality of ...

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Номер записи: 102
12-11-2020 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH MULTILAYERED CHANNEL STRUCTURE

Номер: US20200357914A1
Автор: CHEN I-Sheng, Chen Tzu-Chiang, CHENG Chao-Ching, CHIANG Hung-Li, Chiu Jung-Piao, LEE Tsung-Lin, WU Cheng-Hsien, YANG Yu-Lin, YEH Chih Chieh
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A semiconductor device includes a fin field effect transistor (FinFET). The FinFET includes a channel disposed on a fin, a gate disposed over the channel and a source and drain. The channel includes at least two pairs of a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. The first semiconductor layer has a different lattice constant than the second semiconductor layer. A thickness of the first semiconductor layer is three to ten times a thickness of the second semiconductor layer at least in one pair. 1. A semiconductor device including a fin field effect transistor (FinFET) , the FinFET comprising:a channel disposed on a fin;a gate disposed over the channel; anda source and drain, wherein:the channel includes first semiconductor layers and a second semiconductor layer disposed between the first semiconductor layers,the first semiconductor layers have a different lattice constant than the second semiconductor layer, andthe second semiconductor extends into the source and the drain and the first semiconductor layer does not extend into the source and the drain.2. The semiconductor device of claim 1 , wherein the first semiconductor layers have different widths from each other in a source-to-drain direction.3. The semiconductor device of claim 1 , wherein the second semiconductor layer is Si and the first semiconductor layer is SiGe claim 1 , where 0.2 Подробнее

Номер записи: 103
26-12-2019 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

Номер: US20190393102A1
Автор: CHEN Chih-Liang, CHEN I-Sheng, Chen Tzu-Chiang, CHENG Chao-Ching, CHIANG Hung-Li, GUO Ta-Pen, HUANG Szu-Wei, YANG Yu-Lin
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In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer. 1. A semiconductor device , comprising:a first gate-all-around field effect transistor (GAA FET) disposed over a substrate; anda second GAA FET disposed over the substrate, wherein: semiconductor wires vertically arranged over the substrate;', 'a source/drain epitaxial layer in contact with one or more of the semiconductor wires;', 'a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires; and', 'a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region,, 'each of the first GAA FET and the second GAA FET includesin at least one of the first GAA FET and the second GAA FET, at least one of the semiconductor wires is separated from a bottom of the source/drain epitaxial layer by a dielectric layer, anda thickness of an isolation insulating layer surrounding the first GAA FET is different from a thickness of an isolation insulating layer surrounding the second GAA FET.2. The semiconductor device of claim 1 , wherein a number of the ...

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Номер записи: 104