Semiconductor device, method of manufacturing the same, and method of manufacturing wiring board

Interconnect structures for preventing solder bridging, and associated systems and methods

Semiconductor dies having interconnect structures formed thereon, and associated systems and methods, are disclosed herein. In one embodiment, an interconnect structure includes a conductive material electrically coupled to an electrically conductive contact of a semiconductor die. The conductive material includes a first portion vertically aligned with the conductive contact, and a second portion that extends laterally away from the conductive contact. A solder material is disposed on the second portion of the interconnect structure such that the solder material is at least partially laterally offset from the conductive contact of the semiconductor die. In some embodiments, an interconnect structure can further include a containment layer that prevents wicking or other undesirable movement of the solder material during a reflow process.

Halbleiteranordnung und Verfahren zur Herstelllung von Halbleiteranordnungen

Die vorliegende Anmeldung betrifft eine Halbleiteranordnung umfassend einen Halbleiterchip, einen den Halbleiterchip überdeckenden ausgeformten Körper, wobei der ausgeformte Körper ein Array ausgeformter Strukturelemente umfasst, und erste Lotelemente in Eingriff mit den ausgeformten Strukturelementen.

Semiconductor device and manufacturing method thereof

HYBRIDIZATION TO-FACE TWO MICROELECTRONIC COMPONENTS USING ANNEAL UV

Ce procédé de fabrication d'un dispositif microélectronique comportant un premier composant (12) hybridé à un second composant (14) au moyen d'interconnexions électriques, consiste : ▪ à réaliser des premier et second composants (12, 14), le second composant (14) étant transparent à un rayonnement ultraviolet au moins au droit d'emplacements prévus pour les interconnexions ; ▪ à former des éléments d'interconnexion (22) comprenant de l'oxyde de cuivre sur le second composant (14) aux emplacements prévus pour les interconnexions; ▪ à reporter les premier et second composants (12, 14) l'un sur l'autre ; et ▪ à appliquer un rayonnement ultraviolet au travers le second composant (14) sur les éléments comprenant de l'oxyde de cuivre de manière à mettre en œuvre un recuit ultraviolet transformant l'oxyde de cuivre en cuivre.

Semiconductor packaging and manufacturing method thereof

The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI.

3di solder cup

本發明揭示一種基板或半導體裝置、半導體裝置總成及一種用於形成包含一焊料杯上之一障壁之一半導體裝置總成之方法。該半導體裝置總成包含安置於另一基板上面之一基板。至少一焊料杯自一基板朝向另一基板上之一凸塊下金屬(UBM)延伸。該焊料杯之外部上之該障壁可為一間隔件以控制該等基板之間的一接合線。在形成一半導體裝置總成期間，該障壁可減少焊料橋接。該障壁可在形成一半導體裝置總成時有助於使該焊料杯與一UBM對準且可減少歸因於基板及/或半導體裝置之橫向移動之失準。

BUMP STRESS MITIGATION LAYER FOR INTEGRATED CIRCUITS

Method for Aligning Micro-Electronic Components

Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force. By applying appropriate charges on the conductor lines, electrostatic self-alignment is realized, which improves ...

MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE

The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI.

Solder structures for out of plane connections and related methods

Methods of forming a solder structure may include providing a wafer including a plurality of die therein, and a solder wettable pad may be formed on one of the die adjacent an edge of the die. The solder wettable pad may have a length parallel to the edge of the die and a width perpendicular to the edge of the die wherein the length parallel to the edge of the die is greater than the width perpendicular to the edge of the die. A solder bump may be plated on the solder wettable pad, and the die may be separated from the wafer along the edge of the die after plating the solder bump on the solder wettable pad. Moreover, the solder bump may be reflowed on the solder wettable pad so that the solder structure extends laterally from the solder wettable pad beyond the edge of the die after separating the die from the wafer. Related structures are also discussed.

FILMSCHEMA ZUR KONTAKTHÖCKERBILDUNG

Eine Kontakthöckerstruktur mit einer Sperrschicht und ein Verfahren zur Herstellung der Kontakthöckerstruktur werden bereitgestellt. In einigen Ausführungsformen umfasst die Kontakthöckerstruktur eine leitfähige Kontaktinsel, einen leitfähigen Kontakthöcker und eine Sperrschicht. Die leitfähige Kontaktinsel umfasst ein Kontaktinselmaterial. Der leitfähige Kontakthöcker liegt über der leitfähigen Kontaktinsel und umfasst eine untere Kontakthöckerschicht und eine obere Kontakthöckerschicht, die die untere Kontakthöckerschicht bedeckt. Die Sperrschicht ist dafür konfiguriert, die Bewegung des Kontaktinselmaterials von der leitfähigen Kontaktinsel zu der oberen Kontakthöckerschicht entlang Seitenwänden der unteren Kontakthöckerschicht zu blockieren. In einigen Ausführungsformen ist die Sperrschicht ein Abstandshalter, der die Seitenwände der unteren Kontakthöckerschicht auskleidet. In anderen Ausführungsformen befindet sich die Sperrschicht zwischen der Sperrschicht und der leitfähigen Kontaktinsel ...

HYBRIDIZATION FACE-TO-FACE TWO MICROELECTRONIC COMPONENTS USING ANNEALING UV

Ce procédé de fabrication d'un dispositif microélectronique comportant un premier composant (12) hybridé à un second composant (14) au moyen d'interconnexions électriques, consiste : * à réaliser des premier et second composants (12, 14), le second composant (14) étant transparent à un rayonnement ultraviolet au moins au droit d'emplacements prévus pour les interconnexions ; * à former des éléments d'interconnexion (22) comprenant de l'oxyde de cuivre sur le second composant (14) aux emplacements prévus pour les interconnexions; * à reporter les premier et second composants (12, 14) l'un sur l'autre ; et * à appliquer un rayonnement ultraviolet au travers le second composant (14) sur les éléments comprenant de l'oxyde de cuivre de manière à mettre en oeuvre un recuit ultraviolet transformant l'oxyde de cuivre en cuivre. This method of manufacturing a microelectronic device comprising a first component (12) hybridized to a second component (14) by means of electrical interconnections, consists of: * producing first and second components (12, 14), the second component (14) being transparent to ultraviolet radiation at least to the right of the locations provided for the interconnects; * forming interconnection elements (22) comprising copper oxide on the second component (14) at the locations provided for the interconnections; * to transfer the first and second components (12, 14) one on the other; and * applying ultraviolet radiation through the second component (14) on the elements comprising copper oxide so as to carry out ultraviolet annealing transforming the copper oxide into copper.

Film scheme for bumping

本發明實施例提供一種具有一阻障層之凸塊結構及一種用於製造該凸塊結構之方法。在一些實施例中，該凸塊結構包括一導電墊、一導電凸塊及一阻障層。該導電墊包括一墊材料。該導電凸塊上覆於該導電墊，且包括一下凸塊層及覆蓋該下凸塊層之一上凸塊層。該阻障層經組態以阻止墊材料沿著該下凸塊層之側壁從該導電墊移動至該上凸塊層。在一些實施例中，該阻障層係襯於該下凸塊層之該等側壁之一間隔件。在其他實施例中，該阻障層在該阻障層與該導電墊之間，且將該下凸塊層之該等側壁與該導電墊間隔開。

SOLDER STRUCTURES FOR OUT OF PLANE CONNECTIONS AND RELATED METHODS

Methods of forming a solder structure may include providing a wafer including a plurality of die therein, and a solder wettable pad may be formed on one of the die adjacent an edge of the die. The solder wettable pad may have a length parallel to the edge of the die and a width perpendicular to the edge of the die wherein the length parallel to the edge of the die is greater than the width perpendicular to the edge of the die. A solder bump may be plated on the solder wettable pad, and the die may be separated from the wafer along the edge of the die after plating the solder bump on the solder wettable pad. Moreover, the solder bump may be reflowed on the solder wettable pad so that the solder structure extends laterally from the solder wettable pad beyond the edge of the die after separating the die from the wafer. Related structures are also discussed.

SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME

A semiconductor package includes: (1) a substrate; (2) a first isolation layer disposed on the substrate, the first isolation layer including an opening; (3) a pad disposed on the substrate and exposed from the opening; (4) an interconnection layer disposed on the pad; and (5) a conductive post including a bottom surface, the bottom surface having a first part disposed on the interconnection layer and a plurality of second parts disposed on the first isolation layer.

Semiconductor device and method of manufacture thereof

A semiconductor device and a method of making a semiconductor device are disclosed. The semiconductor device comprises a redistribution layer arranged over a chip, the redistribution layer comprising a first redistribution line. The semiconductor further comprises an isolation layer disposed over the redistribution layer, the isolation layer having a first opening forming a first pad area and a first interconnect located in the first opening and in contact with the first redistribution line.

Semiconductor device

A semiconductor device includes a semiconductor element, a lead on which the semiconductor element is mounted, a bonding member fixing the semiconductor element to the lead, and a resin package enclosing the semiconductor element and a portion of the lead. This lead is formed with a groove recessed at a location spaced from the semiconductor element. The groove has first and second inner surfaces, where the first inner surface is closer to the semiconductor element than is the second inner surface. The angle the first inner surface forms with respect to the thickness direction of the semiconductor element is smaller than the angle the second inner surface forms with respect to the thickness direction.

Semiconductor device and methods of manufacturing semiconductor devices

This application relates to a semiconductor device comprising a semiconductor chip, a molded body covering the semiconductor chip, wherein the molded body comprises an array of molded structure elements, and first solder elements engaged with the molded structure elements.

Flip chip

Coupling of integrated circuits (ICs) through a passivation-defined contact pad

External components may be placed on an active side of a wafer 100 as part of wafer-level chip scale packaging (WLCSP) for use in electronic devices. Pad layouts for the components on an active side of a wafer 100 may be passivation-defined by forming a conductive terminal 502 over a first dielectric layer 508 and a forming a passivating, second dielectric layer 510 over the conductive terminal 502. Openings formed in the second dielectric layer 510 define component contacts to the conductive terminal 502 and circuitry on the wafer 100 coupled to the conductive terminal 502. Trenches 506 may be used between pairs of contact pads 524 to further reduce issues resulting from short circuits and/or underfills. A conductive pad 524 may further be deposited in the opening to form underbump metallization (UBM) for coupling the component to the wafer. The external components may be coupled to contact pads 524 which are located on the wafer 100 surface amongst a grid of solder balls.

PACKAGING DEVICES AND METHODS OF MANUFACTURE THEREOF

Semiconductor packaging and manufacturing method thereof

METHODS OF FORMING CONNECTOR PAD STRUCTURES, INTERCONNECT STRUCTURES, AND STRUCTURES THEREOF

Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.

Chip, manufacturing method therefor, and laminated chip manufacturing method

SEMICONDUCTOR PACKAGE INCLUDING A CONNECTION MEMBER FOR ELECTRICALLY CONNECTING SEMICONDUCTOR CHIPS

PURPOSE: A semiconductor package is provided to form a contact prevention layer adjacent to a connection member and to prevent the connection member from being extended to a part of a semiconductor chip. CONSTITUTION: A second semiconductor chip(100b) is formed on the surface of a first semiconductor chip(100a). A first semiconductor chip includes and a through silicon via(105) electrically connected to a connection pad(122). A connection member(120) electrically connects the first semiconductor chip to a second semiconductor chip. A connection member includes the connection pad, a connection pillar(126), and a bonding member(124) for connecting the connection pad to the connection pillar. A contact prevention layer(130) is formed on the surface of the connection pad. COPYRIGHT KIPO 2013 ...

Methods of forming connector pad structures, interconnect structures, and structures thereof

Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.

Coupling of integrated circuits (ICs) through a passivation-defined contact pad

SEMICONDUCTOR DEVICE AND ITS MANUFACTURE METHOD CAPABLE OF PREVENTING SHORT CIRCUIT OF ELECTRODES WHEN SEMICONDUCTOR DEVICE IS MOUNTED ON SUB-MOUNT SUBSTRATE

A confronting surface of a substrate faces a first surface of a semiconductor element. Extension layers are formed on the substrate at positions facing electrodes on the semiconductor element. A levee film is disposed on one of the confronting surface and the first surface. Openings are formed through the levee film. Connection members which is filled but is not completely filled in the openings connect the electrodes and the extension layers.

DISPLAY BACKPLANE ASSEMBLY, LED DISPLAY MODULE, AND RELATED METHODS FOR MANUFACTURING THE SAME

A display backplane assembly, a light-emitting diode (LED) display module and a device, and related methods for manufacturing the same are provided in the disclosure. The display backplane assembly includes a display backplane and a planarization layer. The display backplane has a first surface, and electrode connecting pads are disposed on the first surface. The planarization layer is stacked on the first surface and defines multiple accommodating holes extending in a thickness direction of the planarization layer. The multiple accommodating holes correspond to the electrode connection pads. Each of the multiple accommodating holes includes a first hole and a second hole. A bonding material is filled in the first hole and in contact with the electrode connection pad. An adhesive is filled in the second hole.

Solder limiting layer for integrated circuit die copper bumps

An apparatus comprises a semiconductor substrate having a device layer, a plurality of metallization layers, a passivation layer, and a metal bump formed on the passivation layer that is electrically coupled to at least one of the metallization layers. The apparatus further includes a solder limiting layer formed on the passivation layer that masks an outer edge of the top surface of the metal bump, thereby making the outer edge of the top surface non-wettable to a solder material.

Interconnect structures for preventing solder bridging, and associated systems and methods

Semiconductor dies having interconnect structures formed thereon, and associated systems and methods, are disclosed herein. In one embodiment, an interconnect structure includes a conductive material electrically coupled to an electrically conductive contact of a semiconductor die. The conductive material includes a first portion vertically aligned with the conductive contact, and a second portion that extends laterally away from the conductive contact. A solder material is disposed on the second portion of the interconnect structure such that the solder material is at least partially laterally offset from the conductive contact of the semiconductor die. In some embodiments, an interconnect structure can further include a containment layer that prevents wicking or other undesirable movement of the solder material during a reflow process.

Packaging devices and methods of manufacture thereof

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad. A second portion of the contact pad is exposed. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to the second portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element includes a hollow region.

Film Scheme for Bumping

A bump structure with a barrier layer, and a method for manufacturing the bump structure, are provided. In some embodiments, the bump structure comprises a conductive pad, a conductive bump, and a barrier layer. The conductive pad comprises a pad material. The conductive bump overlies the conductive pad, and comprises a lower bump layer and an upper bump layer covering the lower bump layer. The barrier layer is configured to block movement of the pad material from the conductive pad to the upper bump layer along sidewalls of the lower bump layer. In some embodiments, the barrier layer is a spacer lining the sidewalls of the lower bump layer. In other embodiments, the barrier layer is between the barrier layer and the conductive pad, and spaces the sidewalls of the lower bump layer from the conductive pad. 1. An integrated circuit comprising:a conductive pad comprising a pad material;a conductive bump overlying the conductive pad, wherein the conductive bump comprises a first bump layer and a second bump layer covering the first bump layer; and a barrier layer configured to block movement of the pad material from the conductive pad to the second bump layer along sidewalls of the first bump layer.2. The integrated circuit according to claim 1 , wherein the barrier layer is between the conductive bump and the conductive pad claim 1 , wherein the barrier layer extends laterally from a first sidewall of the barrier layer to a second sidewall of the barrier layer claim 1 , and wherein the conductive bump is laterally spaced between the first and second sidewalls of the barrier layer.3. The integrated circuit according to claim 2 , wherein the barrier layer cups an underside of the conductive bump.4. The integrated circuit according to claim 2 , further comprising:a first seed layer covering the barrier layer, between the barrier layer and the conductive bump, wherein the first seed layer extends laterally from a first sidewall of the first seed layer to a second sidewall ...

HALBLEITERVORRICHTUNG MIT EINEM DIE-PAD MIT EINER DAMMARTIGEN KONFIGURATION

Eine Halbleitervorrichtung umfasst ein Halbleitersubstrat, einen Leistungstransistor, der in dem Halbleitersubstrat gebildet ist, wobei der Leistungstransistor einen aktiven Bereich umfasst, in dem eine oder mehrere Leistungstransistorzellen gebildet sind, ein erstes Metallpad, das über dem Halbleitersubstrat gebildet ist und im Wesentlichen den gesamten aktiven Bereich des Leistungstransistors abdeckt, wobei das erste Metallpad elektrisch mit einem Source- oder Emitter-Bereich in dem aktiven Bereich des Leistungstransistors verbunden ist, wobei das erste Metallpad einen inneren Bereich aufweist, der seitlich von einem peripheren Bereich umgeben ist, wobei der periphere Bereich dicker als der innere Bereich ist, und eine erste Verbindungsplatte oder einen Halbleiterchip, die bzw. der an dem inneren Bereich des ersten Metallpads durch ein Chipbefestigungsmaterial befestigt ist. Entsprechende Herstellungsverfahren werden ebenfalls beschrieben.

Semiconductor package having an anti-contact layer

A semiconductor package includes a first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip, and a connection member to electrically connect the first semiconductor chip and the second semiconductor chip. The connection member may include a connection pad disposed on the first semiconductor chip, a connection pillar disposed on the second semiconductor chip, and a bonding member to connect the connection pad and the connection pillar. An anti-contact layer may be formed on at least one surface of the connection pad.

Semiconductor device having a die pad with a dam-like configuration

A semiconductor device includes a semiconductor substrate, a power transistor formed in the semiconductor substrate, the power transistor including an active area in which one or more power transistor cells are formed, a first metal pad formed above the semiconductor substrate and covering substantially all of the active area of the power transistor, the first metal pad being electrically connected to a source or emitter region in the active area of the power transistor, the first metal pad including an interior region laterally surrounded by a peripheral region, the peripheral region being thicker than the interior region, and a first interconnect plate or a semiconductor die attached to the interior region of the first metal pad by a die attach material. Corresponding methods of manufacture are also described.

Substrat mit einem Bereich zur Begrenzung eines Lotbereichs

Substrat, das auf der Oberfläche einen ersten Bereich für eine Lötverbindung für mindestens ein Bauteil aufweist, wobei der erste Bereich durch mindestens einen zweiten Bereich auf der Oberfläche des Substrats wenigstens teilweise begrenzt ist, dadurch gekennzeichnet, dass der mindestens eine zweite Bereich lötmittelabweisend ist.

CHIP PACKAGE AND CHIP THEREOF

A microchip is electrically connected to a substrate to become a chip package, preferably for LED. A chip of the package includes a body and at least one electrode which is disposed and exposed on a surface of the body. The electrode includes a confining groove and a confining wall. The confining wall is peripherally located around the confining groove and provided to confine at least one conductive particle of an adhesive in the confining groove. The electrode of the chip is electrically connected to a bonding pad of a substrate via the conductive particle confined in the confining groove.

PACKAGING DEVICES AND METHODS OF MANUFACTURE THEREOF

Chip package and chip thereof

SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME

A semiconductor package comprises a substrate, a pad, a first isolation layer, an interconnection layer, and a conductive post. The substrate has a first surface and a second surface opposite the first surface. The pad has a first portion and a second portion on the first surface of the substrate. The first isolation layer is disposed on the first surface and covers the first portion of the pad, and the first isolation layer has a top surface. The interconnection layer is disposed on the second portion of the pad and has a top surface. The conductive post is disposed on the top surface of the first isolation layer and on the top surface of the interconnection layer. The top surface of the first isolation layer and the top surface of the interconnection layer are substantially coplanar. 1. A semiconductor package , comprising:a substrate having a first surface and a second surface opposite the first surface;a pad including a first portion and a second portion, the pad disposed on the first surface of the substrate;a first isolation layer disposed on the first surface and covering the first portion of the pad, the first isolation layer having a top surface;an interconnection layer disposed on the second portion of the pad and having a top surface; anda conductive post disposed on the top surface of the first isolation layer and on the top surface of the interconnection layer;wherein the top surface of the first isolation layer and the top surface of the interconnection layer are substantially coplanar.2. The semiconductor package claim 1 , wherein the conductive post has a bottom surface including a first part and a second part claim 1 , and the first part contacts the top surface of the interconnection layer and the second part contacts the top surface of the first isolation layer.3. The semiconductor package claim 2 , wherein the area of the first part of the bottom surface of the conductive post is substantially the same as claim 2 , or larger than claim 2 , the ...

INTERCONNECT STRUCTURES FOR PREVENTING SOLDER BRIDGING, AND ASSOCIATED SYSTEMS AND METHODS

Semiconductor dies having interconnect structures formed thereon, and associated systems and methods, are disclosed herein. In one embodiment, an interconnect structure includes a conductive material electrically coupled to an electrically conductive contact of a semiconductor die. The conductive material includes a first portion vertically aligned with the conductive contact, and a second portion that extends laterally away from the conductive contact. A solder material is disposed on the second portion of the interconnect structure such that the solder material is at least partially laterally offset from the conductive contact of the semiconductor die. In some embodiments, an interconnect structure can further include a containment layer that prevents wicking or other undesirable movement of the solder material during a reflow process. 1. A method comprising:forming an interconnect structure on a semiconductor die by plating a conductive material onto a surface of the semiconductor die and at least partially over a conductive contact of the semiconductor die so that the interconnect structure is electrically coupled to the conductive contact;forming a containment layer on at least a first portion of a top surface of the interconnect structure; anddisposing a solder material on a second portion of the top surface of the interconnect structure, wherein the second portion of the top surface of the interconnect structure is at least partially laterally offset from the conductive contact of the semiconductor die, and wherein the containment layer is configured to inhibit wicking of the solder material from the second portion to the first portion of the top surface of the interconnect structure.2. The method of wherein forming the interconnect structure includes—plating a first conductive material onto the conductive contact and an insulating material at the surface of the semiconductor die; andplating a second conductive material onto the first conductive material.3. ...

Manufacturing method of semiconductor package

The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI.

Halbleiterbauelement und Verfahren zu dessen Herstellung

Es werden ein Halbleiterbauelement und ein Verfahren zum Herstellen eines Halbleiterbauelements offenbart. Das Halbleiterbauelement umfasst eine Umverdrahtungsschicht, die über einem Chip angeordnet ist, wobei die Umverdrahtungsschicht eine erste Umverdrahtungsleitung umfasst. Der Halbleiter umfasst ferner eine Isolationsschicht, die über der Umverdrahtungsschicht angeordnet ist, wobei die Isolationsschicht eine erste Öffnung aufweist, die einen ersten Pad-Bereich ausbildet, und eine erste Zwischenverbindung, die sich in der ersten Öffnung und in Kontakt mit der ersten Umverdrahtungsleitung befindet. Die Umverdrahtungsleitung in dem ersten Pad-Bereich ist orthogonal zu einer ersten Richtung auf einen Neutralpunkt des Halbleiterbauelements angeordnet.

Interconnect structures for preventing solder bridging, and associated systems and methods

本文中揭示其上形成有互連結構之半導體晶粒及相關系統及方法。在一項實施例中，一互連結構包含電耦合至一半導體晶粒之一導電接觸件的一導電材料。該導電材料包含與該導電接觸件垂直對準之一第一部分、及橫向延伸遠離該導電接觸件之一第二部分。一焊錫材料安置於該互連結構之該第二部分上使得該焊錫材料至少部分橫向偏離該半導體晶粒之該導電接觸件。在一些實施例中，一互連結構可進一步包含在一回熔程序期間預防該焊錫材料之芯吸或其他非所要移動的一圍阻層。

Integrated circuit packaging system with coupling features and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a wafer substrate having an active side containing a contact; forming a through silicon via extending through the wafer substrate electrically connected to the contact having a via width; forming a first coupling feature extending from a top side of the through silicon via; and forming a second coupling feature on the side of the through silicon via opposite the first coupling feature.

Packaging devices and methods of manufacture thereof

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad. A second portion of the contact pad is exposed. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to the second portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element includes a hollow region.

SEMICONDUCTOR DEVICE HAVING THROUGH ELECTRODE, SEMICONDUCTOR PACKAGE COMPRISING SAME, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

According to the present invention, a semiconductor device having a through-electrode comprises: a substrate having a first surface and a second surface facing the first surface; a plurality of through electrodes penetrating a gap between the first and second surfaces and being spaced apart from each other; a front-side bump coupled to odd-numbered through electrodes among the through electrodes in the first surface; and a backside bump coupled to even-numbered through electrodes among the through electrodes in the second surface facing the first surface wherein the front-side bump is formed. The purpose of the present invention is to provide a semiconductor package comprising a semiconductor device having a through electrode capable of forming a bum structure. COPYRIGHT KIPO 2016 ...

Packaging Devices and Methods of Manufacture Thereof

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad, a second portion of the contact pad being exposed. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to the second portion of the contact pad. A PPI pad is disposed over the passivation layer and is coupled to the PPI line. An insulating material is disposed over the PPI line, the PPI pad being exposed. The insulating material is spaced apart from an edge portion of the PPI pad by a predetermined distance.

Packaging Devices and Methods of Manufacture Thereof

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to a second portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element comprises a first side and a second side coupled to the first side. The first side and the second side of the transition element are non-tangential to the PPI pad.

Methods of forming connector pad structures, interconnect structures, and structures thereof

Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.

Packaging devices and methods of manufacture thereof

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad, a second portion of the contact pad being exposed. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to the second portion of the contact pad. A PPI pad is disposed over the passivation layer and is coupled to the PPI line. An insulating material is disposed over the PPI line, the PPI pad being exposed. The insulating material is spaced apart from an edge portion of the PPI pad by a predetermined distance.

CHIP PACKAGE AND CHIP THEREOF

SUBSTRATE HAVING A SOLDERING RESIST REGION CONSISTING OF OXIDE, SULFIDE OR NITRIDE FOR DELIMITING A SOLDERING REGION AND CORRESPONDING PRODUCTION PROCESS

Substrate (1) (e.g. DBC, lead frame or semiconductor, in particular Si or SiC), which on the surface has a first region (2) for a soldered connection for at least one component (4), wherein the first region (2) is at least partially delimited by at least one second region (3, 5, 6) on the surface of the substrate (1), and wherein the at least one second region (3, 5, 6) repels solder agent and acts as a soldering resist. The height of the second, solder agent-repelling region (3, 5, 6) is greater or smaller than the height of the first region (2). The second, solder agent-repelling region (3, 5, 6) is produced by physical and/or chemical surface treatment, in particular by oxidation or sulfiding or nitriding of materials containing copper, nickel or silver. After the component (4) has been soldered on, the oxide can be removed again, as a result of which a roughened surface, at which a molding compound, for example, finds a better bond during further processing of the substrate (2), is ...

Semiconductor Device and Method of Manufacture Thereof

A semiconductor device and a method of making a semiconductor device are disclosed. The semiconductor device comprises a redistribution layer arranged over a chip, the redistribution layer comprising a first redistribution line. The semiconductor further comprises an isolation layer disposed over the redistribution layer, the isolation layer having a first opening forming a first pad area and a first interconnect located in the first opening and in contact with the first redistribution line. 1. A semiconductor device comprising:a redistribution layer arranged over a chip, the redistribution layer comprising a first redistribution line;an isolation layer disposed over the redistribution layer, the isolation layer having a first opening forming a first pad area; anda first interconnect located in the first opening, the first interconnect being in direct contact with the first redistribution line and directly contacting in the first opening at least partially the isolation layer.2. The semiconductor device according to claim 2 , wherein the redistribution layer comprises a second redistribution line claim 2 , wherein the isolation layer has a second opening forming a second pad area for the second redistribution line claim 2 , wherein a second interconnect is located in the second opening claim 2 , the second interconnect located in the second opening claim 2 , the second interconnect being in direct contact with the first redistribution line and in direct contact with the isolation layer.3. The semiconductor device according to claim 1 , wherein a first width of the first redistribution line is not larger in the first pad area than outside of the first pad area.4. The semiconductor device according to claim 1 , wherein the isolation layer is thicker than about 15 μm.5. The semiconductor device according to claim 1 , wherein the chip comprises an integrated circuit.6. A semiconductor device claim 1 , comprising:a redistribution layer arranged over a chip, the ...

FILM SCHEME FOR BUMPING

A bump structure with a barrier layer, and a method for manufacturing the bump structure, are provided. In some embodiments, the bump structure comprises a conductive pad, a conductive bump, and a barrier layer. The conductive pad comprises a pad material. The conductive bump overlies the conductive pad, and comprises a lower bump layer and an upper bump layer covering the lower bump layer. The barrier layer is configured to block movement of the pad material from the conductive pad to the upper bump layer along sidewalls of the lower bump layer. In some embodiments, the barrier layer is a spacer lining the sidewalls of the lower bump layer. In other embodiments, the barrier layer is between the barrier layer and the conductive pad, and spaces the sidewalls of the lower bump layer from the conductive pad.

반도체 패키지

... 반도체 패키지가 제공된다. 본 발명의 일 실시예에 따른 반도체 패키지는, 제1 반도체 칩; 제1 반도체 칩 상에 위치하는 제2 반도체 칩; 제1 반도체 칩과 제2 반도체 칩을 전기적으로 연결하며, 제1 반도체 칩 상에 위치하는 연결 패드, 제2 반도체 칩 상에 위치하는 연결 필라, 및 연결 패드와 연결 필라를 연결하는 접합 부재를 포함하는 연결 부재; 및 연결 패드의 적어도 일 면 상에 위치하는 접촉 방지층을 포함한다.

Solder structures for out of plane connections

Methods of forming a solder structure may include providing a wafer including a plurality of die therein, and a solder wettable pad may be formed on one of the die adjacent an edge of the die. The solder wettable pad may have a length parallel to the edge of the die and a width perpendicular to the edge of the die wherein the length parallel to the edge of the die is greater than the width perpendicular to the edge of the die. A solder bump may be plated on the solder wettable pad, and the die may be separated from the wafer along the edge of the die after plating the solder bump on the solder wettable pad. Moreover, the solder bump may be reflowed on the solder wettable pad so that the solder structure extends laterally from the solder wettable pad beyond the edge of the die after separating the die from the wafer. Related structures are also discussed.

Halbleiterbauelement und Verfahren zu dessen Herstellung

Halbleiterbauelement (100, 200, 300), umfassend: eine Umverdrahtungsschicht, die über einem Chip (110, 320) oder über einem Chip (320) und einem Fan-Out-Gebiet (310) angeordnet ist, wobei die Umverdrahtungsschicht eine erste Umverdrahtungsleitung (150, 151, 152, 153) umfasst; eine Isolationsschicht (160), die über der Umverdrahtungsschicht angeordnet ist, wobei die Isolationsschicht (160) eine auf einer Oberfläche des Halbleiterbauelements (100, 200, 300) angeordnete erste Öffnung aufweist, die einen ersten Pad-Bereich (170, 171, 172, 173) ausbildet; und eine erste Zwischenverbindung (180, 181, 182, 183), die sich in der ersten Öffnung und in Kontakt mit der ersten Umverdrahtungsleitung (150, 151, 152, 153) befindet, wobei die erste Umverdrahtungsleitung in dem ersten Pad-Bereich (170, 171, 172, 173) orthogonal zu einer von der ersten Öffnung zum Mittelpunkt der Oberfläche des Halbleiterbauelements verlaufenden ersten Richtung (AR, AR1, AR2, AR3) angeordnet ist, und wobei die erste Umverdrahtungsleitung ...

SOLDER STRUCTURES FOR OUT OF PLANE CONNECTIONS AND RELATED METHODS

Methods of forming a solder structure may include providing a wafer including a plurality of die therein, and a solder wettable pad may be formed on one of the die adjacent an edge of the die. The solder wettable pad may have a length parallel to the edge of the die and a width perpendicular to the edge of the die wherein the length parallel to the edge of the die is greater than the width perpendicular to the edge of the die. A solder bump may be plated on the solder wettable pad, and the die may be separated from the wafer along the edge of the die after plating the solder bump on the solder wettable pad. Moreover, the solder bump may be reflowed on the solder wettable pad so that the solder structure extends laterally from the solder wettable pad beyond the edge of the die after separating the die from the wafer. Related structures are also discussed.

SEMICONDUCTOR PACKAGING AND MANUFACTURING METHOD THEREOF

The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI. 1. A method of manufacturing a semiconductor package , comprising:patterning a metal derivative in a second region of a post-passivation interconnect (PPI);forming a flux layer in a first region of the PPI, wherein the first region is surrounded by the second region;dropping a solder ball on the flux layer; andforming electrical connection between the solder ball and the PPI.2. The method of manufacturing a semiconductor package in claim 1 , wherein the to patterning the metal derivative in the second region of the PPI further comprising forming a mask layer over the PPI.3. The method of manufacturing a semiconductor package in claim 2 , wherein the forming the mask layer over the PPI comprises forming a mask layer on the PPI.4. The method of manufacturing a semiconductor package in claim 2 , wherein the forming the mask layer over the PPI comprises positioning a first stencil plate over the PPI.5. The method of manufacturing a semiconductor package in claim 1 , wherein the patterning the metal derivative in the second region of the PPI comprises an oxygen plasma ...

Semiconductor device and its manufacture method capable of preventing short circuit of electrodes when semiconductor device is mounted on sub-mount substrate

A confronting surface of a substrate faces a first surface of a semiconductor element. Extension layers are formed on the substrate at positions facing electrodes on the semiconductor element. A levee film is disposed on one of the confronting surface and the first surface. Openings are formed through the levee film. Connection members which is filled but is not completely filled in the openings connect the electrodes and the extension layers.

SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

This application relates to a semiconductor device comprising a semiconductor chip, a molded body covering the semiconductor chip, wherein the molded body comprises an array of molded structure elements, and first solder elements engaged with the molded structure elements. 1. A method , comprising:providing a semiconductor chip;applying mold material over at least a portion of the semiconductor chip to mold a molded body;generating at least one molded structure element on the molded body; andapplying solder over the molded structure element.2. The method according to claim 1 , wherein the molded structure element is generated during the molding of the molded body.3. The method according to claim 1 , wherein the of molded structure element is generated after the molding of the molded body.4. The method according to claim 1 , wherein the generating act generates a plurality of molded structure elements on the molded body claim 1 , and the applying act applies solder over each of the plurality of molded structure elements.5. The method according to claim 4 , further comprising:placing the semiconductor chip on a carrier, the carrier including at least one recess; andfilling the at least one recess with mold material to form the at least one molded structure element.6. The method according to claim 4 , wherein the applying act provides a molded body having a surface coplanar with a surface of the semiconductor chip.7. The method according to claim 6 , wherein the surface of the semiconductor includes at least one connection element.8. A method claim 6 , comprising:providing a plurality of semiconductor chips;applying mold material over the plurality of semiconductor chips to mold a molded workpiece;generating an array of molded structure elements on the molded workpiece; andapplying solder elements over the molded structure elements.9. The method according to claim 8 , wherein the array of molded structure elements is generated during the molding of the molded workpiece ...

Copper ring solder mask defined ball grid array pad

A ball grid array device includes a substrate, further including a first major surface and a second major surface. An array of pads is positioned on one of the first major surface or the second major surface. At least some of the pads include a raised ring. The raised ring circumscribes the pad or surrounds an interior pad or land on the substrate.

The semiconductor device package and manufacturing method thereof

Bump stress mitigation layer for integrated circuits

Packaging devices

Packaging Devices and Methods of Manufacture Thereof

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad. A second portion of the contact pad is exposed. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to the second portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element includes a hollow region.

3DI Solder Cup

A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices. 1. A device comprising:a substrate;an electrical interconnect within the substrate;a barrier structure electrically connected to the electrical interconnect, the barrier structure having a funnel-shaped recess defined therein; andsolder positioned within the funnel-shaped recess of the barrier structure.2. The device of claim 1 , further comprising:a copper structure positioned within the funnel-shaped recess of the barrier structure; anda nickel structure positioned within the funnel-shaped recess of the barrier structure.3. The device of claim 1 , wherein the barrier structure comprises tantalum claim 1 , tungsten claim 1 , titanium nitride claim 1 , or combinations thereof.4. The device of claim 1 , further comprising:a semiconductor device having a via and an under bump metal (UBM) electrically connected to the via, and wherein the UBM is encased in the solder within the funnel-shaped recess of the barrier structure.5. The device of claim 4 , wherein the UBM includes angled sidewalls.6. The device of claim 5 , wherein the angled sidewalls of the UBM are configured to produce a wetting force between the substrate and the semiconductor device during thermal compression bonding.7. The device of claim 4 , wherein the ...

INTERCONNECT STRUCTURES FOR PREVENTING SOLDER BRIDGING, AND ASSOCIATED SYSTEMS AND METHODS

Semiconductor dies having interconnect structures formed thereon, and associated systems and methods, are disclosed herein. In one embodiment, an interconnect structure includes a conductive material electrically coupled to an electrically conductive contact of a semiconductor die. The conductive material includes a first portion vertically aligned with the conductive contact, and a second portion that extends laterally away from the conductive contact. A solder material is disposed on the second portion of the interconnect structure such that the solder material is at least partially laterally offset from the conductive contact of the semiconductor die. In some embodiments, an interconnect structure can further include a containment layer that prevents wicking or other undesirable movement of the solder material during a reflow process. 1. A semiconductor die , comprising:a substrate having a center portion and an outer edge portion;an insulating material over a surface of the substrate;an electrically conductive contact at the surface of the substrate;an interconnect structure electrically coupled to the conductive contact, wherein the interconnect structure includes a top surface having a first portion and a second portion, wherein the first portion is vertically aligned with the conductive contact, and wherein the second portion extends (a) laterally away from the first portion in a direction away from the center portion and toward the outer edge portion of the substrate and (b) over at least a portion of the insulating material; anda solder material disposed at least partially on the second portion of the top surface.2. The semiconductor die of wherein the conductive contact is exposed at an opening in the insulating material.3. The semiconductor die of claim 1 , further comprising a containment layer over substantially all of the first portion of the top surface of the interconnect structure.4. The semiconductor die of wherein the containment layer is ...

Methods of Forming Connector Pad Structures, Interconnect Structures, and Structures Thereof

Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed. 1. A semiconductor device comprising:a first redistribution layer (RDL);a metallization pad disposed over a portion of the first RDL, an entire upper surface of the metallization pad having a surface roughness, wherein the surface roughness is an average surface roughness of approximately 0.18 μm to approximately 0.25 μm;an intermetallic compound (IMC) disposed over a portion of the upper surface of the metallization pad; anda connector disposed over the IMC.2. The semiconductor device of claim 1 , further comprising an insulating layer extending over a portion of the upper surface of the metallization pad.3. The semiconductor device of claim 2 , wherein the insulating layer comprises a polymer layer.4. The semiconductor device of claim 2 , wherein the insulating layer covers all edges of the metallization pad.5. The semiconductor device of claim 2 , wherein the insulating layer extends along sidewalls of the metallization pad.6. The semiconductor device of claim 1 , further comprising:an integrated circuit die coupled to the RDL, wherein portions of the RDL are coupled to contact pads of the integrated circuit die;molding material disposed around the integrated circuit die, the RDL extending over the integrated circuit die and the molding material; andplurality of through vias disposed within the molding material.7. A semiconductor device comprising:an integrated circuit die comprising a first connector pad and a second connector pad;a first metallization pad electrically coupled to the first connector pad, the first metallization ...

Method for aligning micro-electronic components

Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force. By applying appropriate charges on the conductor lines, electrostatic self-alignment is realized, which improves ...

Film scheme for bumping

A bump structure with a barrier layer, and a method for manufacturing the bump structure, are provided. In some embodiments, the bump structure comprises a conductive pad, a conductive bump, and a barrier layer. The conductive pad comprises a pad material. The conductive bump overlies the conductive pad, and comprises a lower bump layer and an upper bump layer covering the lower bump layer. The barrier layer is configured to block movement of the pad material from the conductive pad to the upper bump layer along sidewalls of the lower bump layer. In some embodiments, the barrier layer is a spacer lining the sidewalls of the lower bump layer. In other embodiments, the barrier layer is between the barrier layer and the conductive pad, and spaces the sidewalls of the lower bump layer from the conductive pad.

Semiconductor chip and method of manufacturing the same

A chip includes a substrate and a dielectric layer disposed on the substrate. The dielectric layer includes a first dielectric region and a second dielectric region surrounding an outer periphery of the first dielectric region. A top surface of the first dielectric region is disposed below a top surface of the second dielectric region. The chip further includes a metal pad disposed in a through-hole in the first dielectric region and contacting a portion of the substrate.

Copper ring solder mask defined ball grid array pad

A ball grid array device includes a substrate, further including a first major surface and a second major surface. An array of pads is positioned on one of the first major surface or the second major surface. At least some of the pads include a raised ring. The raised ring circumscribes the pad or surrounds an interior pad or land on the substrate.

FLIP-CHIP HYBRIDISATION OF TWO MICROELECTRONIC COMPONENTS USING A UV ANNEAL

This process for fabricating a microelectronic device comprising a first component (12) hybridised with a second component (14) by means of electrical interconnects consists in: producing first and second components (12, 14), the second component (14) being transparent to ultraviolet radiation at least in line with locations provided for the interconnects; forming interconnecting elements (22) comprising copper oxide on the second component (14) in the locations provided for the interconnects; placing the first and second components (12, 14) one on the other; and applying ultraviolet radiation, through the second component (14), to the elements comprising copper oxide so as to implement an ultraviolet anneal converting the copper oxide into copper.

반도체 장치, 반도체 장치의 제조 방법 및 배선 기판의 제조 방법

반도체 장치는 기판의 전극 패드부상에 형성된 배리어 메탈층과, 배리어 메탈층 윗면의 중앙부에 형성되고, 외경보다도 작은 외경을 갖고서 형성된 솔더층으로 이루어지는 솔더 범프를 구비한다. The semiconductor device has a barrier metal layer formed on the electrode pad portion of the substrate and a solder bump formed of a solder layer formed on the central portion of the upper surface of the barrier metal layer and formed with an outer diameter smaller than the outer diameter.

BUMP STRESS MITIGATION LAYER FOR INTEGRATED CIRCUITS

Semiconductor device and its manufacture method capable of preventing short circuit of electrodes when semiconductor device is mounted on sub-mount substrate

A confronting surface of a substrate faces a first surface of a semiconductor element. Extension layers are formed on the substrate at positions facing electrodes on the semiconductor element. A levee film is disposed on one of the confronting surface and the first surface. Openings are formed through the levee film. Connection members which is filled but is not completely filled in the openings connect the electrodes and the extension layers.

COUPLING OF INTEGRATED CIRCUITS (ICS) THROUGH A PASSIVATION-DEFINED CONTACT PAD

Components may be placed on an active side of a wafer as part of wafer-level chip scale packaging (WLCSP) for use in electronic devices. Pad layouts for the components on an active side of a wafer may be passivation-defined by forming a conductive terminal over a first dielectric layer and a forming a passivating, second dielectric layer over the conductive terminal. Openings formed in the second dielectric layer define component contacts to the conductive terminal and circuitry on the wafer coupled to the conductive terminal. Trenches may be used between pairs of contact pads to further reduce issues resulting from short circuits and/or underfills. A conductive pad may further be deposited in the opening to form underbump metallization (UBM) for coupling the component to the wafer.

For aligning a microelectronic assembly

Interconnect structures for preventing solder bridging, and associated systems and methods

Semiconductor dies having interconnect structures formed thereon, and associated systems and methods, are disclosed herein. In one embodiment, an interconnect structure includes a conductive material electrically coupled to an electrically conductive contact of a semiconductor die. The conductive material includes a first portion vertically aligned with the conductive contact, and a second portion that extends laterally away from the conductive contact. A solder material is disposed on the second portion of the interconnect structure such that the solder material is at least partially laterally offset from the conductive contact of the semiconductor die. In some embodiments, an interconnect structure can further include a containment layer that prevents wicking or other undesirable movement of the solder material during a reflow process.

Semiconductor Device and Method of Manufacture Thereof

A semiconductor device and a method of making a semiconductor device are disclosed. The semiconductor device comprises a redistribution layer arranged over a chip, the redistribution layer comprising a first redistribution line. The semiconductor further comprises an isolation layer disposed over the redistribution layer, the isolation layer having a first opening forming a first pad area and a first interconnect located in the first opening and in contact with the first redistribution line. The redistribution line in the first pad area is arranged orthogonal to a first direction to a neutral point of the semiconductor device.

Flip chip

A flip chip includes a substrate, an electrode pad layer stacked over the substrate, a passivation layer stacked at both ends of the electrode pad layer, an under bump metallurgy (UBM) layer stacked over the electrode pad layer and the passivation layer, and a bump formed over the UBM layer. The width of an opening on which the passivation layer is not formed over the electrode pad layer is greater than the width of the bump. The flip chip can prevent a crack from being generated in the pad upon ultrasonic bonding.

Semiconductor device, method of manufacturing the same, and method of manufacturing wiring board

A semiconductor device includes: a solder bump including a barrier metal layer formed on an electrode pad portion of a substrate, and a solder layer formed at a central portion of an upper surface of the barrier metal layer so as to have a smaller outer diameter than that of the barrier metal layer.

Methods of forming connector pad structures and interconnect structures, and the structures

3DI SOLDER CUP

本發明揭示一種基板或半導體裝置、半導體裝置總成及一種用於形成包含一焊料杯上之一障壁之一半導體裝置總成之方法。該半導體裝置總成包含安置於另一基板上面之一基板。至少一焊料杯自一基板朝向另一基板上之一凸塊下金屬(UBM)延伸。該焊料杯之外部上之該障壁可為一間隔件以控制該等基板之間的一接合線。在形成一半導體裝置總成期間，該障壁可減少焊料橋接。該障壁可在形成一半導體裝置總成時有助於使該焊料杯與一UBM對準且可減少歸因於基板及/或半導體裝置之橫向移動之失準。

SEMICONDUCTOR DEVICE

A semiconductor device may include a semiconductor substrate, a first bonding pad provided on an upper surface of the semiconductor substrate and constituted of a metal including aluminum, a second bonding pad provided on the upper surface of the semiconductor substrate, and a first protrusion protruding from an upper surface of the first bonding pad. The first protrusion may be provided on the upper surface of the first bonding pad only at a position adjacent to a peripheral edge of the first bonding pad, the peripheral edge of the first bonding pad may be opposed to the second bonding pad.

Methods of providing solder structures for out plane connections

Methods of forming a solder structure may include providing a wafer including a plurality of die therein, and a solder wettable pad may be formed on one of the die adjacent an edge of the die. The solder wettable pad may have a length parallel to the edge of the die and a width perpendicular to the edge of the die wherein the length parallel to the edge of the die is greater than the width perpendicular to the edge of the die. A solder bump may be plated on the solder wettable pad, and the die may be separated from the wafer along the edge of the die after plating the solder bump on the solder wettable pad. Moreover, the solder bump may be reflowed on the solder wettable pad so that the solder structure extends laterally from the solder wettable pad beyond the edge of the die after separating the die from the wafer. Related structures are also discussed.

Semiconductor packaging and manufacturing method thereof

The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI.

SEMICONDUCTOR PACKAGING AND MANUFACTURING METHOD THEREOF

The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI.

3DI solder cup

A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices.

Bump stress mitigation layer for integrated circuits

Solder structures for out of plane connections and related methods

Methods of forming a solder structure may include providing a wafer including a plurality of die therein, and a solder wettable pad may be formed on one of the die adjacent an edge of the die. The solder wettable pad may have a length parallel to the edge of the die and a width perpendicular to the edge of the die wherein the length parallel to the edge of the die is greater than the width perpendicular to the edge of the die. A solder bump may be plated on the solder wettable pad, and the die may be separated from the wafer along the edge of the die after plating the solder bump on the solder wettable pad. Moreover, the solder bump may be reflowed on the solder wettable pad so that the solder structure extends laterally from the solder wettable pad beyond the edge of the die after separating the die from the wafer. Related structures are also discussed.

Packaging devices and methods of manufacture thereof

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to a second portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element comprises a first side and a second side coupled to the first side. The first side and the second side of the transition element are non-tangential to the PPI pad.

SEMICONDUCTOR DEVICES HAVING THROUGH ELECTRODES, SEMICONDUCTOR PACKAGES INCLUDING THE SAME, METHODS OF MANUFACTURING THE SAME, ELECTRONIC SYSTEMS INCLUDING THE SAME, AND MEMORY CARDS INCLUDING THE SAME

A semiconductor device includes a substrate having a first surface and a second surface that are opposite to each other, a plurality of through electrodes penetrating the substrate and extending from the first surface to the second surface, front-side bumps disposed on the first surface and connected to odd-numbered through electrodes among the plurality of through electrodes, and backside bumps disposed on the second surface and connected to even-numbered through electrodes among the plurality of through electrodes. Related semiconductor packages, fabrication methods, electronic systems and memory cards are also provided. 1. A semiconductor package comprising:a first semiconductor chip including:a first substrate having a first surface and a second surface that are opposite to each other;a plurality of first through electrodes penetrating the first substrate and being spaced apart from each other;a plurality of first front-side bumps disposed on the first surface of the first substrate and connected to first odd-numbered through electrodes among the first through electrodes;a plurality of first backside bumps disposed on the second surface of the first substrate and connected to first even-numbered through electrodes among the first through electrodes; anda second semiconductor chip including:a second substrate having a first surface and a second surface that are opposite to each other;a plurality of second through electrodes penetrating the second substrate and being spaced apart from each other;a plurality of second front-side bumps disposed on the first surface of the second substrate and connected to second odd-numbered through electrodes among the second through electrodes; anda plurality of second backside bumps disposed on the second surface of the second substrate and connected to second even-numbered through electrodes among the second through electrodes,wherein the first and second semiconductor chips are combined with each other so that the first surface ...

Solder structures for out of plane connections

Methods of forming a solder structure may include providing a wafer including a plurality of die therein, and a solder wettable pad may be formed on one of the die adjacent an edge of the die. The solder wettable pad may have a length parallel to the edge of the die and a width perpendicular to the edge of the die wherein the length parallel to the edge of the die is greater than the width perpendicular to the edge of the die. A solder bump may be plated on the solder wettable pad, and the die may be separated from the wafer along the edge of the die after plating the solder bump on the solder wettable pad. Moreover, the solder bump may be reflowed on the solder wettable pad so that the solder structure extends laterally from the solder wettable pad beyond the edge of the die after separating the die from the wafer. Related structures are also discussed.

METHODS OF FORMING CONNECTOR PAD STRUCTURES, INTERCONNECT STRUCTURES, AND STRUCTURES THEREOF

Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed. 1. A semiconductor device comprising:an integrated circuit die;a metallization pad electrically connected to the integrated circuit die, an upper surface of the metallization pad having an average surface roughness of 0.18 μm to 0.25 μm;a connector on a first portion of the upper surface of the metallization pad;a polymer layer on a second portion of the upper surface of the metallization pad and a sidewall of the metallization pad; andan intermetallic compound (IMC) between the first portion of the upper surface of the metallization pad and the connector.2. The semiconductor device of claim 1 , wherein the metallization pad is in a dielectric layer claim 1 , and wherein the polymer layer extends between a sidewall of the metallization pad and a sidewall of the dielectric layer.3. The semiconductor device of further comprising:a first redistribution line (RDL) on a first side of the integrated circuit die and electrically connected the metallization pad, the metallization pad is on the first side of the integrated circuit die;a molding compound encapsulating the integrated circuit die;a though via extending through the molding compound;a second RDL on a second side of the integrated circuit die and electrically connected to the first RDL through the through via, the second side of the integrated circuit die being opposite the first side; anda second metallization pad electrically connected to the second RDL, the second metallization pad is on the second side of the integrated circuit die.4. The semiconductor device of claim 3 , ...

SHEET MOLDING PROCESS FOR WAFER LEVEL PACKAGING

Discussed generally herein are methods and devices including or providing a redistribution layer device without under ball metallization. A device can include a substrate, electrical interconnect circuitry in the substrate, redistribution layer (RDL) circuitry electrically connected to the electrical interconnect circuitry, a conductive bump electrically connected to the RDL circuitry, the conductive bump interfacing directly with the RDL circuitry, and a sheet molding material over the substrate. 1. A device comprising:a substrate;electrical interconnect circuitry in the substrate;redistribution layer (RDL) circuitry electrically connected to the electrical interconnect circuitry;a conductive bump electrically connected to the RDL circuitry, the conductive bump forming a direct interface with the RDL circuitry through a flux; anda molding material over the substrate wherein the molding material is a backside coating film.2. The device of claim 1 , further comprising:patterned passivation material on portions of the RDL circuitry and portions of the substrate between the molding material and the substrate.3. The device of claim 2 , wherein the molding material is a planarized molding material.4. The device of claim 3 , wherein the molding material includes first holes therethrough claim 3 , the passivation material includes second holes therethrough claim 3 , the first holes and the second holes are at least partially aligned claim 3 , and the conductive bump is situated in the aligned first and second holes claim 3 , in direct contact with the RDL circuitry claim 3 , and does not include an under bump metallization (UBM).5. The device of claim 4 , wherein the first holes are laser ablated leaving burn marks on the molding material on an exposed surface of the molding material and abutting the conductive bump.6. The device of claim 1 , wherein the RDL circuitry includes one or more pads formed thereon claim 1 , the one or more pads including copper or aluminum claim ...

Substrate structure with selective surface finishes for flip chip assembly

The present disclosure relates to a substrate structure with selective surface finishes used in flip chip assembly, and a process for making the same. The disclosed substrate structure includes a substrate body, a metal structure with a first finish area and a second finish area, a first surface finish, and a second surface finish. The metal structure is formed on a top surface of the substrate body, the first surface finish is formed over the first finish area of the metal structure, and the second surface finish is formed over the second finish area of the metal structure. The first surface finish is different from the second surface finish.

3DI Solder Cup

A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices. 1. (canceled)2. The assembly of claim 8 , wherein the solder cup and UBM form an interconnect that electrically connects the first substrate and the second substrate.3. The assembly of claim 2 , wherein the first substrate further comprises a first semiconductor device and the second substrate further comprises a second semiconductor device.4. The assembly of claim 3 , wherein the second end of the barrier engages the first surface of the first semiconductor device and supports the second semiconductor device.5. (canceled)6. The assembly of claim 8 , wherein the second end of the barrier surrounds the UBM.7. (canceled)8. A semiconductor device assembly comprising:a first substrate having a first surface and a second surface opposite the first surface, the first surface having at least one under bump metal (UBM) disposed thereon;a second substrate having a first surface and a second surface opposite the first surface, the second substrate disposed over the first substrate, the second substrate having at least one solder cup on the second surface, the at least one solder cup comprising a barrier having a first end proximal to the second surface of the second substrate and a second end distal to the second surface of ...

3DI Solder Cup

A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices.

Flip-Chip Hybridisation Of Two Microelectronic Components Using A UV Anneal

A method of manufacturing a microelectronic device including a first component hybridized with a second component via electric interconnects, involves the steps of: (i) forming the first and second components, the second component being transparent to ultraviolet radiation at least in line with locations provided for the interconnects; (ii) forming interconnection elements including copper oxide on the second component at the locations provided for the interconnects; (iii) placing the first and second components on each other; and (iv) applying the ultraviolet radiation through the second component on the elements including copper oxide to implement an ultraviolet anneal converting copper oxide into copper.

Film scheme for bumping

A bump structure with a barrier layer, and a method for manufacturing the bump structure, are provided. In some embodiments, the bump structure comprises a conductive pad, a conductive bump, and a barrier layer. The conductive pad comprises a pad material. The conductive bump overlies the conductive pad, and comprises a lower bump layer and an upper bump layer covering the lower bump layer. The barrier layer is configured to block movement of the pad material from the conductive pad to the upper bump layer along sidewalls of the lower bump layer. In some embodiments, the barrier layer is a spacer lining the sidewalls of the lower bump layer. In other embodiments, the barrier layer is between the barrier layer and the conductive pad, and spaces the sidewalls of the lower bump layer from the conductive pad.

CONDUCTIVE PILLAR SHAPED FOR SOLDER CONFINEMENT

Pillar-type connections and methods for fabricating a pillar-type connection. A conductive layer is formed on a bond pad. A second conductive layer is formed on the first conductive layer to define a conductive pillar. The conductive pillar includes a non-planar top surface defining a recess. The recess may receive a portion of a solder body used to connect the conductive pillar with a package. 2. The method of wherein forming the conductive pillar on the bond pad comprises: forming a plating mask that includes an opening aligned with the bond pad and a sacrificial plug within the opening.3. The method of wherein the first conductive layer is formed inside the opening in a space between the plating mask surrounding the opening and the sacrificial plug.4. The method of wherein the sacrificial plug has a top surface claim 3 , the first conductive layer has a top surface claim 3 , and forming the first conductive layer inside the opening comprises:depositing the first conductive layer such that the top surface of the first conductive layer is recessed relative to the top surface of the sacrificial plug.5. The method of wherein the first conductive layer is comprised of copper claim 4 , and the first conductive layer is deposited by electrodeposition.6. The method of further comprising:after the first conductive layer is formed, removing the sacrificial plug from within the opening.7. The method of wherein the second conductive layer is formed inside the opening and in contact with the first conductive layer after the sacrificial plug is removed.8. The method of wherein the second conductive layer includes the non-planar top surface and the recess.9. The method of wherein forming the plating mask further comprises:forming the opening in the plating mask and the sacrificial plug using a half-tone photoresist process.10. The method of further comprising: forming a solder body on the conductive pillar claim 1 , wherein a portion of the solder body is received in the recess ...

Film scheme for bumping

A bump structure with a barrier layer, and a method for manufacturing the bump structure, are provided. In some embodiments, the bump structure comprises a conductive pad, a conductive bump, and a barrier layer. The conductive pad comprises a pad material. The conductive bump overlies the conductive pad, and comprises a lower bump layer and an upper bump layer covering the lower bump layer. The barrier layer is configured to block movement of the pad material from the conductive pad to the upper bump layer along sidewalls of the lower bump layer. In some embodiments, the barrier layer is a spacer lining the sidewalls of the lower bump layer. In other embodiments, the barrier layer is between the barrier layer and the conductive pad, and spaces the sidewalls of the lower bump layer from the conductive pad.

Semiconductor device

Semiconductor device, method for manufacturing semiconductor device, and method for manufacturing wiring board

Semiconductor device package and method of manufacturing the same

一种半导体封装及其制造方法，所述半导体封装包括衬底、接垫、第一绝缘层、互连层和预先形成的导电柱。所述第一绝缘层安置于所述衬底上，且包括开口。所述接垫安置于所述衬底上且从所述开口暴露。所述互连层安置于所述接垫上。所述预先形成的导电柱，其包括底部表面，所述底部表面具有安置于所述互连层上的第一部分以及安置于所述第一绝缘层上且接触所述第一绝缘层的第二部分。

Semiconductor device package and method of manufacturing the same

一种半导体封装及其制造方法，所述半导体封装包括衬底、接垫、第一绝缘层、互连层和预先形成的导电柱。所述第一绝缘层安置于所述衬底上，且包括开口。所述接垫安置于所述衬底上且从所述开口暴露。所述互连层安置于所述接垫上。所述预先形成的导电柱，其包括底部表面，所述底部表面具有安置于所述互连层上的第一部分以及安置于所述第一绝缘层上且接触所述第一绝缘层的第二部分。

Semiconductor device and method of manufacture thereof

A semiconductor device and a method of making a semiconductor device are disclosed. The semiconductor device comprises a redistribution layer arranged over a chip, the redistribution layer comprising a first redistribution line. The semiconductor further comprises an isolation layer disposed over the redistribution layer, the isolation layer having a first opening forming a first pad area and a first interconnect located in the first opening and in contact with the first redistribution line. The redistribution line in the first pad area is arranged orthogonal to a first direction to a neutral point of the semiconductor device.

Flip-chip connection of two microelectronic components using a uv anneal

Interconnect structures for preventing solder bridging, and associated systems and methods

Semiconductor dies having interconnect structures formed thereon, and associated systems and methods, are disclosed herein. In one embodiment, an interconnect structure includes a conductive material electrically coupled to an electrically conductive contact of a semiconductor die. The conductive material includes a first portion vertically aligned with the conductive contact, and a second portion that extends laterally away from the conductive contact. A solder material is disposed on the second portion of the interconnect structure such that the solder material is at least partially laterally offset from the conductive contact of the semiconductor die. In some embodiments, an interconnect structure can further include a containment layer that prevents wicking or other undesirable movement of the solder material during a reflow process.

Flip chip

本发明一实施例的倒装芯片，其特征在于，包括：基板；层压在所述基板上的电极焊盘层；层压在所述电极焊盘层的两侧末端的钝化层；层压在所述电极焊盘层及所述钝化层上的UMB层；形成在所述UBM层上的凸点，所述电极焊盘层上未层压所述钝化层的开口的宽度大于所述凸点的宽度。本发明的倒装芯片能够防止超声波焊接时焊盘上产生裂纹。

Packaging devices and methods of manufacture thereof

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to a second portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element comprises a first side and a second side coupled to the first side. The first side and the second side of the transition element are non-tangential to the PPI pad.

Semiconductor Device and Methods of Manufacturing Semiconductor Devices

This application relates to a semiconductor device comprising a semiconductor chip, a molded body covering the semiconductor chip, wherein the molded body comprises an array of molded structure elements, and first solder elements engaged with the molded structure elements.

칩-투-웨이퍼 장치용 반도체 장치 및 언더필 댐 형성 방법

반도체 장치는 감지 영역이 있는 반도체 다이를 갖는다. 댐 벽은 감지 영역에 근접한 반도체 다이 위에 형성된다. 일 실시예에서, 댐 벽은 수직 세그먼트 및 측면 윙을 갖는다. 댐 벽은 단일체로서 복수의 수직 세그먼트와 통합된 복수의 둥근 세그먼트를 가질 수 있다. 대안적으로, 댐 벽은 2개 이상의 중첩 행으로 배열된 복수의 개별 수직 세그먼트를 갖는다. 복수의 전도성 포스트가 반도체 다이 위에 형성된다. 반도체 다이 위에 전기 구성요소가 배치된다. 반도체 다이 및 전기 구성요소는 기판 위에 배치된다. 댐 벽 외부의 기판 위에 절연 층이 형성된다. 반도체 다이와 기판 사이에 언더필 재료가 증착된다. 댐 벽과 절연 층은 언더필 재료가 감지 영역의 일부와 접촉하는 것을 방지한다.

半導体装置

【課題】 ボンディングパッド間の短絡を抑制するとともに、ワイヤのボンディングの制御を簡易とする技術を提供する。【解決手段】 半導体装置は、半導体基板と、前記半導体基板の上面に設けられており、アルミニウムを含有する金属によって構成されている第１ボンディングパッドと、前記半導体基板の前記上面に設けられている第２ボンディングパッドと、前記第１ボンディングパッドの上面から突出する第１凸部、を有している。前記第１凸部が、前記第１ボンディングパッドの前記上面のうちの、前記第１ボンディングパッドの前記第２ボンディングパッドに対向する外周縁に隣接する位置のみに設けられている。【選択図】図３

칩 패키지 구조 및 그 칩

칩 패키지 구조는 마이크로 칩을 기판에 전기적으로 연결시키기 위한 것으로, 특히 LED에 응용되고, 상기 칩 패키지 구조의 칩은 본체 및 적어도 하나의 전극을 포함하며, 상기 전극은 상기 본체의 표면에 설치되며, 또한 상기 표면으로부터 노출되고, 상기 전극은 위치한정 홈 및 상기 위치한정 홈의 주변에 위치하는 위치한정 벽을 구비하며, 상기 위치한정 벽은 접착제 중의 적어도 하나의 도전성 입자를 상기 위치한정 홈에 위치 한정시키며, 또한 상기 칩은 상기 위치한정 홈에 위치한 상기 도전성 입자를 통해 상기 전극과 기판의 접속패드를 전기적으로 연결시킨다.

Semiconductor chip and method of manufacturing the same

A chip includes a substrate and a dielectric layer disposed on the substrate. The dielectric layer includes a first dielectric region and a second dielectric region surrounding an outer periphery of the first dielectric region. A top surface of the first dielectric region is disposed below a top surface of the second dielectric region. The chip further includes a metal pad disposed in a through-hole in the first dielectric region and contacting a portion of the substrate.

用於晶片對晶圓裝置之形成有底部填充阻擋件的半導體裝置及方法

一種半導體裝置，其具有半導體晶粒，半導體晶粒具有敏感區域。阻擋壁在半導體晶粒上方靠近敏感區域形成。在實施例中，阻擋壁具有垂直區段及側翼。阻擋壁能具有與複數個垂直區段整合為一單體本體之複數個圓形區段。替代地，阻擋壁具有以兩個或多於兩個重疊列布置之複數個分開的垂直區段。複數個導體柱形成於半導體晶粒上方。電組件設置於半導體晶粒上方。半導體晶粒該組件設置於基板上方。絕緣層在基板上方而於阻擋壁外形成。底部填充材料沉積於半導體晶粒與基板之間。阻擋壁及絕緣層抑制底部填充材料接觸敏感區域之任何部分。

用于预防焊料桥接的互连结构及相关系统及方法

本文中揭示其上形成有互连结构的半导体裸片及相关系统及方法。在一个实施例中，互连结构包含电耦合到半导体裸片的导电接点的导电材料。所述导电材料包含与所述导电接点垂直对准的第一部分，及横向延伸远离所述导电接点的第二部分。焊料材料安置于所述互连结构的所述第二部分上使得所述焊料材料至少部分横向偏离所述半导体裸片的所述导电接点。在一些实施例中，互连结构可进一步包含在回流工艺期间预防所述焊料材料的芯吸或其它非所要移动的围阻层。

为芯片到晶片器件形成底部填充坝的半导体器件和方法

为芯片到晶片器件形成底部填充坝的半导体器件和方法。一种半导体器件具有带敏感区域的半导体管芯。在半导体管芯上形成靠近敏感区域的坝壁。在一个实施例中，坝壁具有垂直区段和侧翼。坝壁可以具有多个圆形区段，所述多个圆形区段与多个垂直区段集成为一体。可替代地，坝壁具有布置成两个或更多个重叠排的多个分开的垂直区段。在半导体管芯上形成多个导电支柱。电气组件设置在半导体管芯上。半导体管芯和电气组件设置在衬底上。在衬底上形成在坝壁外部的绝缘层。底部填充材料沉积在半导体管芯和衬底之间。坝壁和绝缘层抑制底部填充材料接触敏感区域的任何部分。

Semiconductor Device and Method of Forming Underfill Dam for Chip-to-Wafer Device

A semiconductor device has a semiconductor die with a sensitive area. A dam wall is formed over the semiconductor die proximate to the sensitive area. In one embodiment, the dam wall has a vertical segment and side wings. The dam wall can have a plurality of rounded segments integrated with a plurality of vertical segments as a unitary body. Alternatively, the dam wall has a plurality of separate vertical segments arranged in two or more overlapping rows. A plurality of conductive posts is formed over the semiconductor die. An electrical component is disposed over the semiconductor die. The semiconductor die and electrical component are disposed over a substrate. An insulating layer is formed over the substrate outside the dam wall. An underfill material is deposited between the semiconductor die and substrate. The dam wall and insulating layer inhibit the underfill material from contacting any portion of the sensitive area.

凸塊的薄膜技術

本發明實施例提供一種具有一阻障層之凸塊結構及一種用於製造該凸塊結構之方法。在一些實施例中，該凸塊結構包括一導電墊、一導電凸塊及一阻障層。該導電墊包括一墊材料。該導電凸塊上覆於該導電墊，且包括一下凸塊層及覆蓋該下凸塊層之一上凸塊層。該阻障層經組態以阻止墊材料沿著該下凸塊層之側壁從該導電墊移動至該上凸塊層。在一些實施例中，該阻障層係襯於該下凸塊層之該等側壁之一間隔件。在其他實施例中，該阻障層在該阻障層與該導電墊之間，且將該下凸塊層之該等側壁與該導電墊間隔開。

Chip package and chip thereof

A microchip (200) is electrically connected to a substrate (100) to become a chip package, preferably for LED. A chip (200) of the package includes a body (210) and at least one electrode (220, 230) which is disposed and exposed on a surface of the body (210). The electrode (220, 230) includes a confining groove (221, 231) and a confining wall. (222, 232) The confining wall (222, 232) is peripherally located around the confining groove (221, 231) and provided to confine at least one conductive particle (310, 320) of an adhesive (300) in the confining groove (221, 231). The electrode of the chip (200) is electrically connected to a bonding pad (110, 120) of a substrate (200) via the conductive particle (310, 320) confined in the confining groove (221,231).

晶片封裝構造及其晶片

一種晶片封裝構造，其用於微細晶片電性連接於一基板，尤其是運用於發光二極體，該晶片封裝構造的一晶片包含一本體及至少一電極，該電極設置於該本體的一表面，且顯露於該表面，該電極具有一限位槽及一位於該限位槽周邊的限位牆，該限位牆用以限制一膠體中的至少一導電粒子於該限位槽，且該晶片藉由位於該限位槽中的該導電粒子電性連接該電極及一基板的一導接墊。

チップパッケージ及びチップ

【課題】チップパッケージ及びチップを提供する。【解決手段】本発明のチップパッケージ及びチップは、微細チップを基板に電気的に接続させるために用いられ、特に発光ダイオードに適用される。前記チップパッケージのチップ２００は本体２１０及び前記本体２１０の表面２１１に設置されると共に前記表面２１１に露出される少なくとも１つの電極２２０を備え、前記電極２２０は第一位置限定溝２２１及び前記第一位置限定溝２２１周辺に位置する第一位置限定壁２２２を有し、前記第一位置限定壁２２２は接着剤３００中の少なくとも１つの導電性粒子３１０の位置を前記第一位置限定溝２２１に制限するために用いられる。前記チップ２００は前記第一位置限定溝２２１中に位置する前記導電性粒子３１０を介して前記電極２２０及び基板１００の第一導電パッド１１０に電気的に接続される。【選択図】図１

칩 패키지 구조 및 그 칩

칩 패키지 구조는 마이크로 칩을 기판에 전기적으로 연결시키기 위한 것으로, 특히 LED에 응용되고, 상기 칩 패키지 구조의 칩은 본체 및 적어도 하나의 전극을 포함하며, 상기 전극은 상기 본체의 표면에 설치되며, 또한 상기 표면으로부터 노출되고, 상기 전극은 위치한정 홈 및 상기 위치한정 홈의 주변에 위치하는 위치한정 벽을 구비하며, 상기 위치한정 벽은 접착제 중의 적어도 하나의 도전성 입자를 상기 위치한정 홈에 위치 한정시키며, 또한 상기 칩은 상기 위치한정 홈에 위치한 상기 도전성 입자를 통해 상기 전극과 기판의 접속패드를 전기적으로 연결시킨다.

半導體裝置之製造方法

一種半導體裝置之製造方法包括：在第一金屬層上形成熱固性樹脂薄膜；在該樹脂薄膜中形成開口；形成第二金屬層，其覆蓋自該第一金屬層之自該樹脂薄膜之該開口曝露之上表面至該樹脂薄膜之上表面的區域；在形成該第二金屬層之後，在等於或高於固化該樹脂薄膜之溫度的溫度下執行熱處理；在執行該熱處理之後，形成覆蓋該樹脂薄膜之該上表面及該第二金屬層之側表面的覆蓋薄膜；及在形成該覆蓋薄膜之後，在該第二金屬層之自該覆蓋薄膜之開口曝露之上表面上形成焊料。

Halbleitervorrichtung mit einem die-pad mit einer dammartigen konfiguration und verfahren zur herstellung einer halbleitervorrichtung

Halbleitervorrichtung (100), umfassend:ein Halbleitersubstrat (104);einen Leistungstransistor, der in dem Halbleitersubstrat (104) ausgebildet ist, wobei der Leistungstransistor einen aktiven Bereich (214) enthält, in dem eine oder mehrere Leistungstransistorzellen ausgebildet sind;ein erstes Metallpad (102), das über einer ersten Seite des Halbleitersubstrats (140) ausgebildet ist und im Wesentlichen den gesamten aktiven Bereich (214) des Leistungstransistors bedeckt, wobei das erste Metallpad (102) elektrisch mit einem Source- oder Emitter-Bereich (220) in dem aktiven Bereich (214) des Leistungstransistors verbunden ist, wobei das erste Metallpad (102) einen inneren Bereich (106) umfasst, der seitlich von einem peripheren Bereich (108) umgeben ist, wobei der periphere Bereich (108) dicker als der innere Bereich (106) ist und wobei eine laterale Ausdehnung des ersten Metallpads (102) auf einen Bereich innerhalb eines Umrisses der ersten Seite des Halbleitersubstrats (104) beschränkt ist; undeine erste Verbindungsplatte (206) oder einen Halbleiterchip (302), die bzw. der mit einem Chipbefestigungsmaterial (208) am inneren Bereich (106) des ersten Metallpads (102) befestigt ist.

범핑용 피막법

배리어층을 갖는 범프 구조체, 및 범프 구조체를 제조하는 방법이 제공된다. 일부 실시예에서, 범프 구조체는 전도성 패드, 전도성 범프, 및 배리어층을 포함한다. 전도성 패드는 패드 재료를 포함한다. 전도성 범프는 전도성 패드 위에 놓이며, 하부 범프층 및 하부 범프층을 덮는 상부 범프층을 포함한다. 배리어층은 전도성 패드로부터 하부 범프층의 측벽을 따라 상부 범프층으로 패드 재료의 이동을 차단하도록 구성된다. 일부 실시예에서, 배리어층은 하부 범프층의 측벽을 라이닝하는 스페이서이다. 다른 실시예에서, 배리어층은 배리어층과 전도성 패드 사이에 있고, 전도성 패드로부터 하부 범프층의 측벽을 이격시킨다.

集積回路のバンプ応力緩和層

本発明は、デバイス層を含む半導体基板、複数の金属化層、不動態化層、及び前記金属化層の少なくともひとつの前記金属化層と電気的に結合する前記不動態化層に形成される金属バンプ、とを含む装置である。当該装置はさらに、前記不動態化層に形成されるはんだ限定層を含み、前記金属バンプの上表面の外側端部をマスクし、それにより前記表面の外側端部が、はんだ材料により濡れないようにされる。

Semiconductor device and method for manufacturing semiconductor device

A semiconductor device according to the present disclosure includes a semiconductor substrate, a first electrode provided on the semiconductor substrate, an insulating layer including a first part provided on an upper surface of the first electrode, a second electrode including a main portion and an eaves portion, the main portion being provided on the upper surface of the first electrode, the eaves portion extending over the first part and solder covering an upper surface of the main portion and a part of an upper surface of the eaves portion wherein the insulating layer includes a second part covering a part of the upper surface of the eaves portion, the part being closer to an end portion of the eaves portion than the part covered by the solder and a third part connecting the first part and the second part and covering the end portion of the eaves portion.

Integrierter Schaltkreis und Verfahren zur Herstellung eines integrierten Schaltkreises

Integrierter Schaltkreis, der Folgendes aufweist:eine leitfähige Kontaktinsel (104), die ein Kontaktinselmaterial aufweist;einen leitfähigen Kontakthöcker (120), der über der leitfähigen Kontaktinsel (104) liegt, wobei der leitfähige Kontakthöcker (120) eine erste Kontakthöckerschicht (116) und eine zweite Kontakthöckerschicht (118), die die erste Kontakthöckerschicht (116) bedeckt, aufweist; undeine Sperrschicht (102) zwischen der Kontaktinsel (104) und dem leitfähigen Kontakthöcker (120), wobei die Sperrschicht (102) dafür konfiguriert ist, eine Bewegung des Kontaktinselmaterials von der leitfähigen Kontaktinsel (104) zu der zweiten Kontakthöckerschicht (118) entlang Seitenwänden der ersten Kontakthöckerschicht (116) zu blockieren;eine erste Keimschicht (112), die die Sperrschicht (102) zwischen der Sperrschicht (102) und dem leitfähigem Kontakthöcker (120) bedeckt;eine zweite Keimschicht (114), die über der ersten Keimschicht (112), direkt zwischen der ersten Keimschicht (112) und dem leitfähigen Kontakthöcker (120), liegt,wobei der Kontakthöcker (120), die erste Keimschicht (112) und die zweite Keimschicht (114) jeweils kein Kupfer aufweisen.

Integrated circuit having exposed leads

An electronic device that includes a semiconductor substrate and a conductive structure disposed over the semiconductor substrate. An insulator layer overlies the semiconductor substrate and includes a tapered opening that overlies a portion of the conductive structure. A flanged conductive column that includes a base portion is disposed in the tapered opening and is coupled to the portion of the conductive structure. The flanged conductive column further includes a flanged portion that is configured to be exposed to provide a conductive contact to the electronic device.

集成电路和用于制造集成电路的方法

本申请公开了集成电路和用于制造集成电路的方法。提供了具有阻挡层的凸块结构以及用于制造凸块结构的方法。在一些实施例中，凸块结构包括导电衬垫、导电凸块和阻挡层。导电衬垫包括衬垫材料。导电凸块叠加在导电衬垫上，并且包括下凸块层和覆盖下凸块层的上凸块层。阻挡层被配置为阻止衬垫材料沿着下凸块层的侧壁从导电衬垫移动到上凸块层。在一些实施例中，阻挡层是形成下凸块层的侧壁的衬里的间隔件。在其他实施例中，阻挡层位于下凸块层和导电衬垫之间，并且将下凸块层的侧壁与导电衬垫间隔开。

범핑용 피막법

배리어층을 갖는 범프 구조체, 및 범프 구조체를 제조하는 방법이 제공된다. 일부 실시예에서, 범프 구조체는 전도성 패드, 전도성 범프, 및 배리어층을 포함한다. 전도성 패드는 패드 재료를 포함한다. 전도성 범프는 전도성 패드 위에 놓이며, 하부 범프층 및 하부 범프층을 덮는 상부 범프층을 포함한다. 배리어층은 전도성 패드로부터 하부 범프층의 측벽을 따라 상부 범프층으로 패드 재료의 이동을 차단하도록 구성된다. 일부 실시예에서, 배리어층은 하부 범프층의 측벽을 라이닝하는 스페이서이다. 다른 실시예에서, 배리어층은 배리어층과 전도성 패드 사이에 있고, 전도성 패드로부터 하부 범프층의 측벽을 이격시킨다.

Method for manufacturing semiconductor device

A method for manufacturing a semiconductor device includes forming a thermosetting resin film on a first metal layer, forming an opening in the resin film, forming a second metal layer that covers a region from an upper surface of the first metal layer exposed from the opening of the resin film to an upper surface of the resin film, performing heat treatment at a temperature equal to or higher than a temperature at which the resin film is cured after forming the second metal layer, forming a cover film that covers the upper surface of the resin film and a side surface of the second metal layer after performing the heat treatment, and forming a solder on an upper surface of the second metal layer exposed from an opening of the cover film after forming the cover film.

半導体装置の製造方法

【課題】半田の回り込みを抑制することが可能な半導体装置の製造方法を提供する。【解決手段】第１金属層の上に熱硬化性の樹脂膜を形成する工程と、前記樹脂膜に開口部を形成する工程と、前記樹脂膜の開口部から露出する前記第１金属層の上面から、前記樹脂膜の上面まで第２金属層を形成する工程と、前記第２金属層を形成する工程の後、前記樹脂膜が硬化する温度以上の温度で熱処理する工程と、前記熱処理する工程の後に、前記樹脂膜の上面および前記第２金属層の側面を覆うカバー膜を形成する工程と、前記カバー膜を形成する工程の後に、前記カバー膜の開口部から露出する前記第２金属層の上面に、半田を形成する工程と、を有する半導体装置の製造方法。【選択図】 図１Ｂ

半导体装置的制造方法

本发明提供能够抑制焊料的流入的半导体装置的制造方法。一种半导体装置的制造方法，具有：在第一金属层上形成热固性树脂膜的工序；在所述树脂膜上形成开口部的工序；形成第二金属层的工序，所述第二金属层覆盖从所述树脂膜的开口部露出的所述第一金属层的上表面到所述树脂膜的上表面的区域；在所述形成第二金属层的工序之后，在所述树脂膜固化的温度以上的温度下进行热处理的工序；在所述进行热处理的工序之后，形成覆盖膜的工序，所述覆盖膜覆盖所述树脂膜的上表面和所述第二金属层的侧面；和在所述形成覆盖膜的工序之后，在从所述覆盖膜的开口部露出的所述第二金属层的上表面形成焊料的工序。

Method for manufacturing semiconductor device

A method for manufacturing a semiconductor device includes forming a thermosetting resin film on a first metal layer, forming an opening in the resin film, forming a second metal layer that covers a region from an upper surface of the first metal layer exposed from the opening of the resin film to an upper surface of the resin film, performing heat treatment at a temperature equal to or higher than a temperature at which the resin film is cured after forming the second metal layer, forming a cover film that covers the upper surface of the resin film and a side surface of the second metal layer after performing the heat treatment, and forming a solder on an upper surface of the second metal layer exposed from an opening of the cover film after forming the cover film.

집적 회로용 범프 응력 완화 층

장치는 디바이스 층과, 다수의 금속피복 층(a plurality of metallization layers)과, 패시베이션 층(a passivation layer)과, 패시베이션 층 위에 형성되고 적어도 하나의 금속피복 층에 전기적으로 접속된 금속 범프(a metal bump)를 구비하는 반도체 기판을 포함한다. 이 장치는 금속 범프의 상부 표면의 외곽 에지(an outer edge)를 가리도록 패시베이션 층 위에 형성된 땜납 제한 층(a solder limiting layer)을 더 포함하여, 상부 표면의 외곽 에지가 납땜 금속에 젖지 않도록 한다.

用于集成电路的凸块应力减轻层

一种装置，包括：具有器件层的半导体基板、多个金属化层、钝化层以及形成在钝化层上并电耦合到至少一个钝化层的金属凸块。所述装置进一步包括形成在钝化层上的焊料限定层，所述焊料限定层遮蔽金属凸块的上表面的外边缘，因此使得上表面的外边缘不能被焊接材料润湿。

Bump stress mitigation layer for integrated circuits

An apparatus comprises a semiconductor substrate having a device layer, a plurality of metallization layers, a passivation layer, and a metal bump formed on the passivation layer that is electrically coupled to at least one of the metallization layers. The apparatus further includes a solder limiting layer formed on the passivation layer that masks an outer edge of the top surface of the metal bump, thereby making the outer edge of the top surface non-wettable to a solder material.

Bump stress mitigation layer for integrated circuits

An apparatus comprises a semiconductor substrate having a device layer, a plurality of metallization layers, a passivation layer, and a metal bump formed on the passivation layer that is electrically coupled to at least one of the metallization layers. The apparatus further includes a solder limiting layer formed on the passivation layer that masks an outer edge of the top surface of the metal bump, thereby making the outer edge of the top surface non-wettable to a solder material.

Bump stress mitigation layer for integrated circuits

穿過鈍化界定的接觸墊之積體電路的耦接

組件可放置在晶圓之有源側上作為用於在電子裝置中使用的晶圓級晶片尺度封裝(WLCSP)之部分。該等組件在晶圓之有源側上的墊佈置可藉由在第一介電層上方形成導電端子及在該導電端子上方形成鈍化的第二介電層來鈍化界定。形成在該第二介電層中的開口界定與該導電端子的組件觸點及位於耦接到該導電端子的該晶圓上的電路。溝槽可在接觸墊之對之間使用以進一步減少由短路及/或未充滿引起的問題。導電墊可進一步沉積在該開口中以形成用於將該組件耦接到該晶圓的底部凸塊金屬化(UBM)。

半導体装置の製造方法

Integrierte schaltung, die freiliegende leitungen besitzt

Eine elektronische Vorrichtung, die ein Halbleitersubstrat und eine leitende Struktur, die über dem Halbleitersubstrat angeordnet ist, enthält. Eine Isolatorschicht überlagert das Halbleitersubstrat und enthält eine sich verjüngende Öffnung, die einen Abschnitt der leitenden Struktur überlagert. Eine Flanschleitersäule, die einen Basisabschnitt enthält, ist in der sich verjüngenden Öffnung angeordnet und ist an den Abschnitt der leitenden Struktur gekoppelt. Die Flanschleitersäule enthält ferner einen Flanschabschnitt, der konfiguriert ist, freizuliegen, um einen leitenden Kontakt zur elektronischen Vorrichtung zu schaffen.

반도체 패키지 및 이의 제조 방법

본 발명은 반도체 패키지 및 이의 제조 방법을 제공한다. 이 반도체 패키지는, 상부면에 배치되는 제1 하부 도전 패드를 포함하는 하부 구조체; 상기 하부 구조체 상에 배치되는 제1 반도체 칩, 상기 제1 반도체 칩은 하부면에 배치되는 제1 칩 도전 패드를 포함하고; 상기 제1 하부 도전 패드와 상기 제1 칩 도전 패드를 연결시키는 솔더볼; 상기 하부 구조체와 상기 제1 반도체 칩 사이의 공간을 채우는 감광성 절연막; 및 상기 제1 칩 도전 패드의 측면을 덮는 제1 유기 절연막을 포함한다.

Coupling of integrated circuits (ics) through a passivation-defined contact pad

穿過鈍化界定的接觸墊之積體電路的耦接

組件可放置在晶圓之有源側上作為用於在電子裝置中使用的晶圓級晶片尺度封裝(WLCSP)之部分。該等組件在晶圓之有源側上的墊佈置可藉由在第一介電層上方形成導電端子及在該導電端子上方形成鈍化的第二介電層來鈍化界定。形成在該第二介電層中的開口界定與該導電端子的組件觸點及位於耦接到該導電端子的該晶圓上的電路。溝槽可在接觸墊之對之間使用以進一步減少由短路及/或未充滿引起的問題。導電墊可進一步沉積在該開口中以形成用於將該組件耦接到該晶圓的底部凸塊金屬化(UBM)。

Chip and chip package

Semiconductor device

A semiconductor device may include a semiconductor substrate, a first bonding pad provided on an upper surface of the semiconductor substrate and constituted of a metal including aluminum, a second bonding pad provided on the upper surface of the semiconductor substrate, and a first protrusion protruding from an upper surface of the first bonding pad. The first protrusion may be provided on the upper surface of the first bonding pad only at a position adjacent to a peripheral edge of the first bonding pad, the peripheral edge of the first bonding pad may be opposed to the second bonding pad.

半导体装置及半导体装置的制造方法

本申请的发明涉及的半导体装置具有：半导体基板；第一电极，其设置于半导体基板之上；绝缘层，其具有在第一电极的上表面设置的第一部分；第二电极，其具有在第一电极的上表面设置的主要部分和与主要部分相连且攀上至第一部分之上的檐部；以及焊料，其将第二电极中的主要部分的上表面和与主要部分的上表面相连的檐部的上表面的一部分覆盖，绝缘层具有将檐部的上表面中的与被焊料覆盖的部分相比更靠檐部的端部侧的部分覆盖的第二部分和将第一部分与第二部分连接且将檐部的端部覆盖的第三部分。

Sheet molding process for wafer level packaging

Discussed generally herein are methods and devices including or providing a redistribution layer device without under ball metallization. A device can include a substrate, electrical interconnect circuitry in the substrate, redistribution layer (RDL) circuitry electrically connected to the electrical interconnect circuitry, a conductive bump electrically connected to the RDL circuitry, the conductive bump interfacing directly with the RDL circuitry, and a sheet molding material over the substrate.

半导体封装及其制造方法

一种半导体封装及其制造方法。该半导体封装包括：下部结构，包括设置在其上表面上的第一下导电焊盘；第一半导体芯片，设置在下部结构上，第一半导体芯片包括设置在其下表面上的第一芯片导电焊盘；焊球，连接第一下导电焊盘和第一芯片导电焊盘；光敏绝缘层，填充下部结构和第一半导体芯片之间的空间；以及第一有机绝缘层，覆盖第一芯片导电焊盘的侧表面。

Semiconductor package and method of fabricating the same

A semiconductor package and a method of fabricating the same. The semiconductor package includes a lower structure including a first lower conductive pad disposed on an upper surface thereof, a first semiconductor chip disposed on the lower structure, the first semiconductor chip including a first chip conductive pad disposed on a lower surface thereof, a solder ball connecting the first lower conductive pad and the first chip conductive pad, a photosensitive insulating layer filling a space between the lower structure and the first semiconductor chip, and a first organic insulating layer covering a side surface of the first chip conductive pad.

三维度互连(3di)焊料杯

本发明揭示一种衬底或半导体装置、半导体装置组合件，及形成包含焊料杯上的屏障的半导体装置组合件的方法。所述半导体装置组合件包含安置于另一衬底上面的衬底。至少一个焊料杯从一个衬底朝向另一衬底上的凸块下金属UBM延伸。所述焊料杯的外部上的所述屏障可为支座以控制所述衬底之间的接合线。在形成半导体装置组合件期间，所述屏障可减少焊料桥接。所述屏障可在形成半导体装置组合件时有助于使所述焊料杯与UBM对准，且可减少归因于衬底及/或半导体装置的横向移动的失准。

三维度互连(3di)焊料杯

本发明揭示一种衬底或半导体装置、半导体装置组合件，及形成包含焊料杯上的屏障的半导体装置组合件的方法。所述半导体装置组合件包含安置于另一衬底上面的衬底。至少一个焊料杯从一个衬底朝向另一衬底上的凸块下金属UBM延伸。所述焊料杯的外部上的所述屏障可为支座以控制所述衬底之间的接合线。在形成半导体装置组合件期间，所述屏障可减少焊料桥接。所述屏障可在形成半导体装置组合件时有助于使所述焊料杯与UBM对准，且可减少归因于衬底及/或半导体装置的横向移动的失准。