METHODS OF FORMING A MICROELECTRONIC DEVICE STRUCTURE, AND RELATED MICROELECTRONIC DEVICE STRUCTURES AND MICROELECTRONIC DEVICES

Procédé de formation d'une structure de dispositif micro-électronique qui comprend l'enroulement d'une portion d'un câble électrique autour d'au moins une paroi Latérale d'une structure qui fait saillie depuis un substrat. Au moins une interface entre une région supérieure de la structure et une région supérieure de la portion enroulée du câble électrique est soudée pour former une région de fusion entre la structure et le câble électrique.

DEVICE SUBSTRATE AND METHOD FOR MANUFACTURING SAME

Disclosed is a device substrate wherein an insulating layer (60) having a terminal (24) formed on the surface thereof is formed over the entire surface of a glass substrate (20), excluding a display section, and therefore, the border (outer periphery) of the insulating layer (60) does not approach a region where an NCF (81) is provided, i.e., an area close to an LSI chip (40). This prevents the insulating layer (60) from being peeled off from the border thereof by the NCF (81), and thereby prevents the terminal (24) from breaking. Furthermore, the terminal (24) and a bump electrode (40a) are permanently pressure-bonded to each other by the elasticity of the insulating layer (60), and a stable electrical connection therebetween can be ensured.

3di solder cup

本發明揭示一種基板或半導體裝置、半導體裝置總成及一種用於形成包含一焊料杯上之一障壁之一半導體裝置總成之方法。該半導體裝置總成包含安置於另一基板上面之一基板。至少一焊料杯自一基板朝向另一基板上之一凸塊下金屬(UBM)延伸。該焊料杯之外部上之該障壁可為一間隔件以控制該等基板之間的一接合線。在形成一半導體裝置總成期間，該障壁可減少焊料橋接。該障壁可在形成一半導體裝置總成時有助於使該焊料杯與一UBM對準且可減少歸因於基板及/或半導體裝置之橫向移動之失準。

Method for Aligning Micro-Electronic Components

Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force. By applying appropriate charges on the conductor lines, electrostatic self-alignment is realized, which improves ...

Bond Pad Having Ruthenium Covering Passivation Sidewall

A method of forming bond pads includes providing a substrate including an integrated circuit (IC) device formed thereon having an oxidizable uppermost metal interconnect layer which provides a plurality of bond pads that are coupled to circuit nodes on the IC device. The plurality of bond pads include a metal bond pad area. At least one passivation layer provides a trench including dielectric sidewalls above the metal bond pad area. A ruthenium (Ru) layer is deposited directly on the dielectric sidewalls and directly on the metal bond pad area, which removes the need for a barrier layer lining the dielectric sidewalls of the trench. The Ru layer is patterned to provide a bond pad surface for the plurality of bond pads. 1. A device , comprising:a semiconductor substrate;a metal layer formed above the semiconductor substrate;a bond pad metal area formed above the metal layer and coupled to the metal layer using a via plug;a passivation layer patterned with an opening exposing the bond pad metal area, the passivation layer forming a trench with the bond pad metal area, the trench having passivation sidewalls; anda ruthenium (Ru) layer covering the passivation sidewalls and the bond pad metal area.2. The device of claim 1 , wherein the Ru layer is formed directly on the passivation sidewalls and the bond pad metal area.3. The device of claim 1 , further comprising:a barrier layer formed directly on the passivation sidewalls and the bond pad metal area, the barrier layer directly interfacing the bond pad metal area with the Ru layer.4. The device of claim 1 , further comprising:a barrier layer formed directly on the passivation sidewalls and the bond pad metal area;a nickel layer formed directly on the barrier layer and within the trench, wherein the Ru layer is positioned directly on the nickel layer.5. The device of claim 1 , further comprising:a barrier layer formed directly on the passivation sidewalls and the bond pad metal area, the barrier layer interfacing the ...

Methods and apparatus for package with interposers

Methods and apparatus for an interposer with dams used in packaging dies are disclosed. An interposer may comprise a metal layer above a substrate. A plurality of dams may be formed above the metal layer around each corner of the metal layer. Dams may be formed on both sides of the interposer substrate. A dam surrounds an area where connectors such as solder balls may be located to connect to other packages. A non-conductive dam may be formed above the dam. An underfill may be formed under the package connected to the connector, above the metal layer, and contained within the area surrounded by the dams at the corner, so that the connectors are well protected by the underfill. Such dams may be further formed on a printed circuit board as well.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

To improve the reliability of a semiconductor device. 110-. (canceled)11. A method of manufacturing a semiconductor device , the method comprising:(a) preparing a semiconductor substrate which includes a plurality of wiring layers and a pad formed on an uppermost wiring layer of the plurality of wiring layers;(b) forming a surface protection film which includes an opening on the pad and is made of an inorganic insulating film;(c) forming a rewiring, which is electrically connected to the pad via the opening, on the surface protection film;(d) forming a pad electrode on the rewiring; and(e) forming a ball at a tip end of a wire, and connecting the ball to the pad electrode while applying ultrasonic vibration to the ball in a first direction,wherein the rewiring includes a pad electrode mounting portion on which the pad electrode is mounted, a connection portion which is connected to the pad, and an extended wiring portion that couples the pad electrode mounting portion and the connection portion, andthe pad electrode mounting portion has a rectangular shape with long sides and short sides.12. The method of manufacturing the semiconductor device according to claim 11 ,wherein the first direction is a direction along the long side.13. The method of manufacturing the semiconductor device according to claim 12 ,wherein the pad electrode covers a front surface of the pad electrode mounting portion, and extends to a side wall of the pad electrode mounting portion.14. The method of manufacturing the semiconductor device according to claim 11 ,wherein the first direction is a direction along the short side.15. The method of manufacturing the semiconductor device according to claim 11 ,wherein the pad electrode mounting portion includes a fin portion which extends from the long side or the short side to an outer side of the pad electrode mounting portion. The present application claims priority from Japanese Patent Application No. 2015-029409 filed on Feb. 18, 2015, the ...

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE

A semiconductor device includes: a first semiconductor chip having a first pad and a second pad, a depression being formed in the second pad; an organic insulating film provided on the first semiconductor chip, the organic insulating film covering the depression and not covering at least a portion of the first pad; and a redistribution layer having a lower portion connected to the first pad and an upper portion disposed on the organic insulating film.

Semiconductor Device and Method

A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

PROBLEM TO BE SOLVED: To provide a semiconductor device having a bump electrode on a pad electrode for effectively using the lower region of a pad electrode having the bump and preventing a local large force from being applied to a semiconductor substrate located at the lower side of the bump during mounting and a method of manufacturing the same. SOLUTION: A first layer metal wiring 5 that is formed on a semiconductor substrate and a pad electrode 7 that is formed on the first layer metal wiring 5 through an interlayer dielectric and connected with the first layer metal wiring 5 through via holes 10 that are formed on the interlayer dielectric are provided. Moreover, a protective film 8 that is formed on a pad electrode 7 and provided with an opening that exposes the pad electrode 7 and island-shaped protective films 9 in the opening and an Au bump 11 that is formed on the pad electrode 7 and connected with the pad electrode 7 through the opening of the protective film 8 are provided.

Packaged semiconductor devices and methods of packaging thereof

Packaging methods for semiconductor devices and methods of packaging thereof are disclosed. In some embodiments, a device includes a packaging apparatus and contact pads disposed on the packaging apparatus. The contact pads are arranged in an array of rows and columns. The contact pads include first contact pads proximate a perimeter region of the packaging apparatus and second contact pads disposed in an interior region of the packaging apparatus. A dam structure that is continuous is disposed around the second contact pads. The contact pads comprise a mounting region for a semiconductor device.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

The semiconductor device includes a plurality of wiring layers formed on a semiconductor substrate, a pad (9a) formed on an uppermost wiring layer (9) of the plurality of wiring layers (5,7,9), a surface protection film (10) which includes an opening (10a) on the pad (9a) and is made of an inorganic insulating film, a rewiring (12) formed on the surface protection film (10); a pad electrode (13) formed on the rewiring, and a wire (20) connected to the pad electrode (13). The rewiring (12) includes a pad electrode mounting portion (121) on which the pad electrode (13) is mounted, a connection portion which is connected to the pad (9a), and an extended wiring portion which couples the pad electrode mounting portion (121) and the connection portion, and the pad electrode mounting portion (121) has a rectangular shape when seen in a plan view.

Flip chip

Halbleiter-Chip und Halbleitergehäuse, welches diesen umfasst

Offenbarte Ausführungsformen umfassen einen Halbleiter-Chip umfassend ein Halbleitersubstrat aufweisend eine obere Fläche mit einem darin angeordneten oberen Verbindungs-Pad und eine Schutzisolierschicht, die eine Öffnung darin aufweist, wobei die Schutzisolierschicht mindestens einen Abschnitt des oberen Verbindungs-Pads auf dem Halbleitersubstrat nicht bedeckt. Die Schutzisolierschicht kann umfassen: eine untere Schutzisolierschicht, eine Deckisolierschicht aufweisend einen Seitendeckteil, der mindestens einen Abschnitt einer Seitenfläche der unteren Schutzisolierschicht bedeckt, und einen oberen Deckteil, der von dem Seitendeckteil beabstandet angeordnet ist, sodass er mindestens einen Abschnitt einer oberen Fläche der unteren Schutzisolierschicht bedeckt. Die Schutzisolierschicht kann ferner eine obere Schutzisolierschicht auf dem oberen Deckteil umfassen.

Semiconductor device and manufacturing method thereof

A semiconductor device includes: a pad electrode 9a formed in an uppermost layer of a plurality of wiring layers; a base insulating film 11 having an opening 11a on the pad electrode 9a; a base metal film UM formed on the base insulating film 11; a redistribution line RM formed on the base metal film UM; and a cap metal film CM formed so as to cover an upper surface and a side surface of the redistribution line RM. In addition, in a region outside the redistribution line RM, the base metal film UM made of a material different from that of the redistribution line RM and the cap metal film CM made of a material different from the redistribution line RM are formed between the cap metal film CM formed on the side surface of the redistribution line RM and the base insulating film 11, and the base metal film UM and the cap metal film CM are in direct contact with each other in the region outside the redistribution line RM.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME

The present invention is to improve reliability of a semiconductor device. The semiconductor device (1) includes a plurality of wiring layers (5, 7, 9) formed on a semiconductor substrate (1P), a pad (9a) formed on an uppermost wiring layer of the wiring layers (5, 7, 9), a surface protection film (10) which includes an opening on the pad and is made of an inorganic insulating film, a rewiring (12) formed on the surface protection film (10), a pad electrode (13) formed on the rewiring (12), and a wire (20) connected to the pad electrode (13). The rewiring (12) includes a pad electrode mounting portion on which the pad electrode (13) is mounted, a connection portion which is connected to the pad, and an extended wiring portion which connects the pad electrode mounting portion and the connection portion, and the pad electrode mounting portion (13) is in a rectangular shape when viewed from a plane. COPYRIGHT KIPO 2016 (1) Semiconductor device (Semiconductor chip) (10) Surface protection film ...

Methods and Apparatus for Package with Interposers

Methods and apparatus for an interposer with dams used in packaging dies are disclosed. An interposer may comprise a metal layer above a substrate. A plurality of dams may be formed above the metal layer around each corner of the metal layer. Dams may be formed on both sides of the interposer substrate. A dam surrounds an area where connectors such as solder balls may be located to connect to other packages. A non-conductive dam may be formed above the dam. An underfill may be formed under the package connected to the connector, above the metal layer, and contained within the area surrounded by the dams at the corner, so that the connectors are well protected by the underfill. Such dams may be further formed on a printed circuit board as well.

Semiconductor device and method

Semiconductor device and semiconductor package

A semiconductor device includes: a first semiconductor chip having a first pad and a second pad, a depression being formed in the second pad; an organic insulating film provided on the first semiconductor chip, the organic insulating film covering the depression and not covering at least a portion of the first pad; and a redistribution layer having a lower portion connected to the first pad and an upper portion disposed on the organic insulating film.

Semiconductor packages and manufacturing methods for the same

A semiconductor package and a fabrication method of the semiconductor package are disclosed. First and second redistribution layer patterns are formed on a semiconductor substrate including a chip region and a scribe lane region to provide a bonding pad portion and an edge pad portion, respectively. A polymer pattern is formed to reveal the bonding pad portion and a portion of the edge pad portion. A dicing line is set on the scribe lane region. A stealth dicing process is performed along the dicing line to separate a semiconductor chip including the bonding pad portion from the semiconductor substrate. The semiconductor chip is disposed on a package substrate. A bonding wire is formed to connect the bonding pad portion to the package substrate. The bonding wire is supported by an edge of the polymer pattern to be spaced apart from the revealed portion of the edge pad portion.

METHODS OF FORMING A MICROELECTRONIC DEVICE STRUCTURE, AND RELATED MICROELECTRONIC DEVICE STRUCTURES AND MICROELECTRONIC DEVICES

A method of forming a microelectronic device structure comprises coiling a portion of a wire up and around at least one sidewall of a structure protruding from a substrate. At least one interface between an upper region of the structure and an upper region of the coiled portion of the wire is welded to form a fused region between the structure and the wire.

Semiconductor device with edge-protecting spacers over bonding pad

The present application provides a semiconductor device with an edge-protecting spacer over a bonding pad. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a dielectric liner disposed between the first spacer and the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate, wherein the dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the bonding pad and covering the first spacer and the dielectric liner, wherein the conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad.

Halbleitermodul und Verfahren zur Herstellung desselben

Gemäß einer Ausführungsform umfasst ein Halbleitermodul einen ersten Halbleiterchip, einen Metalldraht und einen linearen Körper. Der erste Halbleiterchip umfasst eine erste Oberfläche und eine an der ersten Oberfläche vorgesehene erste Elektrode, die erste Elektrode umfasst einen ersten Bereich und einen zweiten Bereich. Der Metalldraht weist einen gekrümmten Abschnitt auf, welche nach oben gerichtet weg von der ersten Oberfläche gebogen ist, der gekrümmte Abschnitt ist an beiden Enden mit dem ersten Bereich und dem zweiten Bereich jeweils verbunden. Der lineare Körper ist zwischen dem gekrümmten Abschnitt und der ersten Oberfläche angeordnet.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device includes: a semiconductor element that includes an element main body having an element main surface facing one side in a thickness direction, and a first electrode arranged on the element main surface; a first insulating layer that is arranged over a peripheral edge portion of the first electrode and the element main surface and includes a first annular portion formed in an annular shape when viewed in the thickness direction; and a second insulating layer that is laminated on the first insulating layer, is made of a resin material, and includes a second annular portion overlapping with the first annular portion when viewed in the thickness direction.

Package substrates and methods for fabricating the same

A package substrate and a method of fabricating the same are provided, the method includes providing a substrate body having a first surface and a second surface opposite thereto, a plurality of first electric connection pads formed on the first surface; and disposing a metal plate on the plurality of first electric connection pads, then patterning the metal plate so as to define a metal column corresponding to each first electric connection pad. According to the present invention, drawbacks of raw edges and unequal heights of the metal columns can be obviated.

CHIP PACKAGE AND CHIP THEREOF

A microchip is electrically connected to a substrate to become a chip package, preferably for LED. A chip of the package includes a body and at least one electrode which is disposed and exposed on a surface of the body. The electrode includes a confining groove and a confining wall. The confining wall is peripherally located around the confining groove and provided to confine at least one conductive particle of an adhesive in the confining groove. The electrode of the chip is electrically connected to a bonding pad of a substrate via the conductive particle confined in the confining groove.

Chip package and chip thereof

BOND HEAD WITH ELASTIC MATERIAL AROUND PERIMETER TO IMPROVE BONDING QUALITY

A bond head is provided. The bond head includes a bond base, a chuck member, and an elastic material. The chuck member protrudes from a surface of the bond base, and has a chuck surface formed with vacuum holes for holding a die using differential air pressure. In the direction parallel to the chuck surface, the width of the chuck surface is less than the width of the bond base and is equal to or greater than the width of the die. The elastic material is disposed over the chuck surface. The elastic material is arranged around the periphery of the chuck surface to cover edges and/or corners of the chuck surface.

Semiconductor device with spacer over bonding pad

The present application provides a semiconductor device. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a second spacer disposed over a sidewall of the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate. The dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the first passivation layer. The conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad.

Semiconductor device and manufacturing method thereof

Semiconductor Device and Method

A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures.

SEMICONDUCTOR DEVICE WITH SPACER OVER BONDING PAD

The present application provides a semiconductor device. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a second spacer disposed over a sidewall of the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate. The dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the first passivation layer. The conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad

Semiconductor device with spacer over bonding pad

The present application provides a semiconductor device. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a second spacer disposed over a sidewall of the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate. The dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the first passivation layer. The conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad. The semiconductor device also includes a dielectric liner disposed between the first spacer and the bonding pad; and a first passivation layer covering the second spacer, wherein the dielectric liner is L-shaped, and the first spacer is separated from the bonding pad by the dielectric liner.

Kontakthöckerkissenumfassung, Kontakthöckerverbinder, elektrisches Bauteil, elektrische Vorrichtung und Verfahren zum Herstellen

Es ist eine Kontakthöckerkissenumfassung bereitgestellt, die eine verbesserte Zuverlässigkeit einer Kontakthöckerverbindung bereitstellt. Die Kontakthöckerkissenumfassung umfasst ein Elektrodenkissen, eine UBM und eine erste Abschirmung. Die erste Abschirmung deckt wenigstens einen ersten Umfangsbereich des Elektrodenkissens ab. Die erste Abschirmung ist bereitgestellt und ist dazu ausgelegt, den ersten Umfangsbereich von einem schädlichen Einfluss der Umgebung abzuschirmen.

CHIP PACKAGE AND CHIP THEREOF

CHIP-SCALE PACKAGE

Aspects of the present disclosure relate to a semiconductor device such as a chip-scale package. Aspects of the present disclosure further relate to a method for manufacturing such a device. According to an aspect of the present disclosure, a semiconductor device is provided that comprises a conformal coating arranged on its sidewalls and on the perimeter part of the semiconductor die of the semiconductor device. To prevent the conformal coating from covering unwanted areas, such as electrical terminals, a sacrificial layer is arranged prior to arranging the conformal coating. By removing the sacrificial layer, the conformal coating can be removed locally. The conformal coating covers the perimeter part of the semiconductor die comprises by the semiconductor device, in which part a remainder of a sawing line or dicing street is provided.

SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

A semiconductor device includes a semiconductor substrate and a connection terminal, including a base pillar, on the semiconductor substrate. An insulation layer is formed on the semiconductor substrate, the insulation layer including an opening in the insulation layer through which the base pillar extends, wherein a side wall of the insulation layer defining the opening includes a horizontal step at a level that is lower than an uppermost portion of the base pillar.

SEMICONDUCTOR DEVICE

PURPOSE: To prevent a metal comprising a pad for bonding from corroding further minimizing the danger of cracking in a protective film covering a semiconductor chip extending over almost the whole body by a method wherein the diameter of an opening part for bonding is made smaller than that of the pad for bonding as well as that of bonded part of a wire. CONSTITUTION: Within a semiconductor device wherein a semiconductor chip and a lead frame are electrically connected by wire bonding process, the said semiconductor chip is provided with a bonding pad 1 formed on the semiconductor chip, a protective film 2 formed on the bonding pad 1, an opening part 4 for bonding made in the bonding pad 1 through the protective film 2 while the diameter of the opening part 4 is made smaller than that of the bonding pad 1 as well as that of a bonded part 3' of a wire 3. For example, the said protective film 2 is provided with slit parts 5 formed around the opening part 4 for bonding excluding the part above ...

Semiconductor device and manufacturing method thereof

A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures.

Semiconductor chip and semiconductor package including the same

A semiconductor device includes a semiconductor substrate and a connection terminal, including a base pillar, on the semiconductor substrate. An insulation layer is formed on the semiconductor substrate, the insulation layer including an opening in the insulation layer through which the base pillar extends, wherein a side wall of the insulation layer defining the opening includes a horizontal step at a level that is lower than an uppermost portion of the base pillar.

Semiconductor device

Methods and apparatus for package with interposers

Methods and apparatus for an interposer with dams used in packaging dies are disclosed. An interposer may comprise a metal layer above a substrate. A plurality of dams may be formed above the metal layer around each corner of the metal layer. Dams may be formed on both sides of the interposer substrate. A dam surrounds an area where connectors such as solder balls may be located to connect to other packages. A non-conductive dam may be formed above the dam. An underfill may be formed under the package connected to the connector, above the metal layer, and contained within the area surrounded by the dams at the corner, so that the connectors are well protected by the underfill. Such dams may be further formed on a printed circuit board as well.

3DI Solder Cup

A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices. 1. A device comprising:a substrate;an electrical interconnect within the substrate;a barrier structure electrically connected to the electrical interconnect, the barrier structure having a funnel-shaped recess defined therein; andsolder positioned within the funnel-shaped recess of the barrier structure.2. The device of claim 1 , further comprising:a copper structure positioned within the funnel-shaped recess of the barrier structure; anda nickel structure positioned within the funnel-shaped recess of the barrier structure.3. The device of claim 1 , wherein the barrier structure comprises tantalum claim 1 , tungsten claim 1 , titanium nitride claim 1 , or combinations thereof.4. The device of claim 1 , further comprising:a semiconductor device having a via and an under bump metal (UBM) electrically connected to the via, and wherein the UBM is encased in the solder within the funnel-shaped recess of the barrier structure.5. The device of claim 4 , wherein the UBM includes angled sidewalls.6. The device of claim 5 , wherein the angled sidewalls of the UBM are configured to produce a wetting force between the substrate and the semiconductor device during thermal compression bonding.7. The device of claim 4 , wherein the ...

Final passivation for wafer level warpage and ULK stress reduction

Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having an annular PSPI region formed under a BLM pad. An annular region is formed under a barrier layer metallurgy (BLM) pad. The annular region includes a photosensitive polyimide (PSPI). A conductive pedestal is formed on a surface of the BLM pad and a solder bump is formed on a surface of the conductive pedestal. The annular PSPI region reduces wafer warpage and ULK peeling stress.

Method for aligning micro-electronic components

Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force. By applying appropriate charges on the conductor lines, electrostatic self-alignment is realized, which improves ...

SEMICONDUCTOR DEVICE WITH SPACER OVER BONDING PAD

Reduced stress under bump metallization structure

An improved under bump structure for use in semiconductor devices is described. The under bump structure includes a passivation layer having a plurality of vias. The vias are positioned such that a plurality of vias are associated with (i.e., located over) each contact pad. A metal layer fills the vias and forms a metallization pad that is suitable for supporting a solder bump. Preferably the metal layer extends over at least portions of the passivation layer to form a unified under bump metallization pad over the associated contact pad. Each metallization pad is electrically connected to the contact pad through a plurality of the vias. The described under bump structures can be formed at the wafer level.

Semiconductor Device and Method

A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures. 16.-. (canceled)7. A method of manufacturing a semiconductor device , the method comprising:depositing a dielectric layer over a redistribution layer, the dielectric layer comprising a first dielectric material;forming at least one opening through the dielectric layer, wherein the forming the at least one opening leaves a support structure of the first dielectric material between separate portions of the at least one opening; anddepositing a conductive material into the at least one opening and also at least partially over the dielectric layer, wherein the depositing the conductive material deposits the conductive material over the dielectric layer to a thickness of no greater than about 3 μm.8. The method of claim 7 , further comprising forming a cap layer over the conductive material.9. The method of claim 8 , wherein the cap layer comprises solder and has a thickness of less than about 2 μm.10. The method of claim 8 , further comprising:connecting the cap layer to a test probe; andremoving the cap layer.11. The method of claim 7 , wherein the forming the at least one opening comprises forming a circular opening that surrounds the support structure.12. The method of claim 7 , wherein the forming the at least one opening comprises forming two or more separate openings.13. The method of claim 12 , wherein the forming the at least one opening comprises forming four separate openings.14. The method of claim 13 , wherein each of the four separate openings has a diameter of about 10 μm.15. A method of manufacturing a semiconductor device claim 13 , the method comprising:depositing a seed layer over a dielectric layer, wherein a ...

Semiconductor device and method

A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures.

Semiconductor device with edge-protecting spacers over bonding pad

The present application provides a semiconductor device with an edge-protecting spacer over a bonding pad. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a dielectric liner disposed between the first spacer and the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate, wherein the dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the bonding pad and covering the first spacer and the dielectric liner, wherein the conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad.

For aligning a microelectronic assembly

Semiconductor device and method

A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures.

Flip chip

A flip chip includes a substrate, an electrode pad layer stacked over the substrate, a passivation layer stacked at both ends of the electrode pad layer, an under bump metallurgy (UBM) layer stacked over the electrode pad layer and the passivation layer, and a bump formed over the UBM layer. The width of an opening on which the passivation layer is not formed over the electrode pad layer is greater than the width of the bump. The flip chip can prevent a crack from being generated in the pad upon ultrasonic bonding.

Semiconductor structure with low-melting-temperature conductive regions, and method of repairing a semiconductor structure

A semiconductor structure includes at least a semiconductor body, a delimiting structure delimiting a cup-shaped recess in the body and a conductive region in the recess. The conductive region is made of a low-melting-temperature material, having a melting temperature lower than that of the materials forming the delimiting structure.

Semiconductor device and method of manufacturing semiconductor device

A semiconductor device includes: a semiconductor element that includes an element main body having an element main surface facing one side in a thickness direction, and a first electrode arranged on the element main surface; a first insulating layer that is arranged over a peripheral edge portion of the first electrode and the element main surface and includes a first annular portion formed in an annular shape when viewed in the thickness direction; and a second insulating layer that is laminated on the first insulating layer, is made of a resin material, and includes a second annular portion overlapping with the first annular portion when viewed in the thickness direction.

Chip package and manufacturing method thereof

Packaged Semiconductor Devices and Methods of Packaging Thereof

Packaging methods for semiconductor devices and methods of packaging thereof are disclosed. In some embodiments, a device includes a packaging apparatus and contact pads disposed on the packaging apparatus. The contact pads are arranged in an array of rows and columns. The contact pads include first contact pads proximate a perimeter region of the packaging apparatus and second contact pads disposed in an interior region of the packaging apparatus. A dam structure that is continuous is disposed around the second contact pads. The contact pads comprise a mounting region for a semiconductor device.

3DI SOLDER CUP

本發明揭示一種基板或半導體裝置、半導體裝置總成及一種用於形成包含一焊料杯上之一障壁之一半導體裝置總成之方法。該半導體裝置總成包含安置於另一基板上面之一基板。至少一焊料杯自一基板朝向另一基板上之一凸塊下金屬(UBM)延伸。該焊料杯之外部上之該障壁可為一間隔件以控制該等基板之間的一接合線。在形成一半導體裝置總成期間，該障壁可減少焊料橋接。該障壁可在形成一半導體裝置總成時有助於使該焊料杯與一UBM對準且可減少歸因於基板及/或半導體裝置之橫向移動之失準。

Semiconductor device and method

A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures.

3DI solder cup

A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices.

Semiconductor device with edge-protecting spacers over bonding pad

FINAL PASSIVATION FOR WAFER LEVEL WARPAGE AND ULK STRESS REDUCTION

Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having an annular PSPI region formed under a BLM pad. An annular region is formed under a barrier layer metallurgy (BLM) pad. The annular region includes a photosensitive polyimide (PSPI). A conductive pedestal is formed on a surface of the BLM pad and a solder bump is formed on a surface of the conductive pedestal. The annular PSPI region reduces wafer warpage and ULK peeling stress.

Semiconductor Device and Method

A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures.

DISPLAY BACKBOARD AND MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE

A display backboard and a manufacturing method thereof, and a display device are provided. The display backboard includes: a driving substrate; a plurality of driving electrodes on the driving substrate; and a plurality of connection structures respectively on the plurality of driving electrodes. The connection structure includes: at least one conductive component on the driving electrode; and a restriction component on a side of the driving electrodes provided with the at least one conductive component and in at least a part of a peripheral region of the at least one conductive component. The restriction component protrudes from the driving electrode and has a first height in a direction perpendicular to the driving substrate.

PACKAGE SUBSTRATES AND METHODS FOR FABRICATING THE SAME

Semiconductor device and method

A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures.

3DI Solder Cup

A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices. 1. (canceled)2. The assembly of claim 8 , wherein the solder cup and UBM form an interconnect that electrically connects the first substrate and the second substrate.3. The assembly of claim 2 , wherein the first substrate further comprises a first semiconductor device and the second substrate further comprises a second semiconductor device.4. The assembly of claim 3 , wherein the second end of the barrier engages the first surface of the first semiconductor device and supports the second semiconductor device.5. (canceled)6. The assembly of claim 8 , wherein the second end of the barrier surrounds the UBM.7. (canceled)8. A semiconductor device assembly comprising:a first substrate having a first surface and a second surface opposite the first surface, the first surface having at least one under bump metal (UBM) disposed thereon;a second substrate having a first surface and a second surface opposite the first surface, the second substrate disposed over the first substrate, the second substrate having at least one solder cup on the second surface, the at least one solder cup comprising a barrier having a first end proximal to the second surface of the second substrate and a second end distal to the second surface of ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SAME

Semiconductor structure

A semiconductor structure including a substrate, a dielectric layer, a first conductive layer, and a passivation layer is provided. The dielectric layer is disposed on the substrate. The first conductive layer is disposed on the dielectric layer. The passivation layer is disposed on the first conductive layer and the dielectric layer. The passivation layer includes a first upper surface and a second upper surface. The first upper surface is located above a top surface of the first conductive layer. The second upper surface is located on one side of the first conductive layer. A height of the first upper surface is higher than a height of the second upper surface. The height of the second upper surface is lower than or equal to a height of a lower surface of the first conductive layer located between a top surface of the dielectric layer and the first conductive layer.

REDISTRIBUTION LAYER (RDL) STRUCTURE, SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

The present disclosure provides a redistribution layer (RDL) structure, a semiconductor device and manufacturing method thereof. The semiconductor device comprising an RDL structure that may include a substrate, a first conductive layer, a reinforcement layer and, and a second conductive layer. The first conductive layer may be formed on the substrate and has a first bond pad area. The reinforcement layer may be formed on a surface of the first conductive layer facing away from the substrate and located in the first bond pad area. The second conductive layer may be formed on the reinforcement layer and an area of the first conductive layer not covered by the reinforcement layer. The reinforcement layer has a material strength greater than those of the first conductive layer and the second conductive layer. The semiconductor device and the manufacturing method provided by the present disclosure may improve the performance of the semiconductor device. 1. A redistribution layer (RDL) structure , comprising:a substrate;a first conductive layer formed on the substrate and having a first bond pad area;a reinforcement layer formed on a surface of the first conductive layer not adjacent to the substrate and located in the first bond pad area; anda second conductive layer formed on the reinforcement layer and an area of the first conductive layer not covered by the reinforcement layer,wherein the reinforcement layer has a material strength greater than those of the first conductive layer and the second conductive layer and the reinforcement layer is conductive.2. The RDL structure according to claim 1 , wherein the reinforcement layer has at least one first through via claim 1 , and the second conductive layer fills the at least one first through via and is connected to the first conductive layer.3. The RDL structure according to claim 2 , wherein the at least one first through via comprises a plurality of first through vias distributed at intervals along an annular track.4. ...

DISPLAY DEVICE AND TILED DISPLAY DEVICE

A display device includes a substrate, a plurality of electrode pads including a first electrode pad and a common electrode pad on the substrate, a light emitting element including a first contact electrode on the first electrode pad and a second contact electrode on the common electrode pad, a conductive adhesive member including a plurality of conductive balls connecting the first electrode pad and the first contact electrode and connecting the common electrode pad and the second contact electrode, and a plurality of protrusions on the substrate and protruding in a thickness direction of the substrate. First protrusions from among the plurality of protrusions overlap the electrode pads in the thickness direction of the substrate.

INTEGRATED CIRCUIT HAVING EXPOSED LEADS

An electronic device that includes a semiconductor substrate and a conductive structure disposed over the semiconductor substrate. An insulator layer overlies the semiconductor substrate and includes a tapered opening that overlies a portion of the conductive structure. A flanged conductive column that includes a base portion is disposed in the tapered opening and is coupled to the portion of the conductive structure. The flanged conductive column further includes a flanged portion that is configured to be exposed to provide a conductive contact to the electronic device.

SEMICONDUCTOR PACKAGES AND MANUFACTURING METHODS FOR THE SAME

A semiconductor package and a fabrication method of the semiconductor package are disclosed. First and second redistribution layer patterns are formed on a semiconductor substrate including a chip region and a scribe lane region to provide a bonding pad portion and an edge pad portion, respectively. A polymer pattern is formed to reveal the bonding pad portion and a portion of the edge pad portion. A dicing line is set on the scribe lane region. A stealth dicing process is performed along the dicing line to separate a semiconductor chip including the bonding pad portion from the semiconductor substrate. The semiconductor chip is disposed on a package substrate. A bonding wire is formed to connect the bonding pad portion to the package substrate. The bonding wire is supported by an edge of the polymer pattern to be spaced apart from the revealed portion of the edge pad portion.

Chip package and chip

一種晶片封裝構造，其用於微細晶片電性連接於一基板，尤其是運用於發光二極體，該晶片封裝構造的一晶片包含一本體及至少一電極，該電極設置於該本體的一表面，且顯露於該表面，該電極具有一限位槽及一位於該限位槽周邊的限位牆，該限位牆用以限制一膠體中的至少一導電粒子於該限位槽，且該晶片藉由位於該限位槽中的該導電粒子電性連接該電極及一基板的一導接墊。

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

In a semiconductor device, a region under a pad electrode with a bump can be utilized efficiently and a large amount of force is prevented from applying locally to a semiconductor substrate under the bump when the semiconductor device is mounted. A first layer metal wiring is formed on the semiconductor substrate. A pad electrode is formed on the first layer metal wiring through an interlayer insulation film. The pad electrode is connected with the first layer metal wiring through a via hole that is formed in the interlayer insulation film. A protection film is formed on the pad electrode. The protection film has an opening to expose the pad electrode and an island-shaped protection film formed in the opening. An Au bump connected with the pad electrode through the opening in the protection film is formed on the pad electrode. The via hole is formed under the island-shaped protection film, and incompletely filled with a portion of the pad electrode.

3DI solder cup

A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices.

Semiconductor device with spacer over bonding pad

本揭露提供一種半導體元件。該半導體元件具有一接合墊、一第一間隙子、一第二間隙子以及一介電層。該接合墊設置在一半導體基底上。該第一間隙子設置在該接合墊的一頂表面上。該第二間隙子設置在該接合墊的一側壁上。該介電層位在該接合墊與該半導體基底之間。該介電層包含富含矽的氧化物；而一導電凸塊設置在該第一鈍化層上。該導電凸塊經由該導電凸塊電性連接一源極/汲極區，該源極/汲極區未在該半導體基底中。

CHIP PACKAGE AND CHIP

SEMICONDUCTOR DEVICE

In a semiconductor device, a first protection film covers an end portion of a first metal layer disposed on a semiconductor substrate, and has a first opening above the first metal layer. A second metal layer is disposed on the first metal layer in the first opening. An oxidation inhibition layer is disposed on the second metal layer in the first opening. A second protection film has a second opening and covers an end portion of the oxidation inhibition layer and the first protection film. The second protection film has an opening peripheral portion on a periphery of the second opening, and covers the end portion of the oxidation inhibition layer. An adhesion portion adheres to a portion of a lower surface of the opening peripheral portion. The adhesion portion has a higher adhesive strength with the second protection film than the oxidation inhibition layer.

SOLDER FATIGUE ARREST FOR WAFER LEVEL PACKAGE

A wafer level package includes a wafer, a lead disposed of the wafer for connecting the wafer to an electrical circuit, and a core disposed of the lead. In some embodiments, the lead disposed of the wafer is a copper pillar, and the core is plated onto the copper pillar. In some embodiments, the core is polymer screen-plated onto the lead. In some embodiments, the core extends between at least approximately thirty-five micrometers (35 μm) and fifty micrometers (50 μm) from the lead. In some embodiments, the core covers between at least approximately one-third (⅓) and one-half (½) of the surface area of the lead. In some embodiments, the core comprises a stud-shape extending from the lead. In some embodiments, the core extends perpendicularly across the lead. In some embodiments, the core extends longitudinally along the lead. Further, a portion of the core can extend perpendicularly from a longitudinal core.

Chip package and chip thereof

A microchip is electrically connected to a substrate to become a chip package, preferably for LED. A chip of the package includes a body and at least one electrode which is disposed and exposed on a surface of the body. The electrode includes a confining groove and a confining wall. The confining wall is peripherally located around the confining groove and provided to confine at least one conductive particle of an adhesive in the confining groove. The electrode of the chip is electrically connected to a bonding pad of a substrate via the conductive particle confined in the confining groove.

Wafer packaging structure and wafer thereof

PACKAGE SUBSTRATE AND METHOD FOR FABRICATING THE SAME

A package substrate and a method of fabricating the same are provided. The method includes providing a substrate body having a first surface, a second surface opposing the first surface, a plurality of first electrical connecting pads disposed on the first surface; mounting a metal board on the first electrical connecting pads; and patterning the metal board so as to define a plurality of metal pillars corresponding to the first electrical connecting pads. Therefore, drawbacks of raw edges and unequal heights of the metal pillars can be obviated.

3DI Solder Cup

A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices.

SEMICONDUCTOR DEVICE WITH EDGE-PROTECTING SPACERS OVER BONDING PAD

The present application provides a semiconductor device with an edge-protecting spacer over a bonding pad. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a dielectric liner disposed between the first spacer and the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate, wherein the dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the bonding pad and covering the first spacer and the dielectric liner, wherein the conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad.

Electronic element and electronic device comprising the same

A first electronic element is disclosed, which includes: a first substrate having a first surface; a first electrode pad disposed on the first surface, wherein the first electrode pad has a second surface away from the first substrate; and an insulating layer disposed on the first surface, wherein the insulating layer includes an opening, the opening is disposed correspondingly to the first electrode pad, and the opening overlaps the first electrode pad in a normal direction of the first surface, wherein the insulating layer has a third surface away from the first substrate, a distance between the third surface and the second surface in the normal direction of the first surface is defined as a first distance, and the first distance is greater than 0 μm and less than or equal to 14 μm. In addition, the disclosure further provides an electronic device including the first electronic element.

Packaged semiconductor devices and methods of packaging thereof

Packaging methods for semiconductor devices and methods of packaging thereof are disclosed. In some embodiments, a device includes a packaging apparatus and contact pads disposed on the packaging apparatus. The contact pads are arranged in an array of rows and columns. The contact pads include first contact pads proximate a perimeter region of the packaging apparatus and second contact pads disposed in an interior region of the packaging apparatus. A dam structure that is continuous is disposed around the second contact pads. The contact pads comprise a mounting region for a semiconductor device.

Semiconductor device and manufacturing method thereof

In a semiconductor device, a region under a pad electrode with a bump can be utilized efficiently and a large amount of force is prevented from applying locally to a semiconductor substrate under the bump when the semiconductor device is mounted. A first layer metal wiring is formed on the semiconductor substrate. A pad electrode is formed on the first layer metal wiring through an interlayer insulation film. The pad electrode is connected with the first layer metal wiring through a via hole that is formed in the interlayer insulation film. A protection film is formed on the pad electrode. The protection film has an opening to expose the pad electrode and an island-shaped protection film formed in the opening. An Au bump connected with the pad electrode through the opening in the protection film is formed on the pad electrode. The via hole is formed under the island-shaped protection film, and incompletely filled with a portion of the pad electrode.

Solder fatigue arrest for wafer level package

A wafer level package includes a wafer, a lead disposed of the wafer for connecting the wafer to an electrical circuit, and a core disposed of the lead. In some embodiments, the lead disposed of the wafer is a copper pillar, and the core is plated onto the copper pillar. In some embodiments, the core is polymer screen-plated onto the lead. In some embodiments, the core extends between at least approximately thirty-five micrometers (35 μm) and fifty micrometers (50 μm) from the lead. In some embodiments, the core covers between at least approximately one-third (⅓) and one-half (½) of the surface area of the lead. In some embodiments, the core comprises a stud-shape extending from the lead. In some embodiments, the core extends perpendicularly across the lead. In some embodiments, the core extends longitudinally along the lead. Further, a portion of the core can extend perpendicularly from a longitudinal core.

Semiconductor device and method of manufacturing the same

Semiconductor device and manufacturing method for same

A semiconductor device has: a pad electrode 9a formed on the uppermost layer of a plurality of wiring layers; a base insulation film 11 having an opening 11a on the pad electrode 9a; a base metal film UM formed on the base insulation film 11; a rewiring RM formed on the base metal film UM; and a cap metal film CM formed so as to cover the top surface and side surface of the rewiring RM. In the region on the outer side of the rewiring RM, the base metal film UM, which is of a different material from the rewiring RM, and the cap metal film CM, which is of a different material from the rewiring RM, are formed between the cap metal film CM and the base insulation film 11 formed on the side wall of the rewiring RM, and in the region on the outer side of the rewiring RM, the base metal film UM and the cap metal film CM are directly in contact.

Methods of forming a microelectronic device structure, and related microelectronic device structures and microelectronic devices

A method of forming a microelectronic device structure comprises coiling a portion of a wire up and around at least one sidewall of a structure protruding from a substrate. At least one interface between an upper region of the structure and an upper region of the coiled portion of the wire is welded to form a fused region between the structure and the wire.

Electronic element and electronic device comprising the same

A first electronic element is disclosed, which includes: a first substrate having a first surface; a first electrode pad disposed on the first surface, wherein the first electrode pad has a second surface away from the first substrate; and an insulating layer disposed on the first surface, wherein the insulating layer includes an opening, the opening is disposed correspondingly to the first electrode pad, and the opening overlaps the first electrode pad in a normal direction of the first surface, wherein the insulating layer has a third surface away from the first substrate, a distance between the third surface and the second surface in the normal direction of the first surface is defined as a first distance, and the first distance is greater than 0 μm and less than or equal to 14 μm. In addition, the disclosure further provides an electronic device including the first electronic element. 1. A first electronic element , comprising:a first substrate having a first surface;a first electrode pad disposed on the first surface, wherein the first electrode pad has a second surface away from the first substrate; andan insulating layer disposed on the first surface, wherein the insulating layer comprises an opening, the opening is disposed correspondingly to the first electrode pad, and the opening overlaps the first electrode pad in a normal direction of the first surface,wherein the insulating layer has a third surface away from the first substrate, a distance between the third surface and the second surface in the normal direction of the first surface is defined as a first distance, and the first distance is greater than 0 μm and less than or equal to 14 μm.2. The first electronic element of claim 1 , wherein the first electrode pad comprises a first electrode layer and a second electrode layer claim 1 , the first electrode layer disposed between the first substrate and the second electrode layer claim 1 , and the second electrode layer electrically connects to the first ...

DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

The invention relates to display device and method of manufacturing the same. The display device includes: a substrate; a driving pad disposed on the substrate; an insulating layer exposing the driving pad and disposed on the substrate; a circuit board including a circuit pad overlapping the driving pad; and a connector disposed between the circuit board and the insulating layer and including a plurality of conductive particles electrically connecting the driving pad and the circuit pad, the driving pad including: a first pad disposed on the substrate; and a second pad disposed on the first pad and having an opening exposing the first pad.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes: a pad electrode 9 a formed in an uppermost layer of a plurality of wiring layers; a base insulating film 11 having an opening 11 a on the pad electrode 9 a ; a base metal film UM formed on the base insulating film 11 ; a redistribution line RM formed on the base metal film UM; and a cap metal film CM formed so as to cover an upper surface and a side surface of the redistribution line RM. In addition, in a region outside the redistribution line RM, the base metal film UM made of a material different from that of the redistribution line RM and the cap metal film CM made of a material different from the redistribution line RM are formed between the cap metal film CM formed on the side surface of the redistribution line RM and the base insulating film 11 , and the base metal film UM and the cap metal film CM are in direct contact with each other in the region outside the redistribution line RM.

Semiconductor packages and manufacturing methods for the same

A semiconductor package and a fabrication method of the semiconductor package are disclosed. First and second redistribution layer patterns are formed on a semiconductor substrate including a chip region and a scribe lane region to provide a bonding pad portion and an edge pad portion, respectively. A polymer pattern is formed to reveal the bonding pad portion and a portion of the edge pad portion. A dicing line is set on the scribe lane region. A stealth dicing process is performed along the dicing line to separate a semiconductor chip including the bonding pad portion from the semiconductor substrate. The semiconductor chip is disposed on a package substrate. A bonding wire is formed to connect the bonding pad portion to the package substrate. The bonding wire is supported by an edge of the polymer pattern to be spaced apart from the revealed portion of the edge pad portion.

SEMICONDUCTOR PACKAGES AND MANUFACTURING METHODS FOR THE SAME

A semiconductor package and a fabrication method of the semiconductor package are disclosed. First and second redistribution layer patterns are formed on a semiconductor substrate including a chip region and a scribe lane region to provide a bonding pad portion and an edge pad portion, respectively. A polymer pattern is formed to reveal the bonding pad portion and a portion of the edge pad portion. A dicing line is set on the scribe lane region. A stealth dicing process is performed along the dicing line to separate a semiconductor chip including the bonding pad portion from the semiconductor substrate. The semiconductor chip is disposed on a package substrate. A bonding wire is formed to connect the bonding pad portion to the package substrate. The bonding wire is supported by an edge of the polymer pattern to be spaced apart from the revealed portion of the edge pad portion. 1. A method of fabricating a semiconductor package , the method comprising:preparing a semiconductor substrate including a chip region in which first pads are disposed and a scribe lane region in which second pads are disposed, wherein the scribe lane region surrounds the chip region;forming a dielectric layer on the semiconductor substrate so as to reveal the first and second pads;forming first redistribution layer patterns connected to the first pads and second redistribution layer patterns connected to the second pads on the dielectric layer, wherein the first redistribution layer patterns extend to provide bonding pads and the second redistribution layer patterns extend to provide edge pad portions located on the scribe lane region;forming a polymer pattern covering the first and second redistribution layer patterns, wherein the polymer pattern is formed so as to reveal the bonding pad portions and a boundary region including a portion of the dielectric layer on the scribe lane region and portions of the edge pad portions;setting a dicing line extending to surround the chip region in the ...

Final passivation for wafer level warpage and ULK stress reduction

Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having an annular PSPI region formed under a BLM pad. An annular region is formed under a barrier layer metallurgy (BLM) pad. The annular region includes a photosensitive polyimide (PSPI). A conductive pedestal is formed on a surface of the BLM pad and a solder bump is formed on a surface of the conductive pedestal. The annular PSPI region reduces wafer warpage and ULK peeling stress.

SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

Disclosed embodiments include a semiconductor chip including a semiconductor substrate having a top surface with a top connection pad disposed therein, and a protection insulation layer comprising an opening therein, the protection insulation layer not covering at least a portion of the top connection pad, on the semiconductor substrate. The protection insulation layer may include: a bottom protection insulation layer, a cover insulation layer comprising a side cover part that covers at least a portion of a side surface of the bottom protection insulation layer and a top cover part disposed apart from the side cover part to cover at least a portion of a top surface of the bottom protection insulation layer. The protection insulation layer may further include a top protection insulation layer on the top cover part.

Methods and Apparatus for Package with Interposers

Methods and apparatus for an interposer with dams used in packaging dies are disclosed. An interposer may comprise a metal layer above a substrate. A plurality of dams may be formed above the metal layer around each corner of the metal layer. Dams may be formed on both sides of the interposer substrate. A dam surrounds an area where connectors such as solder balls may be located to connect to other packages. A non-conductive dam may be formed above the dam. An underfill may be formed under the package connected to the connector, above the metal layer, and contained within the area surrounded by the dams at the corner, so that the connectors are well protected by the underfill. Such dams may be further formed on a printed circuit board as well.

Semiconductor Device and Method of Manufacturing the Same

To improve the reliability of a semiconductor device. 1. A semiconductor device comprising:a semiconductor substrate;a plurality of wiring layers formed on the semiconductor substrate;a pad formed on an uppermost wiring layer of the plurality of wiring layers;a surface protection film which includes an opening on the pad and is made of an inorganic insulating film;a rewiring formed on the surface protection film; anda pad electrode which is formed on the rewiring, and is a region for connection with a wire,wherein the rewiring includes a pad electrode mounting portion on which the pad electrode is mounted, a connection portion which is connected to the pad, and an extended wiring portion which couples the pad electrode mounting portion and the connection portion, andthe pad electrode mounting portion has a rectangular shape when seen in a plan view.2. The semiconductor device according to claim 1 ,wherein the pad electrode covers an entire upper surface and a side surface of the pad electrode mounting portion.3. The semiconductor device according to claim 1 ,wherein a film thickness of the rewiring is five or more times a film thickness of the uppermost wiring layer on which the pad is formed.4. The semiconductor device according to claim 3 ,wherein the rewiring is made of a copper film.5. The semiconductor device according to claim 1 ,wherein the pad electrode mounting portion has two short sides and two long sides,the extended wiring portion is connected to one side of the two short sides, anda wiring width of the extended wiring portion is smaller than a length of the short side.6. The semiconductor device according to claim 5 ,wherein a first fin portion is connected to the other side of the two short sides, andthe first fin portion extends to an outer side of the pad electrode mounting portion.7. The semiconductor device according to claim 6 ,wherein the wire is formed on the pad electrode, andthe wire extends from the pad electrode mounting portion toward the ...

METHODS OF FORMING A MICROELECTRONIC DEVICE STRUCTURE, AND RELATED MICROELECTRONIC DEVICE STRUCTURES AND MICROELECTRONIC DEVICES

A method of forming a microelectronic device structure comprises coiling a portion of a wire up and around at least one sidewall of a structure protruding from a substrate. At least one interface between an upper region of the structure and an upper region of the coiled portion of the wire is welded to form a fused region between the structure and the wire. 1. A method of forming a microelectronic device structure , comprising: a proximal region adjacent an interface between the structure and the surface of the another structure; and', 'a distal region opposing the proximal region; and, 'coiling a portion of a wire up and around at least one sidewall of a structure protruding from a surface of another structure, the structure comprisingwelding at least one interface between an upper region of the structure and an upper region of the coiled portion of the wire to form a fused region integral and continuous with the distal region of the structure and a terminal end of the wire.2. The method of claim 1 , wherein coiling a portion of a wire up and around at least one sidewall of a structure comprises coiling the portion of the wire substantially completely around a lateral periphery of the structure at least one time.3. The method of claim 1 , wherein coiling a portion of a wire up and around at least one sidewall of a structure comprises coiling each of a sheathed region of the wire and an unsheathed region of the wire up and around the at least one sidewall of the structure.4. The method of claim 3 , wherein coiling each of a sheathed region of the wire and an unsheathed region of the wire up and around the at least one sidewall of the structure comprises:wrapping the sheathed region of the wire up and around a periphery of the structure at least one time; andwrapping the unsheathed region of the wire up and around the periphery of the structure at least one time.5. The method of claim 1 , wherein coiling a portion of a wire up and around at least one sidewall of a ...

Semiconductor Device with Metal Structure Electrically Connected to a Conductive Structure

A semiconductor device includes a semiconductor die that having a conductive structure. A metal structure is electrically connected to the conductive structure and contains a first metal. An auxiliary layer stack is sandwiched between the conductive structure and the metal structure and includes an adhesion layer that contains a second metal. The auxiliary layer stack further includes a metal diffusion barrier layer between the adhesion layer and the conductive structure. The adhesion layer contains the first metal and a second metal. 1. A semiconductor device comprising:a semiconductor die that comprises a conductive structure;a metal structure electrically connected to the conductive structure and containing a first metal; andan auxiliary layer stack sandwiched between the conductive structure and the metal structure and comprising an adhesion layer containing a second metal and a metal diffusion barrier layer between the adhesion layer and the conductive structure, wherein the adhesion layer contains the first metal and a second metal.2. The semiconductor device of claim 1 , further comprising a dielectric passivation layer between the metal structure and the conductive structure claim 1 , wherein the metal structure is electrically connected to the conductive structure through an opening in the dielectric passivation layer.3. The semiconductor device of claim 1 , wherein the semiconductor die comprises a semiconductor portion comprising a doped region forming the conductive structure.4. The semiconductor device of claim 1 , wherein the semiconductor die comprises a semiconductor portion and a wiring line electrically connected to a doped region formed in the semiconductor portion claim 1 , the wiring line forming the conductive structure.5. The semiconductor device of claim 1 , wherein the auxiliary layer stack comprises an auxiliary barrier layer between the metal structure and the adhesion layer.6. The semiconductor device of claim 1 , wherein the metal ...

Bond pad having ruthenium directly on passivation sidewall

A method of forming bond pads includes providing a substrate including an integrated circuit (IC) device formed thereon having an oxidizable uppermost metal interconnect layer which provides a plurality of bond pads that are coupled to circuit nodes on the IC device. The plurality of bond pads include a metal bond pad area. At least one passivation layer provides a trench including dielectric sidewalls above the metal bond pad area. A ruthenium (Ru) layer is deposited directly on the dielectric sidewalls and directly on the metal bond pad area, which removes the need for a barrier layer lining the dielectric sidewalls of the trench. The Ru layer is patterned to provide a bond pad surface for the plurality of bond pads.

Package substrate and method for fabricating the same

一种封装基板及其制法，该制法包括提供一具有相对的第一表面与第二表面的基板本体，该第一表面上形成有多个第一电性连接垫，并于该等第一电性连接垫上接置一金属板，再图案化该金属板，以于各该第一电性连接垫上对应定义出一金属柱。本发明能有效改善金属柱的毛边问题及金属柱的高度不一问题。

Semiconductor device

Redistribution layer (rdl) structure, semiconductor device and manufacturing method thereof

The present disclosure provides a redistribution layer (RDL) structure, a semiconductor device and manufacturing method thereof. The semiconductor device comprises an RDL structure that may include a substrate, a first conductive layer, a reinforcement layer and a second conductive layer. The first conductive layer may be formed on the substrate and has a first bond pad area. The reinforcement layer may be formed on a surface of the first conductive layer facing away from the substrate and located in the first bond pad area. The second conductive layer may be formed on the reinforcement layer and an area of the first conductive layer not covered by the reinforcement layer. The reinforcement layer has a material strength greater than those of the first conductive layer and the second conductive layer. The semiconductor device and the manufacturing method provided by the present disclosure may improve the performance of the semiconductor device.

Semiconductor device and manufacturing method for same

Semiconductor device and method for manufacturing semiconductor device

【課題】樹脂材料部分の収縮による影響を抑制するのに適した半導体装置、および半導体装置の製造方法を提供する。【解決手段】第１および第２絶縁層３１，３３を形成する工程を備え、第１絶縁層３１を形成する工程では、第１電極２１の周縁部２１１と主面とに跨って配置された第１環状部３１０を形成し、第２絶縁層３３を形成する工程は、第１環状部３１０と重なる環状をなし、かつ樹脂材料からなる第２環状部３３０を配置するステップと、第２環状部３３０を加熱するステップと、を含み、第１環状部３１０の外端境界線３１１と第２環状部３３０の外端境界線３３１との方向ｙにおける距離Ｄ１は、方向ｘの中央よりも外端境界線３３２寄りの端部において大とされ、第１環状部３１０の外端境界線３１２と第２環状部３３０の外端境界線３３２との方向ｘにおける距離Ｄ２は、方向ｙの中央よりも外端境界線３３１寄りの端部において大とされる。【選択図】図１７

Flip chip

本发明一实施例的倒装芯片，其特征在于，包括：基板；层压在所述基板上的电极焊盘层；层压在所述电极焊盘层的两侧末端的钝化层；层压在所述电极焊盘层及所述钝化层上的UMB层；形成在所述UBM层上的凸点，所述电极焊盘层上未层压所述钝化层的开口的宽度大于所述凸点的宽度。本发明的倒装芯片能够防止超声波焊接时焊盘上产生裂纹。

Semiconductor device with a plurality of semiconductor chips

在半导体装置中，第1金属层(22)形成在半导体衬底(21)的一面上。第1保护膜(23)在第1金属层上具有开口部(23a)，以将第1金属层的端部覆盖的方式形成。在开口部(23a)中，在第1金属层上形成有第2金属层(24)，在第2金属层上形成有防氧化层(25)。第2保护膜(26)具有开口部(26a)，以将防氧化层的端部及第1保护膜覆盖的方式形成。并且，与防氧化层相比对第2保护膜的密接性高的密接部(27)与第2保护膜中的开口周缘部(26c)的下表面的一部分密接。

METHODS OF FORMING A MICRO-ELECTRONIC DEVICE STRUCTURE, AND MICRO-ELECTRONIC DEVICE STRUCTURES AND RELATED MICRO-ELECTRONIC DEVICES

Semiconductor device

In a semiconductor device, a first protection film covers an end portion of a first metal layer disposed on a semiconductor substrate, and has a first opening above the first metal layer. A second metal layer is disposed on the first metal layer in the first opening. An oxidation inhibition layer is disposed on the second metal layer in the first opening. A second protection film has a second opening and covers an end portion of the oxidation inhibition layer and the first protection film. The second protection film has an opening peripheral portion on a periphery of the second opening, and covers the end portion of the oxidation inhibition layer. An adhesion portion adheres to a portion of a lower surface of the opening peripheral portion. The adhesion portion has a higher adhesive strength with the second protection film than the oxidation inhibition layer.

칩-투-웨이퍼 장치용 반도체 장치 및 언더필 댐 형성 방법

반도체 장치는 감지 영역이 있는 반도체 다이를 갖는다. 댐 벽은 감지 영역에 근접한 반도체 다이 위에 형성된다. 일 실시예에서, 댐 벽은 수직 세그먼트 및 측면 윙을 갖는다. 댐 벽은 단일체로서 복수의 수직 세그먼트와 통합된 복수의 둥근 세그먼트를 가질 수 있다. 대안적으로, 댐 벽은 2개 이상의 중첩 행으로 배열된 복수의 개별 수직 세그먼트를 갖는다. 복수의 전도성 포스트가 반도체 다이 위에 형성된다. 반도체 다이 위에 전기 구성요소가 배치된다. 반도체 다이 및 전기 구성요소는 기판 위에 배치된다. 댐 벽 외부의 기판 위에 절연 층이 형성된다. 반도체 다이와 기판 사이에 언더필 재료가 증착된다. 댐 벽과 절연 층은 언더필 재료가 감지 영역의 일부와 접촉하는 것을 방지한다.

半导体结构

本发明公开一种半导体结构，包括基底、介电层、第一导电层与保护层。介电层设置在基底上。第一导电层设置在介电层上。保护层设置在第一导电层与介电层上。保护层包括第一上表面与第二上表面。第一上表面位于第一导电层的顶面上方。第二上表面位于第一导电层的一侧。第一上表面的高度高于第二上表面的高度。第二上表面的高度低于或等于位于介电层的顶面与第一导电层之间的第一导电层的下表面的高度。

칩 패키지 구조 및 그 칩

칩 패키지 구조는 마이크로 칩을 기판에 전기적으로 연결시키기 위한 것으로, 특히 LED에 응용되고, 상기 칩 패키지 구조의 칩은 본체 및 적어도 하나의 전극을 포함하며, 상기 전극은 상기 본체의 표면에 설치되며, 또한 상기 표면으로부터 노출되고, 상기 전극은 위치한정 홈 및 상기 위치한정 홈의 주변에 위치하는 위치한정 벽을 구비하며, 상기 위치한정 벽은 접착제 중의 적어도 하나의 도전성 입자를 상기 위치한정 홈에 위치 한정시키며, 또한 상기 칩은 상기 위치한정 홈에 위치한 상기 도전성 입자를 통해 상기 전극과 기판의 접속패드를 전기적으로 연결시킨다.

Chip-scale package

Aspects of the present disclosure relate to a semiconductor device such as a chip-scale package. Aspects of the present disclosure further relate to a method for manufacturing such a device.According to an aspect of the present disclosure, a semiconductor device is provided that comprises a conformal coating arranged on its sidewalls and on the perimeter part of the semiconductor die of the semiconductor device. To prevent the conformal coating from covering unwanted areas, such as electrical terminals, a sacrificial layer is arranged prior to arranging the conformal coating. By removing the sacrificial layer, the conformal coating can be removed locally. The conformal coating covers the perimeter part of the semiconductor die comprises by the semiconductor device, in which part a remainder of a sawing line or dicing street is provided.

Packaged Semiconductor Devices And Methods of Packaging Thereof

Packaging methods for semiconductor devices and methods of packaging thereof are disclosed. In some embodiments, a device includes a packaging apparatus and contact pads disposed on the packaging apparatus. The contact pads are arranged in an array of rows and columns. The contact pads include first contact pads proximate a perimeter region of the packaging apparatus and second contact pads disposed in an interior region of the packaging apparatus. A dam structure that is continuous is disposed around the second contact pads. The contact pads comprise a mounting region for a semiconductor device.

Display backboard and manufacturing method thereof and display device

A display backboard and a manufacturing method thereof, and a display device are provided. The display backboard includes: a driving substrate; a plurality of driving electrodes on the driving substrate; and a plurality of connection structures respectively on the plurality of driving electrodes. The connection structure includes: at least one conductive component on the driving electrode; and a restriction component on a side of the driving electrodes provided with the at least one conductive component and in at least a part of a peripheral region of the at least one conductive component. The restriction component protrudes from the driving electrode and has a first height in a direction perpendicular to the driving substrate.

用於晶片對晶圓裝置之形成有底部填充阻擋件的半導體裝置及方法

一種半導體裝置，其具有半導體晶粒，半導體晶粒具有敏感區域。阻擋壁在半導體晶粒上方靠近敏感區域形成。在實施例中，阻擋壁具有垂直區段及側翼。阻擋壁能具有與複數個垂直區段整合為一單體本體之複數個圓形區段。替代地，阻擋壁具有以兩個或多於兩個重疊列布置之複數個分開的垂直區段。複數個導體柱形成於半導體晶粒上方。電組件設置於半導體晶粒上方。半導體晶粒該組件設置於基板上方。絕緣層在基板上方而於阻擋壁外形成。底部填充材料沉積於半導體晶粒與基板之間。阻擋壁及絕緣層抑制底部填充材料接觸敏感區域之任何部分。

半導体装置

【課題】半導体素子にクリップが接合されてなる半導体装置において、半導体素子とクリップとの接合部分の近傍における局所的な発熱を抑制し、信頼性を向上する。 【解決手段】半導体装置１は、半導体素子３とクリップ８とが接合材４を介して接合されると共に、これらの間に熱抵抗部としての絶縁層７が配置されている。半導体素子３とクリップ８との間であって、接合材４を介して接合された領域を接合領域とすると、接合領域は、絶縁層７が配置された部分の放熱性が、接合領域の他の部分よりも小さくなっている。これにより、クリップ８において意図的に発熱領域が設けられ、半導体装置１における発熱領域が分散される結果、半導体素子３とクリップ８との接合部分の近傍における局所的な発熱が抑制される。 【選択図】図３

Method of manufacturing a semiconductor device having a bond wire or clip bonded to a bonding pad

A method of manufacturing a semiconductor device includes: forming a base portion of a bonding pad on a semiconductor portion, the base portion further comprising a base layer; forming a main surface of the bonding pad, the main surface comprising a bonding region; bonding a bond wire or clip to the bonding region; and forming a supplemental structure directly on the base portion. The supplemental structure laterally adjoins the bond wire or clip or is laterally spaced apart from the bond wire or clip. A volume-related specific heat capacity of the supplemental structure is higher than a volume-related specific heat capacity of the base layer.

Chip-scale packaged vertical semiconductor device

Aspects of the present disclosure relate to a vertical semiconductor device. Aspects of the present disclosure further relate to a method for manufacturing such a vertical semiconductor device.According to an aspect of the present disclosure, a vertical semiconductor device is provided that comprises a conformal coating arranged on its sidewalls. To prevent the conformal coating from covering unwanted areas, such as electrical terminals, a sacrificial layer is arranged prior to arranging the conformal coating. By removing the sacrificial layer, the conformal coating can be removed locally.

Chip-scale package

A semiconductor device such as a chip-scale package is provided. Aspects of the present disclosure further relate to a method for manufacturing such a device. According to an aspect of the present disclosure, a semiconductor device is provided that includes a conformal coating arranged on its sidewalls and on the perimeter part of the semiconductor die of the semiconductor device. To prevent the conformal coating from covering unwanted areas, such as electrical terminals, a sacrificial layer is arranged prior to arranging the conformal coating. By removing the sacrificial layer, the conformal coating can be removed locally. The conformal coating covers the perimeter part of the semiconductor die by the semiconductor device, in which part a remainder of a sawing line or dicing street is provided.

Verfahren zur Herstellung eines Halbleitermoduls

Ein Herstellungsverfahren eines Halbleitermoduls (10), umfassend:Vorbereiten eines ersten Halbleiterchips (11), umfassend eine erste Oberfläche (11a) und eine auf der ersten Oberfläche (11a) vorgesehene erste Elektrode (15), wobei die erste Elektrode (15) einen ersten Bereich und einen zweiten Bereich umfasst;Anordnen eines linearen Körpers (13) in einem Bereich zwischen dem ersten Bereich und dem zweiten Bereich; undBonden eines Metalldrahts (14) an den ersten Bereich, Biegen des Metalldrahts (14) nach oben weg von der ersten Oberfläche (11a) unter Verwendung des linearen Körpers (13) als ein Stützelement, und Bonden des Metalldrahts (14) an dem zweiten Bereich, wobeider lineare Körper (13) ein metallischer Draht desselben Typs wie der Metalldraht (14) ist.

Semiconductor chip and semiconductor package including the same

Disclosed embodiments include a semiconductor chip including a semiconductor substrate having a top surface with a top connection pad disposed therein, and a protection insulation layer comprising an opening therein, the protection insulation layer not covering at least a portion of the top connection pad, on the semiconductor substrate. The protection insulation layer may include: a bottom protection insulation layer, a cover insulation layer comprising a side cover part that covers at least a portion of a side surface of the bottom protection insulation layer and a top cover part disposed apart from the side cover part to cover at least a portion of a top surface of the bottom protection insulation layer. The protection insulation layer may further include a top protection insulation layer on the top cover part.

Passivation Structure for Metal Pattern

A semiconductor device and method of manufacturing the same are provided. The semiconductor device may include a substrate, a first via, a first pad, a second pad, and a first passivation layer. The first pad may be over the substrate. The second pad may be over the substrate. The second pad may be parallel to the first pad. The first passivation layer may surround the first pad and the second pad. The first passivation layer may include a first part on the first pad. The first passivation layer may include a second part on the second pad. A thickness of the first part of the first passivation layer may exceed a height of the first pad. A thickness of the second part of the first passivation layer may exceed a height of the second pad.

Semiconductor device including base pillar, connection pad, and insulation layer disposed on a substrate

A semiconductor device includes a semiconductor substrate and a connection terminal, including a base pillar, on the semiconductor substrate. An insulation layer is formed on the semiconductor substrate, the insulation layer including an opening in the insulation layer through which the base pillar extends, wherein a side wall of the insulation layer defining the opening includes a horizontal step at a level that is lower than an uppermost portion of the base pillar.

半导体装置

在半导体装置中，第1金属层(22)形成在半导体衬底(21)的一面上。第1保护膜(23)在第1金属层上具有开口部(23a)，以将第1金属层的端部覆盖的方式形成。在开口部(23a)中，在第1金属层上形成有第2金属层(24)，在第2金属层上形成有防氧化层(25)。第2保护膜(26)具有开口部(26a)，以将防氧化层的端部及第1保护膜覆盖的方式形成。并且，与防氧化层相比对第2保护膜的密接性高的密接部(27)与第2保护膜中的开口周缘部(26c)的下表面的一部分密接。

Semiconductor device

According to an aspect of the present disclosure, a semiconductor device includes a semiconductor substrate, a lower electrode provided on the semiconductor substrate, an insulating film that is provided on the semiconductor substrate and surrounds the lower electrode and a metal film that is provided on the lower electrode and includes a convex portion on an upper surface thereof, wherein the convex portion includes a first portion extending in a first direction parallel to an upper surface of the semiconductor substrate, and a second portion extending in a second direction that is parallel to the upper surface of the semiconductor substrate and intersects the first direction, and the metal film is thinner than the insulating film.

半导体装置以及半导体封装

实施方式提高可靠性较高的半导体装置以及半导体封装。实施方式的半导体装置具备第一半导体芯片、有机绝缘膜、以及再布线层。所述第一半导体芯片具有第一焊盘、以及形成有凹部的第二焊盘。所述有机绝缘膜设于所述第一半导体芯片上，覆盖所述凹部，不覆盖所述第一焊盘的至少一部分。所述再布线层的下部与所述第一焊盘连接，上部配置于所述有机绝缘膜上。

Display backboard and manufacturing method thereof and display device

A display backboard and a manufacturing method thereof, and a display device are provided. The display backboard includes: a driving substrate; a plurality of driving electrodes on the driving substrate; and a plurality of connection structures respectively on the plurality of driving electrodes. The connection structure includes: at least one conductive component on the driving electrode; and a restriction component on a side of the driving electrodes provided with the at least one conductive component and in at least a part of a peripheral region of the at least one conductive component. The restriction component protrudes from the driving electrode and has a first height in a direction perpendicular to the driving substrate.

显示装置和拼接显示装置

本公开涉及显示装置和拼接显示装置。显示装置包括：衬底；多个电极焊盘，包括在衬底上的第一电极焊盘和公共电极焊盘；发光元件，包括在第一电极焊盘上的第一接触电极和在公共电极焊盘上的第二接触电极；导电粘合构件，包括连接第一电极焊盘和第一接触电极并连接公共电极焊盘和第二接触电极的多个导电球；以及多个突出部，在衬底上并且在衬底的厚度方向上突出。多个突出部中的第一突出部在衬底的厚度方向上与电极焊盘重叠。

为芯片到晶片器件形成底部填充坝的半导体器件和方法

为芯片到晶片器件形成底部填充坝的半导体器件和方法。一种半导体器件具有带敏感区域的半导体管芯。在半导体管芯上形成靠近敏感区域的坝壁。在一个实施例中，坝壁具有垂直区段和侧翼。坝壁可以具有多个圆形区段，所述多个圆形区段与多个垂直区段集成为一体。可替代地，坝壁具有布置成两个或更多个重叠排的多个分开的垂直区段。在半导体管芯上形成多个导电支柱。电气组件设置在半导体管芯上。半导体管芯和电气组件设置在衬底上。在衬底上形成在坝壁外部的绝缘层。底部填充材料沉积在半导体管芯和衬底之间。坝壁和绝缘层抑制底部填充材料接触敏感区域的任何部分。

Semiconductor Device and Method of Forming Underfill Dam for Chip-to-Wafer Device

A semiconductor device has a semiconductor die with a sensitive area. A dam wall is formed over the semiconductor die proximate to the sensitive area. In one embodiment, the dam wall has a vertical segment and side wings. The dam wall can have a plurality of rounded segments integrated with a plurality of vertical segments as a unitary body. Alternatively, the dam wall has a plurality of separate vertical segments arranged in two or more overlapping rows. A plurality of conductive posts is formed over the semiconductor die. An electrical component is disposed over the semiconductor die. The semiconductor die and electrical component are disposed over a substrate. An insulating layer is formed over the substrate outside the dam wall. An underfill material is deposited between the semiconductor die and substrate. The dam wall and insulating layer inhibit the underfill material from contacting any portion of the sensitive area.

Sealing ring, stacked structure, and method for manufacturing sealing ring

Embodiments of the disclosure provide a sealing ring, a stacked structure, and a method for manufacturing a sealing ring. The sealing ring is arranged at a periphery of a device area of a chip, and includes an inner ring structure, a middle ring structure, and an outer ring structure. The middle ring structure is connected to the device area through a doped well. The doped well is located in part of a substrate corresponding to the inner ring structure and the middle ring structure, and is isolated from the inner ring structure.

Method for fabricating semiconductor device with stress-relieving structures

The present application provides a method for fabricating a semiconductor device including providing a semiconductor substrate, forming a first stress-relieving structure including a first conductive frame above the semiconductor substrate and a plurality of first insulating pillars within the first conductive frame, forming a second stress-relieving structure comprising a plurality of second conductive pillars above the first stress-relieving structure and a second insulating frame, the plurality of second conductive pillars are disposed within the second conductive frame, wherein the plurality of second conductive pillars is disposed correspondingly above the plurality of first insulating pillars, and the second insulating frame is disposed correspondingly above the first conductive frame; and forming a conductive structure including a supporting portion above the second stress-relieving structure, a conductive portion adjacent to the supporting portion, and a plurality of spacers attached to two sides of the conductive portion.

半导体封装件及其制造方法

公开半导体封装件及其制造方法。在包括芯片区域和划线道区域的半导体基板上形成第一重分布层图案和第二重分布层图案，以分别提供接合焊盘部分和边缘焊盘部分。聚合物图案形成为显露接合焊盘部分和边缘焊盘部分的一部分。在划线道区域上设置切片线。沿着切片线执行隐形切片工艺，以将包括接合焊盘部分的半导体芯片从半导体基板分离。半导体芯片设置在封装基板上。接合布线形成为将接合焊盘部分连接至接合指。接合布线由聚合物图案的边缘支撑以与边缘焊盘部分的暴露部分间隔开。

Chip package and chip thereof

A microchip (200) is electrically connected to a substrate (100) to become a chip package, preferably for LED. A chip (200) of the package includes a body (210) and at least one electrode (220, 230) which is disposed and exposed on a surface of the body (210). The electrode (220, 230) includes a confining groove (221, 231) and a confining wall. (222, 232) The confining wall (222, 232) is peripherally located around the confining groove (221, 231) and provided to confine at least one conductive particle (310, 320) of an adhesive (300) in the confining groove (221, 231). The electrode of the chip (200) is electrically connected to a bonding pad (110, 120) of a substrate (200) via the conductive particle (310, 320) confined in the confining groove (221,231).

チップパッケージ及びチップ

【課題】チップパッケージ及びチップを提供する。【解決手段】本発明のチップパッケージ及びチップは、微細チップを基板に電気的に接続させるために用いられ、特に発光ダイオードに適用される。前記チップパッケージのチップ２００は本体２１０及び前記本体２１０の表面２１１に設置されると共に前記表面２１１に露出される少なくとも１つの電極２２０を備え、前記電極２２０は第一位置限定溝２２１及び前記第一位置限定溝２２１周辺に位置する第一位置限定壁２２２を有し、前記第一位置限定壁２２２は接着剤３００中の少なくとも１つの導電性粒子３１０の位置を前記第一位置限定溝２２１に制限するために用いられる。前記チップ２００は前記第一位置限定溝２２１中に位置する前記導電性粒子３１０を介して前記電極２２０及び基板１００の第一導電パッド１１０に電気的に接続される。【選択図】図１

칩 패키지 구조 및 그 칩

칩 패키지 구조는 마이크로 칩을 기판에 전기적으로 연결시키기 위한 것으로, 특히 LED에 응용되고, 상기 칩 패키지 구조의 칩은 본체 및 적어도 하나의 전극을 포함하며, 상기 전극은 상기 본체의 표면에 설치되며, 또한 상기 표면으로부터 노출되고, 상기 전극은 위치한정 홈 및 상기 위치한정 홈의 주변에 위치하는 위치한정 벽을 구비하며, 상기 위치한정 벽은 접착제 중의 적어도 하나의 도전성 입자를 상기 위치한정 홈에 위치 한정시키며, 또한 상기 칩은 상기 위치한정 홈에 위치한 상기 도전성 입자를 통해 상기 전극과 기판의 접속패드를 전기적으로 연결시킨다.

Semiconductor device

A semiconductor device includes a lead frame, a semiconductor element, a clip, a sealing material, and a thermal resistance portion. The semiconductor element is mounted on the lead frame. The clip is bonded through a bonding material to an electrode on a surface of the semiconductor element opposite to the lead frame. The sealing material covers the semiconductor element and the clip. The thermal resistance portion is disposed in a bonding region bonded through the bonding material between the semiconductor element and the clip. The thermal resistance portion has a thermal resistance higher than that of a different portion in the bonding region.

칩-스케일 패키지

본 발명의 양태는 칩-스케일 패키지와 같은 반도체 디바이스에 관한 것이다. 본 발명의 양태는 또한 이러한 디바이스를 제조하는 방법에 관한 것이다. 본 발명의 양태에 따르면, 반도체 디바이스의 반도체 다이의 측벽 상에 그리고 주변 부분 상에 배열된 컨포멀 코팅을 포함하는 반도체 디바이스가 제공된다. 컨포멀 코팅이 전기 터미널과 같은 원하지 않는 영역을 덮는 것을 방지하기 위해 컨포멀 코팅을 배열하기 전에 희생층이 배열된다. 희생층을 제거함으로써, 컨포멀 코팅을 국부적으로 제거될 수 있다. 컨포멀 코팅은 반도체 디바이스에 포함된 반도체 다이의 주변 부분을 덮으며, 이 부분에 소잉 라인 또는 다이싱 스트리트의 나머지 부분이 제공된다.

チップスケールパッケージ

【課題】短絡の危険が存在しないチップスケールパッケージ及びそのようなデバイスを製造する方法を提供する。【解決手段】側壁及び半導体デバイスの半導体ダイ３０’の周囲部分に配置されたコンフォーマルコーティング３４を備える半導体デバイスの製造方法であって、コンフォーマルコーティング３４が電気端子Ｔ１、Ｔ２等の領域を覆うことを防ぐために、コンフォーマルコーティング３４を配置Ｓ１＿４する前に犠牲層３２を配置しＳ１＿２、犠牲層３２をフォトアブレーションによって除去するＳ１＿５ことにより、コンフォーマルコーティング３４を局所的に除去する。コンフォーマルコーティング３４は、半導体デバイスによって構成される半導体ダイ３０’の周囲部分を覆い、その部分には、ソーイングライン又はダイシングストリートの残部が設けられる。【選択図】図６

晶片級封裝

本公開的各方面涉及諸如晶片級封裝件的半導體裝置。本公開的各方面還涉及一種用於製造這種裝置的方法。根據本公開的一方面，提供了一種半導體裝置，該半導體裝置包括佈置在其側壁上和半導體裝置的半導體裸片的周邊部分上的共形塗層。為了防止共形塗層覆蓋諸如電端子的不需要的區域，在佈置共形塗層之前佈置犧牲層。通過去除犧牲層，可以局部地去除共形塗層。共形塗層覆蓋半導體裝置所包括的半導體裸片的周邊部分，在該周邊部分中提供了鋸切線或切割道的剩餘部分。

顯示裝置及拼接顯示裝置

本發明提供了一種顯示裝置，包含一基板、複數個電極焊墊、發光元件、導電黏合構件以及複數個突起。複數個電極焊墊包含位於基板上的第一電極焊墊和一共同電極焊墊，發光元件包含在第一電極焊墊上的第一接觸電極和在共同電極焊墊上的一第二接觸電極，導電黏合構件包含複數個導電球，複數個導電球將第一電極焊墊連接至第一接觸電極，並且將共同電極焊墊連接到第二接觸電極，複數個突起位於基板上並且沿著基板的厚度方向突出。其中，複數個突起中的複數個第一突起在基板的厚度方向上與複數個電極焊墊重疊。

显示装置和制造该显示装置的方法

本发明涉及显示装置和制造该显示装置的方法。该显示装置包括：基板；驱动焊盘，被布置在基板上；绝缘层，暴露驱动焊盘并且被布置在基板上；电路板，包括与驱动焊盘重叠的电路焊盘；以及连接件，被布置在电路板和绝缘层之间并且包括电连接驱动焊盘和电路焊盘的多个导电颗粒，驱动焊盘包括：第一焊盘，被布置在基板上；以及第二焊盘，被布置在第一焊盘上并且具有暴露第一焊盘的开口。

Semiconductor structure with low-melting-temperature conductive regions, and method of repairing a semiconductor structure

A semiconductor structure includes at least a semiconductor body, a delimiting structure delimiting a cup-shaped recess in the body and a conductive region in the recess. The conductive region is made of a low-melting-temperature material, having a melting temperature lower than that of the materials forming the delimiting structure.

半導体モジュールおよびその製造方法

【課題】 半導体チップに大電流を通電可能で信頼性の高い半導体モジュールおよびその製造方法を提供することにある。【解決手段】 半導体モジュール１０は、第１の面１１ａに第１の領域と第２の領域とを有する第１電極１５が設けられた第１半導体チップ１１と、第１の面１１ａより上方に湾曲する湾曲部を有し、湾曲部の両端が第１の領域と第２の領域とに接続された金属ワイヤー１４と、湾曲部と第１の面１１ａとの間に配置された線状体１３と、を具備する。【選択図】 図１

Method for fabricating semiconductor device with stress-relieving structures

The present application provides a method for fabricating a semiconductor device including providing a semiconductor substrate, forming a first stress-relieving structure including a first conductive frame above the semiconductor substrate and a plurality of first insulating pillars within the first conductive frame, forming a second stress-relieving structure comprising a plurality of second conductive pillars above the first stress-relieving structure and a second insulating frame, the plurality of second conductive pillars are disposed within the second conductive frame, wherein the plurality of second conductive pillars is disposed correspondingly above the plurality of first insulating pillars, and the second insulating frame is disposed correspondingly above the first conductive frame; and forming a conductive structure including a supporting portion above the second stress-relieving structure, a conductive portion adjacent to the supporting portion, and a plurality of spacers attached to two sides of the conductive portion.

半导体装置

提供了一种半导体装置，所述半导体装置可以包括半导体基底和位于半导体基底上的连接基体柱。绝缘层可以位于半导体基底上，绝缘层可以包括位于绝缘层中的开口，连接基体柱穿过开口延伸，其中，绝缘层的限定开口的侧壁包括位于比连接基体柱的最上部分低的水平处的水平台阶。

具有應力釋放結構的半導體元件及其製備方法

本揭露提供一種具有二應力釋放結構的半導體元件及該半導體元件的製備方法。該半導體元件具有一半導體基底、一第一應力釋放結構、一第二應力釋放結構以及一導電結構；該第一應力釋放結構具有一第一導電框架以及複數個第一隔離栓柱，該第一導電框架位在該半導體基底上，該複數個第一隔離栓柱位在該第一導電框架內；該第二應力釋放結構具有複數個第二導電栓柱以及一第二隔離框架，該複數個第二導電栓柱位在該第一應力釋放結構上，並位在該第二隔離框架內；該導電結構具有一支撐部、一導電部以及複數個間隙子，該支撐部位在該第二應力釋放結構上，該導電部位在鄰近該支撐部處，該複數個間隙子貼合到該導電部的兩側處。該複數個第二導電栓柱對應設置在複數個第一隔離栓柱上，以及該第二隔離框架對應設置在該第一導電框架上。

Semiconductor device with stress-relieving structures and method for fabricating the same

The present application discloses a semiconductor device with two stress-relieving structures and a method for fabricating the semiconductor device. The semiconductor device includes a semiconductor substrate, a first stress-relieving structure including a first conductive frame positioned above the semiconductor substrate and a plurality of first insulating pillars positioned within the conductive frame, a second stress-relieving structure including a plurality of second conductive pillars positioned above the first stress-relieving structure and a second insulating frame, the plurality of second conductive pillars is positioned within the second insulating frame, and a conductive structure including a supporting portion positioned above the second stress-relieving structure, a conductive portion positioned adjacent to the supporting portion, and a plurality of spacers attached to two sides of the conductive portion. The plurality of second conductive pillars is disposed correspondingly above the plurality of first insulating pillars, and the second insulating frame is disposed correspondingly above the first conductive frame.

半导体元件及其制备方法

本公开提供一种半导体元件及其制备方法。该半导体元件具有一半导体基底、一第一应力释放结构、一第二应力释放结构以及一导电结构；第一应力释放结构具有一第一导电框架以及多个第一隔离栓柱，第一导电框架位在半导体基底上，该多个第一隔离栓柱位在第一导电框架内；第二应力释放结构具有多个第二导电栓柱以及一第二隔离框架，该多个第二导电栓柱位在第一应力释放结构上，并位在第二隔离框架内；该导电结构具有一支撑部、一导电部以及多个间隙子，支撑部位在第二应力释放结构上，导电部位在邻近支撑部处，该多个间隙子贴合到导电部的两侧处。该多个第二导电栓柱对应设置在多个第一隔离栓柱上，以及第二隔离框架对应设置在第一导电框架上。

Semiconductor device with edge-protecting spacers over bonding pad

The present application provides a semiconductor device with an edge-protecting spacer over a bonding pad. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a dielectric liner disposed between the first spacer and the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate, wherein the dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the bonding pad and covering the first spacer and the dielectric liner, wherein the conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad.

用于金属图案的钝化层结构

本发明实施例涉及用于金属图案的钝化层结构。本文提供了一种半导体元件及其制造方法。前述半导体元件可以包含衬底、第一通孔、第一衬垫、第二衬垫以及第一钝化层。所述第一衬垫可以位于所述衬底上方。所述第二衬垫可以位于所述衬底上方。所述第二衬垫可以平行于所述第一衬垫。所述第一钝化层可以围绕所述第一衬垫以及所述第二衬垫。第一钝化层可以包含位于所述第一衬垫上的第一部分。所述第一钝化层可以包含位于所述第二衬垫上的第二部分。所述第一钝化层的所述第一部分的厚度可以超过所述第一衬垫的高度。所述第一钝化层的所述第二部分的厚度可以超过所述第二衬垫的高度。

用於金屬圖案的鈍化層結構

本文提供了一種半導體元件及其製造方法。前述半導體元件可以包含基板、第一通孔、第一襯墊、第二襯墊以及第一鈍化層。該第一襯墊可以位於該基板上方。該第二襯墊可以位於該基板上方。該第二襯墊可以平行於該第一襯墊。該第一鈍化層可以圍繞該第一襯墊以及該第二襯墊。第一鈍化層可以包含位於該第一襯墊上的第一部分。該第一鈍化層可以包含位於該第二襯墊上的第二部分。該第一鈍化層的該第一部分的厚度可以超過該第一襯墊的高度。該第一鈍化層的該第二部分的厚度可以超過該第二襯墊的高度。

Integrierte schaltung, die freiliegende leitungen besitzt

Eine elektronische Vorrichtung, die ein Halbleitersubstrat und eine leitende Struktur, die über dem Halbleitersubstrat angeordnet ist, enthält. Eine Isolatorschicht überlagert das Halbleitersubstrat und enthält eine sich verjüngende Öffnung, die einen Abschnitt der leitenden Struktur überlagert. Eine Flanschleitersäule, die einen Basisabschnitt enthält, ist in der sich verjüngenden Öffnung angeordnet und ist an den Abschnitt der leitenden Struktur gekoppelt. Die Flanschleitersäule enthält ferner einen Flanschabschnitt, der konfiguriert ist, freizuliegen, um einen leitenden Kontakt zur elektronischen Vorrichtung zu schaffen.