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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 5520. Отображено 100.
05-01-2012 дата публикации

Double molded chip scale package

Номер: US20120001322A1
Автор: Luke England, Yong Liu
Принадлежит: Fairchild Semiconductor Corp

Chip scale semiconductor packages and methods for making and using the same are described. The chip scale semiconductor packages (CSPs) contain a die with an integrated circuit device, a patterned plating layer, and a second interconnect structure formed from a Cu etched substrate that has a portion of an upper surface connected to the patterned plating layer, a side surface, and a bottom surface. The die can be attached to the patterned plating layer by a first interconnect structure that uses wirebonding or that uses a flip chip attachment process. The CSP contains a double molded structure where a first molding layer encapsulates the die, the patterned plating layer, the first interconnect structure, and the upper surface of the second interconnect structure. The second molding layer encapsulates the side surface of the second interconnect structure without encapsulating the bottom surface of the second interconnect structure. With such a configuration, the second molding layer helps control warpage during the manufacturing process and no printed circuit board (PCB) substrate is needed when the package is used in an electronic device since the signal routing is performed by the second interconnect structure. Other embodiments are described.

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Номер записи: 1
05-01-2012 дата публикации

Semiconductor package having a stacked structure

Номер: US20120001347A1
Автор: Chan-Min Han, Jin-yang Lee, Kil-Soo Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor package includes a substrate, a first semiconductor chip stacked on the substrate and a second semiconductor chip stacked on the first semiconductor chip. In the semiconductor package, the second semiconductor chip is rotated to be stacked on the first semiconductor chip. The semiconductor package is used in an electronic system.

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Номер записи: 2
26-01-2012 дата публикации

Semiconductor Device and Method of Forming RDL Wider than Contact Pad along First Axis and Narrower than Contact Pad Along Second Axis

Номер: US20120018904A1
Автор: Jianmin Fang, KANG Chen, Xia Feng, Yaojian Lin
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer.

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Номер записи: 3
01-03-2012 дата публикации

Conductive connection structure with stress reduction arrangement for a semiconductor device, and related fabrication method

Номер: US20120049343A1
Автор: Frank Kuechenmeister, Lei Fu, Michael Su, Thomas Schulze
Принадлежит: Advanced Micro Devices Inc, Globalfoundries Inc

A semiconductor device disclosed herein includes a conductive connection structure having a stepped profile that serves as a stress relief feature. The conductive connection structure includes a stress buffer arrangement for a contact pad. The stress buffer arrangement has a stepped via that terminates at the contact pad, and the stepped via has a plurality of inwardly sloped and concentric sections in a stacked orientation. The connection structure also includes underbump metallization overlying at least a portion of the contact pad and lining the stepped via, and a conductive connection element coupled to the underbump metallization. The conductive connection element fills the lined recess.

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Номер записи: 4
15-03-2012 дата публикации

Semiconductor chip with redundant thru-silicon-vias

Номер: US20120061821A1
Автор: Bryan Black, Gamal Refai-Ahmed, Joe Siegel, Michael Z. Su, Seth Prejean
Принадлежит: Advanced Micro Devices Inc, ATI TECHNOLOGIES ULC

A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip. The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.

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Номер записи: 5
26-04-2012 дата публикации

Conductive feature for semiconductor substrate and method of manufacture

Номер: US20120098121A1
Автор: Hsien-Wei Chen, Ying-Ju Chen
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A conductive feature on a semiconductor component is disclosed. A first passivation layer is formed over a substrate. A bond pad is formed over the first passivation layer. A second passivation layer overlies the first passivation layer and the bond pad. The second passivation layer has a first opening overlying the bond pad and a plurality of second openings exposing a top surface of the first passivation layer. A buffer layer overlies the second passivation layer and fills the plurality of second openings. The buffer layer has a third opening overlapping the first opening and together exposes a portion the bond pad. The combined first opening and third opening has sidewalls. An under bump metallurgy (UBM) layer overlies the sidewalls of the combined first opening and third opening, and contacts the exposed portion of the bond pad. A conductive feature overlies the UBM layer.

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Номер записи: 6
24-05-2012 дата публикации

Package carrier

Номер: US20120125669A1
Автор: Chau-Jie Zhan, Jing-Yao Chang, Tao-Chih Chang, Tsung-Fu Tsai
Принадлежит: Industrial Technology Research Institute ITRI

A package carrier including a substrate, at least an under bump metallurgic (UBM) layer and at least a conductive bump is provided. The substrate has a conductive structure and at least a pad connected with the conductive structure. A region of the pad connected with the conductive structure is a signal source region. The UBM layer is disposed on the pad and includes a first conductive pattern and a second conductive pattern. A side wall of the second conductive pattern is directly connected to a side wall of the first conductive pattern, and the second conductive pattern is disposed close to the signal source region. The conductivity of the second conductive pattern is smaller than the conductivity of the first conductive pattern. The conductive bump is disposed on the UBM layer.

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Номер записи: 7
24-05-2012 дата публикации

Method of manufacturing semiconductor device

Номер: US20120129335A1
Автор: Hiroyuki Yoda, Masamitsu Ikumo, Yoshito Akutagawa
Принадлежит: Fujitsu Semiconductor Ltd

A method of manufacturing a semiconductor device including the following steps: forming an insulator layer over a first conductor over a semiconductor substrate; forming a barrier layer to coat the surface of the insulator layer; forming a second conductor over the barrier layer; melting the second conductor in an atmosphere containing either hydrogen or carboxylic acid in a condition that the surface of the insulator layer over the first conductor is coated with the barrier layer; and removing the barrier layer partially from the surface of the insulator layer with the second conductor as a mask.

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Номер записи: 8
31-05-2012 дата публикации

Mechanisms for resistivity measurement of bump structures

Номер: US20120133379A1
Автор: Feynmann CHU, Jeff Wang, Mill-Jer Wang, Pi-Huang Lee, You-Hua Chou
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The embodiments described above provide mechanisms for bump resistivity measurement. By using designated bumps on one or more corners of dies, the resistivity of bumps may be measured without damaging devices and without a customized probing card. In addition, bump resistivity may be collected across the entire wafer. The collected resistivity data may be used to monitor the stability and/or health of processes used to form bumps and their underlying layers.

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Номер записи: 9
14-06-2012 дата публикации

Semiconductor Device and Method of Forming an Inductor Within Interconnect Layer Vertically Separated from Semiconductor Die

Номер: US20120146181A1
Автор: Jianmin Fang, KANG Chen, Yaojian Lin
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has an adhesive layer formed over a carrier. A semiconductor die has bumps formed over an active surface of the semiconductor die. The semiconductor die is mounted to the carrier with the bumps partially disposed in the adhesive layer to form a gap between the semiconductor die and adhesive layer. An encapsulant is deposited over the semiconductor die and within the gap between the semiconductor die and adhesive layer. The carrier and adhesive layer are removed to expose the bumps from the encapsulant. An insulating layer is formed over the encapsulant. A conductive layer is formed over the insulating layer in a wound configuration to exhibit inductive properties and electrically connected to the bumps. The conductive layer is partially disposed within a footprint of the semiconductor die. The conductive layer has a separation from the semiconductor die as determined by the gap and insulating layer.

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Номер записи: 10
28-06-2012 дата публикации

Chip scale surface mounted semiconductor device package and process of manufacture

Номер: US20120161307A1
Автор: Tao Feng
Принадлежит: ALPHA AND OMEGA SEMICONDUCTOR INC

A semiconductor device package die and method of manufacture are disclosed. The device package die may comprise a device substrate having one or more front electrodes located on a front surface of the device substrate and electrically connected to one or more corresponding device regions formed within the device substrate proximate the front surface. A back conductive layer is formed on a back surface of the device substrate. The back conductive layer is electrically connected to a device region formed within the device substrate proximate a back surface of the device substrate. One or more conductive extensions are formed on one or more corresponding sidewalls of the device substrate in electrical contact with the back conductive layer, and extend to a portion of the front surface of the device substrate. A support substrate is bonded to the back surface of the device substrate.

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Номер записи: 11
26-07-2012 дата публикации

Structures for improving current carrying capability of interconnects and methods of fabricating the same

Номер: US20120187558A1
Автор: Charles L. Arvin, Harry D. Cox, Krystyna W. Semkow, Raschid J. Bezama, Timothy D. Sullivan, Timothy H. Daubenspeck
Принадлежит: International Business Machines Corp

Interconnect structures and methods of fabricating the same are provided. The interconnect structures provide highly reliable copper interconnect structures for improving current carrying capabilities (e.g., current spreading). The structure includes an under bump metallurgy formed in a trench. The under bump metallurgy includes at least: an adhesion layer; a plated barrier layer; and a plated conductive metal layer provided between the adhesion layer and the plated barrier layer. The structure further includes a solder bump formed on the under bump metallurgy.

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Номер записи: 12
16-08-2012 дата публикации

Semiconductor Device and Method of Forming Narrow Interconnect Sites on Substrate with Elongated Mask Openings

Номер: US20120208326A9
Автор: Rajendra D. Pendse
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A plurality of conductive traces is formed over a surface of the substrate with interconnect sites. A masking layer is formed over the surface of the substrate. The masking layer has a plurality of parallel elongated openings each exposing at least two of the conductive traces and permitting a flow of bump material along a length of the plurality of conductive traces within the plurality of elongated openings while preventing the flow of bump material past a boundary of the plurality of elongated openings. One of the conductive traces passes beneath at least two of the elongated openings. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

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Номер записи: 13
23-08-2012 дата публикации

Electroconductive bonding material, method for bonding conductor, and method for manufacturing semiconductor device

Номер: US20120211549A1
Автор: Kuniko Ishikawa, Masayuki Kitajima, Takashi Kubota, Takatoyo Yamakami
Принадлежит: Fujitsu Ltd

An electro-conductive bonding material includes: metal components of a high-melting-point metal particle that have a first melting point or higher; a middle-melting-point metal particle that has a second melting point which is first temperature or higher, and second temperature or lower, the second temperature is lower than the first melting point and higher than the first temperature; and a low-melting-point metal particle that has a third melting point or lower, the third melting point is lower than the first temperature.

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Номер записи: 14
30-08-2012 дата публикации

Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump

Номер: US20120217629A1
Автор: Daesik Choi, Joonyoung Choi, SungWon Cho
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a carrier. A semiconductor wafer including a semiconductor die is mounted to the carrier with an active surface of the semiconductor die facing away from the carrier. A plurality of bumps is formed over the active surface of the semiconductor die. An opening is formed in a periphery of the semiconductor die. An encapsulant is deposited over the carrier and semiconductor die, in the opening, and around the plurality of bumps such that an exposed portion of the plurality of bumps is devoid of encapsulant. A conductive via is formed through the encapsulant, within the opening, and extends to the carrier. A conductive layer is formed over the encapsulant and electrically connects to the conductive via and the exposed portion of the plurality of bumps. The carrier is removed to expose an end of the conductive via.

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Номер записи: 15
30-08-2012 дата публикации

Semiconductor Device and Method of Forming Bond Wires Between Semiconductor Die Contact Pads and Conductive TOV in Peripheral Area Around Semiconductor Die

Номер: US20120217643A1
Автор: Byung Tai Do, Dioscoro A. Merilo, Reza A. Pagaila
Принадлежит: Stats Chippac Pte Ltd

A semiconductor wafer has a plurality of semiconductor die with contact pads. An organic material is deposited in a peripheral region around the semiconductor die. A portion of the organic material is removed to form a plurality of vias. A conductive material is deposited in the vias to form conductive TOV. The conductive TOV can be recessed with respect to a surface of the semiconductor die. Bond wires are formed between the contact pads and conductive TOV. The bond wires can be bridged in multiple sections across the semiconductor die between the conductive TOV and contact pads. An insulating layer is formed over the bond wires and semiconductor die. The semiconductor wafer is singulated through the conductive TOV or organic material between the conductive TOV to separate the semiconductor die. A plurality of semiconductor die can be stacked and electrically connected through the bond wires and conductive TOV.

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Номер записи: 16
30-08-2012 дата публикации

Semiconductor apparatus, method for manufacturing the same and electric device

Номер: US20120217660A1
Автор: Keishiro Okamoto, Motoaki Tani
Принадлежит: Fujitsu Ltd

A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.

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Номер записи: 17
11-10-2012 дата публикации

Solder ball contact susceptible to lower stress

Номер: US20120256313A1
Автор: Luc Guerin, Mario J. Interrante, Michael J. Shapiro, Thuy Tran-Quinn, Van T. Truong
Принадлежит: International Business Machines Corp

A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball.

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Номер записи: 18
25-10-2012 дата публикации

Light-emitting diode die packages and illumination apparatuses using same

Номер: US20120267675A1
Автор: Yu-Nung Shen
Принадлежит: Evergrand Holdings Ltd

The present invention relates to an LED die package, which has a light-emitting diode die having a sapphire layer, a first doped layer doped with a p- or n-type dopant, and a second doped layer doped with a different dopant from that doped in the first doped layer. A surface of the sapphire layer opposite to the surface on which the first doped layer is disposed is formed with generally inverted-pyramidal-shaped recesses and overlaid with a phosphor powder layer. Each of the first and the second doped layers has an electrode-forming surface formed with an electrode, on which an insulation layer is disposed and formed with exposure holes for exposing the electrodes. The exposure holes are each filled with an electrically conductive linker.

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Номер записи: 19
01-11-2012 дата публикации

Semiconductor Device and Method of Embedding TSV Semiconductor Die Within Substrate for Vertical Interconnect in POP

Номер: US20120273959A1
Автор: Dongsam Park, Yongduk Lee
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a substrate with a first conductive layer over a surface of the substrate and a plurality of cavities exposing the first conductive layer. A first semiconductor die having conductive TSV is mounted into the cavities of the substrate. A first insulating layer is formed over the substrate and first semiconductor die and extends into the cavities to embed the first semiconductor die within the substrate. A portion of the first insulating layer is removed to expose the conductive TSV. A second conductive layer is formed over the conductive TSV. A portion of the first conductive layer is removed to form electrically common or electrically isolated conductive segments of the first conductive layer. A second insulating layer is formed over the substrate and conductive segments of the first conductive layer. A second semiconductor die is mounted over the substrate electrically connected to the second conductive layer.

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Номер записи: 20
15-11-2012 дата публикации

Electronic device and manufacturing thereof

Номер: US20120286293A1
Автор: Josef Hoeglauer, Ralf Otremba
Принадлежит: INFINEON TECHNOLOGIES AG

An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane.

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Номер записи: 21
22-11-2012 дата публикации

Methods and structures for forming integrated semiconductor structures

Номер: US20120292748A1
Автор: Mariam Sadaka, Radu Ionut
Принадлежит: Soitec SA

The invention provides methods and structures for fabricating a semiconductor structure and particularly for forming a semiconductor structure with improved planarity for achieving a bonded semiconductor structure comprising a processed semiconductor structure and a number of bonded semiconductor layers. Methods for forming semiconductor structures include forming a dielectric layer over a non-planar surface of a processed semiconductor structure, planarizing a surface of the dielectric layer on a side thereof opposite the processed semiconductor structure, and attaching a semiconductor structure to the planarized surface of the dielectric layer. Semiconductor structures include a dielectric layer overlaying a non-planar surface of a processed semiconductor structure, and a masking layer overlaying the dielectric layer on a side thereof opposite the processed semiconductor structure. The masking layer includes a plurality of mask openings over conductive regions of the non-planar surface of the processed semiconductor structure.

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Номер записи: 22
07-02-2013 дата публикации

Integrated Inductor

Номер: US20130032923A1
Автор: Chen-Shien Chen, Ching-Wen Hsiao, Mirng-Ji Lii, Tsung-Ding Wang, Yen-Liang Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A system and method for providing an integrated inductor with a high Quality factor (Q) is provided. An embodiment comprises a magnetic core that is in a center of a conductive spiral. The magnetic core increases the inductance of the integrated inductor to allow the inductor to be used in applications such as a RF choke. The magnetic core may be formed in the same manner and time as an underbump metallization.

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Номер записи: 23
21-03-2013 дата публикации

Paste and method for connecting electronic component to substrate

Номер: US20130068373A1
Автор: Albert Heilmann, Jens Nachreiner, Michael Schäfer, Wolfgang Schmitt
Принадлежит: Heraeus Materials Technology GmbH and Co KG

A paste may be used to connect at least one electronic component to at least one substrate through contact regions, wherein at least one of the contact regions contains a non-noble metal. The paste contains (a) metal particles, (b) at least one activator that bears at least two carboxylic acid units in the molecule, and (c) a dispersion medium. A method for connecting at least one electronic component to at least one substrate through the contact regions includes steps of providing a substrate having a first contact region and an electronic component having a second contact region; providing the above paste; generating a structure, wherein the first contact region of the substrate contacts the second contact region of the electronic component through the paste; and sintering the structure while producing a module including at least the substrate and the electronic component connected to each other through the sintered paste.

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Номер записи: 24
28-03-2013 дата публикации

Semiconductor Device and Method of Forming Stacked Vias Within Interconnect Structure for FO-WLCSP

Номер: US20130075924A1
Автор: Gu Yu, KANG Chen, Rui Huang, Yaojian Lin
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over the encapsulant and semiconductor die. First vias are formed through the first insulating layer to expose contact pads of the semiconductor die. A first conductive layer is formed over the first insulating layer and into the first vias to electrically connect to the contact pads of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. Second vias are formed through the second insulating layer by laser direct ablation and aligned or offset with the first vias to expose the first conductive layer. A second conductive layer is formed over the second insulating layer and into the second vias. Conductive vias can be formed through the encapsulant.

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Номер записи: 25
28-03-2013 дата публикации

Multi-chip semiconductor package and method of fabricating the same

Номер: US20130078763A1
Автор: Jong-Gi Lee, Kwang-Yong Lee, Min-Ho Lee
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A first semiconductor chip having a first projection electrode formed on an upper surface thereof is prepared. A second semiconductor chip having a second projection electrode is mounted on the first semiconductor chip to expose the first projection electrode. An insulating film is formed between the first projection electrode and the second projection electrode. A groove is formed in the insulating film. An interconnection configured to fill an inside of the groove and connected to the first projection electrode and the second projection electrode is formed.

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Номер записи: 26
25-04-2013 дата публикации

Semiconductor Device and Method of Forming Interposer Frame Electrically Connected to Embedded Semiconductor Die

Номер: US20130099378A1
Автор: HanGil Shin, HeeJo Chi, NamJu Cho
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die.

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Номер записи: 27
02-05-2013 дата публикации

Method to form solder deposits and non-melting bump structures on substrates

Номер: US20130105329A1
Автор: Catherine Schoenenberger, Ingo Ewert, Jürgen Kress, Kai-Jens Matejat, Sven Lamprecht
Принадлежит: Atotech Deutschland GmbH and Co KG

Described is a method of forming a metal or metal alloy layer onto a substrate comprising the following steps i) provide a substrate including a permanent resin layer on top of at least one contact area and a temporary resin layer on top of the permanent resin layer, ii) contact the entire substrate area including the at least one contact area with a solution suitable to provide a conductive layer on the substrate surface and i) electroplate a metal or metal alloy layer onto the conductive layer.

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Номер записи: 28
02-05-2013 дата публикации

Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect

Номер: US20130105989A1
Автор: Reza A. Pagaila, Seng Guan Chow, Seung Uk Yoon
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

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Номер записи: 29
02-05-2013 дата публикации

Methods of manufacturing stress buffer structures in a mounting structure of a semiconductor device

Номер: US20130109169A1
Автор: Shin-puu Jeng, Tzu-Wei Chiu, Tzu-Yu Wang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A mounting structure for a semiconductor device is formed to include a stepwise stress buffer layer under a stepwise UBM structure.

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Номер записи: 30
30-05-2013 дата публикации

Wafer Level Semiconductor Package

Номер: US20130134596A1
Автор: Chonghua ZHONG, Edward Law, Kevin (Kunzhong) HU
Принадлежит: Broadcom Corp

There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process.

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Номер записи: 31
30-05-2013 дата публикации

METHOD OF MANUFACTURING GaN-BASED SEMICONDUCTOR DEVICE

Номер: US20130137220A1
Автор: Hideki Matsubara, Kuniaki Ishihara
Принадлежит: Sumitomo Electric Industries Ltd

A method of manufacturing a GaN-based semiconductor device includes the steps of: preparing a composite substrate including: a support substrate having a thermal expansion coefficient at a ratio of not less than 0.8 and not more than 1.2 relative to a thermal expansion coefficient of GaN; and a GaN layer bonded to the support substrate, using an ion implantation separation method; growing at least one GaN-based semiconductor layer on the GaN layer of the composite substrate; and removing the support substrate of the composite substrate by dissolving the support substrate. Thus, the method of manufacturing a GaN-based semiconductor device is provided by which GaN-based semiconductor devices having excellent characteristics can be manufactured at a high yield ratio.

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Номер записи: 32
06-06-2013 дата публикации

Electronic Device and a Method for Fabricating an Electronic Device

Номер: US20130140685A1
Автор: Alexander Heinrich, Kok Chai Goh, Konrad Roesl, Michael Juerss, Oliver EICHINGER, Tobias Schmidt
Принадлежит: INFINEON TECHNOLOGIES AG

The electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.

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Номер записи: 33
06-06-2013 дата публикации

Semiconductor device and method for production of semiconductor device

Номер: US20130140699A1
Автор: Atsushi Okuyama
Принадлежит: Sony Corp

A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto.

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Номер записи: 34
04-07-2013 дата публикации

Bump structure and electronic packaging solder joint structure and fabricating method thereof

Номер: US20130168851A1
Автор: Chau-Jie Zhan, Tao-Chih Chang, Yu-Min Lin
Принадлежит: Industrial Technology Research Institute ITRI

A bump structure includes a substrate, a pad, an electrode and a protruding electrode. The pad is disposed on the substrate. The electrode is formed by a first metal material and disposed on the pad. The protruding electrode is formed by a second metal material and disposed on the electrode, wherein a cross-sectional area of the protruding electrode is less than a cross-sectional area of the electrode.

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Номер записи: 35
29-08-2013 дата публикации

Electronic device and electronic component

Номер: US20130221523A1
Автор: Ryogo Honda, Tomokazu HONDA, Yoshihiro Kobayashi
Принадлежит: Yaskawa Electric Corp

The disclosure discloses an electronic device including an electronic component including a chip main body, a plurality of electrodes, a passivation which includes openings, and UBMs which are respectively formed to be smaller than an opening area of the opening, a substrate including a plurality of substrate electrodes, and a plurality of spherical solder bumps configured to electrically connect the plurality of electrodes with the plurality of substrate electrodes. The solder bump is bonded to the electrode at a bonding portion located on a bottom surface of the spherical shape. Each of the plurality of electrodes includes an exposed portion generated because a bonding area between the solder bump and the electrode via the UBM is smaller than the opening area. The solder bump is separated apart from the passivation via an upper space located above the exposed portion of the electrode.

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Номер записи: 36
19-09-2013 дата публикации

Contact Test Structure and Method

Номер: US20130240883A1
Автор: Hsien-Wei Chen, Jie Chen, Tsung-Yuan Yu, Ying-Ju Chen
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A system and method for testing electrical connections is provided. In an embodiment one or more floating pads may be manufactured in electrical connection with an underbump metallization structure. A test may then be performed to measure the electrical characteristics of the underbump metallization structure through the floating pad in order to test for defects. Alternatively, a conductive connection may be formed on the underbump metallization and the test may be performed on the conductive connection and the underbump metallization together.

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Номер записи: 37
26-09-2013 дата публикации

Semiconductor device and manufacturing method thereof

Номер: US20130249084A1
Автор: Naoki Fujimoto, Tatsuya Usami, Tomoyuki Nakamura
Принадлежит: Renesas Electronics Corp

A semiconductor device includes an interlayer insulating film containing Si, O, C, and H, an under-bump metal film disposed over the interlayer insulating film and containing Ni, and a bump electrode disposed over the under-bump metal film. In the interlayer insulating film, a ratio of a peak height of Si—CH 3 near a wave number 1270 cm −1 to a peak height of Si—O near a wave number 1030 cm −1 obtained by Fourier-transform infrared spectroscopy (FTIR) is 0.15 or greater and 0.27 or less. A ratio of a peak height of Si—CH 2 —Si near a wave number 1360 cm −1 to the peak height of Si—CH 3 near the wave number 1270 cm −1 is 0.031 or greater.

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Номер записи: 38
26-09-2013 дата публикации

Magnet Assisted Alignment Method for Wafer Bonding and Wafer Level Chip Scale Packaging

Номер: US20130252375A1
Автор: Ge Yi, Shaoping Li, YunJun Tang, Zongrong Liu
Принадлежит: Individual

A high-precision alignment method with high throughput is proposed, which can be used for wafer-to-wafer, chip-to-wafer or chip-to-chip bonding. The scheme implements pairing patterned magnets predetermined designed and made using wafer level process on two components (wafer or chip). The magnetization in patterned magnet can be set at predetermined configuration before bonding starts. When, the two components are bought to close proximity after a coarse alignment, the magnetic force will bring the magnet pairs together and aligned the patterned magnet on one component with its mirrored or complimentary patterned magnets on the other component to minimize the overall the magnetic energy of the pairing magnet. A few patterned magnet structures and materials, with their unique merits are proposed as examples for magnet pair for the self-alignment purpose. This method enables solid contact at the bonding interface via patterned magnets under the magnetic force, which avoid the wafer drafting due to the formation of the liquid phases.

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Номер записи: 39
26-09-2013 дата публикации

Method of manufacturing a semiconductor integrated circuit device

Номер: US20130252416A1
Автор: Hiroshi Yanagita, Takao Kumihashi, Takashi Takeuchi, Yasuhiro Takeda, Yasushi Matsuda
Принадлежит: Renesas Electronics Corp

The TSV technology has been popular as one of stacking technologies of a plurality of semiconductor chips. It has however been revealed by the present inventors that when TSV is formed using a so-called first via process, via middle process, front-via via last process, or the like, there is a possibility of defects such as gate breakdown occurring due to electrostatic breakdown in the subsequent process. In order to overcome the above problem, the present invention provides a method of manufacturing a semiconductor integrated circuit device, in which a through via electrode is formed by forming a hole in a semiconductor substrate, forming an insulating member in the hole, and burying a conductive member in the resulting hole while covering a portion of the hole except for the bottom portion with the insulating member.

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Номер записи: 40
03-10-2013 дата публикации

Via plugs

Номер: US20130256841A1
Автор: Helmut Hagleitner, Van Mieczkowski, William T. Pulz
Принадлежит: Cree Inc

The present disclosure relates to providing via plugs in vias of a semiconductor material. The via plugs may be formed of a polymer, such as a polyimide, that can withstand subsequent soldering and operating temperatures. The via plugs effectively fill the vias to prevent the vias from being filled substantially with solder during a subsequent soldering processes.

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Номер записи: 41
28-11-2013 дата публикации

Semiconductor device having wafer-level chip size package

Номер: US20130313703A1
Автор: Kiyonori Watanabe
Принадлежит: Oki Semiconductor Co Ltd

A semiconductor device including a semiconductor substrate with circuit elements and electrode pads formed on one surface. The surface is covered by a dielectric layer with openings above the electrode pads. A metal layer is included on the dielectric layer and patterned to form a conductive pattern with traces leading to the electrode pads. A protective layer is included as having openings exposing part of the conductive pattern. Each opening is covered by an electrode such as a solder bump, which is electrically connected through the conductive pattern to one of the electrode pads. The thickness of the protective layer, which may function as a package of the semiconductor device, is thus reduced. The protective layer may be formed from a photosensitive material, simplifying the formation of the openings for the electrodes.

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Номер записи: 42
28-11-2013 дата публикации

Semiconductor integrated circuit device

Номер: US20130313708A1
Автор: Akira Yajima, Hiromi Shigihara, Hiroshi Tsukamoto
Принадлежит: Renesas Electronics Corp

In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate).

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Номер записи: 43
05-12-2013 дата публикации

Stacked Integrated Chips and Methods of Fabrication Thereof

Номер: US20130320531A1
Автор: Jao Sheng Huang, Ming-Fa Chen
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Structure and methods of forming stacked semiconductor chips are described. In one embodiment, a method of forming a semiconductor chip includes forming an opening for a through substrate via from a top surface of a first substrate. The sidewalls of the opening are lined with an insulating liner and the opened filled with a conductive fill material. The first substrate is etched from an opposite bottom surface to form a protrusion, the protrusion being covered with the insulating liner. A resist layer is deposited around the protrusion to expose a portion of the insulating liner. The exposed insulating liner is etched to form a sidewall spacer along the protrusion.

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Номер записи: 44
26-12-2013 дата публикации

Simultaneous wafer bonding and interconnect joining

Номер: US20130341804A1
Автор: Belgacem Haba, Craig Mitchell, Ilyas Mohammed, Piyush Savalia, Vage Oganesian
Принадлежит: Tessera LLC

Disclosed are a microelectronic assembly of two elements and a method of forming same. A microelectronic element includes a major surface, and a dielectric layer and at least one bond pad exposed at the major surface. The microelectronic element may contain a plurality of active circuit elements. A first metal layer is deposited overlying the at least one bond pad and the dielectric layer. A second element having a second metal layer deposited thereon is provided, and the first metal layer is joined with the second metal layer. The assembly may be severed along dicing lanes into individual units each including a chip.

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Номер записи: 45
23-01-2014 дата публикации

Semiconductor package and method of fabricating the same

Номер: US20140021608A1
Автор: Keun-ho CHOI
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor package includes a first semiconductor chip including a first chip pad located on an upper surface thereof, a second semiconductor chip offset-stacked on the upper surface of the first semiconductor chip and including a second chip pad located on an upper surface thereof, a chip coupling ball located on a first board pad of the first semiconductor chip, a chip coupling bump located on a second board pad of the second semiconductor chip, and a chip connection wire connecting the chip coupling ball and the chip coupling bump. The chip connection wire has a chip connection curve part with a reverse curve shape.

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Номер записи: 46
20-02-2014 дата публикации

Semiconductor device including through via structures and redistribution structures

Номер: US20140048952A1
Автор: Byung-lyul Park, Gil-heyun Choi, Ho-Jin Lee, Kyu-Ha Lee, Pil-Kyu Kang, Tae-Yeong Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Semiconductor device including through via structure and redistribution structures is provided. The semiconductor device may include internal circuits on a first side of a substrate, a through via structure vertically penetrating the substrate to be electrically connected to one of the internal circuits, a redistribution structure on a second side of the substrate and electrically connected to the through via structure, and an insulating layer between the second side of the substrate and the redistribution structure. The redistribution structure may include a redistribution barrier layer and a redistribution metal layer, and the redistribution barrier layer may extend on a bottom surface of the redistribution metal layer and may partially surround a side of the redistribution metal layer.

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Номер записи: 47
27-02-2014 дата публикации

Methods and Apparatus of Packaging Semiconductor Devices

Номер: US20140057431A1
Автор: Chia-Wei Tu, Fu-Ying Huang, Hsien-Wei Chen, Ming-Song Sheu, Tsung-Fu Tsai, Yian-Liang Kuo
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface.

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Номер записи: 48
06-03-2014 дата публикации

Method of manufacturing semiconductor device

Номер: US20140065767A1
Автор: Michiaki Sugiyama, Nobuhiro Kinoshita
Принадлежит: Renesas Electronics Corp

In a semiconductor device formed by mounting a chip laminate including a semiconductor chip having a small diameter and a semiconductor chip having a large diameter over the top surface of a substrate, an excessive stress is prevented from being added to a joint of the two semiconductor chips. By mounting a first semiconductor chip having a large diameter over a support substrate and thereafter mounting a second semiconductor chip having a small diameter over the first semiconductor chip, it is possible to: suppress the inclination and unsteadiness of the second semiconductor chip mounted over the first semiconductor chip; and hence inhibit an excessive stress from being added to a joint of the first semiconductor chip and the second semiconductor chip.

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Номер записи: 49
13-03-2014 дата публикации

Methods for manufacturing a chip arrangement, methods for manufacturing a chip package, a chip package and chip arrangements

Номер: US20140070376A1
Автор: Alexander Heinrich, Gabriel Maier, Gunther Mackh, Hannes Eder, Katharina Umminger, Markus Menath, Reinhard Hess
Принадлежит: INFINEON TECHNOLOGIES AG

A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.

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Номер записи: 50
20-03-2014 дата публикации

Solder interconnect with non-wettable sidewall pillars and methods of manufacture

Номер: US20140077367A1
Автор: Brian R. Sundlof, Charles L. Arvin, Christopher D. Muzzy, David L. Questad, Jeffrey P. Gambino, Raschid J. Bezama, Timothy D. Sullivan, Timothy H. Daubenspeck, Wolfgang Sauter
Принадлежит: International Business Machines Corp

A solder interconnect structure is provided with non-wettable sidewalls and methods of manufacturing the same. The method includes forming a nickel or nickel alloy pillar on an underlying surface. The method further includes modifying the sidewall of the nickel or nickel alloy pillar to prevent solder wetting on the sidewall.

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Номер записи: 51
01-01-2015 дата публикации

Power semiconductor module

Номер: US20150001726A1
Автор: Baik-Woo Lee, Seong-Woon Booh
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A power semiconductor module includes a first power device on a substrate, a first electrode on an upper surface of the first power device, a first nickel plating layer on the first electrode, and a copper wire connected to the first nickel plating layer.

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Номер записи: 52
05-01-2017 дата публикации

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Номер: US20170005048A1
Автор: Shigihara Hiromi, TSUKAMOTO Hiroshi, YAJIMA Akira
Принадлежит:

In a method of manufacturing a semiconductor device, a semiconductor chip has first and second pads, a passivation film formed such that respective parts of the first and second pads are exposed, a first surface-metal-layer provided on the part of the first pad and a part of the passivation film, and a second surface-metal-layer provided on the part of the second pad and another part of the passivation film. Respective wires are electrically connected to the first and second surface-metal-layers. The semiconductor chip and the respective wires are then sealed with a resin. 1. A method of manufacturing a semiconductor device , comprising: a main surface on which a first pad and a second pad arranged next to the first pad are provided,', 'a passivation film formed on the main surface of the semiconductor chip such that a first part of the first pad and a second part of the second pad are exposed from the passivation film,', 'a first surface-metal layer provided over the first part of the first pad and a first part of the passivation film, and', 'a second surface-metal layer provided over the second part of the second pad and a second part of the passivation film,, '(a) providing a semiconductor chip havingwherein, in plan view, a width of the first surface-metal layer is less than a width of the first pad,wherein, in plan view, a width of the second surface-metal layer is less than a width of the second pad,wherein the width of each of the first surface-metal layer, the second surface-metal layer, the first pad and the second pad is a respective dimension along the main surface of the semiconductor chip and, in plan view, in a direction along which the first pad and the second pad are arranged,wherein the passivation film has a third part located between the first pad and the second pad in cross-section view, andwherein, in cross-section view, a surface of the third part is located closer to the main surface of the semiconductor chip than a surface of the first part ...

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Номер записи: 53
13-01-2022 дата публикации

ITERATIVE FORMATION OF DAMASCENE INTERCONNECTS

Номер: US20220013478A1
Автор: Kilcoyne Sean P., Liguori Michael V., Miller Eric R., Rondon Michael J.
Принадлежит:

Disclosed herein are interconnects and methods of fabricating a plurality of interconnects. The method includes depositing a conformal layer of a plating base in each of a plurality of vias, and depositing a photoresist on two portions of a surface of the plating base outside and above the plurality of vias. The method also includes depositing a plating metal over the plating base in each of the plurality of vias, the depositing resulting in each of the plurality of vias being completely filled or incompletely filled, performing a chemical mechanical planarization (CMP), and performing metrology to determine if any of the plurality of vias is incompletely filled following the depositing the plating metal. A second iteration of the depositing the plating metal over the plating base is performed in each of the plurality of vias based on determining that at least one of the plurality of vias is incompletely filled. 1. A method of fabricating a plurality of interconnects , the method comprising:depositing a conformal layer of a plating base in each of a plurality of vias;depositing a photoresist on two portions of a surface of the plating base outside and above the plurality of vias;depositing a plating metal over the plating base in each of the plurality of vias, wherein the depositing the plating metal results in each of the plurality of vias being completely filled or incompletely filled with the plating metal;performing a chemical mechanical planarization (CMP);performing metrology to determine if any of the plurality of vias is incompletely filled following the depositing the plating metal; andperforming a second iteration of the depositing the plating metal over the plating base in each of the plurality of vias based on determining that at least one of the plurality of vias is incompletely filled.2. The method according to claim 1 , further comprising forming a plurality of intermediate structures corresponding to the plurality of interconnects by etching a ...

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Номер записи: 54
04-01-2018 дата публикации

Repackaged integrated circuit assembly method

Номер: US20180005910A1
Автор: Spory Erick Merle
Принадлежит: Global Circuit Innovations Inc.

A method is provided. The method includes one or more of extracting a die from an original packaged integrated circuit, modifying the extracted die, reconditioning the modified extracted die, placing the reconditioned die into a cavity of a hermetic package base, bonding a plurality of bond wires between reconditioned die pads of the reconditioned die to leads of the hermetic package base or downbonds to create an assembled hermetic package base, and sealing a hermetic package lid to the assembled hermetic package base to create a new packaged integrated circuit. Modifying the extracted die includes removing the one or more ball bonds on the one or more die pads. Reconditioning the modified extracted die includes adding a sequence of metallic layers to bare die pads of the modified extracted die. The extracted die is a fully functional semiconductor die with one or more ball bonds on one or more die pads of the extracted die. 1. A method , comprising:extracting a die from an original packaged integrated circuit, wherein the extracted die is a fully functional semiconductor die with one or more ball bonds on one or more die pads of the extracted die;modifying the extracted die, comprising removing the one or more ball bonds on the one or more die pads; 'adding a sequence of metallic layers to bare die pads of the modified extracted die;', 'reconditioning the modified extracted die, comprisingplacing the reconditioned die into a cavity of a hermetic package base;bonding a plurality of bond wires between reconditioned die pads of the reconditioned die to leads of the hermetic package base or downbonds to create an assembled hermetic package base; andsealing a hermetic package lid to the assembled hermetic package base to create a new packaged integrated circuit.2. The method as recited in claim 1 , wherein bare die pads of the modified extracted die comprises all metallic and chemical residue claim 1 , all ball bonds claim 1 , and all bond wires removed from all die ...

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Номер записи: 55
04-01-2018 дата публикации

Semiconductor backmetal (bm) and over pad metallization (opm) structures and related methods

Номер: US20180005951A1
Автор: Shinzo Ishibe, Takashi Noma, Yusheng Lin
Принадлежит: Semiconductor Components Industries LLC

A method of forming semiconductor devices includes providing a wafer having a first side and second side, electrically conductive pads at the second side, and an electrically insulative layer at the second side with openings to the pads. The first side of the wafer is background to a desired thickness and an electrically conductive layer is deposited thereon. Nickel layers are simultaneously electrolessly deposited over the electrically conductive layer and over the pads, and diffusion barrier layers are then simultaneously deposited over the nickel layers. Another method of forming semiconductor devices includes depositing backmetal (BM) layers on the electrically conductive layer including a titanium layer, a nickel layer, and/or a silver layer. The BM layers are covered with a protective coating and a nickel layer is electrolessly deposited over the pads. A diffusion barrier layer is deposited over the nickel layer over the pads, and the protective coating is removed.

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Номер записи: 56
07-01-2021 дата публикации

Semiconductor device

Номер: US20210005565A1
Автор: Ho-Jin Lee, Jeong-Gi Jin, Jin-ho An, Jin-Ho Chun, Kwang-jin Moon, Seong-min Son
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern. The semiconductor device may have a high reliability.

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Номер записи: 57
04-01-2018 дата публикации

Semiconductor Device and Method of Forming Build-Up Interconnect Structures Over a Temporary Substrate

Номер: US20180006008A1
Автор: Chen Kang, Lin Yaojian
Принадлежит: STATS ChipPAC Pte. Ltd.

A semiconductor device has a first build-up interconnect structure formed over a substrate. The first build-up interconnect structure includes an insulating layer and conductive layer formed over the insulating layer. A vertical interconnect structure and semiconductor die are disposed over the first build-up interconnect structure. The semiconductor die, first build-up interconnect structure, and substrate are disposed over a carrier. An encapsulant is deposited over the semiconductor die, first build-up interconnect structure, and substrate. A second build-up interconnect structure is formed over the encapsulant. The second build-up interconnect structure electrically connects to the first build-up interconnect structure through the vertical interconnect structure. The substrate provides structural support and prevents warpage during formation of the first and second build-up interconnect structures. The substrate is removed after forming the second build-up interconnect structure. A portion of the insulating layer is removed exposing the conductive layer for electrical interconnect with subsequently stacked semiconductor devices. 1. A method of making a semiconductor device , comprising:providing a substrate;forming a first interconnect structure over the substrate;disposing a first semiconductor die over the first interconnect structure;disposing the substrate over a carrier with the first semiconductor die oriented away from the carrier;depositing an encapsulant over the carrier, substrate, and first semiconductor die;forming a second interconnect structure over the encapsulant and semiconductor die; andremoving the substrate to expose the first interconnect structure after forming the second interconnect structure.2. The method of claim 1 , further including forming a conductive column over the first interconnect structure.3. The method of claim 2 , wherein the conductive column extends from the first interconnect structure to the second interconnect structure ...

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Номер записи: 58
02-01-2020 дата публикации

Molded Semiconductor Package

Номер: US20200006267A1
Автор: Aileen Manantan Soriano, Fong Mei Lum, Hock Heng Chong, Mei Chin Ng, MUHAMMAD Muhammat Sanusi, Soon Lock Goh, Swee Kah Lee
Принадлежит: INFINEON TECHNOLOGIES AG

A molded semiconductor package includes a mold compound having opposing first and second main surfaces and an edge extending between the first and second main surfaces. A semiconductor die is embedded in the mold compound. A plurality of metal pads embedded in the mold compound are electrically connected to the semiconductor die. The metal pads have a bottom face which is uncovered by the mold compound at the second main surface of the mold compound. The metal pads disposed around a periphery of the molded package have a side face which is uncovered by the mold compound at the edge of the mold compound. The faces of the metal pads uncovered by the mold compound are plated. The side face of each metal pad disposed around the periphery of the molded package is recessed inward from the edge of the mold compound. A corresponding manufacturing method is also described.

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Номер записи: 59
02-01-2020 дата публикации

BOND PADS FOR LOW TEMPERATURE HYBRID BONDING

Номер: US20200006280A1
Автор: Bhagavat Milind S., Shah Priyal
Принадлежит:

Various chip stacks and methods and structures of interconnecting the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip that has a first glass layer and plural first groups of plural conductor pads in the first glass layer. Each of the plural first groups of conductor pads is configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a plurality interconnects that connect the first semiconductor chip to the second semiconductor chip. The first glass layer is configured to bond to a second glass layer of the second semiconductor chip. 1. An apparatus , comprising:a first semiconductor chip having a first glass layer and plural first groups of plural conductor pads in the first glass layer, each of the plural first groups of conductor pads including a main conductor pad and one or more dummy pads adjacent the main conductor pad and being configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a plurality of interconnects that connect the first semiconductor chip to the second semiconductor chip; andthe first glass layer being configured to bond to a second glass layer of the second semiconductor chip.2. The apparatus of claim 1 , wherein each of the first groups comprises a main conductor pad and plural dummy pads circumferentially arranged around the main conductor pad.3. The apparatus of claim 1 , comprising the second semiconductor chip mounted on the first semiconductor chip and electrically connected thereto by the plurality of interconnects.4. An apparatus claim 1 , comprising:a first semiconductor chip having a first glass layer and plural first conductor pads in the first glass layer, each of the plural first conductor pads including a base layer and a bonding layer on the base layer, the base layer having a greater ...

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Номер записи: 60
03-01-2019 дата публикации

Heat Spreading Device and Method

Номер: US20190006263A1
Автор: Chen-Hua Yu, Ming-Fa Chen, Tsung-Yu Chen, Wensen Hung
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

In an embodiment, a device includes: an integrated circuit die having a first side and a second side opposite the first side; a die stack on the first side of the integrated circuit die; a dummy semiconductor feature on the first side of the integrated circuit die, the dummy semiconductor feature laterally surrounding the die stack, the dummy semiconductor feature electrically isolated from the die stack and the integrated circuit die; a first adhesive disposed between the die stack and the dummy semiconductor feature; and a plurality of conductive connectors on the second side of the integrated circuit die.

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Номер записи: 61
03-01-2019 дата публикации

Method for Producing Electronic Device With Multi-Layer Contact

Номер: US20190006311A1
Автор: EICHINGER Oliver, Goh Kok Chai, HEINRICH Alexander, Juerss Michael, Roesl Konrad, SCHMIDT TOBIAS
Принадлежит:

A method for producing an electric device with a multi-layer contact is disclosed. In an embodiment, a method includes providing a carrier, the carrier having a metallic layer disposed on its surface, providing a semiconductor substrate, forming a layer stack on the semiconductor substrate and attaching the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer. 1. A method for fabricating an electronic device , the method comprising:providing a carrier, the carrier having a metallic layer disposed on its surface, wherein the metallic layer comprises Ni or NiNiP;providing a semiconductor substrate; directly depositing an electrical contact layer on the semiconductor substrate, the electrical contact layer being a single elemental Al layer;', 'directly depositing a functional layer on the electrical contact layer, the functional layer comprising Ti or an alloy containing Ti;', 'directly depositing an adhesion layer on the functional layer, the adhesion layer comprising Ni or NiV;', 'directly depositing a solder layer on the adhesion layer, the solder layer being a single element Sn layer or a noble metal free alloy layer containing Sn; and', 'directly depositing a protective layer on the solder layer, the protection layer being an Ag layer; and, 'forming a layer stack on the semiconductor substrate bybonding the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer, the intermetallic phase comprising a binary alloy of Ni/Sn.2. The method according to claim 1 , wherein the electrical contact layer has a thickness in a range from 100 nm to 1 μm.3.The method according to claim 2 , wherein the functional layer has a thickness in a range from 50 nm to 200 nm.4382. The method according to claim claim 2 , wherein the solder layer has a thickness in ...

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Номер записи: 62
03-01-2019 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20190006324A1
Автор: MIGITA Tatsuo, OGISO Koji
Принадлежит:

A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a first metal layer located on the first semiconductor substrate, a second metal layer located on the second semiconductor substrate, a third metal layer, a first alloy layer, and a second alloy layer. The third metal layer extends between the first metal layer and the second metal layer. The first alloy layer comprises components of the first and third metal layers, and is provided between the first metal layer and the third metal layer. The second alloy layer comprises components of the second and third metal layers, and is provided between the second metal layer and the third metal layer. At least one of the first metal the second metal layers projects into the third metal layer at a circumferential edge portion thereof. 1. A semiconductor device comprising:a first semiconductor substrate;a second semiconductor substrate facing the first semiconductor substrate;a first pad electrode disposed on a surface of the first semiconductor substrate facing the second semiconductor substrate;a second pad electrode disposed on a surface of the second semiconductor substrate facing the first semiconductor substrate;a first insulating layer disposed on an edge portion of the first pad electrode and the first semiconductor substrate;a second insulating layer disposed on an edge portion of the second pad electrode and the second semiconductor substrate;a first metal layer disposed over the first pad electrode and facing the second semiconductor substrate;a second metal layer disposed over the second pad electrode and facing the first semiconductor substrate;a third metal layer disposed between the first metal layer and the second metal layer;a first alloy layer disposed between the first metal layer and the third metal layer and comprising a component of the first metal layer and a component of the third metal layer; anda second alloy layer disposed between the second metal layer ...

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Номер записи: 63
08-01-2015 дата публикации

Semiconductor chip and stacked type semiconductor package having the same

Номер: US20150008588A1
Автор: Byoung Do LEE, Jae Hyun SON, Jong Hoon Kim, Kuk Jin Chun, Woong Kyu CHOI
Принадлежит: SK hynix Inc

The disclosure relates to a semiconductor chip and a stacked type semiconductor package having the same. The semiconductor chip includes: a semiconductor chip body having a first surface formed with a plurality of bonding pads and a second surface which is opposite to the first surface, a plurality of first and second through electrodes that pass through the semiconductor chip body and one ends thereof are electrically connected to the bonding pads, an insulating layer formed over the second surface of the semiconductor chip body such that the other ends of the first and second through electrodes are not covered by the insulating layer, and a first heat spreading layer formed over the insulating layer.

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Номер записи: 64
27-01-2022 дата публикации

Semiconductor module

Номер: US20220028761A1
Автор: Takafumi Yamada, Toru Yamada
Принадлежит: Fuji Electric Co Ltd

A semiconductor module includes a semiconductor device having a gate runner extending in a first direction at an upper surface of the semiconductor device, and a metal wiring plate having a first bonding portion with a bonding surface to which the upper surface of the semiconductor device is bonded via a first bonding material. The first bonding portion has a plurality of first protrusions at the bonding surface. Each first protrusion protrudes toward the semiconductor device, and is provided in a position away from the gate runner by a first distance in a plan view of the semiconductor module.

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Номер записи: 65
27-01-2022 дата публикации

Unified semiconductor devices having processor and heterogeneous memories and methods for forming the same

Номер: US20220028829A1
Автор: Jun Liu, Weihua Cheng
Принадлежит: Yangtze Memory Technologies Co Ltd

Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes NAND memory cells and a first bonding layer including first bonding contacts. The semiconductor device also includes a second semiconductor structure including DRAM cells and a second bonding layer including second bonding contacts. The semiconductor device also includes a third semiconductor structure including a processor, SRAM cells, and a third bonding layer including third bonding contacts. The semiconductor device further includes a first bonding interface between the first and third bonding layers, and a second bonding interface between the second and third bonding layers. The first bonding contacts are in contact with a first set of the third bonding contacts at the first bonding interface. The second bonding contacts are in contact with a second set of the third bonding contacts at the second bonding interface. The first and second bonding interfaces are in a same plane.

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Номер записи: 66
11-01-2018 дата публикации

Semiconductor Device and Method of Forming PoP Semiconductor Device with RDL Over Top Package

Номер: US20180012857A1
Автор: Yaojian Lin
Принадлежит: Stats Chippac Pte Ltd

A PoP semiconductor device has a top semiconductor package disposed over a bottom semiconductor package. The top semiconductor package has a substrate and a first semiconductor die disposed over the substrate. First and second encapsulants are deposited over the first semiconductor die and substrate. A first build-up interconnect structure is formed over the substrate after depositing the second encapsulant. The top package is disposed over the bottom package. The bottom package has a second semiconductor die and modular interconnect units disposed around the second semiconductor die. A second build-up interconnect structure is formed over the second semiconductor die and modular interconnect unit. The modular interconnect units include a plurality of conductive vias and a plurality of contact pads electrically connected to the conductive vias. The I/O pattern of the build-up interconnect structure on the top semiconductor package is designed to coincide with the I/O pattern of the modular interconnect units.

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Номер записи: 67
11-01-2018 дата публикации

Package assembly

Номер: US20180012860A1
Автор: Chien-Hsiun Lee, Chung-Shi Liu, Hung-Jen Lin, Ming-Da Cheng, Tsung-Ding Wang, Wen-Hsiung LU
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

In some embodiments, the present disclosure relates to a package assembly having a bump on a first substrate. A molding compound is on the first substrate and contacts sidewalls of the bump. A no-flow underfill layer is on a conductive region of a second substrate. The no-flow underfill layer and the conductive region contact the bump. A mask layer is arranged on the second substrate and laterally surrounds the no-flow underfill layer. The no-flow underfill layer contacts the substrate between the conductive region and the mask layer.

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Номер записи: 68
10-01-2019 дата публикации

CONDUCTIVE BALL AND ELECTRONIC DEVICE

Номер: US20190013285A1
Автор: MURAYAMA Kei
Принадлежит:

A conductive ball includes a copper ball, a nickel layer formed with being patterned on an outer surface of the copper ball, and a tin-based solder covering each outer surface of the copper ball and the nickel layer. 1. A conductive ball comprising:a copper ball;a nickel layer formed with being patterned on an outer surface of the copper ball; anda tin-based solder covering each outer surface of the copper ball and the nickel layer.2. The conductive ball according to claim 1 , wherein an area of the copper ball exposed from the nickel layer is adjusted so that copper in the copper ball is diffused into the tin-based solder and a copper concentration in the tin-based solder becomes 0.7 wt % to 3 wt % when reflow heating the tin-based solder.3. The conductive ball according to claim 1 , wherein the nickel layer has at least one opening region and the outer surface of the copper ball is exposed from the opening region of the nickel layer.4. An electronic device comprising:a lower electronic member having a first connection pad;an upper electronic member arranged above the lower electronic member and having a second connection pad; anda conductive ball configured to interconnect the first connection pad of the lower electronic member and the second connection pad of the upper electronic member,wherein the conductive ball comprises:a copper ball,a nickel layer formed with being patterned on an outer surface of the copper ball, anda tin-based solder covering each outer surface of the copper ball and the nickel layer.5. The electronic device according to claim 4 ,{'sub': 6', '5, 'b': '14', 'wherein a (Cu, Ni)Snlayer is formed between the nickel layer and the tin-based solder () of the conductive ball, and'}{'sub': 3', '6', '5, 'wherein a CuSn layer and a (Cu, Ni)Snlayer are formed in order from below between the copper ball exposed from the nickel layer of the conductive ball and the tin-based solder.'}6. The electronic device according to claim 4 , wherein each surface of ...

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Номер записи: 69
10-01-2019 дата публикации

Tall and fine pitch interconnects

Номер: US20190013287A1
Автор: Cyprian Emeka Uzoh, Rajesh Katkar
Принадлежит: Invensas LLC

Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.

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Номер записи: 70
14-01-2021 дата публикации

3D Integrated Circuit and Methods of Forming the Same

Номер: US20210013098A1
Автор: Chao Lan-Lin, Chen Xiaomeng, Chu Yen-Chang, Hsiao Cheng-Tai, Kuang Hsun-Chung, Liu Ping-Yin, Tsai Chia-Shiung, Tu Yeur-Luen
Принадлежит:

An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer. 1. A semiconductor device comprising:a first contact extending away from a planar surface of a substrate, the first contact having straight sidewalls;a first dielectric layer surrounding a first portion of the first contact, the first dielectric layer being separated from the planar surface;a second dielectric layer surrounding a second portion of the first contact, wherein the second dielectric layer has a larger porosity than the first dielectric layer and wherein the first dielectric layer is located between the second dielectric layer and the substrate; anda dielectric barrier layer surrounding a third portion of the first contact, the dielectric barrier layer sharing a planar surface with the first contact.2. The semiconductor device of claim 1 , wherein the straight sidewalls are perpendicular to a major surface of the substrate.3. The semiconductor device of claim 1 , wherein the straight sidewalls are tilted with respect to a major surface of the substrate.4. The semiconductor device of claim 1 , wherein the first dielectric layer has a porosity of less than about 5%.5. The semiconductor device of claim 4 , wherein the first dielectric layer comprises un-doped silicate glass (USG).6. The semiconductor device of claim 1 , wherein the second dielectric layer ...

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Номер записи: 71
09-01-2020 дата публикации

Semiconductor Device and Method

Номер: US20200014169A1
Автор: An-Jhih Su, Chen-Hua Yu, Chia-Nan Yuan, Der-Chyang Yeh, Ming Shih Yeh, Shih-Guo Shen, Yu-Hung Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

In an embodiment, a device includes: a first reflective structure including first doped layers of a semiconductive material, alternating ones of the first doped layers being doped with a p-type dopant; a second reflective structure including second doped layers of the semiconductive material, alternating ones of the second doped layers being doped with a n-type dopant; an emitting semiconductor region disposed between the first reflective structure and the second reflective structure; a contact pad on the second reflective structure, a work function of the contact pad being less than a work function of the second reflective structure; a bonding layer on the contact pad, a work function of the bonding layer being greater than the work function of the second reflective structure; and a conductive connector on the bonding layer.

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Номер записи: 72
03-02-2022 дата публикации

Semiconductor device with recessed pad layer and method for fabricating the same

Номер: US20220037287A1
Автор: Shing-Yih Shih
Принадлежит: Nanya Technology Corp

The present application discloses a semiconductor device with a recessed pad layer and a method for fabricating the semiconductor device. The semiconductor device includes a first die, a second die positioned on the first die, a pad layer positioned in the first die, a filler layer including an upper portion and a recessed portion, and a barrier layer positioned between the second die and the upper portion of the filler layer, between the first die and the upper portion of the filler layer, and between the pad layer and the recessed portion of the filler layer. The upper portion of the filler layer is positioned along the second die and the first die, and the recessed portion of the filler layer is extending from the upper portion and positioned in the pad layer.

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Номер записи: 73
18-01-2018 дата публикации

Method for processing an electronic component and an electronic component

Номер: US20180019218A1
Автор: Jens Peter Konrath, Jochen Hilsenbeck
Принадлежит: INFINEON TECHNOLOGIES AG

According to various embodiments an electronic component includes: at least one electrically conductive contact region; a contact pad including a self-segregating composition disposed over the at least one electrically conductive contact region; a segregation suppression structure disposed between the contact pad and the at least one electrically conductive contact region, wherein the segregation suppression structure includes more nucleation inducing topography features than the at least one electrically conductive contact region for perturbing a chemical segregation of the self-segregating composition by crystallographic interfaces of the contact pad defined by the nucleation inducing topography features.

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Номер записи: 74
18-01-2018 дата публикации

SURFACE FINISHES FOR INTERCONNECTION PADS IN MICROELECTRONIC STRUCTURES

Номер: US20180019219A1
Автор: Lee Kyu Oh, PIETAMBARAM Srinivas V.
Принадлежит: Intel Corporation

A surface finish may be formed in a microelectronic structure, wherein the surface finish may include a multilayer interlayer structure. Thus, needed characteristics, such as compliance and electro-migration resistance, of the interlayer structure may be satisfied by different material layers, rather attempting to achieve these characteristics with a single layer. In one embodiment, the multilayer interlayer structure may comprises a two-layer structure, wherein a first layer is formed proximate a solder interconnect and comprises a material which forms a ductile joint with the solder interconnect, and a second layer comprising a material having strong electro-migration resistance formed between the first layer and an interconnection pad. In a further embodiment, third layer may be formed adjacent the interconnection pad comprising a material which forms a ductile joint with the interconnection pad. 125.-. (canceled)26. A microelectronic structure , comprising:an interconnection pad;a surface finish on the interconnection pad, wherein the surface finish comprises a multilayer interlayer structure including at least one ductile layer and at least one electro-migration resistant layer; anda solder interconnect on the surface finish.27. The microelectronic structure of claim 26 , wherein the at least one ductile layer comprises a nickel material having phosphorus content of between about 2% and 10% by weight.28. The microelectronic structure of claim 26 , wherein the at least one electro-migration resistant layer comprises a nickel material having phosphorus content of between about 11% and 20% by weight.29. The microelectronic structure of claim 26 , wherein the at least one electro-migration resistant layer comprises a high atomic weight metal.30. The microelectronic structure of claim 29 , wherein the high atomic weight metal is selected from the group consisting of nickel claim 29 , cobalt claim 29 , and iron.31. The microelectronic structure of claim 26 , wherein ...

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Номер записи: 75
16-01-2020 дата публикации

CONDUCTIVE BUMP AND ELECTROLESS Pt PLATING BATH

Номер: US20200020660A1
Автор: Sho Kanzaki, Takuma MAEKAWA, Toshiaki Shibata, Yoshito II, Yukinori Oda
Принадлежит: C Uyemura and Co Ltd

The present invention provides a bump that can prevent diffusion of a metal used as a base conductive layer of the bump into a surface of an Au layer or an Ag layer. A conductive bump of the present invention is a conductive bump formed on a substrate. The conductive bump comprises, at least in order from the substrate: a base conductive layer; a Pd layer; a Pt layer; and an Au layer or an Ag layer having directly contact with the Pd layer, wherein a diameter of the conductive bump is 20 μm or less.

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Номер записи: 76
26-01-2017 дата публикации

Pre-package and methods of manufacturing semiconductor package and electronic device using the same

Номер: US20170025302A1
Автор: Gun-ho Chang, Tae-Je Cho, Un-Byoung Kang
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Methods of fabricating semiconductor packages are provided. One of the methods includes forming a protection layer including metal on a first surface of a substrate to cover a semiconductor device disposed on the first surface of the substrate, attaching a support substrate to the protection layer by using an adhesive member, processing a second surface of the substrate opposite to the protection layer to remove a part of the substrate, and detaching the support substrate from the substrate.

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Номер записи: 77
26-01-2017 дата публикации

Electronic Device with Multi-Layer Contact

Номер: US20170025375A1
Автор: Alexander Heinrich, Kok Chai Goh, Konrad Roesl, Michael Juerss, Oliver EICHINGER, Tobias Schmidt
Принадлежит: INFINEON TECHNOLOGIES AG

An electric device with a multi-layer contact is disclosed. In an embodiment, the electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.

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Номер записи: 78
28-01-2016 дата публикации

METHOD OF FORMING A MEMORY DEVICE

Номер: US20160027748A1
Автор: Brooks Joseph F., MOORE John
Принадлежит:

A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication. 1. A memory device structure comprising:circuitry formed over a substrate;at least one insulating portion formed over said circuitry, each of said at least insulating portions having a plurality of openings;a plurality of electrical connections formed in the respective openings of said insulating portions;at least one bond pad formed within at least one of said insulating portions; anda cap formed over said bond pad.2. The device of claim 1 , wherein said bond pad comprises copper.3. The device of claim 1 , wherein said cap comprises nickel having a thickness of about 4000 Angstroms.4. The device of claim 1 , wherein at least one of said plurality of electrical connections comprises a via filled with tungsten. This application is a divisional of U.S. patent application Ser. No. 14/534,668, filed Nov. 6, 2014, which is a divisional of U.S. patent application Ser. No. 13/253,512, filed Oct. 5, 2011, which is a continuation of U.S. patent application Ser. No. 12/853,100, filed Aug. 9, 2010, now U.S. Pat. No. 8,043,961, which is a divisional of U.S. patent application Ser. No. 12/219,836, filed Jul. 29, 2008, now U.S. Pat. No. 7,795,093, which is a divisional of U.S. patent application Ser. No. 11/399,358, filed Apr. 7, 2006, now U.S. Pat. No. 7,485,948, which is a divisional of U.S. patent application Ser. No. 10/902,569, filed Jul. 30, 2004, now U.S. Pat. No. 7,226,857. Each of the above listed applications are incorporated by reference in their entirety.The present invention relates to the field of semiconductor devices and, in particular, to the formation of bond pads for memory and other integrated circuit devices.A well known semiconductor memory component is random access memory (RAM). RAM permits ...

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Номер записи: 79
24-04-2014 дата публикации

Strong, heat stable junction

Номер: US20140110848A1
Автор: Patrick J. Taylor, Sudhir Trivedi, Wendy L. Sarney
Принадлежит: US Army Research Laboratory

Provided among other things is an electrical device comprising: a first component that is a semiconductor or an electrical conductor; a second component that is an electrical conductor; and a strong, heat stable junction there between including an intermetallic bond formed of: substantially (a) indium (In), tin (Sn) or a mixture thereof, and (b) substantially nickel (Ni). The junction can have an electrical contact resistance that is small compared to the resistance of the electrical device.

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Номер записи: 80
25-01-2018 дата публикации

Flip-chip, face-up and face-down centerbond memory wirebond assemblies

Номер: US20180025967A1
Автор: Belgacem Haba, Richard DeWitt Crisp, Wael Zohni
Принадлежит: Tessera LLC

A microelectronic assembly can include a substrate having first and second surfaces and an aperture extending therebetween, the substrate having terminals. The assembly can also include a first microelectronic element having a front surface facing the first surface of the substrate, a second microelectronic element having a front surface facing the first microelectronic element and projecting beyond an edge of the first microelectronic element, first and second leads electrically connecting contacts of the respective first and second microelectronic elements to the terminals, and third leads electrically interconnecting the contacts of the first and second microelectronic elements. The contacts of the first microelectronic element can be exposed at the front surface thereof adjacent the edge thereof. The contacts of the second microelectronic element can be disposed in a central region of the front surface thereof. The first, second, and third leads can have portions aligned with the aperture.

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Номер записи: 81
25-01-2018 дата публикации

Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP

Номер: US20180026023A1
Автор: KANG Chen, Seung Wook Yoon, Yaojian Lin
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the first insulating layer. An interconnect structure is formed through the encapsulant outside a footprint of the semiconductor die and electrically connected to the conductive layer. The first insulating layer includes an optically transparent or translucent material. The semiconductor die includes a sensor configured to receive an external stimulus passing through the first insulating layer. A second insulating layer is formed over the first surface of the semiconductor die. A conductive via is formed through the first insulating layer outside a footprint of the semiconductor die. A plurality of stacked semiconductor devices is electrically connected through the interconnect structure.

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Номер записи: 82
29-01-2015 дата публикации

Semiconductor Device and Method of Forming Overlapping Semiconductor Die with Coplanar Vertical Interconnect Structure

Номер: US20150028496A1
Автор: Henry D. Bathan, Jairus L. Pisigan, Zigmund R. Camacho
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device is made by forming first and second interconnect structures over a first semiconductor die. A third interconnect structure is formed in proximity to the first die. A second semiconductor die is mounted over the second and third interconnect structures. An encapsulant is deposited over the first and second die and first, second, and third interconnect structures. A backside of the second die is substantially coplanar with the first interconnect structure and a backside of the first semiconductor die is substantially coplanar with the third interconnect structure. The first interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the second die. The third interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the first die.

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Номер записи: 83
24-01-2019 дата публикации

SEMICONDUCTOR DEVICES, SEMICONDUCTOR PACKAGES, AND METHODS OF MANUFACTURING THE SEMICONDUCTOR DEVICES

Номер: US20190027450A1
Автор: CHOI Ju-Il, FUJISAKI Atsushi, LEE Ho-Jin, LIM Dong-Chan, MOON Kwang-Jin, Seo Ju-Bin
Принадлежит:

A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer. 1. A semiconductor device comprising:a conductive component on a substrate;a passivation layer on the substrate and including an opening therein, wherein the opening exposes at least a portion of the conductive component; and a lower conductive layer conformally extending on an inner sidewall of the opening and on a top surface of the passivation layer around the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked,', 'a first pad layer on the lower conductive layer, the first pad layer at least partially filling the opening, and', 'a second pad layer on the first pad layer, the second pad layer laterally extending beyond the first pad layer to contact a peripheral portion of the lower conductive layer located on the top surface of the passivation layer., 'a pad structure on the passivation layer and in the opening, the pad structure electrically connected to the conductive component, the pad structure comprising2. The semiconductor device of claim 1 , wherein the second pad layer is ...

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Номер записи: 84
24-01-2019 дата публикации

SEMICONDUCTOR DEVICES

Номер: US20190027453A1
Автор: Kim Yong Ho, LEE IN YOUNG, NOH BO IN, PARK SOO JEOUNG
Принадлежит:

A semiconductor device includes a substrate, a protection layer on the substrate that includes a trench that penetrates therethrough, a lower bump that includes a first part that fills at least a portion of the trench and a second part on the protection layer; and an upper bump on the lower bump. The protection layer includes a first part that surrounds the trench and a second part that surrounds the first part. A first height from an upper surface of the substrate to an upper surface of the first part of the protection layer is greater than a second height from the upper surface of the substrate to an upper surface of the second part of the protection layer. 1. A semiconductor device , comprising:a substrate;a protection layer on the substrate, the protection layer including a trench that penetrates therethrough;a lower bump that includes a first part that fills at least a portion of the trench and a second part on the protection layer, wherein an upper surface of the first art of the lower bump is curved downward toward the substrate; andan upper bump on the lower bump,wherein the protection layer includes a first part that surrounds the trench and a second part that surrounds the first part, anda first height from an upper surface of the substrate to an upper surface of the first part of the protection layer is greater than a second height from the upper surface of the substrate to an upper surface of the second part of the protection layer.2. The semiconductor device according to claim 1 , wherein the lower bump includes a recess claim 1 , andthe upper bump includes a first part in the recess and a second part on the first part.3. The semiconductor device according to claim 1 , wherein an upper surface of the first part of the lower bump includes a second point spaced apart by a first distance from a first point on a sidewall of the trench in a first direction parallel to the upper surface of the substrate and a third point spaced apart by a second distance from ...

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Номер записи: 85
24-01-2019 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20190027455A1
Автор: Makuta Kiichi, Suzuki Shinya
Принадлежит:

To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged. 1. A semiconductor device comprising:(a) a semiconductor substrate of substantially rectangular shape having a pair of long edges and a pair of short edges;(b) an internal circuit including a plurality of MISFETs formed over the semiconductor substrate;(c) a plurality of protection elements formed over the semiconductor substrate so as to protect the internal circuit against static electricity;(d) a first insulating film formed over the semiconductor substrate so as to cover the plurality of MISFETs and the plurality of protection elements; and(e) a plurality of bump electrodes formed over the first insulating film, the plurality of bump electrodes being arranged along a first long edge of the pair of long edges,wherein the plurality of bump electrodes are bump electrodes for receiving input signals from an external device,wherein the plurality of protection elements are electrically coupled between the respective plurality of bump electrodes and the internal circuit,wherein the plurality of bump electrodes include a first bump electrode and a second bump electrode,wherein the plurality of protection elements include a first protection element and a second protection element,wherein the first protection element electrically coupled to the first bump electrode is disposed at a position overlapped with the first bump electrode in a planar view when ...

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Номер записи: 86
24-01-2019 дата публикации

ELECTRONIC MODULE

Номер: US20190027676A1
Автор: YASUDA Junpei
Принадлежит:

An electronic module includes a substrate that includes a first main surface and a second main surface, at least one first electronic component that includes electrodes on a mounting surface thereof on the substrate and that includes a hollow portion, at least one second electronic component that includes electrodes on a mounting surface thereof on the substrate and that includes no hollow portion, and a sealing resin. The at least one first electronic component is mounted on the first main surface of the substrate and sealed with the sealing resin. The at least one second electronic component is mounted on the second main surface of the substrate and is not sealed with the sealing resin. 1. An electronic module comprising:a substrate that includes a first main surface and a second main surface;at least one first electronic component that includes electrodes provided on a mounting surface thereof on the substrate and that includes a hollow portion;at least one second electronic component that includes electrodes provided on a mounting surface thereof on the substrate and that includes no hollow portion; anda sealing resin; whereinthe at least one first electronic component is mounted on the first main surface of the substrate and sealed with the sealing resin; andthe at least one second electronic component has a narrowest pitch between the electrodes that are provided on the mounting surface and is mounted on the second main surface of the substrate, and at least a portion of the at least one second electronic component that is joined to the substrate is not sealed with the sealing resin.2. The electronic module according to claim 1 , wherein the sealing resin includes a filler.3. The electronic module according to claim 1 , wherein an outer electrode that is defined by a metal piece is mounted on the second main surface of the substrate.4. The electronic module according to claim 1 , wherein the at least one first electronic component is an elastic wave device.5. ...

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Номер записи: 87
28-01-2021 дата публикации

POLYMER RESIN AND COMPRESSION MOLD CHIP SCALE PACKAGE

Номер: US20210028133A1
Автор: Carney Francis J., Chew Chee Hiong, LIN Yusheng, WANG Soon Wei
Принадлежит: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

A method for fabricating a chip scale package, comprising: providing a wafer; applying a polymer resin on at least part of a first surface of the wafer and to one or more sides of the wafer; and applying a compression mold on at least part of a second surface of the wafer and to one or more sides of the wafer, said first and second surfaces opposing each other. 1. A chip scale package , comprising:a semiconductor die having a top surface, a bottom surface, and side surfaces;a metallization layer coupled on the top surface of the semiconductor die; anda compression mold coupled on the bottom surface of the die, on the side surfaces of the die, and on a portion of the top surface of the die,wherein a portion of the compression mold of the die forms a strip along at least part of the perimeter of the top surface; andwherein a portion of the compression mold covering the portion of the top surface of the die is over-mold.2. The chip scale package of claim 1 , wherein the strip has an average width between 40 and 60 micrometers claim 1 , inclusive.3. The chip scale package of claim 1 , wherein the strip occupies between 20 percent and 40 percent claim 1 , inclusive claim 1 , of a total area of the top surface excluding metallization.4. The chip scale package of claim 1 , wherein the compression mold is made of a material selected from the group consisting of: polyamides claim 1 , polyimides claim 1 , polyamide-imides claim 1 , polyphenylene sulfide (PPS) claim 1 , polyether ether ketone (PEEK) claim 1 , and polyester fiberglass resin.5. The chip scale package of claim 1 , wherein the top and bottom surfaces oppose each other.6. A chip scale package claim 1 , comprising:a semiconductor die having a first largest planar surface, a second largest planar surface, and side surfaces across a thickness between the first largest planar surface and the second largest planar surface;a metallization layer coupled on the first largest planar surface of the semiconductor die; anda ...

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Номер записи: 88
28-01-2021 дата публикации

BONDED ASSEMBLY CONTAINING OXIDATION BARRIERS AND/OR ADHESION ENHANCERS AND METHODS OF FORMING THE SAME

Номер: US20210028149A1
Автор: Alsmeier Johann, Makala Raghuveer S.
Принадлежит:

A method of forming a bonded assembly includes providing a first semiconductor die containing a first substrate, first semiconductor devices, and first bonding pads that are electrically connected to a respective node of the first semiconductor devices, forming a first oxidation barrier layer on physically exposed surfaces of the first bonding pads, providing a second semiconductor die containing a second substrate, second semiconductor devices, and second bonding pads that are electrically connected to a respective node of the second semiconductor devices, and bonding the second bonding pads to the first bonding pads with at least the first oxidation barrier layer located between the respective first and second bonding pads. 1. A method of forming a bonded assembly , comprising:providing a first semiconductor die comprising a first substrate, first semiconductor devices, and first bonding pads that are electrically connected to a respective node of the first semiconductor devices;forming a first oxidation barrier layer on physically exposed surfaces of the first bonding pads;providing a second semiconductor die comprising a second substrate, second semiconductor devices, and second bonding pads that are electrically connected to a respective node of the second semiconductor devices; andbonding the second bonding pads to the first bonding pads with at least the first oxidation barrier layer located between the respective first and second bonding pads.2. The method of claim 1 , wherein:the first bonding pads are located within a first bonding dielectric layer;the second bonding pads are located within a second bonding dielectric layer; andthe oxidation barrier layer is selectively formed on physically exposed surfaces of the first bonding pads without forming the first oxidation barrier layer on physically exposed surfaces of the first bonding dielectric layer.3. The method of claim 2 , wherein:the first bonding dielectric layer and the second bonding dielectric ...

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Номер записи: 89
02-02-2017 дата публикации

THREE-DIMENSIONAL INTEGRATED CIRCUIT LAMINATE, AND INTERLAYER FILLER FOR THREE-DIMENSIONAL INTEGRATED CIRCUIT LAMINATE

Номер: US20170033050A1
Автор: IKEMOTO Makoto, Kawase Yasuhiro, Kiritani Hideki
Принадлежит: MITSUBISHI CHEMICAL CORPORATION

To provide a three-dimensional integrated circuit laminate filled in with an interlayer filler composition having both high thermal conductivity and low linear expansion property. 124-. (canceled)25: A three-dimensional integrated circuit laminate , which comprises a semiconductor substrate laminate having at least two semiconductor substrates each having a semiconductor device layer formed thereon laminated , and has an interlayer filler layer containing a resin (A) and an inorganic filler (B) and having a thermal conductivity of at least 0.8 W/(m·K) between the semiconductor substrates , wherein the epoxy resin (A) comprises a plurality of epoxy resins differing in the structural units.26: The three-dimensional integrated circuit laminate according to claim 25 , wherein the coefficient of linear thermal expansion of the first interlayer filler layer is at least 3 ppm/K and at most 70 ppm/K.27: The three-dimensional integrated circuit laminate according to wherein the dielectric constant of the inorganic filler (B) contained in the first interlayer filler layer is at most 6.28: The three-dimensional integrated circuit laminate according to claim 25 , wherein the specific surface area of the inorganic filler (B) contained in the first interlayer filler layer between the semiconductor substrates is at least 1 m/g and at most 60 m/g.29: The three-dimensional integrated circuit laminate according to claim 25 , wherein the semiconductor substrates are silicon substrates.30: The three-dimensional integrated circuit laminate according to claim 25 , wherein the inorganic filler (B) is boron nitride.31: The three-dimensional integrated circuit laminate according to claim 25 , which has solder connection terminals for electric signal connection between the semiconductor substrates each having a semiconductor device layer formed thereon in the first interlayer filler layer.32: The three-dimensional integrated circuit laminate according to claim 25 , wherein the organic ...

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Номер записи: 90
02-02-2017 дата публикации

Semiconductor Devices and Methods of Forming Thereof

Номер: US20170033066A1
Автор: Alexander Heinrich, Evelyn Napetschnig, Thomas Fischer, Ulrike Fastner
Принадлежит: INFINEON TECHNOLOGIES AG

In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced.

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Номер записи: 91
02-02-2017 дата публикации

BONDING STRUCTURE FOR SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

Номер: US20170033075A1
Автор: CHEN Kuan-Neng, KUO Shu-Chiao, SHU Min-Fong, TSENG Yi-Hsiu
Принадлежит:

A method of manufacturing a bonding structure includes (a) providing a substrate, wherein the substrate includes a top surface and at least one bonding pad disposed adjacent to the top surface of the substrate, at least one bonding pad having a sloped surface with a first slope; (b) providing a semiconductor element, wherein the semiconductor element includes at least one pillar, and at least one pillar has a sidewall with a second slope, wherein the absolute value of the first slope is smaller than the absolute value of the second slope; and (c) bonding at least one pillar to a portion of the sloped surface of corresponding ones of the at least one bonding pad. 1. A method of manufacturing a bonding structure , comprising:(a) providing a substrate, wherein the substrate includes a top surface and at least one bonding pad disposed adjacent to the top surface of the substrate, at least one bonding pad having a sloped surface with a first slope;(b) providing a semiconductor element, wherein the semiconductor element includes at least one pillar, and at least one pillar has a sidewall with a second slope, wherein the absolute value of the first slope is smaller than the absolute value of the second slope; and(c) bonding at least one pillar to a portion of the sloped surface of corresponding ones of the at least one bonding pad.2. The method of claim 1 , wherein in (a) claim 1 , a space defined by the sloped surface of at least one bonding pad has a maximum width and a minimum width claim 1 , and in (b) claim 1 , a width of a corresponding one of the at least one pillar is greater than the minimum width of the space and less than the maximum width of the space.3. The method of claim 1 , wherein in (c) claim 1 , a gap is formed between the sidewall of the at least one pillar and the sloped surface of a corresponding bonding pad.4. The method of claim 1 , wherein in (b) claim 1 , at least one pillar further has a top surface and an edge portion claim 1 , wherein the edge ...

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Номер записи: 92
04-02-2016 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20160035683A1
Автор: KIDO Kazumasa, MOMOSE Fumihiko, Nishimura Yoshitaka, Saito Takashi
Принадлежит: FUJI ELECTRIC CO., LTD.

A highly reliable semiconductor device capable of heavy current conduction and high temperature operation has a module structure in which a semiconductor chip and a circuit pattern are electrically connected via a wire. A front surface metal film is formed on a front surface electrode of the chip, and the wire is bonded to the front surface metal film by wire bonding. The chip has a front surface electrode on the front surface of an Si substrate or an SiC substrate, and has a rear surface substrate on the rear surface thereof. The front surface metal film is a Ni film or a Ni alloy film of having a thickness ranging from 3 μm to 7 μm. The wire is an Al wire having an increased recrystallizing temperature and improved strength due to controlling the crystal grain sizes before wire bonding to a range of 1 μm to 20 μm. 1. A semiconductor device , comprising:a conducting unit that is disposed on a surface of a semiconductor element;a metal film having a thickness ranging from 3 μm to 7 μm that is disposed on a surface of the conducting unit; anda wire having a wire diameter ranging from 500 μm or larger that is bonded to the metal film by wire-bonding using ultrasonic vibration.2. The semiconductor device according to claim 1 , wherein the semiconductor element includes:a semiconductor substrate selected from a silicon substrate and a silicon carbide substrate; andthe conducting unit having, as a major component, aluminum and being disposed on the surface of the semiconductor substrate.3. The semiconductor device according to claim 1 , wherein the metal film has a main component that is nickel.4. The semiconductor device according to claim 3 , wherein the metal film is a nickel alloy film having a main component that is nickel claim 3 , and containing at least one of phosphorus and boron.5. The semiconductor device according to claim 2 , wherein the metal film has a main component that is nickel.6. The semiconductor device according to claim 5 , wherein the metal film ...

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Номер записи: 93
01-02-2018 дата публикации

Molded Semiconductor Package Having an Optical Inspection Feature

Номер: US20180033752A1
Автор: Chong Hock Heng, Goh Soon Lock, Lee Swee Kah, Lum Fong Mei, Muhammat Sanusi Muhammad, Ng Mei Chin, Soriano Aileen Manantan
Принадлежит:

A molded semiconductor package includes a mold compound having opposing first and second main surfaces and an edge extending between the first and second main surfaces. A semiconductor die is embedded in the mold compound. A plurality of metal pads embedded in the mold compound are electrically connected to the semiconductor die. The metal pads have a bottom face which is uncovered by the mold compound at the second main surface of the mold compound. The metal pads disposed around a periphery of the molded package have a side face which is uncovered by the mold compound at the edge of the mold compound. The faces of the metal pads uncovered by the mold compound are plated. The side face of each metal pad disposed around the periphery of the molded package is recessed inward from the edge of the mold compound. A corresponding manufacturing method is also described. 1. A molded semiconductor package , comprising:a mold compound having a first main surface, a second main surface opposite the main surface, and an edge extending between the first and the second main surfaces;a semiconductor die embedded in the mold compound; anda plurality of metal pads embedded in the mold compound and electrically connected to the semiconductor die,wherein the metal pads have a bottom face which is uncovered by the mold compound at the second main surface of the mold compound,wherein the metal pads disposed around a periphery of the molded package have a side face which is uncovered by the mold compound at the edge of the mold compound,wherein the faces of the metal pads uncovered by the mold compound are plated,wherein the side face of each metal pad disposed around the periphery of the molded package is recessed inward from the edge of the mold compound.2. The molded semiconductor package of claim 1 , wherein the faces of the metal pads uncovered by the mold compound are plated with a layer of nickel-phosphorus or nickel-boron alloy and a layer of gold.3. The molded semiconductor ...

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Номер записи: 94
31-01-2019 дата публикации

3D Integrated Circuit and Methods of Forming the Same

Номер: US20190035681A1
Автор: Chao Lan-Lin, Chen Xiaomeng, Chu Yen-Chang, Hsiao Cheng-Tai, Kuang Hsun-Chung, Liu Ping-Yin, Tsai Chia-Shiung, Tu Yeur-Luen
Принадлежит:

An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer. 1. A method of manufacturing a semiconductor device , the method comprising:pre-bonding a first dielectric barrier layer and a second dielectric barrier layer at room temperature for a time of less than about one minute, wherein the first dielectric barrier layer is adjacent to a first high porosity dielectric layer and the second dielectric barrier layer is adjacent to a second high porosity dielectric layer, wherein the first high porosity dielectric layer is adjacent to a first low porosity dielectric layer and the second high porosity dielectric layer is adjacent to a second low porosity dielectric layer, and wherein a first contact extends through the first low porosity dielectric layer, the first high porosity dielectric layer, and the first dielectric barrier layer to make contact with a second contact, the second contact extending through the second dielectric barrier layer, the second high porosity dielectric layer, and the second low porosity dielectric layer; andannealing the first dielectric barrier layer and the second dielectric barrier layer at a temperature of between about 300° C. and about 400° C.2. The method of claim 1 , further comprising curing the first dielectric barrier layer and the second dielectric barrier layer.3. The method of claim 1 ...

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Номер записи: 95
31-01-2019 дата публикации

Semiconductor device and method of forming a curved image sensor

Номер: US20190035718A1
Автор: Eric Woolsey, Francis J. Carney, Michael J. Seddon
Принадлежит: Semiconductor Components Industries LLC

A semiconductor device has a semiconductor die containing a base material having a first surface and a second surface with an image sensor area. A masking layer with varying width openings is disposed over the first surface of the base material. The openings in the masking layer are larger in a center region of the semiconductor die and smaller toward edges of the semiconductor die. A portion of the first surface of the base material is removed by plasma etching to form a first curved surface. A metal layer is formed over the first curved surface of the base material. The semiconductor die is positioned over a substrate with the first curved surface oriented toward the substrate. Pressure and temperature is applied to assert movement of the base material to change orientation of the second surface with the image sensor area into a second curved surface.

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Номер записи: 96
31-01-2019 дата публикации

SEMICONDUCTOR PACKAGE

Номер: US20190035738A1
Автор: Lin Jing-Cheng, Lu Szu Wei, SHIH YING CHING, Tsai Po-Hao
Принадлежит:

The present disclosure provides a manufacturing method of a semiconductor packaging, including forming a redistribution layer (RDL) on a carrier, defining an active portion and a dummy portion of the RDL, and placing a semiconductor die over the dummy portion of the RDL. The present disclosure also provides a manufacturing method of a package-on-package (PoP) semiconductor structure, including forming a first redistribution layer (RDL) on a polymer-based layer of a carrier, defining an active portion and a dummy portion of the first RDL, placing a semiconductor die over the dummy portion of the first RDL, a back side of the semiconductor die facing the first RDL, forming a second RDL over a front side of the semiconductor die, the front side having at least one contact pad, and attaching a semiconductor package at the back side of the semiconductor die. 1. A semiconductor structure , comprising:a first redistribution layer (RDL) having a plurality of pads;a semiconductor die over the first RDL, at least one contact pad being positioned on a front side of the semiconductor die;a through package via (TPV) electrically connecting the front side and the first RDL; anda semiconductor device over a back side of the semiconductor die, the back side being opposite to the front side.2. The semiconductor structure of claim 1 , wherein the plurality of pads of the first RDL further comprises a dummy portion electrically isolated from any component of the semiconductor structure.3. The semiconductor structure of claim 1 , wherein the plurality of pads of the first RDL further comprises an active portion electrically coupled to the through package via.4. The semiconductor structure of claim 1 , further comprising a conductive plug at the back side of the semiconductor die.5. The semiconductor structure of claim 4 , further comprising a first carrier surrounding the conductive plug.6. The semiconductor structure of claim 4 , further comprising a second carrier between the ...

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Номер записи: 97
30-01-2020 дата публикации

Integrated circuit device structures and double-sided fabrication techniques

Номер: US20200035560A1
Автор: Bruce Block, Doug Ingerly, Kevin O'Brien, Kimin Jun, Patrick Morrow, Rishabh Mehandru, Szyua S. LIAO, Valluri R. Rao
Принадлежит: Intel Corp

Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.

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Номер записи: 98
30-01-2020 дата публикации

PACKAGED SEMICONDUCTOR DEVICE AND METHOD FOR PREPARING THE SAME

Номер: US20200035629A1
Автор: WANG Mao-Ying
Принадлежит:

The present disclosure provides a packaged semiconductor device and a method for preparing the same. The packaged semiconductor device includes a chip having a conductive pad; a first insulating layer disposed on the chip; a second insulating layer disposed on the first insulating layer; a conductive film disposed on the second insulating layer, a redistribution layer disposed on the conductive film; a probe pad disposed on the redistribution layer; and a third insulating, layer disposed on the redistribution layer and the second insulating layer, wherein the third insulating layer covers a portion of the probe pad, and there is no undercut at a region between the redistribution layer and the probe pad. The size of the probe pad is not limited by the undercut, as the size of the probe pad needs to be reduced in order to meet the requirement of continuous minimization of chip size. 1. A packaged semiconductor device , comprising:a chip comprising a conductive pad;a first insulating layer disposed on the chip;a protective layer disposed between the first insulating layer and the chip;a second insulating layer disposed on the first insulating layer;a conductive film disposed on the second insulating layer, wherein the conductive film penetrates the second insulating layer and contacts the conductive pad;a redistribution layer disposed on the conductive film;a probe pad disposed on the redistribution layer; anda third insulating layer disposed on the redistribution layer and the second insulating layer;wherein the protective layer covers a sidewall and a first portion of a top surface of the conductive pad, while the first insulating layer covers the protective layer and a second portion of the top surface of the conductive pad;wherein the third insulating layer covers a portion of the probe pad, and there is no undercut at a region between the redistribution layer and the probe pad;wherein a drop height of the third insulating layer is substantially less than 3 μm and ...

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Номер записи: 99
30-01-2020 дата публикации

Stacked Integrated Circuit Structure and Method of Forming

Номер: US20200035647A1
Автор: CHEN Wei-Ming, Hou Shang-Yun, Hu Hsien-Pin, Wei Wen-Hsin
Принадлежит:

A semiconductor device, and a method of forming the device, are provided. The semiconductor device includes a first die having a first plurality of contact pads and a second die having a second plurality of contact pads. A substrate is bonded to a first contact pad of the first plurality of contact pads and a first contact pad of the second plurality of contact pads in a face-to-face orientation with the first die and the second die. A first through via extends through the substrate. Molding material is interposed between the first die, the second die and the substrate, the molding material extending along sidewalls of the first die, the second die, and the substrate. A second through via is positioned over a second contact pad of the first plurality of contact pads, the second through via extending through the molding material. 1. A method comprising:positioning a first die and a second die on a carrier substrate;bonding a first substrate to the first die and the second die, the first substrate being connected in a face-to-face connection with the first die and the second die, the first substrate comprising a first through-substrate via;forming a molding material along sidewalls of the first die, the second die, and the first substrate, the molding material covering the first substrate;after forming the molding material, forming an opening in the molding material over the first die;forming a first through-mold via in the opening, wherein the first through-mold via extends through the molding material to the first die, surfaces of the first through-mold via, the molding material, the first substrate, and the first through-substrate via being planar after forming the first through-mold via;forming a first external connector over and directly contacting the first through-mold via, the first external connector comprising a first solder portion; andforming a second external connector over and directly contacting the first through-substrate via, the second external ...

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Номер записи: 100