Electronic devices with semiconductor die attached with sintered metallic layers, and methods of formation of such devices

An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a conductive layer underlying the sintered metallic layer, and a conductive substrate underlying the conductive layer.

ELECTRONIC APPARATUS AND METHOD FOR MANUFACTURING ELECTRONIC APPARATUS

An electronic apparatus includes: a first substrate; an electrode over the first substrate; a first conductor having a porous structure above the first substrate, the first conductor covering an upper surface and a side surface of the electrode; and an insulator above the first substrate, the insulator covering an upper surface and a side surface of the first conductor, wherein the insulator has an opening that exposes the first conductor.

Electronic devices with semiconductor die coupled to a thermally conductive substrate

An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a thermally conductive flow layer underlying the sintered metallic layer, and a thermally conductive substrate underlying the thermally conductive flow layer.

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor substrate and a metal film formed on the semiconductor substrate. The metal film includes a Ni base and a material having condensation energy higher than that of Ni. In a method of manufacturing a semiconductor device, a semiconductor substrate and a target, which is formed by melting P in Ni, are prepared, and sputtering is performed with the target while a portion of the semiconductor substrate where the metal film is to be formed is heated to a temperature of from 280° C. inclusive to 870° C. inclusive.

SEMICONDUCTOR DEVICE

A semiconductor device, provided with a semiconductor substrate (10) and a metal film (20) formed on the semiconductor substrate. The metal film (20) is configured so as to include an Ni base (21) and a material (22) having a higher cohesive energy than Ni. In a method for manufacturing the semiconductor device, a semiconductor substrate (10) and a target formed by fusing P onto Ni are readied, and sputtering is performed using the target while heating the portion of the semiconductor substrate (10) at which the metal film (20) is to be formed to a temperature of 280 to 870 °C.

Optoelektronischer Halbleiterchip und Verfahren zur Herstellung eines optoelektronischen Halbleiterchips

Optoelektronischer Halbleiterchip (100) mit einer Strahlungshauptseite (101), umfassend eine Halbleiterschichtenfolge (2), die zur Emission von Strahlung eingerichtet ist, einen strukturierten Träger (1), der an der Strahlungshauptseite (101) abgewandten Seite des Halbleierchips (100) angeordnet ist, wobei die p-dotierte Halbleiterschicht (23) mittels einer ersten Anschlussschicht (3) elektrisch kontaktiert ist und die n-dotierte Halbleiterschicht (21) mittels einer zweiten Anschlussschicht (4) elektrisch kontaktiert ist, wobei die erste Anschlussschicht (3) mittels einer ersten Kontaktschicht (5) elektrisch kontaktiert ist und die zweite Anschlussschicht (4) mittels einer zweiten Kontaktschicht (6) elektrisch kontaktiert ist, wobei die erste und zweite Kontaktschicht (5, 6) den Träger (1) vollständig durchdringen und die erste Kontaktschicht (5) lateral beabstandet zur zweiten Kontaktschicht (6) angeordnet ist, wobei der Träger (1) ein stabilisierendes Material umfasst, das aus der Gruppe ...

NANOSTRUCTURE BARRIER FOR COPPER WIRE BONDING

A nanostructure barrier for copper wire bonding includes metal grains and inter-grain metal between the metal grains. The nanostructure barrier includes a first metal selected from nickel or cobalt, and a second metal selected from tungsten or molybdenum. A concentration of the second metal is higher in the inter-grain metal than in the metal grains. The nanostructure barrier may be on a copper core wire to provide a coated bond wire. The nanostructure barrier may be on a bond pad to form a coated bond pad. A method of plating the nanostructure barrier using reverse pulse plating is disclosed. A wire bonding method using the coated bond wire is disclosed.

Method of packaging and interconnection of integrated circuits

A semiconductor chip packaging on a flexible substrate is disclosed. The chip and the flexible substrate are provided with corresponding raised and indented micron-scale contact pads with the indented contact pads partially filled with a liquid amalgam. After low temperature amalgam curing, the chip and the substrate form a flexible substrate IC packaging with high conductivity, controllable interface layer thickness, micron-scale contact density and low process temperature. Adhesion between the chip and the substrate can be further enhanced by coating other areas with non-conducting adhesive.

VERFAHREN ZUM VERARBEITEN EINES SUBSTRATS UND ELEKTRONISCHE VORRICHTUNG

Gemäß verschiedenen Ausführungsformen kann ein Verfahren (1500) zum Verarbeiten eines Substrats Folgendes beinhalten: Verarbeiten mehrerer Vorrichtungsgebiete in einem Substrat, die durch Zerteilungsgebiete voneinander getrennt sind, wobei jedes Vorrichtungsgebiet wenigstens eine elektronische Komponente beinhaltet; wobei Verarbeiten jedes Vorrichtungsgebiets der mehreren Vorrichtungsgebiete Folgendes beinhaltet: Bilden einer Vertiefung in das Substrat in dem Vorrichtungsgebiet (1502), wobei die Vertiefung durch Vertiefungsseitenwände des Substrats definiert wird, wobei die Vertiefungsseitenwände in dem Vorrichtungsgebiet angeordnet sind; Bilden einer Kontaktstelle in der Vertiefung (1504), um die wenigstens eine elektronische Komponente elektrisch zu verbinden, wobei die Kontaktstelle eine größere Porosität als die Vertiefungsseitenwände aufweist; und Vereinzeln der mehreren Vorrichtungsgebiete voneinander, indem das Substrat in dem Zerteilungsgebiet zerteilt wird.

ENCAPSULATED STRESS MITIGATION LAYER AND POWER ELECTRONIC ASSEMBLIES INCORPORATING THE SAME

Encapsulated stress mitigation layers and assemblies having the same are disclosed. An assembly that includes a first substrate, a second substrate, an encapsulating layer disposed between the first and second substrates, and a stress mitigation layer disposed in the encapsulating layer such that the stress mitigation layer is encapsulated within the encapsulating layer. The stress mitigation layer has a lower melting temperature relative to a higher melting temperature of the encapsulating layer. The assembly includes an intermetallic compound layer disposed between the first substrate and the encapsulating layer such that the encapsulating layer is separated from the first substrate by the intermetallic compound layer. The stress mitigation layer melts into a liquid when the assembly operates at a temperature above the low melting temperature of the stress mitigation layer and the encapsulating layer maintains the liquid of the stress mitigation layer within the assembly.

Method of packaging and interconnection of integrated circuits

A semiconductor chip packaging on a flexible substrate is disclosed. The chip and the flexible substrate are provided with corresponding raised and indented micron-scale contact pads with the indented contact pads partially filled with a liquid amalgam. After low temperature amalgam curing, the chip and the substrate form a flexible substrate IC packaging with high conductivity, controllable interface layer thickness, micron-scale contact density and low process temperature. Adhesion between the chip and the substrate can be further enhanced by coating other areas with non-conducting adhesive.

Conductive connections, structures with such connections, and methods of manufacture

Conductive connections, structures with such connections, and methods of manufacture

A solder connection may be surrounded by a solder locking layer (1210, 2210) and may be recessed in a hole (1230) in that layer. The recess may be obtained by evaporating a vaporizable portion (1250) of the solder connection. Other features are also provided.

Structures and methods for low temperature bonding

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

Leistungshalbleitereinrichtung und Fertigungsverfahren für selbige

Eine Leistungshalbleitereinrichtung (1) weist Folgendes auf: eine plattenförmige erste dicke Kupferschicht (14), eine Isolationslagenschicht (16), die auf der ersten dicken Kupferschicht (14) angeordnet ist, eine plattenförmige bzw. strukturgeformte zweite dicke Kupferschicht (18A), die auf der Isolationslagenschicht (16) angeordnet ist, eine leitfähige Bondschicht (20), die auf der zweiten dicken Kupferschicht (18A) angeordnet ist, und eine Halbleiterleistungsvorrichtung (22), die auf der Bondschicht (20) angeordnet ist, wobei die Halbleiterleistungsvorrichtung (22) an die Bondschicht (20) gebondet ist und die Vickers-Härte der zweiten dicken Kupferschicht (18A) kleiner als eine Vickers-Härte der ersten dicken Kupferschicht (14) ist und gleich oder kleiner als 50 ist. Es ist eine Leistungshalbleitereinrichtung bereitgestellt, die zum Verbessern einer Zuverlässigkeit einer Bondung von dieser ohne Erhöhen eines thermischen Widerstands in der Lage ist.

Method of packaging and interconnection of integrated circuits

A semiconductor chip packaging on a flexible substrate is disclosed. The chip and the flexible substrate are provided with corresponding raised and indented micron-scale contact pads with the indented contact pads partially filled with a liquid amalgam. After low temperature amalgam curing, the chip and the substrate form a flexible substrate IC packaging with high conductivity, controllable interface layer thickness, micron-scale contact density and low process temperature. Adhesion between the chip and the substrate can be further enhanced by coating other areas with non-conducting adhesive.

Electronic apparatus and method for manufacturing electronic apparatus

An electronic apparatus includes: a first substrate; an electrode over the first substrate; a first conductor having a porous structure above the first substrate, the first conductor covering an upper surface and a side surface of the electrode; and an insulator above the first substrate, the insulator covering an upper surface and a side surface of the first conductor, wherein the insulator has an opening that exposes the first conductor.

Method of processing a porous conductive structure in connection to an electronic component on a substrate

According to various embodiments, a method for processing a substrate may include: processing a plurality of device regions in a substrate separated from each other by dicing regions, each device region including at least one electronic component; wherein processing each device region of the plurality of device regions includes: forming a recess into the substrate in the device region, wherein the recess is defined by recess sidewalls of the substrate, wherein the recess sidewalls are arranged in the device region; forming a contact pad in the recess to electrically connect the at least one electronic component, wherein the contact pad has a greater porosity than the recess sidewalls; and singulating the plurality of device regions from each other by dicing the substrate in the dicing region.

Conductive connections, structures with such connections, and methods of manufacture

本案中，藉由焊料卡固層(1210,2210)所圍繞之一種焊料連接，可凹陷進該層中的孔(1230)。該凹陷可藉由蒸發該焊接連接的可蒸發部分(1250)而獲得。另外，本案也提供其他特徵。

Method of packaging and interconnection of integrated circuits

A semiconductor chip packaging on a flexible substrate is disclosed. The chip and the flexible substrate are provided with corresponding raised and indented micron-scale contact pads with the indented contact pads partially filled with a liquid amalgam. After low temperature amalgam curing, the chip and the substrate form a flexible substrate IC packaging with high conductivity, controllable interface layer thickness, micron-scale contact density and low process temperature. Adhesion between the chip and the substrate can be further enhanced by coating other areas with non-conducting adhesive.

NANOSTRUCTURE BARRIER FOR COPPER WIRE BONDING

A nanostructure barrier for copper wire bonding includes metal grains and inter-grain metal between the metal grains. The nanostructure barrier includes a first metal selected from nickel or cobalt, and a second metal selected from tungsten or molybdenum. A concentration of the second metal is higher in the inter-grain metal than in the metal grains. The nanostructure barrier may be on a copper core wire to provide a coated bond wire. The nanostructure barrier may be on a bond pad to form a coated bond pad. A method of plating the nanostructure barrier using reverse pulse plating is disclosed. A wire bonding method using the coated bond wire is disclosed.

ENCAPSULATED STRESS MITIGATION LAYER AND POWER ELECTRONIC ASSEMBLIES INCORPORATING THE SAME

Encapsulated stress mitigation layers and assemblies having the same are disclosed. An assembly that includes a first substrate, a second substrate, an encapsulating layer disposed between the first and second substrates, and a stress mitigation layer disposed in the encapsulating layer such that the stress mitigation layer is encapsulated within the encapsulating layer. The stress mitigation layer has a lower melting temperature relative to a higher melting temperature of the encapsulating layer. The assembly includes an intermetallic compound layer disposed between the first substrate and the encapsulating layer such that the encapsulating layer is separated from the first substrate by the intermetallic compound layer. The stress mitigation layer melts into a liquid when the assembly operates at a temperature above the low melting temperature of the stress mitigation layer and the encapsulating layer maintains the liquid of the stress mitigation layer within the assembly.

DIELECTRIC AND METALLIC NANOWIRE BOND LAYERS

In some examples, an electronic device comprises a first component having a surface, a second component having a surface, and a bond layer positioned between the surfaces of the first and second components to couple the first and second components to each other. The bond layer includes a set of metallic nanowires and a dielectric portion. The dielectric portion comprises a polymer matrix and dielectric nanoparticles.

Dielectric and metallic nanowire bond layers

In some examples, an electronic device comprises a first component having a surface, a second component having a surface, and a bond layer positioned between the surfaces of the first and second components to couple the first and second components to each other. The bond layer includes a set of metallic nanowires and a dielectric portion. The dielectric portion comprises a polymer matrix and dielectric nanoparticles.

Encapsulated stress mitigation layer and power electronic assemblies incorporating the same

Encapsulated stress mitigation layers and assemblies having the same are disclosed. An assembly that includes a first substrate, a second substrate, an encapsulating layer disposed between the first and second substrates, and a stress mitigation layer disposed in the encapsulating layer such that the stress mitigation layer is encapsulated within the encapsulating layer. The stress mitigation layer has a lower melting temperature relative to a higher melting temperature of the encapsulating layer. The assembly includes an intermetallic compound layer disposed between the first substrate and the encapsulating layer such that the encapsulating layer is separated from the first substrate by the intermetallic compound layer. The stress mitigation layer melts into a liquid when the assembly operates at a temperature above the low melting temperature of the stress mitigation layer and the encapsulating layer maintains the liquid of the stress mitigation layer within the assembly.

POWER SEMICONDUCTOR APPARATUS AND FABRICATION METHOD FOR THE SAME

The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10−6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.

ELECTRONIC DEVICES WITH ATTACHED DIE STRUCTURES AND METHODS OF FORMATION OF SUCH DEVICES

An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a conductive layer underlying the sintered metallic layer, and a conductive substrate underlying the conductive layer.

Conductive connections, structures with such connections, and methods of manufacture

A solder connection may be surrounded by a solder locking layer ( 1210, 2210 ) and may be recessed in a hole ( 1230 ) in that layer. The recess may be obtained by evaporating a vaporizable portion ( 1250 ) of the solder connection. Other features are also provided.

Nanostructure barrier for copper wire bonding

A nanostructure barrier for copper wire bonding includes metal grains and inter-grain metal between the metal grains. The nanostructure barrier includes a first metal selected from nickel or cobalt, and a second metal selected from tungsten or molybdenum. A concentration of the second metal is higher in the inter-grain metal than in the metal grains. The nanostructure barrier may be on a copper core wire to provide a coated bond wire. The nanostructure barrier may be on a bond pad to form a coated bond pad. A method of plating the nanostructure barrier using reverse pulse plating is disclosed. A wire bonding method using the coated bond wire is disclosed.

Nanostructure barrier for copper wire bonding

A nanostructure barrier for copper wire bonding includes metal grains and inter-grain metal between the metal grains. The nanostructure barrier includes a first metal selected from nickel or cobalt, and a second metal selected from tungsten or molybdenum. A concentration of the second metal is higher in the inter-grain metal than in the metal grains. The nanostructure barrier may be on a copper core wire to provide a coated bond wire. The nanostructure barrier may be on a bond pad to form a coated bond pad. A method of plating the nanostructure barrier using reverse pulse plating is disclosed. A wire bonding method using the coated bond wire is disclosed.

Encapsulated stress mitigation layer and power electronic assemblies incorporating the same

Encapsulated stress mitigation layers and assemblies having the same are disclosed. An assembly that includes a first substrate, a second substrate, an encapsulating layer disposed between the first and second substrates, and a stress mitigation layer disposed in the encapsulating layer such that the stress mitigation layer is encapsulated within the encapsulating layer. The stress mitigation layer has a lower melting temperature relative to a higher melting temperature of the encapsulating layer. The assembly includes an intermetallic compound layer disposed between the first substrate and the encapsulating layer such that the encapsulating layer is separated from the first substrate by the intermetallic compound layer. The stress mitigation layer melts into a liquid when the assembly operates at a temperature above the low melting temperature of the stress mitigation layer and the encapsulating layer maintains the liquid of the stress mitigation layer within the assembly.

CONDUCTIVE CONNECTIONS, STRUCTURES WITH SUCH CONNECTIONS, AND METHODS OF MANUFACTURE

A solder connection may be surrounded by a solder locking layer ( 1210, 2210 ) and may be recessed in a hole ( 1230 ) in that layer. The recess may be obtained by evaporating a vaporizable portion ( 1250 ) of the solder connection. Other features are also provided.

Method of packaging and interconnection of integrated circuits

A semiconductor chip packaging on a flexible substrate is disclosed. The chip and the flexible substrate are provided with corresponding raised and indented micron-scale contact pads with the indented contact pads partially filled with a liquid amalgam. After low temperature amalgam curing, the chip and the substrate form a flexible substrate IC packaging with high conductivity, controllable interface layer thickness, micron-scale contact density and low process temperature. Adhesion between the chip and the substrate can be further enhanced by coating other areas with non-conducting adhesive.

METHOD FOR PROCESSING A SUBSTRATE AND AN ELECTRONIC DEVICE

According to various embodiments, a method for processing a substrate may include: processing a plurality of device regions in a substrate separated from each other by dicing regions, each device region including at least one electronic component; wherein processing each device region of the plurality of device regions includes: forming a recess into the substrate in the device region, wherein the recess is defined by recess sidewalls of the substrate, wherein the recess sidewalls are arranged in the device region; forming a contact pad in the recess to electrically connect the at least one electronic component, wherein the contact pad has a greater porosity than the recess sidewalls; and singulating the plurality of device regions from each other by dicing the substrate in the dicing region.

Power semiconductor device

パワー半導体装置（１）は、平板状の第１厚銅層（１４）と、第１厚銅層（１４）上に配置された絶縁シート層（１６）と、絶縁シート層（１６）上に配置され、パターン形成された第２厚銅層（１８Ａ）と、第２厚銅層（１８Ａ）上に配置された導電性の接合層（２０）と、接合層（２０）上に配置された半導体パワーデバイス（２２）とを備え、半導体パワーデバイス（２２）は、接合層（２０）と接合すると共に、第２厚銅層（１８Ａ）のビッカースの硬さは、第１厚銅層（１４）のビッカースの硬さよりも小さく、５０以下を有する。熱抵抗を増加させることなく、接合の信頼性の向上が可能なパワー半導体装置を提供する。

Power semiconductor apparatus and fabrication method for the same

The power semiconductor apparatus includes: a semiconductor device 401 ; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420 b having a CTE equal to or less than 5×10 −6 /° C., for example; and a first metal layer 420 a and a third metal layer 420 c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.

Structures and methods for low temperature bonding

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

功率半导体装置和半导体功率模块

本发明提供功率半导体装置和半导体功率模块。该功率半导体装置具备平板状的厚铜基板、部分地配置在所述厚铜基板上的导电性的接合层、配置于所述接合层上的半导体功率器件、以及与所述半导体功率器件的电极电连接的外部连接用端子，所述厚铜基板的维氏硬度为50以下。

Power semiconductor apparatus and fabrication method for the same

The power semiconductor apparatus includes: a semiconductor device 401 ; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420 b having a CTE equal to or less than 5×10 −6 /° C., for example; and a first metal layer 420 a and a third metal layer 420 c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.

Dielectric and metallic nanowire bond layers

In some examples, an electronic device comprises a first component having a surface, a second component having a surface, and a bond layer positioned between the surfaces of the first and second components to couple the first and second components to each other. The bond layer includes a set of metallic nanowires and a dielectric portion. The dielectric portion comprises a polymer matrix and dielectric nanoparticles.

Power semiconductor apparatus and fabrication method for the same

The power semiconductor apparatus includes: a semiconductor device 401 ; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420 b having a CTE equal to or less than 5×10 −6 /° C., for example; and a first metal layer 420 a and a third metal layer 420 c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.

用于铜引线接合的纳米结构阻挡层

本发明的名称为用于铜引线接合的纳米结构阻挡层。用于铜引线接合的纳米结构阻挡层(110)包括金属晶粒(114)和在金属晶粒(114)之间的晶粒间金属(116)。纳米结构阻挡层(110)包括选自镍或钴的第一金属，和选自钨或钼的第二金属。晶粒间金属(116)中第二金属的浓度高于金属晶粒(114)中第二金属的浓度。纳米结构阻挡层(110)可以在铜芯引线(100)上以提供涂布的接合引线。纳米结构阻挡层(110)可以在接合垫上以形成涂布的接合垫。公开了使用反向脉冲电镀来电镀纳米结构阻挡层(110)的方法。公开了使用涂布的接合引线的引线接合方法。

Structures for low temperature bonding using nanoparticles

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

用于低温接合的结构和方法

一种制造组件的方法，其可包含将在第一基板的第一表面处的第一电性传导元件的顶表面与在第二基板的主要表面处的第二电性传导元件的顶表面并置。其中为下列中之一者：所述第一传导元件的所述顶表面可下凹至所述第一表面之下，或所述第二基板的所述顶表面可下凹至所述主要表面之下。电性传导纳米粒子是被设置在所述第一传导元件和所述第二传导元件的所述顶表面之间。所述传导纳米粒子具有的长度尺寸是小于100纳米。所述方法亦可包含至少在所述经并置的第一传导元件和第二传导元件的界面处提高温度到一结合温度，在所述结合温度时所述传导纳米粒子可造成冶金结合形成于所述经并置的第一传导元件和第二传导元件之间。

用于低温接合的结构和方法

一种制造组件的方法，其可包含将在第一基板的第一表面处的第一电性传导元件的顶表面与在第二基板的主要表面处的第二电性传导元件的顶表面并置。其中为下列中之一者：所述第一传导元件的所述顶表面可下凹至所述第一表面之下，或所述第二基板的所述顶表面可下凹至所述主要表面之下。电性传导纳米粒子是被设置在所述第一传导元件和所述第二传导元件的所述顶表面之间。所述传导纳米粒子具有的长度尺寸是小于100纳米。所述方法亦可包含至少在所述经并置的第一传导元件和第二传导元件的界面处提高温度到一结合温度，在所述结合温度时所述传导纳米粒子可造成冶金结合形成于所述经并置的第一传导元件和第二传导元件之间。

用于低温接合的结构和方法

一种制造组件的方法，其可包含将在第一基板的第一表面处的第一电性传导元件的顶表面与在第二基板的主要表面处的第二电性传导元件的顶表面并置。其中为下列中之一者：所述第一传导元件的所述顶表面可下凹至所述第一表面之下，或所述第二基板的所述顶表面可下凹至所述主要表面之下。电性传导纳米粒子是被设置在所述第一传导元件和所述第二传导元件的所述顶表面之间。所述传导纳米粒子具有的长度尺寸是小于100纳米。所述方法亦可包含至少在所述经并置的第一传导元件和第二传导元件的界面处提高温度到一结合温度，在所述结合温度时所述传导纳米粒子可造成冶金结合形成于所述经并置的第一传导元件和第二传导元件之间。

用於低溫接合的結構和方法

一種製造組件之方法，其可包含將在第一基板的第一表面處的第一電性傳導元件的頂表面與在第二基板的主要表面處的第二電性傳導元件的頂表面並置。其中為下列中之一者：所述第一傳導元件的所述頂表面可下凹至所述所述第一表面之下，或所述第二基板的所述頂表面可下凹至所述主要表面之下。電性傳導奈米粒子是被設置在所述第一傳導元件和所述第二傳導元件的所述頂表面之間。所述傳導奈米粒子具有的長度尺寸是小於100奈米。所述方法亦可包含至少在所述經並置的第一傳導元件和第二傳導元件的界面處提高溫度到一結合溫度，在所述結合溫度時所述傳導奈米粒子可造成冶金結合形成於所述經並置的第一傳導元件和第二傳導元件之間。

Methods for low temperature bonding using nanoparticles

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

用于低温接合的结构和方法

一种制造组件的方法，其可包含将在第一基板的第一表面处的第一电性传导元件的顶表面与在第二基板的主要表面处的第二电性传导元件的顶表面并置。其中为下列中之一者：所述第一传导元件的所述顶表面可下凹至所述第一表面之下，或所述第二基板的所述顶表面可下凹至所述主要表面之下。电性传导纳米粒子是被设置在所述第一传导元件和所述第二传导元件的所述顶表面之间。所述传导纳米粒子具有的长度尺寸是小于100纳米。所述方法亦可包含至少在所述经并置的第一传导元件和第二传导元件的界面处提高温度到一结合温度，在所述结合温度时所述传导纳米粒子可造成冶金结合形成于所述经并置的第一传导元件和第二传导元件之间。

Structures for low temperature bonding using nanoparticles

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

パワー半導体装置およびその製造方法

用于低温接合的结构和方法

一种制造组件的方法，其可包含将在第一基板的第一表面处的第一电性传导元件的顶表面与在第二基板的主要表面处的第二电性传导元件的顶表面并置。其中为下列中之一者：所述第一传导元件的所述顶表面可下凹至所述第一表面之下，或所述第二基板的所述顶表面可下凹至所述主要表面之下。电性传导纳米粒子是被设置在所述第一传导元件和所述第二传导元件的所述顶表面之间。所述传导纳米粒子具有的长度尺寸是小于100纳米。所述方法亦可包含至少在所述经并置的第一传导元件和第二传导元件的界面处提高温度到一结合温度，在所述结合温度时所述传导纳米粒子可造成冶金结合形成于所述经并置的第一传导元件和第二传导元件之间。

用于低温接合的结构和方法

一种制造组件的方法，其可包含将在第一基板的第一表面处的第一电性传导元件的顶表面与在第二基板的主要表面处的第二电性传导元件的顶表面并置。其中为下列中之一者：所述第一传导元件的所述顶表面可下凹至所述第一表面之下，或所述第二基板的所述顶表面可下凹至所述主要表面之下。电性传导纳米粒子是被设置在所述第一传导元件和所述第二传导元件的所述顶表面之间。所述传导纳米粒子具有的长度尺寸是小于100纳米。所述方法亦可包含至少在所述经并置的第一传导元件和第二传导元件的界面处提高温度到一结合温度，在所述结合温度时所述传导纳米粒子可造成冶金结合形成于所述经并置的第一传导元件和第二传导元件之间。

用于低温接合的结构和方法

一种制造组件的方法，其可包含将在第一基板的第一表面处的第一电性传导元件的顶表面与在第二基板的主要表面处的第二电性传导元件的顶表面并置。其中为下列中之一者：所述第一传导元件的所述顶表面可下凹至所述第一表面之下，或所述第二基板的所述顶表面可下凹至所述主要表面之下。电性传导纳米粒子是被设置在所述第一传导元件和所述第二传导元件的所述顶表面之间。所述传导纳米粒子具有的长度尺寸是小于100纳米。所述方法亦可包含至少在所述经并置的第一传导元件和第二传导元件的界面处提高温度到一结合温度，在所述结合温度时所述传导纳米粒子可造成冶金结合形成于所述经并置的第一传导元件和第二传导元件之间。

功率半导体装置和半导体功率模块

本发明提供功率半导体装置和半导体功率模块。该功率半导体装置具备平板状的厚铜基板、部分地配置在所述厚铜基板上的导电性的接合层、配置于所述接合层上的半导体功率器件、以及与所述半导体功率器件的电极电连接的外部连接用端子，所述厚铜基板的维氏硬度为50以下。

Structures for low temperature bonding using nanoparticles

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

Structures and methods for low temperature bonding

A bonded structure, comprising a first component including a first substrate having a first dielectric surface and a first conductive feature at the first dielectric surface; and a second component including a second substrate having a second dielectric surface and a second conductive feature at the second dielectric surface. The first dielectric surface is directly bonded to the second dielectric surface without an underfill. The first conductive feature is bonded to second conductive feature by way of a conductive bond region between the first and second conductive features, wherein the bond region comprises structural evidence of conductive nanoparticles employed in bonding the first conductive feature to the second conductive feature.

功率半导体装置及其制造方法

一种功率半导体装置(1)，具备平板状的第1厚铜层(14)、配置于第1厚铜层(14)上的绝缘片层(16)、配置于绝缘片层(16)上且形成了图案的第2厚铜层(18A)、配置于第2厚铜层(18A)上的导电性的接合层(20)、以及配置于接合层(20)上的半导体功率器件(22)，半导体功率器件(22)与接合层(20)接合，同时，第2厚铜层(18A)的维氏硬度比第1厚铜层(14)的维氏硬度小，为50以下。提供一种功率半导体装置，能够不增加热阻而提高接合的可靠性。

用于低温接合的结构和方法

一种制造组件的方法，其可包含将在第一基板的第一表面处的第一电性传导元件的顶表面与在第二基板的主要表面处的第二电性传导元件的顶表面并置。其中为下列中之一者：所述第一传导元件的所述顶表面可下凹至所述第一表面之下，或所述第二基板的所述顶表面可下凹至所述主要表面之下。电性传导纳米粒子是被设置在所述第一传导元件和所述第二传导元件的所述顶表面之间。所述传导纳米粒子具有的长度尺寸是小于100纳米。所述方法亦可包含至少在所述经并置的第一传导元件和第二传导元件的界面处提高温度到一结合温度，在所述结合温度时所述传导纳米粒子可造成冶金结合形成于所述经并置的第一传导元件和第二传导元件之间。

用于铜引线接合的纳米结构阻挡层

本发明的名称为用于铜引线接合的纳米结构阻挡层。用于铜引线接合的纳米结构阻挡层(110)包括金属晶粒(114)和在金属晶粒(114)之间的晶粒间金属(116)。纳米结构阻挡层(110)包括选自镍或钴的第一金属，和选自钨或钼的第二金属。晶粒间金属(116)中第二金属的浓度高于金属晶粒(114)中第二金属的浓度。纳米结构阻挡层(110)可以在铜芯引线(100)上以提供涂布的接合引线。纳米结构阻挡层(110)可以在接合垫上以形成涂布的接合垫。公开了使用反向脉冲电镀来电镀纳米结构阻挡层(110)的方法。公开了使用涂布的接合引线的引线接合方法。