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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 11856. Отображено 100.

05-01-2012 дата публикации

Method for manufacture of integrated circuit package system with protected conductive layers for pads

Номер: US20120003830A1

Автор: Haijing Cao, Qing Zhang, Yaojian Lin

Принадлежит: Individual

A method for manufacture of an integrated circuit package system includes: providing an integrated circuit die having a contact pad; forming a protection cover over the contact pad; forming a passivation layer having a first opening over the protection cover with the first opening exposing the protection cover; developing a conductive layer over the passivation layer; forming a pad opening in the protection cover for exposing the contact pad having the conductive layer partially removed; and an interconnect directly on the contact pad and only adjacent to the protection cover and the passivation layer.

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Номер записи: 1

12-01-2012 дата публикации

Power semiconductor module and fabrication method

Номер: US20120009733A1

Автор: Eladio Clemente Delgado, Ernest Wayne Balch, Kevin Matthew Durocher, Paul Alan McConnelee, Raymond Albert Fillion, Richard Alfred Beaupre, Stephen Daley Arthur

Принадлежит: General Electric Co

A power semiconductor module includes: an interconnect layer including an electrical conductor patterned on a dielectric layer, the electrical conductor including a power coupling portion having a thickness sufficient to carry power currents and a control coupling portion having a thickness thinner than that of the power coupling portion; and a semiconductor power device physically coupled to the interconnect layer and electrically coupled to the power coupling portion of the electrical conductor.

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Номер записи: 2

09-02-2012 дата публикации

Method for Forming a Patterned Thick Metallization atop a Power Semiconductor Chip

Номер: US20120034775A1

Автор: Il Kwan Lee

Принадлежит: Individual

A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK 1 together with its built-in alignment mark using a hot metal process; depositing a top metal layer of sub-thickness TK 2 using a cold metal process thus forming a stacked thick metallization of total thickness TK=TK 1 +TK 2 ; then, use the built-in alignment mark as reference, patterning the stacked thick metallization. A patterned thick metallization is thus formed with the advantages of better metal step coverage owing to the superior step coverage nature of the hot metal process as compared to the cold metal process; and lower alignment error rate owing to the lower alignment signal noise nature of the cold metal process as compared to the hot metal process.

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Номер записи: 3

08-03-2012 дата публикации

Bi-directional, reverse blocking battery switch

Номер: US20120056261A1

Автор: Anthony C. Tsui, Anthony Chia, Hongbo Yang, HUI Teng, James Harnden, Liming Wong, Lynda Harnden, Ming Zhou

Принадлежит: GEM Services Inc USA

Embodiments of the present invention relate to an improved package for a bi-directional and reverse blocking battery switch. According to one embodiment, two switches are oriented side-by-side, rather than end-to-end, in a die package. This configuration reduces the total switch resistance for a given die area, often reducing the resistance enough to avoid the use of backmetal in order to meet resistance specifications. Elimination of backmetal reduces the overall cost of the die package and removes the potential failure modes associated with the manufacture of backmetal. Embodiments of the present invention may also allow for more pin connections and an increased pin pitch. This results in redundant connections for higher current connections, thereby reducing electrical and thermal resistance and minimizing the costs of manufacture or implementation of the die package.

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Номер записи: 4

15-03-2012 дата публикации

Control device of semiconductor device

Номер: US20120061722A1

Автор: Masahiro MASUNAGA, Takayuki Hashimoto

Принадлежит: Renesas Electronics Corp

A control device of a semiconductor device is provided. The control device of a semiconductor device is capable of reducing both ON resistance and feedback capacitance in a hollow-gate type planar MOSFET to which a second gate electrode is provided or a trench MOSFET to which a second gate electrode is provided. In the control device controlling driving of a hollow-gate type planar MOSFET to which a second gate electrode is provided or a trench MOSFET to which a second gate electrode is provided, a signal of tuning ON or OFF is outputted to a gate electrode in a state of outputting a signal of turning OFF to the second gate electrode.

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Номер записи: 5

22-03-2012 дата публикации

Integrated Power Converter Package With Die Stacking

Номер: US20120068320A1

Автор: Eric Yang, Hunt Hang Jiang, Jinghai Zhou

Принадлежит: Monolithic Power Systems Inc

An integrated circuit for implementing a switch-mode power converter is disclosed. The integrated circuit comprises at least a first semiconductor die having an electrically quiet surface, a second semiconductor die for controlling the operation of said first semiconductor die stacked on said first semiconductor die having said electrically quiet surface and a lead frame structure for supporting said first semiconductor die and electrically coupling said first and second semiconductor dies to external circuitry.

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Номер записи: 6

31-05-2012 дата публикации

Transistor power switch device and method of measuring its characteristics

Номер: US20120133388A1

Автор: Beatrice Bernoux, Jean Reynes, Rene Escoffier

Принадлежит: FREESCALE SEMICONDUCTOR INC

A transistor power switch device comprising an array of vertical transistor elements for carrying current between first and second faces of a semiconductor body. The device also comprises a semiconductor monitor element comprising first and second semiconductor monitor regions in the semiconductor body and a monitor conductive layer distinct from the current carrying conductive layer of the transistor array. The semiconductor monitor element presents semiconductor properties representative of the transistor array. Characteristics of the semiconductor monitor element are measured as representative of characteristics of the transistor array. Source metal ageing of a transistor power switch device is monitored by measuring and recording a parameter which is a function of a sheet resistance of the monitor conductive layer when the transistor power switch device is new and comparing it with its value after operation of the device. A measured current is applied between a first location on an elongate strip element of the monitor conductive layer and a first location on one of a pair of lateral extensions of the strip, and the corresponding voltage developed between a second location on the elongate strip element and the other of said pair of lateral extensions is measured.

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Номер записи: 7

07-06-2012 дата публикации

Semiconductor Device

Номер: US20120139130A1

Автор: Masaki Shiraishi, Nobuyoshi Matsuura, Tomoaki Uno, Yukihiro Satou

Принадлежит: Renesas Electronics Corp

The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.

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Номер записи: 8

28-06-2012 дата публикации

Semiconductor device

Номер: US20120161231A1

Автор: Tomohiro Tamaki, Yoshito Nakazawa

Принадлежит: Renesas Electronics Corp

In a semiconductor power device such as a power MOSFET having a super-junction structure in each of an active cell region and a chip peripheral region, an outer end of a surface region of a second conductivity type coupled to a main junction of the second conductivity type in a surface of a drift region of a first conductivity type and having a concentration lower than that of the main junction is located in a middle region between an outer end of the main junction and an outer end of the super-junction structure in the chip peripheral region.

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Номер записи: 9

26-07-2012 дата публикации

Semiconductor chip module, semiconductor package having the same and package module

Номер: US20120187560A1

Автор: Hyeon Ji BAEK, Hyung Ju CHOI, Jong Hyun Kim, Mun Aun HYUN

Принадлежит: Hynix Semiconductor Inc

A semiconductor module comprising a plurality of semiconductor chips where at least one semiconductor chip is laterally offset with respect to a second semiconductor chip, and substantially aligned with a third semiconductor chip such that an electrical connection can be made between an electrical contact in the first semiconductor chip and an electrical contact in the third semiconductor chip.

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Номер записи: 10

23-08-2012 дата публикации

Semiconductor device and method for manufacturing semiconductor device

Номер: US20120211764A1

Автор: Keiji Watanabe, Keishiro Okamoto, Nobuhiro Imaizumi, Tadahiro Imada

Принадлежит: Fujitsu Ltd

A semiconductor device includes: a support base material, and a semiconductor element bonded to the support base material with a binder, the binder including: a porous metal material that contacts the support base material and the semiconductor element, and a solder that is filled in at least one part of pores of the porous metal material.

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Номер записи: 11

30-08-2012 дата публикации

Method of producing semiconductor device and semiconductor device

Номер: US20120217545A1

Автор: Yoichi Kamada

Принадлежит: Fujitsu Ltd

A method of producing a semiconductor device, includes: forming a semiconductor layer on a substrate; forming an a recess in the semiconductor layer by dry etching with a gas containing fluorine components, the recess having an opening portion on the surface of the semiconductor layer; forming a fluorine-containing region by heating the semiconductor layer and thus diffusing, into the semiconductor layer, the fluorine components attached to side surfaces and a bottom surface of the recess; forming an insulating film on an inner surface of the recess and on the semiconductor layer; and forming an electrode on the insulating film in a region in which the recess is formed.

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Номер записи: 12

30-08-2012 дата публикации

Semiconductor device and method of manufacturing the same, and power supply apparatus

Номер: US20120217591A1

Автор: Yoichi Kamada

Принадлежит: Fujitsu Ltd

A semiconductor device includes an electrode material diffusion suppression layer provided either between a gate electrode and a gate insulation film, between Al-containing ohmic electrodes and an Au interconnection, and below the gate electrode and above the Al-containing ohmic electrodes, the electrode material diffusion suppression layer having a structure wherein a first the TaN layer, a Ta layer, and a second the TaN layer are stacked in sequence.

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Номер записи: 13

27-09-2012 дата публикации

Semiconductor device and manufacturing method of the same

Номер: US20120241855A1

Автор: Yoshito Nakazawa, Yuji Yatsuda

Принадлежит: Individual

In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n + -type semiconductor region of the protective diode are formed in the same step.

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Номер записи: 14

04-10-2012 дата публикации

Heat conduction for chip stacks and 3-d circuits

Номер: US20120248627A1

Автор: Francois Hebert, Stephen Joseph Gaul

Принадлежит: INTERSIL AMERICAS LLC

A semiconductor device assembly and method can include a single semiconductor layer or stacked semiconductor layers, for example semiconductor wafers or wafer sections (semiconductor dice). On each semiconductor layer, a diamond layer formed therethrough can aid in the routing and dissipation of heat. The diamond layer can include a first portion on the back of the semiconductor layer, and one or more second portions which extend vertically into the semiconductor layer, for example completely through the semiconductor layer. Thermal contact can then be made to the diamond layer to conduct heat away from the one or more semiconductor layers. A conductive via can be formed through the diamond layers to provide signal routing and heat dissipation capabilities.

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Номер записи: 15

25-10-2012 дата публикации

Semiconductor device

Номер: US20120267682A1

Автор: Takamitsu Kanazawa, Toshiyuki Hata

Принадлежит: Renesas Electronics Corp

A semiconductor device in which the wiring resistance and parasitic inductance of a semiconductor package configuring a power semiconductor module is reduced. In the semiconductor device, a semiconductor chip with an IGBT formed therein and a diode chip are mounted over the upper surface of a die pad. An emitter pad of the semiconductor chip and an anode pad of the diode chip are coupled with a lead by an Al wire. One end of the lead is located in a higher position than the upper surface of the die pad in order to shorten the length of the Al wire for coupling the emitter pad and the lead.

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Номер записи: 16

15-11-2012 дата публикации

Electronic device and manufacturing thereof

Номер: US20120286293A1

Автор: Josef Hoeglauer, Ralf Otremba

Принадлежит: INFINEON TECHNOLOGIES AG

An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane.

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Номер записи: 17

15-11-2012 дата публикации

Method for Making Solder-top Enhanced Semiconductor Device of Low Parasitic Packaging Impedance

Номер: US20120289001A1

Автор: Anup Bhalla, Francois Hebert, Kai Liu, Ming Sun

Принадлежит: Alpha and Omega Semiconductor Ltd

A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes lithographically patterning the top metal layer into the contact zones and the contact enhancement zones; then forming a solder layer atop each of the contact enhancement zones using a stencil process for an increased composite thickness.

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Номер записи: 18

22-11-2012 дата публикации

Method for Producing a Metal Layer on a Substrate and Device

Номер: US20120292773A1

Автор: Hans-Joachim Schulze, Khalil Hosseini

Принадлежит: INFINEON TECHNOLOGIES AG

A method produces a metal layer on a semiconductor substrate. A metal layer is produced on the semiconductor substrate by depositing metal particles. The metal particles include cores made of a first metal material and shells surrounding the cores. The shells are made of a second metal material that is resistant to oxidation.

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Номер записи: 19

22-11-2012 дата публикации

Backside Power Delivery Using Die Stacking

Номер: US20120292777A1

Автор: Jonathan P. Lotz

Принадлежит: Advanced Micro Devices Inc

In a stacked die device having an active circuit die bonded on top of a power delivery die using, circuit components formed on the active circuit die are connected to receive power from a coarse network of low resistance, high capacitance power and ground conductors in the power delivery die through conductive via structures or through silicon vias (TSVs) formed in the active circuit die so that primary power is provided from the backside of the active circuit die, leaving more resources and space in the metal interconnect structure for input/output signal routing.

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Номер записи: 20

06-12-2012 дата публикации

Semiconductor device and driving apparatus including semiconductor device

Номер: US20120306328A1

Автор: Toshihiro Fujita

Принадлежит: Denso Corp

A semiconductor device includes a semiconductor module and a pressing member configured to press the semiconductor module to a heat radiation member. The semiconductor module includes switching elements, conductors, and a molded member. Each of the switching elements is mounted on a corresponding one of the conductors. The molded member covers the switching elements and the conductors. More than three of the switching elements are disposed around the pressing member. The switching elements are disposed in a region in which a pressure generated between the semiconductor module and the heat radiation member by pressing with the pressing member is greater than or equal to a predetermined pressure with which heat generated from the switching elements is releasable from the semiconductor module to the heat radiation member.

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Номер записи: 21

13-12-2012 дата публикации

Impedence controlled packages with metal sheet or 2-layer rdl

Номер: US20120313228A1

Автор: Belgacem Haba, Ellis Chau, Philip Damberg, Richard DeWitt Crisp, Wael Zohni

Принадлежит: Tessera LLC

A microelectronic assembly includes an interconnection element, a conductive plane, a microelectronic device, a plurality of traces, and first and second bond elements. The interconnection element includes a dielectric element, a plurality of element contacts, and at least one reference contact thereon. The microelectronic device includes a front surface with device contacts exposed thereat. The conductive plane overlies a portion of the front surface of the microelectronic device. Traces overlying a surface of the conductive plane are insulated therefrom and electrically connected with the element contacts. The traces also have substantial portions spaced a first height above and extending at least generally parallel to the conductive plane, such that a desired impedance is achieved for the traces. First bond element electrically connects the at least one conductive plane with the at least one reference contact. Second bond elements electrically connect device contacts with the traces.

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Номер записи: 22

20-12-2012 дата публикации

Electronic device and manufacturing thereof

Номер: US20120319109A1

Автор: Andreas Schloegl, Marco Seibt, Mario Feldvoss, Michael Treu, Ralf Otremba, Uwe Kirchner, Wolfgang Peinhopf

Принадлежит: INFINEON TECHNOLOGIES AG

An electronic device and manufacturing thereof. One embodiment provides a semiconductor chip having a control electrode and a first load electrode on a first surface and a second load electrode on a second surface. A first lead is electrically coupled to the control electrode. A second lead is electrically coupled to the first load electrode. A third lead is electrically coupled to the first load electrode, the third lead being separate from the second lead. A fourth lead is electrically coupled to the second load electrode, the second and third leads being arranged between the first and fourth leads.

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Номер записи: 23

27-12-2012 дата публикации

Dc/dc convertor power module package incorporating a stacked controller and construction methodology

Номер: US20120326287A1

Автор: Ashok S. Prabhu, Jaime A. Bayan, Rajeev Joshi

Принадлежит: National Semiconductor Corp

Methods and systems are described for enabling the efficient fabrication of small form factor power converters and also the small form factor power converter devices.

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Номер записи: 24

10-01-2013 дата публикации

Semiconductor device and method for manufacturing same

Номер: US20130009300A1

Автор: Hiroi Oka, Yuichi Yato

Принадлежит: Renesas Electronics Corp

A dug portion ( 50 ) in which a die-bonding material is filled is provided to a lower surface of a stamping nozzle ( 42 ) used in a step of applying the die-bonding material onto a chip mounting portion of a wiring board. Planar dimensions of the dug portion ( 50 ) are smaller than external dimensions of a chip to be mounted on the chip mounting portion. In addition, a depth of the dug portion ( 50 ) is smaller than a thickness of the chip. When the thickness of the chip is 100 μm or smaller, a problem of crawling up of the die-bonding material to an upper surface of the chip is avoided by applying the die-bonding material onto the chip mounting portion using the stamping nozzle ( 42 ).

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Номер записи: 25

28-02-2013 дата публикации

Method of processing at least one die and die arrangement

Номер: US20130049214A1

Автор: Ivan Nikitin, Joachim Mahler

Принадлежит: INFINEON TECHNOLOGIES AG

In various embodiments, a method of processing at least one die may include: forming at least one placeholder element over at least one contact pad of at least one die; forming a die embedding layer to at least partially embed the at least one die and the at least one placeholder element; removing the at least one placeholder element to form at least one opening in the at least one die embedding layer and expose the at least one contact pad of the at least one die; filling the at least one opening with electrically conductive material to electrically contact the at least one contact pad of the at least one die.

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Номер записи: 26

28-03-2013 дата публикации

Semiconductor device

Номер: US20130075786A1

Автор: Tetsuro ISHIGURO

Принадлежит: Fujitsu Ltd

A semiconductor device including a high resistance layer formed on a substrate, the high resistance layer being formed with a semiconductor material doped with an impurity element that makes the semiconductor material highly resistant; a multilayer intermediate layer formed on the high resistance layer; an electron transit layer formed with a semiconductor material on the multilayer intermediate layer; and an electron supply layer formed with a semiconductor material on the electron transit layer, wherein the multilayer intermediate layer is formed with a multilayer film in which a GaN layer and an AlN layer are alternately laminated.

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Номер записи: 27

28-03-2013 дата публикации

Power semiconductor module with wireless saw temperature sensor

Номер: US20130077222A1

Автор: Michael Sleven

Принадлежит: INFINEON TECHNOLOGIES AG

A power semiconductor module includes a housing, a base plate disposed in the housing, a plurality of substrates mounted to the base plate, a plurality of power transistor die mounted to the substrates and a plurality of terminals mounted to the substrates and protruding through the housing. The terminals are in electrical connection with the power transistor die. The power semiconductor module further includes a wireless surface acoustic wave (SAW) temperature sensor disposed in the housing of the power semiconductor module.

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Номер записи: 28

04-04-2013 дата публикации

Power semiconductor arrangement and method for producing a power semiconductor arrangement

Номер: US20130082387A1

Автор: Guido Strotmann, Karsten Guth, Thilo Stolze

Принадлежит: INFINEON TECHNOLOGIES AG

In a method for producing a power semiconductor arrangement, an insulation carrier with a top side, a metallization, and a contact pin with a first end are provided. The metallization is attached to the top side and a target section of the metallization is determined. After the metallization is attached to the top side of the insulation carrier, the first end of the contact pin is pressed into the target section such that the first end is inserted in the target section. Thereby, an interference fit and an electrical connection are established between the first end of the contact pin and the target section of the metallization.

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Номер записи: 29

11-04-2013 дата публикации

Semiconductor device having multiple bump heights and multiple bump diameters

Номер: US20130087910A1

Автор: Ramlah Binte Abdul Razak

Принадлежит: Texas Instruments Inc

A semiconductor die includes a first contact stack including a first UBM pad on a first die pad, a second contact stack including a second UBM pad on a second die pad, and a third contact stack including a third UBM pad on a third die pad. The second UBM pad perimeter is shorter than the first UBM pad perimeter, and the third UBM pad perimeter is longer than the second UBM pad perimeter. A first solder bump is on the first UBM pad, a second solder bump is on the second UBM pad, and a third solder bump is on the third UBM pad. The first solder bump, second solder bump and third solder bump all have different sizes.

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Номер записи: 30

25-04-2013 дата публикации

Light Emitting Diodes with Smooth Surface for Reflective Electrode

Номер: US20130102095A1

Автор: Chao-Kun Lin, Heng Liu

Принадлежит: Bridgelux Inc

A light emitting diode comprising an epitaxial layer structure, a first electrode, and a second electrode. The first and second electrodes are separately disposed on the epitaxial layer structure, and the epitaxial layer structure has a root-means-square (RMS) roughness less than about 3 at a surface whereon the first electrode is formed.

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Номер записи: 31

16-05-2013 дата публикации

Power Module with Current Routing

Номер: US20130119907A1

Автор: Andrea Gorgerino, Henning M. Hauenstein

Принадлежит: International Ractifier Corp

According to an exemplary embodiment, a bondwireless power module includes a common output pad coupling an emitter/anode node of a high side device to a collector/cathode node of a low side device. The bondwireless power module also includes a high side conductive clip connecting a collector of the high side device to a cathode of the high side device, and causing current to traverse through the high side conductive clip to another high side conductive clip in another power module. The bondwireless power module further includes a low side conductive clip connecting an emitter of the low side device to an anode of the low side device, and causing current to traverse through the low side conductive clip to another low side conductive clip in the another power module. The bondwireless power module can be a motor drive inverter module.

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Номер записи: 32

23-05-2013 дата публикации

Temperature compensation attenuator

Номер: US20130127513A1

Автор: Brad Nelson, Ed Franzwa, Marcus Granger-Jones

Принадлежит: RF Micro Devices Inc

In one embodiment, a temperature compensating attenuator is disclosed having an attenuation circuit and a control circuit. The temperature compensating attenuator circuit may include a first series connected attenuation circuit segment and a shunt connected attenuation circuit segment, as well as additional attenuation circuit segments. Each attenuation circuit segment includes a stack of transistors that are coupled to provide the attenuation circuit segment with an impedance attenuation level having a continuous impedance range. The control circuit may be operably associated with the stack of transistors in each attenuation circuit segment to control the attenuation level of the attenuation circuit. The temperature compensating attenuator includes a temperature compensating circuit that compensates for variations in operation of the attenuation circuit due to a temperature change.

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Номер записи: 33

23-05-2013 дата публикации

Power Converter Device

Номер: US20130128643A1

Автор: Kaname Sasaki, Kenichiro Nakajima, Shuichi Shinohara

Принадлежит: HITACHI AUTOMOTIVE SYSTEMS LTD

A power converter device includes first through third semiconductor modules provided for phases of a three-phase inverter circuit, and incorporating upper and lower arms series circuit, and a flow path forming cabinet in a rectangular prism shape having an electric equipment containing space and a coolant flow path formed to surround the electric equipment containing space, the coolant flow path includes a first flow path provided along a first side face of the flow path forming cabinet, a second flow path provided along a second side face contiguous to one side of the first side face and connected to one end of the first flow path, and a third flow path provided along a third side face contiguous to other side of the first side face and connected to other end of the first flow path.

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Номер записи: 34

30-05-2013 дата публикации

Wafer level chip scale package

Номер: US20130134502A1

Автор: Yan Xun Xue, Yueh-Se Ho

Принадлежит: ALPHA AND OMEGA SEMICONDUCTOR INC

A semiconductor device, a method of manufacturing semiconductor devices and a circuit package assembly are described. A semiconductor device can have a semiconductor substrate with first and second surfaces and a sidewall between them. First and second conductive pads on the first and second surfaces are in electrical contact with corresponding first and second semiconductor device structures in the substrate. An insulator layer on the first surface and sidewall covers a portion of the first conductive pad on the first surface. An electrically conductive layer on part of the insulator layer on the first conductive pad and sidewall is in electrical contact with the second conductive pad. The insulator layer prevents the conductive layer from making electrical contact between the first and second conductive pads.

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Номер записи: 35

30-05-2013 дата публикации

METHOD OF MANUFACTURING GaN-BASED SEMICONDUCTOR DEVICE

Номер: US20130137220A1

Автор: Hideki Matsubara, Kuniaki Ishihara

Принадлежит: Sumitomo Electric Industries Ltd

A method of manufacturing a GaN-based semiconductor device includes the steps of: preparing a composite substrate including: a support substrate having a thermal expansion coefficient at a ratio of not less than 0.8 and not more than 1.2 relative to a thermal expansion coefficient of GaN; and a GaN layer bonded to the support substrate, using an ion implantation separation method; growing at least one GaN-based semiconductor layer on the GaN layer of the composite substrate; and removing the support substrate of the composite substrate by dissolving the support substrate. Thus, the method of manufacturing a GaN-based semiconductor device is provided by which GaN-based semiconductor devices having excellent characteristics can be manufactured at a high yield ratio.

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Номер записи: 36

06-06-2013 дата публикации

UBM Structures for Wafer Level Chip Scale Packaging

Номер: US20130140706A1

Автор: Hsien-Wei Chen, Shih-Wei Liang, Tsung-Yuan Yu, Ying-Ju Chen

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A wafer level chip scale semiconductor device comprises a semiconductor die, a first under bump metal structure and a second under bump metal structure. The first under bump metal structure having a first enclosure is formed on a corner region or an edge region of the semiconductor die. A second under bump metal structure having a second enclosure is formed on an inner region of the semiconductor die. The first enclosure is greater than the second enclosure.

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Номер записи: 37

13-06-2013 дата публикации

Semiconductor device

Номер: US20130147064A1

Автор: Tomoaki Uno, Yukihiro Sato

Принадлежит: Renesas Electronics Corp

The reliability of a semiconductor device is improved. A package of a semiconductor device internally includes a first semiconductor chip and a second semiconductor chip in which power MOS•FETs are formed and a third semiconductor chip in which a control circuit controlling the first and second semiconductor chips is formed. The first to third semiconductor chips are mounted on die pads respectively. Source electrode bonding pads of the first semiconductor chip on a high side are electrically connected with a first die pad of the die pads via a metal plate. On a top surface of the die pad 7 D 2 , a plated layer formed in a region where the second semiconductor chip is mounted, and another plated layer formed in a region where the metal plate is joined are provided and the plated layers are separated each other with a region where no plated layer is formed in between.

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Номер записи: 38

11-07-2013 дата публикации

Group III-V and Group IV Composite Diode

Номер: US20130175542A1

Автор: Michael A. Briere, Tim Mcdonald

Принадлежит: International Rectifier Corp USA

In one implementation, a group III-V and group IV composite diode includes a group IV diode in a lower active die, the group IV diode having an anode situated on a bottom side of the lower active die. The group III-V and group IV composite diode also includes a group III-V transistor in an upper active die stacked over the lower active die, the group III-V transistor having a drain, a source, and a gate situated on a top side of the upper active die. The source of the group III-V transistor is electrically coupled to a cathode of the group IV diode using a through-semiconductor via (TSV) of the upper active die.

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Номер записи: 39

11-07-2013 дата публикации

Discrete power transistor package having solderless dbc to leadframe attach

Номер: US20130175704A1

Автор: Gi-young Jeun, Kang Rim Choi

Принадлежит: IXYS LLC

A packaged power transistor device includes a Direct-Bonded Copper (“DBC”) substrate. Contact pads of a first lead are attached with solderless welds to a metal layer of the DBC substrate. In a first example, the solderless welds are ultrasonic welds. In a second example, the solderless welds are laser welds. A single power transistor realized on a single semiconductor die is attached to the DBC substrate. In one example, a first bond pad of the die is wire bonded to a second lead, and a second bond pad of the die is wire bonded to a third lead. The die, the wire bonds, and the metal layer of the DBC substrate are covered with an amount of plastic encapsulant. Lead trimming is performed to separate the first, second and third leads from the remainder of a leadframe, the result being the packaged power transistor device.

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Номер записи: 40

25-07-2013 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20130187271A1

Автор: Hiromichi Watanabe, Motoaki Tani, Shinichi Sugiura, Shinya Iijima

Принадлежит: Denso Ten Ltd, Fujitsu Ltd

A semiconductor device includes a first bump that is located over a surface of a semiconductor element, and is formed on a first bump formation face distanced from a back surface of the semiconductor element at a first distance, and a second bump that is located over the surface of the semiconductor element, and is formed on a second bump formation face distanced from the back surface of the semiconductor element at a second distance being longer than the first distance, the second bump having a diameter larger than a diameter of the first bump.

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Номер записи: 41

15-08-2013 дата публикации

Power Device with Solderable Front Metal

Номер: US20130207120A1

Автор: Chuan Cheah, Michael A. Briere

Принадлежит: International Rectifier Corp USA

Some exemplary embodiments of a III-nitride power device including a HEMT with multiple interconnect metal layers and a solderable front metal structure using solder bars for external circuit connections have been disclosed. The solderable front metal structure may comprise a tri-metal such as TiNiAg, and may be configured to expose source and drain contacts of the HEMT as alternating elongated digits or bars. Additionally, a single package may integrate multiple such HEMTs wherein the front metal structures expose alternating interdigitated source and drain contacts, which may be advantageous for DC-DC power conversion circuit designs using III-nitride devices. By using solder bars for external circuit connections, lateral conduction is enabled, thereby advantageously reducing device Rdson.

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Номер записи: 42

15-08-2013 дата публикации

Complex Semiconductor Packages and Methods of Fabricating the Same

Номер: US20130207253A1

Автор: Gwi-gyeon Yang, Seung-won Lim

Принадлежит: Fairchild Korea Semiconductor Ltd

Disclosed are complex semiconductor packages, each including a large power module package which includes a small semiconductor package, and methods of manufacturing the complex semiconductor packages. An exemplary complex semiconductor package includes a first package including: a first packaging substrate; a plurality of first semiconductor chips disposed on the first packaging substrate; and a first sealing member covering the first semiconductor chips on the first packaging substrate; and at least one second package separated from the first packaging substrate, disposed in the first sealing member, and including second semiconductor chips.

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Номер записи: 43

22-08-2013 дата публикации

DC/DC Converter Power Module Package Incorporating a Stacked Controller and Construction Methodology

Номер: US20130214399A1

Автор: Ashok S. Prabhu, Jaime Bayan, Rajeev Joshi

Принадлежит: National Semiconductor Corp

Methods and systems are described for enabling the efficient fabrication of small form factor power converters and also the small form factor power converter devices.

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Номер записи: 44

22-08-2013 дата публикации

Power module and air conditioner

Номер: US20130214746A1

Автор: Masahiro Kato

Принадлежит: Mitsubishi Electric Corp

A power module is a power module having a PFC (power factor correction) function. The power module includes: IGBTs in a pair; first diodes in a pair connected to the IGBTs in a pair, the first diodes forming a reverse-conducting element; and second diodes in a pair connected to the IGBTs in a pair, the second diodes having a rectifying function. The power module further includes a driving IC that drives the IGBTs in a pair, and P terminals in a pair provided independently of each other. The P terminals are connected to one ends of the first diodes in a pair, respectively, the one ends being opposite to the other ends of the first diodes to which the IGBTs in a pair are connected.

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Номер записи: 45

12-09-2013 дата публикации

Semiconductor Packages and Methods of Forming The Same

Номер: US20130234283A1

Автор: Andrew Roberts, Martin Standing

Принадлежит: INFINEON TECHNOLOGIES AG

In one embodiment, a method of fabricating a semiconductor package includes forming a first plurality of die openings on a laminate substrate. The laminate substrate has a front side and an opposite back side. A plurality of first dies is placed within the first plurality of die openings. An integrated spacer is formed around each die of the plurality of first dies. The integrated spacer is disposed in gaps between the laminate substrate and an outer sidewall of each die of the plurality of first dies. The integrated spacer holds the die within the laminate substrate by partially extending over a portion of a top surface of each die of the plurality of first dies. Front side contacts are formed over the front side of the laminate substrate.

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Номер записи: 46

19-09-2013 дата публикации

Contact Test Structure and Method

Номер: US20130240883A1

Автор: Hsien-Wei Chen, Jie Chen, Tsung-Yuan Yu, Ying-Ju Chen

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A system and method for testing electrical connections is provided. In an embodiment one or more floating pads may be manufactured in electrical connection with an underbump metallization structure. A test may then be performed to measure the electrical characteristics of the underbump metallization structure through the floating pad in order to test for defects. Alternatively, a conductive connection may be formed on the underbump metallization and the test may be performed on the conductive connection and the underbump metallization together.

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Номер записи: 47

26-09-2013 дата публикации

Circuit package, an electronic circuit package, and methods for encapsulating an electronic circuit

Номер: US20130249069A1

Автор: Edward Fuergut, Joachim Mahler, Khalil Hosseini

Принадлежит: INFINEON TECHNOLOGIES AG

A circuit package is provided, the circuit package including: an electronic circuit; a metal block next to the electronic circuit; encapsulation material between the electronic circuit and the metal block; a first metal layer structure electrically contacted to at least one first contact on a first side of the electronic circuit; a second metal layer structure electrically contacted to at least one second contact on a second side of the electronic circuit, wherein the second side is opposite to the first side; wherein the metal block is electrically contacted to the first metal layer structure and to the second metal layer structure by means of an electrically conductive medium; and wherein the electrically conductive medium includes a material different from the material of the first and second metal layer structures or has a material structure different from the material of the first and second metal layer structures.

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Номер записи: 48

03-10-2013 дата публикации

Compound semiconductor device and method of manufacturing the same

Номер: US20130256682A1

Автор: Atsushi Yamada, Kenji Imanishi, Norikazu Nakamura, Tetsuro ISHIGURO

Принадлежит: Fujitsu Ltd

An embodiment of a method of manufacturing a compound semiconductor device includes: forming an initial layer over a substrate; forming a buffer layer over the initial layer; forming an electron transport layer and an electron supply layer over the buffer layer; and forming a gate electrode, a source electrode and a gate electrode over the electron supply layer. The forming an initial layer includes: forming a first compound semiconductor film with a flow rate ratio being a first value, the flow rate ratio being a ratio of a flow rate of a V-group element source gas to a flow rate of a III-group element source gas; and forming a second compound semiconductor film with the flow rate ratio being a second value different from the first value over the first compound semiconductor film. The method further includes forming an Fe-doped region between the buffer layer and the electron transport layer.

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Номер записи: 49

03-10-2013 дата публикации

Compound semiconductor device and method for manufacturing the same

Номер: US20130256754A1

Автор: Youichi Kamada

Принадлежит: Fujitsu Ltd

A compound semiconductor device includes: a substrate; an electron transit layer and electron supply layer formed over the substrate; a gate electrode, source electrode, and drain electrode formed over the electron supply layer; and a first Fe-doped layer provided between the substrate and the electron transit layer in a region corresponding to the position of the gate electrode in plan view, the first Fe-doped layer being doped with Fe to reduce two dimensional electron gas generated below the gate electrode.

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Номер записи: 50

03-10-2013 дата публикации

Dual Power Converter Package Using External Driver IC

Номер: US20130256859A1

Автор: Dan Clavette, Eung San Cho

Принадлежит: International Rectifier Corp USA

A dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control PET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a first plurality of contacts configured to receive control signals for each of the control PETS and each of the sync FETs from a driver integrated circuit (IC) external to the leadframe. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control PET and the second sync PET via a second clip, respectively.

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Номер записи: 51

03-10-2013 дата публикации

Monolithic Power Converter Package

Номер: US20130257524A1

Автор: Dan Clavette, Dean Fernando, Eung San Cho, Tim Philips

Принадлежит: International Rectifier Corp USA

According to an exemplary embodiment, a monolithic power converter package includes a monolithic die over a substrate, the monolithic die integrating a driver integrated circuit (IC) with a control power transistor and a sync power transistor connected in a half-bridge. A high side power input, a low side power input, and a power output of the half-bridge are each disposed on a top surface of the monolithic die. The high side power input is electrically and mechanically coupled to the substrate by a high side power strip. Also, the low side power input is electrically and mechanically coupled to the substrate by a low side power strip. Furthermore, the power output is electrically and mechanically coupled to the substrate by a power output strip.

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Номер записи: 52

14-11-2013 дата публикации

Rf power amplifier

Номер: US20130300505A1

Автор: Kenta Seki, Masao Kondo, Satoshi Sakurai, Yoshikuni Matsunaga

Принадлежит: Renesas Electronics Corp

A reduction is achieved in the primary-side input impedance of a transformer (voltage transformer) as an output matching circuit without involving a reduction in Q-factor. An RF power amplifier includes transistors, and a transformer as the output matching circuit. The transformer has a primary coil and a secondary coil which are magnetically coupled to each other. To the input terminals of the transistors, respective input signals are supplied. The primary coil is coupled to each of the output terminals of the transistors. From the secondary coil, an output signal is generated. The primary coil includes a first coil and a second coil which are coupled in parallel between the respective output terminals of the transistors, and each magnetically coupled to the secondary coil. By the parallel coupling of the first and second coils of the primary coil, the input impedance of the primary coil is reduced.

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Номер записи: 53

21-11-2013 дата публикации

Reliable Area Joints for Power Semiconductors

Номер: US20130307156A1

Автор: Reinhold Bayerer

Принадлежит: INFINEON TECHNOLOGIES AG

A power semiconductor module includes an electrically insulating substrate, copper metallization disposed on a first side of the substrate and patterned into a die attach region and a plurality of contact regions, and a semiconductor die attached to the die attach region. The die includes an active device region and one or more copper die metallization layers disposed above the active device region. The active device region is disposed closer to the copper metallization than the one or more copper die metallization layers. The copper die metallization layer spaced furthest from the active device region has a contact area extending over a majority of a side of the die facing away from the substrate. The module further includes a copper interconnect metallization connected to the contact area of the die via an aluminum-free area joint and to a first one of the contact regions of the copper metallization.

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Номер записи: 54

12-12-2013 дата публикации

Narrow active cell ie type trench gate igbt and a method for manufacturing a narrow active cell ie type trench gate igbt

Номер: US20130328105A1

Автор: Hitoshi Matsuura

Принадлежит: Renesas Electronics Corp

In an equal width active cell IE type IGBT, a wide active cell IE type IGBT, and the like, an active cell region is equal in trench width to an inactive cell region, or the trench width of the inactive cell region is narrower. Accordingly, it is relatively easy to ensure the breakdown voltage. However, with such a structure, an attempt to enhance the IE effect entails problems such as further complication of the structure. The present invention provides a narrow active cell IE type IGBT having an active cell two-dimensional thinned-out structure, and not having a substrate trench for contact.

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Номер записи: 55

19-12-2013 дата публикации

Semiconductor device and system using the same

Номер: US20130335134A1

Автор: Satoru Akiyama, Takamitsu Kanazawa

Принадлежит: Renesas Electronics Corp

There exists a possibility that a semiconductor device configured with a normally-on JFET and a normally-off MOSFET which are coupled in cascade may break by erroneous conduction, etc. A semiconductor device is configured with a normally-on SiCJFET and a normally-off Si-type MOSFET. The normally-on SiCJFET and the normally-off Si-type MOSFET are coupled in cascade and configure a switching circuit. According to one input signal, the normally-on SiCJFET and the normally-off Si-type MOSFET are controlled so as to have a period in which both transistors are set in an OFF state.

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Номер записи: 56

19-12-2013 дата публикации

Thermally Enhanced Semiconductor Package with Conductive Clip

Номер: US20130337611A1

Автор: Eung San Cho

Принадлежит: International Rectifier Corp USA

One exemplary disclosed embodiment comprises a semiconductor package including an inside pad, a transistor, and a conductive clip coupled to the inside pad and a terminal of the transistor. A top surface of the conductive clip is substantially exposed at the top of the package, and a side surface of the conductive clip is exposed at a side of the package. By supporting the semiconductor package on an outside pad during the fabrication process and by removing the outside pad during singulation, the conductive clip may be kept substantially parallel and in alignment with the package substrate while optimizing the package form factor compared to conventional packages. The exposed top surface of the conductive clip may be further attached to a heat sink for enhanced thermal dissipation.

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Номер записи: 57

26-12-2013 дата публикации

Simultaneous wafer bonding and interconnect joining

Номер: US20130341804A1

Автор: Belgacem Haba, Craig Mitchell, Ilyas Mohammed, Piyush Savalia, Vage Oganesian

Принадлежит: Tessera LLC

Disclosed are a microelectronic assembly of two elements and a method of forming same. A microelectronic element includes a major surface, and a dielectric layer and at least one bond pad exposed at the major surface. The microelectronic element may contain a plurality of active circuit elements. A first metal layer is deposited overlying the at least one bond pad and the dielectric layer. A second element having a second metal layer deposited thereon is provided, and the first metal layer is joined with the second metal layer. The assembly may be severed along dicing lanes into individual units each including a chip.

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Номер записи: 58

16-01-2014 дата публикации

Method and Apparatus for Image Sensor Packaging

Номер: US20140015084A1

Автор: Dun-Nian Yaung, Jen-Cheng Liu, Szu-Ying Chen, Tzu-Jui WANG

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Methods and apparatus for packaging a backside illuminated (BSI) image sensor or a BSI sensor device with an application specific integrated circuit (ASIC) are disclosed. A bond pad array may be formed in a bond pad area of a BSI sensor where the bond pad array comprises a plurality of bond pads electrically interconnected, wherein each bond pad of the bond pad array is of a small size which can reduce the dishing effect of a big bond pad. The plurality of bond pads of a bond pad array may be interconnected at the same layer of the pad or at a different metal layer. The BSI sensor may be bonded to an ASIC in a face-to-face fashion where the bond pad arrays are aligned and bonded together.

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Номер записи: 59

23-01-2014 дата публикации

Method of Manufacturing a Semiconductor Device with a Carrier Having a Cavity and Semiconductor Device

Номер: US20140021634A1

Автор: Ivan Nikitin, Joachim Mahler

Принадлежит: INFINEON TECHNOLOGIES AG

A method includes providing a carrier having a first cavity, providing a dielectric foil with a metal layer attached to the dielectric foil, placing a first semiconductor chip in the first cavity of the carrier, and applying the dielectric foil to the carrier.

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Номер записи: 60

13-02-2014 дата публикации

Trench-based power semiconductor devices with increased breakdown voltage characteristics

Номер: US20140042532A1

Автор: Ashok Challa, Daniel Calafut, Daniel M. Kinzer, Dean E. Probst, Joseph A. Yedinak

Принадлежит: Fairchild Semiconductor Corp

Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

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Номер записи: 61

13-02-2014 дата публикации

Power MOSFET Having Selectively Silvered Pads for Clip and Bond Wire Attach

Номер: US20140042624A1

Автор: Nathan Zommer

Принадлежит: IXYS LLC

A packaged power field effect transistor device includes a power field effect transistor die, a DBA substrate, a clip, a wire bond, leads, and an amount of plastic encapsulant. The top of the DBA has a plurality of metal plate islands. A sintered silver feature is disposed on one of the islands. A silvered backside of the die is directly bonded to the sintered silver structure of the DBA. The upper surface of the die includes a first aluminum pad (a source pad) and a second aluminum pad (a gate pad). A sintered silver structure is disposed on the first aluminum pad, but there is no sintered silver structure disposed on the second aluminum pad. A high current clip is attached via soft solder to the sintered silver structure on the first aluminum pad (the source pad). A bond wire is ultrasonically welded to the second aluminum pad (gate pad).

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Номер записи: 62

06-03-2014 дата публикации

Electronic device and semiconductor device

Номер: US20140061821A1

Автор: Hiroyuki Nakamura, Kenya Kawano, Yukihiro Sato

Принадлежит: Renesas Electronics Corp

Provided is an electronic device having a semiconductor device and a mounting board. The semiconductor device has a die pad, a semiconductor chip on the die pad, a coupling member coupling the die pad to the semiconductor chip, and a semiconductor package member covering the upper portion of the semiconductor chip and the side surface of the die pad. In this semiconductor device, the plane area of the coupling member coupling the mounting board to the die pad is smaller than the plane area of the lower surface of the die pad exposed from the semiconductor package material. This makes it possible to reduce separation between the die pad and the semiconductor chip resulting from cracks, due to temperature cycling, of the coupling member present between the die pad and the semiconductor chip.

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Номер записи: 63

06-03-2014 дата публикации

Stacked die power converter

Номер: US20140061884A1

Автор: Alok Lohia, Brian A. CARPENTER, Christopher Sanzo, Matthew D. Romig, William T. Harrison

Принадлежит: Texas Instruments Inc

A stacked die power converter package includes a lead frame including a die pad and a plurality of package pins, a first die including a first power transistor switch (first power transistor) attached to the die pad, and a first metal clip attached to one side of the first die. The first metal clip is coupled to at least one package pin. A second die including a second power transistor switch (second power transistor) is attached to another side on the first metal clip. A controller is provided by a controller die attached to a non-conductive layer on the second metal clip on one side of the second die.

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Номер записи: 64

13-03-2014 дата публикации

Semiconductor device and method of detecting wire open failure thereof

Номер: US20140070839A1

Автор: Shigemi Miyazawa

Принадлежит: Fuji Electric Co Ltd

In a semiconductor device, two series connections are arranged to be connected between respective split emitter electrodes and a gate electrode with Zener diode units connected in series to respective resistors, with the cathode sides thereof directed to the gate electrode side. The numbers of the Zener diodes in the Zener diode units in the respective series connections are different between the respective Zener diode units. Thus, a semiconductor device can be provided which is capable of detecting an open failure of a bonding wire regardless of the number of a plurality of the bonding wires connected in parallel, by a simple electrical test to make it possible to reliably sort out a semiconductor device with a wire open failure at an early stage.

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Номер записи: 65

27-03-2014 дата публикации

Semiconductor Device Having a Clip Contact

Номер: US20140084433A1

Автор: Josef Hoeglauer, Khalil Hosseini, Ralf Otremba

Принадлежит: INFINEON TECHNOLOGIES AG

A semiconductor device comprises a carrier. Further, the semiconductor devices comprises a semiconductor chip comprising a first main surface and a second main surface opposite to the first main surface, wherein a first electrode is arranged on the first main surface and the semiconductor chip is mounted on the carrier with the second main surface facing the carrier. Further, an encapsulation body embedding the semiconductor chip is provided. The semiconductor device further comprises a contact clip, wherein the contact clip is an integral part having a bond portion bonded to the first electrode and having a terminal portion forming an external terminal of the semiconductor device.

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Номер записи: 66

03-04-2014 дата публикации

Solid-state image pickup element and solid-state image pickup element mounting structure

Номер: US20140091421A1

Автор: Hisanori Suzuki, Masaharu Muramatsu, Tomohiro Ikeya, Toshiyuki Fukui

Принадлежит: Hamamatsu Photonics KK

A solid-state image pickup element is provided with a semiconductor substrate having a photosensitive region, a plurality of first electrode pads arrayed on a principal face of the semiconductor substrate, a plurality of second electrode pads arrayed in a direction along a direction in which the plurality of first electrode pads are arrayed, on the principal face of the semiconductor substrate, and a plurality of interconnections connecting the plurality of first electrode pads and the plurality of second electrode pads in one-to-one correspondence. The plurality of interconnections connect the first and second electrode pads so that each interconnection connects the first electrode pad and the second electrode pad in a positional relation of line symmetry with respect to a center line perpendicular to the array directions of the plurality of first and second electrode pads.

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Номер записи: 67

01-01-2015 дата публикации

Semiconductor device

Номер: US20150001688A1

Автор: Kenichi Iguchi

Принадлежит: Fuji Electric Co Ltd

A groove for air ventilation is formed in a rib with a substantially rectangular ring shape which is provided so as to surround a concave portion provided in a rear surface of a semiconductor chip. The groove is provided in each side or at each corner of the rib so as to traverse the rib from the inner circumference to the outer circumference of the rib. The depth of the groove is equal to or less than the depth of the concave portion provided in the rear surface of the chip. In this way, it is possible to reliably solder a semiconductor device, in which the concave portion is provided in the rear surface of the semiconductor chip and the rib is provided in the outer circumference of the concave portion, to a base substrate, without generating a void in a drain electrode provided in the concave portion.

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Номер записи: 68

01-01-2015 дата публикации

Semiconductor package

Номер: US20150001695A1

Автор: Francois Hebert

Принадлежит: MagnaChip Semiconductor Ltd

Provided are a semiconductor die and a semiconductor package. The semiconductor package includes: a monolithic die; a driving circuit, a low-side output power device, and a high-side output power device disposed in the monolithic die; and an upper electrode and a lower electrode disposed above and below the monolithic die.

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Номер записи: 69

01-01-2015 дата публикации

Semiconductor device

Номер: US20150001699A1

Автор: Katsuhiko Funatsu, Tomoaki Uno, Yuichi Yato, Yukihiro Sato

Принадлежит: Renesas Electronics Corp

A semiconductor device includes a first chip mounting portion, a first semiconductor chip arranged over the first chip mounting portion, a first pad formed in a surface of the first semiconductor chip, a first lead which serves as an external coupling terminal, a first conductive member which electrically couples the first pad and the first lead, and a sealing body which seals a part of the first chip mounting portion, the first semiconductor chip, a part of the first lead, and the first conductive member. The first conductive member includes a first plate-like portion, and a first support portion formed integrally with the first plate-like portion. An end of the first support portion is exposed from the sealing body, and the first support portion is formed with a first bent portion.

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Номер записи: 70

01-01-2015 дата публикации

Power semiconductor module

Номер: US20150001726A1

Автор: Baik-Woo Lee, Seong-Woon Booh

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A power semiconductor module includes a first power device on a substrate, a first electrode on an upper surface of the first power device, a first nickel plating layer on the first electrode, and a copper wire connected to the first nickel plating layer.

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Номер записи: 71

06-01-2022 дата публикации

Semiconductor device

Номер: US20220005753A1

Автор: Atsushi Yamaguchi, Hiroyuki SAKAIRI, Takukazu Otsuka

Принадлежит: ROHM CO LTD

Semiconductor device A1 includes: first terminal 201A and second terminal 201B; first switching element 1A including first gate electrode 12A, first source electrode 13A and first drain electrode 14A; and second switching element 1B including second gate electrode 12B, second source electrode 13B and second drain electrode 14B. First switching element 1A and second switching element 1B are connected in series to each other between first terminal 201A and second terminal 201B. Semiconductor device A1 includes first capacitor 3A connected in parallel to first switching element 1A and second switching element 1B between first terminal 201A and second terminal 201B. First switching element 1A and second switching element 1B are aligned in y direction. First capacitor 3A overlaps with at least one of first switching element 1A and second switching element 1B as viewed in z direction. These arrangements serve to suppress surge voltage.

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Номер записи: 72

06-01-2022 дата публикации

STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD FOR BONDING TWO SUBSTRATES

Номер: US20220005775A1

Автор: Chen Hui-Ling, Hsu Chien En, Kuo Chung-hsing, Lin Ming-Tse, Sheng Zhirui, YEH Chun-Ting

Принадлежит: UNITED MICROELECTRONICS CORP.

A structure of semiconductor device is provided, including a first circuit structure, formed on a first substrate. A first test pad is disposed on the first substrate. A second circuit structure is formed on a second substrate. A second test pad is disposed on the second substrate. A first bonding pad of the first circuit structure is bonded to a second bonding pad of the second circuit structure. One of the first test pad and the second test pad is an inner pad while another one of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad. 1. A structure of semiconductor device , comprising:a first circuit structure, formed on a first substrate;a first test pad, disposed on the first substrate;a second circuit structure, formed on a second substrate; anda second test pad, disposed on the second substrate,wherein a first bonding pad of the first circuit structure is bonded to a second bonding pad of the second circuit structure, wherein one of the first test pad and the second test pad is an inner pad while another one of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad.2. The structure of semiconductor device as recited in claim 1 , further comprising:a first leading circuit, disposed on the first substrate to connect to the first test pad; anda second leading circuit, disposed on the second substrate to connect to the second test pad.3. The structure of semiconductor device as recited in claim 2 , wherein the first leading circuit and the second leading circuit respectively provide test terminals in use for test.4. The structure of semiconductor device as recited in claim 2 , wherein the inner pad includes at least one pad and the outer pad includes a ring pad.5. The structure of semiconductor device as recited in claim 4 , wherein the at least one pad includes a round pad claim 4 , a rectangle pad claim 4 , a triangle pad claim 4 , a square pad claim 4 , or a ...

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Номер записи: 73

13-01-2022 дата публикации

Display panel and manufacturing method for same

Номер: US20220013517A1

Автор: Chan-Jae Park, Hyun a Lee, Kikyung YOUK, Sangduk Lee, Soo Yeon Han, Sunok Oh

Принадлежит: Samsung Display Co Ltd

A display panel having a display region and a non-display region, the display panel includes: a substrate having at least one first opening; an electronic component disposed on the substrate; a plurality of pads disposed in the non-display region and including a first pad and a second pad are spaced apart from each other in a first direction with the at least one first opening therebetween; and an adhesive layer disposed between the substrate and the electronic component and overlapping the at least one first opening.

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Номер записи: 74

07-01-2021 дата публикации

Lead frame assembly for a semiconductor device

Номер: US20210005538A1

Автор: Adam Richard Brown, Dave Anderson, Ricardo Lagmay Yandoc

Принадлежит: Nexperia BV

This disclosure relates to a lead frame assembly for a semiconductor device, a semiconductor device and an associated method of manufacture. The lead frame assembly includes a die attach structure and a clip frame structure. The clip frame structure includes a die connection portion configured to contact a contact terminal on a top side of the semiconductor die; and a continuous lead portion extending along the die connection portion. The continuous lead portion is integrally formed with the die connection portion.

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Номер записи: 75

07-01-2021 дата публикации

Multi-Stacked Package-on-Package Structures

Номер: US20210005556A1

Автор: An-Jhih Su, Chen-Hua Yu, Chi-Hsi Wu, Der-Chyang Yeh, Ming Shih Yeh, Wei-Cheng Wu

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the first die having a different function from each of the plurality of second dies; attaching a passive device over the first die; encapsulating the first die, the plurality of second dies, and the passive device; and forming a first redistribution structure over the passive device, the first die, and the plurality of second dies, the passive device connecting the first die to the first redistribution structure.

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Номер записи: 76

07-01-2021 дата публикации

Semiconductor Device and Method of Manufacturing

Номер: US20210005561A1

Автор: Chen Ming-Fa, Hu Chih-Chia, Jan Sen-Bor, Yeh Sung-Feng, Yuan Ching-Pin

Принадлежит:

A semiconductor device including a first die and a second die bonded to one another. The first die includes a first passivation layer over a substrate, and first bond pads in the first passivation layer. The second die includes a second passivation layer, which may be bonded to the first passivation layer, and second bond pads in the second passivation layer, which may be bonded to the first bond pads. The second bond pads include inner bond pads and outer bond pads. The outer bond pads may have a greater diameter than the inner bond pads as well as the first bond pads. 1. A semiconductor device , comprising: a first passivation layer disposed over a first substrate; and', 'first bond pads disposed in the first passivation layer; and, 'a first die, comprising a second passivation layer, the second passivation layer being bonded to the first passivation layer; and', 'second bond pads disposed in the second passivation layer, each of the second bond pads being bonded to one of the first bond pads, the second bond pads comprising inner bond pads and outer bond pads, the outer bond pads having a greater diameter than the inner bond pads., 'a second die, comprising2. The semiconductor device of further comprising third bond pads disposed in the second passivation layer claim 1 , wherein the third bond pads are closer than the outer bond pads to an outer edge of the second passivation layer claim 1 , and wherein the third bond pads have a greater diameter than the outer bond pads.3. The semiconductor device of claim 1 , wherein:a center of one of the first bond pads is located a first distance from a center of the first passivation layer, the one of the first bond pads having a first diameter;a center of one of the second bond pads is located a second distance from a center of the second passivation layer, the one of the second bond pads being bonded to the one of the first bond pads, the one of the second bond pads having a second diameter; andthe second distance being ...

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Номер записи: 77

07-01-2021 дата публикации

DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME, DISPLAY DEVICE

Номер: US20210005632A1

Автор: FANG Song, HUANG HUA, LI Shulei, MAI Hsuanwei

Принадлежит:

The present disclosure provides a display substrate and a method of manufacturing the same, and a display device. The display substrate includes a base substrate; a driving circuit layer disposed on the base substrate; and a planarization layer disposed on a side of the driving circuit layer away from the base substrate and having a plurality of conductive pads therein, the plurality of conductive pads are respectively electrically coupled to electrodes in the driving circuit layer, and a surface of each of the plurality of conductive pads away from the base substrate is flush with a surface of the planarization layer away from the base substrate. 1. A display substrate , comprising:a base substrate;a driving circuit layer located on the base substrate; anda planarization layer located on a side of the driving circuit layer away from the base substrate,wherein the planarization layer has a plurality of conductive pads therein, and a surface of each of the plurality of conductive pads away from the base substrate is flush with a surface of the planarization layer away from the base substrate, andwherein the plurality of conductive pads are electrically coupled to electrodes in the driving circuit layer respectively.2. The display substrate of claim 1 , wherein a material of the planarization layer is photoresist.3. The display substrate of claim 2 , wherein a height tolerance d1 of the surface of the planarization layer away from the base substrate is in a range from −1 μm to 1 μm.4. The display substrate of claim 1 , wherein a height tolerance of a surface of the driving circuit layer away from the base substrate is d2 claim 1 , and a thickness D of the planarization layer in a direction perpendicular to a surface of the base substrate satisfies: |2.5*d2|≤D≤|4*d2|.5. The display substrate of claim 3 , wherein a height tolerance of a surface of the driving circuit layer away from the base substrate is d2 claim 3 , and a thickness D of the planarization layer in a ...

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Номер записи: 78

02-01-2020 дата публикации

BOND PADS FOR LOW TEMPERATURE HYBRID BONDING

Номер: US20200006280A1

Автор: Bhagavat Milind S., Shah Priyal

Принадлежит:

Various chip stacks and methods and structures of interconnecting the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip that has a first glass layer and plural first groups of plural conductor pads in the first glass layer. Each of the plural first groups of conductor pads is configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a plurality interconnects that connect the first semiconductor chip to the second semiconductor chip. The first glass layer is configured to bond to a second glass layer of the second semiconductor chip. 1. An apparatus , comprising:a first semiconductor chip having a first glass layer and plural first groups of plural conductor pads in the first glass layer, each of the plural first groups of conductor pads including a main conductor pad and one or more dummy pads adjacent the main conductor pad and being configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a plurality of interconnects that connect the first semiconductor chip to the second semiconductor chip; andthe first glass layer being configured to bond to a second glass layer of the second semiconductor chip.2. The apparatus of claim 1 , wherein each of the first groups comprises a main conductor pad and plural dummy pads circumferentially arranged around the main conductor pad.3. The apparatus of claim 1 , comprising the second semiconductor chip mounted on the first semiconductor chip and electrically connected thereto by the plurality of interconnects.4. An apparatus claim 1 , comprising:a first semiconductor chip having a first glass layer and plural first conductor pads in the first glass layer, each of the plural first conductor pads including a base layer and a bonding layer on the base layer, the base layer having a greater ...

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Номер записи: 79

02-01-2020 дата публикации

Semiconductor Device and Power Conversion Apparatus

Номер: US20200006301A1

Автор: FURUKAWA Tomoyasu, Morita Toshiaki, Shiraishi Masaki

Принадлежит:

Provided is a semiconductor device in which, in a case where a metallic plate (a conductive member) is bonded by being sintered to a semiconductor chip having an IGBT gate structure, an excess stress is less likely to be generated in a gate wiring section of the semiconductor chip even when pressure is applied in a sinter bonding process, so that a characteristic failure is reduced. The semiconductor device according to the present invention is characterized by: being provided with a semiconductor chip having a gate structure represented by an IGBT; including first gate wiring and second gate wiring formed on the surface of the semiconductor chip; and including an emitter electrode disposed so as to cover the first gate wiring and a sintered layer disposed above the emitter electrode, wherein a multilayer structure formed by including at least the emitter electrode and the sintered layer on the surface of the semiconductor chip continuously exists over a range including an emitter electrode connecting contact and gate wiring regions. 110.-. (canceled)11. A semiconductor device comprising:a semiconductor chip;a first gate wiring and a second gate wiring formed on a front surface of the semiconductor chip;an emitter electrode arranged so as to cover the first gate wiring; anda sintered layer arranged above the emitter electrode,wherein a multilayer structure consisting of at least the emitter electrode and the sintered layer is continuously present over a range including an emitter electrode connecting contact and a gate wiring region on the front surface of the semiconductor chip.12. The semiconductor device according to claim 11 , whereinthe semiconductor chip is joined to a collector wiring on a common ceramic substrate together with a diode chip by another sintered layer separated from the sintered layer.13. The semiconductor device according to claim 11 , whereinthe multilayer structure is configured to include an electrode layer, which contains nickel (Ni) as a ...

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Номер записи: 80

03-01-2019 дата публикации

METHOD TO IMPROVE CMP SCRATCH RESISTANCE FOR NON PLANAR SURFACES

Номер: US20190006299A1

Автор: Burnett Andrew Frank, Davis Jonathan Philip, Zinn Brian Edward

Принадлежит:

An electronic device is formed by providing a substrate having a recess at a top surface. A layer of an organic protective material is formed over the substrate, with the organic protective material extending into the recess. A polishing process is performed on the layer of protective material. The polishing process may remove a portion of an underlying metal layer over the top surface while protecting the underlying metal layer within the recess. 1. A method of forming an electronic device , comprising:providing a substrate having a recess in a top surface of the substrate;forming a layer of an organic protective material over the substrate, the layer of organic protective material extending into the recess and covering the top surface;performing a polishing process on the layer of protective material.2. The method of claim 1 , wherein the layer of protective material comprises photoresist.3. The method of claim 1 , wherein the layer of protective material comprises a resin.4. The method of claim 1 , wherein the layer of protective material comprises polymer.5. The method of claim 1 , wherein the layer of protective material comprises a material mixed with a solvent.6. The method of claim 5 , wherein the layer of protective material is treated to remove solvent.7. The method of claim 1 , wherein forming a layer of an organic protective material includes spin-coating the organic protective material onto the top surface.8. The method of claim 1 , wherein the top surface of the substrate comprises a dielectric material.9. The method of claim 1 , wherein the polishing processes comprises chemical-mechanical polishing.10. The method of claim 1 , wherein a metal layer is located over the substrate surface and within the recess prior to forming a layer of an organic protective material over the substrate claim 1 , and the polishing process removes the metal layer from over the top surface and leaves a remaining portion of the metal layer within the recess.11. The method ...

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Номер записи: 81

03-01-2019 дата публикации

SEMICONDUCTOR CHIP

Номер: US20190006306A1

Автор: KUROKAWA Atsushi, Shibata Masahiro, TOKUDA Daisuke, TOKUYA Hiroaki, UMEMOTO Yasunari

Принадлежит: MURATA MANUFACTURING CO., LTD.

A semiconductor chip includes a semiconductor substrate having a main surface, first and second electrodes, a first insulating layer, and first and second bumps. The first and second electrodes are formed above the main surface of the semiconductor substrate. The first insulating layer is formed above a first portion of the first electrode. The first bump is formed above a second portion of the first electrode and above the first insulating layer and is electrically connected to the first electrode. The second bump is formed above the second electrode. The area of the second bump is larger than that of the first bump in a plan view of the main surface of the semiconductor substrate. The first insulating layer adjusts the distance from the main surface of the semiconductor substrate to the top surface of the first bump in a direction normal to the main surface. 1. A semiconductor chip comprising:a semiconductor substrate having a main surface;a first electrode formed above the main surface of the semiconductor substrate;a second electrode formed above the main surface of the semiconductor substrate;a first insulating layer formed above a first portion of the first electrode;a first bump that is formed above a second portion of the first electrode and above the first insulating layer, and that is electrically connected to the first electrode; anda second bump formed above the second electrode, an area of the second bump being larger than an area of the first bump in a plan view of the main surface of the semiconductor substrate,wherein a level on which the first bump is formed is higher than a level on which the second bump is formed.2. The semiconductor chip according to claim 1 , wherein a longest distance from the main surface of the semiconductor substrate to a top surface of the first bump in a direction normal to the main surface of the semiconductor substrate is substantially equal to a longest distance from the main surface of the semiconductor substrate to a ...

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Номер записи: 82

03-01-2019 дата публикации

Mounting component, semiconductor device using same, and manufacturing method thereof

Номер: US20190006310A1

Автор: Masatoshi Nakagaki

Принадлежит: Nichia Corp

A mounting component includes a main body and a metal layer. The main body has a first main surface and a second main surface. The metal layer is arranged on the first main sur face of the main body. The metal layer includes at least one concave recognition mark having an inclined surface that is inclined with respect to a main surface of the metal layer.

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Номер записи: 83

03-01-2019 дата публикации

Heterojunction Semiconductor Device for Reducing Parasitic Capacitance

Номер: US20190006504A1

Автор: Chen Shih-Peng, LIAO Wen-Chia, Lin Li-Fan, Shiue Ching-Chuan, YANG Chun-Chieh

Принадлежит:

A semiconductor device including an active layer made of III-V group semiconductors, a source electrode and a drain electrode disposed on the active layer, a gate electrode disposed on or above the active layer and between the source electrode and the drain electrode, an interlayer dielectric covering the source electrode, the drain electrode, and the gate electrode and having a plurality of inter-gate via holes. The semiconductor device further includes an inter-source layer, an inter-drain layer, and an inter-gate layer disposed on the interlayer dielectric. The semiconductor device further includes an inter-gate plug filled in the inter-gate via hole and electrically connected to the gate electrode and the inter-gate layer, and a gate field plate being separated from the gate electrode and electrically connected to the gate electrode through the inter-gate layer. 1. A semiconductor device , comprising:an active layer made of III-V group semiconductor materials;a source electrode disposed on the active layer;a drain electrode disposed on the active layer;a gate electrode disposed above the active layer and between the source electrode and the drain electrode;a gate field plate disposed above the active layer;an interlayer dielectric covering the source electrode, the drain electrode, the gate field plate, and the gate electrode, the interlayer dielectric having a plurality of inter-gate via holes;an inter-source layer disposed on the interlayer dielectric and electrically connected to the source electrode;an inter-drain layer disposed on the interlayer dielectric and electrically connected to the drain electrode;an inter-gate layer disposed on the interlayer dielectric, wherein the gate field plate is separated from the gate electrode and electrically connected to the gate electrode through the inter-gate layer; anda plurality of inter-gate plugs filled into the inter-gate via holes;wherein at least one of the inter-gate via holes positioned on the gate field ...

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Номер записи: 84

08-01-2015 дата публикации

III-Nitride Device and FET in a Package

Номер: US20150008445A1

Автор: Alberto Guerra, Heny Lin, Jason Zhang

Принадлежит: International Rectifier Corp USA

One exemplary disclosed embodiment comprises a three-terminal stacked-die package including a field effect transistor (PET), such as a silicon PET, stacked atop a III-nitride transistor, such that a drain of the PET resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a gate of the FET, a second terminal of the package is coupled to a drain of the III-nitride transistor. A third terminal of the package is coupled to a source of the FET. In this manner, devices such as cascoded switches may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.

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Номер записи: 85

27-01-2022 дата публикации

Semiconductor module

Номер: US20220028761A1

Автор: Takafumi Yamada, Toru Yamada

Принадлежит: Fuji Electric Co Ltd

A semiconductor module includes a semiconductor device having a gate runner extending in a first direction at an upper surface of the semiconductor device, and a metal wiring plate having a first bonding portion with a bonding surface to which the upper surface of the semiconductor device is bonded via a first bonding material. The first bonding portion has a plurality of first protrusions at the bonding surface. Each first protrusion protrudes toward the semiconductor device, and is provided in a position away from the gate runner by a first distance in a plan view of the semiconductor module.

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Номер записи: 86

12-01-2017 дата публикации

Chip package and manufacturing method thereof

Номер: US20170012081A1

Автор: Chia-Lun SHEN, Hsiao-Lan Yeh, Yen-Shih Ho, Yi-Ming Chang

Принадлежит: XinTec Inc

A manufacturing method of a chip package includes the following steps. A patterned solder paste layer is printed on a patterned conductive layer of a wafer. Plural solder balls are disposed on the solder paste layer that is on a first portion of the conductive layer. A reflow process is performed on the solder balls and the solder paste layer. A flux layer converted from a surface of the solder paste layer is cleaned.

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Номер записи: 87

10-01-2019 дата публикации

NON-DESTRUCTIVE TESTING OF INTEGRATED CIRCUIT CHIPS

Номер: US20190013251A1

Автор: Abraham David W., Cotte John M.

Принадлежит:

Semiconductor devices and electronics packaging methods include integrated circuit chips having redundant signal bond pads along with signal bond pads connected to the same signal port for non-destructive testing of the integrated circuit chips prior to packaging. Electrical testing is made via the redundant signal bond after which qualified integrated circuit chips can be attached to a pristine and bumped final interposer or printed circuit board to provide increased reliability to the assembled electronic package. 110-. (canceled)12. The integrated circuit chip of claim 11 , wherein the at least one redundant signal bond pad and the at least one final signal bond pad are different sizes.13. The integrated circuit chip of claim 11 , wherein the test fixture comprises a probe and the at least one redundant signal bond pad has square-shape claim 11 , circular-shape claim 11 , or asymmetrical shape.14. The integrated circuit chip of claim 11 , wherein the at least one redundant signal bond pad and the at least one signal bond pad on the chip are formed of a superconducting material.15. The integrated circuit chip of claim 11 , wherein the test fixture comprises a probe and the at least one redundant signal bond pad is located such that the probe does not has square-shape claim 11 , circular-shape claim 11 , or asymmetrical shape.1619-. (canceled)20. A semiconductor device comprising:an integrated circuit chip comprising a first signal bond pad and a second signal bond pad connected to the same signal port, wherein the first signal bond pad has a greater lateral width than the second signal bond pad and is configured for testing the chip prior to packaging, and wherein the second signal bond pad is configured for packaging with an interposer or a printed circuit board.21. The semiconductor device of claim 20 , wherein the first signal bond pad and the second signal bond pad are of different sizes.22. The semiconductor device of claim 20 , wherein the first signal bond ...

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Номер записи: 88

10-01-2019 дата публикации

NON-DESTRUCTIVE TESTING OF INTEGRATED CIRCUIT CHIPS

Номер: US20190013252A1

Автор: Abraham David W., Cotte John M.

Принадлежит:

Semiconductor devices and electronics packaging methods include integrated circuit chips having redundant signal bond pads along with signal bond pads connected to the same signal port for non-destructive testing of the integrated circuit chips prior to packaging. Electrical testing is made via the redundant signal bond after which qualified integrated circuit chips can be attached to a pristine and bumped final interposer or printed circuit board to provide increased reliability to the assembled electronic package. 1. A method of testing an integrated circuit chip , the method comprising:fabricating an integrated circuit chip comprising at least one redundant signal bond pad and at least one final signal bond pad, wherein the at least one redundant signal bond pad and at the least one final signal bond pad are connected to the same signal port;contacting the at least one redundant signal bond pad to a test fixture in electrical communication with electrical evaluation equipment; andelectrically testing the chip with the electrical evaluation equipment.2. The method of further comprising selecting out qualified ones of the integrated circuit chips; and coupling the at least one final signal bond pad of the qualified ones to a final interposer or printed circuit board claim 1 , wherein the final signal bond pad is pristine and has not been previously bonded to a bump or reworked.3. The method of claim 1 , wherein the test fixture comprises a probe.4. The method of claim 1 , wherein the test fixture comprises a wirebond.5. The method of claim 1 , wherein the test fixture comprises a test interposer comprising a test socket coupled to an electrical conductive pad claim 1 , wherein a solder bump is formed on the electrically conductive pad and configured to contact the at least one redundant signal bond pad claim 1 , wherein the test socket is in electrical communication with electrical evaluation equipment.6. The method of claim 2 , wherein selecting out the qualified ...

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Номер записи: 89

10-01-2019 дата публикации

Electronic component device

Номер: US20190013262A1

Автор: Yukinori Hatori

Принадлежит: Shinko Electric Industries Co Ltd

An electronic component device includes a first lead frame having a first connection terminal and an electronic component. The first connection terminal includes a first metal electrode, a first pad part formed on an upper surface of the first metal electrode and formed by a metal plated layer, and a first metal oxide layer formed on an upper surface of the first metal electrode in a surrounding region of the first pad part so as to surround an outer periphery of the first pad part. The electronic component has a first terminal part provided on its lower surface. The first terminal part of the electronic component is connected to the first pad part of the first connection terminal via a metal joining material.

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Номер записи: 90

14-01-2021 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

Номер: US20210013144A1

Автор: Ryu Ji Yeon, SHIM Jae Beom

Принадлежит: Amkor Technology Singapore Holding Pte. Ltd.

In one example, a semiconductor device comprises a substrate comprising a dielectric, a first conductor on a top side of the dielectric, and a second conductor on a bottom side of the dielectric, wherein the dielectric has an aperture, and the first conductor comprises a partial via contacting a pad of the second conductor through the aperture, an electronic device having an interconnect electrically coupled to the first conductor, and an encapsulant on a top side of the substrate contacting a side of the electronic device. Other examples and related methods are also disclosed herein. 1. A semiconductor device , comprising:a substrate comprising a dielectric, a first conductor on a top side of the dielectric, and a second conductor on a bottom side of the dielectric, wherein the dielectric has an aperture, and the first conductor comprises a partial via contacting a pad of the second conductor through the aperture;an electronic device having an interconnect electrically coupled to the first conductor; andan encapsulant on a top side of the substrate contacting a side of the electronic device.2. The semiconductor device of claim 1 , wherein the substrate comprises a third conductor on the top side of the dielectric claim 1 , and a fourth conductor on the bottom side of the dielectric claim 1 , wherein the dielectric has an additional aperture claim 1 , and the third conductor comprises a partial via contacting a pad of the fourth conductor through the additional aperture.3. The semiconductor device of claim 2 , further comprising a trace on the dielectric between the partial via of the first conductor and the partial via of the third conductor.4. The semiconductor device of claim 2 , wherein an end of the partial vial of the first conductor and an end of the partial via of the third conductor are spaced apart by 30 microns or less.5. The semiconductor device of claim 2 , wherein:the first conductor comprises a first trace on the top side of the dielectric and ...

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Номер записи: 91

09-01-2020 дата публикации

Semiconductor power device including wire or ribbon bonds over device active region

Номер: US20200013692A1

Автор: Gabriele Formicone

Принадлежит: Integra Technologies Inc

A semiconductor power device including a base plate; an input lead; an output lead; a field effect transistor (FET) power die disposed over the base plate, wherein the FET power die includes a set of source fingers, a set of drain fingers, and a set of gate fingers disposed directly over an active region, wherein the gate fingers are configured to receive an input signal from the input lead, and wherein the FET power die is configured to process the input signal to generate an output signal at the drain fingers for routing to the output lead; and electrical conductors (wirebonds or ribbons) bonded to the source and/or drain directly over the active region of the FET power die. The electrical conductors produce additional thermal paths between the active region and the base plate for thermal management of the FET power die.

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Номер записи: 92

09-01-2020 дата публикации

CHIP PARTS AND METHOD FOR MANUFACTURING THE SAME, CIRCUIT ASSEMBLY HAVING THE CHIP PARTS AND ELECTRONIC DEVICE

Номер: US20200013737A1

Автор: Yamamoto Hiroki

Принадлежит: ROHM CO., LTD.

A chip part according to the present invention includes a substrate having a penetrating hole, a pair of electrodes formed on a front surface of the substrate and including one electrode overlapping the penetrating hole in a plan view and another electrode facing the one electrode, and an element formed on the front surface side of the substrate and electrically connected to the pair of electrodes. 1. A bidirectional Zener diode chip , comprising:a semiconductor substrate of a first conductivity type;an insulating film which covers a front surface of the semiconductor substrate;a first diffusion region of a second conductivity type formed in the semiconductor substrate and exposed at the front surface of the semiconductor substrate;a second diffusion region of the second conductivity type formed in the semiconductor substrate across an interval from the first diffusion region and exposed at the front surface of the semiconductor substrate;contact holes in the insulating film for selectively exposing the first diffusion region and the second diffusion region through the insulating film;a first electrode formed on the front surface of the semiconductor substrate and connected to the first diffusion region; anda second electrode formed on the front surface of the semiconductor substrate and connected to the second diffusion region,wherein the first electrode includes a plurality of first extraction electrodes which are defined to cover the first diffusion region,wherein the second electrode includes a plurality of second extraction electrodes which are defined to cover the second diffusion region along the second extraction electrodes extending parallel to the first extraction electrodes in a lengthwise direction as viewed from a plan view,wherein the plurality of first extraction electrodes and the plurality of second extraction electrodes are defined in a comb-toothed shape engaging with each other,wherein a shape of the contact holes is an elongated shape in the ...

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Номер записи: 93

09-01-2020 дата публикации

DUAL BOND PAD STRUCTURE FOR PHOTONICS

Номер: US20200014171A1

Автор: Gambino Jeffrey P., Graf Richard S., LEIDY Robert K., MALING Jeffrey C.

Принадлежит:

A dual bond pad structure for a wafer with laser die attachment and methods of manufacture are disclosed. The method includes forming a bonding layer on a surface of a substrate. The method further includes forming solder bumps on the bonding layer. The method further includes patterning the bonding layer to form bonding pads some of which comprise the solder bumps thereon. The method further includes attaching a laser diode to selected bonding pads using solder connections formed on the laser diode. The method further includes attaching an interposer substrate to the solder bumps formed on the bonding pads. 1. A method , comprising:forming a masking layer over a bonding layer;patterning the bonding layer to form bonding pads;attaching a laser diode to selected bonding pads using solder connections formed on the laser diode such that the laser diode is unobstructed by solder bumps and the selected bonding pads; andattaching an interposer substrate to the solder bumps which are on the bonding pads such that the interposer substrate is spaced away and disconnected from the laser diode.2. The method of claim 1 , wherein the masking layer is formed over portions of the bonding layer which are to be attached to the laser diode.3. The method of claim 1 , wherein the solder bumps are formed through a resist pattern claim 1 , after the forming of the masking layer over the bonding layer.4. The method of claim 1 , further comprising forming the solder bumps on the bonding layer.5. The method of claim 4 , wherein the patterning of the bonding layer is performed after the forming of the solder bumps such that the solder bumps and the masking layer protect underlying portions of the bonding layer during an etching process.6. The method of claim 5 , further comprising removing the masking layer and attaching the solder connections formed on the laser diode directly to the bonding pads which are formed underneath the masking layer prior to removal.7. The method of claim 6 , ...

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Номер записи: 94

09-01-2020 дата публикации

POWER MODULE, POWER CONVERTER AND MANUFACTURING METHOD OF POWER MODULE

Номер: US20200015380A1

Автор: Zeng Jian-Hong

Принадлежит:

A power module includes a heat-dissipating substrate, a first planar power device and a second planar power device. The first planar power device includes a plurality of electrodes disposed on an upper surface of the first planar power device. The second planar power device includes a plurality of electrodes disposed on an upper surface of the second planar power device. Lower surfaces of the first planar power device and the second planar power device are disposed on the heat-dissipating substrate. 1. A power module , comprising:a heat-dissipating substrate;an insulating layer, wherein the insulating layer is disposed on the heat-dissipating substrate;a first planar power device comprising a plurality of electrodes which are all on an upper surface of the first planar power device;a second planar power device comprising a plurality of electrodes which are all on an upper surface of the second planar power device, and the first planar power device is electrically connected with the second planar power device in series to form a series branch;a capacitor being electrically coupled with the series branch in parallel; anda switching device comprising a plurality of electrodes, the switching device is coupled with the series branch;wherein a lower surface of the first planar power device and a lower surface of the second planar power device are disposed on the heat-dissipating substrate.2. The power module of claim 1 , wherein a drain of the switching device is on the lower surface of the switching device and a source of the switching device is on the upper surface of the switching device; wherein the drain of the switching device is directly connected to a source of the second planar power device; or a drain of the switching device and a source of the switching device is on the upper surface of the switching device.3. The power module of claim 1 , wherein the switching device and the capacitor are disposed on the insulating layer.4. The power module of claim 1 , ...

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Номер записи: 95

19-01-2017 дата публикации

ELECTRONIC CIRCUIT

Номер: US20170018536A1

Автор: Okumura Keiji

Принадлежит: ROHM CO., LTD.

A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first wire connects the PN junction diode to one of the two terminals of the unipolar device. A second wire connects the one of the two terminals of the unipolar device to an output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire. In one embodiment the connection of the first wire to the diode is with its anode, and in another the connection is with the cathode. 1. A semiconductor device comprising:a MOSFET including a PN junction diode;a unipolar device connected in parallel to the MOSFET and having two terminals;an output line;a first wire that connects an anode of the PN junction diode to one of the two terminals of the unipolar device; anda second wire that connects the one of the two terminals of the unipolar device to the output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire,wherein the first wire and the second wire are continuous with each other.2. The semiconductor device according to claim 1 , wherein an operating voltage of the unipolar device is lower than an operating voltage of the PN junction diode.3. The semiconductor device according to claim 1 , wherein the MOSFET is an SiC semiconductor device made of a semiconducting material that chiefly includes SiC.4. The semiconductor device according to claim 1 , wherein a counter electromotive force generated by an inductance between the unipolar device and the output line is 2.0 V or more.5. The semiconductor device according to claim 1 , wherein the unipolar device includes a Schottky barrier diode.6. The semiconductor device according to claim 5 , whereinthe first wire connects the anode of the PN junction diode to an anode of the Schottky barrier diode, andthe second wire connects the anode of the Schottky ...

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Номер записи: 96

03-02-2022 дата публикации

TEST PAD STRUCTURE OF CHIP

Номер: US20220037218A1

Автор: CHEN PO-CHI, TSENG KUO-WEI

Принадлежит:

The present invention provides a test pad structure of chip, which comprises a plurality of first internal test pads, a plurality of second internal test pads, a plurality of first extended test pads, and a plurality of second extended test pads. The first internal test pads and the second internal test pads are disposed in a chip. The second internal test pads and the first internal test pads are spaced by a distance. The first extended test pads are connected with the first internal test pads. The second extended test pads are connected with the second internal test pads. The first extended test pads and the second extended test pads may increase the contact area to be contacted by probes. Signals or power are transmitted to the first internal test pads and the second internal test pads via the first extended test pads and the second extended test pads for the probes to test the chip. 1. A test pad structure of chip , comprising:a plurality of first internal test pads, disposed in a chip;a plurality of second internal test pads, disposed in said chip, and spaced with said first internal test pads by a distance;a plurality of first extended test pads, disposed on said chip, connected with said first internal test pads, and located above said first internal test pads; anda plurality of second extended test pads, disposed on said chip, connected with said second internal test pads, and located above said second internal test pads.2. The test pad structure of chip of claim 1 , wherein an area of said first extended test pads is greater than an area of said first internal test pads.3. The test pad structure of chip of claim 1 , wherein an area of said second extended test pads is greater than an area of said second internal test pads.4. The test pad structure of chip of claim 1 , wherein a length of said first extended test pads is greater than a length of said first internal test pads.5. The test pad structure of chip of claim 1 , wherein a length of said second ...

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Номер записи: 97

03-02-2022 дата публикации

SEMICONDUCTOR PACKAGE FOR IMPROVING BONDING RELIABILITY

Номер: US20220037273A1

Автор: Hong Yikoan, Kim Seokho, Lee Kyuha, Na Hoonjoo, PARK Jaehyung, SON Seongmin

Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A semiconductor package includes main pad structures and dummy pad structures between a first semiconductor chip and a second semiconductor chip. The main pad structures include first main pad structures apart from one another on the first semiconductor chip and second main pad structures placed apart from one another on the second semiconductor chip and bonded to the first main pad structures. The dummy pad structures include first dummy pad structures including first dummy pads apart from one another on the first semiconductor chip and first dummy capping layers on the first dummy pads, and second dummy pad structures including second dummy pads apart from one another on the second semiconductor chip and second dummy capping layers on the second dummy pads. The first dummy capping layers of the first dummy pad structures are not bonded to the second dummy capping layers of the second dummy pad structures. 1. A semiconductor package comprising:a first semiconductor chip;a second semiconductor chip arranged above the first semiconductor chip; andmain pad structures and dummy pad structures between the first semiconductor chip and the second semiconductor chip,wherein the main pad structures comprise first main pad structures apart from one another on the first semiconductor chip and second main pad structures apart from one another on the second semiconductor chip and bonded to the first main pad structures,wherein the dummy pad structures comprise first dummy pad structures comprising first dummy pads that are arranged apart from one another on the first semiconductor chip and first dummy capping layers arranged on the first dummy pads, and second dummy pad structures comprising second dummy pads that are arranged apart from one another on the second semiconductor chip and second dummy capping layers arranged on the second dummy pads, andwherein the first dummy capping layers of the first dummy pad structures are not bonded to the second dummy capping layers of the ...

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Номер записи: 98

03-02-2022 дата публикации

ELECTRONIC DEVICE

Номер: US20220037446A1

Автор: CHO Youngmin, KIM HONGAM

Принадлежит: Samsung Display Co., Ltd.

An electronic device includes a first electronic component and a second electronic component. The first electronic component includes a first pad area including first pads and second pads spaced apart from the first pads. A number of the first pads is greater than a number of the second pads. The second electronic component includes first bumps electrically connected to the first pads, and second bumps electrically connected to the second pads. Each of the second bumps has a bonding area greater than a bonding area of each of the first bumps. A conductive adhesive layer is disposed between the first electronic component and the second electronic component to electrically connect the first pads to the first bumps. 1. An electronic device comprising:a first electronic component comprising a first pad area including first pads and second pads spaced apart from the first pads, wherein a number of the first pads is greater than a number of the second pads; first bumps electrically connected to the first pads; and', 'second bumps electrically connected to the second pads, wherein each of the second bumps has a bonding area greater than a bonding area of each of the first bumps; and, 'a second electronic component comprisinga conductive adhesive layer disposed between the first electronic component and the second electronic component to electrically connect the first pads to the first bumps.2. The electronic device of claim 1 , whereinthe first electronic component comprises a display area adjacent to the first pad area, wherein a pixel is disposed in the display area, andthe second electronic component comprises a driving chip.3. The electronic device of claim 2 , wherein the first electronic component comprises a second pad area comprising third pads electrically connected to the second pads.4. The electronic device of claim 3 , further comprising a circuit board electrically connected to the second pad area.5. The electronic device of claim 3 , whereinthe driving chip ...

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Номер записи: 99

18-01-2018 дата публикации

Chip packaging and composite system board

Номер: US20180019178A1

Автор: Jing-Yao Chang, Kuo-Shu Kao, Tao-Chih Chang, Yu-Min Lin

Принадлежит: Industrial Technology Research Institute ITRI

A chip packaging includes a substrate, a first chip, a molding material, a first circuit, and a second circuit. The substrate includes a bottom surface, a first top surface disposed above the bottom surface with a first height, and a second top surface disposed above the bottom surface with a second height. The first height is smaller than the second height. The first chip is disposed on the first top surface. The molding material is disposed on the substrate and covers the first chip. The first and second circuits are disposed on the molding material, and are respectively and electrically connected to the first chip and the second top surface of the substrate. The substrate is made of copper material with huge area and has the properties of high current withstand capacity and high thermal efficiency. The second top surface protects the first chip from damage.

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Номер записи: 100