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06-06-2013 дата публикации

Semiconductor device and method for production of semiconductor device

Номер: US20130140699A1

Автор: Atsushi Okuyama

Принадлежит: Sony Corp

A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto.

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Номер записи: 1

05-12-2013 дата публикации

Chip package and method for forming the same

Номер: US20130320532A1

Автор: Chao-Yen Lin, Yi-Hang Lin

Принадлежит: XinTec Inc

An embodiment of the invention provides a chip package which includes: a carrier substrate; a semiconductor substrate having an upper surface and a lower surface, disposed overlying the carrier substrate; a device region or sensing region located on the upper surface of the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to a sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate.

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Номер записи: 2

02-01-2020 дата публикации

Forming Metal Bonds with Recesses

Номер: US20200006288A1

Автор: Chen Hsien-Wei, Chen Ming-Fa, Chiou Wen-Chih, Yeh Sung-Feng

Принадлежит:

A method includes forming a first device die, which includes depositing a first dielectric layer, and forming a first metal pad in the first dielectric layer. The first metal pad includes a recess. The method further includes forming a second device die including a second dielectric layer and a second metal pad in the second dielectric layer. The first device die is bonded to the second device die, with the first dielectric layer being bonded to the second dielectric layer, and the first metal pad being bonded to the second metal pad. 1. A device comprising: a first dielectric layer; and', a diffusion barrier contacting the first dielectric layer; and', 'a metallic material between opposite portions of the diffusion barrier, wherein in a cross-sectional view of the first metal pad, an edge portion of the metallic material is recessed from a top edge of a nearest portion of the diffusion barrier to form an air gap; and, 'a first metal pad comprising], 'a first device die comprising a second dielectric layer bonded to the first dielectric layer; and', 'a second metal pad bonded to the first metal pad through metal-to-metal direct bonding., 'a second device die comprising2. The device of claim 1 , wherein the air gap further extends into the second metal pad.3. The device of claim 1 , wherein the air gap is formed between a sidewall of the diffusion barrier claim 1 , a surface of the metallic material claim 1 , and a surface of the second metal pad.4. The device of claim 1 , wherein the air gap is formed between a sidewall of the diffusion barrier claim 1 , a surface of the metallic material claim 1 , and a surface of the second dielectric layer.5. The device of claim 1 , wherein a surface of the metallic material in the first metal pad and facing the air gap is rounded.6. The device of claim 1 , wherein a surface of the second metal pad facing the air gap is rounded.7. The device of claim 1 , wherein the first device die further comprises a third metal pad comprising ...

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Номер записи: 3

07-01-2016 дата публикации

ELECTRONIC DEVICE AND MOUNTING STRUCTURE OF THE SAME

Номер: US20160007464A1

Автор: Kasuya Yasumasa, Matsubara Hiroaki, Nishioka Taro

Принадлежит:

An electronic device includes an electronic element, a plurality of first sub-electrodes arrayed in a first direction, a plurality of second sub-electrodes arrayed in a second direction that is orthogonal to the first direction, a dummy electrode, and a sealing resin. The sealing resin has a resin back surface from which the plurality of first sub-electrodes, the plurality of second sub-electrodes and the dummy electrode are exposed. The plurality of second sub-electrodes are located further in the first direction than any of the plurality of first sub-electrodes. The plurality of first sub-electrodes are located further in the second direction than any of the plurality of second sub-electrodes. The dummy electrode is located further in the first direction than any of the plurality of first sub-electrodes, and is located further in the second direction than any of the plurality of second sub-electrodes. 1. An electronic device comprising:an electronic element;a plurality of first sub-electrodes arrayed in a first direction;a plurality of second sub-electrodes arrayed in a second direction that is orthogonal to the first direction;a dummy electrode; anda sealing resin covering the electronic device, the plurality of first sub-electrodes, the plurality of second sub-electrodes, and the dummy electrode,wherein the sealing resin has a resin back surface from which the plurality of first sub-electrodes, the plurality of second sub-electrodes and the dummy electrode are exposed,the plurality of second sub-electrodes are located further in the first direction than any of the plurality of first sub-electrodes,the plurality of first sub-electrodes are located further in the second direction than any of the plurality of second sub-electrodes, andthe dummy electrode is located further in the first direction than any of the plurality of first sub-electrodes, and is located further in the second direction than any of the plurality of second sub-electrodes.2. The electronic ...

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Номер записи: 4

19-01-2017 дата публикации

SEMICONDUCTOR DEVICE AND METHOD

Номер: US20170018526A1

Автор: Rusli Sukianto

Принадлежит:

Disclosed herein is a semiconductor device that includes a semiconductor die and a substrate including a first surface and a second surface. The substrate includes a conductive circuit and an insulative material over the conductive circuit. The semiconductor die is attached to the second surface. The semiconductor device further includes an interconnect joint structure in the substrate creating a capture pad including a middle copper layer, an adjacent top nickel layer, and an adjacent bottom nickel layer. A method for making a semiconductor device is further disclosed. 1. A semiconductor device comprising:a semiconductor die;a substrate including a first surface and a second surface, the substrate comprising a conductive circuit and an insulative material over the conductive circuit, wherein the semiconductor die is attached to the second surface; andan interconnect joint structure in the substrate creating a capture pad including a middle copper layer, an adjacent top nickel layer, and an adjacent bottom nickel layer.2. The semiconductor device of claim 1 , wherein the conductive circuit includes an etched layer of conductive foil that is located on the first surface of the substrate.3. The semiconductor device of claim 1 , wherein the interconnect joint structure is found in a single layer of the insulative material.4. The semiconductor device of claim 1 , wherein the semiconductor die is attached to the substrate without a via.5. The semiconductor device of claim 1 , wherein the substrate and interconnect joint structure are formed using a build-up process.6. The semiconductor device of claim 1 , wherein the substrate and interconnect joint structure are formed using a subtractive process.7. The semiconductor device of claim 1 , wherein the insulative material comprises a layer that is less than 12 μm thick.8. The semiconductor device of claim 1 , wherein the substrate further includes an etched foil layer claim 1 , and wherein the substrate further includes a ...

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Номер записи: 5

28-01-2016 дата публикации

ARRAY SUBSTRATE, METHOD FOR FABRICATING THE SAME AND DISPLAY DEVICE

Номер: US20160027812A1

Автор: Choi Seungjin, KIM HeecheoI, Song Youngsuk, Yoo Seongyeol

Принадлежит:

An array substrate, a method for fabricating the same and a display device are disclosed. The array substrate includes: a gate electrode of a TFT and a gate insulation layer sequentially formed on a base substrate; a semiconductor active layer, an etch stop layer and a source electrode and a drain electrode of the TFT sequentially formed on a part of the gate insulation layer that corresponds to the gate electrode of the TFT, the source and drain electrodes of the TFT are respectively in contact with the semiconductor active layer by way of via holes. The array substrate further includes: a first insulation layer formed between the gate electrode of the TFT and the gate insulation layer and the gate electrode is in contact with the gate insulation layer at a channel region of the TFT between the source electrode and the drain electrode of the TFT. 1. An array substrate , comprising:a gate electrode of a TFT and a gate insulation layer sequentially formed on a base substrate;a semiconductor active layer, an etch stop layer and a source electrode and a drain electrode of the TFT sequentially formed on a part of the gate insulation layer that corresponds to the gate electrode of the TFT, wherein the source and drain electrodes of the TFT are respectively in contact with the semiconductor active layer by way of via holes; a first insulation layer formed between the gate electrode of the TFT and the gate insulation layer, wherein the first insulation layer corresponds to at least one of the source electrode and the drain electrode of the TFT; and', 'the gate electrode is in contact with the gate insulation layer at a channel region of the TFT between the source electrode and the drain electrode of the TFT., 'the array substrate further comprising2. The array substrate of claim 1 , further comprising:a second insulation layer formed between the base substrate and the gate electrode of the TFT, wherein the second insulation layer corresponds to the TFT channel and a sum of ...

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Номер записи: 6

28-01-2021 дата публикации

Bonded assembly containing oxidation barriers, hybrid bonding, or air gap, and methods of forming the same

Номер: US20210028135A1

Автор: Raghuveer S. Makala, Ramy Nashed Bassely SAID, Senaka Kanakamedala

Принадлежит: SanDisk Technologies LLC

At least one polymer material may be employed to facilitate bonding between the semiconductor dies. Plasma treatment, formation of a blended polymer, or formation of polymer hairs may be employed to enhance bonding. Alternatively, air gaps can be formed by subsequently removing the polymer material to reduce capacitive coupling between adjacent bonding pads.

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Номер записи: 7

02-02-2017 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20170033085A1

Автор: Hamada Yusuke, MORIYAMA Osamu, Shikibu Takahiro

Принадлежит: FUJITSU LIMITED

A semiconductor device, includes: a first semiconductor chip including: a first substrate; a first via; a first rear surface-side pad connected to the first via; a first wiring layer; a first front surface-side pad formed on the first wiring layer; and an input circuit formed in the first substrate, an input signal wire connecting the first via, the first front surface-side pad, and an input terminal of the input circuit; and a second semiconductor chip including: a second substrate; a second wiring layer; a second front surface-side pad; and an output circuit formed in the second substrate, an output signal wire connecting the second front surface-side pad to an output terminal of the output circuit. The second semiconductor chip is stacked on a rear surface side of the first semiconductor chip, and the first rear surface-side pad and the second front surface-side pad are connected. 1. A semiconductor device comprising:a first semiconductor chip including: a first substrate; a first via penetrating through the first substrate; a first rear surface-side pad formed on a rear surface side of the first substrate and connected to the first via; a first wiring layer formed on a front surface side of the first substrate; a first front surface-side pad formed on a front surface side of the first wiring layer; and an input circuit formed in the first substrate, the first wiring layer being provided with an input signal wire which connects the first via, the first front surface-side pad, and an input terminal of the input circuit; anda second semiconductor chip including: a second substrate, a second wiring layer formed on a front surface side of the second substrate; a second front surface-side pad formed on a front surface side of the second wiring layer; and an output circuit formed in the second substrate, the second wiring layer being provided with an output signal wire which connects the second front surface-side pad to an output terminal of the output circuit,wherein ...

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Номер записи: 8

24-02-2022 дата публикации

Memory device including pass transistors

Номер: US20220059480A1

Автор: Jin HO KIM, Tae Sung Park

Принадлежит: SK hynix Inc

A memory device includes an active region with a drain; a plurality of memory blocks arranged in a first direction; and a plurality of pass transistors formed in the active region and sharing the drain, each one of the plurality of pass transistors configured to transfer an operating voltage from the drain to a corresponding one of the plurality of memory blocks in response to a block select signal. The plurality of pass transistors is divided into first pass transistors and second pass transistors. A channel length direction of the first pass transistors and a channel length direction of the second pass transistors are different from each other.

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Номер записи: 9

06-02-2020 дата публикации

Interface structures and methods for forming same

Номер: US20200043848A1

Автор: Javier A. Delacruz, Shaowu HUANG

Принадлежит: Invensas Bonding Technologies Inc

A stacked and electrically interconnected structure is disclosed. The stacked structure can include a first element comprising a first contact pad and a second element comprising a second contact pad. The first contact pad and the second contact pad can be electrically and mechanically connected to one another by an interface structure. The interface structure can comprise a passive equalization circuit that includes a resistive electrical pathway between the first contact pad and the second contact pad and a capacitive electrical pathway between the first contact pad and the second contact pad. The resistive electrical pathway and the capacitive electrical pathway form an equivalent parallel resistor-capacitor (RC) equalization circuit.

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Номер записи: 10

18-02-2021 дата публикации

LOW STRESS PAD STRUCTURE FOR PACKAGED DEVICES

Номер: US20210050317A1

Автор: Gong Zhiwei, SOUTHWORTH Paul

Принадлежит:

Embodiments are provided for package semiconductor devices, each device including: a low stress pad structure comprising: a dielectric layer, a seed layer having: a center section, and a ring section formed around the center section and over a top surface of the dielectric layer, wherein the ring section of the seed layer includes a set of elongated openings through which a portion of the top surface of the dielectric layer is exposed, and a metal layer having: an inner section formed over a top surface of the center section of the seed layer, and an outer section formed over a top surface of the ring section of the seed layer, wherein a bottom surface of the outer section of the metal layer directly contacts the portion of the top surface of the dielectric layer exposed through the set of elongated openings. 1. A packaged semiconductor device comprising: a dielectric layer,', a center section, and', 'a ring section formed around the center section and over a top surface of the dielectric layer, wherein the ring section of the seed layer includes a set of elongated openings through which a portion of the top surface of the dielectric layer is exposed, and, 'a seed layer having, an inner section formed over a top surface of the center section of the seed layer, and', 'an outer section formed over a top surface of the ring section of the seed layer, wherein a bottom surface of the outer section of the metal layer directly contacts the portion of the top surface of the dielectric layer exposed through the set of elongated openings., 'a metal layer having], 'a low stress pad structure comprising2. The packaged semiconductor device of claim 1 , whereina remaining portion of the seed layer around the one or more elongated openings is continuous within the ring section.3. The packaged semiconductor device of claim 1 , whereinthe inner and outer sections of the metal layer are plated onto the center and ring sections of the seed layer sections.4. The packaged semiconductor ...

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Номер записи: 11

03-03-2022 дата публикации

LEAD FRAME-BASED SEMICONDUCTOR PACKAGE

Номер: US20220068773A1

Автор: Cha Chan Lam, Hetzel Wolfgang, Lee Swee Kah, Macheiner Stefan, Scharf Thorsten

Принадлежит:

A semiconductor package includes: a lead frame having a plurality of blocks of uniform size and laterally spaced apart from one another with uniform spacing; a first semiconductor die attached to a first group of the blocks; electrical conductors connecting a plurality of input/output (I/O) terminals of the first semiconductor die to a second group of the blocks, at least some blocks of the second group being laterally spaced outward from the blocks of the first group; and a mold compound encapsulating the first semiconductor die and the electrical conductors. Corresponding methods of producing the semiconductor package are also described. 1. A semiconductor package , comprising:a lead frame comprising a plurality of blocks of uniform size and laterally spaced apart from one another with uniform spacing;a first semiconductor die attached to a first group of the blocks;electrical conductors connecting a plurality of input/output (I/O) terminals of the first semiconductor die to a second group of the blocks, at least some blocks of the second group being laterally spaced outward from the blocks of the first group; anda mold compound encapsulating the first semiconductor die and the electrical conductors.2. The semiconductor package of claim 1 , wherein the uniform size and the uniform spacing are the same.3. The semiconductor package of claim 1 , wherein the uniform spacing defines an internal pitch within the semiconductor package claim 1 , and wherein the semiconductor package has a different pitch than the internal pitch.4. The semiconductor package of claim 1 , wherein the uniform size plus the uniform spacing defines a pitch of the semiconductor package claim 1 , and wherein the pitch is 0.4 mm claim 1 , 0.5 mm claim 1 , 0.65 mm claim 1 , or 1.27 mm.5. The semiconductor package of claim 1 , wherein the first semiconductor die overhangs one or more of the blocks to which the first semiconductor die is attached.6. The semiconductor package of claim 1 , wherein the ...

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Номер записи: 12

22-02-2018 дата публикации

Method for manufacturing semiconductor devices, and corresponding device

Номер: US20180053709A1

Автор: Paolo Casati, Paolo Crema

Принадлежит: STMICROELECTRONICS SRL

Semiconductor devices comprising at least one electrically conductive metal element in a non-conductive package material are manufactured by: providing a first metal layer having a smooth morphology for covering the aforesaid metal element; and providing a second metal layer for covering partially the first layer, leaving at least one portion of the surface of the first layer exposed, the second layer having a rough morphology. There may moreover be provided a die pad for mounting a semiconductor die by providing the aforesaid first layer for covering the die pad and attaching a semiconductor die on the die pad in contact with said first layer.

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Номер записи: 13

23-02-2017 дата публикации

ELECTRONIC DEVICE HAVING A REDISTRIBUTION AREA

Номер: US20170053882A1

Автор: An Jinho, CHUN Jinho, JIN Jeonggi, Lee Kyu-Ha, Park Byunglyul

Принадлежит:

An electronic device includes an upper insulating layer on a substrate. An upper redistribution structure is embedded in the upper insulating layer. The upper redistribution structure includes an upper contact portion, an upper pad portion, and an upper line portion between the upper contact portion and the upper pad portion. A passivation layer is on the upper insulating layer and the upper redistribution structure. An upper opening is configured to pass through the passivation layer and expose the upper pad portion. Vertical thicknesses of the upper pad portion and the upper contact portion are greater than a vertical thickness of the upper line portion. 1. An electronic device comprising:an upper insulating layer on a substrate;an upper redistribution structure embedded in the upper insulating layer, wherein the upper redistribution structure comprises an upper contact portion, an upper pad portion, and an upper line portion between the upper contact portion and the upper pad portion;a passivation layer on the upper insulating layer and the upper redistribution structure; andan upper opening configured to pass through the passivation layer and expose the upper pad portion,wherein vertical thicknesses of the upper pad portion and the upper contact portion are greater than a vertical thickness of the upper line portion.2. The electronic device of claim 1 , wherein:the upper insulating layer has an upper contact opening, an upper line recess, and an upper pad opening;the upper contact opening and the upper pad opening pass through the upper insulating layer; andthe upper line recess connects an upper portion of the upper contact opening to an upper portion of the upper pad opening.3. The electronic device of claim 2 , wherein:the upper contact portion is in the upper contact opening;the upper pad portion is in the upper pad opening; andthe upper line portion is in the upper line portion.4. The electronic device of claim 1 , wherein the upper redistribution structure ...

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Номер записи: 14

10-03-2022 дата публикации

Semiconductor package with air gap

Номер: US20220077091A1

Автор: Tse-Yao Huang

Принадлежит: Nanya Technology Corp

The present application provides a semiconductor package with air gaps for reducing capacitive coupling between conductive features and a method for manufacturing the semiconductor package. The semiconductor package includes a first semiconductor structure and a second semiconductor structure bonded with the first semiconductor structure. The first semiconductor structure has a first bonding surface. The second semiconductor structure has a second bonding surface partially in contact with the first bonding surface. A portion of the first bonding surface is separated from a portion of the second bonding surface, a space between the portions of the first and second bonding surfaces is sealed and forms an air gap in the semiconductor package.

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Номер записи: 15

10-03-2022 дата публикации

HYBRID BONDING STRUCTURE AND HYBRID BONDING METHOD

Номер: US20220077105A1

Автор: DAI Yufeng, He Ran, HO Chihon, Jiao Huifang, XIE Ronghua, Yang Guanglin

Принадлежит: Huawei Technologies CO.,Ltd.

Embodiments of this application disclose a hybrid bonding structure and a hybrid bonding method. The hybrid bonding structure includes a first chip and a second chip. A surface of the first chip includes a first insulation dielectric and a first metal, and a first gap area exists between the first metal and the first insulation dielectric. A surface of the second chip includes a second insulation dielectric and a second metal. A surface of the first metal is higher than a surface of the first insulation dielectric. Metallic bonding is formed after the first metal is in contact with the second metal, and the first metal is longitudinally and transversely deformed in the first gap area. Insulation dielectric bonding is formed after the first insulation dielectric is in contact with the second insulation dielectric. 1. A hybrid bonding structure , comprising:a first chip; anda second chip, whereina surface of the first chip includes a first dielectric layer and a first metal layer, the first dielectric layer includes a first insulation dielectric, the first metal layer includes a first metal, and a first gap area exists between an edge of the first metal and the first insulation dielectric;a surface of the second chip includes a second dielectric layer and a second metal layer, the second dielectric layer includes a second insulation dielectric, and the second metal layer includes a second metal;a surface of the first metal is higher than a surface of the first insulation dielectric;metallic bonding is formed after the first metal is in contact with the second metal, and the first metal is longitudinally and transversely deformed in the first gap area, andinsulation dielectric bonding is formed after the first insulation dielectric is in contact with the second insulation dielectric.2. The hybrid bonding structure according to claim 1 , wherein a surface of the second metal is higher than a surface of the second insulation dielectric.3. The hybrid bonding structure ...

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Номер записи: 16

03-03-2016 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20160064340A1

Автор: Chen Chen-Shien, Chuang Chita, Lii Mirng-Ji, TSENG HUA-WEI, Tseng Ming Hung

Принадлежит:

A semiconductor device structure includes a first substrate having a first surface and a second surface opposite to the first surface, a conductive pad at the first surface of the first substrate, and a connector overlying the conductive pad, wherein the connector is configured for electrically connecting with a conductive land of a second substrate, wherein a geometric center of the connector is deviated from a geometric center of the conductive pad and a geometric center of the conductive land. 1. A semiconductor device , comprising:a first substrate having a first surface and a second surface opposite to the first surface;a conductive pad at the first surface of the first substrate; anda connector overlying the conductive pad, wherein the connector is configured for electrically connecting with a conductive land of a second substrate,wherein a geometric center of the connector is deviated from a geometric center of the conductive pad and a geometric center of the conductive land.2. The semiconductor device according to claim 1 , wherein the second substrate comprises a plurality of dielectric layers and conductors stacked together without an intervening core.3. The semiconductor device according to claim 1 , wherein the second substrate further includes a tapered metallic plug protruded from a surface of the second substrate and configured for electrically connecting with the connector.4. The semiconductor device according to claim 1 , further comprising a plurality of conductive pads and a plurality of corresponding connectors claim 1 , wherein a pitch between neighboring connectors is between about 50 μm and about 150 μm.5. The semiconductor device according to claim 1 , further comprising a solder disposed on top of the pillar claim 1 , wherein the solder is configured to become in contact with the conductive land of the second substrate.6. A semiconductor device claim 1 , comprising:a first substrate with a connector protruding from a conductive pad at a ...

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Номер записи: 17

02-03-2017 дата публикации

POWER PACKAGE MODULE OF MULTIPLE POWER CHIPS AND METHOD OF MANUFACTURING POWER CHIP UNIT

Номер: US20170062386A1

Автор: LI Zeng, Lu Kai, WANG TAO, ZENG Jianhong, ZHAO Zhenqing

Принадлежит: DELTA ELECTRONICS (SHANGHAI) CO., LTD

The embodiments of the present disclosure relate to a power package module of multiple power chips and a method of manufacturing a power chip unit. The power package module of multiple power chips includes: a power chip unit including at least two power chips placed in parallel and a bonding part bonding the two power chips; a substrate supporting the power chip unit and including a metal layer electronically connecting with the power chip unit; and a sealing layer isolating the power chip unit on the substrate from surroundings to seal the power chip unit; the bonding part and the sealing layer are made from different insulated material, the distance of a gap between the two power chips placed in parallel is smaller than or equal to a preset width, and the bonding part is filled in the gap, insulatedly bonding the two power chips placed in parallel. 1. A power package module of multiple power chips , comprising:a power chip unit comprising at least two power chips placed in parallel and a bonding part bonding the two power chips;a substrate supporting the power chip unit and comprising a metal layer which is electronically connected with the power chip unit; anda sealing layer isolating the power chip unit on the substrate from surroundings to seal the power chip unit;wherein the bonding part and the sealing layer are made from different insulated materials, a gap between the two power chips placed in parallel is smaller than or equal to a preset width, and the bonding part is filled into the gap for bonding and insulating the two power chips placed in parallel.2. The power package module according to claim 1 , wherein the preset width is 200 μm.3. The power package module according to claim 1 , wherein a thickness of the bonding part is in a range of 1/3T˜T claim 1 , wherein T refers to a thickness of the power chip.4. The power package module according to claim 1 , wherein a material of the bonding part has a rigidity more than Shore A 10 claim 1 , an insulating ...

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Номер записи: 18

04-03-2021 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20210066224A1

Автор: Jang Joohee, Kim Seokho, Lee Kyuha, Na Hoonjoo, PARK Jaehyung

Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A semiconductor device is provided and includes first and second semiconductor chips bonded together. The first chip includes a first substrate, a first insulating layer disposed on the first substrate and having a top surface, a first metal pad embedded in the first insulating layer and having a top surface substantially planar with the top surface of the first insulating layer, and a first barrier disposed between the first insulating layer and the first metal pad. The second chip includes a second substrate, a second insulating layer, a second metal pad, and a second barrier with a similar configuration to the first chip. The top surfaces of the first and second insulating layers are bonded to provide a bonding interface, the first and second metal pads are connected, and a portion of the first insulating layer is in contact with a side region of the first metal pad. 1. A semiconductor device comprising:a first semiconductor chip; anda second semiconductor chip disposed on the first semiconductor chip, a first substrate;', 'a first insulating layer disposed on the first substrate and having a top surface;', 'a first metal pad embedded in the first insulating layer and having a top surface substantially planar with the top surface of the first insulating layer; and', 'a first barrier disposed between the first insulating layer and the first metal pad,, 'wherein the first semiconductor chip includes a second substrate;', 'a second insulating layer disposed below the second substrate and having a top surface;', 'a second metal pad embedded in the second insulating layer and having a top surface substantially planar with the top surface of the second insulating layer; and', 'a second barrier disposed between the second insulating layer and the second metal pad, and, 'wherein the second semiconductor chip includeswherein the top surfaces of the first insulating layer and the second insulating layer are bonded to provide a bonding interface,the first metal pad and the ...

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Номер записи: 19

08-03-2018 дата публикации

Conductive Pad Structure for Hybrid Bonding and Methods of Forming Same

Номер: US20180068965A1

Автор: Chen Sheng-Chau, Chou Cheng-Hsien, Chou Shih Pei, Chu Yen-Chang, HUANG Chih-Hui, Tu Yeur-Luen

Принадлежит:

A representative device includes a patterned opening through a layer at a surface of a device die. A liner is disposed on sidewalls of the opening and the device die is patterned to extend the opening further into the device die. After patterning, the liner is removed. A conductive pad is formed in the device die by filling the opening with a conductive material. 1. A device comprising:a first substrate;a first redistribution structure over the first substrate;a first dielectric layer over the first redistribution structure; and a first portion extending through the first dielectric layer, the first portion having a first width; and', 'a second portion extending through the first redistribution structure, the second portion having a second width, the second width being different from the first width., 'a first conductive pad extending through the first dielectric layer and the first redistribution structure, a bottommost surface of the first conductive pad being below a bottommost surface of the first redistribution structure, wherein the first conductive pad comprises2. The device of claim 1 , wherein the second width is less than the first width.3. The device of claim 1 , further comprising:a second substrate;a second redistribution structure interposed between the second substrate and the first dielectric layer;a second dielectric layer interposed between the second redistribution structure and the first dielectric layer, the second dielectric layer being in physical contact with first dielectric layer; anda second conductive pad extending through the second dielectric layer and the second redistribution structure, the second conductive pad being in physical contact with the first conductive pad.4. The device of claim 3 , wherein a topmost surface of the second conductive pad is above a topmost surface of the second redistribution structure.5. The device of claim 3 , wherein the second conductive pad comprises:a third portion extending through the second ...

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Номер записи: 20

11-03-2021 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20210074658A1

Автор: TAGAMI Masayoshi

Принадлежит: Toshiba Memory Corporation

In one embodiment, a semiconductor device includes a first chip including a substrate, a first plug on the substrate, and a first pad on the first plug, and a second chip including a second plug and a second pad under the second plug. The second chip includes an electrode layer electrically connected to the second plug, a charge storage layer provided on a side face of the electrode layer via a first insulator, and a semiconductor layer provided on a side face of the charge storage layer via a second insulator. The first and second pads are bonded with each other, and the first and second plugs are disposed so that at least a portion of the first plug and at least a portion of the second plug do not overlap with each other in a first direction that is perpendicular to a surface of the substrate. 1. A semiconductor device comprising: a substrate,', 'a first interconnect layer provided above the substrate,', 'a first pad provided above the first interconnect layer, and', 'a first plug extending in a first direction crossing a surface of the substrate and connecting the first interconnect layer and the first pad; and, 'a first chip including a second interconnect layer,', 'a second pad provided under the second interconnect layer,', 'a second plug extending in the first direction and connecting the second interconnect layer and the second pad, and', 'a memory cell array electrically connected to the second interconnect layer, wherein', 'the first and second plugs do not overlap with each other in the first direction,, 'a second chip includinga first portion of the first pad overlapping with the first plug in the first direction are all bonded with the second pad, anda second portion of the second pad overlapping with the second plug in the first direction are all bonded with the first pad.2. The device of claim 1 , whereina material of the first plug is identical with a material of the first pad and different from a material of the first interconnect layer, anda ...

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Номер записи: 21

11-03-2021 дата публикации

LIGHT EMITTING PACKAGE, AND MANUFACTURING METHOD THEREOF, AND CARRIER

Номер: US20210074896A1

Автор: Chen Chih-Yuan, LIN CHEN-HSIU

Принадлежит:

A light emitting package is provided, the light emitting package includes a carrier having a main part that has multiple chip bonding regions, and each the chip bonding regions has two neighboring conductive parts. An insulating part is disposed on the main part and portion of the two neighboring conductive parts, and multiple hollow-out structures are formed by the insulating part and corresponded in position to the chip bonding regions. Each of the hollow-out structures has a side wall that surrounds the chip bonding regions, and the portion of the tops of the two neighboring conductive parts are exposed from a bottom portion of the hollow-out structure, and multiple light emitting chips are disposed onto the chip bonding surfaces. 1. A light emitting package comprising:a carrier having at least one chip bonding region that is defined by at least two neighboring conductive parts and an insulating part around the least two neighboring conductive parts, wherein a top of the insulating part is higher than tops of the at least two neighboring conductive parts;at least one hollow-out structure formed at a portion of the insulating part corresponding in position to the at least one chip bonding region, wherein the at least one hollow-out structure has a side wall surrounding the at least one chip bonding region and a bottom portion being parallel to the at least one chip bonding region, and portions of the tops of the at least two neighboring conductive parts are exposed from the bottom portion, and the tops of the at least two neighboring conductive parts corresponding in position to the at least one hollow-out structure are defined as the least one chip bonding region;at least one light emitting chip disposed on the at least one chip bonding region, electrically connected with the exposed portions of the at least two neighboring conductive parts; anda sealant disposed on the carrier and surrounding the at least one light emitting chip.2. The light emitting package ...

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Номер записи: 22

07-03-2019 дата публикации

Semiconductor structure and manufacturing method thereof

Номер: US20190074248A1

Автор: Chih-Kang Han, Ching-Fu Chang, Hsi-Kuei Cheng, Hsin-Chieh Huang

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method of manufacturing a semiconductor structure is provided. The method includes providing a substrate, disposing a die over the substrate, forming a molding over the substrate and around the die, disposing a first dielectric layer over the die and the molding, curing the first dielectric layer under a first curing condition, disposing a second dielectric layer over the first dielectric layer, and curing the first dielectric layer and the second dielectric layer under the first curing condition.

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Номер записи: 23

15-03-2018 дата публикации

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Номер: US20180076129A1

Автор: Chang Ching-Fu, Cheng Hsi-Kuei, HAN Chih-Kang, Huang Hsin-Chieh

Принадлежит:

A semiconductor structure includes a substrate; a die disposed over the substrate, and including a die pad, a conductive via disposed over the die pad and a dielectric material surrounding the conductive via; a molding disposed over the substrate and surrounding the die; a lower dielectric layer disposed nearer the substrate and over the dielectric material and the molding; and an upper dielectric layer disposed further the substrate and over the lower dielectric layer, wherein a material content ratio in the upper dielectric layer is substantially greater than that in the lower dielectric layer, and the material content ratio substantially inversely affects a mechanical strength of the upper dielectric layer and the lower dielectric layer. 1. A semiconductor structure , comprising:a substrate;a die disposed over the substrate, and including a die pad, a conductive via disposed over the die pad and a dielectric material surrounding the conductive via;a molding disposed over the substrate and surrounding the die;a lower dielectric layer disposed nearer the substrate and over the dielectric material and the molding; and 'wherein a material content ratio in the upper dielectric layer is substantially greater than that in the lower dielectric layer, and the material content ratio substantially inversely affects a mechanical strength of the upper dielectric layer and the lower dielectric layer.', 'an upper dielectric layer disposed further the substrate and over the lower dielectric layer,'}2. The semiconductor structure of claim 1 , wherein the material content ratio includes at least one of oxygen content ratio or nitrogen content ratio.3. The semiconductor structure of claim 2 , wherein the oxygen content ratio of the lower dielectric layer is substantially less than about 10% of overall content in the lower dielectric layer claim 2 , or the nitrogen content ratio of the lower dielectric layer is substantially less than about 20% of overall content in the lower ...

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Номер записи: 24

24-03-2022 дата публикации

MICROELECTRONIC ASSEMBLIES WITH INDUCTORS IN DIRECT BONDING REGIONS

Номер: US20220093546A1

Автор: "OBRIEN Kevin P.", Aleksov Aleksandar, Bharath Krishna, EID Feras, Elsherbini Adel A., Jun Kimin, Kabir Mohammad Enamul, Liff Shawna M., Pasdast Gerald S., Swan Johanna M., Then Han Wui

Принадлежит: Intel Corporation

Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor. 1. A microelectronic assembly , comprising:a first microelectronic component; anda second microelectronic component coupled to the first microelectronic component by a direct bonding region,wherein the direct bonding region includes at least part of an inductor.2. The microelectronic assembly of claim 1 , wherein the direct bonding region includes at least part of a magnetic region of the inductor.3. The microelectronic assembly of claim 2 , wherein the magnetic region includes a first layer of magnetic material claim 2 , a second layer of magnetic material claim 2 , and a layer of dielectric material between the first layer of magnetic material and the second layer of magnetic material.4. The microelectronic assembly of claim 2 , wherein the magnetic region includes a first portion provided by the first microelectronic component and a second portion provided by the second microelectronic component.5. The microelectronic assembly of claim 4 , wherein the first portion has a lip extending away from a side of the first portion.6. The microelectronic assembly of claim 4 , wherein the first portion is larger than the second portion.7. The microelectronic assembly of claim 4 , wherein the first portion has a first U-shaped cross-section claim 4 , the second portion has a second U-shaped cross-section claim 4 , and the first U-shaped cross-section is larger than the second U-shaped cross-section.8. A microelectronic assembly claim 4 , comprising:a first microelectronic component; anda second microelectronic ...

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Номер записи: 25

24-03-2022 дата публикации

MICROELECTRONIC ASSEMBLIES WITH INDUCTORS IN DIRECT BONDING REGIONS

Номер: US20220093547A1

Автор: "OBRIEN Kevin P.", Aleksov Aleksandar, EID Feras, Elsherbini Adel A., Jun Kimin, Kabir Mohammad Enamul, Liff Shawna M., Pasdast Gerald S., Qian Zhiguo, Swan Johanna M., Then Han Wui

Принадлежит: Intel Corporation

Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor. 1. A microelectronic assembly , comprising:a first microelectronic component having a direct bonding interface, wherein the first microelectronic component includes an inductor trace, and an interface portion of the inductor trace is at the direct bonding interface of the first microelectronic component; anda second microelectronic component having a direct bonding interface, wherein the direct bonding interface of the second microelectronic component is coupled to the direct bonding interface of the first microelectronic component.2. The microelectronic assembly of claim 1 , wherein the interface portion of the inductor trace is part of a first turn of the inductor trace claim 1 , and at least a portion of a second turn of the inductor trace is in a metallization stack of the first microelectronic component.3. The microelectronic assembly of claim 1 , wherein the interface portion of the inductor trace is in contact with dielectric material of the direct bonding interface of the second microelectronic component.4. The microelectronic assembly of claim 1 , wherein the interface portion of the inductor trace is in contact with conductive material of the direct bonding interface of the second microelectronic component.5. The microelectronic assembly of claim 1 , wherein the inductor trace is a first inductor trace claim 1 , the second microelectronic component includes a second inductor trace claim 1 , and the first inductor trace and second inductor trace are parts of a transformer.6. The microelectronic ...

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Номер записи: 26

05-03-2020 дата публикации

Stacked Semiconductor Structure and Method

Номер: US20200075556A1

Автор: Chen Szu-Ying, Wan Meng-Hsun, Yaung Dun-Nian

Принадлежит:

A device comprises a first chip comprising a first connection pad embedded in a first dielectric layer and a first bonding pad embedded in the first dielectric layer, wherein the first bonding pad comprises a first portion and a second portion, the second portion being in contact with the first connection pad and a second chip comprising a second bonding pad embedded in a second dielectric layer of the second chip, wherein the first chip and the second chip are face-to-face bonded together through the first bonding pad the second bonding pad. 1. A device comprising: a first connection pad embedded in a first dielectric layer;', 'a first connector embedded in the first dielectric layer, the first connector directly contacting the first connection pad; and', 'a first bonding pad embedded in the first dielectric layer, the first connector being interposed between first bonding pad and the first connection pad; and, 'a first chip comprising a semiconductor substrate', 'an interconnect structure interposed between the semiconductor substrate and the first chip;', 'an external connection pad directly on the interconnect structure, the interconnect structure being interposed between the external connection pad and the first chip;', 'a second dielectric layer interposed between the interconnect structure the first chip, the second dielectric layer being directly bonded to the first dielectric layer; and', 'a second bonding pad embedded in the second dielectric layer of the second chip, wherein the first chip and the second chip are face-to-face bonded together through the first bonding pad the second bonding pad., 'a second chip bonded to the first chip, the second chip comprising2. The device of claim 1 , wherein a width of the first connector is less than a width of the first bonding pad and a width of the first connection pad.3. The device of claim 2 , wherein a width of the first bonding pad is less than a width of the second bonding pad.4. The device of claim 1 , ...

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Номер записи: 27

23-03-2017 дата публикации

SEMICONDUCTOR PACKAGE

Номер: US20170084558A1

Автор: Baek Hyung-gil, CHO Tae-Je, Chung Hyun-Soo, Kwon Yong-hwan, PARK MYEONG-SOON, Ryu Seung-kwan, Seo Sun-kyoung

Принадлежит:

A semiconductor package includes a semiconductor substrate and an electrode pad formed on the semiconductor substrate. The electrode pad includes a central portion and a peripheral portion, and a first pattern is located on the peripheral portion. A passivation layer is formed on the semiconductor substrate and the electrode pad. The passivation layer has an opening exposing the central portion of the electrode pad and a second pattern located on the first pattern. A seed layer is formed on the electrode pad and the passivation layer. The seed layer has a third pattern formed on the second pattern. A bump is formed on the seed layer and electrically connected to the electrode pad. An undercut is formed around the third pattern located under an edge of a lower portion of the bump. 1. A semiconductor package comprising:a semiconductor substrate;an electrode pad on the semiconductor substrate and including a central portion and a peripheral portion, wherein a first pattern is located on the peripheral portion;a passivation layer on the semiconductor substrate and the electrode pad, the passivation layer having an opening exposing the central portion of the electrode pad and a second pattern located on the first pattern;a seed layer on the electrode pad and the passivation layer and having a third pattern on the second pattern; anda bump on the seed layer and electrically connected to the electrode pad,wherein an undercut is formed in the third pattern located under an edge of a lower portion of the bump.2. The semiconductor package of claim 1 , wherein the bump comprises a pillar layer being in contact with the seed layer and a solder layer on the pillar layer.3. The semiconductor package of claim 2 , wherein a top surface of the pillar layer is a flat surface claim 2 , anda bottom surface of the pillar layer is a curved surface corresponding to the third pattern.4. The semiconductor package of claim 2 , wherein a distance from a center of the pillar layer to a side ...

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Номер записи: 28

31-03-2022 дата публикации

SEMICONDUCTOR PACKAGES

Номер: US20220102245A1

Автор: Jang Chulyong

Принадлежит:

A semiconductor package includes a plurality of semiconductor chips. At least one of the semiconductor chips includes a semiconductor substrate including a semiconductor layer and a passivation layer having a third surface, a backside pad on the third surface, and a through-via penetrating through the semiconductor substrate. The backside pad includes an electrode pad portion, on the third surface, and a dam structure protruding on one side of the electrode pad portion and surrounding a side surface of the through-via. The dam structure is spaced apart from the side surface of the through-via. 1. A semiconductor package comprising:a plurality of semiconductor chips electrically connected to each other and stacked in a first direction, a semiconductor substrate including a semiconductor layer having a first surface and a second surface that are opposite each other;', 'a passivation layer on the first surface and having a third surface that is opposite the first surface;', 'a circuit structure on the second surface;', 'a frontside pad on the circuit structure;', 'a backside pad on the third surface; and', 'a through-via in the semiconductor substrate and extending between the second surface and the third surface to be electrically connected to the backside pad and the frontside pad,, 'wherein at least one of the plurality of semiconductor chips includeswherein the backside pad includes an electrode pad portion, on the third surface, and a dam structure protruding toward the first surface on one side of the electrode pad portion and surrounding a side surface of the through-via, andwherein the dam structure is spaced apart from the side surface of the through-via.2. The semiconductor package of claim 1 ,wherein the dam structure penetrates the third surface of the passivation layer,wherein a ratio of a height of the dam structure in the first direction to a maximum thickness of the passivation layer is within a range of about 0.5:1 to about 0.8:1,wherein the through- ...

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Номер записи: 29

12-03-2020 дата публикации

Method for producing structure, and structure

Номер: US20200083190A1

Автор: Hiroshi Kikuchi, Kohei Seyama, Miyuki UOMOTO, Takehito Shimatsu, Tomonori Nakamura, Yuji Eguchi

Принадлежит: Shinkawa Ltd, Tohoku University NUC

This method for producing a structure wherein base materials are bonded by atomic diffusion comprises: a step for applying a liquid resin on the base material; a step for smoothing the surface of the liquid resin by surface tension; a step for forming a resin layer by curing; a step for forming a metal thin film on the resin layer; a step for forming a metal thin film on the base material; and a step for bringing the metal thin film of the base material and the metal thin film of the base material into close contact with each other, thereby bonding the metal thin film of the resin layer and the metal thin film of the base material with each other by atomic diffusion

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Номер записи: 30

05-05-2022 дата публикации

Semiconductor device and data storage system including the same

Номер: US20220139944A1

Автор: Jiyoung Kim, Jungtae Sung, Junyoung Choi, Yoonjo Hwang

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device includes a first substrate structure including a first substrate, circuit devices, first interconnection lines, bonding metal layers on upper surfaces of the first interconnection lines, and a first bonding insulating layer on the upper surfaces of the first interconnection lines and on lateral surfaces of the bonding metal layers, and a second substrate structure on the first substrate structure, and including a second substrate, gate electrodes, channel structures, second interconnection lines, bonding vias connected to the second interconnection lines and the bonding metal layers and having a lateral surface that is inclined such that widths of the bonding vias increase approaching the first substrate structure, and a second bonding insulating layer in contact with at least lower portions of the bonding vias. The bonding metal layers include dummy bonding metal layers not connected to the bonding vias and that contacts the second bonding insulating layer.

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Номер записи: 31

19-03-2020 дата публикации

PATTERN DECOMPOSITION LITHOGRAPHY TECHNIQUES

Номер: US20200091101A1

Автор: ABDALLAH HOSSAM A., Bigwood Robert M., Golonzka Oleg, Sivakumar Swaminathan, Tan Elliot N., Wallace Charles H.

Принадлежит: Intel Corporation

Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes. 1. An integrated circuit , comprising: a first group of unidirectional linear features, each linear feature of the first group having a first width and aligned in the first direction, and', 'a second group of unidirectional linear features, each linear feature of the second group having a second width and aligned in the first direction; and, 'a layer including unidirectional linear features aligned in a first direction, the unidirectional linear features including'}wherein the linear features of the first group are arranged in an interleaved fashion with the linear features of the second group in a series that alternates between a linear feature of the first group and a linear feature of the second group, the series traversing the layer in a second direction perpendicular to the first direction as seen in a plan view of the layer of the unidirectional linear features.2. ...

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Номер записи: 32

05-04-2018 дата публикации

INTERFACE STRUCTURES AND METHODS FOR FORMING SAME

Номер: US20180096931A1

Автор: DeLaCruz Javier, Huang Shaowu

Принадлежит:

A stacked and electrically interconnected structure is disclosed. The stacked structure can include a first element comprising a first contact pad and a second element comprising a second contact pad. The first contact pad and the second contact pad can be electrically and mechanically connected to one another by an interface structure. The interface structure can comprise a passive equalization circuit that includes a resistive electrical pathway between the first contact pad and the second contact pad and a capacitive electrical pathway between the first contact pad and the second contact pad. The resistive electrical pathway and the capacitive electrical pathway form an equivalent parallel resistor-capacitor (RC) equalization circuit. 1. A stacked and electrically interconnected structure comprising:a first element comprising a first contact pad; anda second element comprising a second contact pad,the first contact pad and the second contact pad being electrically and mechanically connected to one another by an interface structure, the interface structure comprising a passive equalization circuit that includes a resistive electrical pathway between the first contact pad and the second contact pad and a capacitive electrical pathway between the first contact pad and the second contact pad.2. The structure of claim 1 , wherein the resistive electrical pathway comprises a conductive interface feature between the first contact pad and the second contact pad claim 1 , and wherein the capacitive electrical pathway comprises a first dielectric gap between the first contact pad and the second contact pad.3. The structure of claim 2 , wherein the first dielectric gap is disposed about the conductive interface feature.4. The structure of claim 2 , wherein the conductive interface feature comprises an elongate interface feature in which a length of the elongate interface feature is greater than a width of the elongate interface feature.5. The structure of claim 4 , wherein ...

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Номер записи: 33

12-05-2022 дата публикации

Semiconductor device structure with bottle-shaped through silicon via and method for forming the same

Номер: US20220148995A1

Автор: Shing-Yih Shih, Tse-Yao Huang

Принадлежит: Nanya Technology Corp

A semiconductor device structure includes a silicon layer disposed over a first semiconductor die, and a first mask layer disposed over the silicon layer. The semiconductor device structure also includes a second semiconductor die disposed over the first mask layer, and a through silicon via penetrating through the silicon layer and the first mask layer. A bottom surface of the through silicon via is greater than a top surface of the through silicon via, and the top surface of the through silicon via is greater than a cross-section of the through silicon via between and parallel to the top surface and the bottom surface of the through silicon via.

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Номер записи: 34

02-06-2022 дата публикации

SEMICONDUCTOR CHIP HAVING CHIP PADS OF DIFFERENT SURFACE AREAS, AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

Номер: US20220173061A1

Автор: CHO Hyung Ho, EOM Ju Il, Lee Woo Jin

Принадлежит: SK HYNIX INC.

A semiconductor chip includes a chip body including a signal input/output circuit unit, a chip pad unit disposed on one surface of the chip body and including first and second chip pads having different surface areas from each other, and a chip pad selection circuit unit disposed in the chip body and electrically connected to the signal input/output circuit unit and the chip pad unit. The chip pad selection circuit unit is configured to select one chip pad of the first and second chip pads and electrically connect the selected one chip pad to the signal input/output circuit unit. 1. A semiconductor chip comprising:a chip body including a signal input/output circuit unit;a chip pad unit disposed on a surface of the chip body and including first and second chip pads having different surface areas from each other; anda chip pad selection circuit unit disposed in the chip body and electrically connected to the signal input/output circuit unit and the chip pad unit,wherein the chip pad selection circuit unit is configured to select one chip pad of the first and second chip pads and electrically connect the selected one chip pad to the signal input/output circuit unit.2. The semiconductor chip of claim 1 , wherein the chip pad selection circuit unit is further configured to electrically open the other chip pad not selected among the first and second chip pads from the signal input/output circuit unit.3. The semiconductor chip of claim 1 , wherein each of the first and second chip pads has a surface area and a parasitic capacitance proportional to the surface area.4. The semiconductor chip of claim 1 , wherein the chip pad selection circuit unit is configured to electrically connect the signal input/output circuit unit to the selected one chip pad based on a control signal provided to the chip pad selection circuit unit.5. A semiconductor package comprising:a package substrate; anda semiconductor chip disposed on the package substrate, a substrate body; and', 'a plurality ...

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Номер записи: 35

02-06-2022 дата публикации

Hybrid Bonding with Uniform Pattern Density

Номер: US20220173092A1

Автор: Chen Szu-Ying, Yaung Dun-Nian

Принадлежит:

A chip includes a semiconductor substrate, integrated circuits with at least portions in the semiconductor substrate, and a surface dielectric layer over the integrated circuits. A plurality of metal pads is distributed substantially uniformly throughout substantially an entirety of a surface of the chip. The plurality of metal pads has top surfaces level with a top surface of the surface dielectric layer. The plurality of metal pads includes active metal pads and dummy metal pads. The active metal pads are electrically coupled to the integrated circuits. The dummy metal pads are electrically decoupled from the integrated circuits. 1. An integrated circuit structure comprising: a semiconductor substrate;', a first portion underlying and contacting the semiconductor substrate; and', 'a second portion extending laterally beyond opposing edges of the semiconductor substrate; and, 'a first dielectric layer comprising, first metal pads overlapped by the semiconductor substrate; and', 'second metal pads overlapped by the second portion of the first dielectric layer., 'a first plurality of metal pads distributed substantially uniformly, wherein the first plurality of metal pads comprise], 'a first chip comprising2. The integrated circuit structure of further comprising:a second dielectric layer over and contacting the second portion of the first dielectric layer, wherein additional opposing edges of the second dielectric layer contact the opposing edges of the semiconductor substrate to form vertical interfaces.3. The integrated circuit structure of claim 1 , wherein the first plurality of metal pads are distributed to an area more than about 90 percent of a chip area of the first chip.4. The integrated circuit structure of claim 1 , wherein the first plurality of metal pads are distributed to regions proximate edges of the first chip.5. The integrated circuit structure of claim 1 , wherein the first chip further comprises:a seal ring proximate edges of the first chip, ...

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Номер записи: 36

20-04-2017 дата публикации

SEMICONDUCTOR DEVICE WITH AN ANTI-PAD PEELING STRUCTURE AND ASSOCIATED METHOD

Номер: US20170110429A1

Автор: Cheng Chih-Kai, Hsieh Cheng-Chieh, Huang Shih-Wen

Принадлежит:

A semiconductor device with an anti-pad peeling structure is disclosed. The semiconductor device includes: a semiconductor substrate including a Through Substrate Via (TSV); a dielectric layer on the semiconductor substrate and including a plurality of recesses therein; and a pad above the semiconductor substrate to cover a portion of the dielectric layer and extend to the recesses; wherein the pad extends to the plurality of recesses, and a plurality of contact points are confined in the recesses between the pad and the conductive layer, and each of the contact points is at least partially excluded from a boundary of the TSV when being seen from a top-down perspective. 1. A semiconductor device with an anti-pad peeling structure , comprising:a semiconductor substrate comprising a Through Substrate Via (TSV) including a conductive portion;a dielectric layer on the semiconductor substrate and comprising a plurality of recesses therein; anda pad above the semiconductor substrate to cover a portion of the dielectric layer and extend to the recesses,wherein from a top-down perspective the pad fully covers the TSV, and a distance between an edge of the pad and the outermost edge of the recesses is greater than a specified length;wherein a plural portion of the plurality of the recesses has planar boundaries that partially overlap that of the conductive portion of the TSV; and for the recesses that partially overlap the conductive portion of the TSV, an overlap ratio is less than a specified ratio of an area of the recess.2. The semiconductor device of claim 1 , further comprising:a conductive layer on the TSV;wherein the pad is extended to the conductive layer through the recesses so that the pad is electrically connected to the TSV.4. The semiconductor device of claim 2 , wherein the conductive layer comprises copper (Cu).5. The semiconductor device of claim 1 , wherein the specified length is about 2 μm.6. (canceled)7. The semiconductor device of claim 1 , wherein the ...

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Номер записи: 37

11-04-2019 дата публикации

Diffusion barrier collar for interconnects

Номер: US20190109042A1

Автор: Cyprian Emeka Uzoh, Rajesh Katkar

Принадлежит: Invensas Bonding Technologies Inc

Representative implementations of techniques and devices are used to reduce or prevent conductive material diffusion into insulating or dielectric material of bonded substrates. Misaligned conductive structures can come into direct contact with a dielectric portion of the substrates due to overlap, especially while employing direct bonding techniques. A barrier interface that can inhibit the diffusion is disposed generally between the conductive material and the dielectric at the overlap.

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Номер записи: 38

07-05-2015 дата публикации

PACKAGED SEMICONDUCTOR DEVICE

Номер: US20150123267A1

Автор: Chen Hsien-Wei, Kuo Hung-Yi, Lii Mirng-Ji, Tsai Hao-Yi

Принадлежит: Taiwan Semiconductor Manufacturing Company Ltd.

A semiconductor device with an under-bump metallurgy (UBM) over a dielectric is provided. The UBM has a trench configured to be offset from a central point of the UBM. A distance between a center of the trench to an edge of the UBM is larger than a distance between the center of the trench to an opposite edge of the UBM. A probe pin is configured to contact the UBM and collect measurement data. 1. A semiconductor device , comprising:an under-bump metallurgy (UBM) overlying a dielectric, the UBM having a trench,wherein the trench is offset from a central point of the UBM,wherein the trench has a base portion at a center of the trench,wherein the UBM has a first skirt and a second skirt, the first skirt being greater in dimension than the second skirt, and a terminal portion of the first skirt not being contacting with a conductive material.2. The semiconductor device according to claim 1 , wherein the base portion is substantially quadrilateral.3. The semiconductor device according to claim 1 , wherein the UBM is substantially quadrilateral.4. The semiconductor device according to claim 1 , wherein a first distance from the center of the trench to an edge of the UBM is larger than a second distance between the center of the trench to an opposite edge of the UBM.5. The semiconductor device according to claim 4 , wherein a difference between the first distance and the second distance is about 50 μm and about 100 μm.6. The semiconductor device according to claim 1 , wherein the trench has a perimeter portion next to the base portion claim 1 ,wherein a distance from an outer boundary of the perimeter portion to an edge of the UBM is different from a distance from an outer boundary of the base portion to an opposite edge of the UBM.7. The semiconductor device according to claim 1 , wherein the trench has a first perimeter portion and a second perimeter portion claim 1 , and the first perimeter portion and the second perimeter portion are at opposites sides of the base ...

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Номер записи: 39

03-05-2018 дата публикации

DISPLAY APPARATUS AND METHOD FOR BINDING THE SAME

Номер: US20180122758A1

Автор: CHEN Liqiang, Zhou Huiji

Принадлежит:

Embodiments of the present application provide a display apparatus and a method for binding the same. The apparatus includes: a flexible display panel; and a chip on film bound on a binding region of the flexible display panel. The chip on film has at least two rows of output pads and the flexible display panel has at least two rows of input pads. Virtual elongation lines of all of the output pads intersect at a same intersection point in a first datum line perpendicular to the first direction. The output pads are electrically connected to the input pads and the output pads and the input pads have the virtual elongation lines at a same angle with respect to a common datum line, the common datum line being composed of the first datum line and the second datum line coinciding with each other. 1. A display apparatus , comprising:a flexible display panel; anda chip on film bound on a binding region of the flexible display panel;wherein the chip on film has at least two rows of output pads separated from each other, the at least two rows of output pads being arranged along a first direction, and virtual elongation lines of all of the output pads intersect at a same intersection point in a first datum line perpendicular to the first direction, and wherein in a same row of output pads, the farther a distance between the virtual elongation line of the output pad and the first datum line is, the larger an angle between said virtual elongation line and the first datum line becomes;wherein the flexible display panel has at least two rows of input pads separated from each other, the at least two rows of input pads being arranged along the first direction, and the input pads are in one to one correspondence with the output pads, and wherein virtual elongation lines of all of the input pads intersect at a same intersection point in a second datum line perpendicular to the first direction, and wherein in a same row of input pads, the farther a distance between the virtual ...

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Номер записи: 40

25-04-2019 дата публикации

Stacked Semiconductor Structure and Method

Номер: US20190123026A1

Автор: Chen Szu-Ying, Wan Meng-Hsun, Yaung Dun-Nian

Принадлежит:

A device comprises a first chip comprising a first connection pad embedded in a first dielectric layer and a first bonding pad embedded in the first dielectric layer, wherein the first bonding pad comprises a first portion and a second portion, the second portion being in contact with the first connection pad and a second chip comprising a second bonding pad embedded in a second dielectric layer of the second chip, wherein the first chip and the second chip are face-to-face bonded together through the first bonding pad the second bonding pad. 1. A device comprising: a first connection pad embedded in a first dielectric layer; and', 'a first bonding pad embedded in the first dielectric layer, wherein the first bonding pad comprises a first portion and a second portion, the second portion being in contact with the first connection pad; and, 'a first chip comprisinga second chip comprising a second bonding pad embedded in a second dielectric layer of the second chip, wherein the first chip and the second chip are face-to-face bonded together through the first bonding pad the second bonding pad.2. The device of claim 1 , wherein:a width of the first connection pad is greater than a width of the second portion of the first bonding pad; anda width of the first portion of the first bonding pad is greater than the width of the second portion of the first bonding pad.3. The device of claim 1 , wherein:a width of the second bonding pad is greater than a width of the first portion of the first bonding pad.4. The device of claim 1 , further comprising:a homogeneous layer between the first bonding pad and the second bonding pad, wherein the homogeneous layer is formed through an inter-diffusion process between the first bonding pad and the second bonding pad.5. The device of claim 1 , wherein:the second portion of the first bonding pad is a connector between the first portion of the first bonding pad and the first connection pad.6. The device of claim 5 , wherein:the connector ...

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Номер записи: 41

11-05-2017 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

Номер: US20170133339A1

Автор: Chen Hsien-Wei, Kuo Hung-Yi, Lii Mirng-Ji, Tsai Hao-Yi

Принадлежит:

A semiconductor device with an under-bump metallurgy (UBM) over a dielectric is provided. The UBM has a trench configured to be offset from a central point of the UBM. A distance between a center of the trench to an edge of the UBM is larger than a distance between the center of the trench to an opposite edge of the UBM. A probe pin is configured to contact the UBM and collect measurement data. 1. A semiconductor device , comprising:an interconnecta dielectric layer overlying the interconnect having an opening defined therein that exposes a portion of the interconnect; andan under-bump metallurgy (UBM) overlying a top surface of the dielectric layer, the UBM comprising a trench structure that is offset from a central point of the UBM and electrically connects the interconnect through the opening;wherein the UBM comprises a first skirt on one end and a second skirt on the other end, the first skirt having a greater dimension than that of the second skirt,wherein the trench structure comprises a partially tapered shape defined by a substantially flat base portion and only one angled perimeter portion, andwherein the only one angled perimeter portion is proximal to the first skirt.2. The semiconductor device of claim 1 , wherein the trench structure comprises a trench set having a first trench and a second trench.3. The semiconductor device of claim 2 , wherein a length between the first trench and the second trench is in a range of from about 30 μm to about 45 μm..4. The semiconductor device of claim 1 , wherein a top surface of the first skirt and a top surface of the second skirt being free of material formed directly on it.5. The semiconductor device of claim 1 , wherein a length of the first skirt is in a range of from about 50 μm to about 200 μm.6. The semiconductor device of claim 5 , wherein a length of the second skirt is in a range of from about 10 μm to about 50 μm.7. The semiconductor device of claim 2 , further comprising a bump disposed in one of the ...

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Номер записи: 42

17-05-2018 дата публикации

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD, SOLID STATE IMAGE SENSOR, AND ELECTRONIC EQUIPMENT

Номер: US20180138224A1

Автор: Haneda Masaki

Принадлежит:

The present disclosure relates to a semiconductor device, a manufacturing method, a solid state image sensor, and electronic equipment that can achieve further improvement in reliability. Connection pads are formed in interlayer films provided respectively in interconnection layers of a sensor substrate on which a sensor surface having pixels is formed and a signal processing substrate configured to perform signal processing on the sensor substrate to make an electrical connection between the sensor substrate and the signal processing substrate. Then, a metal oxide film is formed between the interlayer films of the sensor substrate and the signal processing substrate, between the connection pad formed on a side toward the sensor substrate and the interlayer film on a side toward the signal processing substrate, and between the connection pad formed on the side toward the signal processing substrate and the interlayer film on the side toward the sensor substrate. The present technology can be applied to a laminated-type CMOS image sensor, for example. 1. A semiconductor device comprising:connection pads formed in interlayer films provided respectively in interconnection layers of a first semiconductor substrate and a second semiconductor substrate to make an electrical connection between the first semiconductor substrate and the second semiconductor substrate; anda metal oxide film formed between the interlayer films of the first semiconductor substrate and the second semiconductor substrate, between the connection pad formed on a side toward the first semiconductor substrate and the interlayer film on a side toward the second semiconductor substrate, and between the connection pad formed on the side toward the second semiconductor substrate and the interlayer film on the side toward the first semiconductor substrate.2. The semiconductor device according to claim 1 , whereina metal film is formed on at least one bonding surface of a bonding surface including the ...

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Номер записи: 43

26-05-2016 дата публикации

Bonding Pad on a Back Side Illuminated Image Sensor

Номер: US20160148967A1

Автор: CHEN Hsin-Chi, CHEN I-CHIH, CHEN Ying-Hao, CHIEN Volume, Huang Hung-Ta, Wang Ying-Lang

Принадлежит:

A bonding pad structure comprises an interconnect layer, an isolation layer over the interconnect layer, a conductive pad, and one or more non-conducting stress-releasing structures. The conductive pad comprises a planar portion over the isolation layer, and one or more bridging portions extending through at least the isolation layer and to the interconnect layer for establishing electric contact therewith, wherein there is a trench in the one or more bridging portions. The one or more non-conducting stress-releasing structures are disposed between the isolation layer and the conductive pad. The trench is surrounded by one of the one or more non-conducting stress-releasing structures from a top view. 1. A bonding pad structure , comprising:an interconnect layer;an isolation layer over the interconnect layer; a planar portion over the isolation layer, and', 'one or more bridging portions extending through at least the isolation layer and to the interconnect layer for establishing electric contact therewith, wherein there is a trench in the one or more bridging portions; and, 'a conductive pad comprisingone or more non-conducting stress-releasing structures disposed between the isolation layer and the conductive pad, wherein the trench is surrounded by one of the one or more non-conducting stress-releasing structures from a top view.2. The bonding pad structure of claim 1 , wherein the one or more non-conducting stress-releasing structures comprise an oxide.3. The bonding pad structure of claim 1 , wherein the one or more non-conducting stress-releasing structures are made of the same material as the isolation layer.4. The image sensor device of claim 1 , wherein each of the one or more non-conducting stress-releasing structures has a configuration of a generally rectangular wall.5. The bonding pad structure of claim 1 , further comprising a conductive ball bonded with the planar portion of the conductive pad.6. The bonding pad structure of claim 5 , wherein the ...

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Номер записи: 44

02-06-2016 дата публикации

PACKAGE SUBSTRATE, SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

Номер: US20160155716A1

Автор: Chiu Shih-Chao, Lin Chun-Hsien, Pai Yu-Cheng, SHEN TZU-CHIEH, Sun Ming-Chen

Принадлежит:

A package substrate and a semiconductor package are provided. The package substrate includes an insulating layer having opposing first and second surfaces; a first wiring layer formed in the insulating layer, exposed from the first surface of the insulating layer, and having a plurality of first conductive pads; a second wiring layer formed in the insulating layer, exposed from the second surface, and having a plurality of second conductive pads; a third wiring layer formed on the first surface and electrically connected with the first wiring layer; a plurality of first metal bumps formed on the first conductive pads corresponding; and at least one conductive via vertically embedded in the insulating layer and electrically connected to the second and third wiring layers. Therefore, the surfaces of first conductive pads are reduced, and the non-wetting between the first conductive pads and the solder materials formed on conductive bumps is avoided. 1. A package substrate , comprising:an insulating layer having opposing first and second surfaces;a first wiring layer embedded in the insulating layer, exposed from the first surface, and having a plurality of first conductive pads;a second wiring layer embedded in the insulating layer, exposed from the second surface, and having a plurality of second conductive pads;a third wiring layer formed on the first surface and electrically connected with the first wiring layer;a plurality of first metal bumps formed on the first conductive pads correspondingly; andat least one conductive via embedded in the insulating layer and electrically connected with the second wiring layer and the third wiring layer.2. The package substrate of claim 1 , wherein each of the first metal bumps has an area projected onto the first surface that is less than an area of a corresponding one of the first conductive pads.3. The package substrate of claim 1 , wherein the first wiring layer has an exposed surface lower than the first surface.4. The ...

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Номер записи: 45

02-06-2016 дата публикации

Methods of manufacturing a semiconductor device

Номер: US20160155862A1

Автор: Byung-lyul Park, Joo-Hee Jang, Yeun-Sang Park, Yi-koan Hong

Принадлежит: SAMSUNG ELECTRONICS CO LTD

In a method for fabricating a semiconductor, a first conductive pattern structure partially protruding upwardly from first insulating interlayer is formed in first insulating interlayer. A first bonding insulation layer pattern covering the protruding portion of first conductive pattern structure is formed on first insulating interlayer. A first adhesive pattern containing a polymer is formed on first bonding insulation layer pattern to fill a first recess formed on first bonding insulation layer pattern. A second bonding insulation layer pattern covering the protruding portion of second conductive pattern structure is formed on second insulating interlayer. A second adhesive pattern containing a polymer is formed on second bonding insulation layer pattern to fill a second recess formed on second bonding insulation layer pattern. The first and second adhesive patterns are melted. The first and second substrates are bonded with each other so that the conductive pattern structures contact each other.

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Номер записи: 46

31-05-2018 дата публикации

Semiconductor package structure

Номер: US20180151499A1

Автор: Hsien-Wei Chen, Jie Chen

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Semiconductor package structures are provided. A semiconductor package structure includes a chip, a molding material surrounding the chip, a through-via extending from a first surface to a second surface of the molding material, a first re-distribution layer (RDL) wire disposed on the second surface of the molding material and coupled to the through-via, and a second RDL wire disposed on the second surface of the molding material and parallel to the first RDL wire. The second surface is opposite to the first surface. A portion of the second RDL wire across the through-via has a first segment with a first width and a second segment with a second width different from the first width.

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Номер записи: 47

17-06-2021 дата публикации

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD, SOLID STATE IMAGE SENSOR, AND ELECTRONIC EQUIPMENT

Номер: US20210183661A1

Автор: Haneda Masaki

Принадлежит: SONY CORPORATION

Connection pads are formed in interlayer films provided respectively in interconnection layers of a sensor substrate on which a sensor surface having pixels is formed and a signal processing substrate configured to perform signal processing on the sensor substrate to make an electrical connection between the sensor substrate and the signal processing substrate. Then, a metal oxide film is formed between the interlayer films of the sensor substrate and the signal processing substrate, between the connection pad formed on a side toward the sensor substrate and the interlayer film on a side toward the signal processing substrate, and between the connection pad formed on the side toward the signal processing substrate and the interlayer film on the side toward the sensor substrate. The present technology can be applied to a laminated-type CMOS image sensor, for example. 111-. (canceled)12. A semiconductor device comprising:a sensor substrate including a photodiode, a transistor, and a first wiring layer; anda circuit substrate including a signal processing circuit and a second wiring layer, the sensor substrate being stacked on the circuit substrate,wherein the first wiring layer includes a first connection pad and a first insulating film,wherein the second wiring layer includes a second connection pad and a second insulating film,wherein a first portion of a first barrier metal contacts a first portion of the second connection pad,wherein a first portion of the first connection pad contacts a second portion of the second connection pad,wherein a second portion of the first connection pad contacts a first portion of a barrier film,wherein a second portion of the first barrier metal contacts a second portion of the barrier film, andwherein the first portion of the first barrier metal and the second portion of the first barrier metal are on opposite sides of the first connection pad.13. The semiconductor device according to claim 12 , wherein claim 12 , in a cross ...

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Номер записи: 48

07-06-2018 дата публикации

Semiconductor device having semiconductor chip with large and small irregularities on upper and lower side surface portions thereof

Номер: US20180158792A1

Автор: Makoto TAKESAWA

Принадлежит: Ablic Inc

A semiconductor device has a semiconductor chip adhesively bonded to a die pad. An area having large irregularities is formed on an upper side surface of the semiconductor chip to be covered by an encapsulating resin, and an area having small irregularities is formed on a lower side surface of the semiconductor chip, thereby improving adhesive strength between the semiconductor chip and the encapsulating resin and preventing penetration of moisture from outside.

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Номер записи: 49

22-09-2022 дата публикации

Semiconductor device

Номер: US20220302055A1

Автор: Kotaro Fujii, Shinya Watanabe

Принадлежит: Kioxia Corp

According to one or more embodiments, a semiconductor device includes a first substrate and a second substrate. The first substrate includes a first metal layer and a first insulating layer. The first insulating layer surrounds the first metal layer. The second substrate includes a second metal layer, a second insulating layer, and a first conducive body. The second metal layer is in contact with the first metal layer. The second insulating layer surrounds the second metal layer and is in contact with the first insulating layer. A part of the first conductive body is in the second metal layer and extends in a first direction toward the first metal layer.

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Номер записи: 50

23-05-2019 дата публикации

Method for Manufacturing Chip Cards and Chip Card Obtained by Said Method

Номер: US20190157223A1

Автор: EYMARD Eric, PROYE Cyril

Принадлежит: Linxens Holding

The invention relates to a chip card manufacturing method. According to this method, there are produced on the one hand, a module including a substrate supporting contacts on one face, and bonding pads on the other, on the other hand, an antenna on a support. The ends of the antenna are linked to lands of connection lands receiving a drop of soldering material on a connection portion. In order to make the soldered electrical connection between the module and the antenna reliable, the bonding pads extend over a zone covering a surface area less than that of the connection portions. The invention relates also to a chip card whose module includes bonding pads extending over a zone covering a surface area less than that of the connection portions. 1. A method for manufacturing a chip card , comprising:the production of a chip card module comprising a substrate having a first and a second main faces, with contacts on the first face of the substrate and bonding pads on the second face of the substrate, this module being also provided with an electronic chip connected to at least some contacts and to at least two conductive tracks dedicated to an antenna connection,the production of an antenna comprising two ends,the lamination of the antenna between layers of plastic material, andthe placement of the module in a cavity formed in at least some of the layers of plastic material,the connection, using a soldering material deposited on a portion of connection of each of the ends of the antenna with a bonding pads of the module, and heated up, once the module is in place in the cavity,characterized by the fact that bonding pads are each produced on a zone covering a surface area less than that of a connection portion covered with soldering material.2. The method as claimed in claim 1 , in which at least one of the bonding pads is produced comprising at least one bar extending longitudinally in a direction (L) over a length of between 1 and 7 mm.3. The method as claimed in claim ...

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Номер записи: 51

15-06-2017 дата публикации

THREE DIMENSIONAL DEVICE INTEGRATION METHOD AND INTEGRATED DEVICE

Номер: US20170170132A1

Автор: ENQUIST Paul M., FOUNTAIN, JR. Gaius Gillman

Принадлежит:

A method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed. 1. (canceled)2. An integration method , comprising:preparing a first element having a first layer of bondable material for direct bonding;preparing a second element for direct bonding;bringing into direct contact the first layer of bondable material with the second element;directly bonding the first layer of bondable material to the second element with a covalent bond at room temperature; andafter the bonding, removing a portion of the first element by one of polishing and grinding to leave a remaining portion of the first element.3. The method of claim 2 , further comprising polishing the first layer of bondable material prior to bring into direct contact.4. The method of claim 2 , wherein preparing the first layer of bondable material comprises providing the first layer of bondable material with a surface roughness less than about 1 nm (rms) on the first element.5. The method of claim 4 , wherein preparing the second element comprises providing a surface of the second element with a surface roughness less than about 1 nm (rms) on the second element).6. The method of claim 2 , further comprising providing a second layer of bondable material over the first layer of bondable material claim 2 , the second layer of bondable material having ...

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Номер записи: 52

29-09-2022 дата публикации

Integrated fan-out (info) package structure

Номер: US20220310519A1

Автор: Hung-Jui Kuo, Ming-Che Ho, Tzung-Hui Lee

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Provided is an integrated fan-out (InFO) package structure including a first die, a second die, a third die, a protective layer, and an interconnect structure. The first die has a first surface and a second surface opposite to each other. The first die has a plurality of through substrate vias (TSVs) protruding from the second surface. The second die and the third die are bonded on the first surface of the first die. The protective layer laterally surrounds protrusions of the plurality of TSVs that protrude from the second surface. The interconnect structure are disposed on the protective layer and electrically connected to the plurality of TSVs. The interconnect structure includes a polymer layer covering the protective layer.

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Номер записи: 53

29-09-2022 дата публикации

SEMICONDUCTOR DEVICE WITH THROUGH SEMICONDUCTOR VIA AND METHOD FOR FABRICATING THE SAME

Номер: US20220310580A1

Автор: CHIU Hsih-Yang

Принадлежит:

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure, a second semiconductor structure, a through semiconductor via, and an insulation layer. The first semiconductor structure includes a first circuit layer and a first main bonding layer in the first circuit layer and substantially coplanar with a front face of the first circuit layer. The second semiconductor structure includes a second circuit layer on the first circuit layer and a second main bonding layer in the second circuit layer, and topologically aligned with and contacted to the first main bonding layer. The through semiconductor via is along the second semiconductor structure and the first and second main bonding layer, and extending to the first circuit layer. The insulation layer is positioned on a sidewall of the through semiconductor via. 1. A semiconductor device , comprising:a first semiconductor structure comprising a first circuit layer positioned on a first substrate, and a first main bonding layer positioned in the first circuit layer and substantially coplanar with a front face of the first circuit layer;a second semiconductor structure comprising a second circuit layer positioned on the first circuit layer, a second substrate positioned on the second circuit layer, and a second main bonding layer positioned in the second circuit layer, and topologically aligned with and contacted to the first main bonding layer;a through semiconductor via positioned along the second semiconductor structure and the first main bonding layer, extending to the first circuit layer, and physically and electrically coupled to a corresponding conductive line in the first circuit layer; andan insulation layer positioned between the second semiconductor structure and the through semiconductor via, between the first main bonding layer and the through semiconductor via, and between the first circuit ...

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Номер записи: 54

02-07-2015 дата публикации

Semiconductor device and method comprising thickened redistribution layers

Номер: US20150187710A1

Автор: Christopher M. Scanlan, Craig Bishop

Принадлежит: DECA Technologies Inc

A method of making a semiconductor package can comprise forming a plurality of thick redistribution layer (RDL) traces over active surfaces of a plurality of semiconductor die that are electrically connected to contact pads on the plurality of semiconductor die, singulating the plurality of semiconductor die comprising the plurality of thick RDL traces, mounting the singulated plurality of semiconductor die over a temporary carrier with the active surfaces of the plurality of semiconductor die oriented away from the temporary carrier, disposing encapsulant material over the active surfaces and at least four side surfaces of each of the plurality of semiconductor die, over the plurality of thick RDL traces, and over the temporary carrier, forming a via through the encapsulant material to expose at least one of the plurality of thickened RDL traces with respect to the encapsulant material, removing the temporary carrier, and singulating the plurality of semiconductor die.

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Номер записи: 55

08-07-2021 дата публикации

Solid-state imaging device, method of manufacturing solid-state imaging device, and electronic apparatus

Номер: US20210210541A1

Автор: Yukihiro Ando

Принадлежит: Sony Semiconductor Solutions Corp

A solid-state imaging device capable of preventing variation in bonding strength in a bonding plane between a first semiconductor substrate and a second semiconductor substrate is provided. The solid-state imaging device includes a first semiconductor substrate having a plurality of first conductors, and a second semiconductor substrate bonded to the first semiconductor substrate and having a plurality of second conductors. In a bonding plane between the first and second semiconductor substrates, the device includes regions where the conductors overlap, regions where insulating films and the conductors overlap, and regions where the insulating films overlap. The proportion of areas where the first insulating films and the second insulating films are bonded together to the bonding area between the first semiconductor substrate and the second semiconductor substrate is constant before and after the first semiconductor substrate and the second semiconductor substrate are bonded together.

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Номер записи: 56

09-07-2015 дата публикации

Bond pad having a trench and method for forming

Номер: US20150194396A1

Автор: David B. Clegg, Sohrab Safai, Tu-Anh N. Tran

Принадлежит: Individual

A conductive structure is formed in a last metal layer of an integrated circuit. Passivation material is patterned over a portion of the conductive structure. A first trench is patterned around a selected portion of the passivation material. The selected portion represents a bond region of a wire bond to be formed above the passivation material. A portion of the passivation material completely covers a bottom of the trench. A layer of conductive material is conformally deposited over the passivation material. The conformal depositing resulting in a second trench forming in the conductive material over the first trench in the passivation material. The second trench is positioned to contain at least a portion of a splash of the conductive material when the wire bond is subsequently formed.

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Номер записи: 57

16-07-2015 дата публикации

Package Having Substrate With Embedded Metal Trace Overlapped by Landing Pad

Номер: US20150200172A1

Автор: Chen Yu-Feng, LIANG Yu-Min, Lii Mirng-Ji

Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

An embodiment package includes a conductive pillar mounted on an integrated circuit chip, the conductive pillar having a stepper shape, a metal trace partially embedded in a substrate, the metal trace having a bonding pad portion protruding from the substrate, and a solder feature electrically coupling the conductive pillar to the bonding pad portion of the metal trace. 1. A package , comprising:a conductive pillar mounted on an integrated circuit chip, the conductive pillar having a stepper shape;a metal trace partially embedded in a substrate, the metal trace having a bonding pad portion protruding from the substrate; anda solder feature electrically coupling the conductive pillar to the bonding pad portion of the metal trace.2. The package of claim 1 , wherein the bonding pad portion has a stepper shape.3. The package of claim 1 , wherein the bonding pad portion has an inverted stepper shape.4. The package of claim 1 , wherein a diameter of the bonding pad portion tapers from top to bottom.5. The package of claim 1 , wherein a diameter of the bonding pad portion tapers from bottom to top.6. The package of claim 1 , wherein a top width of the bonding pad portion is less than a bottom width of the bonding pad portion.7. The package of claim 1 , wherein a top width of the bonding pad portion is greater than a bottom width of the bonding pad portion.8. The package of claim 1 , wherein the bonding pad portion utilizes a stepper shape when a formula b−a>0.36h−0.1 is satisfied claim 1 , where b is a bottom width of the bonding pad portion claim 1 , a is a top width of the bonding pad portion claim 1 , and his a height of the bonding pad portion.9. The package of claim 1 , wherein the bonding pad portion utilizes an inverted stepper shape when a formula a−b>0.36h−0.1 is satisfied claim 1 , where a is a top width of the bonding pad portion claim 1 , b is a bottom width of the bonding pad portion claim 1 , and his a height of the bonding pad portion.10. The package of ...

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Номер записи: 58

05-07-2018 дата публикации

BONDED STRUCTURES WITH INTEGRATED PASSIVE COMPONENT

Номер: US20180190580A1

Автор: Delacruz Javier A., Guevara Gabriel Z., Haba Belgacem, Huang Shaowu, Katkar Rajesh, Mirkarimi Laura Wills, Mohammed Ilyas

Принадлежит:

In various embodiments, a bonded structure is disclosed. The bonded structure can include an element and a passive electronic component having a first surface bonded to the element and a second surface opposite the first surface. The passive electronic component can comprise a first anode terminal bonded to a corresponding second anode terminal of the element and a first cathode terminal bonded to a corresponding second cathode terminal of the element. The first anode terminal and the first cathode terminal can be disposed on the first surface of the passive electronic component. 1. A microelectronic device comprising:a first insulating substrate;a capacitor having a first surface and a second surface opposite the first surface, the first surface of the capacitor mechanically coupled to the first insulating substrate;a second insulating substrate, the second surface of the capacitor mechanically coupled to the second insulating substrate such that the capacitor is disposed between the first and second insulating substrates;an insulating element disposed between the first and second insulating substrates; anda first interconnect extending through the first insulating substrate to electrically connect to a first terminal of the capacitor.2. The microelectronic device of claim 1 , wherein the first surface of the capacitor is mechanically coupled to the first insulating substrate by way of a first adhesive.3. The microelectronic device of claim 2 , wherein the second surface of the capacitor is mechanically coupled to the second insulating substrate by way of a second adhesive claim 2 , the insulating element further comprising the second adhesive.4. The microelectronic device of claim 2 , wherein the first adhesive comprises solder.5. The microelectronic device of claim 1 , wherein the insulating element comprises a molding compound disposed about portions of the capacitor.6. The microelectronic device of claim 1 , wherein the insulating element comprises a third ...

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Номер записи: 59

05-07-2018 дата публикации

Power semiconductor module

Номер: US20180190636A1

Автор: Yasushige Mukunoki, Yoshiko Tamada

Принадлежит: Mitsubishi Electric Corp

A power semiconductor module including a positive-side switching device and a positive-side diode device which are mounted on a positive-side conductive pattern, and a negative-side switching device and a negative-side diode device which are mounted on an output-side conductive pattern. When an insulating substrate is viewed in plan view, the positive-side diode device and the negative-side diode device are disposed between the positive-side switching device and the negative-side switching device, and the negative-side diode device is disposed closer to the positive-side switching device than the positive-side diode device is.

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Номер записи: 60

22-07-2021 дата публикации

Stacked Semiconductor Structure and Method

Номер: US20210225813A1

Автор: Chen Szu-Ying, Wan Meng-Hsun, Yaung Dun-Nian

Принадлежит:

A device comprises a first chip comprising a first connection pad embedded in a first dielectric layer and a first bonding pad embedded in the first dielectric layer, wherein the first bonding pad comprises a first portion and a second portion, the second portion being in contact with the first connection pad and a second chip comprising a second bonding pad embedded in a second dielectric layer of the second chip, wherein the first chip and the second chip are face-to-face bonded together through the first bonding pad the second bonding pad. 1. A device comprising: a first substrate;', 'a first insulating layer;', 'a first interconnect structure interposed between the first insulating layer and the first substrate;', 'a first aluminum connection pad embedded in the first insulating layer; and', 'a first copper bonding pad embedded in the first insulating layer, wherein the first aluminum connection pad directly contacts the first copper bonding pad; and, 'a first chip comprising a second substrate;', 'a second interconnect structure;', 'a second insulating layer, the second interconnect structure being interposed between the second insulating layer and the second substrate; and', 'a second copper bonding pad embedded in the second insulating layer of the second chip, wherein the first chip and the second chip are face-to-face bonded together through the first copper bonding pad and the second copper bonding pad, wherein the first copper bonding pad and the second copper bonding pad comprise a single homogenous copper layer., 'a second chip comprising2. The device of claim 1 , further comprising an external connection pad contacting the second interconnect structure claim 1 , wherein the second interconnect structure is interposed between the external connection pad and the first chip.3. The device of claim 1 , wherein a width of the first copper bonding pad is different than a width of the second copper bonding pad.4. The device of claim 1 , wherein a width of at ...

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Номер записи: 61

21-07-2016 дата публикации

Hybrid Bonding with Uniform Pattern Density

Номер: US20160211248A1

Автор: Dun-Nian Yaung, Szu-Ying Chen

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A chip includes a semiconductor substrate, integrated circuits with at least portions in the semiconductor substrate, and a surface dielectric layer over the integrated circuits. A plurality of metal pads is distributed substantially uniformly throughout substantially an entirety of a surface of the chip. The plurality of metal pads has top surfaces level with a top surface of the surface dielectric layer. The plurality of metal pads includes active metal pads and dummy metal pads. The active metal pads are electrically coupled to the integrated circuits. The dummy metal pads are electrically decoupled from the integrated circuits.

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Номер записи: 62

20-07-2017 дата публикации

SEMICONDUCTOR DEVICE AND METHOD

Номер: US20170207184A1

Автор: Rusli Sukianto

Принадлежит:

Disclosed herein is a semiconductor device that includes a semiconductor die and a substrate including a first surface and a second surface. The substrate includes a conductive circuit and an insulative material over the conductive circuit. The semiconductor die is attached to the second surface. The semiconductor device further includes a metal barrier layer plated onto a functional copper layer etched to form the conductive circuit. The conductive circuit has a thickness of less than or equal to 3 μm. Further disclosed is a method of making a semiconductor device. 1. A semiconductor device comprising:a semiconductor die;a substrate including a first surface and a second surface, the substrate comprising a conductive circuit and an insulative material over the conductive circuit, wherein the semiconductor die is attached to the second surface; anda metal barrier layer plated onto a functional copper layer etched to form the conductive circuit, wherein the conductive circuit has a thickness of less than or equal to 3 μm.2. The semiconductor device of claim 1 , wherein the conductive circuit includes an etched layer of conductive foil that is located on the first surface of the substrate.3. The semiconductor device of claim 1 , wherein the metal barrier layer has a thickness of less than or equal to 2 μm.4. The semiconductor device of claim 1 , wherein metal barrier layer is made of nickel.5. The semiconductor device of claim 1 , wherein the substrate is formed using a build-up process.6. The semiconductor device of claim 1 , wherein the substrate is formed using a subtractive process.7. The semiconductor device of claim 1 , wherein the conductive circuit has a thickness of less than or equal to 2 μm.8. The semiconductor device of claim 1 , wherein the substrate further includes an etched foil layer claim 1 , and wherein the substrate further includes a nickel layer etch stop barrier between the conductive circuit and the etched foil layer.9. The semiconductor device ...

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Номер записи: 63

20-07-2017 дата публикации

PATTERN DECOMPOSITION LITHOGRAPHY TECHNIQUES

Номер: US20170207185A1

Автор: ABDALLAH HOSSAM A., Bigwood Robert M., Golonzka Oleg, Sivakumar Swaminathan, Tan Elliot N., Wallace Charles H.

Принадлежит: Intel Corporation

Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated, substantially (e.g., fully) represent the original target feature without leaving an unrepresented remainder (e.g., a whole-number quantity of unidirectional target features). The unidirectional target features may be arbitrarily grouped such that, within a grouping, all unidirectional target features share a common target width value. Where multiple such groupings are provided, individual groupings may or may not have the same common target width value. In some cases, a series of reticles is provided, each reticle having a mask pattern correlating to a grouping of unidirectional target features. Exposure of a photoresist material via the aggregated series of reticles substantially (e.g., fully) produces the original target feature/pattern. The pattern decomposition techniques may be integrated into any number of patterning processes, such as litho-freeze-litho-etch and litho-etch-litho-etch patterning processes. 1. An integrated circuit , comprising:a layer of unidirectional linear features, such that substantially all of the linear features of the layer are linear features running in a first direction, the linear features including a first grouping of linear features and a second grouping of linear features;wherein the first grouping comprises a plurality of unidirectional linear features, each linear feature of the first grouping running in the first direction and having a first width;wherein the second grouping comprises a plurality of unidirectional linear features, each linear feature of the second grouping running in the first direction and having a second width;wherein the linear features of the first grouping are arranged in an interleaved fashion with the linear features of the second grouping, so as to provide a series of linear features, the series having an order and ...

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Номер записи: 64

04-07-2019 дата публикации

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD, SOLID STATE IMAGE SENSOR, AND ELECTRONIC EQUIPMENT

Номер: US20190206919A1

Автор: Haneda Masaki

Принадлежит: SONY CORPORATION

The present disclosure relates to a semiconductor device, a manufacturing method, a solid state image sensor, and electronic equipment that can achieve further improvement in reliability. Connection pads are formed in interlayer films provided respectively in interconnection layers of a sensor substrate on which a sensor surface having pixels is formed and a signal processing substrate configured to perform signal processing on the sensor substrate to make an electrical connection between the sensor substrate and the signal processing substrate. Then, a metal oxide film is formed between the interlayer films of the sensor substrate and the signal processing substrate, between the connection pad formed on a side toward the sensor substrate and the interlayer film on a side toward the signal processing substrate, and between the connection pad formed on the side toward the signal processing substrate and the interlayer film on the side toward the sensor substrate. The present technology can be applied to a laminated-type CMOS image sensor, for example. 1. A semiconductor device comprising:connection pads formed in interlayer films provided respectively in interconnection layers of a first semiconductor substrate and a second semiconductor substrate to make an electrical connection between the first semiconductor substrate and the second semiconductor substrate; anda metal oxide film formed between the interlayer films of the first semiconductor substrate and the second semiconductor substrate, between the connection pad formed on a side toward the first semiconductor substrate and the interlayer film on a side toward the second semiconductor substrate, and between the connection pad formed on the side toward the second semiconductor substrate and the interlayer film on the side toward the first semiconductor substrate.2. The semiconductor device according to claim 1 , whereina metal film is formed on at least one bonding surface of a bonding surface including the ...

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Номер записи: 65

13-08-2015 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20150228504A1

Автор: TAKESAWA Makoto

Принадлежит:

Provided is a semiconductor device having satisfactory moisture resistance. By forming an area () having large irregularities on an upper side surface of a semiconductor chip () to be covered by an encapsulating resin (), and an area () having small irregularities on a lower side surface of the semiconductor chip (), adhesive strength between the semiconductor chip () and the encapsulating resin () is improved, and penetration of moisture from outside is prevented. 1. A semiconductor device , comprising:a semiconductor chip;a die pad for supporting the semiconductor chip;an adhesive for adhering the semiconductor chip and the die pad;a plurality of signal leads extending toward a side of the die pad;bonding wires for connecting the semiconductor chip and the plurality of signal leads; andan encapsulating body for encapsulating with a mold resin,wherein a side surface of the semiconductor chip comprises a first irregular side surface and a second irregular side surface formed above the first irregular side surface, andwherein the second irregular side surface comprises second irregularities that are larger than first irregularities formed on the first irregular side surface.2. A semiconductor device according to claim 1 , wherein the second irregular side surface corresponds to two thirds or more of a thickness of the semiconductor chip.3. A method of manufacturing a semiconductor device comprising:a semiconductor chip;a die pad for supporting the semiconductor chip;an adhesive for adhering the semiconductor chip and the die pad;a plurality of signal leads extending toward a side of the die pad;bonding wires for connecting the semiconductor chip and the plurality of signal leads; andan encapsulating body for encapsulating with a mold resin,the method comprising:forming a first irregular side surface on a side surface of the semiconductor chip; andforming a second irregular side surface on the side surface of the semiconductor chip, the second irregular side surface ...

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Номер записи: 66

19-08-2021 дата публикации

Diffusion barrier collar for interconnects

Номер: US20210257253A1

Автор: Cyprian Emeka Uzoh, Rajesh Katkar

Принадлежит: Invensas Bonding Technologies Inc

Representative implementations of techniques and devices are used to reduce or prevent conductive material diffusion into insulating or dielectric material of bonded substrates. Misaligned conductive structures can come into direct contact with a dielectric portion of the substrates due to overlap, especially while employing direct bonding techniques. A barrier interface that can inhibit the diffusion is disposed generally between the conductive material and the dielectric at the overlap.

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Номер записи: 67

16-08-2018 дата публикации

Semiconductor apparatus and method for preparing the same

Номер: US20180233479A1

Автор: Chin-Lung Chu, Po-Chun Lin

Принадлежит: Nanya Technology Corp

The present disclosure is directed to a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique and a method for preparing the same. The semiconductor devices have conductive portions with higher coefficient of thermal expansion than their dielectric portions. By forming the depression to provide a space for the volume expansion of the conductive portion with higher coefficient of thermal expansion during the subsequent thermal treating process of the fusion bonding, the semiconductor apparatus formed of semiconductor devices by the fusion bonding technique does not exhibit a lateral protrusion into the interface between the two dielectric portions. As a result, the failure of the electrical function due to the lateral protrusion is effectively eliminated.

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Номер записи: 68

06-11-2014 дата публикации

CHIP PACKAGE AND METHOD FOR FORMING THE SAME

Номер: US20140328523A1

Автор: LIN Chao-Yen, LIN Yi-Hang

Принадлежит:

An embodiment of the invention provides a chip package which includes: a carrier substrate; a semiconductor substrate having an upper surface and a lower surface, disposed overlying the carrier substrate; a device region or sensing region located on the upper surface of the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to a sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate. 1. A chip package , comprising:a substrate having an upper surface and a lower surface;a recess adjacent to a sidewall of the substrate, wherein the recess is formed along a direction from the upper surface toward the lower surface of the substrate;a device region or sensing region of biological features located on the upper surface of the substrate;a conducting pad located on the upper surface of the substrate; anda conducting layer electrically connected to the conducting pad and extending to the recess along the sidewall of the substrate.2. The chip package as claimed in claim 1 , wherein the sidewall of the substrate inclines toward the upper surface of the substrate.3. The chip package as claimed in claim 1 , wherein the conducting pad is between the recess and the device region or sensing region.4. The chip package as claimed in claim 1 , wherein the conducting layer further extends on a bottom of the recess.5. The chip package as claimed in claim 4 , wherein the bottom of the recess is located beyond the lower surface of the substrate and substantially parallel to the upper surface of the substrate.6. The chip package as claimed in claim 5 , further comprising an insulating layer located between the conducting layer and the substrate.7. The chip package as claimed in claim 5 , further comprising a circuit board claim 5 , ...

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Номер записи: 69

16-07-2020 дата публикации

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD, SOLID STATE IMAGE SENSOR, AND ELECTRONIC EQUIPMENT

Номер: US20200227462A1

Автор: Haneda Masaki

Принадлежит: SONY CORPORATION

The present disclosure relates to a semiconductor device, a manufacturing method, a solid state image sensor, and electronic equipment that can achieve further improvement in reliability. Connection pads are formed in interlayer films provided respectively in interconnection layers of a sensor substrate on which a sensor surface having pixels is formed and a signal processing substrate configured to perform signal processing on the sensor substrate to make an electrical connection between the sensor substrate and the signal processing substrate. Then, a metal oxide film is formed between the interlayer films of the sensor substrate and the signal processing substrate, between the connection pad formed on a side toward the sensor substrate and the interlayer film on a side toward the signal processing substrate, and between the connection pad formed on the side toward the signal processing substrate and the interlayer film on the side toward the sensor substrate. The present technology can be applied to a laminated-type CMOS image sensor, for example. 111-. (canceled)12. A semiconductor device comprising:a sensor substrate including a photodiode, a transistor, and a first wiring layer; anda circuit substrate including a signal processing circuit and a second wiring layer, the sensor substrate being stacked on the circuit substrate,wherein the first wiring layer includes a first connection pad and a first insulating film,wherein the second wiring layer includes a second connection pad and a second insulating film,wherein the first connection pad and the second connection pad are disposed in a peripheral region other than a pixel region that includes the photodiode,wherein a first portion of a first barrier metal contacts a first portion of the second connection pad,wherein a first portion of the first connection pad contacts a second portion of the second connection pad,wherein a second portion of the first connection pad contacts a first portion of a barrier film, ...

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Номер записи: 70

26-08-2021 дата публикации

DISPLAY DEVICE

Номер: US20210265446A1

Автор: KIM Byeong Beom, KIM Min Ki, KIM Yu Ri, LEE Hoi Kwan, SEO Woo Suk

Принадлежит: Samsung Display Co., Ltd.

A display device includes a display panel including panel pads adjacent to the side surface of a display panel; connection pads disposed on the side surface of the display panel and connected to the panel pads; and a circuit board disposed on the side surface of the display panel and including lead signal lines directly bonded to the connection pads, wherein the connection pads include a first connection pad, a second connection pad disposed on the first connection pad, and a third connection pad disposed on the second connection pad, and the first connection pad is in contact with corresponding one of the panel pads, and the third connection pad is directly bonded to corresponding one of the lead signal lines. 1. A display device , comprising:a display panel including panel pads adjacent to a side surface of the display panel;connection pads disposed on the side surface of the display panel and connected to the panel pads; anda circuit board disposed on the side surface of the display panel, the circuit board including lead signal lines directly bonded to the connection pads, wherein a first connection pad;', 'a second connection pad disposed on the first connection pad; and', 'a third connection pad disposed on the second connection pad,, 'the connection pads includethe first connection pad is in contact with corresponding one of the panel pads, andthe third connection pad is directly bonded to corresponding one of the lead signal lines.2. The display device of claim 1 , wherein the third connection pad is ultrasonically bonded to the corresponding one of the lead signal lines.3. The display device of claim 2 , wherein an interface between the third connection pad and the corresponding one of the lead signal lines has a non-flat shape.4. The display device of claim 1 , wherein a melting point of the third connection pad is lower than a melting point of the second connection pad and a melting point of the first connection pad.5. The display device of claim 4 , ...

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Номер записи: 71

10-09-2015 дата публикации

DIE-TO-DIE BONDING AND ASSOCIATED PACKAGE CONFIGURATIONS

Номер: US20150255411A1

Автор: Alur Amruthavalli P., Karhade Omkar G., Mahajan Ravindranath V., Mallik Debendra

Принадлежит:

Embodiments of the present disclosure are directed towards die-to-die bonding and associated integrated circuit (IC) package configurations. In one embodiment, a package assembly includes a package substrate having a solder resist layer disposed on a first side and a second side disposed opposite to the first side, a first die mounted on the first side and having an active side that is electrically coupled with the package substrate by one or more first die-level interconnects and a second die bonded with the active side of the first die using one or more second die-level interconnects, wherein at least a portion of the second die is disposed in a cavity that extends into the solder resist layer. Other embodiments may be described and/or claimed. 1. A package assembly comprising:a package substrate having a solder resist layer disposed on a first side and a second side disposed opposite to the first side;a first die mounted on the first side and having an active side that is electrically coupled with the package substrate by one or more first die-level interconnects; anda second die bonded with the active side of the first die using one or more second die-level interconnects, wherein at least a portion of the second die is disposed in a cavity that extends into the solder resist layer.2. The package assembly of claim 1 , wherein:the cavity extends into a laminate layer of the package substrate that is disposed beneath the solder resist layer; andat least a portion of the second die is disposed in a portion of the cavity that extends into the laminate layer.3. The package assembly of claim 1 , further comprising:a third die mounted on the first side of the package substrate and having an active side that is electrically coupled with the package substrate by one or more third die-level interconnects, wherein the second die is bonded with the active side of the third die by one or more fourth die-level interconnects.4. The package assembly of claim 3 , wherein the ...

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Номер записи: 72

01-09-2016 дата публикации

Method of Manufacturing Semiconductor Device and Semiconductor Device

Номер: US20160254160A1

Автор: KASHIWAZAKI Tomoya

Принадлежит:

Reliability of a semiconductor device is improved. A power device includes: a semiconductor chip; a chip mounting part; a solder material electrically coupling a back surface electrode of the semiconductor chip with an upper surface of the chip mounting part; a plurality of inner lead parts and a plurality of outer lead parts electrically coupled with an electrode pad of the semiconductor chip through wires; and a sealing body for sealing the semiconductor chip and the wires. Further, a recess is formed in a peripheral region of the back surface of the semiconductor chip. The recess has a first surface extending to join the back surface and a second surface extending to join the first surface. Also, a metal film is formed over the first surface and the second surface of the recess. 1. A method of manufacturing a semiconductor device , comprising the steps of:(a) forming a concave in a first back surface on the side opposite to a first main surface along dicing lines formed over the first main surface of a semiconductor wafer;(b) after the step (a), forming a metal film over the first back surface of the semiconductor wafer so as to enclose the concave;(c) after the step (b), dicing the semiconductor wafer along the dicing lines and forming a plurality of semiconductor chips each having a recess in a peripheral region of a second back surface located on the side opposite to a second main surface; and(d) after the step (c), mounting the semiconductor chip over a chip mounting part of a lead frame through a bonding material,wherein, in the step (d), the semiconductor chip is mounted over the chip mounting part through the bonding material such that the recess in the second back surface of the semiconductor chip comes in contact with the bonding material.2. The method of manufacturing a semiconductor device according to claim 1 , wherein a solder material is used as the bonding material.3. The method of manufacturing a semiconductor device according to claim 1 , wherein ...

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Номер записи: 73

23-07-2020 дата публикации

THREE-DIMENSIONAL INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME

Номер: US20200235063A1

Автор: CHEN Chun-Hung, Lin Ming-Tse

Принадлежит: UNITED MICROELECTRONICS CORP.

Provided are a three-dimensional integrated circuit (3DIC) and a method of manufacturing the same. The 3DIC includes a first wafer, a second wafer, and a hybrid bonding structure. The second wafer is bonded to the first wafer by the hybrid bonding structure. The hybrid bonding structure includes a blocking layer between a hybrid bonding dielectric layer and a hybrid bonding metal layer. 1. A three-dimensional integrated circuit (3DIC) , comprising:a first wafer; anda second wafer, bonded to the first wafer by a hybrid bonding structure, wherein the hybrid bonding structure comprises a blocking layer disposed between a hybrid bonding dielectric layer and a hybrid bonding metal layer.2. The 3DIC of claim 1 , wherein a material of the blocking layer is from the hybrid bonding dielectric layer and the hybrid bonding metal layer claim 1 , and the blocking layer is in direct contact with the hybrid bonding dielectric layer and the hybrid bonding metal layer.3. The 3DIC of claim 1 , wherein the blocking layer comprises manganese oxide (MnO) claim 1 , manganese silicate (MnSiO) claim 1 , manganese oxynitride (MnON) claim 1 , cobalt oxide (CoO) claim 1 , or a combination thereof.4. The 3DIC of claim 1 , wherein a thickness of the blocking layer is between 0.5 nm and 1.0 nm.5. The 3DIC of claim 1 , wherein the hybrid bonding structure comprises:a first portion, comprising a first bonding metal layer and a second bonding metal layer bonding to each other;a second portion, comprising a first bonding dielectric layer and a second bonding dielectric layer bonding to each other; anda third portion, comprising the first bonding metal layer and the second bonding dielectric layer bonding to each other, the first bonding dielectric layer and the second bonding metal layer bonding to each other, and the blocking layer disposed between the first bonding metal layer and the second bonding dielectric layer and disposed between the first bonding dielectric layer and the second bonding ...

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Номер записи: 74

08-08-2019 дата публикации

Semiconductor Packages and Methods of Forming the Same

Номер: US20190244935A1

Автор: Chen-Hua Yu, Hao-Yi Tsai, Ming Hung TSENG, Tin-Hao Kuo, Tzu-Sung Huang, Yen-Liang Lin

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A device is provided, including: a first device package including: a first redistribution structure including a first redistribution line and a second redistribution line; a die on the first redistribution structure; a first via coupled to a first side of the first redistribution line; a second via coupled to a first side of the second redistribution line and extending through the second redistribution line; an encapsulant surrounding the die, the first via, and the second via; and a second redistribution structure over the encapsulant, the second redistribution structure electrically connected to the die, the first via, and the second via; a first conductive connector coupled to a second side of the first redistribution line, the first conductive connector disposed along a different axis than a longitudinal axis of the first via; and a second conductive connector coupled to a second side of the second redistribution line, the second conductive connector disposed along a longitudinal axis of the second via.

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Номер записи: 75

30-07-2020 дата публикации

Microelectronic assembly from processed substrate

Номер: US20200243380A1

Автор: Cyprian Emeka Uzoh, Laura Wills Mirkarimi

Принадлежит: Invensas Bonding Technologies Inc

Representative implementations of techniques, methods, and formulary provide repairs to processed semiconductor substrates, and associated devices, due to erosion or “dishing” of a surface of the substrates. The substrate surface is etched until a preselected portion of one or more embedded interconnect devices protrudes above the surface of the substrate. The interconnect devices are wet etched with a selective etchant, according to a formulary, for a preselected period of time or until the interconnect devices have a preselected height relative to the surface of the substrate. The formulary includes one or more oxidizing agents, one or more organic acids, and glycerol, where the one or more oxidizing agents and the one or more organic acids are each less than 2% of formulary and the glycerol is less than 10% of the formulary.

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Номер записи: 76

14-09-2017 дата публикации

Semiconductor device and manufacturing method

Номер: US20170263666A1

Автор: Kenichi Aoyagi, Nobutoshi Fujii, Yoshihisa Kagawa, Yoshiya Hagimoto

Принадлежит: Sony Corp

A semiconductor device includes a first substrate having an attaching surface on which first electrodes and a first insulating film are exposed, an insulating thin film that covers the attaching surface of the first substrate, and a second substrate which has an attaching surface on which second electrodes and a second insulating film are exposed and is attached to the first substrate in a state in which the attaching surface of the second substrate and the attaching surface of the first substrate are attached together sandwiching the insulating thin film therebetween, and the first electrodes and the second electrodes deform and break a part of the insulating thin film so as to be directly electrically connected to each other.

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Номер записи: 77

13-09-2018 дата публикации

RELEASABLE CARRIER METHOD

Номер: US20180261489A1

Автор: Rusli Sukianto

Принадлежит:

A method for making a semiconductor device includes providing a releasable carrier attached to a conductive layer, patterning a conductive circuit on a surface of the conductive layer, applying an insulative material at least partially covering the conductive circuit, releasing the releasable carrier from the conductive layer, and facilitating the releasing with an activating source. A method of fabricating a releasable carrier includes providing a supporting carrier, attaching a releasable tape to the supporting carrier, providing a first conductive layer and a second conductive layer attached to the first conductive layer, and attaching the first conductive layer to the releasable tape, where the releasable tape is configured to release the supporting carrier from the first conductive layer after being exposed to an activating source. 1. A method for making a semiconductor device comprising:providing a releasable carrier attached to a conductive layer;patterning a conductive circuit on a surface of the conductive layer;applying an insulative material at least partially covering the conductive circuit;releasing the releasable carrier from the conductive layer; andfacilitating the releasing with an activating source.2. The method of claim 1 , the conductive layer further including a carrier conductive layer and a thin conductive layer claim 1 , the method further comprising:providing a releasable tape between the releasable carrier and the conductive layer;releasing the carrier conductive layer from the releasable tape;releasing the thin conductive layer from the carrier conductive layer; andreleasing the releasable carrier from the releasable tape.3. The method of claim 1 , wherein the activating source does not make physical contact with the releasable carrier.4. The method of claim 1 , wherein the activating source is a UV light source generating irradiation energy between 20 mW/cmand 40 mW/cm.5. The method of claim 1 , wherein the activating source is a heat ...

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Номер записи: 78

11-12-2014 дата публикации

SEMICONDUCTOR DEVICE WITH OVERLAPPED LEAD TERMINALS

Номер: US20140361444A1

Автор: NARITA Hiroaki

Принадлежит:

The size and thickness of a semiconductor device are reduced. A semiconductor package with a flip chip bonding structure includes: a semiconductor chip having a main surface with multiple electrode pads formed therein and a back surface located on the opposite side thereto; four lead terminals each having an upper surface with the semiconductor chip placed thereover and a lower surface located on the opposite side thereto; and a sealing body having a main surface and a back surface located on the opposite side thereto. In this semiconductor package, the distance between adjacent first lower surfaces of the four lead terminals exposed in the back surface of the sealing body is made longer than the distance between adjacent upper surfaces thereof. This makes it possible to suppress the production of a solder bridge when the semiconductor package is solder mounted to a mounting board and to reduce the size and thickness of the semiconductor package and further enhance the reliability of the semiconductor package. 119-. (canceled)20. A semiconductor device comprising:a semiconductor chip having a first surface over which four electrode pads are arranged and a second surface opposite the first surface;four external terminals; anda sealing body sealing the semiconductor chip and a part of each of the four external terminals,wherein each of the four external terminals has a first top surface, a first bottom surface opposite the first top surface, and a second bottom surface opposite the first top surface and between the first top surface and the first bottom surface in a thickness direction thereof,wherein, in a plan view from the first bottom surface side, the second bottom surface surrounds the first bottom surface,wherein the semiconductor chip is mounted over the first top surface of each of the four external terminals such that the first surface of the semiconductor chip faces the first top surface of each of the four external terminals, with each of the four ...

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Номер записи: 79

01-10-2015 дата публикации

HYBRID BONDING WITH UNIFORM PATTERN DENSITY

Номер: US20150279888A1

Автор: Chen Szu-Ying, Yaung Dun-Nian

Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A chip includes a semiconductor substrate, integrated circuits with at least portions in the semiconductor substrate, and a surface dielectric layer over the integrated circuits. A plurality of metal pads is distributed substantially uniformly throughout substantially an entirety of a surface of the chip. The plurality of metal pads has top surfaces level with a top surface of the surface dielectric layer. The plurality of metal pads includes active metal pads and dummy metal pads. The active metal pads are electrically coupled to the integrated circuits. The dummy metal pads are electrically decoupled from the integrated circuits. 1. An integrated circuit structure comprising: a semiconductor substrate; and', 'first integrated circuits with at least portions in the semiconductor substrate;', 'a first surface dielectric layer over the first integrated circuits; and', first active metal pads electrically coupled to the first integrated circuits; and', 'first dummy metal pads electrically decoupled from the first integrated circuits., 'a first plurality of metal pads distributed substantially uniformly throughout substantially an entire top surface of the first chip, wherein the first plurality of metal pads comprises top surfaces level with a top surface of the first surface dielectric layer, and wherein the first plurality of metal pads comprises], 'a first chip comprising2. The integrated circuit structure of claim 1 , wherein the first chip comprises an array-containing circuit selected from the group consisting essentially of an image sensor array claim 1 , a memory array claim 1 , and combinations thereof.3. The integrated circuit structure of further comprising:a second plurality of metal pads underlying the first plurality of metal pads, wherein top surfaces of the second plurality of metal pads are in contact with bottom surfaces of the first plurality of metal pads.4. The integrated circuit structure of further comprising:a plurality of metal vias underlying ...

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Номер записи: 80

18-11-2021 дата публикации

Method for fabricating semiconductor device with protection structure and air gaps

Номер: US20210358862A1

Автор: Teng-Yen Huang

Принадлежит: Nanya Technology Corp

The present application discloses a method for fabricating a semiconductor device with a protection structure for suppressing electromagnetic interference and air gaps for reducing parasitic capacitance. The method includes providing a first semiconductor die, forming a connecting dielectric layer above the first semiconductor die, forming a first trench in the connecting dielectric layer, forming a plurality of sacrificial spacers on sides of the first trench, forming a first protection structure in the first trench, and performing an energy treatment to turn the plurality of sacrificial spacers into a plurality of air gaps. The plurality of sacrificial spacers are formed of an energy-removable material and the first protection structure is formed of copper, aluminum, titanium, tungsten, or cobalt.

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Номер записи: 81

20-08-2020 дата публикации

Semiconductor Arrangement and Method for Producing a Semiconductor Arrangement

Номер: US20200266141A1

Автор: Stadler Michael

Принадлежит:

A semiconductor arrangement includes a lower semiconductor chip, an upper semiconductor chip arranged over an upper main side of the lower semiconductor chip, a metallization layer arranged on the upper main side of the lower semiconductor chip, and a bonding material which fastens the upper semiconductor chip on the lower semiconductor chip. The metallization layer includes a structure with increased roughness in comparison with the rest of the metallization layer, the structure being arranged along a contour of the upper semiconductor chip. 1. A semiconductor arrangement , comprising:a lower semiconductor chip;an upper semiconductor chip arranged over an upper main side of the lower semiconductor chip;a metallization layer arranged on the upper main side of the lower semiconductor chip; anda bonding material which fastens the upper semiconductor chip on the lower semiconductor chip,wherein the metallization layer comprises a structure with increased roughness in comparison with the rest of the metallization layer, the structure being arranged along a contour of the upper semiconductor chip.2. The semiconductor arrangement of claim 1 , wherein the structure comprises a plurality of depressions.3. The semiconductor arrangement of claim 2 , wherein the depressions are holes which extend fully through the metallization layer.4. The semiconductor arrangement of claim 2 , wherein the depressions have an edge length or a diameter in a range of from 0.05 mm to 0.5 mm.5. The semiconductor arrangement of claim 1 , wherein the structure fully encloses the upper semiconductor chip.6. The semiconductor arrangement of claim 1 , wherein wetting the upper main side of the lower semiconductor chip by the bonding material is limited by the structure to a region below the upper semiconductor chip.7. The semiconductor arrangement of claim 1 , wherein the bonding material is an adhesive.8. The semiconductor arrangement of claim 1 , wherein the metallization layer is a metallization of ...

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Номер записи: 82

05-09-2019 дата публикации

Semiconductor device, fabrication method for a semiconductor device and electronic apparatus

Номер: US20190273109A1

Автор: Kenichi Aoyagi, Nobutoshi Fujii, Yoshihisa Kagawa, Yoshiya Hagimoto

Принадлежит: Sony Corp

Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate.

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Номер записи: 83

12-09-2019 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20190279952A1

Автор: TAGAMI Masayoshi

Принадлежит: Toshiba Memory Corporation

In one embodiment, a semiconductor device includes a first chip including a substrate, a first plug on the substrate, and a first pad on the first plug, and a second chip including a second plug and a second pad under the second plug. The second chip includes an electrode layer electrically connected to the second plug, a charge storage layer provided on a side face of the electrode layer via a first insulator, and a semiconductor layer provided on a side face of the charge storage layer via a second insulator. The first and second pads are bonded with each other, and the first and second plugs are disposed so that at least a portion of the first plug and at least a portion of the second plug do not overlap with each other in a first direction that is perpendicular to a surface of the substrate. 1. A semiconductor device comprising:a first chip including a substrate, a first plug provided on the substrate, and a first pad provided on the first plug; anda second chip including a second plug and a second pad provided under the second plug,the second chip comprising:an electrode layer electrically connected to the second plug;a charge storage layer provided on a side face of the electrode layer via a first insulator; anda semiconductor layer provided on a side face of the charge storage layer via a second insulator,whereinthe first pad and the second pad are bonded with each other, andthe first and second plugs are disposed so that at least a portion of the first plug and at least a portion of the second plug do not overlap with each other in a first direction that is perpendicular to a surface of the substrate.2. The device of claim 1 , wherein a thickness of the first plug is equal to or greater than twice as thick as a thickness of the first pad claim 1 , and a thickness of the second plug is equal to or greater than twice as thick as a thickness of the second pad.3. The device of claim 1 , further comprising:a first interconnect that extends in a first interconnect ...

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Номер записи: 84

03-09-2020 дата публикации

NANOWIRE BONDING INTERCONNECT FOR FINE-PITCH MICROELECTRONICS

Номер: US20200279821A1

Автор: Haba Belgacem, Mohammed Ilyas

Принадлежит: INVENSAS CORPORATION

A nanowire bonding interconnect for fine-pitch microelectronics is provided. Vertical nanowires created on conductive pads provide a debris-tolerant bonding layer for making direct metal bonds between opposing pads or vias. Nanowires may be grown from a nanoporous medium with a height between 200-1000 nanometers and a height-to-diameter aspect ratio that enables the nanowires to partially collapse against the opposing conductive pads, creating contact pressure for nanowires to direct-bond to opposing pads. Nanowires may have diameters less than 200 nanometers and spacing less than 1 μm from each other to enable contact or direct-bonding between pads and vias with diameters under 5 μm at very fine pitch. The nanowire bonding interconnects may be used with or without tinning, solders, or adhesives. A nanowire forming technique creates a nanoporous layer on conductive pads, creates nanowires within pores of the nanoporous layer, and removes at least part of the nanoporous layer to reveal a layer of nanowires less than 1 μm in height for direct bonding. 1. A bonding interconnect for a microelectronic die or wafer , comprising:one or more conductive pads, each conductive pad comprising a length or a diameter less than approximately 5 μm;multiple nanowires conductively connected to each conductive pad and vertically disposed on each conductive pad for conductively bonding with an opposing conductive pad; anda freestanding end of each nanowire comprising a height-to-diameter aspect ratio enabling the nanowire to partially collapse against the opposing conductive pad providing a compression or a contact pressure of the nanowire for bonding to the opposing conductive pad.2. The bonding interconnect of claim 1 , wherein at least some of the multiple nanowires conductively bond with the opposing conductive pad via a direct metallic bond between the nanowire and a metal of the opposing conductive pad.3. The bonding interconnect of claim 1 , wherein each nanowire has a diameter ...

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Номер записи: 85

11-10-2018 дата публикации

SEMICONDUCTOR PACKAGE STRUCTURE

Номер: US20180294227A1

Автор: Chen Hsien-Wei, Chen Jie

Принадлежит:

Semiconductor package structures are provided. A semiconductor package structure includes a chip, a molding material surrounding the chip, a through-via extending from a first surface to a second surface of the molding material, and a first re-distribution layer (RDL) wire disposed on the second surface of the molding material and electrically separated from the through-via. The second surface is opposite to the first surface. A portion of the first RDL wire across the through-via has a first segment with a first width and a second segment with a second width different from the first width. 1. A semiconductor package structure , comprising:a chip;a molding material surrounding the chip;a through-via extending from a first surface to a second surface of the molding material, wherein the second surface is opposite to the first surface; anda first re-distribution layer (RDL) wire disposed on the second surface of the molding material and electrically separated from the through-via,wherein a portion of the first RDL wire across the through-via has a first segment with a first width and a second segment with a second width different from the first width.2. The semiconductor package structure as claimed in claim 1 , wherein the first width of the first segment of the first RDL wire on a boundary between the through-via and the molding material is greater than the second width of the second segment of the first RDL wire on the through-via.3. The semiconductor package structure as claimed in claim 1 , wherein the first RDL wire has a connecting pattern on a boundary between the through-via and the molding material claim 1 , and a center of the connecting pattern is centered on an edge of the through-via.4. The semiconductor package structure as claimed in claim 3 , wherein the connecting pattern comprises a main portion having a circular shape claim 3 , a regular polygonal shape claim 3 , an ellipse shape or an oval shape.5. The semiconductor package structure as claimed in ...

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Номер записи: 86

17-09-2020 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20200294958A1

Автор: Junichi Shibata

Принадлежит: Toshiba Memory Corp

In one embodiment, a semiconductor device includes a first wafer or a first chip including a first insulator and a first pad. The device further includes a second wafer or a second chip including a second insulator in contact with the first insulator, and a second pad opposed to the first pad and electrically connected to the first pad. Moreover, the first insulator includes a first trench extending to the first pad, and/or the second insulator includes a second trench extending to the second pad.

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Номер записи: 87

05-11-2015 дата публикации

Bonding Structures and Methods of Forming the Same

Номер: US20150318250A1

Автор: Ching-Chun Wang, Luan C. Tran, Yeur-Luen Tu

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A package includes a package component and a second package component. A first elongated bond pad is at a surface of the first package component, wherein the first elongated bond pad has a first length in a first longitudinal direction, and a first width smaller than the first length. A second elongated bond pad is at a surface of the second package component. The second elongated bond pad is bonded to the first elongated bond pad. The second elongated bond pad has a second length in a second longitudinal direction, and a second width smaller than the second width. The second longitudinal direction is un-parallel to the first longitudinal direction.

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Номер записи: 88

24-11-2016 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20160343678A1

Автор: NASU Nobutaka

Принадлежит: LAPIS SEMICONDUCTOR CO., LTD.

A semiconductor device includes a pad group including pads provided on a semiconductor substrate and arranged in a row to form a pad row as a whole. The pad group includes at least one first pad provided with a first via-connection part electrically connected therewith and extending in a first direction perpendicular to a row direction of the pad row, and at least one second pad provided with a second via-connection part electrically connected therewith and extending in a second direction opposite to the first direction. The at least one second pad is formed at a position moved in the first direction from the row direction of the pad row passing through a center of the at least one first pad. 1. A semiconductor device comprising:at least one pad group including a plurality of pads provided on a semiconductor substrate and arranged in a row to form a pad row as a whole, whereinsaid pad group includes: a plurality of first pads provided with a first via-connection part electrically connected therewith; and a plurality of second pads provided with a second via-connection part electrically connected therewith;said plurality of first pads are positioned so that each center point of said plurality of first pads is arranged along a first center line,said plurality of second pads are positioned so that each center point of said plurality of second pads is arranged along a second center line,said first via-connection part extends in a first direction perpendicular to the first center line,said second via-connection part extends in a second direction opposite to the first direction,the first and second center lines are positioned in parallel with each other and apart from each other, andsaid first and second via-connection parts are connected to a circuit block provided in said semiconductor substrate.2. The semiconductor device according to claim 1 , wherein the first and second center lines are apart from each other by a length substantially equal to a connection part ...

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Номер записи: 89

15-10-2020 дата публикации

Protective elements for bonded structures

Номер: US20200328164A1

Автор: Belgacem Haba, Javier A. Delacruz, Rajesh Katkar

Принадлежит: Invensas Bonding Technologies Inc

A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry. The bonded structure can include a protective element directly bonded to the semiconductor element without an adhesive along a bonding interface. The protective element can include an obstructive material disposed over at least a portion of the active circuitry. The obstructive material can be configured to obstruct external access to the active circuitry. The bonded structure can include a disruption structure configured to disrupt functionality of the at least a portion of the active circuitry upon debonding of the protective element from the semiconductor element.

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Номер записи: 90

14-11-2019 дата публикации

METHOD OF ROOM TEMPERATURE COVALENT BONDING

Номер: US20190344533A1

Автор: TONG Qin-Yi

Принадлежит:

A method of bonding includes using a bonding layer having a fluorinated oxide. Fluorine may be introduced into the bonding layer by exposure to a fluorine-containing solution, vapor or gas or by implantation. The bonding layer may also be formed using a method where fluorine is introduced into the layer during its formation. The surface of the bonding layer is terminated with a desired species, preferably an NHspecies. This may be accomplished by exposing the bonding layer to an NHOH solution. High bonding strength is obtained at room temperature. The method may also include bonding two bonding layers together and creating a fluorine distribution having a peak in the vicinity of the interface between the bonding layers. One of the bonding layers may include two oxide layers formed on each other. The fluorine concentration may also have a second peak at the interface between the two oxide layers. 1. (canceled)2. A bonding method comprising: depositing a first film on the first element,', 'introducing fluorine into the first film,', 'polishing the first film,', 'depositing a second film directly on the first film to define an interface between the first film and the second film,', 'introducing fluorine into the second film, and', 'polishing the second film;, 'forming a first bonding layer on a first element, wherein forming the first bonding layer comprisesforming a second bonding layer on a second element;bringing into contact a surface of the second film with a surface of the second bonding layer at about room temperature; andforming a direct bond between the second film and the second bonding layer without an intervening adhesive.3. The method of claim 2 , wherein forming the first bonding layer comprises depositing the first film and subsequently introducing fluorine into the first film; and depositing the second film and subsequently introducing fluorine into the second film.4. The method of claim 3 , wherein introducing fluorine into the first film comprises ...

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Номер записи: 91

14-11-2019 дата публикации

METHOD OF ROOM TEMPERATURE COVALENT BONDING

Номер: US20190344534A1

Автор: TONG Qin-Yi

Принадлежит:

A method of bonding includes using a bonding layer having a fluorinated oxide. Fluorine may be introduced into the bonding layer by exposure to a fluorine-containing solution, vapor or gas or by implantation. The bonding layer may also be formed using a method where fluorine is introduced into the layer during its formation. The surface of the bonding layer is terminated with a desired species, preferably an NHspecies. This may be accomplished by exposing the bonding layer to an NHOH solution. High bonding strength is obtained at room temperature. The method may also include bonding two bonding layers together and creating a fluorine distribution having a peak in the vicinity of the interface between the bonding layers. One of the bonding layers may include two oxide layers formed on each other. The fluorine concentration may also have a second peak at the interface between the two oxide layers. 1. (canceled)2. A bonded structure comprising:a first element;a first bonding layer disposed on the first element, the first bonding layer comprising a first film and a second film formed directly on the first film, wherein each of the first and the second films is planarized and includes fluorine;a second element; anda second bonding layer disposed on the second element,wherein the second film and the second bonding layer are directly bonded to one another without an intervening adhesive.3. The bonded structure of claim 2 , further comprising a fluorine concentration within the first bonding layer having a first peak in the vicinity of a bonding interface between the first and second bonding layers and a second peak in the vicinity of an internal interface between the first and second films.4. The bonded structure of claim 2 , wherein the second bonding layer comprises a third film on the second element and a fourth film on the third film.5. The bonded structure of claim 2 , wherein the second film is disposed directly on the first film without intervening layers.6. The ...

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Номер записи: 92

22-12-2016 дата публикации

SEMICONDUCTOR PACKAGE

Номер: US20160372437A1

Автор: Jeong Jae Hong

Принадлежит:

A semiconductor package including a first metal layer configured for use as a bonding pad, a second metal layer formed over the first metal layer, and the second metal layer having a separation allowing for the second metal layer to be positioned above distal ends of the first metal layer. The semiconductor package also including a third metal layer formed over the second metal layer, and the third metal layer having a separation allowing for the third metal layer to be positioned above distal ends of the first metal layer, a trench defined by the separation of the third metal layer and second metal layer, and extending through the third metal layer and the second metal layer to expose the first metal layer, and a bonding ball located within the trench. 1. A semiconductor package comprising:a lower metal layer configured for use as a bonding pad;a plurality of upper metal layer parts formed over the lower metal layer, and separated from one another by gaps; anda pad open region exposing the lower metal layer through spaces defined between the plurality of upper metal layer parts; anda bonding ball positioned to bury the pad open region.2. The semiconductor package according to claim 1 , further comprising:an insulation layer formed over the upper metal layer parts disposed at outermost sides among the upper metal layer parts, and allowing the spaces to pass through to the second metal layer.3. The semiconductor package according to claim 1 , further comprising:a plurality of first contact nodes formed over the lower metal layer, and separated from one another by a predetermined gap.4. The semiconductor package according to claim 3 , wherein the number of first contact nodes is the same as the number of upper metal layer parts claim 3 , andwherein the first contact nodes are connected with the third metal layer parts.5. The semiconductor package according to claim 3 , wherein the first contact nodes are disposed in such a way as to define slits between them.6. The ...

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Номер записи: 93

29-12-2016 дата публикации

Display Device and Method of Manufacturing the Same

Номер: US20160377905A1

Автор: CHOI Jaewoong, CHOI WonJun, KONG Younghyun, NAM SungLim, PARK Misun

Принадлежит:

Disclosed is a display device and a method of manufacturing the same, wherein an end portion of a pad provided on a first substrate is spaced apart and separated from an upper surface of the first substrate, and a connection electrode electrically connected with the pad is in contact with a lateral surface of the pad and a lower surface of the pad. 1. A display device comprising:first and second substrates confronting each other;a pad on the first substrate; anda connection electrode electrically connected with the pad,wherein an end portion of the pad is spaced apart and separated from an upper surface of the first substrate, and the connection electrode is in contact with a lateral surface of the pad and a lower surface of the pad.2. The display device according to claim 1 , wherein an end portion of the first substrate substantially corresponds to an end portion of the second substrate at a contact portion between the pad and the connection electrode.3. The display device according to claim 1 , further comprising a flexible circuit film that is electrically connected with the connection electrode and is attached to a lateral surface of the first substrate and a lateral surface of the second substrate claim 1 , wherein the connection electrode is in contact with the lateral surface of the first substrate and the lateral surface of the second substrate claim 1 , and.4. The display device according to claim 1 , further comprising a light-shielding layer on the second substrate claim 1 , and an overcoat layer on the light-shielding layer claim 1 , wherein the overcoat layer is disposed between the light-shielding layer and the connection electrode so as to insulate the light-shielding layer from the connection electrode.5. The display device according to claim 1 , wherein the end portion of the pad is provided in a bent structure claim 1 , and further comprising a stopper on the second substrate for controlling a bending degree of the end portion of the pad.6. The ...

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Номер записи: 94

05-12-2019 дата публикации

Hybrid Bonding with Uniform Pattern Density

Номер: US20190371780A1

Автор: Chen Szu-Ying, Yaung Dun-Nian

Принадлежит:

A chip includes a semiconductor substrate, integrated circuits with at least portions in the semiconductor substrate, and a surface dielectric layer over the integrated circuits. A plurality of metal pads is distributed substantially uniformly throughout substantially an entirety of a surface of the chip. The plurality of metal pads has top surfaces level with a top surface of the surface dielectric layer. The plurality of metal pads includes active metal pads and dummy metal pads. The active metal pads are electrically coupled to the integrated circuits. The dummy metal pads are electrically decoupled from the integrated circuits. 1. An integrated circuit structure comprising: a semiconductor substrate;', 'a first wire-bonding stud on a side of the semiconductor substrate, wherein the first wire-bonding stud is at a same level as the semiconductor substrate;', 'a first surface dielectric layer underlying the semiconductor substrate; and', 'a first plurality of metal pads underlying the semiconductor substrate, wherein the first plurality of metal pads are distributed substantially uniformly throughout an entire bottom surface of the first chip, and wherein the first plurality of metal pads comprise bottom surfaces level with a bottom surface of the first surface dielectric layer., 'a first chip comprising2. The integrated circuit structure of claim 1 , wherein the first chip further comprises a second wire-bonding stud on an opposite side of claim 1 , and at the same level as claim 1 , the first wire-bonding stud.3. The integrated circuit structure of claim 1 , wherein the first chip further comprises a bond wire attached to the first wire-bonding stud.4. The integrated circuit structure of claim 1 , wherein the first plurality of metal pads comprise:a first subset of metal pads overlapped by the semiconductor substrate; anda second subset of metal pads outside of all regions overlapped by the semiconductor substrate.5. The integrated circuit structure of claim 1 , ...

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Номер записи: 95

03-12-2020 дата публикации

Semiconductor device

Номер: US20200381323A1

Автор: Masafumi Jochi

Принадлежит: Mitsubishi Electric Corp

A semiconductor device includes a semiconductor element, a die pad, an encapsulating member, and a plurality of leads. The die pad has a front surface on which the semiconductor element is mounted. The encapsulating member covers and seals the semiconductor element. The plurality of leads each have a first end connected to the semiconductor element in an inside of the encapsulating member and a second end led out from a side surface of the encapsulating member. A lower surface of a package including the semiconductor element, the die pad, and the encapsulating member is located on a back surface side of the die pad and has a convexly curved shape.

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Номер записи: 96

03-12-2020 дата публикации

Low temperature bonded structures

Номер: US20200381389A1

Автор: Cyprian Emeka Uzoh, Guilian Gao, Jeremy Alfred Theil, Laura Wills Mirkarimi, Liang Wang, Rajesh Katkar

Принадлежит: Invensas Bonding Technologies Inc

Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.

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Номер записи: 97

19-12-2019 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD

Номер: US20190386056A1

Автор: Aoyagi Kenichi, Fujii Nobutoshi, Hagimoto Yoshiya, Kagawa Yoshihisa

Принадлежит: SONY CORPORATION

A semiconductor device includes a first substrate having an attaching surface on which first electrodes and a first insulating film are exposed, an insulating thin film that covers the attaching surface of the first substrate, and a second substrate which has an attaching surface on which second electrodes and a second insulating film are exposed and is attached to the first substrate in a state in which the attaching surface of the second substrate and the attaching surface of the first substrate are attached together sandwiching the insulating thin film therebetween, and the first electrodes and the second electrodes deform and break a part of the insulating thin film so as to be directly electrically connected to each other. 1. A method for manufacturing semiconductor devices , comprising:providing a first substrate including a photodiode, at least one of a transfer transistor or a reset transistor, and a first electrode at a first surface side of the first substrate opposite to a light incident surface side;providing a second substrate including a second electrode at a first surface side of the second substrate and a plurality of transistors;forming an insulating thin film that covers at least one of an attaching surface of the first substrate and an attaching surface of the second substrate;bonding the first substrate and the second substrate to each other such that the first surface side of the first substrate and the first surface side of the second substrate are facing each other, thereby attaching the two substrates, wherein the first substrate and the second substrate are thermally treated so that the insulating thin film is broken by deforming the first and second electrodes, thereby bringing the first electrode and the second electrode into direct electrical contact.2. The manufacturing method according to claim 1 , wherein the step of bonding the first substrate and the second substrate further comprises growing a grain of the first electrode into the ...

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Номер записи: 98

31-03-2020 дата публикации

Increased contact alignment tolerance for direct bonding

Номер: US10607937B2

Автор: Gaius Gillman Fountain, Jr., Javier A. Delacruz, Paul M. Enquist

Принадлежит: Invensas Bonding Technologies Inc

A bonded device structure including a first substrate having a first set of conductive contact structures, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the contact structures on the first substrate, a second substrate having a second set of conductive contact structures, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the contact structures on the second substrate, and a contact-bonded interface between the first and second set of contact structures formed by contact bonding of the first non-metallic region to the second non-metallic region. The contact structures include elongated contact features, such as individual lines or lines connected in a grid, that are non-parallel on the two substrates, making contact at intersections. Alignment tolerances are thus improved while minimizing dishing and parasitic capacitance.

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Номер записи: 99

19-05-2020 дата публикации

Selective recess

Номер: US10658313B2

Автор: Gaius Gillman Fountain, Jr., Javier A. Delacruz, Laura Wills Mirkarimi, Liang Wang, Rajesh Katkar, Shaowu HUANG

Принадлежит: Invensas Bonding Technologies Inc

Representative implementations of techniques and devices are used to remedy or mitigate the effects of damaged interconnect pads of bonded substrates. A recess of predetermined size and shape is formed in the surface of a second substrate of the bonded substrates, at a location that is aligned with the damaged interconnect pad on the first substrate. The recess encloses the damage or surface variance of the pad, when the first and second substrates are bonded.

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Номер записи: 100

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