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Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 51. Отображено 51.
19-07-2007 дата публикации

WAFER LEVEL CHIP SCALE PACKAGE HAVING REROUTING LAYER AND METHOD OF MANUFACTURING THE SAME

Номер: US2007164431A1
Автор: LEE IN YOUNG, CHUNG HYUN-SOO, LEE DONG-HO, SIM SUNG-MIN, SEO DONG-SOO, RYU SEUNG-KWAN, PARK MYEONG-SOON
Принадлежит:

A wafer level chip scale package capable of reducing parasitic capacitances between a rerouting and the metal wiring of a wafer, and a method for manufacturing the same are provided. An embodiment of the wafer level chip scale package includes a wafer arranged with a plurality of bonding pads and an insulating member formed on the wafer so that the bonding pads are exposed. A rerouting is further formed on the insulating member in contact with the exposed bonding pads and an external connecting terminal is electrically connected to a portion of the rerouting. Here, the insulating member overlapping the rerouting is provided with a plurality of spaces in which air is trapped.

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Номер записи: 1
22-12-2015 дата публикации

Integrated circuit chips having vertically extended through-substrate vias therein

Номер: US0009219035B2
Автор: Ho-jin Lee, Kang-wook Lee, Myeong-soon Park, Ju-il Choi, Son-kwan Hwang, LEE HO-JIN, LEE KANG-WOOK, PARK MYEONG-SOON, CHOI JU-IL, HWANG SON-KWAN
Принадлежит: Samsung Electronics Co., Ltd., LEE HO-JIN, LEE KANG-WOOK, PARK MYEONG-SOON, CHOI JU-IL, HWANG SON-KWAN, SAMSUNG ELECTRONICS CO LTD, SAMSUNG ELECTRONICS CO., LTD.

Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.

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Номер записи: 2
20-08-2020 дата публикации

SEMICONDUCTOR CHIP INCLUDING CHIP PAD, REDISTRIBUTION WIRING TEST PAD, AND REDISTRIBUTION WIRING CONNECTION PAD

Номер: US20200266114A1
Автор: Myeong-soon Park, Hyun-Soo Chung, Chan-Ho Lee, PARK MYEONG-SOON, CHUNG HYUN-SOO, LEE CHAN-HO, Park, Myeong-soon, Chung, Hyun-Soo, Lee, Chan-Ho
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A semiconductor chip is disclosed that includes a chip pad disposed in a first region of a chip body, a redistribution wiring test pad disposed in the first region of the chip body spaced apart from the chip pad and connected to the chip pad through a redistribution wiring structure, and a redistribution wiring connection pad disposed in the first region of the chip body or a second region of the chip body and connected to the chip pad through the redistribution wiring structure.

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Номер записи: 3
14-01-2014 дата публикации

Methods of forming integrated circuit chips having vertically extended through-substrate vias therein

Номер: US0008629059B2
Автор: Ho-Jin Lee, Kang-Wook Lee, Myeong-Soon Park, Ju-il Choi, Son-Kwan Hwang, LEE HO-JIN, LEE KANG-WOOK, PARK MYEONG-SOON, CHOI JU-IL, HWANG SON-KWAN
Принадлежит: Samsung Electronics Co., Ltd., LEE HO-JIN, LEE KANG-WOOK, PARK MYEONG-SOON, CHOI JU-IL, HWANG SON-KWAN, SAMSUNG ELECTRONICS CO LTD, SAMSUNG ELECTRONICS CO., LTD.

Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.

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Номер записи: 4
22-02-2007 дата публикации

Wiring structure e.g. for semiconductor wafer plane pack, has insulating photo-resist structure on surface of conductive structure

Номер: DE102006037717A1
Автор: LEE IN-YOUNG, SIM SUNG-MIN, JANG DONG-HYEON, CHUNG HYUN-SOO, CHUNG JAE-SIK, RYU SEUNG-KWAN, PARK MYEONG-SOON, YOON JONG-KOOK, CHOI JU-IL, LEE, IN-YOUNG, SIM, SUNG-MIN, JANG, DONG-HYEON, CHUNG, HYUN-SOO, CHUNG, JAE-SIK, RYU, SEUNG-KWAN, PARK, MYEONG-SOON, YOON, JONG-KOOK, CHOI, JU-IL
Принадлежит:

A wiring structure has a body (102) with circuit unit (105) and contact point (110) provided on the body and electrically connected to the circuit unit, a conductive structure (120) provided on the body (102) is electrically connected to the contact point. An insulating photo-resist structure (130) is provided on the surface of the conductive structure (120) and a has contact opening (132) through which the conductive structure is partly exposed. An independent claim is included for a method for fabricating a wiring structure.

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Номер записи: 5
17-04-2007 дата публикации

Wafer level chip scale package having a gap and method for manufacturing the same

Номер: US0007205660B2
Автор: Myeong-Soon Park, Hyun-Soo Chung, In-Young Lee, Jae-Sik Chung, Sung-Min Sim, Dong-Hyeon Jang, Young-Hee Song, Seung-Kwan Ryu, PARK MYEONG-SOON, CHUNG HYUN-SOO, LEE IN-YOUNG, CHUNG JAE-SIK, SIM SUNG-MIN, JANG DONG-HYEON, SONG YOUNG-HEE, RYU SEUNG-KWAN
Принадлежит: Samsung Electronics Co., Ltd, SAMSUNG ELECTRONICS CO LTD, SAMSUNG ELECTRONICS CO., LTD

A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.

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Номер записи: 6
23-02-2006 дата публикации

Electrode structure of a semiconductor device and method of manufacturing the same

Номер: US2006038291A1
Автор: CHUNG HYUN-SOO, SIM SUNG-MIN, PARK MYEONG-SOON, JANG DONG-HYEON, SONG YOUNG-HEE
Принадлежит:

In the manufacture of a semiconductor device, a photosensitive layer is deposited to cover an exposed portion of an electrode with the photosensitive layer. The photosensitive layer is then subjected to a photolithography process to partially remove the photosensitive layer covering the electrode. The electrode may be a ball electrode or a bump electrode, and the semiconductor device may be contained in a wafer level package (WLP) or flip-chip package.

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Номер записи: 7
30-04-2013 дата публикации

Semiconductor devices having redistribution structures and packages, and methods of forming the same

Номер: US0008431479B2
Автор: Ki-Hyuk Kim, Nam-Seog Kim, Hyun-Soo Chung, Seok-Ho Kim, Myeong-Soon Park, Chang-Woo Shin, KIM KI-HYUK, KIM NAM-SEOG, CHUNG HYUN-SOO, KIM SEOK-HO, PARK MYEONG-SOON, SHIN CHANG-WOO
Принадлежит: SAMSUNG Electronics Co., Ltd., KIM KI-HYUK, KIM NAM-SEOG, CHUNG HYUN-SOO, KIM SEOK-HO, PARK MYEONG-SOON, SHIN CHANG-WOO, SAMSUNG ELECTRONICS CO LTD, SAMSUNG ELECTRONICS CO., LTD.

Semiconductor devices and methods of forming the same, including forming a chip pad on a chip substrate, forming a passivation layer on the chip pad and the chip substrate, forming a first insulation layer on the passivation layer, forming a recess and a first opening in the first insulation layer, forming a second opening in the passivation layer to correspond to the first opening, forming a redistribution line in a redistribution line area of the recess, the first opening, and the second opening, forming a second insulation layer on the redistribution line and the first insulation layer, and forming an opening in the second insulation to expose a portion of the redistribution line as a redistribution pad.

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Номер записи: 8
08-05-2014 дата публикации

INTEGRATED CIRCUIT CHIPS HAVING VERTICALLY EXTENDED THROUGH-SUBSTRATE VIAS THEREIN

Номер: US20140124901A1
Автор: Ho-jin Lee, Kang-wook Lee, Myeong-soon Park, Ju-iI Choi, Son-kwan Hwang, LEE HO-JIN, LEE KANG-WOOK, PARK MYEONG-SOON, CHOI JU-II, HWANG SON-KWAN
Принадлежит:

Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode. 1. An integrated circuit device , comprising:a semiconductor substrate having first and second opposing surfaces thereon and a plurality of active semiconductor devices in the first surface;a through-via electrode extending from the first surface to the second surface and having a tapered profile that is wider adjacent the first surface and narrower adjacent the second surface, said through-via electrode having a length greater than a distance between the first and second surfaces;an intermetal dielectric layer on the first surface;a multi-level metal interconnect extending through said intermetal dielectric layer; anda first contact pad electrically coupled by said multi-level metal interconnect to said through-via electrode.2. The device of claim 1 , wherein said multi-level metal interconnect comprises a plurality of metal wiring patterns at respective levels of metallization and a plurality of electrically conductive plugs that electrically connect the plurality of metal wiring patterns together.3. The device of claim 2 , wherein at least one of the plurality of electrically conductive plugs electrically connects said first contact pad to a metal ...

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Номер записи: 9
25-12-2007 дата публикации

Wafer level chip scale package having a gap and method for manufacturing the same

Номер: US0007312143B2
Автор: Myeong-Soon Park, Hyun-Soo Chung, In-Young Lee, Jae-Sik Chung, Sung-Min Sim, Dong-Hyeon Jang, Young-Hee Song, Seung-Kwan Ryu, PARK MYEONG-SOON, CHUNG HYUN-SOO, LEE IN-YOUNG, CHUNG JAE-SIK, SIM SUNG-MIN, JANG DONG-HYEON, SONG YOUNG-HEE, RYU SEUNG-KWAN
Принадлежит: Samsung Electronics Co., Ltd., SAMSUNG ELECTRONICS CO LTD, SAMSUNG ELECTRONICS CO., LTD.

A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.

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Номер записи: 10
23-03-2006 дата публикации

Halbleiterchip und Herstellungsverfahren

Номер: DE102005036646A1
Автор: LEE IN-YOUNG, SIM SUNG-MIN, JANG DONG-HYEON, CHUNG HYUN-SOO, SONG YOUNG-HEE, PARK MYEONG-SOON, LEE, IN-YOUNG, SIM, SUNG-MIN, JANG, DONG-HYEON, CHUNG, HYUN-SOO, SONG, YOUNG-HEE, PARK, MYEONG-SOON
Принадлежит:

Die Erfindung bezieht sich auf einen Halbleiterchip, der ein Halbleitersubstrat mit einer Oberseite und einer Unterseite beinhaltet und eine sich durch ein Durchgangsloch hindurch zur Substratunterseite erstreckende Verbindungselektrode (43) umfasst, sowie auf zugehörige Verfahren zur Herstellung integrierter Schaltkreischips und zur Halbleiterwaferarbeitung. DOLLAR A Erfindungsgemäß befindet sich das Durchgangsloch in einem seitlich an das Halbleitersubstrat anschließenden elektrischen Isolationsbereich, der in fertigungstechnisch vorteilhafter Weise in Trennlinienbereichen eines Halbleiterwafers liegen kann. Über die Verbindungselektrode kann eine Kontaktstelle auf der Substratoberseite mit einer Anschlussstelle an der Substratunterseite elektrisch verbunden werden. DOLLAR A Verwendung z. B. für Mehrchippackungstechnologien mit gestapelten Chips.

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Номер записи: 11
17-11-2020 дата публикации

Semiconductor chip including chip pad, redistribution wiring test pad, and redistribution wiring connection pad

Номер: US0010840159B2
Автор: Myeong-soon Park, Hyun-soo Chung, Chan-ho Lee, PARK MYEONG-SOON, CHUNG HYUN-SOO, LEE CHAN-HO, Park, Myeong-soon, Chung, Hyun-soo, Lee, Chan-ho
Принадлежит: SAMSUNG ELECTRONICS CO., LTD., SAMSUNG ELECTRONICS CO LTD, Samsung Electronics Co., Ltd.

A semiconductor chip is disclosed that includes a chip pad disposed in a first region of a chip body, a redistribution wiring test pad disposed in the first region of the chip body spaced apart from the chip pad and connected to the chip pad through a redistribution wiring structure, and a redistribution wiring connection pad disposed in the first region of the chip body or a second region of the chip body and connected to the chip pad through the redistribution wiring structure.

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Номер записи: 12
30-11-2021 дата публикации

Semiconductor chip including chip pad, redistribution wiring test pad, and redistribution wiring connection pad

Номер: US0011189535B2
Автор: Myeong-soon Park, Hyun-Soo Chung, Chan-Ho Lee, PARK MYEONG-SOON, CHUNG HYUN-SOO, LEE CHAN-HO, Park, Myeong-soon, Chung, Hyun-Soo, Lee, Chan-Ho
Принадлежит: SAMSUNG ELECTRONICS CO., LTD., SAMSUNG ELECTRONICS CO LTD

A semiconductor chip is disclosed that includes a chip pad disposed in a first region of a chip body, a redistribution wiring test pad disposed in the first region of the chip body spaced apart from the chip pad and connected to the chip pad through a redistribution wiring structure, and a redistribution wiring connection pad disposed in the first region of the chip body or a second region of the chip body and connected to the chip pad through the redistribution wiring structure.

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Номер записи: 13
09-02-2006 дата публикации

METHOD OF MANUFACTURING INTEGRATED-CIRCUIT CHIP FOR MULTI-CHIP PACKAGE, AND WAFER AND CHIP FORMED BY THE METHOD THEREOF

Номер: JP2006041512A
Автор: LEE IN-YOUNG, SIM SUNG-MIN, CHO TOGEN, CHUNG HYUN-SOO, SONG YOUNG-HEE, PARK MYEONG-SOON
Принадлежит:

PROBLEM TO BE SOLVED: To provide a method of manufacturing integrated-circuit chips for a multi-chip package which can simplify the manufacturing process and reduce the manufacturing cost and process time. SOLUTION: The integrated-circuit chip comprises a semiconductor substrate, having upper and lower surfaces which extend to outer edges and having at least one first contact pad on the upper surface contiguous to the outer edge, an electrically insulating region which is formed on the outer edge side of the semiconductor substrate and in which a through hole is formed, and a contact electrode that fills the through hole and is electrically connected to the first contact pad. COPYRIGHT: (C)2006,JPO&NCIPI ...

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Номер записи: 14
09-06-2009 дата публикации

Wafer level package having redistribution interconnection layer and method of forming the same

Номер: US0007545027B2
Автор: Hyun-Soo Chung, In-Young Lee, Dong-Hyeon Jang, Myeong-Soon Park, Dong-Ho Lee, CHUNG HYUN-SOO, LEE IN-YOUNG, JANG DONG-HYEON, PARK MYEONG-SOON, LEE DONG-HO
Принадлежит: Samsung Electronics Co., Ltd., SAMSUNG ELECTRONICS CO LTD, SAMSUNG ELECTRONICS CO., LTD.

A wafer level package may include a semiconductor substrate supporting an electrode pad. A first insulating layer may be provided on the semiconductor substrate. The first insulating layer may include a first opening through which the electrode pad may be exposed. A seed metal layer may be provided on an entire surface of the first insulating layer. A redistribution interconnection metal layer may be provided on the seed metal layer. A second insulating layer may be provided on the redistribution interconnection metal layer. The second insulating layer may have a second opening spaced from the first opening to expose a portion of the redistribution interconnection metal layer. The second insulating layer may surround the redistribution interconnection metal layer. An unwanted portion of seed metal layer may be removed using the second insulating layer as an etch mask.

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Номер записи: 15
09-03-2006 дата публикации

Manufacturing semiconductor device involves depositing photosensitive layer to cover exposed portion of electrode, and subjecting photosensitive layer to photolithography to partially remove photosensitive layer

Номер: DE102005040213A1
Автор: CHUNG HYUN-SOO, SIM SUNG-MIN, JANG DONG-HYEON, PARK MYEONG-SOON, SONG YOUNG-HEE, CHUNG, HYUN-SOO, SIM, SUNG-MIN, JANG, DONG-HYEON, PARK, MYEONG-SOON, SONG, YOUNG-HEE
Принадлежит:

Manufacturing a semiconductor device involves: depositing a photosensitive layer to cover an exposed portion of an electrode with the photosensitive layer; and subjecting the photosensitive layer to a photolithography process to partially remove the photosensitive layer covering the electrode. The electrode is one of a ball electrode and a bump electrode. A bottom of the electrode is mounted to a conductive layer, and the partial removal of the photosensitive layer exposes a top portion of the electrode. A diameter of the electrode is greater than a diameter of the exposed top portion of the electrode. The conductive layer is located on a semiconductor chip. The conductive layer is located on a printed circuit board. An independent claim is included for the manufacture of a wafer level package using the same method.

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Номер записи: 16
17-05-2007 дата публикации

Wafer level package having redistribution interconnection layer and method of forming the same

Номер: US2007108573A1
Автор: CHUNG HYUN-SOO, LEE IN-YOUNG, JANG DONG-HYEON, PARK MYEONG-SOON, LEE DONG-HO
Принадлежит:

A wafer level package may include a semiconductor substrate supporting an electrode pad. A first insulating layer may be provided on the semiconductor substrate. The first insulating layer may include a first opening through which the electrode pad may be exposed. A seed metal layer may be provided on an entire surface of the first insulating layer. A redistribution interconnection metal layer may be provided on the seed metal layer. A second insulating layer may be provided on the redistribution interconnection metal layer. The second insulating layer may have a second opening spaced from the first opening to expose a portion of the redistribution interconnection metal layer. The second insulating layer may surround the redistribution interconnection metal layer. An unwanted portion of seed metal layer may be removed using the second insulating layer as an etch mask.

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Номер записи: 17
29-07-2010 дата публикации

METHOD OF FORMING CONNECTION TERMINAL

Номер: US20100190333A1
Автор: Myeong-Soon PARK, Eunchul Ahn, Hyunsoo Chung, Seokho Kim, Do-Yeon Choi, Jinho Chun, PARK MYEONG-SOON, AHN EUNCHUL, CHUNG HYUNSOO, KIM SEOKHO, CHOI DO-YEON, CHUN JINHO
Принадлежит: Samsung Electronics Co., Ltd

A method of forming a connection terminal may include preparing a substrate, forming a first conductor of a tube shape having an opened upper portion on the substrate, forming a second conductor on the first conductor, and annealing the second conductor so that a portion of the second conductor extends in an internal space of the first conductor through the opened upper portion.

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Номер записи: 18
16-09-2009 дата публикации

Semiconductor package and multi-chip package using the same

Номер: TW0200939447A
Автор: PARK MYEONG-SOON, CHUNG HYUN-SOO, KIM SEOK-HO, KIM KI-HYUK, SHIN CHANG-WOO, PARK, MYEONG-SOON, CHUNG, HYUN-SOO, KIM, SEOK-HO, KIM, KI-HYUK, SHIN, CHANG-WOO
Принадлежит:

A semiconductor package may have a semiconductor chip that includes a chip pad formed on a substrate including an integrated circuit, and a passivation layer exposing the chip pad, a first redistribution wiring layer that is connected to the chip pad and extends on the semiconductor chip and includes a wire bonding pad to provide wire bonding and a first solder pad to connect the first redistribution wiring layer to a second semiconductor chip, and a second redistribution wiring layer that is connected to the first redistribution wiring layer on the first redistribution wiring layer and includes a second solder pad to connect the second redistribution wiring layer to a third semiconductor chip.

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Номер записи: 19
10-12-2009 дата публикации

Methods of Forming Integrated Circuit Chips Having Vertically Extended Through-Substrate Vias Therein and Chips Formed Thereby

Номер: US2009305502A1
Автор: LEE HO-JIN, LEE KANG-WOOK, PARK MYEONG-SOON, CHOI JU-IL, HWANG SON-KWAN
Принадлежит:

Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.

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Номер записи: 20
29-12-2009 дата публикации

Stacked chip package and method for forming the same

Номер: US0007638365B2
Автор: Se-Young Jeong, Nam-Seog Kim, Cha-Jea Jo, Jong-Ho Lee, Myeong-Soon Park, JEONG SE-YOUNG, KIM NAM-SEOG, JO CHA-JEA, LEE JONG-HO, PARK MYEONG-SOON
Принадлежит: Samsung Electronics Co., Ltd., SAMSUNG ELECTRONICS CO LTD, SAMSUNG ELECTRONICS CO., LTD.

Provided is a stacked chip package and a method for forming the same. A spacer is formed on a side of an upper chip. A conductive line is formed on the spacer to electrically connect upper and lower chips. The reliability of the stacked chip package is improved because wire bonding is not used to electrically connect the upper and lower chips. Further, the overall size of the stacked chip package can be reduced as the height of bonding wire loops does not contribute to the overall stacked chip package height.

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Номер записи: 21
24-04-2008 дата публикации

STACKED CHIP PACKAGE AND METHOD FOR FORMING THE SAME

Номер: US2008096315A1
Автор: JEONG SE-YOUNG, KIM NAM-SEOG, JO CHA-JEA, LEE JONG-HO, PARK MYEONG-SOON
Принадлежит:

Provided is a stacked chip package and a method for forming the same. A spacer is formed on a side of an upper chip. A conductive line is formed on the spacer to electrically connect upper and lower chips. The reliability of the stacked chip package is improved because wire bonding is not used to electrically connect the upper and lower chips. Further, the overall size of the stacked chip package can be reduced as the height of bonding wire loops does not contribute to the overall stacked chip package height.

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Номер записи: 22
29-03-2007 дата публикации

Wiring structure of a semiconductor package and method of manufacturing the same, and wafer level package having the wiring structure and method of manufacturing the same

Номер: US2007069320A1
Автор: LEE IN-YOUNG, SIM SUNG-MIN, JANG DONG-HYEON, CHUNG HYUN-SOO, CHUNG JAE-SIK, RYU SEUNG-KWAN, PARK MYEONG-SOON, YOON JONG-KOOK, CHOI JU-IL
Принадлежит:

A wiring structure may include a pad, a conductive pattern and an insulating photoresist structure. The pad may be provided on a body and electrically connected to a circuit unit of the body. The conductive pattern may be provided on the body and may be electrically connected to the pad. The insulating photoresist structure may be provided on a surface of the conductive pattern. The insulating photoresist structure may have a contact hole through which the conductive pattern may be partially exposed. The insulating photoresist structure may be fabricated by providing a photosensitive photoresist film on the conductive layer, and patterning the photosensitive photoresist film by two photo processes.

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Номер записи: 23
06-04-2006 дата публикации

Method of forming bump that may reduce possibility of losing contact pad material

Номер: US2006073704A1
Автор: JEONG SE-YOUNG, LEE IN-YOUNG, SIM SUNG-MIN, SONG YOUNG-HEE, JANG DONG-HYEON, PARK MYEONG-SOON, PARK SUN-YOUNG, KIM SUN-BUM, CHUNG HYUN-SOO
Принадлежит:

A method of forming a bump may involve providing a seed layer on a contact pad of a wafer. A shielding layer and a photosensitive mask layer may be formed on the seed layer. The photosensitive mask layer may be exposed and developed to form a mask pattern. An exposed portion of the shielding layer may be removed. The bump may be formed by plating the exposed seed layer.

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Номер записи: 24
01-03-2007 дата публикации

SEMICONDUCTOR PACKAGE WIRING STRUCTURE, WAFER-LEVEL PACKAGE USING THE SAME AND THEIR MANUFACTURING METHODS

Номер: JP2007053346A
Автор: LEE IN-YOUNG, SIM SUNG-MIN, JANG DONG-HYEON, CHUNG HYUN-SOO, CHUNG JAE-SIK, RYU SEUNG-KWAN, PARK MYEONG-SOON, YOON JONG-KOOK, CHOI JU-IL
Принадлежит:

PROBLEM TO BE SOLVED: To provide not only a semiconductor package wiring structure simplifying a manufacturing process and its manufacturing method but also a wafer-level package using the structure and its manufacturing method. SOLUTION: A wiring structure 100 contains a pad 110, a conductive pattern 120, and a insulating photo resist structure 130. The pad is placed on a main unit 102 with a circuit 105 so that it can input a signal to or output it from the circuit. A conductive pattern is electrically connected to the pad and is placed on the top of the main unit. The insulating photo resist structure is formed on the entire top surface of the conductive pattern, and is equipped with a contact hole partially exposing the top surface of the conductive pattern. For wiring, the insulating photo resist structure is formed by treating twice a photo resist film formed on a metal film in the photography process, so that the wiring structure formation process can be simplified. COPYRIGHT: (C ...

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Номер записи: 25
05-06-2008 дата публикации

System-in-package (SiP) and method of manufacturing the same

Номер: US2008128888A1
Автор: PARK MYEONG-SOON, LEE IN-YOUNG, LEE HO-JIN, SEO MOON-SUN
Принадлежит:

Provided is a system-in-package (SiP) including a main chip and one or more sub chips. In the SiP, a first surface of the main chip is electrically connected with a second surface of the main chip, through a via electrode, the one or more sub chips are assembled on the second surface of the main chip on which a ReDistribution Line (RDL) is formed, and the length of the SiP is substantially equal to the length of the main chip.

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Номер записи: 26
01-12-2016 дата публикации

INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20160351472A1
Автор: MYEONG-SOON PARK, HYUN-SOO CHUNG, CHAN-HO LEE, PARK MYEONG-SOON, CHUNG HYUN-SOO, LEE CHAN-HO
Принадлежит:

An integrated circuit device is provided as follows. A connection terminal is disposed on a first surface of a semiconductor structure. A conductive pad is disposed on a second surface, opposite to the first surface, of the semiconductor structure. A through-substrate-via (TSV) structure penetrates through the semiconductor structure. An end portion of the TSV structure extends beyond the second surface of the semiconductor structure. The conductive pad surrounds the end portion of the TSV structure. The connection terminal is electrically connected to the conductive pad through the TSV structure 1. An integrated circuit device comprising:a semiconductor structure;a connection terminal disposed on a first surface of the semiconductor structure;a conductive pad disposed on a second surface, opposite to the first surface, of the semiconductor structure;a through-substrate-via (TSV) structure penetrating through the semiconductor structure, wherein an end portion of the TSV structure extends beyond the second surface of the semiconductor structure,wherein the conductive pad surrounds the end portion of the TSV structure, andwherein the connection terminal is electrically connected to the conductive pad through the TSV structure.2. The integrated circuit device of claim 1 , further comprising:an insulating layer disposed on the second surface of the semiconductor structure, a first portion surrounding a side wall of the conductive pad; and', 'a second portion overlapping vertically the conductive pad and surrounding a part of a side wall of the TSV structure, wherein the part of the side wall is disposed between the conductive pad and the second surface of the semiconductor structure., 'wherein the insulating layer comprises3. The integrated circuit device of claim 2 ,wherein the first portion and the second portion of the insulating layer are in contact with each other.4. The integrated circuit device of claim 2 ,wherein an upper surface of the first portion of the ...

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Номер записи: 27
08-05-2008 дата публикации

STACKED CHIP PACKAGE AND METHOD FOR FORMING THE SAME

Номер: JP2008109138A
Автор: JEONG SE-YOUNG, KIN NANSHAKU, JO CHA-JEA, LEE JONG-HO, PARK MYEONG-SOON
Принадлежит:

PROBLEM TO BE SOLVED: To provide a stacked chip package and a method of forming the same. SOLUTION: The stacked chip package has a spacer 20a formed on the side plane of an upper chip, and a metal wire electrically connecting the upper and lower chips or the like is formed on the spacer 20a. The method of forming the package includes a step of stacking a second semiconductor chip 30 on a first semiconductor chip 10, a step of forming a spacer 20a on the side plane of the second semiconductor chip 30, and a step of forming a metal wire for electrically connecting both the first semiconductor chip 10 and the second semiconductor chip 30 on the spacer 20a. COPYRIGHT: (C)2008,JPO&INPIT ...

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Номер записи: 28
26-01-2006 дата публикации

Methods of fabricating integrated circuit chips for multi-chip packaging and wafers and chips formed thereby

Номер: US2006019467A1
Автор: LEE IN-YOUNG, SIM SUNG-MIN, JANG DONG-HYEON, CHUNG HYUN-SOO, SONG YOUNG-HEE, PARK MYEONG-SOON
Принадлежит:

Methods of forming integrated circuit chips include forming a plurality of criss-crossing grooves in a semiconductor wafer having a plurality of contact pads thereon and filling the criss-crossing grooves with an electrically insulating layer. The electrically insulating layer is then patterned to define at least first and second through-holes therein that extend in a first one of the criss-crossing groves. The first and second through-holes are then filled with first and second through-chip connection electrodes, respectively. The semiconductor wafer is then diced into a plurality of integrated circuit chips by cutting through the electrically insulating layer in a criss-crossing pattern that overlaps with the locations of the criss-crossing grooves.

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Номер записи: 29
02-08-2007 дата публикации

Wafer level chip scale package having a gap and method for manufacturing the same

Номер: US2007176290A1
Автор: PARK MYEONG-SOON, CHUNG HYUN-SOO, LEE IN-YOUNG, CHUNG JAE-SIK, SIM SUNG-MIN, JANG DONG-HYEON, SONG YOUNG-HEE, RYU SEUNG-KWAN
Принадлежит:

A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.

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Номер записи: 30
23-03-2017 дата публикации

SEMICONDUCTOR PACKAGE

Номер: US20170084558A1
Автор: Sun-kyoung Seo, Tae-je Cho, Yong-hwan Kwon, Hyung-gil Baek, Hyun-soo Chung, Seung-kwan Ryu, Myeong-soon Park, SEO SUN-KYOUNG, CHO TAE-JE, KWON YONG-HWAN, BAEK HYUNG-GIL, CHUNG HYUN-SOO, RYU SEUNG-KWAN, PARK MYEONG-SOON, Seo Sun-kyoung, Cho Tae-je, Kwon Yong-hwan, Baek Hyung-gil, Chung Hyun-soo, Ryu Seung-kwan, Park Myeong-soon
Принадлежит:

A semiconductor package includes a semiconductor substrate and an electrode pad formed on the semiconductor substrate. The electrode pad includes a central portion and a peripheral portion, and a first pattern is located on the peripheral portion. A passivation layer is formed on the semiconductor substrate and the electrode pad. The passivation layer has an opening exposing the central portion of the electrode pad and a second pattern located on the first pattern. A seed layer is formed on the electrode pad and the passivation layer. The seed layer has a third pattern formed on the second pattern. A bump is formed on the seed layer and electrically connected to the electrode pad. An undercut is formed around the third pattern located under an edge of a lower portion of the bump. 1. A semiconductor package comprising:a semiconductor substrate;an electrode pad on the semiconductor substrate and including a central portion and a peripheral portion, wherein a first pattern is located on the peripheral portion;a passivation layer on the semiconductor substrate and the electrode pad, the passivation layer having an opening exposing the central portion of the electrode pad and a second pattern located on the first pattern;a seed layer on the electrode pad and the passivation layer and having a third pattern on the second pattern; anda bump on the seed layer and electrically connected to the electrode pad,wherein an undercut is formed in the third pattern located under an edge of a lower portion of the bump.2. The semiconductor package of claim 1 , wherein the bump comprises a pillar layer being in contact with the seed layer and a solder layer on the pillar layer.3. The semiconductor package of claim 2 , wherein a top surface of the pillar layer is a flat surface claim 2 , anda bottom surface of the pillar layer is a curved surface corresponding to the third pattern.4. The semiconductor package of claim 2 , wherein a distance from a center of the pillar layer to a side ...

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Номер записи: 31
26-01-2017 дата публикации

SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE HAVING THE SAME

Номер: US20170025384A1
Автор: MYEONG-SOON PARK, HYUN-SOO CHUNG, CHAN-HO LEE, PARK MYEONG-SOON, CHUNG HYUN-SOO, LEE CHAN-HO
Принадлежит:

Provided are a semiconductor chip and a semiconductor package capable of obtaining stability and reliability through a connection structure using a through-silicon-via (TSV). The semiconductor chip includes a semiconductor substrate and a through-silicon-via (TSV) structure penetrating through the semiconductor substrate. A connection pad includes a foundation base disposed on a lower surface of the semiconductor substrate and connected to the TSV structure. A protruding portion protrudes from the foundation base and extend to an inside of a first groove formed in a lower surface of the semiconductor substrate. 1. A semiconductor chip comprising:a semiconductor substrate;a through-silicon-via (TSV) structure penetrating the semiconductor substrate; anda connection pad comprising a foundation base disposed on a lower surface of the semiconductor substrate and connected to the TSV structure, and a protruding portion which protrudes from the foundation base and extends to an inside of a first groove formed in a lower surface of the semiconductor substrate.2. The semiconductor chip of claim 1 , further comprising:a chip alignment mark including a second groove formed in the lower surface of the semiconductor substrate, wherein a depth of the first groove is substantially the same as that of the second groove.3. The semiconductor chip of claim 2 , further comprising:a lower insulating layer covering a part of the lower surface of the semiconductor substrate and inner surfaces of the first and second grooves, and defining first and second recesses in the first and second grooves, wherein the protruding portion of the connection pad fills the first recess.4. The semiconductor chip of claim 2 , wherein the semiconductor substrate includes a TSV region in which the TSV structure is arranged and an element region in which a plurality of individual devices is arranged claim 2 , and wherein the chip alignment mark is arranged in the element region.5. The semiconductor chip of ...

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Номер записи: 32
12-01-2017 дата публикации

SEMICONDUCTOR CHIP INCLUDING CHIP PAD, REDISTRIBUTION WIRING TEST PAD, AND REDISTRIBUTION WIRING CONNECTION PAD

Номер: US20170011976A1
Автор: Myeong-soon PARK, Hyun-soo CHUNG, Chan-ho LEE, PARK MYEONG-SOON, CHUNG HYUN-SOO, LEE CHAN-HO, PARK Myeong-soon, CHUNG Hyun-soo, LEE Chan-ho
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor chip is disclosed that includes a chip pad disposed in a first region of a chip body, a redistribution wiring test pad disposed in the first region of the chip body spaced apart from the chip pad and connected to the chip pad through a redistribution wiring structure, and a redistribution wiring connection pad disposed in the first region of the chip body or a second region of the chip body and connected to the chip pad through the redistribution wiring structure.

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Номер записи: 33
05-06-2012 дата публикации

Semiconductor package and multi-chip package using the same

Номер: US0008193637B2
Автор: Myeong-soon Park, Hyun-soo Chung, Seok-ho Kim, Ki-hyuk Kim, Chang-woo Shin, PARK MYEONG-SOON, CHUNG HYUN-SOO, KIM SEOK-HO, KIM KI-HYUK, SHIN CHANG-WOO
Принадлежит: SAMSUNG Electronics Co., Ltd., PARK MYEONG-SOON, CHUNG HYUN-SOO, KIM SEOK-HO, KIM KI-HYUK, SHIN CHANG-WOO, SAMSUNG ELECTRONICS CO LTD, SAMSUNG ELECTRONICS CO., LTD.

A semiconductor package may have a semiconductor chip that includes a chip pad formed on a substrate including an integrated circuit, and a passivation layer exposing the chip pad, a first redistribution wiring layer that is connected to the chip pad and extends on the semiconductor chip and includes a wire bonding pad to provide wire bonding and a first solder pad to connect the first redistribution wiring layer to a second semiconductor chip, and a second redistribution wiring layer that is connected to the first redistribution wiring layer on the first redistribution wiring layer and includes a second solder pad to connect the second redistribution wiring layer to a third semiconductor chip.

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Номер записи: 34
25-01-2011 дата публикации

Methods of forming integrated circuit chips having vertically extended through-substrate vias therein and chips formed thereby

Номер: US0007875552B2
Автор: Ho-Jin Lee, Kang-Wook Lee, Myeong-Soon Park, Ju-il Choi, Son-Kwan Hwang, LEE HO-JIN, LEE KANG-WOOK, PARK MYEONG-SOON, CHOI JU-IL, HWANG SON-KWAN
Принадлежит: Samsung Electronics Co., Ltd., SAMSUNG ELECTRONICS CO LTD, SAMSUNG ELECTRONICS CO., LTD.

Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.

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Номер записи: 35
29-05-2008 дата публикации

METHOD OF FORMING METAL LAYER WIRING STRUCTURE ON BACKSIDE OF WAFER, METAL LAYER WIRING STRUCTURE FORMED USING THE METHOD, METHOD OF STACKING CHIP PACKAGE, AND CHIP PACKAGE STACK STRUCTURE FORMED USING THE METHOD

Номер: US2008122116A1
Автор: PARK MYEONG-SOON, LEE IN-YOUNG, LEE HO-JIN, OH YONG-TAE
Принадлежит:

Provided are a method of forming a metal layer wiring structure on the backside of a wafer, a metal layer wiring structure formed using the method, a method of stacking a chip package, and a chip package stack structure formed using the method. The method of stacking a chip package includes: forming recess patterns on a backside of wafers; forming a passivation layer on the backside of the wafers except for an area corresponding to a through electrode; forming a metal layer on the passivation layer; planarizing the metal layers to expose only the recess patterns; forming a lower insulating layer on the planarized metal layers except for an area corresponding to a contact portion with another wafer; forming an adhesive layer on the lower insulating layer of each of the wafers; and adhering the wafers to one another, wherein the recess patterns are formed using a laser.

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Номер записи: 36
12-05-2011 дата публикации

SEMICONDUCTOR DEVICE HAVING REWIRING STRUCTURE AND PACKAGE, AND METHOD OF FORMING THE SAME

Номер: JP2011097034A
Автор: KIN KIKAKU, KIN NANSHAKU, CHUNG HYUN-SOO, KIM SEOK-HO, PARK MYEONG-SOON, SHIN CHANG-WOO
Принадлежит:

PROBLEM TO BE SOLVED: To provide a semiconductor device having rewiring structure and a package, and a method of forming the same. SOLUTION: There are provided the semiconductor device and the method of forming the same including steps for forming a chip pad on a chip substrate, forming a passivation layer on the chip pad and the chip substrate, forming a first insulation layer on the passivation layer, forming a recess and a first opening in the first insulation layer, forming a second opening vertically aligned with the first opening in the passivation layer, forming a rewiring line in a rewiring line area of the recess, the first opening, and the second opening, forming a second insulation layer on the rewiring line and the first insulation layer, and forming an opening in the second insulation to expose a portion of the rewiring line as a rewiring pad. COPYRIGHT: (C)2011,JPO&INPIT ...

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Номер записи: 37
02-03-2006 дата публикации

ELECTRODE STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: JP2006060219A
Автор: CHUNG HYUN-SOO, SIM SUNG-MIN, CHO TOGEN, PARK MYEONG-SOON, SONG YOUNG-HEE
Принадлежит:

PROBLEM TO BE SOLVED: To provide an electrode structure of a semiconductor device and a method of manufacturing the same. SOLUTION: In the semiconductor device, a photosensitive film (adhesion reinforcing polymer layer) 216A is additionally applied on the surface of an electrode. A part of the photosensitive film 216A is uniformly removed on the electrode by a photolithography process. The electrode may be a solder ball 214A or a solder bump. The semiconductor device may be a wafer level package or a flip chip package. COPYRIGHT: (C)2006,JPO&NCIPI ...

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Номер записи: 38
09-02-2012 дата публикации

Apparatus for bump reflow and methods of forming bumps using the same

Номер: US20120031953A1
Автор: Eunchul Ahn, Myeong Soon PARK, Sanghee Lee, Taegyeong Chung, Ulhyoung LEE
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of forming wafer level bump includes forming at least one pre-bump on a first surface of a wafer, and performing a bump reflow process to the pre-bump while the first surface faces downward, such that a bump is formed.

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Номер записи: 39
07-01-2016 дата публикации

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

Номер: US20160005707A1
Автор: Kwon Yong-hwan, Lee Chan-Ho, PARK MYEONG-SOON
Принадлежит:

A semiconductor package includes a package board that includes an circuit pattern and a plurality of contact pads electrically connected to the circuit pattern; a semiconductor chip having a plurality of chip pads; and a bump structure including a plurality of connecting bumps electrically connected with the semiconductor chip and the circuit pattern and a plurality of gap adjusting bumps bonded to the semiconductor chip and shaped into a slender bar between the semiconductor chip and the package board, the gap adjusting bumps spacing the semiconductor chip from the package board such that a gap space, S, is maintained between the package board and the semiconductor chip. A method of fabrication and a memory unit are disclosed. 1. A semiconductor package comprising:a package board comprising an circuit pattern and a plurality of contact pads electrically connected to the circuit pattern;a semiconductor chip having a plurality of chip pads; anda bump structure comprising a plurality of connecting bumps electrically connected with the semiconductor chip and the circuit pattern and a plurality of gap adjusting bumps bonded to the semiconductor chip and shaped into a slender bar between the semiconductor chip and the package board, the gap adjusting bumps spacing the semiconductor chip from the package board such that a gap space, S, is maintained between the package board and the semiconductor chip.2. The semiconductor package of claim 1 , wherein the semiconductor chip includes a passivation pattern covering an active face thereof and through which the chip pads are exposed and the plurality of gap adjusting bumps comprises at least one slender body connected to the passivation layer and a sidewall solder member arranged on a sidewall of the slender body.3. The semiconductor package of claim 2 , wherein the sidewall of the slender body is shaped into a concave face that is directed to a center of the slender body and is at least partially covered with the sidewall ...

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Номер записи: 40
24-02-2022 дата публикации

Semiconductor chip including chip pad, redistribution wiring test pad, and redistribution wiring connection pad

Номер: US20220059417A1
Автор: Chan-Ho Lee, Hyun-Soo Chung, Myeong-Soon Park
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor chip is disclosed that includes a chip pad disposed in a first region of a chip body, a redistribution wiring test pad disposed in the first region of the chip body spaced apart from the chip pad and connected to the chip pad through a redistribution wiring structure, and a redistribution wiring connection pad disposed in the first region of the chip body or a second region of the chip body and connected to the chip pad through the redistribution wiring structure.

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Номер записи: 41
23-03-2017 дата публикации

SEMICONDUCTOR DEVICES WITH REDISTRIBUTION PADS

Номер: US20170084559A1
Автор: Chung Hyunsoo, JANG Ae-nee, Kim Won-young, Lee Chanho, PARK Myeong Soon
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

Semiconductor devices with redistribution pads are disclosed. The semiconductor device includes a plurality of electric pads provided on a semiconductor substrate, and a plurality of redistribution pads electrically connected to the electric pads and an outer terminal. The plurality of redistribution pads includes a plurality of first redistribution pads constituting a transmission path for a first electrical signal and at least one second redistribution pad constituting a transmission path for a second electrical signal different from the first electrical signal. The first redistribution pads are arranged on the semiconductor substrate to form at least two rows, and the at least one second redistribution pad is disposed between the at least two rows of the first redistribution pads. 1. A semiconductor device , comprising:a plurality of electric pads provided on a semiconductor substrate; anda plurality of redistribution pads electrically connected to the electric pads and to an outer terminal, a plurality of first redistribution pads forming a first transmission path for a first electrical signal; and', 'at least one second redistribution pad forming a second transmission path for a second electrical signal different from the first electrical signal,, 'wherein the plurality of redistribution pads include,'}the plurality of first redistribution pads are arrange on the semiconductor substrate to form at least two rows, andthe at least one second redistribution pad are disposed on the semiconductor substrate between the at least two rows of the first redistribution pads.2. The device of claim 1 , wherein the semiconductor substrate comprises:at least one peripheral region extending across a center of the semiconductor substrate; andat least two cell regions separated from each other by the peripheral region,wherein the first and second redistribution pads are arranged on the peripheral region and are parallel to an extension direction of the peripheral region.35-. ( ...

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Номер записи: 42
13-04-2017 дата публикации

SEMICONDUCTOR PACKAGE

Номер: US20170103958A1
Автор: Chung Hyunsoo, Lee Chanho, PARK Myeong Soon
Принадлежит:

A semiconductor package includes a semiconductor chip mounted on a substrate that has a top surface and a bottom surface opposite to each other, and connection members that connect the substrate and the semiconductor chip to each other. The connection members include first connection members disposed on a central region of the semiconductor chip and that have heights equal to each other, and second connection members disposed on an edge region of the semiconductor chip and that have heights equal to each other. The heights of the first connection members differ from the heights of the second connection members. 1. A semiconductor package comprising:a semiconductor chip mounted on a substrate, the semiconductor chip having a top surface and a bottom surface opposite to the top surface; andconnection members that connect the substrate and the semiconductor chip to each other,wherein the connection members comprise:first connection members disposed on a central region of the semiconductor chip, the first connection members having heights equal to each other; andsecond connection members disposed on an edge region of the semiconductor chip, the second connection members having heights equal to each other,wherein heights of the first connection members differ from heights of the second connection members.2. The semiconductor package of claim 1 , wherein the semiconductor chip is warped so that the bottom surface of the semiconductor chip is concave claim 1 , andthe heights of the first connection members are greater than the heights of the second connection members.3. The semiconductor package of claim 1 , wherein the semiconductor chip is warped so that the top surface of the semiconductor chip is concave claim 1 , andthe heights of the first connection members are less than the heights of the second connection members.4. The semiconductor package of claim 1 , wherein the connection members further comprise:third connection members disposed on a middle region disposed ...

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Номер записи: 43
08-06-2017 дата публикации

Semiconductor device

Номер: US20170162500A1
Автор: Chanho LEE, Hyunsoo Chung, Myeong Soon PARK
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device comprising: a substrate; a decoupling capacitor disposed on the substrate; a first connection pad vertically overlapping with the decoupling capacitor; a passivation layer exposing a portion of the first connection pad; and a first solder bump disposed on the first connection pad and covering a portion of a top surface of the passivation layer.

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Номер записи: 44
10-04-2008 дата публикации

Semiconductor chip and manufacturing process

Номер: DE102005036646B4
Автор: Dong-hyeon Suwon Jang, Hyun-Soo Hwaseong Chung, In-Young Yongin Lee, Myeong-Soon Suwon Park, Sung-Min Seongnam Sim, Young-Hee Seongnam Song
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Halbleiterchip mit – einem Halbleitersubstrat (32) mit einer Oberseite (35) und einer Unterseite (39) und wenigstens einer ersten Kontaktstelle (31), die auf der Oberseite benachbart zu einem Seitenrand des Halbleitersubstrats angeordnet ist, – einem Durchgangsloch (41), das durch einen seitlich am Halbleitersubstrat (32) vorgesehenen elektrischen Isolationsbereich hindurch an einer Stelle lateral zwischen der ersten Kontaktstelle und dem betreffenden Seitenrand eingebracht ist, und – einer Verbindungselektrode (43a, 43b), die elektrisch mit der ersten Kontaktstelle verbunden ist und sich einteilig von der ersten Kontaktstelle zu dem Durchgangsloch (41) und durch dieses hindurch zur Unterseite des Isolationsbereichs erstreckt, wobei der elektrische Isolationsbereich mit einer Unterseite koplanar zur Unterseite des Halbleitersubstrats abschließt. Semiconductor chip with A semiconductor substrate having a top side and a bottom side and at least one first contact point arranged on the top side adjacent to a side edge of the semiconductor substrate. - A through hole (41) which is inserted through a laterally on the semiconductor substrate (32) provided in the electrical insulation region at a position laterally between the first contact point and the respective side edge, and - A connecting electrode (43 a, 43 b), which is electrically connected to the first contact point and integrally extending from the first contact point to the through hole (41) and therethrough to the bottom of the insulating region, wherein the electrical insulation region with a bottom coplanar to the bottom of the semiconductor substrate completes.

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Номер записи: 45
08-06-2006 дата публикации

Integrated circuit chip having pass-through vias therein that extend between multiple integrated circuits on the chip

Номер: US20060118972A1
Автор: Dong-Hyeon Jang, Hyun-Soo Chung, In-Young Lee, Myeong-Soon Park, Seung-Duk Baek, Sung-min Sim, Young-hee Song
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Packaged integrated circuit devices include a package substrate and a multi-chip stack of integrated circuit devices on the package substrate. The multi-chip stack includes at least one chip-select rerouting conductor. This rerouting conductor extends from the package substrate to a chip pad on an upper one of the chips in the multi-chip stack. The chip-select rerouting conductor extends through a first via hole in a lower one of the chips in the multi-chip stack.

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Номер записи: 46
06-04-2006 дата публикации

Method of forming bump that may reduce possibility of losing contact pad material

Номер: US20060073704A1
Автор: Dong-Hyeon Jang, Hyun-Soo Chung, In-Young Lee, Myeong-Soon Park, Se-young Jeong, Sun-bum Kim, Sun-Young Park, Sung-min Sim, Young-hee Song
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of forming a bump may involve providing a seed layer on a contact pad of a wafer. A shielding layer and a photosensitive mask layer may be formed on the seed layer. The photosensitive mask layer may be exposed and developed to form a mask pattern. An exposed portion of the shielding layer may be removed. The bump may be formed by plating the exposed seed layer.

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Номер записи: 47
18-07-2023 дата публикации

Semiconductor chip including chip pad, redistribution wiring test pad, and redistribution wiring connection pad

Номер: US11705376B2
Автор: Chan-Ho Lee, Hyun-Soo Chung, Myeong-Soon Park
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor chip is disclosed that includes a chip pad disposed in a first region of a chip body, a redistribution wiring test pad disposed in the first region of the chip body spaced apart from the chip pad and connected to the chip pad through a redistribution wiring structure, and a redistribution wiring connection pad disposed in the first region of the chip body or a second region of the chip body and connected to the chip pad through the redistribution wiring structure.

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Номер записи: 48
28-09-2006 дата публикации

Wafer level chip scale package having a gap and method for manufacturing the same

Номер: US20060214293A1
Автор: Dong-Hyeon Jang, Hyun-Soo Chung, In-Young Lee, Jae-Sik Chung, Myeong-Soon Park, Seung-Kwan Ryu, Sung-min Sim, Young-hee Song
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.

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Номер записи: 49
01-05-2018 дата публикации

Semiconductor device

Номер: US09960112B2
Автор: Chanho LEE, Hyunsoo Chung, Myeong Soon PARK
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device comprising: a substrate; a decoupling capacitor disposed on the substrate; a first connection pad vertically overlapping with the decoupling capacitor; a passivation layer exposing a portion of the first connection pad; and a first solder bump disposed on the first connection pad and covering a portion of a top surface of the passivation layer.

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Номер записи: 50
02-01-2018 дата публикации

Semiconductor devices with redistribution pads

Номер: US09859204B2
Автор: Ae-nee JANG, Chanho LEE, Hyunsoo Chung, Myeong Soon PARK, Won-Young Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Semiconductor devices with redistribution pads are disclosed. The semiconductor device includes a plurality of electric pads provided on a semiconductor substrate, and a plurality of redistribution pads electrically connected to the electric pads and an outer terminal. The plurality of redistribution pads includes a plurality of first redistribution pads constituting a transmission path for a first electrical signal and at least one second redistribution pad constituting a transmission path for a second electrical signal different from the first electrical signal. The first redistribution pads are arranged on the semiconductor substrate to form at least two rows, and the at least one second redistribution pad is disposed between the at least two rows of the first redistribution pads.

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Номер записи: 51