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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 4116. Отображено 100.

12-01-2012 дата публикации

Redistribution layers for microfeature workpieces, and associated systems and methods

Номер: US20120007256A1

Автор: David Pratt

Принадлежит: Micron Technology Inc

Redistribution layers for microfeature workpieces, and associated systems and methods are disclosed. One method for processing a microfeature workpiece system includes positioning a pre-formed redistribution layer as a unit proximate to and spaced apart from a microfeature workpiece having an operable microfeature device. The method can further include attaching the redistribution layer to the microfeature workpiece and electrically coupling the redistribution layer to the operable microfeature device.

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Номер записи: 1

09-02-2012 дата публикации

Semiconductor device

Номер: US20120032325A1

Автор: Osamu Miyata, Shingo Higuchi

Принадлежит: ROHM CO LTD

There is provided a semiconductor device with which stress can be prevented from locally concentrating on an external connecting terminal on a post and thus damages of the external connecting terminal can be prevented. The semiconductor device includes a semiconductor chip, a sealing resin layer stacked on a surface of the semiconductor chip, and the post which penetrates the sealing resin layer in a stacking direction of the semiconductor chip and the sealing resin layer, protrudes from the sealing resin layer, and has a periphery of the protruding portion opposedly in contact with a surface of the sealing resin layer in the stacking direction.

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Номер записи: 2

23-02-2012 дата публикации

Mechanisms for forming copper pillar bumps using patterned anodes

Номер: US20120043654A1

Автор: Chih-Wei Lin, Chung-Shi Liu, Ming-Da Cheng, Wen-Hsiung LU

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The mechanisms of preparing bump structures described by using patterned anodes may simplify bump-making process, reduce manufacturing cost, and improve thickness uniformity within die and across the wafer. In addition, the mechanisms described above allow forming bumps with different heights to allow bumps to be integrated with elements on a substrate with different heights. Bumps with different heights expand the application of copper post bumps to enable further chip integration.

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Номер записи: 3

15-03-2012 дата публикации

Semiconductor chip, stacked chip semiconductor package including the same, and fabricating method thereof

Номер: US20120061834A1

Автор: Tae Min Kang

Принадлежит: Hynix Semiconductor Inc

A semiconductor chip includes a silicon wafer formed with a via hole, a metal wire disposed in the via hole, and a filler that exposes a part of an upper portion of the metal wire while filing the via hole.

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Номер записи: 4

22-03-2012 дата публикации

Microsprings Partially Embedded In A Laminate Structure And Methods For Producing Same

Номер: US20120068331A1

Автор: Eric Peeters, Eugene M. Chow

Принадлежит: Palo Alto Research Center Inc

At least one microspring has applied thereover a laminate structure to provide: mechanical protection during handling and wafer processing, a spring spacer layer, strengthening of the anchor between spring and substrate, provision of a gap stop during spring deflection, and moisture and contaminant protection. A fully-formed laminate structure may be applied over the microspring structure or a partly-formed laminate structure may be applied over the microspring structure then cured or hardened. The tip portion of the microspring may protrude through the laminate structure and be exposed for contact or may be buried within the contact structure. The laminate structure may remain in place in the final microspring structure or be removed in whole or in part. The laminate structure may be photolithographically patternable material, patterned and etched to remove some or all of the structure, forming for example additional structural elements such as a gap stop for the microspring.

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Номер записи: 5

22-03-2012 дата публикации

Semiconductor device and manufacturing method thereof

Номер: US20120068334A1

Автор: Hirokazu Ezawa, Soichi Yamashita, Tatsuo Migita

Принадлежит: Toshiba Corp

Semiconductor devices of embodiments include a plurality of solder bumps electrically connected on a plurality of electrode pads disposed on a semiconductor substrate in parallel at a pitch of 40 μm or less via under bump metals. The ratio of the diameter (the top diameter) of the portion of each solder bump most away from the semiconductor substrate and the diameter (the bottom diameter) of the bottom side of each solder bump is 1:1 to 1:4.

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Номер записи: 6

22-03-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120069530A1

Автор: Kazushige Kanda, Satoshi Inoue, Yuui Shimizu

Принадлежит: Toshiba Corp

According to one embodiment, a semiconductor device includes a stacked chip includes semiconductor chips which are stacked, the semiconductor chips comprises semiconductor substrates and through electrodes formed in the semiconductor substrates, respectively, the through electrodes being electrically connected, and deactivating circuits provided in the semiconductor chips, respectively, and configured to deactivate a failed semiconductor chip.

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Номер записи: 7

12-04-2012 дата публикации

Semiconductor assembly and semiconductor package including a solder channel

Номер: US20120086123A1

Автор: Jeong-Woo Park, Moon-Gi Cho, Sun-Hee Park, Ui-Hyoung Lee

Принадлежит: SAMSUNG ELECTRONICS CO LTD

Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

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Номер записи: 8

19-04-2012 дата публикации

Semiconductor device, method for forming the same, and data processing system

Номер: US20120091520A1

Автор: Nobuyuki Nakamura

Принадлежит: Elpida Memory Inc

A semiconductor device includes a semiconductor substrate, a first interlayer insulating film over the semiconductor substrate, a first interconnect over the first interlayer insulating film, and a via plug penetrating the semiconductor substrate and the first interlayer insulating film. The via plug is coupled to the first interconnect.

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Номер записи: 9

10-05-2012 дата публикации

Method for manufacturing a semiconductor device having a refractory metal containing film

Номер: US20120115324A1

Автор: Mari Watanabe, Toshiyuki Takewaki

Принадлежит: Renesas Electronics Corp

A semiconductor device and a method for manufacturing the same of the present invention in which the semiconductor device is provided with a fuse structure or an electrode pad structure, suppress the copper blowing-out from a copper containing metal film. The semiconductor device comprises a silicon substrate, SiO 2 film provided on the silicon substrate, copper films embedded in the SiO 2 film, TiN films covering an upper face of a boundary region between an upper face of copper films and the copper films, and the SiO 2 film, and SiON films covering an upper face of the TiN films.

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Номер записи: 10

24-05-2012 дата публикации

Package carrier

Номер: US20120125669A1

Автор: Chau-Jie Zhan, Jing-Yao Chang, Tao-Chih Chang, Tsung-Fu Tsai

Принадлежит: Industrial Technology Research Institute ITRI

A package carrier including a substrate, at least an under bump metallurgic (UBM) layer and at least a conductive bump is provided. The substrate has a conductive structure and at least a pad connected with the conductive structure. A region of the pad connected with the conductive structure is a signal source region. The UBM layer is disposed on the pad and includes a first conductive pattern and a second conductive pattern. A side wall of the second conductive pattern is directly connected to a side wall of the first conductive pattern, and the second conductive pattern is disposed close to the signal source region. The conductivity of the second conductive pattern is smaller than the conductivity of the first conductive pattern. The conductive bump is disposed on the UBM layer.

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Номер записи: 11

24-05-2012 дата публикации

Method of manufacturing semiconductor device

Номер: US20120129335A1

Автор: Hiroyuki Yoda, Masamitsu Ikumo, Yoshito Akutagawa

Принадлежит: Fujitsu Semiconductor Ltd

A method of manufacturing a semiconductor device including the following steps: forming an insulator layer over a first conductor over a semiconductor substrate; forming a barrier layer to coat the surface of the insulator layer; forming a second conductor over the barrier layer; melting the second conductor in an atmosphere containing either hydrogen or carboxylic acid in a condition that the surface of the insulator layer over the first conductor is coated with the barrier layer; and removing the barrier layer partially from the surface of the insulator layer with the second conductor as a mask.

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Номер записи: 12

31-05-2012 дата публикации

Tsv substrate structure and the stacked assembly thereof

Номер: US20120133030A1

Автор: Cha-Hsin Lin, Chung-Chih Wang, Pei-Jer Tzeng, Tzu-Kun Ku

Принадлежит: Industrial Technology Research Institute ITRI

The disclosure provides a TSV substrate structure and the stacked assembly of a plurality of the substrate structures, the TSV substrate structure including: a substrate comprising a first surface, a corresponding second surface, and a TSV communicating the first surface with the second surface through the substrate; and a conductor unit completely filling the TSV, the conductor unit comprising a conductor body which has a first and a second ends corresponding to the first and second surfaces of the substrate, respectively.

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Номер записи: 13

21-06-2012 дата публикации

Tsv for 3d packaging of semiconductor device and fabrication method thereof

Номер: US20120153496A1

Автор: Chang-woo Lee, Jae-hak Lee, Joon-Yub Song, Tae-Ho Ha

Принадлежит: Korea Institute of Machinery and Materials KIMM

The present invention relates to a through silicon via (TSV) for 3D packaging to integrate a semiconductor device and a method for manufacturing the same, and more particularly, to a through silicon via (TSV) for 3D packaging of a semiconductor device that is capable of improving production efficiency, having very high electric conductivity, and minimizing electrical signal delay, without using a carrier wafer by self-aligning substrates in a low temperature state and sequentially bonding a plurality of semiconductor dies (or semiconductor chips), and a method of manufacturing the same.

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Номер записи: 14

19-07-2012 дата публикации

Packaging substrate with conductive structure

Номер: US20120181688A1

Автор: Shih-Ping Hsu

Принадлежит: Individual

A packaging substrate with conductive structure is provided, including a substrate body having at least one conductive pad on a surface thereof, a stress buffer metal layer disposed on the conductive pad and a thickness of the stress buffer metal layer being 1-20 μm, a solder resist layer disposed on the substrate body and having at least one opening therein for correspondingly exposing a portion of top surface of the stress buffer metal layer, a metal post disposed on a central portion of the surface of the stress buffer metal layer, and a solder bump covering the surfaces of the metal post. Therefore, a highly reliable conductive structure is provided, by using the stress buffer metal layer to release thermal stresses, and using the metal post and the solder bump to increase the height of the conductive structure.

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Номер записи: 15

23-08-2012 дата публикации

Chip package with plank stack of semiconductor dies

Номер: US20120211878A1

Автор: Bruce M. Guenin, Darko R. Popovic, David C. Douglas, Ivan Shubin, Jing Shi, John A. Harada, Matthew D. Giere, Theresa Y. Sze

Принадлежит: Oracle International Corp

In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are separated by a mechanical spacer (such as a filler material or an adhesive). Moreover, the chip package includes a substrate at a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the substrate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as: solder, stud bumps, plated traces, wire bonds, spring connectors, a conductive adhesive and/or an anisotropic conducting film. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the substrate.

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Номер записи: 16

30-08-2012 дата публикации

Bonded Semiconductor Structure With Pyramid-Shaped Alignment Openings and Projections

Номер: US20120217610A1

Автор: Luu Nguyen, Peter J. Hopper, Peter Johnson, Peter Smeys

Принадлежит: National Semiconductor Corp

A bonded semiconductor structure is formed in a method that first forms a female semiconductor structure with pyramid-shaped openings and a male semiconductor structure with pyramid-shaped projections, and then inserts the projections into the openings to align the male semiconductor structure to the female semiconductor structure for bonding.

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Номер записи: 17

06-09-2012 дата публикации

Etching liquid for etching silicon substrate rear surface in through silicon via process and method for manufacturing semiconductor chip having through silicon via using the etching liquid

Номер: US20120225563A1

Автор: Ryuji Sotoaka, Yoshiko Fujioto

Принадлежит: Mitsubishi Gas Chemical Co Inc

Disclosed are an etching liquid which is used for etching a silicon substrate rear surface in a through silicon via process, etches only a silicon substrate without etching a connecting plug composed of a metal such as copper, tungsten, etc., or polysilicon or the like, and has an excellent etching rate; and a method for manufacturing a semiconductor chip having a through silicon via using the same. The etching liquid is an etching liquid for etching a silicon substrate rear surface in a through silicon via process containing potassium hydroxide, hydroxylamine, and water; and the method for manufacturing a semiconductor chip includes a silicon substrate rear surface etching step using the etching liquid.

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Номер записи: 18

18-10-2012 дата публикации

Test structure and methodology for three-dimensional semiconductor structures

Номер: US20120262197A1

Автор: Christopher M. Durham, Donald L. Wheater, Jerome L. Cann, Kerry Bernstein, Paul D. Kartschoke, Peter J. Klim

Принадлежит: International Business Machines Corp

A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.

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Номер записи: 19

01-11-2012 дата публикации

Semiconductor Device and Method of Making a Semiconductor Device

Номер: US20120273935A1

Автор: Beng Keh See, Chin Wei Ronnie Tan, Horst Theuss, Kathleen Ong, Kian Pin Queck, Stefan Martens, Tze Yang Hin, Ulrich Krumbein

Принадлежит: INFINEON TECHNOLOGIES AG

A semiconductor device and a method of manufacturing a semiconductor device are disclosed. An embodiment comprises forming a bump on a die, the bump having a solder top, melting the solder top by pressing the solder top directly on a contact pad of a support substrate, and forming a contact between the die and the support substrate.

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Номер записи: 20

29-11-2012 дата публикации

Pad structure, circuit carrier and integrated circuit chip

Номер: US20120299192A1

Автор: Yeh-Chi Hsu, Yu-Kai Chen

Принадлежит: Via Technologies Inc

A pad structure is suitable for a circuit carrier or an integrated circuit chip. The pad structure includes an inner pad, a conductive via and an outer pad. The conductive via connects the inner pad. The outer pad connects the conductive via and further connects a conductive ball or a conductive bump. The outer diameter of the outer pad is greater than the outer diameter of the inner pad.

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Номер записи: 21

13-12-2012 дата публикации

Semiconductor device structures

Номер: US20120313248A1

Автор: Mark E. Tuttle

Принадлежит: Micron Technology Inc

The present invention relates to methods for forming through-wafer interconnects in semiconductor substrates and the resulting structures. In one embodiment, a method for forming a through-wafer interconnect includes providing a substrate having a pad on a surface thereof, depositing a passivation layer over the pad and the surface of the substrate, and forming an aperture through the passivation layer and the pad using a substantially continuous process. An insulative layer is deposited in the aperture followed by a conductive layer and a conductive fill. In another embodiment of the invention, a semiconductor device is formed including a first interconnect structure that extends through a conductive pad and is electrically coupled with the conductive pad while a second interconnect structure is formed through another conductive pad while being electrically isolated therefrom. Semiconductor devices and assemblies produced with the methods are also disclosed.

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Номер записи: 22

03-01-2013 дата публикации

Bump-on-trace (bot) structures

Номер: US20130001778A1

Автор: Han-Ping Pu, Tin-Hao Kuo, Yu-feng Chen, Yuh Chern Shieh

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A bump-on-trace (BOT) structure is described. The BOT structure includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis. The BOT structure further includes a second work piece with an elongated metal bump, wherein the elongated metal bump has a second axis, wherein the second axis is at a non-zero angle from the first axis. The BOT structure further includes a metal bump, wherein the metal bump electrically connects the metal trace and the elongated metal bump. A package having a BOT structure and a method of forming the BOT structure are also described.

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Номер записи: 23

17-01-2013 дата публикации

Interconnection and assembly of three-dimensional chip packages

Номер: US20130015578A1

Автор: Ashok V. Krishnamoorthy, Hiren D. Thacker, Ivan Shubin, John E. Cunningham

Принадлежит: Oracle International Corp

In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are aligned by positive features that are mechanically coupled to negative features recessed below the surfaces of adjacent semiconductor dies. Moreover, the chip package includes an interposer plate at approximately a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the interposer plate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as solder balls or spring connectors. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the interposer plate.

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Номер записи: 24

07-02-2013 дата публикации

Integrated Inductor

Номер: US20130032923A1

Автор: Chen-Shien Chen, Ching-Wen Hsiao, Mirng-Ji Lii, Tsung-Ding Wang, Yen-Liang Lin

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A system and method for providing an integrated inductor with a high Quality factor (Q) is provided. An embodiment comprises a magnetic core that is in a center of a conductive spiral. The magnetic core increases the inductance of the integrated inductor to allow the inductor to be used in applications such as a RF choke. The magnetic core may be formed in the same manner and time as an underbump metallization.

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Номер записи: 25

25-04-2013 дата публикации

Multiple die stacking for two or more die

Номер: US20130100616A1

Автор: Belgacem Haba, Wael Zohni

Принадлежит: Tessera LLC

A microelectronic package can include a substrate having first and second opposed surfaces, and first and second microelectronic elements having front surfaces facing the first surface. The substrate can have a plurality of substrate contacts at the first surface and a plurality of terminals at the second surface. Each microelectronic element can have a plurality of element contacts at the front surface thereof. The element contacts can be joined with corresponding ones of the substrate contacts. The front surface of the second microelectronic element can partially overlie a rear surface of the first microelectronic element and can be attached thereto. The element contacts of the first microelectronic element can be arranged in an area array and are flip-chip bonded with a first set of the substrate contacts. The element contacts of the second microelectronic element can be joined with a second set of the substrate contacts by conductive masses.

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Номер записи: 26

02-05-2013 дата публикации

Method to form solder deposits and non-melting bump structures on substrates

Номер: US20130105329A1

Автор: Catherine Schoenenberger, Ingo Ewert, Jürgen Kress, Kai-Jens Matejat, Sven Lamprecht

Принадлежит: Atotech Deutschland GmbH and Co KG

Described is a method of forming a metal or metal alloy layer onto a substrate comprising the following steps i) provide a substrate including a permanent resin layer on top of at least one contact area and a temporary resin layer on top of the permanent resin layer, ii) contact the entire substrate area including the at least one contact area with a solution suitable to provide a conductive layer on the substrate surface and i) electroplate a metal or metal alloy layer onto the conductive layer.

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Номер записи: 27

23-05-2013 дата публикации

Adjusting Sizes of Connectors of Package Components

Номер: US20130127059A1

Автор: Chia-Tung Chang, Chien Rhone Wang, Chih-Wei Lai, Chung-Shi Liu, Hung-Jui Kuo, Ming-Che Ho, Tzong-Hann Yang

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A device includes a plurality of connectors on a top surface of a package component. The plurality of connectors includes a first connector having a first lateral dimension, and a second connector having a second lateral dimension. The second lateral dimension is greater than the first lateral dimension. The first and the second lateral dimensions are measured in directions parallel to a major surface of the package component.

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Номер записи: 28

15-08-2013 дата публикации

Semiconductor chips including passivation layer trench structure

Номер: US20130207263A1

Автор: Deepak Kulkarni, Michael W. Lane, Satyanayana V. Nitta, Shom Ponoth

Принадлежит: International Business Machines Corp

An integrated circuit including an active region a passive region and a cut line in the passive region includes a passivation layer that includes an outer nitride layer over an oxide layer. The integrated circuit also includes a crack stop below the passivation layer and in the passive region, and a solder ball in the active region. The passivation layer has a trench formed therein in a location that is further from the active region than the crack stop and closer to the active region than the cut line, the trench passing completely through the outer nitride layer and a least a portion of the way through the oxide layer.

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Номер записи: 29

29-08-2013 дата публикации

Mechanisms of forming connectors for package on package

Номер: US20130221522A1

Автор: Chun-Hung Lin, Han-Ping Pu, Kai-Chiang Wu, Ming-Da Cheng, Yu-feng Chen

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The described embodiments of mechanisms of forming connectors for package on package enable smaller connectors with finer pitch, which allow smaller package size and additional connections. The conductive elements on one package are partially embedded in the molding compound of the package to bond with contacts or metal pads on another package. By embedding the conductive elements, the conductive elements may be made smaller and there are is gaps between the conductive elements and the molding compound. A pitch of the connectors can be determined by adding a space margin to a maximum width of the connectors. Various types of contacts on the other package can be bonded to the conductive elements.

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Номер записи: 30

29-08-2013 дата публикации

Electronic device and electronic component

Номер: US20130221523A1

Автор: Ryogo Honda, Tomokazu HONDA, Yoshihiro Kobayashi

Принадлежит: Yaskawa Electric Corp

The disclosure discloses an electronic device including an electronic component including a chip main body, a plurality of electrodes, a passivation which includes openings, and UBMs which are respectively formed to be smaller than an opening area of the opening, a substrate including a plurality of substrate electrodes, and a plurality of spherical solder bumps configured to electrically connect the plurality of electrodes with the plurality of substrate electrodes. The solder bump is bonded to the electrode at a bonding portion located on a bottom surface of the spherical shape. Each of the plurality of electrodes includes an exposed portion generated because a bonding area between the solder bump and the electrode via the UBM is smaller than the opening area. The solder bump is separated apart from the passivation via an upper space located above the exposed portion of the electrode.

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Номер записи: 31

05-09-2013 дата публикации

Semiconductor device structures and printed circuit boards comprising semiconductor devices

Номер: US20130228922A1

Автор: Mark E. Tuttle

Принадлежит: Micron Technology Inc

The present invention relates to methods for forming through-wafer interconnects in semiconductor substrates and the resulting structures. In one embodiment, a method for forming a through-wafer interconnect includes providing a substrate having a pad on a surface thereof, depositing a passivation layer over the pad and the surface of the substrate, and forming an aperture through the passivation layer and the pad using a substantially continuous process. An insulative layer is deposited in the aperture followed by a conductive layer and a conductive fill. In another embodiment of the invention, a semiconductor device is formed including a first interconnect structure that extends through a conductive pad and is electrically coupled with the conductive pad while a second interconnect structure is formed through another conductive pad while being electrically isolated therefrom. Semiconductor devices and assemblies produced with the methods are also disclosed.

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Номер записи: 32

12-09-2013 дата публикации

Semiconductor device bonding with stress relief connection pads

Номер: US20130234327A1

Автор: Hiroshi Okumura, Masaki Kasai

Принадлежит: ROHM CO LTD

An inventive semiconductor device includes: a semiconductor chip; an internal pad provided on a surface of the semiconductor chip for electrical connection; a surface protective film covering the surface of the semiconductor chip and having a pad opening from which the internal pad is exposed; a stress relief layer provided on the surface protective film and having an opening portion through which the internal pad exposed from the pad opening is exposed; a connection pad including an anchor buried in the pad opening and the opening portion and connected to the internal pad, and a projection provided integrally with the anchor as projecting on the stress relief layer, the projection having a width greater than an opening width of the opening portion; and a metal ball provided for external electrical connection as covering the projection of the connection pad.

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Номер записи: 33

19-09-2013 дата публикации

Contact Test Structure and Method

Номер: US20130240883A1

Автор: Hsien-Wei Chen, Jie Chen, Tsung-Yuan Yu, Ying-Ju Chen

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A system and method for testing electrical connections is provided. In an embodiment one or more floating pads may be manufactured in electrical connection with an underbump metallization structure. A test may then be performed to measure the electrical characteristics of the underbump metallization structure through the floating pad in order to test for defects. Alternatively, a conductive connection may be formed on the underbump metallization and the test may be performed on the conductive connection and the underbump metallization together.

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Номер записи: 34

24-10-2013 дата публикации

Cleaning Methods and Compositions

Номер: US20130276837A1

Автор: Chung-Shi Liu, Hui-Jung TSAI, Hung-Jui Kuo

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Methods and chemical solvents used for cleaning residues on metal contacts during a semiconductor device packaging process are disclosed. A chemical solvent for cleaning a residue formed on a metal contact may comprise a reactive inorganic component and a reactive organic component. The method may comprise spraying a semiconductor device with a chemical solvent at a first pressure, and spraying the semiconductor device with the chemical solvent at a second pressure less than the first pressure.

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Номер записи: 35

28-11-2013 дата публикации

Semiconductor device having wafer-level chip size package

Номер: US20130313703A1

Автор: Kiyonori Watanabe

Принадлежит: Oki Semiconductor Co Ltd

A semiconductor device including a semiconductor substrate with circuit elements and electrode pads formed on one surface. The surface is covered by a dielectric layer with openings above the electrode pads. A metal layer is included on the dielectric layer and patterned to form a conductive pattern with traces leading to the electrode pads. A protective layer is included as having openings exposing part of the conductive pattern. Each opening is covered by an electrode such as a solder bump, which is electrically connected through the conductive pattern to one of the electrode pads. The thickness of the protective layer, which may function as a package of the semiconductor device, is thus reduced. The protective layer may be formed from a photosensitive material, simplifying the formation of the openings for the electrodes.

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Номер записи: 36

12-12-2013 дата публикации

Semiconductor package and method for manufacturing the same

Номер: US20130328192A1

Автор: Dai Hyun JUNG, In Tae Kim, Jae Sik Park, Jeong Seok Lee

Принадлежит: Amkor Technology Inc

One embodiment provides a semiconductor package by forming a redistribution layer extending from a bonding pad of a semiconductor chip using a photoresist pattern plated with the seed layer. Fabrication of the semiconductor package is relatively simple thereby shortening a manufacturing time and reducing the manufacturing cost, and which can increase an adhered area of input/output terminals and can prevent delamination by connecting and welding the input/output terminals to a pair of redistribution layers.

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Номер записи: 37

26-12-2013 дата публикации

Semiconductor chip with expansive underbump metallization structures

Номер: US20130341785A1

Автор: Lei Fu, Lihong Cao, Xuefeng Zhang

Принадлежит: Advanced Micro Devices Inc

Methods and apparatus to protect fragile dielectric layers in a semiconductor chip are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first polymer layer over a conductor pad of a semiconductor chip where the conductor pad has a first lateral dimension. An underbump metallization structure is formed on the first polymer layer and in ohmic contact with the conductor pad. The underbump metallization structure has a second lateral dimension greater than the first lateral dimension. A second polymer layer is formed on the first polymer layer with a first opening exposing at least a portion of the underbump metallization structure.

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Номер записи: 38

26-12-2013 дата публикации

Method for manufacturing semiconductor device

Номер: US20130344658A1

Автор: Shinichi Sakurada

Принадлежит: Longitude Semiconductor SARL

A method for manufacturing a semiconductor device includes: preparing a semiconductor wafer including a plurality of semiconductor chips arranged in the shape of a matrix, the semiconductor wafer having a first bump electrode formed on one face thereof; forming a depressed portion on a first face of the semiconductor wafer, the depressed portion partitioning the semiconductor wafer into respective semiconductor chips; placing the first face of the semiconductor wafer onto a support tape; and cutting the semiconductor wafer along the depressed portion from a second face opposite to the first face of the semiconductor wafer by the use of a dicing blade having a width smaller than the width of the depressed portion to thereby divide the semiconductor wafer into a plurality of semiconductor chips.

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Номер записи: 39

02-01-2014 дата публикации

Integrated wluf and sod process

Номер: US20140001631A1

Автор: Rubayat Mahmud, Saikumar Jayaraman, Sriram Muthukumar

Принадлежит: Intel Corp

This disclosure relates generally to a wafer having a plurality of semiconductor chips having a major surface, a metal contact positioned on one of the plurality of semiconductor chips and having a side surface and contact surface, the contact surface substantially parallel to the major surface, wherein the contact surface defines a thickness of the metal contact relative to the major surface, an underfill layer abutting the one of the plurality of semiconductor chips and the side surface of the metal contact, the underfill layer having a top surface substantially parallel to the major surface, wherein the top surface of the underfill layer defines a thickness of the underfill layer relative to the major surface, the thickness of the underfill layer being not greater than the thickness of the metal contact, and a solder bump formed in electrical contact with the contact surface of the metal contact.

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Номер записи: 40

23-01-2014 дата публикации

Semiconductor manufacturing method and semiconductor structure thereof

Номер: US20140021601A1

Автор: Chia-Yeh Huang, Chih-Ming Kuo, Chin-Tang Hsieh, Lung-Hua Ho, Shih-Chieh Chang

Принадлежит: Chipbond Technology Corp

A semiconductor manufacturing method includes providing a carrier; forming a first photoresist layer; forming plural core portions; removing the first photoresist layer; forming a second photoresist layer; forming a plurality of connection portions, each of the plurality of connection portions includes a first connection layer and a second connection layer and connects to each of the core portions to form a hybrid bump, wherein each of the first connection layers comprises a base portion, a projecting portion and an accommodating space, each base portion comprises an upper surface, each projecting portion is protruded to the upper surface and located on top of each core portion, each accommodating space is located outside each projecting portion, the second connection layers cover the projecting portions and the upper surfaces, and the accommodating spaces are filled by the second connection layers; removing the second photoresist layer to reveal the hybrid bumps.

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Номер записи: 41

06-02-2014 дата публикации

Method for fabricating a through wire interconnect (twi) on a semiconductor substrate having a bonded connection and an encapsulating polymer layer

Номер: US20140038406A1

Автор: Alan G. Wood, David R Hembree

Принадлежит: Micron Technology Inc

A method for fabricating a through wire interconnect for a semiconductor substrate having a substrate contact includes the steps of: forming a via through the semiconductor substrate from a first side to a second side thereof; placing a wire in the via having a first end with a bonded connection to the substrate contact and a second end proximate to the second side; forming a first contact on the wire proximate to the first side; forming a second contact on the second end of the wire; and forming a polymer layer on the first side at least partially encapsulating the wire while leaving the first contact exposed.

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Номер записи: 42

06-02-2014 дата публикации

Fluorine depleted adhesion layer for metal interconnect structure

Номер: US20140038407A1

Автор: Emily R. Kinser, Mukta G. Farooq

Принадлежит: International Business Machines Corp

A line trough and a via cavity are formed within a dielectric layer comprising a fluorosilicate glass (FSG) layer. A fluorine depleted adhesion layer is formed within the line trough and the via cavity either by a plasma treatment that removes fluorine from exposed surfaces of the FSG layer, or by deposition of a substantially fluorine-free dielectric layer. Metal is deposited within the line trough and the via cavity to form a metal line and a metal via. The fluorine depleted adhesion layer provides enhanced adhesion to the metal line compared with prior art structures in which a metal line directly contacts a FSG layer. The enhanced adhesion of metal with an underlying dielectric layer provides higher resistance to delamination for a semiconductor package employing lead-free C4 balls on a metal interconnect structure.

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Номер записи: 43

27-02-2014 дата публикации

Methods and Apparatus of Packaging Semiconductor Devices

Номер: US20140057431A1

Автор: Chia-Wei Tu, Fu-Ying Huang, Hsien-Wei Chen, Ming-Song Sheu, Tsung-Fu Tsai, Yian-Liang Kuo

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface.

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Номер записи: 44

20-03-2014 дата публикации

Bump Structure and Method of Forming Same

Номер: US20140077358A1

Автор: Chen-Shien Chen, Guan-Yu Chen, Tin-Hao Kuo, Yu-Jen Tseng, Yu-Wei Lin

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent.

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Номер записи: 45

20-03-2014 дата публикации

Metal Bump and Method of Manufacturing Same

Номер: US20140077365A1

Автор: Chang-Chia HUANG, Chen-Shien Chen, Tin-Hao Kuo, Yen-Liang Lin, Yu-Jen Tseng

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An embodiment bump structure includes a contact element formed on a substrate, a passivation layer overlying the substrate, the passivation layer having a passivation opening exposing the contact element a polyimide layer overlying the passivation layer, the polyimide layer having a polyimide opening exposing the contact element an under bump metallurgy (UMB) feature electrically coupled to the contact element, the under bump metallurgy feature having a UBM width, and a copper pillar on the under bump metallurgy feature, a distal end of the copper pillar having a pillar width, the UBM width greater than the pillar width.

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Номер записи: 46

13-01-2022 дата публикации

METHOD FOR FORMING CONDUCTIVE LAYER, AND CONDUCTIVE STRUCTURE AND FORMING METHOD THEREFOR

Номер: US20220013479A1

Автор: Hsieh Ming-Teng

Принадлежит: CHANGXIN MEMORY TECHNOLOGIES, INC.

A method for forming the conductive layer includes: providing a first conductive film and a solution with a conductive material; coating a surface of the first conductive film with the solution, before performing the coating, a temperature of the first conductive film being lower than an evaporation temperature or a sublimation temperature of the solution; and in a process step of performing the coating or after performing the coating, heating the first conductive film, such that the temperature of the first conductive film is higher than or equal to the evaporation temperature or the sublimation temperature of the solution, and forming a second conductive film covering the surface of the first conductive film, wherein the second conductive film including the conductive material. 1. A method for forming a conductive layer , comprising:providing a first conductive film and a solution with a conductive material;coating a surface of the first conductive film with the solution, and prior to said coating, a temperature of the first conductive film being lower than an evaporation temperature or a sublimation temperature of the solution; andin a process step of performing the coating or after performing the coating, heating the first conductive film, such that the temperature of the first conductive film is higher than or equal to the evaporation temperature or the sublimation temperature of the solution, and forming a second conductive film covering the surface of the first conductive film, the second conductive film comprising the conductive material.2. The method for forming a conductive layer of claim 1 , wherein the first conductive film has a damaged surface; the damaged surface is coated with the solution; and after said coating claim 1 , the second conductive film covering the damaged surface is formed.3. The method for forming a conductive layer of claim 1 , wherein in a process step of heating the first conductive film claim 1 , the temperature of the first ...

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Номер записи: 47

07-01-2016 дата публикации

Method of forming semiconductor device having a conductive via structure

Номер: US20160005645A1

Автор: Kuo-Chin Chang, Yuh Chern Shieh

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method for fabricating a semiconductor device includes forming a first photo-sensitive layer over a contact pad, wherein the contact pad is on a substrate. The method further includes patterning the first photo-sensitive layer to form a first opening over a portion of the contact pad. The method further includes plating a conductive via in the first opening; and removing the first photo-sensitive layer. The method further includes forming a passivation layer over the substrate, contact pad, and conductive via, and exposing the conductive via by grinding the passivation layer. The method further includes forming a second photo-sensitive layer over the conductive via and passivation layer. The method further includes patterning the second photo-sensitive layer to form a second opening larger than and completely exposing the conductive via. The method further includes plating a conductive pillar in the second opening; and removing the second photo-sensitive layer.

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Номер записи: 48

07-01-2016 дата публикации

Semiconductor device

Номер: US20160005670A1

Автор: Yuuji IIZUKA

Принадлежит: Fuji Electric Co Ltd

A semiconductor device includes a supporting plate including a first surface, a second surface opposite to the first surface, and a through hole extending from the first surface to the second surface; and a semiconductor unit fixed to the first surface. The semiconductor unit includes an insulating plate, a circuit plate fixed to a front surface of the insulating plate, a semiconductor chip fixed to the circuit plate, and a protruding metal block fixed to a rear surface of the insulating plate and penetrating through the through hole to extend to the second surface.

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Номер записи: 49

07-01-2016 дата публикации

Semiconductor devices having through electrodes, methods of manufacturing the same, and semiconductor packages including the same

Номер: US20160005706A1

Автор: Wan Choon PARK

Принадлежит: SK hynix Inc

A semiconductor device includes a semiconductor layer having a first surface and a second surface, a through electrode penetrating the semiconductor layer and having a protruding portion that protrudes over the second surface of the semiconductor layer, a front-side bump disposed on the first surface of the semiconductor layer and electrically coupled to the through electrode, a passivation pattern including a first insulation pattern that surrounds a sidewall of the protruding portion of the through electrode and extends onto the second surface of the semiconductor layer and a second insulation pattern that covers the first insulation pattern and has an etch selectivity with respect to the first insulation pattern, and a back-side bump covering an end surface of the protruding portion of the through electrode and extending onto the passivation pattern.

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Номер записи: 50

03-01-2019 дата публикации

Semiconductor Device with Shielding Structure for Cross-Talk Reduction

Номер: US20190006289A1

Автор: Chen-Hua Yu, Chih-Yuan Chang, Chuei-Tang Wang, Chung-Hao Tsai, Sylvia Huang

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method includes embedding a die in a molding material; forming a first dielectric layer over the molding material and the die; forming a conductive line over an upper surface of the first dielectric layer facing away from the die; and forming a second dielectric layer over the first dielectric layer and the conductive line. The method further includes forming a first trench opening extending through the first dielectric layer or the second dielectric layer, where a longitudinal axis of the first trench is parallel with a longitudinal axis of the conductive line, and where no electrically conductive feature is exposed at a bottom of the first trench opening; and filling the first trench opening with an electrically conductive material to form a first ground trench.

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Номер записи: 51

03-01-2019 дата публикации

3D Packaging Method for Semiconductor Components

Номер: US20190006301A1

Автор: Fabrice Duval, Fumihiro Inoue

Принадлежит: Interuniversitair Microelektronica Centrum vzw IMEC

The present disclosure relates to a method for bonding semiconductor components. A semiconductor component comprising microbumps on a planar bonding surface is prepared for bonding by applying a photosensitive polymer layer on the bonding surface. The average thickness of the initial polymer layer in between the microbumps is similar to the average height of the microbumps. In a lithography process, the polymer is removed from the upper surface of the microbumps and from areas around the microbumps. The polymer is heated to a temperature at which the polymer flows, resulting in a polymer layer that closely adjoins the microbumps, without exceeding the microbump height. The closely adjoining polymer layer may have a degree of planarity substantially similar to a planarized layer.

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Номер записи: 52

03-01-2019 дата публикации

THERMAL PADS BETWEEN STACKED SEMICONDUCTOR DIES AND ASSOCIATED SYSTEMS AND METHODS

Номер: US20190006323A1

Автор: Gandhi Jaspreet S., Koopmans Michel

Принадлежит:

Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. Heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). In some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (UBM) structures. 1. A semiconductor die , comprising:a semiconductor substrate having a first surface and a second surface angled relative to the first surface, wherein the second surface at least partially defines an opening in the first surface;an interconnect extending at least partially through the semiconductor substrate, wherein the interconnect includes an end portion projecting from the opening, and wherein the end portion has a sidewall exposed from the semiconductor substrate in the opening;a metallization structure extending at least partially around the sidewall of the end portion of the interconnect, wherein the metallization structure is laterally spaced apart from the second surface of the semiconductor substrate; anda thermal pad on the first surface of the semiconductor substrate, wherein the thermal pad and the metallization structure project to generally the same vertical height above the first surface of the semiconductor substrate.2. The semiconductor die of claim 1 , further comprising a passivation material at least partially on the first surface of the semiconductor substrate.3. The semiconductor die of claim 1 , further comprising a passivation material in the opening between the metallization structure and the semiconductor substrate.4. The ...

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Номер записи: 53

03-01-2019 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20190006324A1

Автор: MIGITA Tatsuo, OGISO Koji

Принадлежит:

A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a first metal layer located on the first semiconductor substrate, a second metal layer located on the second semiconductor substrate, a third metal layer, a first alloy layer, and a second alloy layer. The third metal layer extends between the first metal layer and the second metal layer. The first alloy layer comprises components of the first and third metal layers, and is provided between the first metal layer and the third metal layer. The second alloy layer comprises components of the second and third metal layers, and is provided between the second metal layer and the third metal layer. At least one of the first metal the second metal layers projects into the third metal layer at a circumferential edge portion thereof. 1. A semiconductor device comprising:a first semiconductor substrate;a second semiconductor substrate facing the first semiconductor substrate;a first pad electrode disposed on a surface of the first semiconductor substrate facing the second semiconductor substrate;a second pad electrode disposed on a surface of the second semiconductor substrate facing the first semiconductor substrate;a first insulating layer disposed on an edge portion of the first pad electrode and the first semiconductor substrate;a second insulating layer disposed on an edge portion of the second pad electrode and the second semiconductor substrate;a first metal layer disposed over the first pad electrode and facing the second semiconductor substrate;a second metal layer disposed over the second pad electrode and facing the first semiconductor substrate;a third metal layer disposed between the first metal layer and the second metal layer;a first alloy layer disposed between the first metal layer and the third metal layer and comprising a component of the first metal layer and a component of the third metal layer; anda second alloy layer disposed between the second metal layer ...

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Номер записи: 54

03-01-2019 дата публикации

BUMP STRUCTURES FOR INTERCONNECTING FOCAL PLANE ARRAYS

Номер: US20190006409A1

Автор: Huang Wei, Paik Namwoong

Принадлежит:

A method of forming bump structures for interconnecting components includes dry etching a layer of insulating material to create a pattern for bump structures. A seed layer is deposited on the insulating material over the pattern. The seed layer is patterned with a photo resist material. The method also includes forming bump structures over the seed layer and the photo resist material with a plating material to form bump structures in the pattern, wherein the bump structures are isolated from one another. 1. A system comprising:a layer of insulating material with holes therein;a seed layer seated within the holes, wherein the seed layer is recessed below a top surface of the insulating material that is opposite a bottom surface of the holes; anda respective bump structure seated in the seed layer of each hole.2. The system as recited in claim 1 , wherein the bump structures are on one of a photodiode array (PDA) or a read-out integrated circuit (ROIC) claim 1 , and wherein the PDA and ROIC are joined together by the bump structures.3. The system as recited in claim 2 , wherein the PDA and ROIC define a plurality of pixels claim 2 , wherein the plurality of pixels have a pitch size claim 2 , wherein the pitch size is less than 10 μm.4. The system as recited in claim 1 , wherein the bump structures each have a diameter less than 5 um.5. The system as recited in claim 1 , wherein the bump structures each have a height to diameter ratio of greater than 1:1.6. The system as recited in claim 1 , wherein a portion of the bump structures extend from the seed layer proud of the top surface of the insulating material.7. The system as recited in claim 1 , further comprising a dielectric layer on the top surface of the insulating material claim 1 , wherein the seed layer is recessed below the insulating material to provide a gap between the bump structures and the insulating material claim 1 , wherein the gap between the bump structures and the insulating material is also ...

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Номер записи: 55

08-01-2015 дата публикации

DEVICE PACKAGING WITH SUBSTRATES HAVING EMBEDDED LINES AND METAL DEFINED PADS

Номер: US20150008578A1

Автор: Hlad Mark S., Lee Kyu Oh, Liu Yueli, Roy Mihir K., Salama Islam A., Wu Tao

Принадлежит:

Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing. 1. A method of forming an integrated circuit (IC) package substrate , the method comprising:laminating a first dielectric layer over a first metal feature;laser drilling a via in the dielectric layer to expose the first metal feature;laminating a permanent photodefinable layer over the first dielectric layer;patterning a pad into the permanent photodefinable layer, the pad disposed over the via;electrolytically plating a fill metal into the via and the pad;planarizing the fill metal to a top surface of the permanent photodefinable layer; andperforming a self-aligned plating of a surface finish metal over a top surface of the fill metal.2. The method of claim 1 , wherein filling the pad and via further comprises:depositing a catalyst on the permanent photodefinable layer;electrolessly plating a seed layer on the catalyst; andwherein the method further comprises removing the catalyst, with a wet chemical treatment, from the permanent photodefinable layer that is exposed when the fill metal is planarized.3. The method of claim 2 , wherein plating a surface finish metal over the fill metal further comprises: forming a catalyst on an exposed surface of the fill metal and plating one or more metal layers.4. A method of forming an integrated circuit (IC) package substrate claim 2 , the method comprising:laminating a first dielectric layer over a first metal feature;laser drilling a via in the dielectric layer to expose the first metal feature;laser patterning a trace in the dielectric laterally ...

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Номер записи: 56

18-01-2018 дата публикации

CONDUCTIVE CONNECTIONS, STRUCTURES WITH SUCH CONNECTIONS, AND METHODS OF MANUFACTURE

Номер: US20180019191A1

Автор: Katkar Rajesh, Uzoh Cyprian Emeka

Принадлежит: INVENSAS CORPORATION

A solder connection may be surrounded by a solder locking layer () and may be recessed in a hole () in that layer. The recess may be obtained by evaporating a vaporizable portion () of the solder connection. Other features are also provided. 1. A manufacturing method comprising: one or more first components each of which comprises solder and a material sublimatable or vaporizable when the solder is melted; and', 'a first layer comprising a top surface and one or more holes in the top surface, each hole containing at least a segment of a corresponding first component;, 'obtaining a first structure comprisingheating each first component to sublimate or vaporize at least part of each sublimatable or vaporizable material and provide an electrically conductive connection at a location of each first component;wherein in the heating operation at least part of each first component recedes down from the top surface to provide or increase a recess in each hole at the top surface.2. The method of wherein each hole is a through-hole.3. The method of wherein each hole's sidewall is a dielectric sidewall.4. The method of wherein the first layer is dielectric.5. The method of wherein the first layer is formed by molding.6. The method of further comprising:obtaining a second structure with one or more protruding conductive posts; andinserting each conductive post into a corresponding recess provided or increased in the heating operation, and forming a solder bond in each recess between the corresponding conductive post and the corresponding electrically conductive connection.7. The method of wherein before the heating operation claim 1 , at least a segment of each first component either:comprises of a solder core coated with the sublimatable or vaporizable material; orconsists of the sublimatable or vaporizable material.8. The method of wherein in obtaining the first structure claim 7 , the one or more first components are formed before the first layer.9. The method of wherein in ...

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Номер записи: 57

22-01-2015 дата публикации

SEMICONDUCTOR DEVICE WITH REDISTRIBUTION LAYERS ON PARTIAL ENCAPSULATION AND NON-PHOTOSENSITIVE PASSIVATION LAYERS

Номер: US20150021764A1

Автор: Bae JaeHun, Cha SeWoong, Kim DongJin, Kim JinHan, Kim Jinyoung, Kim SungKyu, Kim YoonJoo, Lee Seungjae, Paek JongSik, Park DooHyun

Принадлежит:

A semiconductor device with redistribution layers on partial encapsulation is disclosed and may include providing a carrier with a non-photosensitive protection layer, forming a pattern in the non-photosensitive protection layer, providing a semiconductor die with a contact pad on a first surface, and bonding the semiconductor die to the non-photosensitive protection layer such that the contact pad aligns with the pattern formed in the non-photosensitive protection layer. A second surface opposite to the first surface of the semiconductor die, side surfaces between the first and second surfaces of the semiconductor die, and a portion of a first surface of the non-photosensitive protection layer may be encapsulated with an encapsulant. The carrier may be removed leaving the non-photosensitive protection layer bonded to the semiconductor die. A redistribution layer may be formed on the contact pad and a second surface of the non-photosensitive protection layer opposite to the first surface. 1. A method for manufacturing a semiconductor device , the method comprising:providing a carrier with a non-photosensitive protection layer;forming a pattern in the non-photosensitive protection layer;providing a semiconductor die with a contact pad on a first surface;bonding the semiconductor die to the non-photosensitive protection layer such that the contact pad aligns with the pattern formed in the non-photosensitive protection layer;encapsulating a second surface opposite to the first surface of the semiconductor die, side surfaces between the first and second surfaces of the semiconductor die, and a portion of a first surface of the non-photosensitive protection layer with an encapsulant;removing the carrier and leaving the non-photosensitive protection layer bonded to the semiconductor die; andforming a redistribution layer on the contact pad and a second surface of the non-photosensitive protection layer opposite to the first surface.2. The method according to claim 1 , ...

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Номер записи: 58

22-01-2015 дата публикации

Semiconductor Device

Номер: US20150021765A1

Автор: Morifuji Tadahiro, Ueda Shigeyuki

Принадлежит:

Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion () formed on the upper surface of a semiconductor substrate (), a passivation layer () so formed on the upper surface of the semiconductor substrate () as to overlap a part of the electrode pad portion () and having a first opening portion () where the upper surface of the electrode pad portion () is exposed, a barrier metal layer () formed on the electrode pad portion (), and a solder bump () formed on the barrier metal layer (). The barrier metal layer () is formed such that an outer peripheral end () lies within the first opening portion () of the passivation layer () when viewed in plan. 110.-. (canceled)11. A semiconductor chip comprising:an electrode pad portion formed on a face of a substrate;a first protection layer including a first opening through which a top face of the electrode pad portion is exposed, the first protection layer disposed on the face of the substrate and overlapping part of the electrode pad portion;a barrier metal layer formed on the electrode pad portion;a bump electrode on the barrier metal layer; anda second protection layer covering a region on the first protection layer and a region on the electrode pad portion,wherein the first protection layer has a step part formed therein as a result of the first protection layer overlapping the part of the electrode pad portion,wherein the barrier metal layer has a circumferential end part thereof formed outward of the first opening as seen in a plan view,wherein the bump electrode is bonded to the barrier metal layer,wherein the barrier metal layer is on the electrode pad portion with a peripheral part of the barrier metal layer located over the second protection layer,wherein the second protection layer has a second opening through which the top face of the electrode pad portion is exposed and that has an opening width smaller than the first opening, ...

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Номер записи: 59

22-01-2015 дата публикации

Substrate for semiconductor package and process for manufacturing

Номер: US20150021766A1

Автор: Chun-Che Lee, Sheng-Ming Wang, Tien-Szu Chen

Принадлежит: Advanced Semiconductor Engineering Inc

A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved.

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Номер записи: 60

17-01-2019 дата публикации

METHOD FOR FORMING BUMP STRUCTURE

Номер: US20190019772A1

Автор: Chen Chun-Jen, Cheng Hsi-Kuei, LAI Yi-Jen, LEE Li-Guo, LIU Yi-Chen, LIU Yung-Sheng

Принадлежит:

Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a metal pad over a first substrate and forming a resist layer having an opening over the metal layer. The method for forming a semiconductor structure further includes forming a conductive pillar and a solder layer over the conductive pillar in the opening of the resist layer and removing the resist layer. The method for forming a semiconductor structure further includes removing a portion of the conductive pillar so that the conductive pillar has an angled sidewall. 1. A method for forming a semiconductor structure , comprising:forming a metal pad over a first substrate;forming a resist layer having an opening over the metal layer;forming a conductive pillar and a solder layer over the conductive pillar in the opening of the resist layer;removing the resist layer; andremoving a portion of the conductive pillar so that the conductive pillar has an angled sidewall.2. The method for forming a semiconductor structure as claimed in claim 1 , wherein the angled sidewall includes a first sidewall at a top portion of the conductive pillar and a second sidewall at a bottom portion of the conductive pillar claim 1 , and the first sidewall is in a first direction and the second sidewall is in a second direction different from the first direction.3. The method for forming a semiconductor structure as claimed in claim 2 , further comprising:reflowing the solder layer after the removing the portion of the conductive pillar to form the angled sidewall.4. The method for forming a semiconductor structure as claimed in claim 3 , wherein an inter-metal compound is formed partially covering the first sidewall of the top portion of the conductive pillar after reflowing the solder layer.5. The method for forming a semiconductor structure as claimed in claim 1 , further comprising:forming a seed layer over the metal pad before the conductive pillar is formed, ...

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Номер записи: 61

17-01-2019 дата публикации

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF

Номер: US20190019775A1

Автор: EGUCHI Toyokazu, KAWAMURA Takuma

Принадлежит:

A semiconductor device includes a board having a solder resist layer with first and second openings on a first surface, and a first electrode on the first surface, a portion thereof exposed in the first opening and electrically connected to the board. A second electrode is located on the first surface having a portion exposed in the second opening and electrically connected to the board. A portion of the second electrode is covered by the solder resist layer. A first solder bump is on the first electrode and covers a side surface. A second solder bump is on the second electrode. A semiconductor chip has a first region and a second region facing the first surface. A third electrode is in the first region and electrically connected to the first solder bump. A fourth electrode is in the second region and electrically connected to the second solder bump. 1. A semiconductor device , comprising:a board having a first surface;a solder resist layer on the first surface, the solder resist layer comprising a first opening and a second opening;a first electrode on the first surface and having a side surface exposed in the first opening, the first electrode electrically connected to the board;a second electrode, having an outer perimeter, on the first surface, wherein the second electrode electrically connected to the board and at least a portion of the outer perimeter of the second electrode covered by the solder resist layer;a first solder hump on the first electrode, the first solder bump covering the side surface of the first electrode;a second solder bump on the second electrode; anda semiconductor chip comprising a second surface facing the first surface, the second surface comprising a first region and a second region, wherein a third electrode in the first region of the semiconductor chip is electrically connected to the first solder bump, and a fourth electrode in the second region of the semiconductor chip is electrically connected to the second solder bump, ...

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Номер записи: 62

16-01-2020 дата публикации

PACKAGE WITH METAL-INSULATOR-METAL CAPACITOR AND METHOD OF MANUFACTURING THE SAME

Номер: US20200020623A1

Автор: Chen Shuo-Mao, Yeh Chiung-Han, Yeh Der-Chyang

Принадлежит:

A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A first polymer layer is formed on the chip and the molding compound, a second polymer layer is formed on the first polymer layer, and a plurality of interconnect structures is formed between the first polymer layer and the second polymer layer. A metal-insulator-metal (MIM) capacitor is formed on the second polymer layer and electrically coupled to at least one of the plurality of interconnect structures. A metal bump is formed over and electrically coupled to at least one of the plurality of interconnect structures. 1. A package comprising:a chip and a molding compound adjacent to each other;a first polymer layer and a second polymer layer that are stacked on the chip and the molding compound, wherein the second polymer layer overlies the first polymer layer;a first interconnect structure between the first and second polymer layers;a capacitor on the second polymer layer and protruding through the second polymer layer to the first interconnect structure, wherein the capacitor comprises a lower electrode, a dielectric layer overlying the lower electrode, and an upper electrode overlying the dielectric layer;a barrier layer overlying and independent of the upper electrode, wherein the barrier layer is conductive;a metal layer overlying the barrier layer, wherein the capacitor, the barrier layer, and the metal layer collectively define a first common sidewall and collectively define a second common sidewall on an opposite side of the capacitor as the first common sidewall;an isolation coating covering the first and second polymer layers and the metal layer, wherein the isolation coating directly contacts a top surface of the metal layer continuously from the first common sidewall to the second common sidewall; anda conductive bump in an opening defined by the isolation coating and level with the capacitor.2. The ...

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Номер записи: 63

26-01-2017 дата публикации

SEMICONDUCTOR DEVICE WITH TRENCH-LIKE FEED-THROUGHS

Номер: US20170025527A1

Автор: Chen Kuo-In, Chen Qufei, Choi Calvin, Kasem Mohammed, Katraro Reuven, Lui Kam Hong, Owyang King, Pattanayak Deva, TERRILL Kyle, Wong Ronald, Xu Robert

Принадлежит:

A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated. 1. A semiconductor device comprising:an electrically conductive substrate layer;a layer of drain metal, wherein said substrate layer is separated from said drain metal by an intervening layer;a plurality of gate trenches in a gate region under a layer of source metal and that extend into but not completely through said intervening layer, said gate trenches comprising a first gate trench and a second gate trench, each of said gate trenches filled with a first filler material;a plurality of source contact trenches in a source region under said layer of source metal and that that extend into but not completely through said intervening layer, each of said source contact trenches filled with a second filler material, said source contact trenches comprising a first source contact trench and a second source contact trench, wherein said first source contact trench is between said first gate trench and said second gate trench, and wherein said second gate trench is between said first source contact trench and said second source contact trench; anda plurality of feed-through trenches under said layer of drain metal and that extend completely through said intervening layer to said substrate layer, each of said feed-through trenches filled with said second filler material and coupled to said drain metal, wherein said plurality of feed-through trenches are arrayed in only a portion of a drain region of said device under said drain metal, wherein said plurality of feed-through trenches are not included outside said portion and wherein said feed-through trenches within said portion are concentrated toward said source region.2. The semiconductor device of wherein said first ...

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Номер записи: 64

10-02-2022 дата публикации

Semiconductor package and method of fabricating the same

Номер: US20220045008A1

Автор: Myungsam Kang, Taesung Jeong, Youngchan KO

Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor package and associated methods, the package including a substrate; first and second semiconductor chips on the substrate; and external terminals below the substrate, wherein the substrate includes a core portion; first and second buildup portions on top and bottom surfaces of the core portion, the first and second buildup portions including a dielectric pattern and a line pattern; and an interposer chip in an embedding region in the core portion and electrically connected to the first and second buildup portions, the interposer chip includes a base layer; a redistribution layer on the base layer; and a via that penetrates the base layer, the via being connected to the redistribution layer and exposed at a surface of the base layer, the redistribution layer is connected to a line pattern of the first buildup portion, and the via is connected to a line pattern of the second buildup portion.

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Номер записи: 65

05-02-2015 дата публикации

Copper Post Structure for Wafer Level Chip Scale Package

Номер: US20150035139A1

Автор: Chiang Yung-Ping, HSIEH CHEN-CHIH, Shih Chao-Wen, Tsai Hao-Yi

Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

In a method for forming a packaging structure, a metal pad is formed on a semiconductor substrate, and a first polymer insulating layer is formed over the semiconductor substrate. An opening passing through the first polymer insulating layer is formed to expose a portion of the metal pad. A copper-containing material is deposited in the opening and over the first polymer insulating layer, thereby forming a copper-containing layer having a first thickness and a first width over the first polymer insulating layer. A conductive bump having a second width is formed over the copper-containing layer, in which the second width is smaller than the first width. An exposed portion of the copper-containing layer is etched using the conductive bump as a mask until the exposed portion is reduced to a second thickness, thereby forming a monolithic copper-containing structure. 1. A device , comprising:a semiconductor substrate;a metal pad on the semiconductor substrate;a first polymer insulating layer overlying the semiconductor substrate and covering a portion of the metal pad;a monolithic copper-containing structure over the metal pad and the first polymer insulating layer, and electrically connected to the metal pad, the monolithic copper-containing structure comprising:a via portion contacting the metal pad embedded in the first polymer insulating layer;a bottom portion having a first thickness and a first width, wherein the bottom portion comprises a post-passivation interconnect (PPI) line; anda top portion adjoining the bottom portion and having a second thickness and a second width, the monolithic copper-containing structure having an undercut structure between the top portion and the bottom portion, wherein the second thickness is greater than the first thickness, and the first width is greater than the second width; anda conductive bump over the top portion of the monolithic copper-containing structure.2. The device of claim 1 , wherein the PPI line is a redistribution ...

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Номер записи: 66

02-02-2017 дата публикации

Semiconductor Devices and Methods of Forming Thereof

Номер: US20170033066A1

Автор: Alexander Heinrich, Evelyn Napetschnig, Thomas Fischer, Ulrike Fastner

Принадлежит: INFINEON TECHNOLOGIES AG

In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced.

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Номер записи: 67

02-02-2017 дата публикации

PACKAGING STRUCTURE

Номер: US20170033071A1

Автор: Ichikawa Sumihiro

Принадлежит:

A packaging structure includes a first substrate including a first metal terminal and a first protruding resin portion formed at a first surface; a second substrate including a second metal terminal and a second protruding resin portion formed at a second surface, the second metal terminal being made of the same kind of metal as the first metal terminal; and a sealing portion filled between the first surface of the first substrate and the second surface of the second substrate, the first metal terminal and the second metal terminal being directly bonded with each other, the first protruding resin portion and the second protruding resin portion being directly bonded with each other, each of the first protruding resin portion and the second protruding resin portion being made of a resin material that does not include fillers, and the sealing portion being made of a resin material including fillers. 1. A packaging structure comprising:a first substrate including a first metal terminal and a first protruding resin portion formed at a first surface of the first substrate;a second substrate including a second metal terminal and a second protruding resin portion formed at a second surface of the second substrate, the second metal terminal being made of the same kind of metal as the first metal terminal,the second substrate being provided on the first substrate such that the second surface of the second substrate faces the first surface of the first substrate; anda sealing portion filled between the first surface of the first substrate and the second surface of the second substrate,the first metal terminal and the second metal terminal being directly bonded with each other,the first protruding resin portion and the second protruding resin portion being directly bonded with each other,each of the first protruding resin portion and the second protruding resin portion being made of a resin material that does not include fillers, andthe sealing portion being made of a resin ...

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Номер записи: 68

04-02-2016 дата публикации

Bump structural designs to minimize package defects

Номер: US20160035687A1

Автор: Cheng-Lin Huang, Jing-Cheng Lin

Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method of forming a chip package includes providing a chip with a plurality of first bumps, wherein the plurality of first bumps has a first height. The method further includes providing a substrate with a plurality of second bumps, wherein the plurality of second bumps has a second height. The method further includes bonding the plurality of first bumps to the plurality of second bumps to form a first bump structure of the chip package, wherein the first bump structure has a standoff, wherein a ratio of a sum of the first height and the second height to the standoff is equal to or greater than about 0.6 and less than 1.

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Номер записи: 69

01-02-2018 дата публикации

Integrated circuit chip and display device including the same

Номер: US20180033755A1

Автор: Jeong Do Yang, Jeong Ho Hwang, Jung Yun Jo, Sang Hyeon SONG, Seung-Hwa HA

Принадлежит: Samsung Display Co Ltd

An exemplary embodiment provides a driving circuit chip including: a substrate; a terminal electrode disposed on the substrate; and an electrode pad disposed on the terminal electrode, wherein the electrode pad includes: a bump structure protruded from the substrate to include a short side and a long side; and a bump electrode disposed on the bump structure and connected with the terminal electrode around a short edge portion of the bump structure, wherein the bump electrode is disposed to not cover at least a part of a long edge portion of the bump structure.

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Номер записи: 70

01-02-2018 дата публикации

METHOD FOR FORMING BUMP STRUCTURE

Номер: US20180033756A1

Автор: Chen Chun-Jen, Cheng Hsi-Kuei, LAI Yi-Jen, LEE Li-Guo, LIU Yi-Chen, LIU Yung-Sheng

Принадлежит:

Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a metal pad over a first substrate and forming a polymer layer over the metal pad. The method for forming a semiconductor structure further includes forming a seed layer over the metal pad and extending over the polymer layer and forming a conductive pillar over the seed layer. The method for forming a semiconductor structure further includes wet etching the seed layer using an etchant comprising H2O2. In addition, the step of wet etching the seed layer is configured to form an extending portion having a slope sidewall. 1. A method for forming a semiconductor structure , comprising:forming a metal pad over a first substrate;forming a polymer layer over the metal pad;forming a seed layer over the metal pad and extending over the polymer layer;forming a conductive pillar over the seed layer; and{'sub': 2', '2, 'wet etching the seed layer using an etchant comprising HO, wherein the step of wet etching the seed layer is configured to form an extending portion having a slope sidewall.'}2. The method for forming a semiconductor structure as claimed in claim 1 , wherein the slope sidewall extends from a bottommost of a sidewall of the conductive pillar to a top surface of the polymer layer.3. The method for forming a semiconductor structure as claimed in claim 2 , wherein an inclination of the slope sidewall of the extending portion of the seed layer is different from an inclination of the sidewall of the conductive pillar.4. The method for forming a semiconductor structure as claimed in claim 3 , wherein an angle between the slope sidewall and a bottom surface of the seed layer is in a range from about 20° to about 80°.5. The method for forming a semiconductor structure as claimed in claim 1 , wherein the conductive pillar is directly formed on the seed layer.6. The method for forming a semiconductor structure as claimed in claim 1 , further ...

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Номер записи: 71

30-01-2020 дата публикации

SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME

Номер: US20200035631A1

Автор: CHANG Shih-Cheng

Принадлежит:

The present disclosure provides a semiconductor package, including a substrate, an active region in the substrate, an interconnecting layer over the active region, a conductive pad over the interconnecting layer, surrounded by a dielectric layer. At least two discrete regions of the conductive pad are free from coverage of the dielectric layer. A method of manufacturing the semiconductor package is also disclosed. 1. A semiconductor package , comprising:a substrate;an active region in the substrate;an interconnecting layer over the active region;a conductive pad over the interconnecting layer, surrounded by a dielectric layer, wherein at least two discrete regions of the conductive pad are free from coverage of the dielectric layer: anda conductive bump over the conductive pad and the dielectric layer, the conductive bump comprises at least two protrusions separated by the dielectric layer.2. The semiconductor package of claim 1 , wherein the dielectric layer comprises:a passivation layer having a portion at a same level with the conductive pad; anda polymer layer stacking over the passivation layer.3. The semiconductor package of claim 1 , wherein the conductive bump being in contact with the conductive pad at the at least two discrete regions.4. The semiconductor package of claim 1 , further comprising:an under bump metallurgy (UBM) layer over the conductive pad and the dielectric layer, the UBM layer being in contact with the conductive pad at the at least two discrete regions, wherein the protrusions of the conductive bump are in contact with the UBM layer over the at least two discrete regions of the conductive pad.5. The semiconductor package of claim 1 , wherein the at least two discrete regions comprise different sizes from a top view perspective.6. The semiconductor package of claim 3 , further comprising:a solder bump at an opposite end of the conductive bump contacting the conductive pad; anda package substrate connected to the solder bump.7. The ...

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Номер записи: 72

09-02-2017 дата публикации

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

Номер: US20170040267A1

Автор: YAJlMA Akira

Принадлежит:

Object is to prevent a coupling failure between a rewiring and a coupling member for coupling to outside. A passivation film and a first polyimide film are formed so as to cover a wiring layer. A first opening portion is formed in the first polyimide film. A rewiring is formed on the first polyimide film so as to be coupled to the wiring layer via the first opening portion. A second polyimide film that covers the rewiring and has a second opening portion communicated with the rewiring is formed. A palladium film is formed as a barrier film by sputtering on a portion of the surface of the rewiring at which the second opening portion exists. A solder ball is coupled to the palladium film. 1. A method of manufacturing a semiconductor device , comprising:defining an element formation region and a scribe region in a semiconductor substrate;forming a semiconductor element in the element formation region;forming a plurality of wiring layers above the semiconductor element;forming, with one of uppermost wiring layers of the wiring layers as a first pad electrode, a first insulating film so as to cover the first pad electrode therewith;forming, in the first insulating film, a first opening portion from which the first pad electrode is exposed;forming a rewiring over the first insulating film so as to couple the rewiring to the first pad electrode via the first opening portion;forming a second insulating film that covers the rewiring and has a second opening portion communicated with the rewiring;forming a barrier film over at least a portion of the surface of the rewiring at which the second opening portion is present;after formation of the barrier film, testing the semiconductor element while heat treating; andcoupling, to the barrier film, a coupling member for electrical coupling to the outside, 'forming at least a film having any one of materials selected from the group comprised of palladium (Pd), ruthenium (Ru), rhodium (Rh), platinum (Pt), and iridium (Ir),', 'wherein ...

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Номер записи: 73

08-02-2018 дата публикации

Hollow Metal Pillar Packaging Scheme

Номер: US20180040599A1

Автор: Chen Hsien-Wei, Huang Chang-Pin, LAI YU-CHIA, Shao Tung-Liang, Tu Hsien-Ming, Yang Ching-Jung

Принадлежит:

An integrated circuit includes a bottom substrate, a metal layer disposed over the bottom substrate and a hollow metal pillar disposed on the metal layer. The metal layer and the hollow metal pillar are electrically connected. 1. A structure comprising:a substrate;a redistribution layer over the substrate;a conductive pillar over the redistribution layer, the conductive pillar having an annular shape in a plan view; andan insulating material extending along an inner sidewall and an outer sidewall of the conductive pillar.2. The structure of claim 1 , wherein a topmost surface of the conductive pillar is above a topmost surface of the insulating material.3. The structure of claim 1 , further comprising a solder layer over the conductive pillar.4. The structure of claim 1 , wherein the annular shape comprises one or more holes.5. The structure of claim 1 , wherein the annular shape comprises two holes and a divider separating the two holes.6. The structure of claim 1 , wherein an inner diameter of the annular shape is between about 140 μm and about 160 μm.7. The structure of claim 1 , wherein a height of the annular shape is between about 80 μm and about 90 μm.8. The structure of claim 1 , wherein a distance between the inner sidewall and the outer sidewall of the conductive pillar is between about 40 μm and about 50 μm.9. A structure comprising:a substrate;a redistribution layer over the substrate;a molding compound over the redistribution layer; anda conductive pillar in the molding compound, the conductive pillar surrounding a portion of the molding compound, the conductive pillar being electrically coupled to the redistribution layer.10. The structure of claim 9 , further comprising a contact pad between the substrate and the redistribution layer claim 9 , the redistribution layer electrically coupling the contact pad to the conductive pillar.11. The structure of claim 10 , further comprising a passivation layer between the contact pad and the redistribution layer ...

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Номер записи: 74

24-02-2022 дата публикации

Semiconductor structure and method of manufacturing thereof

Номер: US20220059435A1

Автор: Chiang-Lin Shih, Ching-Hung Chang, Hsih-Yang Chiu, Pei-Jhen WU

Принадлежит: Nanya Technology Corp

A semiconductor structure and a method of manufacturing thereof are provided. The semiconductor includes a semiconductor integrated circuit device and a redistribution layer structure. The semiconductor integrated circuit device has a top surface and an electrode on the top surface. The redistribution layer structure is formed on the top surface. The redistribution layer structure includes an oxide layer, a nitride layer, a dielectric layer, a groove and a through via. The oxide layer and the nitride layer are formed on the top surface. The dielectric layer is formed on the nitride layer. The groove is formed at a topside of the dielectric layer and overlaps the electrode. The through via is formed at a bottom of the groove and extends within the electrode through the dielectric layer, the nitride layer and the oxide layer. The through via and the groove are filled with a conductive material.

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Номер записи: 75

06-02-2020 дата публикации

INTEGRATED CIRCUIT COMPONENT AND PACKAGE STRUCTURE HAVING THE SAME

Номер: US20200043816A1

Автор: Chen Hsien-Wei, Chen Ming-Fa, LIU Tzuan-Horng, Yang Chao-Hsiang

Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads. 1. An integrated circuit component , comprising:a semiconductor substrate having an active surface;conductive pads, located on the active surface of the semiconductor substrate, electrically connected to the semiconductor substrate, and each having a contact region and a testing region, wherein in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region;a passivation layer, located on the semiconductor substrate, wherein the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer; andconductive vias, respectively located on the contact regions of the conductive pads.2. The integrated circuit component of claim 1 , further comprising:a post-passivation layer, located on the semiconductor substrate, wherein the testing regions of the conductive pads exposed by the passivation layer are covered by the post-passivation layer, and the contact regions of the conductive pads exposed by the passivation layer are exposed ...

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Номер записи: 76

06-02-2020 дата публикации

PRINTED REPASSIVATION FOR WAFER CHIP SCALE PACKAGING

Номер: US20200043878A1

Автор: Komatsu Daiki, Nguyen Hau, Nguyen Luu Thanh, Poddar Anindya, Shibuya Makoto, Yan Yi

Принадлежит: TEXAS INSTRUMENTS INCORPORATED

Described examples provide integrated circuits and methods, including forming a conductive seed layer at least partially above a conductive feature of a wafer, forming a conductive structure on at least a portion of the conductive seed layer, performing a printing process that forms a polymer material on a side of the wafer proximate a side of the conductive structure, curing the deposited polymer material, and attaching a solder ball structure to a side of the conductive structure. 1. A method , comprising:forming a conductive seed layer at least partially above a conductive feature of a wafer;forming a conductive structure on at least a portion of the conductive seed layer;performing a printing process that forms a polymer material on a side of the wafer proximate a side of the conductive structure;curing the deposited polymer material; andattaching a solder ball structure to a side of the conductive structure.2. The method of claim 1 , wherein performing the printing process includes performing multiple printing passes to deposit multiple layers of the polymer material proximate the side of the conductive structure.3. The method of claim 2 , wherein curing the deposited polymer material includes:heating the wafer while performing the printing process to at least partially cure the polymer material.4. The method of claim 3 , wherein curing the deposited polymer material further includes:after performing the printing process, performing a final curing process that thermally cures the polymer material.5. The method of claim 2 , wherein curing the deposited polymer material includes:exposing the polymer material to ultraviolet light while performing the printing process to at least partially cure the polymer material.6. The method of claim 5 , wherein curing the deposited polymer material further includes:after performing the printing process, performing a final curing process that UV cures the polymer material.7. The method of claim 1 , further comprising:after ...

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Номер записи: 77

06-02-2020 дата публикации

Fan-out sensor package and camera module

Номер: US20200043970A1

Автор: Byoung Chan Kim, Yong Ho Baek

Принадлежит: SAMSUNG ELECTRONICS CO LTD

The fan-out sensor package includes: a core member having a through-hole; an integrated circuit (IC) for a sensor disposed in the through-hole and having a first surface having a sensor region and first connection pads disposed thereon, a second surface opposing the first surface and having second connection pads disposed thereon, and through-silicon vias (TSVs) penetrating between the first and second surfaces and electrically connecting the first and second connection pads to each other; an encapsulant covering the core member and the second surface of the IC for a sensor and filling at least portions of the through-hole; a redistribution layer disposed on the encapsulant; and vias penetrating through at least portions of the encapsulant and electrically connecting the redistribution layer and the second connection pads to each other.

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Номер записи: 78

15-02-2018 дата публикации

METHOD OF FORMING A SEMICONDUCTOR DEVICE INCLUDING STRAIN REDUCED STRUCTURE

Номер: US20180047686A1

Автор: Chen Hsien-Wei, CHEN Ying-Ju, Chen Yu-Feng, WANG Tsung-Ding, YU Tsung-Yuan

Принадлежит:

A method of forming a device includes forming conductive pads on a semiconductor die. The conductive pads include a first conductive pad having a first width on a first region of the semiconductor die; and a second conductive pad having a second width on a second region of the semiconductor die. The method includes forming bonding pads on a substrate. The bonding pads include a third bonding pad having a third width on a third region of the substrate; and a fourth bonding pad having a fourth width on a fourth region of the substrate. The method further includes forming a conductive material coupled between the first conductive pad and the third bonding pad, and between the second conductive pad and the fourth bonding pad. A ratio A of the first width to the third width is different from a ratio B of the second width to the fourth width. 1. A method of forming a device , the method comprising: a first conductive pad having a first width on a first region of the semiconductor die; and', 'a second conductive pad having a second width on a second region of the semiconductor die;, 'forming conductive pads on a semiconductor die, the conductive pads including'} a third bonding pad having a third width on a third region of the substrate; and', 'a fourth bonding pad having a fourth width on a fourth region of the substrate; and, 'forming bonding pads on a substrate, the bonding pads including'}forming a conductive material coupled between the first conductive pad and the third bonding pad, and between the second conductive pad and the fourth bonding pad, wherein a ratio A of the first width of the first conductive pad to the third width of the third bonding pad is different from a ratio B of the second width of the second conductive pad to the fourth width of the fourth bonding pad.2. The method of claim 1 , wherein the ratio B is between 1 and about 1.3 claim 1 , and the ratio B is greater than the ratio A.3. The method of claim 1 , wherein the conductive material ...

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Номер записи: 79

15-02-2018 дата публикации

Elongated Bump Structures in Package Structure

Номер: US20180047690A1

Автор: Chen Chen-Shien, Chuang Chita, Chuang Yao-Chun, Tseng Ming Hung

Принадлежит:

A package structure includes a chip attached to a substrate. The chip includes a bump structure including a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar. The substrate includes a pad region and a mask layer overlying the pad region, wherein the mask layer has an opening exposing a portion of the pad region. The chip is attached to the substrate to form an interconnection between the conductive pillar and the pad region. The opening has a first dimension (d) measured along the long axis and a second dimension (d) measured along the short axis. In an embodiment, L is greater than d, and W is less than d 1. A method of forming a package structure , comprising:placing a conductive structure over an opening through a masking layer, the opening exposing a conductive element; andreflowing a portion of the conductive structure to bond the conductive structure to the conductive element, wherein after the reflowing the portion of the conductive structure the conductive structure extends in a first direction further than the opening and extends in a second direction less than the opening, the first direction being perpendicular to the second direction.2. The method of claim 1 , wherein the conductive structure comprises a first length along a first axis and a first width along a second axis perpendicular to the first axis claim 1 , the first length being longer than the first width.3. The method of claim 2 , wherein the first length is between about 70 μm and about 150 μm.4. The method of claim 3 , wherein the first width is between about 40 and about 100 μm.5. The method of claim 2 , wherein a ratio between the first length and the first width is between about 1.75 and about 1.5.6. The method of claim 1 , further comprising a molding compound located adjacent to the conductive structure.7. The method of claim 1 , wherein there is no molding compound adjacent to ...

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Номер записи: 80

15-02-2018 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20180047691A1

Автор: Utsunomiya Hiroyuki

Принадлежит:

A flip-chip mounting technique with high reliability is provided in flip-chip mounting using a Cu pillar. In a semiconductor device to be coupled to a mounting board via a Cu pillar, the Cu pillar is caused to have a laminated structure including a pillar layer, a barrier layer, and a bump in this order from below, and the bump is formed to be smaller than the barrier layer. 1. A manufacturing method of a semiconductor device , comprising the steps of:(a) applying a resist film over a terminal pad formed over a main surface of a semiconductor substrate;(b) forming an opening in the resist film for exposing the terminal pad in the bottom thereof;(c) forming a Cu film, an Ni film, and an SnAg film in the opening in this order from below;(d) removing the resist film; and(e) etching an outer peripheries of the SnAg film.2. The manufacturing method of a semiconductor device according to claim 1 ,wherein, in the step (e), the etching is performed by using dilute hydrofluoric acid.3. The manufacturing method of a semiconductor device according to claim 1 ,wherein, in the step (b), the forming the opening is performed by using photolithography.4. The manufacturing method of a semiconductor device according to claim 1 ,wherein, in the step (c), the Cu film, the Ni film, and the SnAg film are formed by electrolytic plating.5. The manufacturing method of a semiconductor device according to claim 1 ,wherein, in the step (d), the resist film is removed by ashing.6. The manufacturing method of a semiconductor device according to claim 1 ,wherein, in the step (e), the outer peripheries of the SnAg film is wet etched.7. A manufacturing method of a semiconductor device claim 1 , comprising the steps of:(a) applying a first resist film over a terminal pad formed over a main surface of a semiconductor substrate;(b) forming a first opening in the first resist film for exposing the terminal pad in the bottom thereof;(c) forming a Cu film and an Ni film in this order from below;(d) ...

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Номер записи: 81

15-02-2018 дата публикации

Semiconductor integrated circuit device

Номер: US20180047696A1

Автор: Jun Yamada, Takafumi Betsui

Принадлежит: Renesas Electronics Corp

A semiconductor integrated circuit chip, in which multi-core processors are integrated, is usually mounted over an organic wiring board by FC bonding to form a BGA package by being integrated with the substrate. In such a structure, power consumption is increased, and hence the power supplied only from a peripheral portion of the chip is insufficient, so that a power supply pad is also provided in the chip central portion. However, because of an increase in the wiring associated with the integration of a plurality of CPU cores, etc., there occurs a portion between the peripheral portion and the central portion of the chip, where a power supply pad cannot be arranged. According to the outline of the present application, in a semiconductor integrated circuit device such as a BGA, etc., in which a semiconductor chip is mounted over an interposer, such as a multilayer organic wiring board, in a face-up manner, a first group of metal through electrodes, which are provided in the semiconductor chip to supply a power supply potential to a core circuit, etc., and a first metal land over the interposer are interconnected by a first conductive adhesive member film.

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Номер записи: 82

26-02-2015 дата публикации

Semiconductor device with pads of enhanced moisture blocking ability

Номер: US20150054129A1

Автор: Kaoru Saigoh, Kouichi Nagai

Принадлежит: Fujitsu Semiconductor Ltd

A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed on a semiconductor substrate; lamination of insulator covering the circuit portion, including a passivation film as an uppermost layer having openings; ferro-electric capacitors formed in the lamination of insulator; wiring structure formed in the lamination of insulator and connected to the semiconductor elements and the ferro-electric capacitors; pad electrodes connected to the wiring structure, formed in the lamination of insulator and exposed in the openings of the passivation film; a conductive pad protection film, including a Pd film, covering each pad electrode via the opening of the passivation film, and extending on the passivation film; and stud bump or bonding wire connected to the pad electrode via the conductive pad protection film.

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Номер записи: 83

26-02-2015 дата публикации

Multilayer pillar for reduced stress interconnect and method of making same

Номер: US20150054152A1

Автор: Brian R. Sundlof, Kamalesh K. Srivastava, Krystyna W. Semkow, Virendra R. Jadhav

Принадлежит: International Business Machines Corp

A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions

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Номер записи: 84

26-02-2015 дата публикации

Electronic device

Номер: US20150054178A1

Автор: Katsumi Ishii, Masashi Yamaura

Принадлежит: Murata Manufacturing Co Ltd

An electronic device includes a surface-mounted component and a mounting component on which the surface-mounted component is mounted, the surface-mounted component includes a first bump and a second bump, a cross-sectional area of which in an in-plane direction of a surface facing the mounting component is larger than that of the first bump, on the surface facing the mounting component, the mounting component includes a first pad that is soldered to the first bump and a second pad soldered to the second bump on the surface facing the surface-mounted component, and a ratio of an area of the second pad to the cross-sectional area of the second bump is larger than a ratio of an area of the first pad to the cross-sectional area of the first bump.

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Номер записи: 85

03-03-2022 дата публикации

ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF

Номер: US20220068867A1

Автор: Kao Feng, Wang Lung-Yuan

Принадлежит: SILICONWARE PRECISION INDUSTRIES CO., LTD.

An electronic package is provided, which stacks an electronic structure as an integrated voltage regulator on an electronic component to facilitate close-range cooperation with the electronic component for electrical transmission.

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Номер записи: 86

14-02-2019 дата публикации

METHODS FOR FORMING INTERCONNECT ASSEMBLIES WITH PROBED BOND PADS

Номер: US20190051569A1

Автор: England Luke G., Fay Owen R., Gandhi Jaspreet S., Kirby Kyle K.

Принадлежит:

An interconnect assembly includes a bond pad and an interconnect structure configured to electrically couple an electronic structure to the bond pad. The interconnect structure physically contacts areas of the bond pad that are located outside of a probe contact area that may have been damaged during testing. Insulating material covers the probe contact area and defines openings spaced apart from the probe contact area. The interconnect structure extends through the openings to contact the bond pad. 1. An assembly , comprising:a semiconductor structure including a probed pad with a probe mark;a microelectronic structure including circuitry; andan interconnect structure coupled to the microelectronic structure and physically contacting the probed pad such that the circuitry of the microelectronic structure is electrically coupled to the semiconductor structure, wherein the interconnect structure physically contacts only one or more areas of the probed pad spaced apart from the probe mark.2. The assembly of claim 1 , wherein the semiconductor structure further comprises:an insulating material that covers at least a portion of the probe mark, the insulating material defines a first opening and a second opening, and a first portion extending through the first opening to contact a first area of the one or more areas, and', 'a second portion extending through the second opening to contact a second area of the of the one or more areas., 'wherein the interconnect structure includes'}3. The assembly of claim 1 , wherein the probe mark is directly underneath the interconnect structure.4. The assembly of claim 1 , further comprising an insulating material covering the probe mark.5. The assembly of claim 1 , wherein the interconnect structure includes a plug portion physically contacting the probed pad.6. The assembly of claim 1 , wherein the microelectronic structure includes at least one of a microelectromechanical system claim 1 , a memory claim 1 , or an LED structure.7. ...

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Номер записи: 87

25-02-2021 дата публикации

SEMICONDUCTOR PACKAGE

Номер: US20210057366A1

Автор: CHANG Shih-Cheng

Принадлежит:

The present disclosure provides a semiconductor package including a semiconductor chip and a package substrate. The semiconductor chip includes a substrate, a plurality of conductive pads in the substrate, and a plurality of conductive bumps. Each of the conductive bumps is over corresponding conductive pad. At least one of the conductive bumps proximity to an edge of the semiconductor chip is in contact with at least two discrete regions of the corresponding conductive pad. The package substrate has a concave surface facing the semiconductor chip and joining the semiconductor chip through the plurality of conductive bumps. 1. A semiconductor package , comprising: a substrate;', 'a plurality of conductive pads in the substrate; and', 'a plurality of conductive bumps, each over corresponding conductive pad, at least one of the conductive bumps proximity to an edge of the semiconductor chip being in contact with at least two discrete regions of the corresponding conductive pad; and, 'a semiconductor chip, comprisinga package substrate having a concave surface facing the semiconductor chip and joining the semiconductor chip through the plurality of conductive bumps.2. The semiconductor package of claim 1 , wherein one of the at least two discrete regions closer to a center of the semiconductor chip is larger than another one of the at least two discrete regions closer to the edge of the semiconductor chip.3. The semiconductor package of claim 1 , wherein the conductive pads having at least two discrete regions are ellipses from top view perspective.4. The semiconductor package of claim 3 , wherein the two discrete regions are on a major axis of each of the conductive pads from top view perspective.5. The semiconductor package of claim 1 , further comprising:an active region in the substrate; andan interconnecting layer over the active region and in contact with a bottom of each of the conductive pads.6. The semiconductor package of claim 5 , further comprising a ...

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Номер записи: 88

05-03-2015 дата публикации

Stack packages and methods of manufacturing the same

Номер: US20150061120A1

Автор: Jong Hoon Kim, Seung Taek Yang, Song Na, Tac Keun OH

Принадлежит: SK hynix Inc

Embodiments of a stack package may include an upper chip on a lower chip, a backside passivation layer covering the backside surface of the lower chip and having a thickness which is substantially equal to a height of the protrusion portion of a lower through via electrode, a backside bump substantially contacting the protrusion portion, and a front side bump electrically connected to a chip contact portion of the upper chip and physically and electrically connected to the backside bump. The backside passivation layer may include a first insulation layer provided over a sidewall of the protrusion portion and the backside surface of the lower chip. Embodiments of fabrication methods are also disclosed.

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Номер записи: 89

05-03-2015 дата публикации

Semiconductor Device and Method for Forming Openings and Trenches in Insulating Layer by First LDA and Second LDA for RDL Formation

Номер: US20150061123A1

Автор: KANG Chen, Pandi C. Marimuthu, Yaojian Lin

Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a semiconductor die with an encapsulant deposited over the semiconductor die. A first insulating layer having high tensile strength and elongation is formed over the semiconductor die and encapsulant. A first portion of the first insulating layer is removed by a first laser direct ablation to form a plurality of openings in the first insulating layer. The openings extend partially through the first insulating layer or into the encapsulant. A second portion of the first insulating layer is removed by a second laser direct ablation to form a plurality of trenches in the first insulating layer. A conductive layer is formed in the openings and trenches of the first insulating layer. A second insulating layer is formed over the conductive layer. A portion of the second insulating layer is removed by a third laser direct ablation. Bumps are formed over the conductive layer.

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Номер записи: 90

21-02-2019 дата публикации

Polymer Layers Embedded with Metal Pads for Heat Dissipation

Номер: US20190057946A1

Автор: CHUANG HAO-HSIANG, LIANG Shih-Wei, Tsai Hao-Yi, WANG Chuei-Tang, Wu Kai-Chiang, Yang Ching-Feng, Yu Chen-Hua

Принадлежит:

An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad. 1. An integrated circuit structure comprising:a metal pad;a passivation layer comprising a portion over the metal pad;a first polymer layer comprising a portion over the passivation layer;a dummy metal pad in the first polymer layer, wherein the dummy metal pad is electrically floating;a second polymer layer over the first polymer layer and the dummy metal pad; anda first Under-Bump-Metallurgy (UBM) extending into the second polymer layer to electrically couple to the dummy metal pad.2. The integrated circuit structure of claim 1 , wherein a top surface and a bottom surface of the dummy metal pad are coplanar with a top surface and a bottom surface claim 1 , respectively claim 1 , of the first polymer layer.3. The integrated circuit structure of further comprising:a package component comprising a surface metallic feature; anda solder region bonding the surface metallic feature in the package component to the first UBM, wherein the dummy metal pad, the solder region, and the surface metallic feature in combination are electrically floating.4. The integrated circuit structure of further comprising:a third polymer layer between the first polymer layer and the second polymer layer; anda Post-Passivation Interconnect (PPI) extending into to the third polymer layer, wherein the PPI electrically couples the dummy metal pad to the first UBM.5. The integrated circuit structure of further comprising: ...

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Номер записи: 91

01-03-2018 дата публикации

Semiconductor chip, display panel, and electronic device

Номер: US20180061748A1

Автор: Byoung Yong Kim, Jeong Ho Hwang

Принадлежит: Samsung Display Co Ltd

A semiconductor chip, a display device or an electronic device includes a substrate, one or more conductive pads disposed on the substrate, and one or more bumps electrically connected to the one or more conductive pads, in which the one or more bumps includes a metal core, a polymer layer disposed over a surface of the metal core, and a conductive coating layer disposed over a surface of the polymer layer and electrically connected to the one or more conductive pads.

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Номер записи: 92

20-02-2020 дата публикации

METHOD OF USING A SACRIFICIAL CONDUCTIVE STACK TO PREVENT CORROSION

Номер: US20200058547A1

Автор: Jain Manoj K.

Принадлежит:

A method of fabricating an integrated circuit (IC) chip is disclosed. The method starts with opening a window on a first surface of the IC chip through a passivation overcoat to expose the copper metallization layer. The window has sidewalls and a bottom that is adjacent the copper metallization layer. The method continues with depositing a barrier conductive stack on the passivation overcoat and exposed portions of the copper metallization layer, then depositing a sacrificial conductive stack on the barrier conductive stack. The sacrificial conductive stack has a thickness between 50 Å and 500 Å. The first surface of the semiconductor chip is polished to remove the sacrificial conductive stack and the barrier conductive stack from the surface of the passivation overcoat. 1. A method of fabricating an integrated circuit (IC) chip , the method comprising:etching an opening through a passivation overcoat to a copper metallization layer;depositing a barrier conductive stack on the passivation overcoat and in the opening on the copper metallization layer;depositing a sacrificial conductive stack on the barrier conductive stack; andpolishing to remove the sacrificial conductive stack and the barrier conductive stack from over the passivation overcoat.2. The method of claim 1 , wherein the barrier conductive stack comprises a first layer of tantalum nitride.3. The method of claim 2 , wherein the barrier conductive stack further comprises a layer of nickel.4. The method of claim 3 , wherein the barrier conductive stack further comprises a second layer of tantalum nitride.5. The method of claim 2 , wherein the barrier conductive stack further comprises a layer of tungsten.6. The method of claim 1 , wherein the sacrificial conductive stack comprises any of palladium claim 1 , platinum claim 1 , gold claim 1 , ruthenium or any combination thereof.7. The method of claim 1 , further comprising performing an etching process to remove the sacrificial conductive stack from at ...

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Номер записи: 93

01-03-2018 дата публикации

METHOD OF FORMING A SOLDER BUMP STRUCTURE

Номер: US20180061796A1

Автор: Aoki Toyohiro, Hisada Takashi, Nakamura Eiji I.

Принадлежит:

A method of the present invention includes preparing a substrate having a surface on which a electrode pad is formed, forming a resist layer on the substrate, the resist layer having an opening on the electrode pad, filling conductive paste in the opening of the resist layer; sintering the conductive paste in the opening to form a conductive layer which covers a side wall of the resist layer and a surface of the electrode pad in the opening, a space on the conductive layer leading to the upper end of the opening being formed, filling solder in the space on the conductive layer and removing the resist layer. 1. A solder bump structure comprising:a metal pillar formed on an electrode pad, the metal pillar having a cone-shaped surface, a substantially perpendicular outside wall, and a conformal cross-section; anda solder formed on the surface of the metal pillar, the solder having a convex top surface.2. The solder bump structure according to claim 1 , wherein the solder is in contact with the whole of the cone-shaped surface of the metal pillar.3. The solder bump structure according to claim 1 , wherein the metal pillar comprises at least one of copper claim 1 , nickel claim 1 , silver or gold.4. The solder bump structure according to claim 1 , wherein a thickness of a central portion of the metal pillar is in a range of ⅕ to ⅔ of a length from the surface of an electrode pad to the top surface of the solder.5. The solder bump structure according to claim 4 , wherein the electrode pad comprises aluminum.6. The solder bump structure according to claim 1 , wherein a thickness of a central portion of the metal pillar is in a range of 1 to 50 micrometers.7. A solder bump structure comprising:a metal pillar formed on an electrode pad and in an opening of a resist layer, the metal pillar having a cone-shaped surface, a substantially perpendicular outside wall connected to a side wall in the opening of the resist layer, and a conformal cross-section; anda solder formed on ...

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Номер записи: 94

01-03-2018 дата публикации

METHOD OF FORMING A SOLDER BUMP STRUCTURE

Номер: US20180061797A1

Автор: Aoki Toyohiro, Hisada Takashi, Nakamura Eiji I.

Принадлежит:

A method of the present invention includes preparing a substrate having a surface on which a electrode pad is formed, forming a resist layer on the substrate, the resist layer having an opening on the electrode pad, filling conductive paste in the opening of the resist layer; sintering the conductive paste in the opening to form a conductive layer which covers a side wall of the resist layer and a surface of the electrode pad in the opening, a space on the conductive layer leading to the upper end of the opening being formed, filling solder in the space on the conductive layer and removing the resist layer. 1. A method of forming a solder bump structure , comprising the steps of:forming a resist layer on a substrate on which an electrode pad is formed, the resist layer having an opening on the electrode pad;filling conductive paste in the opening of the resist layer;sintering the conductive paste in the opening to form a conductive layer which covers a side wall of the resist layer and a surface of the electrode pad in the opening, a space on the conductive layer leading to an upper end of the opening being formed; andfilling solder in the space on the conductive layer.2. The method according to claim 1 , wherein the step of filling conductive paste includes a step of screen-printing conductive paste containing metal nanoparticles in a solvent on the substrate.3. The method according to claim 1 , wherein the step of filling conductive paste includes a step of injecting conductive paste containing metal nanoparticles in a solvent into the opening of the resist layer.4. The method according to claim 1 , wherein the conductive paste includes at least one of copper claim 1 , nickel claim 1 , silver or gold.5. The method according to claim 1 , wherein the conductive layer has a cone-shaped surface.6. The method according to claim 1 , wherein a cross-section of the conductive layer has a conformal shape.7. The method according to claim 1 , wherein a thickness of a central ...

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Номер записи: 95

02-03-2017 дата публикации

SEMICONDUCTOR PACKAGING AND MANUFACTURING METHOD THEREOF

Номер: US20170062369A1

Автор: LIANG Shih-Wei, Liu Ming-Kai, Shih Chao-Wen, Wang Yen-Ping, Wu Kai-Chiang, Yang Ching-Feng

Принадлежит:

The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI. 1. A method of manufacturing a semiconductor package , comprising:patterning a metal derivative in a second region of a post-passivation interconnect (PPI);forming a flux layer in a first region of the PPI, wherein the first region is surrounded by the second region;dropping a solder ball on the flux layer; andforming electrical connection between the solder ball and the PPI.2. The method of manufacturing a semiconductor package in claim 1 , wherein the to patterning the metal derivative in the second region of the PPI further comprising forming a mask layer over the PPI.3. The method of manufacturing a semiconductor package in claim 2 , wherein the forming the mask layer over the PPI comprises forming a mask layer on the PPI.4. The method of manufacturing a semiconductor package in claim 2 , wherein the forming the mask layer over the PPI comprises positioning a first stencil plate over the PPI.5. The method of manufacturing a semiconductor package in claim 1 , wherein the patterning the metal derivative in the second region of the PPI comprises an oxygen plasma ...

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Номер записи: 96

17-03-2022 дата публикации

Semiconductor device with slanted conductive layers and method for fabricating the same

Номер: US20220084967A1

Автор: Kuo-Hui Su

Принадлежит: Nanya Technology Corp

The present application discloses a semiconductor device with slanted conductive layers and a method for fabricating the semiconductor device with the slanted conductive layers. The semiconductor device includes a substrate, a first insulating layer positioned above the substrate, first slanted conductive layers positioned in the first insulating layer, and a top conductive layer positioned covering the first slanted conductive layers.

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Номер записи: 97

28-02-2019 дата публикации

Multi-Pin-Wafer-Level-Chip-Scale-Packaging Solution for High Power Semiconductor Devices

Номер: US20190067229A1

Автор: Aiyandra Rajesh Subraya, Mohammed Habeeb Mohiuddin

Принадлежит:

A multi-pin wafer level chip scale package is achieved. One or more solder pillars and one or more solder blocks are formed on a silicon wafer wherein the one or more solder pillars and the one or more solder blocks all have a top surface in a same horizontal plane. A pillar metal layer underlies the one or more solder pillars and electrically contacts the one or more solder pillars with the silicon wafer through an opening in a polymer layer over a passivation layer. A block metal layer underlies the one or more solder blocks and electrically contacts the one or more solder pillars with the silicon wafer through a plurality of via openings through the polymer layer over the passivation layer wherein the block metal layer is thicker than the pillar metal layer. 1. A multi-pin wafer level chip scale package comprising:one or more solder pillars and one or more solder blocks on a silicon wafer wherein said one or more solder pillars and said one or more solder blocks all have a top surface in a same horizontal plane;a pillar metal layer underlying said one or more solder pillars and electrically connecting said one or more solder pillars with said silicon wafer through an opening in a polymer layer over a passivation layer on said silicon wafer; anda block metal layer underlying said one or more solder blocks and electrically connecting said one or more solder blocks with said silicon wafer through a plurality of via openings through said polymer layer over said passivation layer on said silicon wafer wherein said block metal layer is thicker than said pillar metal layer.2. The package according to wherein said one or more solder blocks connect to devices having high current of greater than 2 A.3. The package according to wherein said one or more solder pillars connect to devices having low current less than or equal to 2 A.4. The package according to wherein said polymer layer comprises a first and a second polymer layer and wherein said pillar metal layer comprises: ...

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Номер записи: 98

08-03-2018 дата публикации

SEMICONDUCTOR DEVICE STRUCTURE AND MANUFACTURING METHOD

Номер: US20180068967A1

Автор: Chen Chun-Jen, Cheng Hsi-Kuei, LAI Yi-Jen, LEE Li-Guo, LIU Yi-Chen, LIU Yung-Sheng

Принадлежит:

A semiconductor device structure and a manufacturing method are provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive trace over the dielectric layer. The semiconductor device structure further includes a conductive feature over the conductive trace, and a width of the conductive feature is substantially equal to or larger than a maximum width of the conductive trace. In addition, the semiconductor device structure includes a conductive bump over the conductive feature. 1. A structure , comprising:a substrate;a conductive trace disposed over the substrate, the conductive trace including a first segment and a second segment that each extend in a first direction, wherein the first segment and the second segment have substantially equal dimensions measured in a second direction;a conductive layer disposed over the first segment, but not over the second segment, of the conductive trace, wherein a dimension of the conductive layer measured in the second direction is greater than the dimension of the first segment of the conductive trace; anda conductive bump disposed over the conductive layer.2. The structure of claim 1 , wherein the conductive bump is in direct contact with the conductive layer.3. The structure of claim 2 , wherein the conductive bump is separated from a sidewall of the conductive trace by the conductive layer.4. The structure of claim 1 , wherein the conductive bump and the conductive layer have similar top view profiles.5. The structure of claim 4 , wherein the conductive bump and the conductive layer each have rounded top view profiles.6. The structure of claim 1 , wherein the conductive trace is free of having a passivation layer formed thereon.7. The structure of claim 1 , wherein an entirety of the conductive trace has a uniform dimension measured in the second direction.8. The structure of claim 1 , ...

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Номер записи: 99

27-02-2020 дата публикации

Three-dimensional memory device having bonding structures connected to bit lines and methods of making the same

Номер: US20200066745A1

Автор: Jian Chen, Jixin Yu, Johann Alsmeier, Tae-Kyung Kim, Yan Li

Принадлежит: SanDisk Technologies LLC

Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.

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Номер записи: 100