Conductive Sidewall for Microbumps

Electromigration in microbump connections causes voids in the microbumps, which reduces the lifetime of an integrated circuit containing the microbump. Electromigration lifetime may be increased in microbumps by forming a copper shell around the solder. The copper shell of one microbump contacts the copper shell of a second microbump to enclose the solder of the microbump connection. The copper shell allows higher current densities through the microbump. Thus, smaller microbumps may be manufactured on a smaller pitch without suffering failure from electromigration. Additionally, the copper shell reduces shorting or bridging between microbump connections on a substrate.

Semiconductor assembly and semiconductor package including a solder channel

Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

Solder Bump with Inner Core Pillar in Semiconductor Package

A flip chip semiconductor package has a substrate with a plurality of active devices. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer, second barrier layer, and adhesion layer are formed between the substrate and an intermediate conductive layer. The intermediate conductive layer is in electrical contact with the contact pad. A copper inner core pillar is formed by plating over the intermediate conductive layer. The inner core pillar has a rectangular, cylindrical, toroidal, or hollow cylinder form factor. A solder bump is formed around the inner core pillar by plating solder material and reflowing the solder material to form the solder bump. A first barrier layer and wetting layer are formed between the inner core pillar and solder bump. The solder bump is in electrical contact with the intermediate conductive layer.

Bump structure and electronic packaging solder joint structure and fabricating method thereof

A bump structure includes a substrate, a pad, an electrode and a protruding electrode. The pad is disposed on the substrate. The electrode is formed by a first metal material and disposed on the pad. The protruding electrode is formed by a second metal material and disposed on the electrode, wherein a cross-sectional area of the protruding electrode is less than a cross-sectional area of the electrode.

Mechanisms of forming connectors for package on package

The described embodiments of mechanisms of forming connectors for package on package enable smaller connectors with finer pitch, which allow smaller package size and additional connections. The conductive elements on one package are partially embedded in the molding compound of the package to bond with contacts or metal pads on another package. By embedding the conductive elements, the conductive elements may be made smaller and there are is gaps between the conductive elements and the molding compound. A pitch of the connectors can be determined by adding a space margin to a maximum width of the connectors. Various types of contacts on the other package can be bonded to the conductive elements.

Second Level Interconnect Structures and Methods of Making the Same

The various embodiments of the present invention provide a stress-relieving, second-level interconnect structure that is low-cost and accommodates TCE mismatch between low-TCE packages and PCBs. The various embodiments of the interconnect structure are reworkable and can be scaled to pitches from about 1 millimeter (mm) to about 150 micrometers (μm). The interconnect structure comprises at least a first pad, a supporting pillar, and a solder bump, wherein the first pad and supporting pillar are operative to absorb substantially all plastic strain, therefore enhancing compliance between the two electronic components. The versatility, scalability, and stress-relieving properties of the interconnect structure of the present invention make it a desirable structure to utilize in current two-dimensional and ever-evolving three-dimensional IC structures.

Bump-on-Trace Interconnect

Disclosed herein is a bump-on-trace interconnect with a wetted trace sidewall and a method for fabricating the same. A first substrate having conductive bump with solder applied is mounted to a second substrate with a trace disposed thereon by reflowing the solder on the bump so that the solder wets at least one sidewall of the trace, with the solder optionally wetting between at least half and all of the height of the trace sidewall. A plurality of traces and bumps may also be disposed on the first substrate and second substrate with a bump pitch of less than about 100 μm, and volume of solder for application to the bump calculated based on at least one of a joint gap distance, desired solder joint width, predetermined solder joint separation, bump geometry, trace geometry, minimum trace sidewall wetting region height and trace separation distance.

Low-temperature flip chip die attach

A mechanism for electrically coupling a semiconductor device die to a semiconductor device package substrate that avoids introduction of excessive temperature induced stresses to the semiconductor device die interconnect is provided. In one embodiment, the semiconductor device die is mechanically attached to the package substrate (or another semiconductor device die) at room temperature through the use of a plug-in socket or wedge connection having corresponding mating features formed on the die and substrate. The mechanical interconnect features can be formed on the die and substrate interconnects using an electroplating process. The surfaces of the semiconductor device die and package substrate can then be coupled using an underfill material. A low-temperature solid state bonding process can then be used to diffuse the materials forming the plug and socket features in order to form the electrical connection.

Semiconductor package and method for manufacturing the same

One embodiment provides a semiconductor package by forming a redistribution layer extending from a bonding pad of a semiconductor chip using a photoresist pattern plated with the seed layer. Fabrication of the semiconductor package is relatively simple thereby shortening a manufacturing time and reducing the manufacturing cost, and which can increase an adhered area of input/output terminals and can prevent delamination by connecting and welding the input/output terminals to a pair of redistribution layers.

Semiconductor manufacturing method and semiconductor structure thereof

A semiconductor manufacturing method includes providing a carrier; forming a first photoresist layer; forming plural core portions; removing the first photoresist layer; forming a second photoresist layer; forming a plurality of connection portions, each of the plurality of connection portions includes a first connection layer and a second connection layer and connects to each of the core portions to form a hybrid bump, wherein each of the first connection layers comprises a base portion, a projecting portion and an accommodating space, each base portion comprises an upper surface, each projecting portion is protruded to the upper surface and located on top of each core portion, each accommodating space is located outside each projecting portion, the second connection layers cover the projecting portions and the upper surfaces, and the accommodating spaces are filled by the second connection layers; removing the second photoresist layer to reveal the hybrid bumps.

STUD BUMP STRUCTURE FOR SEMICONDUCTOR PACKAGE ASSEMBLIES

A semiconductor package structure comprises a substrate, a die bonded to the substrate, and one or more stud bump structures connecting the die to the substrate, wherein each of the stud bump structures having a stud bump and a solder ball encapsulating the stud bump to enhance thermal dissipation and reduce high stress concentrations in the semiconductor package structure. 116.-. (canceled)17. A method of forming a stud bump structure in a package structure , comprising:providing a conductive wire;pressing one end of the conductive wire to a bond pad and melting the conductive wire end to form a stud bump on the bond pad;severing the other end of the conductive wire close above the stud bump; andsoldering a solder ball to a top surface of the stud bump, the solder ball encapsulating the stud bump.18. The method of forming a stud bump structure of claim 17 , wherein the conductive wire comprises aluminum claim 17 , aluminum alloy claim 17 , copper claim 17 , copper alloy claim 17 , gold claim 17 , or gold alloy.19. The method of forming a stud bump structure of claim 17 , wherein the pressing and melting the conductive wire to form a stud bump on the bond pad is performed by wire bonding tool.20. The method of forming a stud bump structure of claim 17 , wherein the pressing and melting the conductive wire to form a stud bump on the bond pad is performed by a stud bump bonder.21. The method of forming a stud bump structure of claim 17 , wherein the severing the other end of the conductive wire leaves a tail extending from the bond pad.22. The method of forming a stud bump structure of claim 17 , further comprising applying ultrasonic energy to form the stud bump.23. The method of forming a stud bump structure of claim 17 , wherein the stud bump is disposed at a corner of a die.24. A method for forming a package structure claim 17 , the method comprising:providing a die wherein the die has a first periphery region adjacent a first edge of the die and a second ...

LOW TEMPERATURE DIRECT COPPER-COPPER BONDING

Direct copper-copper bonding at low temperatures is achieved by electroplating copper features on a substrate followed by electroplanarizing the copper features. The copper features are electroplated on the substrate under conditions so that nanotwinned copper structures are formed. Electroplanarizing the copper features is performed by anodically biasing the substrate and contacting the copper features with an electrolyte so that copper is electrochemically removed. Such electrochemical removal is performed in a manner so that roughness is reduced in the copper features and substantial coplanarity is achieved among the copper features. Copper features having nanotwinned copper structures, reduced roughness, and better coplanarity enable direct copper-copper bonding at low temperatures. 1. A method of preparing copper features for direct copper-copper bonding , the method comprising:forming a plurality of first copper features on a first substrate, each of the plurality of first copper features having nanotwinned copper structures; andelectroplanarizing the plurality of first copper features by electrochemically removing a portion of exposed copper from the first copper features prior to directly bonding the first substrate to a second substrate having a plurality of second copper features disposed on the second substrate.2. The method of claim 1 , further comprising:forming the plurality of second copper features on the second substrate, each of the plurality of second copper features having nanotwinned copper structures; andelectroplanarizing the plurality of second copper features by electrochemically removing a portion of exposed copper from the second copper features.3. The method of claim 1 , wherein electroplanarizing the plurality of first copper features comprises:anodically biasing the first substrate and contacting the plurality of first copper features with an electrolyte.4. The method of claim 3 , wherein anodically biasing the first substrate and ...

Electronic apparatus and method for fabricating the same

An electronic apparatus includes a first electronic part with a first terminal, a second electronic part with a second terminal opposite the first terminal, and a joining portion which joins the first terminal and the second terminal. The joining portion contains a pole-like compound extending in a direction in which the first terminal and the second terminal are opposite to each other. The joining portion contains the pole-like compound, so the strength of the joining portion is improved. When the first terminal and the second terminal are joined, the temperature of one of the first electronic part and the second electronic part is made higher than that of the other. A joining material is cooled and solidified in this state. By doing so, the pole-like compound is formed.

METHOD FOR FORMING BUMP STRUCTURE

Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a metal pad over a first substrate and forming a resist layer having an opening over the metal layer. The method for forming a semiconductor structure further includes forming a conductive pillar and a solder layer over the conductive pillar in the opening of the resist layer and removing the resist layer. The method for forming a semiconductor structure further includes removing a portion of the conductive pillar so that the conductive pillar has an angled sidewall. 1. A method for forming a semiconductor structure , comprising:forming a metal pad over a first substrate;forming a resist layer having an opening over the metal layer;forming a conductive pillar and a solder layer over the conductive pillar in the opening of the resist layer;removing the resist layer; andremoving a portion of the conductive pillar so that the conductive pillar has an angled sidewall.2. The method for forming a semiconductor structure as claimed in claim 1 , wherein the angled sidewall includes a first sidewall at a top portion of the conductive pillar and a second sidewall at a bottom portion of the conductive pillar claim 1 , and the first sidewall is in a first direction and the second sidewall is in a second direction different from the first direction.3. The method for forming a semiconductor structure as claimed in claim 2 , further comprising:reflowing the solder layer after the removing the portion of the conductive pillar to form the angled sidewall.4. The method for forming a semiconductor structure as claimed in claim 3 , wherein an inter-metal compound is formed partially covering the first sidewall of the top portion of the conductive pillar after reflowing the solder layer.5. The method for forming a semiconductor structure as claimed in claim 1 , further comprising:forming a seed layer over the metal pad before the conductive pillar is formed, ...

Wire bond wires for interference shielding

Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

METHOD FOR FABRICATING GLASS SUBSTRATE PACKAGE

A substrate comprising a solid glass core having a first surface and a second surface opposed to the first surface; multiple conductors extending through the solid glass core beginning at the first surface and ending at the second surface, wherein one of the conductors has a third surface and a fourth surface, wherein the third surface and the first surface are substantially coplanar, wherein the second surface and the fourth surface are substantially coplanar, wherein one of the conductors comprise a copper-tungsten alloy material, wherein the solid glass core is directly contact with the conductor; and a first dielectric layer and a first metal layer formed at the first surface, wherein the first metal layer at the first surface is electrically coupled with one of the conductors. 1. A chip packaging structure comprising:a glass substrate having a first surface and a second surface opposed to said first surface, wherein said first surface is parallel to said second surface, multiple metal conductors extending through said glass substrate beginning at said first surface and ending at said second surface, wherein one of said metal conductors comprises a cross-section surface parallel to said first surface, wherein said cross-section surface comprises a first edge, a second edge opposite to and substantially parallel with said first edge, a third edge and a fourth edge opposite to said third edge, wherein said first edge has a first length is greater than that of said third and fourth edges, wherein said second edge has a second length is greater than that of said third and fourth edges, wherein said metal conductors comprises a first sidewall, a second sidewall opposite to and substantially parallel with said first sidewall, a third sidewall and a fourth sidewall opposite to said third sidewall;a first metal connection structure is on said first surface, wherein said first metal connection structure comprises a first dielectric layer on said first surface, wherein a ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

In a semiconductor device (SP) according to an embodiment, a solder resist film (first insulating layer, SR) which is in contact with the base material layer, and a resin body (second insulating layer, ) which is in contact with the solder resist film and the semiconductor chip, are laminated in between the base material layer (CR) of a wiring substrate and a semiconductor chip (). In addition, a linear expansion coefficient of the solder resist film is equal to or larger than a linear expansion coefficient of the base material layer, and the linear expansion coefficient of the solder resist film is equal to or smaller than a linear expansion coefficient of the resin body. Also, the linear expansion coefficient of the base material layer is smaller than the linear expansion coefficient of the resin body. According to the above-described configuration, damage of the semiconductor device caused by a temperature cyclic load can be suppressed, and thereby reliability can be improved. 1. A semiconductor device comprising:a wiring substrate including a base material layer, a terminal formed on a first surface of the base material layer, and an insulating layer formed on the first surface such that the insulating film covers a first portion of the terminal, and such that the insulating film exposes a second portion of the terminal;a semiconductor chip including a front surface, a bonding pad formed on the front surface, and a projecting electrode formed on the bonding pad, and mounted over the wiring substrate such that the front surface faces the first surface of the wiring substrate via the projecting electrode;a solder material located between the second portion of the terminal and the projecting electrode; anda resin body located between the wiring substrate and the semiconductor chip, and sealing a connection part between the projecting electrode and the terminal,wherein the insulating film has an opening in which the second portion of the terminal is exposed,wherein, ...

Semiconductor device

An inventive semiconductor device includes: a semiconductor chip including an integrated circuit; a plurality of electrode pads provided on the semiconductor chip and connected to the integrated circuit; a rewiring to which the electrode pads are electrically connected together, the rewiring being exposed on an outermost surface of the semiconductor chip and having an exposed surface area greater than the total area of the electrode pads; and a resin package which seals the semiconductor chip.

INTEGRATED CIRCUIT PACKAGE

An integrated circuit (“IC”) package including at least one IC die having a first side with at least two adjacent bump pads thereon and a second side opposite the first side; a first substrate having a first side with a plurality of electrical contact surfaces thereon; and a plurality of copper pillars, each having a first end attached to one of the adjacent bump pads and a second end attached to one of the electrical contact surfaces. 1. An integrated circuit (IC) package comprising:an IC die having a first side and a second side opposite the first side;a bump pad on the first side;a first substrate having a first side with a plurality of electrical contact surfaces;a plurality of metal pillars, each having a first end attached to the bump pad via a passivation layer, and a second end attached to one of a plurality of electrical contact surfaces of a first substrate;an intermetallic compound surrounding portions of the plurality of metal pillars; anda mold compound encapsulating the intermetallic compound.2. The IC package of claim 1 , wherein the plurality of metal pillars include copper.3. The IC package of claim 1 , wherein the intermetallic compound comprises a copper and lead compound.4. The IC package of claim 3 , wherein the copper and lead compound comprises CuSn.5. The IC package of claim 3 , wherein the copper and lead compound comprises CuSn.6. The IC package of further comprising a second substrate attached to the second side of the IC die.7. The IC package of claim 6 , wherein the mold compound encapsulates at least a portion of the IC die claim 6 , and the first and second substrates.8. The IC package of claim 6 , wherein said first substrate comprises a first leadframe and wherein said second substrate comprises a second leadframe.9. The IC package of claim 1 , wherein the intermetallic compound has higher melting temperatures than solder and lower coefficients of expansion than solder.10. An integrated circuit (“IC”) package comprising:an IC die ...

Wire Bond Wires for Interference Shielding

Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region. 1. An apparatus for a microelectronic package having interference protection , comprising:a substrate having an upper surface and a lower surface opposite the upper surface and having bond pads on the upper surface;a microelectronic device coupled to the upper surface of the substrate;wire bond wires having lower ends coupled to the bond pads, the wire bond wires extending away from the upper surface of the substrate and placed for one or more frequencies associated with the interference;the wire bond wires positioned on at least one side of the microelectronic device to provide a shielding region with respect to the interference;a conductive surface positioned above the wire bond wires for covering the shielding region; andthe wire bond wires having upper ends coupled to the conductive surface.2. The apparatus according to claim 1 , wherein the wire bond wires are place to shield the microelectronic device from the interference.3. The apparatus according to claim 2 , wherein the microelectronic device is an active device.4. The apparatus according to claim 2 ...

METHOD OF FORMING A SOLDER BUMP STRUCTURE

A solder bump structure includes a pillar formed on an electrode pad. The pillar has a concave curve-shaped surface and a geometry defined at least in part by dimensions including a first height greater than a first width. The solder bump structure further includes solder formed on the concave curve-shaped surface of the pillar. The solder has a convex top surface and having dimensions including a second height greater than a second width due to the geometry of the pillar. 1. A solder bump structure comprising:a pillar formed on an electrode pad, the pillar having a concave curve-shaped surface and a geometry defined at least in part by dimensions including a first height greater than a first width; andsolder formed on the concave curve-shaped surface of the pillar, the solder having a convex top surface and having dimensions including a second height greater than a second width due to the geometry of the pillar.2. The solder bump structure according to claim 1 , wherein the solder is in contact with an entirety of the curve-shaped surface of the pillar.3. The solder bump structure according to claim 1 , wherein the pillar includes at least one material selected from the group consisting of: copper claim 1 , nickel claim 1 , silver and gold.4. The solder bump structure according to claim 1 , wherein a thickness of a central portion of the pillar is in a range of ⅕ to ⅔ of a length from a surface of the electrode pad to the convex top surface of the solder.5. The solder bump structure according to claim 4 , wherein the electrode pad includes aluminum.6. The solder bump structure according to claim 1 , wherein a thickness of a central portion of the pillar is in a range of 1 to 50 micrometers.7. The solder bump structure according to claim 1 , wherein the solder has a non-spherical shape.8. A solder bump structure comprising:a resist layer including an opening;a pillar formed on an electrode pad and in the opening of the resist layer, the pillar having a concave curve ...

Anisotropic conductive film structures

Anisotropic conductive film (ACF) structures and manufacturing methods for forming the same are described. The manufacturing methods include preventing clusters of conductive particles from forming between adjacent bonding pads and that are associated with electrical shorting of ACF structures. In some embodiments, the methods involve use of multiple layered ACF materials that include a non-electrically conductive layer that reduces the likelihood of formation of conductive particle clusters between bonding pads. In some embodiment, the methods include the use of ultraviolet sensitive ACF material combined with lithography techniques that eliminate conductive particles from between neighboring bonding pads. In some embodiments, the methods involve the use of insulation spacers that block conductive particles from entering between bonding pads. Any suitable combination of the described methods can be used.

Bump-on-Trace Interconnect

Disclosed herein is a bump-on-trace interconnect with a wetted trace sidewall and a method for fabricating the same. A first substrate having conductive bump with solder applied is mounted to a second substrate with a trace disposed thereon by reflowing the solder on the bump so that the solder wets at least one sidewall of the trace, with the solder optionally wetting between at least half and all of the height of the trace sidewall. A plurality of traces and bumps may also be disposed on the first substrate and second substrate with a bump pitch of less than about 100 μm, and volume of solder for application to the bump calculated based on at least one of a joint gap distance, desired solder joint width, predetermined solder joint separation, bump geometry, trace geometry, minimum trace sidewall wetting region height and trace separation distance.

Advanced Device Assembly Structures And Methods

A microelectronic assembly includes a first substrate having a surface and a first conductive element and a second substrate having a surface and a second conductive element. The assembly further includes an electrically conductive alloy mass joined to the first and second conductive elements. First and second materials of the alloy mass each have a melting point lower than a melting point of the alloy. A concentration of the first material varies in concentration from a relatively higher amount at a location disposed toward the first conductive element to a relatively lower amount toward the second conductive element, and a concentration of the second material varies in concentration from a relatively higher amount at a location disposed toward the second conductive element to a relatively lower amount toward the first conductive element. 1. A microelectronic assembly , comprising:a first substrate having a first surface and first conductive elements;a second substrate having a second surface and second conductive elements; anda plurality of electrically conductive masses, each mass joined to a respective pair of the first and second conductive elements,wherein each electrically conductive mass includes a first material, a second material, and a third material, the third material selected to increase the melting point of an alloy including the third material and at least one of the first material or the second material,wherein a concentration of the first material varies from a relatively higher amount at a location disposed toward the respective first conductive element to a relatively lower amount toward the respective second conductive element,wherein a concentration of the second material varies in concentration from a relatively higher amount at a location disposed toward the respective second conductive element to a relatively lower amount toward the respective first conductive element, andwherein the third material has a highest concentration at a location ...

Semiconductor Device and Method of Forming Patterned Repassivation Openings Between RDL and UBM to Reduce Adverse Effects of Electro-Migration

A semiconductor device has a semiconductor wafer with a first conductive layer formed over a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A plurality of openings is formed in the second insulating layer in a bump formation area of the semiconductor wafer to expose the second conductive layer and reduce adverse effects of electro-migration. The openings are separated by portions of the second insulating layer. A UBM layer is formed over the openings in the second insulating layer in the bump formation area electrically connected to the second conductive layer. A bump is formed over the UBM layer.

DIELECTRIC AND METALLIC NANOWIRE BOND LAYERS

In some examples, an electronic device comprises a first component having a surface, a second component having a surface, and a bond layer positioned between the surfaces of the first and second components to couple the first and second components to each other. The bond layer includes a set of metallic nanowires and a dielectric portion. The dielectric portion comprises a polymer matrix and dielectric nanoparticles. 1. A method of forming an electronic device , the method comprising:providing a first die including a first surface and a second die including a second surface; andpositioning a bond layer positioned between the first surface and second surface the bond layer including a set of metallic wires and a dielectric portion, the dielectric portion comprising a polymer matrix and dielectric nanoparticles.2. The method of claim 1 , wherein the dielectric nanoparticles are selected from the group consisting of silicon nitride claim 1 , aluminum nitride claim 1 , boron nitride claim 1 , and aluminum oxide.3. The method of claim 1 , wherein the dielectric portion is porous.4. The method of claim 1 , wherein a the set of metallic wires is a set of metallic nanowires including a length-to-diameter ratio of at least 100:1.5. The method of claim 1 , wherein the bond layer further includes a metal layer coupled to the set of metallic wires.6. The method of claim 1 , wherein the bond layer further includes a metal layer and a set of metallic nanoparticles positioned on the metal layer claim 1 , the set of metallic nanoparticles coupled to the set of metallic wires.7. The method of claim 1 , wherein the set of metallic wires extend in a direction substantially orthogonal to the first surface or the second surface.8. The method of claim 1 , wherein a viscosity of the dielectric portion is sufficient to prevent flow of the dielectric portion into a pore of a nanowire in the set of metallic nanowires.9. The method of claim 1 , wherein a diameter of a wire in the set of ...

DRIVING SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND MICRO LED BONDING METHOD

The present disclosure provides a driving substrate and a manufacturing method thereof, and a micro LED bonding method. The driving substrate includes: a base substrate; a driving function layer provided on the base substrate, and including a plurality of driving thin film transistors and a plurality of common electrode lines; a pad layer including a plurality of pads provided on a side of the driving function layer away from the base substrate, each pad including a pad body and a microstructure of hard conductive material provided on a side of the pad body away from the base substrate; and a plurality of buffer structures provided on the side of the driving function layer away from the base substrate, each buffer structure surrounding a portion of a corresponding microstructure close to the base substrate, and a height of the buffer structure being lower than a height of the microstructure. 1. A driving substrate , comprising:a base substrate;a driving function layer provided on the base substrate, the driving function layer comprising a plurality of driving thin film transistors and a plurality of common electrode lines;a pad layer comprising a plurality of pads provided on a side of the driving function layer away from the base substrate, each pad comprising a pad body and a microstructure of hard conductive material provided on a side of the pad body away from the base substrate; anda plurality of buffer structures provided on the side of the driving function layer away from the base substrate, each buffer structure surrounding a portion of a corresponding microstructure close to the base substrate, and a height of the buffer structure being lower than a height of the microstructure.2. The driving substrate according to claim 1 , wherein each driving thin film transistor in the driving function layer comprises a gate claim 1 , a first electrode and a second electrode claim 1 , the pad layer comprises a plurality of first pads and a plurality of second pads claim ...

Pre-conductive array disposed on target circuit substrate and conductive structure array thereof

A pre-conductive array disposed on a target circuit substrate comprises a plurality of conductive electrode groups disposed on the target circuit substrate, and at least a conductive particle dispose on each of conductive electrodes of a part or all of the conductive electrode groups. The at least a conductive particle and the corresponding conductive electrode form a pre-conductive structure, and the pre-conductive structures form the pre-conductive array.

SEMICONDUCTOR DEVICE

A technique capable of improving reliability of a semiconductor device is provided. In the present invention, as a wiring board on which a semiconductor chip is mounted, a build-up wiring board is not used but a through wiring board THWB is used. In this manner, in the present invention, the through wiring board formed of only a core layer is used, so that it is not required to consider a difference in thermal expansion coefficient between a build-up layer and the core layer, and besides, it is not required either to consider the electrical disconnection of a fine via formed in the build-up layer because the build-up layer does not exist. As a result, according to the present invention, the reliability of the semiconductor device can be improved while a cost is reduced. 121-. (canceled)22. A semiconductor device , comprising:(a) a semiconductor chip having a surface on which a plurality of protruding electrodes are arranged;(b) a wiring board including a core layer, the core layer having a first front surface on which a plurality of terminals are arranged, and a first back surface opposite the first front surface, the semiconductor chip being mounted over the first front surface so that the plurality of protruding electrodes are electrically connected to the plurality of terminals, respectively; and(c) a sealing resin filled between the semiconductor chip and the wiring board,wherein the plurality of protruding electrodes includes a plurality of first protruding electrodes and a plurality of second protruding electrodes, and the plurality of terminals includes a plurality of first terminals and a plurality of second terminals,wherein the core layer includes the plurality of first terminals, a plurality of first through-holes, and the plurality of second terminals,wherein the plurality of first terminals are arranged in a first area of the first front surface of the core layer, each of the plurality of first terminals being electrically connected to a respective ...

Wire bond wires for interference shielding

Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

WIRE BOND WIRES FOR INTERFERENCE SHIELDING

Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region. 1. An apparatus , comprising:a substrate having an upper surface and a lower surface opposite the upper surface;a microelectronic device coupled to the upper surface of the substrate; andwire bond wires having first ends coupled to the upper surface and second ends extending away therefrom, the wire bond wires arranged to shield one or more frequencies.2. The apparatus according to claim 1 , wherein the first ends and the second ends respectively are lower ends and upper ends claim 1 , the apparatus further comprising a conductive layer positioned above the upper ends of the wire bond wires for covering at least a portion of a region to be shielded.3. The apparatus according to claim 2 , wherein the first ends are lower ends claim 2 , and wherein the upper ends of the wire bond wires are bonded to the conductive layer.4. The apparatus according to claim 3 , wherein the conductive layer is a first conductive layer claim 3 , the apparatus further comprising a second conductive layer formed on or in the substrate.5. The apparatus according to claim 4 , wherein ...

BUMP-ON-TRACE INTERCONNECT

Disclosed herein is a bump-on-trace interconnect with a wetted trace sidewall and a method for fabricating the same. A first substrate having conductive bump with solder applied is mounted to a second substrate with a trace disposed thereon by reflowing the solder on the bump so that the solder wets at least one sidewall of the trace, with the solder optionally wetting between at least half and all of the height of the trace sidewall. A plurality of traces and bumps may also be disposed on the first substrate and second substrate with a bump pitch of less than about 100 μm, and volume of solder for application to the bump calculated based on at least one of a joint gap distance, desired solder joint width, predetermined solder joint separation, bump geometry, trace geometry, minimum trace sidewall wetting region height and trace separation distance. 1. A method of forming a semiconductor package , the method comprising:receiving a first semiconductor package, the first semiconductor package comprising a first substrate and a conductive pillar at a first side of the first substrate;receiving a second semiconductor package, the second semiconductor package comprising a second substrate and a conductive trace on a first surface of the second substrate, a sidewall of the conductive trace having a first height; andbonding the conductive pillar to the conductive trace using a conductive joint, wherein after the bonding, the conductive joint covers the sidewall of the conductive trace by at least half the first height, and the conductive pillar is spaced from the conductive trace by a first distance, the first distance being smaller than the first height.2. The method of claim 1 , wherein the conductive joint comprises solder.3. The method of claim 2 , wherein bonding the conductive pillar comprises performing a reflow process to bond the conductive pillar to the conductive trace.4. The method of claim 1 , wherein a first surface of the conductive pillar distal from the ...

COPPER NANOROD-BASED THERMAL INTERFACE MATERIAL (TIM)

A copper nanorod thermal interface material (TIM) is described. The copper nanorod TIM includes a plurality of copper nanorods having a first end thermally coupled with a first surface, and a second end extending toward a second surface. A plurality of copper nanorod branches are formed on the second end. The copper nanorod branches are metallurgically bonded to a second surface. The first surface may be the back side of a die. The second surface may be a heat spread or a second die. The TIM may include a matrix material surrounding the copper nanorods. In an embodiment, the copper nanorods are formed in clusters. 1. A microelectronic package , comprising:a substrate;a die electrically coupled with the substrate;an integrated heat spreader overlying the die; and a plurality of copper nanorods, each having a first end thermally coupled with the back surface of the die and a second end extending toward the integrated heat spreader; and', 'a plurality of copper nanorod branches extending from each second end, wherein the copper nanorod branches are metallurgically bonded to the integrated heat spreader., 'a thermal interface material thermally coupling the integrated heat spreader with a back surface of the die, wherein the TIM comprises2. The microelectronic package of claim 1 , wherein a bond line thickness (BLT) between the back surface of the die and the integrated heat spreader is less than 50 μm.3. The microelectronic package of claim 1 , wherein the copper nanorods have a diameter less than 20 μm.4. The microelectronic package of claim 1 , wherein the thermal interface material further comprises a matrix material between the back surface of the first die and the integrated heat spreader.5. The microelectronic package of claim 1 , further comprising a copper layer formed over the back surface of the die claim 1 , wherein the first ends are metallurgically bonded with the copper layer.6. The microelectronic package of claim 1 , wherein the nanorods are clustered ...

ASSEMBLY OF AN INTEGRATED CIRCUIT CHIP AND OF A PLATE

An assembly includes an integrated circuit chip and a plate with at least one heat removal channel arranged between the chip and the plate. Metal sidewalls are formed to extend from one surface of the chip to an opposite surface of the plate. The assembly is encapsulated in a body that includes an opening extending to reach the channel. The plate may be one of an interposer, an integrated circuit chip, a support of surface-mount type, or a metal plate. 1. A method of manufacturing a flip-chip assembly of an integrated circuit chip and of a plate between which is arranged at least one channel delimited by metal sidewalls , the method comprising the steps of:a) forming metal walls corresponding to at least part of a height of each of the sidewalls on one of a surface of the integrated circuit chip or a surface of the plate;b) inserting sacrificial resin between the metal walls extending to at least a contour of a smaller one of the plate and the integrated circuit chip;c) mounting the integrated circuit chip and the plate on each other, the sidewalls being formed by the metal walls extending from the integrated circuit chip surface to the plate surface; andd) removing the sacrificial resin.2. The method of claim 1 , wherein the metal walls are formed at the same time as connection elements arranged between opposite surfaces of the integrated circuit chip and of the plate.3. The method of claim 1 , wherein at step c) claim 1 , the sacrificial resin extends along an entire length of said at least one channel and to a height of the sidewalls.4. The method of claim 1 , wherein at step c) claim 1 , the sidewalls extend from the integrated circuit chip surface to the plate surface claim 1 , the sacrificial resin fully obstructing said at least one channel to said contour.5. The method of claim 1 , wherein claim 1 , before step d) claim 1 , interstitial resin is arranged in an entire volume accessible between the integrated circuit chip and the plate.6. The method of claim 1 ...

EXTRUSION-RESISTANT SOLDER INTERCONNECT STRUCTURES AND METHODS OF FORMING

Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, an interconnect structure can include: a photosensitive polyimide (PSPI) layer including a pedestal portion; a controlled collapse chip connection (C4) bump overlying the pedestal portion of the PSPI layer; a solder overlying the C4 bump and contacting a side of the C4 bump; and an underfill layer abutting the pedestal portion of the PSPI and the C4 bump, wherein the underfill layer and the solder form a first interface separated from the PSPI pedestal. 1. An interconnect structure comprising:a photosensitive polyimide (PSPI) layer including a pedestal portion;a controlled collapse chip connection (C4) bump overlying the pedestal portion of the PSPI layer;a solder overlying the C4 bump and contacting a side of the C4 bump; andan underfill layer abutting the pedestal portion of the PSPI and the C4 bump, wherein the underfill layer and the solder form a first interface separated from the PSPI pedestal.2. The interconnect structure of claim 1 , wherein the solder is completely isolated from the PSPI layer.3. The interconnect structure of claim 1 , wherein the C4 bump includes:a pad;a ball limiting metallurgy (BLM) layer over the pad; anda thick copper layer over the BLM layer.4. The interconnect structure of claim 3 , wherein the solder overlies the thick copper layer and directly contacts a side of the thick copper layer.5. The interconnect structure of claim 4 , wherein the solder directly contacts a side of the BLM layer.6. The interconnect structure of claim 1 , further comprising a gap between the solder and the pedestal portion of the PSPI layer.7. The interconnect structure of claim 6 , wherein the underfill and the pedestal portion of the PSPI layer form a second interface.8. The interconnect structure of claim 7 , wherein the first interface and the second interface are separated by the gap.9. The interconnect structure of claim ...

Packaged semiconductor device with a particle roughened surface

A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame. A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame and with a reflow wall that surrounds a portion of the solder joint that couples the semiconductor device to the lead frame. A packaged semiconductor device with a reflow wall that surrounds a portion of a solder joint that couples a semiconductor device to a lead frame.

Copper nanorod-based thermal interface material (tim)

A copper nanorod thermal interface material (TIM) is described. The copper nanorod TIM includes a plurality of copper nanorods having a first end thermally coupled with a first surface, and a second end extending toward a second surface. A plurality of copper nanorod branches are formed on the second end. The copper nanorod branches are metallurgically bonded to a second surface. The first surface may be the back side of a die. The second surface may be a heat spread or a second die. The TIM may include a matrix material surrounding the copper nanorods. In an embodiment, the copper nanorods are formed in clusters.

METHOD OF FORMING A SOLDER BUMP STRUCTURE

A method of the present invention includes preparing a substrate having a surface on which a electrode pad is formed, forming a resist layer on the substrate, the resist layer having an opening on the electrode pad, filling conductive paste in the opening of the resist layer; sintering the conductive paste in the opening to form a conductive layer which covers a side wall of the resist layer and a surface of the electrode pad in the opening, a space on the conductive layer leading to the upper end of the opening being formed, filling solder in the space on the conductive layer and removing the resist layer. 1. A method of forming a solder bump structure , comprising the steps of:filling conductive paste in an opening of a layer formed over an electrode pad;sintering the conductive paste in the opening to cause shrinkage of the conductive paste to form a conductive layer having a cone-shaped surface formed therein, the conductive layer covering a side wall of the opening and a surface of the electrode pad in the opening; andfilling solder in the cone-shaped surface on the conductive layer.2. The method according to claim 1 , wherein the step of filling conductive paste includes a step of screen-printing conductive paste containing metal nanoparticles in a solvent on the substrate.3. The method according to claim 1 , wherein the step of filling conductive paste includes a step of injecting conductive paste containing metal nanoparticles in a solvent into the opening.4. The method according to claim 1 , wherein the conductive paste includes at least one of copper claim 1 , nickel claim 1 , silver or gold.5. The method according to claim 1 , wherein a cross-section of the conductive layer has a conformal shape.6. The method according to claim 1 , wherein a thickness of a central portion of a cross-section of the conductive layer is in a range of ⅕ to ⅔ of a depth of the opening.7. The method according to claim 1 , further comprising a step of etching a surface of the ...

SOLDER BALL DIMENSION MANAGEMENT

A solder ball assembly can include a first spring element having a first shape and formed from a first elastic electrically conductive material. The solder ball assembly can also include a second spring element having a second shape and formed from a second elastic electrically conductive material. The second spring element is mechanically attached to the first spring element to form a spring assembly. The solder ball can be configured to enclose the spring assembly. 1. A solder ball assembly comprising:a first spring element having a first shape and formed from a first elastic electrically conductive material;a second spring element having a second shape and formed from a second elastic electrically conductive material, the second spring element mechanically attached to the first spring element to form a spring assembly; anda solder ball configured to enclose the spring assembly.2. The solder ball assembly of claim 1 , wherein the first spring element and the second spring element are formed from spring steel.3. The solder ball assembly of claim 1 , wherein the first elastic electrically conductive material is different from the second elastic electrically conductive material.4. The solder ball assembly of claim 1 , wherein a weight is fastened to an attachment point at which the first spring element and the second spring element are mechanically attached.5. The solder ball assembly of claim 1 , wherein the solder ball includes high-temperature solder.6. The solder ball assembly of claim 1 , wherein at least one of the first spring element and the second spring element has a “C” shape.7. The solder ball assembly of claim 1 , wherein the first shape is a circle.8. The solder ball assembly of claim 1 , wherein the first shape is an oval.9. The solder ball assembly of claim 1 , wherein the second shape is a convex polygon.10. The solder ball assembly of claim 1 , wherein the second shape is a helix.11. The solder ball assembly of claim 1 , wherein the first shape is ...

Semiconductor Packaging Arrangement

A semiconductor packaging arrangement includes a transistor device including a first side including a source electrode and a gate electrode, a die pad having a first surface, and a lead having a first surface. A first conductive member is arranged between the source electrode and the first surface of the die pad and spaces the source electrode from the first surface of the die pad by a distance that is greater than a distance between the gate electrode and the first surface of the lead.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a conductive bump for disposing over a substrate and an elongated ferromagnetic member surrounded by the conductive bump, including a first end and a second end, and extending from the first end to the second end, the elongated ferromagnetic member is disposed substantially orthogonal to the substrate to dispose the conductive bump at a predetermined orientation and at a predetermined position of the substrate. Further, a method of manufacturing a semiconductor structure includes providing a substrate, forming a conductive trace within the substrate, applying an electric current passing through the conductive trace to generate an electromagnetic field and disposing a conductive bump including an elongated ferromagnetic member in a predetermined orientation and at a predetermined position above the substrate in response to the electromagnetic field generated by the conductive trace. 1. A semiconductor structure , comprising:a conductive bump for disposing over a substrate; andan elongated ferromagnetic member surrounded by the conductive bump, including a first end and a second end, and extended from the first end to the second end,wherein the elongated ferromagnetic member is disposed substantially orthogonal to the substrate to dispose the conductive bump at a predetermined orientation and at a predetermined position over the substrate.2. The semiconductor structure of claim 1 , wherein the elongated ferromagnetic member has a ratio of a width to a length of about 1:2 to about 1:20.3. The semiconductor structure of claim 1 , wherein the predetermined orientation is a center of the conductive bump disposed on a central axis of the elongated ferromagnetic member.4. The semiconductor structure of claim 1 , wherein the first end is exposed from an outer surface of the conductive bump.5. The semiconductor structure of claim 1 , wherein the first end is covered by an outer surface of the conductive bump.6. The semiconductor structure of ...

Packaging through Pre-Formed Metal Pins

A package includes first package component and a second package component. The first package component includes a first electrical connector at a surface of the first package component, and a first solder region on a surface of the first electrical connector. The second package component includes a second electrical connector at a surface of the second package component, and a second solder region on a surface of the second electrical connector. A metal pin has a first end bonded to the first solder region, and a second end bonded to the second solder region. 1. A package comprising: a first electrical connector at a surface of the first package component; and', 'a first solder region on a surface of the first electrical connector;, 'a first package component comprising a second electrical connector at a surface of the second package component; and', 'a second solder region on a surface of the second electrical connector; and, 'a second package component comprising a first end bonded to the first solder region, wherein the first end has a T-shaped cross-sectional view; and', 'a second end bonded to the second solder region., 'a metal pin formed of a non-solder metallic material, the metal pin comprising2. The package of claim 1 , wherein the first solder region is separated from the second solder region.3. The package of claim 1 , wherein the first end of the metal pin is spaced apart from the first electrical connector by a portion of the first solder region.4. The package of claim 3 , wherein the second end of the metal pin is spaced apart from the second electrical connector by a portion of the second solder region.5. The package of claim 1 , wherein the first end is in physical contact with the first electrical connector claim 1 , with no metal-to-metal direct bonding formed between the first end of the metal pin and the first electrical connector.6. The package of claim 5 , wherein the metal pin is bonded to the first electrical connector by the first solder ...

Semiconductor Device and Method of Forming Bump Structure with Insulating Buffer Layer to Reduce Stress on Semiconductor Wafer

A semiconductor wafer has a plurality of semiconductor die with contact pads for electrical interconnect. An insulating layer is formed over the semiconductor wafer. A bump structure is formed over the contact pads. The bump structure has a buffer layer formed over the insulating layer and contact pad. A portion of the buffer layer is removed to expose the contact pad and an outer portion of the insulating layer. A UBM layer is formed over the buffer layer and contact pad. The UBM layer follows a contour of the buffer layer and contact pad. A ring-shaped conductive pillar is formed over the UBM layer using a patterned photoresist layer filled with electrically conductive material. A conductive barrier layer is formed over the ring-shaped conductive pillar. A bump is formed over the conductive barrier layer. The buffer layer reduces thermal and mechanical stress on the bump and contact pad. 1. A method of making a semiconductor device , comprising:providing a semiconductor wafer including a contact pad;forming a buffer layer over the semiconductor wafer;forming a ring-shaped conductive pillar over the buffer layer; andforming a bump within the ring-shaped conductive pillar and electrically coupled to the contact pad.2. The method of claim 1 , further including forming a conductive layer over the buffer layer and contact pad prior to forming the ring-shaped conductive pillar.3. The method of claim 1 , further including forming a conductive layer over the ring-shaped conductive pillar prior to forming the bump.4. The method of claim 1 , wherein forming the ring-shaped conductive pillar includes:forming a photoresist layer over the semiconductor wafer;removing a portion of the photoresist layer to form a ring-shaped opening over the buffer layer;depositing an electrically conductive material in the ring-shaped opening; andremoving the photoresist layer leaving the ring-shaped conductive pillar.5. The method of claim 1 , wherein forming the bump includes:forming a ...

Semiconductor device and method of fabricating the same

A semiconductor device includes a semiconductor substrate, a conductive pad disposed on the semiconductor substrate, and a pillar pattern disposed on the conductive pad. The semiconductor device further includes a solder seed pattern disposed on the pillar pattern, and a solder portion disposed on the pillar pattern and the solder seed pattern. A first width of the solder seed pattern is less than a second width of a top surface of the pillar pattern.

ELECTRONIC APPARATUS AND METHOD FOR FABRICATING THE SAME

An electronic apparatus includes a first electronic part with a first terminal, a second electronic part with a second terminal opposite the first terminal, and a joining portion which joins the first terminal and the second terminal. The joining portion contains a pole-like compound extending in a direction in which the first terminal and the second terminal are opposite to each other. The joining portion contains the pole-like compound, so the strength of the joining portion is improved. When the first terminal and the second terminal are joined, the temperature of one of the first electronic part and the second electronic part is made higher than that of the other. A joining material is cooled and solidified in this state. By doing so, the pole-like compound is formed. 1. An electronic apparatus comprising:a first electronic part with a first terminal;a second electronic part with a second terminal opposite the first terminal; anda joining portion including a first compound and a second compound, the first compound including an intermetallic compound containing a first element and a second element different from the first element, the first compound extending in a direction from the first terminal to the second terminal, the second compound containing the first element and the second element, the second compound joining the first terminal and the second terminal, the second compound being around the first compound.2. The electronic apparatus according to claim 1 , wherein the first element is Sn claim 1 , the second element is Ag claim 1 , and the intermetallic compound is AgSn.3. The electronic apparatus according to further comprising a first member which is disposed over the first electronic part and which has first heat capacity.4. The electronic apparatus according to claim 3 , wherein the first member is separate from the second electronic part.5. The electronic apparatus according to claim 3 , wherein heat capacity of the first electronic part over which ...

BUMP STRUCTURE, DISPLAY DEVICE INCLUDING A BUMP STRUCTURE, AND METHOD OF MANUFACTURING A BUMP STRUCTURE

A bump structure includes a first bump disposed on a substrate, the first bump including a first metal, at least one antioxidant member surrounded by the first bump, the at least one antioxidant member including a second metal having an ionization tendency greater than an ionization tendency of the first metal, and a second bump disposed on the first bump and the at least one antioxidant member. 1. A bump structure , comprising:a first bump disposed on a substrate, the first bump including a first metal;at least one antioxidant member surrounded by the first bump, wherein the at least one antioxidant member includes a second metal having an ionization tendency greater than an ionization tendency of the first metal; anda second bump disposed on the first bump and the at least one antioxidant member.2. The bump structure of claim 1 , wherein the first metal is copper (Cu) and the second metal is zinc (Zn).3. The bump structure of claim 1 , wherein the second bump includes gold (Au).4. The bump structure of claim 1 , wherein the antioxidant member is in contact with the second bump.5. The bump structure of claim 4 , wherein the first bump is in contact with the second bump.6. The bump structure of claim 1 , further comprising a third bump disposed between the first bump and the second bump.7. The bump structure of claim 6 , wherein the first metal is copper (Cu) and the second metal is zinc (Zn).8. The bump structure of claim 6 , wherein the second bump includes gold (Au).9. The bump structure of claim 6 , wherein the third bump includes nickel (Ni).10. The bump structure of claim 6 , wherein the antioxidant member is in contact with the third bump.11. The bump structure of claim 10 , wherein the first bump is in contact with the third bump.12. A display device claim 10 , comprising:a display panel; and a substrate comprising a driver integrated circuit, a wire, and an insulation layer covering the driver integrated circuit and the wire; and', 'a bump structure ...

FILM SCHEME FOR BUMPING

A bump structure with a barrier layer, and a method for manufacturing the bump structure, are provided. In some embodiments, the bump structure comprises a conductive pad, a conductive bump, and a barrier layer. The conductive pad comprises a pad material. The conductive bump overlies the conductive pad, and comprises a lower bump layer and an upper bump layer covering the lower bump layer. The barrier layer is configured to block movement of the pad material from the conductive pad to the upper bump layer along sidewalls of the lower bump layer. In some embodiments, the barrier layer is a spacer lining the sidewalls of the lower bump layer. In other embodiments, the barrier layer is between the barrier layer and the conductive pad, and spaces the sidewalls of the lower bump layer from the conductive pad. 1. An integrated circuit comprising:a conductive pad comprising a pad material;a dielectric structure overlying the conductive pad;a metal bump that extends through the dielectric structure from the conductive pad and is devoid of copper, wherein the metal bump comprises a first metal layer and a second metal layer, that respectively comprise different metals, wherein the second metal layer overlies the first metal layer and is at a topmost surface of the metal bump, and wherein a width of the metal bump is continuous from the conductive pad to the topmost surface; anda conductive spacer having a pair of spacer segments, wherein the metal bump is between and directly contacts the spacer segments, and wherein the conductive spacer is configured to block movement of the pad material from the conductive pad to the second metal layer.2. The integrated circuit according to claim 1 , wherein a top of the dielectric structure has a recess within which the metal bump is arranged claim 1 , and wherein the metal bump extends through a recessed surface of the dielectric structure that is in the recess and that is recessed relative to a top surface of the dielectric structure. ...

CHIP PACKAGE

A display device comprises a display panel substrate and a glass substrate over said display panel substrate, wherein said display panel substrate comprises multiple contact pads, a display area, a first boundary, a second boundary, a third boundary and a fourth boundary, wherein said display area comprises a first edge, a second edge, a third edge and a fourth edge, wherein said first boundary is parallel to said third boundary and said first and third edges, wherein said second boundary is parallel to said fourth boundary and said second and fourth edges, wherein a first least distance between said first boundary and said first edge, wherein a second least distance between said second boundary and said second edge, a third least distance between said third boundary and said third edge, a fourth distance between said fourth boundary and said fourth edge, and wherein said first, second, third and fourth least distances are smaller than 100 micrometers, and wherein said glass substrate comprising multiple metal conductors through in said glass substrate and multiple metal bumps are between said glass substrate and said display panel substrate, wherein said one of said metal conductors is connected to one of said contact pads through one of said metal bumps. 1. A chip package comprising:{'sub': '2', 'a solid layer having a first surface and a second surface opposite to said first surface, wherein said first surface is substantially parallel to said second surface, wherein major one of compositions of said solid layer comprises SiO, wherein said solid layer has a thickness between 100 and 300 micrometers, wherein said solid layer comprises a first region and a second region, wherein a first region has a width greater than that of said second region in the same direction;'}a plurality of copper plugs in a plurality of through vias in said second region of said solid layer respectively, wherein said plurality of copper plugs comprise a first copper layer contacts with a ...

Double solder bumps on substrates for low temperature flip chip bonding

Multiple injections of molten solder are employed to form double solder bumps having outer layers that melt at lower temperatures than the inner portions thereof. During a flip chip assembly process, the reflow temperature is above the melting temperature of the outer layers and below the melting temperature of the inner portions of the solder bumps. As the inner portions of the solder bumps do not collapse during reflow, a flip chip assembly can be made at relatively low temperatures and have a high stand-off height. A structure having double solder bumps facilitates flip chip assembly.

BUMP-ON-TRACE INTERCONNECT

Disclosed herein is a bump-on-trace interconnect with a wetted trace sidewall and a method for fabricating the same. A first substrate having conductive bump with solder applied is mounted to a second substrate with a trace disposed thereon by reflowing the solder on the bump so that the solder wets at least one sidewall of the trace, with the solder optionally wetting between at least half and all of the height of the trace sidewall. A plurality of traces and bumps may also be disposed on the first substrate and second substrate with a bump pitch of less than about 100 μm, and volume of solder for application to the bump calculated based on at least one of a joint gap distance, desired solder joint width, predetermined solder joint separation, bump geometry, trace geometry, minimum trace sidewall wetting region height and trace separation distance. 1. A semiconductor package comprising: a first substrate;', 'a conductive land proximate a first side of the first substrate; and', 'a conductive pillar, a first surface of the conductive pillar coupled to the conductive land;, 'a first semiconductor device comprising a second substrate; and', 'a conductive trace on a surface of the second substrate facing the conductive pillar, a sidewall of the conductive trace having a first height; and, 'a second semiconductor device comprisinga conductive joint between the conductive pillar and the conductive trace, the conductive joint covering the sidewall of the conductive trace by at least half the first height, the conductive pillar being spaced from the conductive trace by a first distance, the first distance being smaller than the first height.2. The semiconductor package of claim 1 , wherein a second surface of the conductive pillar opposing the first surface of the conductive pillar has a first width claim 1 , wherein a third surface of the conductive trace facing the conductive pillar has a second width claim 1 , the first width being larger than the second width.3. The ...

Light emitting diode display device

A light emitting diode display device includes a display board comprising a plurality of unit pixels, a drive circuit board including a plurality of drive circuit regions corresponding to the plurality of unit pixels, and a plurality of bumps interposed between the plurality of unit pixels and the plurality of drive circuit regions. The plurality of unit pixels comprises a first unit pixel including a first P electrode. The plurality of drive circuit regions comprises a first drive circuit region corresponding to the first unit pixel and a first pad connected to a first drive transistor, the plurality of bumps includes a first solder in contact with the first pad, and a first bump on the first solder and including a first filler in contact with the first P electrode, the first solder includes at least one of tin and silver, and the first filler includes copper or nickel.

CONDUCTIVE CONNECTIONS, STRUCTURES WITH SUCH CONNECTIONS, AND METHODS OF MANUFACTURE

In some embodiments, to increase the height-to-pitch ratio of a solder connection that connects different structures with one or more solder balls, only a portion of a solder ball's surface is melted when the connection is formed on one structure and/or when the connection is being attached to another structure. In some embodiments, non-solder balls are joined by an intermediate solder ball (). A solder connection may be surrounded by a solder locking layer () and may be recessed in a hole () in that layer. Other features are also provided. 1. A structure comprising circuitry comprising a semiconductor integrated circuit , the circuitry comprising a conductive connecting feature which has a first end and a second end , the connecting feature extending along a first line from the first end to the second end , wherein at each point of the first line , the connecting feature has a transversal cross-sectional area which is an area of the connecting feature's cross section perpendicular to the first line at said point;wherein the connecting feature comprises a first segment, a second segment physically contacting the first segment, and a third segment physically contacting the second segment, wherein surfaces of the first, second and third segments have the same melting temperature;wherein the first segment has a first end and a second end which is located at a junction with the second segment;wherein the third segment has a first end which is located at a junction with the second segment, and the third segment has a second end; decreases from the first end of the first segment to the junction of the first and second segments;', 'increases from the junction of the first and second segments to a position in the second segment;', 'decreases from said position in the second segment to a junction of the second and third segments; and', 'increases from the junction of the second and third segments to the second end of the third segment;, 'wherein the transversal cross- ...

Module, method for manufacturing the same, and electronic device

A module, comprising an electronic component having a first electrode, a mounting board having a second electrode, a solder-bump configured to connect the first electrode and the second electrode, and a thermoplastic resin member configured to contact both the first electrode and the second electrode and cover the solder-bump, so as to form a space between the electronic component and the mounting board.

Dielectric and metallic nanowire bond layers

In some examples, an electronic device comprises a first component having a surface, a second component having a surface, and a bond layer positioned between the surfaces of the first and second components to couple the first and second components to each other. The bond layer includes a set of metallic nanowires and a dielectric portion. The dielectric portion comprises a polymer matrix and dielectric nanoparticles.

Mixed ubm and mixed pitch on a single die

Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having a mixed under-bump metallization (UBM) size and pitch on a single die. A first set of UBMs having a first total plateable surface area is formed on a first region of a die. A second set of UBMs having an equal total plateable surface area is formed on a second region of the die. A solder bump having a calculated solder height is applied to a plateable surface of each UBM. The solder height is calculated such that a volume of solder in the first region is equal to a volume of solder in the second region.

Interconnect Crack Arrestor Structure and Methods

A system and method for preventing cracks is provided. An embodiment comprises placing crack stoppers into a connection between a semiconductor die and a substrate. The crack stoppers may be in the shape of hollow or solid cylinders and may be placed so as to prevent any cracks from propagating through the crack stoppers. 1. A semiconductor device comprising:a conductive pad on a substrate; anda first crack stopper extending from the conductive pad, the first crack stopper comprising a hollow tube, the first crack stopper located along an exterior region of the conductive pad; anda first conductive material surrounding the first crack stopper.2. The semiconductor device of claim 1 , wherein the wire comprises a cylindrical shape.3. The semiconductor device of claim 1 , wherein the conductive region is an underbump metallization.4. The semiconductor device of claim 1 , wherein the first crack stopper has an outer diameter between 15 microns and 60 microns.5. The semiconductor device of claim 1 , wherein the first crack stopper has an inner diameter between 5 microns and 20 microns.6. The semiconductor device of claim 1 , wherein the first crack stopper comprises one or more additional hollow tubes claim 1 , wherein each of the hollow tubes of the first crack stopper are spaced equidistant from each other along the exterior region of the conductive pad.7. The semiconductor device of claim 1 , wherein the first crack stopper comprises an additional hollow tube claim 1 , the additional hollow tube disposed at a center of the conductive pad.8. The semiconductor device of claim 1 , wherein the first conductive material is coupled to a second conductive pad on a second substrate.9. The semiconductor device of claim 8 , wherein the first conductive material is electrically coupled to a second crack stopper disposed on the second conductive pad.10. A semiconductor device comprising:a conductive pad on a substrate; anda first crack stopper extending from the conductive pad, ...

COMBING BUMP STRUCTURE AND MANUFACTURING METHOD THEREOF

A manufacturing method of a combing bump structure is disclosed. In the manufacturing method, a semiconductor substrate is provided, a pad is formed on the semiconductor substrate, a conductive layer is formed on the pad, a solder bump is formed on the conductive layer, and at least two metal side walls are formed disposed along opposing laterals of the solder bump respectively. 1. A manufacturing method of a combing bump structure , the manufacturing method comprising:providing a semiconductor substrate;forming a pad on the semiconductor substrate;forming a conductive layer on the pad;forming a solder bump on the conductive layer; andforming at least two metal side walls disposed along opposing laterals of the solder bump respectively.2. The manufacturing method of claim 1 , wherein a top of any of the metal side walls is higher than a top of the solder bump.3. The manufacturing method of claim 1 , further comprising:forming a plurality of metal pins protruded from the conductive layer and arranged in the solder bump.4. The manufacturing method of claim 3 , wherein a melting temperature of the metal side walls is higher than a melting temperature of the metal pins.5. The manufacturing method of claim 1 , wherein a top of any of the metal side walls is higher than a top of the solder bump. This Application is a Divisional of U.S. application Ser. No. 15/592,181, filed on May 10, 2017.The present invention relates to a combing bump structure and a manufacturing method thereof.Semiconductor devices are used in a large number of electronic devices, such as computers, cell phones, and others. Semiconductor devices comprise integrated circuits (ICs) that are formed on semiconductor wafers by depositing many types of thin films of material over the semiconductor wafers, and patterning the thin films of material to form the integrated circuits.The Redistribution Layer (RDL) process is to take the original designed IC's I/O pad and use wafer-level metal wiring process and ...

Assembly comprising hybrid interconnecting means including intermediate interconnecting elements and sintered metal joints, and manufacturing process

An assembly includes at least one first element comprising at least one first electrical bonding pad; at least one second element comprising at least one second electrical bonding pad; electrical and mechanical interconnect means, wherein the electrical and mechanical interconnect means comprise at least: at least one first intermediate metal interconnect element, on the surface of at least the first electrical bonding pad; at least one sintered joint of metal microparticles or nanoparticles stacked with the first intermediate metal interconnect element; the melting point of the first intermediate metal interconnect element being greater than the sintering temperature of the metal microparticles or nanoparticles. A method for fabricating an assembly is also provided.

低温铜-铜直接接合

低温下铜‑铜直接接合通过在衬底上电镀铜特征接着电平坦化这些铜特征而实现。在使纳米孪晶铜结构形成的条件下，将铜特征电镀在衬底上。电平坦化铜特征通过使衬底阳极偏置并使铜特征与电解液接触而将铜电化学移除来执行。该电化学移除以一定方式执行，使得粗糙度在铜特征中减小且实质的共平面性在铜特征之间实现。具有纳米孪晶铜结构、减小粗糙度、及较佳共平面性的铜特征实现低温下的铜‑铜直接接合。

Electrical interconnection structures and methods for fabricating the same

본 발명은 전기적 연결 구조 및 그 제조방법에 관한 것으로, 본딩패드를 갖는 기판, 상기 기판 상에 배치되어 상기 본딩패드를 개방하는 보호막, 상기 본딩패드와 전기적으로 연결되는 솔더볼, 상기 본딩패드 상에 배치되어 상기 솔더볼이 채워지는 내부 영역을 제공하는 솔더볼 지지막, 그리고 상기 본딩패드와 상기 솔더볼 지지막 사이에 배치되고 상기 본딩패드를 구성하는 금속에 비해 이온화경향이 작은 금속을 포함하는 금속막을 형성하는 것을 포함할 수 있다. The present invention relates to an electrical connection structure and a method of manufacturing the same, and more particularly, to an electrical connection structure and a method of manufacturing the same, which includes a substrate having a bonding pad, a protective film disposed on the substrate to open the bonding pad, a solder ball electrically connected to the bonding pad, A solder ball supporting film for providing an inner region filled with the solder ball and a metal film disposed between the bonding pad and the solder ball supporting film and including a metal having a lower ionization tendency than a metal constituting the bonding pad .

Electronic component mounting structure and manufacturing method thereof

Semiconductor devices

본 발명은 반도체 장치 및 그 제조방법에 관한 것으로, 회로패턴이 포함된 상면 및 그 반대면인 하면을 갖는 기판, 그리고 상기 기판을 관통하는 관통전극을 포함할 수 있다. 상기 관통전극은 상기 하면으로부터 돌출된 돌출부를 포함하고, 상기 하면으로부터 상기 돌출부를 향해 연장되어 상기 돌출부의 측면을 감싸는 지지부를 포함할 수 있다. The present invention relates to a semiconductor device and a method of manufacturing the same, and may include a substrate having a top surface including a circuit pattern and a bottom surface opposite to the top surface, and a penetrating electrode penetrating the substrate. The penetrating electrode may include a protruding portion protruding from the lower surface, and a supporting portion extending from the lower surface toward the protruding portion and surrounding a side surface of the protruding portion.

The interconnection structure that projection construction is constituted with it

本发明公开一种凸块结构，包括一焊盘，以及一钝化层，覆盖该接垫的周缘，其中所述钝化层包含一开口，显露出所述焊盘的部分表面区域。一第一部位，位于所述焊盘上，所述第一部位包含一上表面及一侧壁。一第二部位，覆盖在所述第一部位的上表面及其全部的侧壁上。

Protsusion forming method, semiconductor device and its mfg. method, circuit board and electronic machine

提供了一种能够以期望的宽度简单地形成凸起的凸起形成方法、半导体器件及其制造方法、电路板和电子机器。凸起的形成方法为在绝缘膜15上形成露出焊盘12的至少一部分的开口部16，形成与上述焊盘12连接的凸起，形成具有与上述焊盘12的至少一部分平面地重叠的通孔22的抗蚀层20，在上述绝缘膜15中形成开口部16，形成与通过上述开口部16露出的上述焊盘12连接的金属层。

Mounting substrate

본 발명은 접합 후에 땜납 내에 보이드가 잔존하는 것을 억제할 수 있는 땜납 접합 방법 및 땜납 접합 구조에 관한 것으로, 보이드의 발생을 유효하게 삭감하는 것을 과제로 한다. 전자 부품(25)의 참조 부호 28을 실장 기판(20)에 형성된 기판측 랜드(22)에 땜납 페이스트(23)를 이용하여 접합하는 땜납 접합 구조에서, 실장 기판(20)에 형성되는 기판측 랜드(22)에, 땜납 페이스트(23) 내의 땜납이 가열되어 용융된 상태에서, 이 용융 땜납에 흐름을 발생시키는 접합재 흐름 발생 수단을 설치한다. 이 접합재 흐름 발생 수단은, 기판측 랜드(22) 상에 땜납 페이스트(23)에 매설되도록 형성되며, 땜납에 대한 습윤성이 기판측 랜드(22)보다 낮은 금속 부재(24)에 의해 구성할 수 있다. The present invention relates to a solder joining method and a solder joint structure capable of suppressing the remaining of voids in solder after joining, and an object of the present invention is to effectively reduce the occurrence of voids. In the solder joint structure in which the reference numeral 28 of the electronic component 25 is bonded to the board-side land 22 formed on the mounting board 20 by using the solder paste 23, the board-side land formed on the mounting board 20. At 22, a bonding material flow generating means for generating a flow in the molten solder is provided in the state where the solder in the solder paste 23 is heated and melted. This bonding material flow generating means is formed on the substrate side land 22 so as to be embedded in the solder paste 23, and can be constituted by the metal member 24 having a lower wettability to the solder than the substrate side land 22. . 땜납, 보이드, 랜드, 땜납 페이스트, 습윤성, 용융, 접합재, 금속 부재, 접합 Solder, Voids, Lands, Solder Pastes, Wetability, Melting, Bonding Materials, Metal Members, Bonding

Bump structure, semiconductor package having the bump structure, and method of manufacturing the semiconductor package

범프 구조물은 제1 범프 및 제2 범프를 포함한다. 상기 제1 범프는 기판의 접속 패드 상에 배치되며, 상기 접속 패드로부터 연장하는 다수개의 나노-와이어들 및 상기 나노-와이어들의 일단부들을 연결시키는 몸체부를 갖는다. 상기 제2 범프는 상기 제1 범프의 상기 몸체부 상에 배치된다. The bump structure includes a first bump and a second bump. The first bump is disposed on a connection pad of the substrate and has a plurality of nano-wires extending from the connection pads and a body connecting the one ends of the nano-wires. The second bump is disposed on the body portion of the first bump.

Semiconductor device having bump and method of forming the same

필라 범프(pillar bump)를 갖는 반도체 소자에 관한 것이다. 기판 상에 도전성 패드가 형성된다. 상기 도전성 패드 상에 필라(pillar)가 형성된다. 상기 필라 상에 금속간 화합물 층(IMC layer)이 형성된다. 상기 금속간 화합물 층 상에 솔더 층이 형성된다. 상기 필라는 상기 금속간 화합물 층보다 좁은 폭을 갖는다. It relates to a semiconductor device having a pillar bump. A conductive pad is formed on the substrate. A pillar is formed on the conductive pad. An intermetallic compound layer (IMC layer) is formed on the pillar. A solder layer is formed on the intermetallic compound layer. The pillar has a narrower width than the intermetallic layer.

Semiconductor device

본 발명의 과제는 반도체 장치의 신뢰성을 향상시킬 수 있는 기술을 제공한다. 본 발명에서는, 반도체 칩을 탑재하는 배선 기판으로서, 빌드업 기판을 사용하지 않고, 관통 기판(THWB)을 사용한다. 이에 의해, 본 발명에서는, 코어층만으로 이루어지는 관통 기판을 사용함으로써, 빌드업층과 코어층과의 열 팽창 계수의 상위를 고려할 필요가 없고, 게다가 빌드업층이 존재하지 않으므로, 빌드업층에 형성되는 미세한 비아의 전기적인 절단도 고려할 필요가 없게 된다. 이 결과, 본 발명에 따르면, 비용 저감을 도모하면서, 반도체 장치의 신뢰성 향상을 도모할 수 있다. The present invention provides a technique for improving the reliability of a semiconductor device. In the present invention, as a wiring substrate on which a semiconductor chip is mounted, a penetrating substrate (THWB) is used without using a build-up substrate. Thus, in the present invention, it is not necessary to consider the difference in the coefficient of thermal expansion between the buildup layer and the core layer by using the penetrating substrate composed of only the core layer. Further, since there is no buildup layer, It is not necessary to consider the electrical cutoff of the semiconductor device. As a result, according to the present invention, it is possible to improve the reliability of the semiconductor device while reducing the cost.

Semiconductor device and manufacturing method of semiconductor device

公开一种半导体装置及半导体装置的制造方法。根据实施例，设置半导体基板、金属膜、表面改性层和再布线。半导体基板上形成了布线及焊盘电极。金属膜在所述半导体基板上形成。表面改性层在所述金属膜的表层形成，提高与光刻胶图形的贴紧性。再布线隔着所述表面改性层在所述金属膜上形成。

Semiconductor devices

반도체 장치, 반도체 패키지 및 이들의 제조 방법을 제공한다. 반도체 기판과 상기 반도체 기판 상에 형성된 전극 패드 및 상기 전극 패드 상에 형성된 접합구조물을 포함한다. 상기 패드 표면에 대해 수직으로 돌기가 신장되어 있다. 상기 돌기는 상기 접합구조물 내부로 신장될 수 있고, 상기 돌기 내부에는 전도성 액체가 채워질 수 있다. 상기 구조물이 형성된 반도체 기판은 접합 패드가 형성된 회로 기판에 결합되어 반도체 패키지가 구성된다. 상기 돌기는 솔더 볼에 크랙이 발생되거나 진행되는 것을 억제하고, 돌기 내의 전도성 액체에 의해 크랙이 패치될 수 있다. A semiconductor device, a semiconductor package, and a manufacturing method thereof are provided. The semiconductor substrate includes an electrode pad formed on the semiconductor substrate, and a junction structure formed on the electrode pad. The protrusion extends perpendicular to the pad surface. The protrusion may extend into the junction structure, and the protrusion may be filled with a conductive liquid. The semiconductor substrate on which the structure is formed is coupled to a circuit board on which a bonding pad is formed to form a semiconductor package. The protrusions suppress cracks or progression in the solder ball, and the cracks may be patched by the conductive liquid in the protrusions. 반도체칩, 패키지, 돌기 Semiconductor Chip, Package, Projection

Structure for microelectronic packaging with bond elements to encapsulation surface

A structure may include bond elements having bases joined to conductive elements at a first portion of a first surface and end surfaces remote from the substrate. A dielectric encapsulation element may overlie and extend from the first portion and fill spaces between the bond elements to separate the bond elements from one another. The encapsulation element has a third surface facing away from the first surface. Unencapsulated portions of the bond elements are defined by at least portions of the end surfaces uncovered by the encapsulation element at the third surface. The encapsulation element at least partially defines a second portion of the first surface that is other than the first portion and has an area sized to accommodate an entire area of a microelectronic element. Some conductive elements are at the second portion and configured for connection with such microelectronic element.

Wire bond wires for interference shielding

Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

Conductive bump, method for producing the same, and electronic component mounted structure

본 발명은 전자 부품의 전극면에 형성된 도전성 범프로서, 도전성 범프가, 상이한 도전 필러 함유율을 갖는 복수의 감광성 수지층으로 이루어지는 구성을 갖는다. 이에 의해, 전극과 도전성 범프의 접착 강도의 향상과 접속 저항의 저감이라는 상반되는 기능을 구비한 도전성 범프를 실현할 수 있다. This invention is a conductive bump formed in the electrode surface of an electronic component, Comprising: A conductive bump has the structure which consists of several photosensitive resin layer which has a different conductive filler content rate. Thereby, the conductive bump with the opposite function of the improvement of the adhesive strength of an electrode and a conductive bump, and reduction of connection resistance can be implement | achieved.

Substrate for semiconductor package, and semiconductor package having the substrate

반도체 패키지용 기판 및 이를 갖는 반도체 패키지가 개시되어 있다. 반도체 패키지는 제1 면 및 상기 제1 면과 대향 하는 제2 면을 갖는 기판, 상기 제1 면 및 상기 제2 면을 관통하는 제1 관통 전극, 상기 제1 면 상에 배치된 블록 형상의 절연 부재 및 상기 절연 부재 내에 배치되며 상기 제1 관통 전극과 전기적으로 연결된 제1 도전부 및 상기 제1 도전부와 전기적으로 연결되며 상기 절연 부재의 양쪽 측면들로부터 노출된 제2 도전부를 갖는 연결 부재를 포함하는 기판 몸체 및 상기 기판 몸체의 상기 제1 면 상에 상기 제1 면에 대하여 수직 하게 배치되며 상호 대향 하는 제3 및 제4 면들, 상기 제3 면 및 상기 제4 면을 관통하며 상기 절연 부재의 측면으로부터 노출된 상기 제2 도전부와 전기적으로 연결된 제2 관통 전극을 갖는 반도체 칩을 포함한다. A substrate for a semiconductor package and a semiconductor package having the same are disclosed. The semiconductor package includes a substrate having a first surface and a second surface facing the first surface, a first through electrode penetrating through the first surface and the second surface, and a block-shaped insulation disposed on the first surface. A connecting member having a first conductive portion disposed in the member and the insulating member and electrically connected to the first through electrode, and a second conductive portion electrically connected to the first conductive portion and exposed from both sides of the insulating member. A substrate body and a third and fourth surfaces disposed perpendicular to the first surface on the first surface of the substrate body and facing each other, and penetrating the third and fourth surfaces, and the insulating member. And a semiconductor chip having a second through electrode electrically connected to the second conductive portion exposed from the side surface of the semiconductor chip.

Bump structure and semiconductor package having the bump structure

本发明提供了一种包括第一凸起和第二凸起的凸起结构、一种包括该凸起结构的半导体封装件和一种制造该半导体封装件的方法。所述凸起结构包括：第一凸起，设置在基底的连接焊盘上，所述第一凸起包括从所述连接焊盘延伸的多条纳米线和连接所述多条纳米线的端部的主体；第二凸起，设置在所述第一凸起的所述主体上。

Packaging through pre-formed metal pins

一种封装件包括第一封装组件和第二封装组件。第一封装组件包括位于第一封装组件的表面处的第一电连接件以及位于第一电连接件的表面上的第一焊料区域。第二封装组件包括位于第二封装组件的表面处的第二电连接件以及位于第二电连接件的表面上的第二焊料区域。金属引脚具有接合至第一焊料区域的第一末端和接合至第二焊料区域的第二末端。本发明的也提供了通过预形成的金属引脚的封装。

Semicondcutor package having lateral bump bonding structure

본 발명은 반도체 패키지를 제공할 수 있다. 반도체 패키지는 복수의 본드핑거들이 배열된 일면, 상기 일면에 대향하며 복수의 볼랜드들이 배열된 타면, 및 상기 본드핑거들 상에 각각 형성된 단자들을 갖는 기판을 포함할 수 있다. 반도체 패키지는 기판의 일면 상부에 배치되며, 상기 일면과 마주하고 복수의 본딩패드들이 배열된 활성면 및 상기 활성면에 대향하는 후면을 갖는 반도체칩을 포함할 수 있다. 반도체 패키지는 반도체칩의 본딩패드들 상에 각각 형성되며, 고융점 금속 필라 및 상기 고융점 금속 필라의 일 측면 상에 형성되고 상기 기판의 단자와 접합된 저융점 금속층을 포함하는 범프들을 포함할 수 있다.

Semiconductor structure and manufacturing method of semiconductor device

本发明揭示一种半导体结构及半导体装置的制造方法，所述半导体结构具有T型立柱(post)。T型立柱具有底层凸块金属化(under bump metallization，UBM)部及延伸自UBM部的一柱体部。UBM部及柱体部可由相同或不同的材料所构成。在一实施例中，一基底，例如芯片、晶片、印刷电路板、封装基底等等，具有T型立柱且与另一基底(例如，芯片、晶片、印刷电路板、封装基底等等)的接触窗接合。T型立柱可具有一焊料预先形成于柱体部上，使柱体部露出来或使焊料覆盖柱体部。在另一实施例中，T型立柱可形成于一基底上，而焊料则形成于另一基底上。本发明能够维持半导体装置的结构完整性，防止在凸块电极/立柱与焊球/凸块之间的接垫区域内形成裂缝。

Solder bump having cored structure and production method therefor

유심 구조 땜납 범프 및 그 제조 방법을 제공한다. 땜납 범프의 제조에 있어서, 미리, 범프의 중심 부분에 심용 페이스트를 인쇄 도포하고, 땜납 금속의 리플로우 처리 온도 근방 또는 그 이하에 이하의 온도에서 심용 페이스트를 소결함으로써 소결심을 형성하고, 이어서, 이 소결심의 주위에 땜납 금속을 인쇄법으로 도포하고, 이 땜납 금속을 리플로우 처리함으로써, 땜납 범프의 내부에, 수직인 방향으로 연장되는 소결심이 형성된 유심 구조 땜납 범프를 얻는다. A cored structure solder bump and a method of manufacturing the same are provided. In the production of the solder bump, a sintered core is formed by previously applying a core paste to the central portion of the bump and sintering the core paste at a temperature below or below the reflow treatment temperature of the solder metal, and then, By applying a solder metal around the sintered core by a printing method and reflowing the solder metal, a cored structure solder bump having a sintered core extending in a vertical direction is formed inside the solder bump.

Semiconductor device mounting method, semiconductor device mounting structure, electro-optical device, electro-optical device manufacturing method, and electronic apparatus

Electronic component mounting structure and method for manufacturing the same

복수의 전극 단자(10a)를 설치한 전자 부품(10)과, 전극 단자(10a)에 대향하는 위치에 접속 단자(12a)를 설치한 실장 기판(12)과, 전극 단자(10a) 상 또는 접속 단자(12a) 상에 설치한 돌기 전극(13)을 개재하여 전극 단자(10a)와 접속 단자(12a)를 접속하는 전자 부품 실장 구조체(1)로서, 돌기 전극(13)은, 적어도 도전성 필러(13a)와 감광성 수지(13b)를 포함하고, 감광성 수지(13b)의 수지 성분 가교 밀도가 돌기 전극(13)의 높이 방향으로 상이한 것을 특징으로 한다. On the electronic component 10 provided with the some electrode terminal 10a, the mounting board 12 which provided the connection terminal 12a in the position which opposes the electrode terminal 10a, and the electrode terminal 10a, or are connected. As the electronic component mounting structure 1 which connects the electrode terminal 10a and the connection terminal 12a via the projection electrode 13 provided on the terminal 12a, the projection electrode 13 is at least a conductive filler ( 13a) and photosensitive resin 13b, characterized in that the resin component crosslinking density of the photosensitive resin 13b is different in the height direction of the protruding electrode 13.

Electronic component, electronic apparatus including the same, and manufacturing method of the electronic apparatus

전자 부품간을 높은 신뢰성으로 접합한다. 전자 부품(1A)은, 전극부(21)와, 그 위에 형성된 땜납(22)을 구비한다. 전극부(21)는, 그 상면에 땜납(22)의 성분에 대한 확산 계수가 상이한 도전부, 예를 들면 배리어 메탈(21b)과 그 위에 형성된 돌기(21c)를 갖는다. 땜납(22)은, 전극부(21)의 배리어 메탈(21b)과 돌기(21c) 위에 형성된다. 상대측 부품과의 접합 시에는, 돌기(21c)에서 우선적으로 땜납(22)의 성분의 확산 및 반응이 발생하여, 전극부(21)의 상면으로부터 측면으로의 땜납(22)의 성분의 확산이 억제되어, 부품간의 접합부의 파단이 억제된다. Thereby bonding the electronic parts with high reliability. The electronic component 1A includes an electrode portion 21 and a solder 22 formed thereon. The electrode portion 21 has a conductive portion, for example, a barrier metal 21b and a projection 21c formed thereon, on the upper surface thereof, the diffusion coefficient of which differs from that of the component of the solder 22. The solder 22 is formed on the barrier metal 21b and the projection 21c of the electrode portion 21. [ Diffusion and reaction of the components of the solder 22 preferentially take place in the protrusions 21c and the diffusion of components of the solder 22 from the upper surface to the side surface of the electrode portion 21 is suppressed So that breakage of the joint portion between the parts is suppressed.

Semiconductor package

A semiconductor package includes a semiconductor chip having at least one chip pad disposed on one surface thereof; a wiring pattern disposed on top of the semiconductor chip and having at least a portion thereof in contact with the chip pad to be electrically connected to the chip pad; and a solder bump disposed on outer surface of the wiring pattern to be electrically connected to the chip pad through the wiring pattern.

ASSEMBLING A CHIP OF INTEGRATED CIRCUITS AND A PLATE

L'invention concerne un assemblage d'une puce (3) de circuits intégrés et d'une plaque (5), dans lequel au moins un canal (15) disposé entre la puce et la plaque s'étend d'un bord à un autre bord de la plus petite de la puce ou de la plaque, et est délimité par des parois latérales métalliques (17) s'étendant au moins partiellement d'une face de la puce à une face en regard de la plaque.

Semiconductor package and method of manufacturing the same

A semiconductor package is disclosed that includes a semiconductor device; a circuit board; and a connection mechanism including a first conductive terminal provided on the semiconductor device, and a second conductive terminal provided on the circuit board side, the connection mechanism electrically connecting the semiconductor device and the circuit board via the first conductive terminal and the second conductive terminal. At least one of the first conductive terminal and the second conductive terminal of the connection mechanism includes one or more carbon nanotubes each having one end thereof fixed to the surface of the at least one of the first conductive terminal and the second conductive terminal, and extending in a direction away from the surface. The first conductive terminal and the second conductive terminal engage each other through the carbon nanotubes.

FLIP-CHIP HYBRIDIZATION OF MICROELECTRONIC COMPONENTS BY LOCAL HEATING OF CONNECTION ELEMENTS

Un procédé de réalisation d'un dispositif hybridé consiste : * à réaliser un premier composant (10) muni de billes métalliques (14), et un second composant (12) muni d'éléments de connexion (40, 42); * fixer les billes (14) avec les éléments de connexion (40, 42). * La fabrication du second composant (12) comporte : * la réalisation, sur une face d'un substrat, d'éléments résistifs (24) aux emplacements prévus pour les éléments de connexion (40, 42) ; * le dépôt d'une couche d'un isolant électrique (34) sur les éléments résistifs (24) ; et * la réalisation des éléments de connexion (40, 42) ; En outre, la fixation des billes (14) avec les éléments de connexion (40, 42) comporte l'application d'un courant électrique au travers des éléments résistifs (24) de manière à échauffer les billes (14). A method of producing a hybrid device consists of: producing a first component (10) provided with metal balls (14), and a second component (12) provided with connection elements (40, 42); * fix the balls (14) with the connection elements (40, 42). * The manufacture of the second component (12) comprises: * the realization, on a face of a substrate, of resistive elements (24) at the locations provided for the connection elements (40, 42); depositing a layer of an electrical insulator (34) on the resistive elements (24); and * providing the connection elements (40,42); In addition, the fixing of the balls (14) with the connecting elements (40, 42) comprises the application of an electric current through the resistive elements (24) so as to heat the balls (14).

Semiconductor device

본 발명의 과제는 반도체 장치의 신뢰성을 향상시킬 수 있는 기술을 제공한다. 본 발명에서는, 반도체 칩을 탑재하는 배선 기판으로서, 빌드업 기판을 사용하지 않고, 관통 기판(THWB)을 사용한다. 이에 의해, 본 발명에서는, 코어층만으로 이루어지는 관통 기판을 사용함으로써, 빌드업층과 코어층과의 열 팽창 계수의 상위를 고려할 필요가 없고, 게다가 빌드업층이 존재하지 않으므로, 빌드업층에 형성되는 미세한 비아의 전기적인 절단도 고려할 필요가 없게 된다. 이 결과, 본 발명에 따르면, 비용 저감을 도모하면서, 반도체 장치의 신뢰성 향상을 도모할 수 있다. The present invention provides a technique for improving the reliability of a semiconductor device. In the present invention, as a wiring substrate on which a semiconductor chip is mounted, a penetrating substrate (THWB) is used without using a build-up substrate. Thus, in the present invention, it is not necessary to consider the difference in the coefficient of thermal expansion between the buildup layer and the core layer by using the penetrating substrate composed of only the core layer. Further, since there is no buildup layer, It is not necessary to consider the electrical cutoff of the semiconductor device. As a result, according to the present invention, it is possible to improve the reliability of the semiconductor device while reducing the cost.

MICROELECTRONIC INTERCONNECTION DEVICE WITH LOCALIZED CONDUCTIVE RODS

ASSEMBLY COMPRISING MIXED INTERCONNECT MEANS COMPRISING INTERMEDIATE INTERCONNECTION ELEMENTS AND METAL SINTERED JOINTS AND METHOD OF MANUFACTURE

INTERCOMPONENT CONNECTION PROCESS WITH OPTIMIZED DENSITY

L'invention concerne un procédé de connexion électrique par hybridation d'un premier composant (100) à un deuxième composant (200). Le procédé comportant les étapes suivantes : formation de plots en matériau ductile (111, 121) en contact respectif des zones de connexion (110, 120) du premier composant (100) ; formation d'inserts (211, 221) en matériau conducteur en contact de des zones de connexion (210, 220) du deuxième composant (200) ; formation de barrières d'hybridation (212, 222) disposées entre les inserts (211, 221) et isolées électriquement l'une de l'autre, lesdites première et deuxième barrière d'hybridation (212, 222) pour faire office de barrière en contenant la déformation des plots en matériau ductile (111, 121) lors de la connexion des zones de connexion (210, 220) du premier composant (100) avec celles du deuxième composant (200). L'invention concerne en outre un ensemble (1) de deux composants (100, 200) connectés The invention relates to a method of electrically connecting by hybridizing a first component (100) to a second component (200). The method comprising the following steps: forming pads of ductile material (111, 121) in respective contact with the connection zones (110, 120) of the first component (100); forming inserts (211, 221) of conductive material in contact with connection areas (210, 220) of the second component (200); formation of hybridization barriers (212, 222) disposed between the inserts (211, 221) and electrically isolated from each other, said first and second hybridization barrier (212, 222) to act as a barrier in containing the deformation of the pads of ductile material (111, 121) during the connection of the connection zones (210, 220) of the first component (100) with those of the second component (200). The invention further relates to an assembly (1) of two components (100, 200) connected

ASSEMBLY COMPRISING MIXED INTERCONNECT MEANS COMPRISING INTERMEDIATE INTERCONNECTION ELEMENTS AND METAL SINTERED JOINTS AND METHOD FOR MANUFACTURING THE SAME

L'invention a pour objet un assemblage comprenant : - au moins un premier élément (100) comprenant au moins un premier plot de connexion électrique (12) ; - au moins un second élément (200) comprenant au moins un second plot de connexion électrique (21) ; - des moyens d'interconnexion électrique et mécanique, caractérisé en ce que lesdits moyens d'interconnexion électrique et mécanique comprennent au moins : - au moins un premier élément intermédiaire métallique d'interconnexion (13), à la surface d'au moins le premier plot de connexion électrique ; - au moins un joint fritté de microparticules ou de nanoparticules métalliques empilé avec ledit premier élément intermédiaire d'interconnexion ; - la température de fusion dudit premier élément intermédiaire d'interconnexion étant supérieure à la température de frittage desdites microparticules ou de nanoparticules métalliques. L'invention a aussi pour objet un procédé de fabrication d'un assemblage de l'invention The invention relates to an assembly comprising: - at least one first element (100) comprising at least a first electrical connection pad (12); at least one second element (200) comprising at least one second electrical connection pad (21); electrical and mechanical interconnection means, characterized in that said electrical and mechanical interconnection means comprise at least: at least one first metallic intermediate interconnection element (13), on the surface of at least the first electrical connection pad; at least one sintered gasket of microparticles or metal nanoparticles stacked with said first intermediate interconnection element; - The melting temperature of said first intermediate interconnect element being greater than the sintering temperature of said microparticles or metal nanoparticles. The invention also relates to a method for manufacturing an assembly of the invention

METHOD FOR MANUFACTURING TWO SUBSTRATES CONNECTED BY AT LEAST ONE MECHANICAL AND ELECTRICALLY CONDUCTIVE CONNECTION OBTAINED

A first substrate provided with a receiving area made from a first metallic material is supplied. A second substrate provided with an insertion area comprising a base surface and at least two bumps made from a second metallic material is arranged facing the first substrate. The bumps are salient from the base surface. A pressure is applied between the first substrate and the second substrate so as to make the bumps penetrate into the receiving area. The first metallic material reacts with the second metallic material so as to form a continuous layer of an intermetallic compound having a base formed by the first and second metallic materials along the interface between the bumps and the receiving area.

A method of self-aligned connection of a structure to a support, device obtained from such a method, and the structure and support implemented by such a method

L’invention concerne un procédé de connexion par hybridation d’une structure semiconductrice (100) sur un support (200). Le procédé comprend les étapes de : fourniture d’une structure semiconductrice (100) comprenant au moins un deux organes primaires de connexion comprenant chacun un premier élément d’alignement magnétique (122, 126) comprenant un matériau ferromagnétique ; fourniture du support (200), le support (200) comprenant au moins deux organes secondaires de connexion (221, 225) comprenant chacun un deuxième élément d’alignement magnétique (222, 226) comprenant un matériau ferromagnétique, au moins les uns parmi les premier élément d’alignement magnétique (122, 126) et le deuxièmes éléments d’alignement magnétique (222, 226) sont des aimants permanents ; et le placement et libération de la structure semiconductrice (100) à distance du support (200) pour obtenir un alignement des premiers éléments d’alignement magnétique (122, 126) avec les deuxièmes éléments d’alignement magnétique (222, 226) correspondant. Figure pour l’abrégé : figure 1C The invention relates to a method of connection by hybridization of a semiconductor structure (100) on a support (200). The method includes the steps of: providing a semiconductor structure (100) comprising at least one of two primary connection members each comprising a first magnetic alignment element (122, 126) comprising a ferromagnetic material; provision of the support (200), the support (200) comprising at least two secondary connection members (221, 225) each comprising a second magnetic alignment element (222, 226) comprising a ferromagnetic material, at least one of first magnetic alignment element (122, 126) and second magnetic alignment element (222, 226) are permanent magnets; and placing and releasing the semiconductor structure (100) away from the support (200) to obtain alignment of the first magnetic alignment elements (122, 126) with the corresponding second magnetic alignment elements (222, 226). Figure ...

STACKED ELECTRONIC DEVICE AND METHOD FOR PRODUCING SUCH AN ELECTRONIC DEVICE

Semiconductor structure and manufacturing method thereof

本发明公开一种半导体结构及其制作方法，该半导体结构包含一第一基板，包含一第一接触结构位于一第一接垫上，其中所述第一接触结构包含被一第一纳米双晶金属涂层覆盖的一第一金属基层；以及一第二基板，包含一第二接触结构位于一第二接垫上，其中，所述第二接触结构包含在所述第二接垫上的一第二纳米双晶金属涂层，其中，所述第一接触结构与所述第二接触结构连接，从而在所述第一纳米双晶金属涂层和所述第二纳米双晶金属涂层之间构成一键合界面。

Packaged semiconductor device with a particle roughened surface

A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame. A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame and with a reflow wall that surrounds a portion of the solder joint that couples the semiconductor device to the lead frame. A packaged semiconductor device with a reflow wall that surrounds a portion of a solder joint that couples a semiconductor device to a lead frame.

Multi-component integrated circuit contacts

An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a spike that has a portion of its body fixed in a layer of an integrated circuit structure and extends outwardly from the integrated circuit structure. The second material is adapted to form a mechanical connection to a further electrical device. The second material (e.g., solder), is held by the first member to the integrated circuit structure. The first member increases the strength of the connection and assists in controlling the collapse of second member to form the mechanical connection to another circuit. The connection is formed by coating the integrated circuit structure with a patterned resist and etching the layer beneath the resist. A first member material (e.g., metal) is deposited. The resist is removed. The collapsible material is fixed to the first member.

Mounting board

Packaging through pre-formed metal pins

A package includes first package component and a second package component. The first package component includes a first electrical connector at a surface of the first package component, and a first solder region on a surface of the first electrical connector. The second package component includes a second electrical connector at a surface of the second package component, and a second solder region on a surface of the second electrical connector. A metal pin has a first end bonded to the first solder region, and a second end bonded to the second solder region.

Extrusion-resistant solder interconnect structures and methods of forming

Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, a method can include: providing a precursor interconnect structure having: a photosensitive polyimide (PSPI) layer; a controlled collapse chip connection (C4) bump overlying the PSPI layer; and a solder overlying the C4 bump and contacting a side of the C4 bump. The method can further include recessing a portion of the PSPI layer adjacent to the C4 bump to form a PSPI pedestal under the C4 bump. The method can additionally include forming an underfill abutting the PSPI pedestal and the C4 bump, wherein the underfill and the solder form an interface separated from the PSPI pedestal.