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20-04-2017 дата публикации

HIGH PERFORMANCE INTERCONNECT

Номер: US20170109315A1

Автор: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert H. Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta, SAFRANEK ROBERT J, BLANKENSHIP ROBERT G, IYER VENKATRAMAN, WILLEY JEFF, BEERS ROBERT H, JUE DARREN S, KUMAR ARVIND A, SHARMA DEBENDRA DAS, SWANSON JEFFREY C, FAHIM BAHAA, GEETHA VEDARAMAN, SPINK AARON T, SPAGNA FULVIO, SHAH RAHUL R, IYER SITARAMAN V, NALE WILLIAM HARRY, DAS ABHISHEK, JOHNSON SIMON P, DHILLON YUVRAJ S, LIU YEN-CHENG, RAMANUJAN RAJ K, MADDOX ROBERT A, HUM HERBERT H, GUPTA ASHISH, Safranek Robert J., Blankenship Robert G., Iyer Venkatraman, Willey Jeff, Beers Robert H., Jue Darren S., Kumar Arvind A., Sharma Debendra Das, Swanson Jeffrey C., Fahim Bahaa, Geetha Vedaraman, Spink Aaron T., Spagna Fulvio, Shah Rahul R., Iyer Sitaraman V., Nale William Harry, Das Abhishek, Johnson Simon P., Dhillon Yuvraj S., Liu Yen-Cheng, Ramanujan Raj K., Maddox Robert A., Hum Herbert H., Gupta Ashish

Принадлежит: Intel Corporation

A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state. 13-. (canceled)4. A processor device comprising:link layer logic to generate a link layer flow control unit (flit) comprising three slots, wherein each slot is adapted to be encoded with a separate packet header, and a particular one of the slots is designated to be alternatively encoded with a link layer credit message,wherein the link layer credit message comprises an opcode field to identify that the particular slot is encoded with a link layer credit message, a credit type field to indicate a type of credit refund included in the link layer credit message, a credit return field to indicate a number of credits to be refunded based on the link layer credit message, and at least one acknowledgement field,wherein format of a payload of the link layer credit message is based on the type of credit refund.5. The processor device of claim 4 , further comprising physical layer logic to send a plurality of phits on a physical link to transmit the flit claim 4 , wherein the phits each comprise a quantum of data to be sent in a single unit interval.6. The processor device of claim 5 , wherein the physical layer logic is to train the physical link according to a link training state machine.7. The processor device of claim 6 , wherein the link training state machine defines a plurality of states.8. The ...

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