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Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 79. Отображено 79.
04-11-2021 дата публикации

UNDERFILL FLOW MANAGEMENT IN ELECTRONIC ASSEMBLIES

Номер: US20210343677A1
Автор: Frederick W. Atadana, Taylor William Gaines, Edvin Cetegen, Wei Li, Hsin-Yu Li, Tony Dambrauskas
Принадлежит: Intel Corporation

Disclosed herein are structures and techniques for underfill flow management in electronic assemblies. For example, in some embodiments, an electronic assembly may include a first component, a second component, an underfill on the first component and at least partially between the first component and the second component, and a material at a surface of the first component, wherein the material is outside a footprint of the second component, and the underfill contacts the material with a contact angle greater than 50 degrees.

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Номер записи: 1
15-11-2022 дата публикации

Dual strip backside metallization for improved alt-FLI plating, KOZ minimization, test enhancement and warpage control

Номер: US0011502008B2
Автор: Nicholas S. Haehn, Edvin Cetegen, Shankar Devasenathipathy
Принадлежит: Intel Corporation

An integrated circuit assembly including a substrate having a surface including at least one area including contact points operable for connection with an integrated circuit die; and at least one ring surrounding the at least one area, the at least one ring including an electrically conductive material. A method of forming an integrated circuit assembly including forming a plurality of electrically conductive rings around a periphery of a die area of a substrate selected for attachment of at least one integrated circuit die, wherein the plurality of rings are formed one inside the other; and forming a plurality of contact points in the die area.

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Номер записи: 2
23-06-2022 дата публикации

MICROELECTRONIC STRUCTURES INCLUDING BRIDGES

Номер: US20220199536A1
Автор: Omkar G. Karhade, Edvin Cetegen, Anurag Tripathi, Nitin A. Deshpande
Принадлежит:

Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

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Номер записи: 3
01-01-2015 дата публикации

UNDERFILL MATERIAL FLOW CONTROL FOR REDUCED DIE-TO-DIE SPACING IN SEMICONDUCTOR PACKAGES

Номер: US20150001717A1
Автор: Omkar G. Karhade, Nitin A. Deshpande, Rajendra C. Dias, Edvin Cetegen, Lars D. Skoglund, KARHADE OMKAR G, DESHPANDE NITIN A, DIAS RAJENDRA C, CETEGEN EDVIN, SKOGLUND LARS D, KARHADE OMKAR G., DESHPANDE NITIN A., DIAS RAJENDRA C., SKOGLUND LARS D.
Принадлежит:

Underfill material flow control for reduced die-to-die spacing in semiconductor packages and the resulting semiconductor packages are described. In an example, a semiconductor apparatus includes first and second semiconductor dies, each having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a common semiconductor package substrate by a plurality of conductive contacts, the first and second semiconductor dies separated by a spacing. A barrier structure is disposed between the first semiconductor die and the common semiconductor package substrate and at least partially underneath the first semiconductor die. An underfill material layer is in contact with the second semiconductor die and with the barrier structure, but not in contact with the first semiconductor die. 1. A semiconductor apparatus , comprising:first and second semiconductor dies, each having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a common semiconductor package substrate by a plurality of conductive contacts, the first and second semiconductor dies separated by a spacing;a barrier structure disposed between the first semiconductor die and the common semiconductor package substrate and at least partially underneath the first semiconductor die; andan underfill material layer in contact with the second semiconductor die and with the barrier structure, but not in contact with the first semiconductor die.2. The semiconductor apparatus of claim 1 , wherein the barrier structure comprises a plurality of copper traces disposed on an uppermost surface of the common semiconductor package substrate.3. The semiconductor apparatus of claim 2 , wherein the plurality of copper traces comprises a chevron pattern.4. The semiconductor apparatus of claim 1 , wherein the barrier structure comprises a patterned ink structure disposed on an uppermost surface of the common semiconductor package ...

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Номер записи: 4
04-10-2022 дата публикации

Conformable heat sink interface with a high thermal conductivity

Номер: US0011464139B2
Автор: Kelly Lofgreen, Joseph Petrini, Todd Coons, Christopher Wade Ackerman, Edvin Cetegen, Yang Jiao, Michael Rutigliano, Kuang Liu
Принадлежит: Intel Corporation

A conformable heat sink interface for an integrated circuit package comprises a mounting plate having a first surface and a deformable membrane having a portion bonded to a second surface of the plate. A cavity is between the second surface of the plate and the deformable membrane. A flowable heat transfer medium is within the cavity. The flowable heat transfer medium has a thermal conductivity of not less than 30 W/m K. The deformable membrane is to conform to a three-dimensional shape of an IC package and the mounting plate has a second surface that is to be adjacent to a heat sink base.

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Номер записи: 5
27-08-2020 дата публикации

COUPLED COOLING FINS IN ULTRA-SMALL SYSTEMS

Номер: US20200273772A1
Автор: Aastha Uppal, Omkar Karhade, Ram Viswanath, Je-Young Chang, Weihua Tang, Nitin Deshpande, Mitul Modi, Edvin Cetegen, Sanka Ganesan, Yiqun Bai, Jan Krajniak, Kumar Singh, UPPAL AASTHA, KARHADE OMKAR, VISWANATH RAM, CHANG JE-YOUNG, TANG WEIHUA, DESHPANDE NITIN, MODI MITUL, CETEGEN EDVIN, GANESAN SANKA, BAI YIQUN, KRAJNIAK JAN, SINGH KUMAR, Uppal, Aastha, Karhade, Omkar, Viswanath, Ram, Chang, Je-Young, Tang, Weihua, Deshpande, Nitin, Modi, Mitul, Cetegen, Edvin, Ganesan, Sanka, Bai, Yiqun, Krajniak, Jan, Singh, Kumar
Принадлежит: Intel Corporation

An apparatus is provided which comprises: a package substrate, an integrated circuit device coupled to a surface of the package substrate, a first material on the surface of the package substrate, the first material contacting one or more lateral sides of the integrated circuit device, the first material extending at least to a surface of the integrated circuit device opposite the package substrate, two or more separate fins over a surface of the integrated circuit device, the two or more fins comprising a second material having a different composition than the first material, and a third material having a different composition than the second material, the third material over the surface of the integrated circuit device and between the two or more fins. Other embodiments are also disclosed and claimed.

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Номер записи: 6
28-01-2021 дата публикации

VARIABLE-THICKNESS INTEGRATED HEAT SPREADER (IHS)

Номер: US20210028084A1
Автор: Sergio Antonio Chan Arguedas, Edvin Cetegen, Baris Bicen, Aravindha R. Antoniswamy, CHAN ARGUEDAS SERGIO ANTONIO, CETEGEN EDVIN, BICEN BARIS, ANTONISWAMY ARAVINDHA R, Chan Arguedas, Sergio Antonio, Cetegen, Edvin, Bicen, Baris, Antoniswamy, Aravindha R.
Принадлежит: Intel Corporation

Embodiments may relate to a microelectronic package that includes a die, a thermal interface material (TIM) coupled with the die, and an integrated heat spreader (IHS) coupled with the TIM. The IHS may include a feature with a non-uniform cross-sectional profile that includes a thin point and a thick point as measured in a direction perpendicular to a face of the die to which the TIM is coupled. Other embodiments may be described or claimed.

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Номер записи: 7
12-08-2021 дата публикации

BARRIER STRUCTURES FOR UNDERFILL CONTAINMENT

Номер: US20210249322A1
Автор: Ziyin Lin, Vipul Mehta, Wei Li, Edvin Cetegen, Xavier Brun, Yang Guo, Soud Choudhury, Shan Zhong, Christopher Rumer, Nai-Yuan Liu, Ifeanyi Okafor, Hsin-Wei Wang
Принадлежит: Intel Corporation

An integrated circuit assembly may be formed comprising an electronic substrate, a first and second integrated circuit device each having a first surface, a second surface, at least one side extending between the first and second surface, and an edge defined at an intersection of the second surface and the at least one side of each respective integrated circuit device, wherein the first surface of each integrated circuit device is electrically attached to the electronic substrate, an underfill material between the first surface of each integrated circuit device and the electronic substrate, and between the sides of the first and second integrated circuit devices, and at least one barrier structure adjacent at least one of the edge of first integrated circuit device and the edge of the second integrated circuit device, wherein the underfill material abuts the at least one barrier structure. 1. An integrated circuit structure , comprising:an integrated circuit device having a first surface, an opposing second surface, at least one side extending between the first surface and the second surface, and an edge defined at an intersection of the second surface and the at least one side of the integrated circuit device; andat least one barrier structure adjacent to the edge of the integrated circuit device.2. The integrated circuit structure of claim 1 , wherein the at least one barrier structure comprises at least one hydrophobic material layer.3. The integrated circuit structure of claim 1 , wherein the at least one barrier structure comprises at least one trench formed in the integrated circuit device.4. The integrated circuit structure of claim 1 , wherein the at least one barrier structure is on the at least one side of the integrated circuit device.5. The integrated circuit structure of claim 1 , wherein the at least one barrier structure is on the second surface of the integrated circuit device.6. An integrated circuit assembly claim 1 , comprising:an electronic ...

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Номер записи: 8
14-05-2019 дата публикации

Thermal interfaces for integrated circuit packages

Номер: US0010290561B2
Автор: Edvin Cetegen, Omkar G. Karhade, Kedar Dhane, Chandra M. Jha, CETEGEN EDVIN, KARHADE OMKAR G, DHANE KEDAR, JHA CHANDRA M, Cetegen, Edvin, Karhade, Omkar G., Dhane, Kedar, Jha, Chandra M.
Принадлежит: Intel Corporation, INTEL CORP

A thermal interface may include a wired network made of a first TIM, and a second TIM surrounding the wired network. A heat spreader lid may include a wired network attached to an inner surface of the heat spreader lid. An IC package may include a heat spreader lid placed over a first electronic component and a second electronic component. A first thermal interface may be formed between the first electronic component and the inner surface of the heat spreader lid, and a second thermal interface may be formed between the second electronic component and the inner surface of the heat spreader lid. The first thermal interface may include a wired network of a first TIM surrounded by a second TIM, while the second thermal interface may include the second TIM, without a wired network of the first TIM. Other embodiments may be described and/or claimed.

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Номер записи: 9
26-09-2023 дата публикации

Thermally-optimized tunable stack in cavity package-on-package

Номер: US0011769753B2
Автор: George Vakanas, Aastha Uppal, Shereen Elhalawaty, Aaron McCann, Edvin Cetegen, Tannaz Harirchian, Saikumar Jayaraman
Принадлежит: Intel Corporation

Embodiments disclosed herein include an electronics package and methods of forming such electronics packages. In an embodiment, the electronics package comprises a package substrate, and a first die coupled to the package substrate. In an embodiment, a cavity is formed through the package substrate. In an embodiment, the cavity is within a footprint of the first die. In an embodiment, the electronics package further comprises a thermal stack in the cavity. In an embodiment, the thermal stack contacts the first die.

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Номер записи: 10
22-08-2023 дата публикации

Active package cooling structures using molded substrate packaging technology

Номер: US0011735495B2
Автор: Omkar Karhade, Mitul Modi, Edvin Cetegen, Aastha Uppal
Принадлежит: Intel Corporation

Package assemblies with a molded substrate comprising fluid conduits. The fluid conduits may be operable for conveying a fluid (e.g., liquid and/or vapor) through some portion of the package substrate structure. Fluid conduits may be at least partially defined by an interconnect trace comprising a metal. The fluid conveyance may improve thermal management of the package assembly, for example removing heat dissipated by one or more integrated circuits (ICs) of the package assembly.

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Номер записи: 11
07-02-2023 дата публикации

Coupled cooling fins in ultra-small systems

Номер: US0011574851B2
Автор: Aastha Uppal, Omkar Karhade, Ram Viswanath, Je-Young Chang, Weihua Tang, Nitin Deshpande, Mitul Modi, Edvin Cetegen, Sanka Ganesan, Yiqun Bai, Jan Krajniak, Kumar Singh
Принадлежит: Intel Corporation

An apparatus is provided which comprises: a package substrate, an integrated circuit device coupled to a surface of the package substrate, a first material on the surface of the package substrate, the first material contacting one or more lateral sides of the integrated circuit device, the first material extending at least to a surface of the integrated circuit device opposite the package substrate, two or more separate fins over a surface of the integrated circuit device, the two or more fins comprising a second material having a different composition than the first material, and a third material having a different composition than the second material, the third material over the surface of the integrated circuit device and between the two or more fins. Other embodiments are also disclosed and claimed.

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Номер записи: 12
30-01-2024 дата публикации

Microelectronic structures including bridges

Номер: US0011887962B2
Автор: Omkar G. Karhade, Nitin A. Deshpande, Mohit Bhatia, Sairam Agraharam, Edvin Cetegen, Anurag Tripathi, Malavarayan Sankarasubramanian, Jan Krajniak, Manish Dubey, Jinhe Liu, Wei Li, Jingyi Huang
Принадлежит: Intel Corporation

Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

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Номер записи: 13
28-11-2023 дата публикации

Full package vapor chamber with IHS

Номер: US0011832419B2
Автор: Nicholas Neal, Nicholas S. Haehn, Je-Young Chang, Kyle Arrington, Aaron McCann, Edvin Cetegen, Ravindranath V. Mahajan, Robert L. Sankman, Ken P. Hackenberg, Sergio A. Chan Arguedas
Принадлежит: Intel Corporation

Embodiments include semiconductor packages. A semiconductor package includes dies on a package substrate, an integrated heat spreader (IHS) with a lid and sidewalls over the dies and package substrate, and a heatsink and a thermal interface material respectively on the IHS. The semiconductor package includes a vapor chamber defined by a surface of the package substrate and surfaces of the lid and sidewalls, and a wick layer in the vapor chamber. The wick layer is on the dies, package substrate, and IHS, where the vapor chamber has a vapor space defined by surfaces of the wick layer and lid of the IHS. The sidewalls are coupled to the package substrate with a sealant that hermetically seals the vapor chamber with the surfaces of the package substrate and the sidewalls and lid. The wick layer has a uniform or non-uniform thickness, and has porous materials including metals, powders, or graphite.

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Номер записи: 14
29-01-2019 дата публикации

Underfill material flow control for reduced die-to-die spacing in semiconductor packages

Номер: US0010192810B2
Автор: Omkar G. Karhade, Nitin A. Deshpande, Rajendra C. Dias, Edvin Cetegen, Lars D. Skoglund, KARHADE OMKAR G, DESHPANDE NITIN A, DIAS RAJENDRA C, CETEGEN EDVIN, SKOGLUND LARS D, Karhade, Omkar G., Deshpande, Nitin A., Dias, Rajendra C., Cetegen, Edvin, Skoglund, Lars D.
Принадлежит: Intel Corporation, INTEL CORP

Underfill material flow control for reduced die-to-die spacing in semiconductor packages and the resulting semiconductor packages are described. In an example, a semiconductor apparatus includes first and second semiconductor dies, each having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a common semiconductor package substrate by a plurality of conductive contacts, the first and second semiconductor dies separated by a spacing. A barrier structure is disposed between the first semiconductor die and the common semiconductor package substrate and at least partially underneath the first semiconductor die. An underfill material layer is in contact with the second semiconductor die and with the barrier structure, but not in contact with the first semiconductor die.

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Номер записи: 15
16-12-2021 дата публикации

MICROELECTRONIC STRUCTURES INCLUDING BRIDGES

Номер: US20210391273A1
Автор: Manish Dubey, Omkar G. Karhade, Nitin A. Deshpande, Jinhe Liu, Sairam Agraharam, Mohit Bhatia, Edvin Cetegen
Принадлежит: Interl Corporation

Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge. 1. A microelectronic structure , comprising:a substrate;a cavity at a face of the substrate;a first conductive contact in the cavity; anda bridge component in the cavity, wherein the bridge component includes a first face and an opposing second face, the second face of the bridge component is between the first face of the bridge component and the substrate, and the bridge component includes a second conductive contact at the second face of the bridge component;wherein the first conductive contact is electrically coupled to the second conductive contact, and the first conductive contact in the cavity has a non-planar contact surface.2. The microelectronic structure of claim 1 , wherein the first conductive contact includes a wire.3. The microelectronic structure of claim 2 , wherein the wire includes copper claim 2 , silver claim 2 , or gold.4. The microelectronic structure of claim 1 , wherein the contact surface includes a pointed shape.5. The microelectronic structure of claim 1 , wherein the contact surface has an arc shape.6. The microelectronic structure of claim 5 , wherein the first conductive contact includes a dome of multiple wires.7. The microelectronic structure of claim 1 , wherein the first conductive contact includes a cantilever.8. A microelectronic assembly claim 1 , comprising:a substrate;a cavity at a face of the substrate;a first conductive contact in the cavity, wherein the first conductive contact has a non-planar contact surface;a bridge component in the cavity, wherein the bridge component includes a first face and an opposing second face, the second face of the bridge component is between the first face of the bridge component and the substrate, and the bridge component includes a second conductive contact at the first face of the bridge component; ...

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Номер записи: 16
16-07-2020 дата публикации

THERMAL MANAGEMENT SOLUTIONS FOR INTEGRATED CIRCUIT PACKAGES

Номер: US20200227332A1
Автор: Kumar Abhishek Singh, Omkar Karhade, Nitin Deshpande, Mitul Modi, Edvin Cetegen, Aastha Uppal, Debendra Mallik, Sanka Ganesan, Yiqun Bai, Jan Krajniak, Manish Dubey, Ravindranath Mahajan, Ram Viswanath, James C. Matayabas, JR., SINGH KUMAR ABHISHEK, KARHADE OMKAR, DESHPANDE NITIN, MODI MITUL, CETEGEN EDVIN, UPPAL AASTHA, MALLIK DEBENDRA, GANESAN SANKA, BAI YIQUN, KRAJNIAK JAN, DUBEY MANISH, MAHAJAN RAVINDRANATH, VISWANATH RAM, MATAYABAS JR JAMES C, Singh, Kumar Abhishek, Karhade, Omkar, Deshpande, Nitin, Modi, Mitul, Cetegen, Edvin, Uppal, Aastha, Mallik, Debendra, Ganesan, Sanka, Bai, Yiqun, Krajniak, Jan, Dubey, Manish, Mahajan, Ravindranath, Viswanath, Ram, Matayabas, JR., James C.
Принадлежит: Intel Corporation

An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate. 1. An integrated circuit assembly , comprising:a substrate;at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate;a mold material on the substrate and adjacent to the at least one integrated circuit device; andat least one heat dissipation structure contacting the at least one integrated circuit device, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.2. The integrated circuit assembly of claim 1 , wherein the at least one integrated circuit device has a first surface claim 1 , an opposing second surface claim 1 , and at least one side extending between the first surface and the second surface claim 1 , and wherein the at least one heat dissipation structure contacts the first surface of the substrate claim 1 , the at least one side of the integrated circuit device claim 1 , and the second surface of the integrated circuit device.3. The integrated circuit assembly of claim 2 , wherein a portion of the at least one heat dissipation structure extends from the integrated circuit device to a first surface of the mold material.4. The integrated circuit assembly of claim 1 , wherein the at least one heat dissipation structure extends from ...

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Номер записи: 17
15-09-2016 дата публикации

METHODS TO FORM HIGH DENSITY THROUGH-MOLD INTERCONNECTIONS

Номер: US20160268231A1
Автор: Omkar G. Karhade, Nitin A. Deshpande, Edvin Cetegen, Eric J. Li, Debendra Mallik, Bassam M. Ziadeh, KARHADE OMKAR G, DESHPANDE NITIN A, CETEGEN EDVIN, LI ERIC J, MALLIK DEBENDRA, ZIADEH BASSAM M, Karhade Omkar G., Deshpande Nitin A., Cetegen Edvin, Li Eric J., Mallik Debendra, Ziadeh Bassam M.
Принадлежит: INTEL CORPORATION

Methods of fabricating a microelectronic device comprising forming a microelectronic substrate having a plurality microelectronic device attachment bond pads and at least one interconnection bond pad formed in and/or on an active surface thereof, attaching a microelectronic device to the plurality of microelectronic device attachment bond pads, forming a mold chase having a mold body and at least one projection extending from the mold body, wherein the at least one projection includes at least one sidewall and a contact surface, contacting the mold chase projection contact surface to a respective microelectronic substrate interconnection bond pad, disposing a mold material between the microelectronic substrate and the mold chase, and removing the mold chase to form at least one interconnection via extending from a top surface of the mold material to a respective microelectronic substrate interconnection bond pad. 125-. (canceled)26. A method of fabricating a microelectronic device comprising:forming a microelectronic substrate having a plurality of microelectronic device attachment bond pads and at least one interconnection bond pad formed in and/or on an active surface thereof;attaching a microelectronic device to the plurality of microelectronic device attachment bond pads;forming a mold chase having a mold body and at least one projection extending from the mold body, wherein the at least one projection includes at least one sidewall and a contact surface;contacting the at least one mold chase projection contact surface to a respective microelectronic substrate interconnection bond pad;disposing a mold material between the microelectronic substrate and the mold chase; andremoving the mold chase to form at least one interconnection via extending from a top surface of the mold material to a respective microelectronic substrate interconnection bond pad.27. The method of claim 26 , further comprising filling the at least one interconnection via with a conductive ...

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Номер записи: 18
27-08-2020 дата публикации

ACTIVE PACKAGE COOLING STRUCTURES USING MOLDED SUBSTRATE PACKAGING TECHNOLOGY

Номер: US20200273775A1
Автор: Omkar Karhade, Mitul Modi, Edvin Cetegen, Aastha Uppal, KARHADE OMKAR, MODI MITUL, CETEGEN EDVIN, UPPAL AASTHA, Karhade, Omkar, Modi, Mitul, Cetegen, Edvin, Uppal, Aastha
Принадлежит:

Package assemblies with a molded substrate comprising fluid conduits. The fluid conduits may be operable for conveying a fluid (e.g., liquid and/or vapor) through some portion of the package substrate structure. The fluid conveyance may improve thermal management of the package assembly, for example removing heat dissipated by one or more integrated circuits (ICs) of the package assembly. 1. A microelectronic device package assembly , comprising:a substrate structure comprising one or more traces adjacent to a mold material, wherein the traces comprises a metal;an integrated circuit (IC) die physically coupled to the substrate structure, and electrically coupled to at least one of the traces; anda fluid conduit within the substrate structure, wherein at least a portion of the fluid conduit comprises the metal.2. The microelectronic device package structure of claim 1 , wherein the fluid conduit comprises an inlet to receive a fluid into the substrate structure and an outlet to discharge the fluid from the substrate structure with a length of the conduit therebetween.3. The microelectronic device package structure of claim 2 , wherein the die is over at least a portion of the fluid conduit claim 2 , and wherein the length of the fluid conduit is greater than a length of the die.4. The microelectronic device package structure of claim 1 , wherein the substrate structure comprises a first and second substrate claim 1 , the first substrate bonded to the second substrate by a plurality of solder features claim 1 , and wherein the fluid conduit is between the first and second substrate.5. The microelectronic package structure of claim 4 , wherein:the die is bonded to the first substrate;the fluid conduit comprises an inlet to receive a fluid into the substrate structure and an outlet to discharge the fluid from the substrate structure; andthe fluid conduit comprises a metal trace of the first substrate attached by solder to a metal trace of the second substrate.6. The ...

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Номер записи: 19
27-08-2020 дата публикации

IC DIE PACKAGE THERMAL SPREADER AND EMI SHIELD COMPRISING GRAPHITE

Номер: US20200273811A1
Автор: Debendra Mallik, Mitul Modi, Sanka Ganesan, Edvin Cetegen, Omkar Karhade, Ravindranath Mahajan, James C. Matayabas, Jr., Jan Krajniak, Kumar Singh, Aastha Uppal, MALLIK DEBENDRA, MODI MITUL, GANESAN SANKA, CETEGEN EDVIN, KARHADE OMKAR, MAHAJAN RAVINDRANATH, MATAYABAS JR JAMES C, KRAJNIAK JAN, SINGH KUMAR, UPPAL AASTHA, Mallik, Debendra, Modi, Mitul, Ganesan, Sanka, Cetegen, Edvin, Karhade, Omkar, Mahajan, Ravindranath, Matayabas, Jr., James C., Krajniak, Jan, Singh, Kumar, Uppal, Aastha
Принадлежит: Intel Corporation

IC package including a material preform comprising graphite. The material preform may have a thermal conductivity higher than that of other materials in the package and may therefore mitigate the formation of hot spots within an IC die during device operation. The preform may have high electrical conductivity suitable for EMI shielding. The preform may comprise a graphite sheet that can be adhered to a package assembly with an electrically conductive adhesive, applied, for example over an IC die surface and a surrounding package dielectric material. Electrical interconnects of the package may be coupled to the graphite sheet as an EMI shield. The package preform may be grounded to a reference potential through electrical interconnects of the package, which may be further coupled to a system-level ground plane. System-level thermal solutions may interface with the package-level graphite sheet. 1. An integrated circuit (IC) package , comprising:a die comprising an integrated circuit,a dielectric material between a sidewall of the die and an electrical interconnect;a first electrically conductive material over the die and the dielectric material; anda second electrically conductive material over the first electrically conductive material, wherein the second electrically conductive material comprises graphite, and wherein at least one of the first or second electrically conductive materials is in contact with the electrical interconnect.2. The IC package of claim 1 , wherein the second electrically conductive material comprises a graphite sheet having an area exceeding that of the die.3. The integrated circuit package of claim 2 , wherein the second electrically conductive material has anisotropic thermal conductivity with a highest thermal conductivity in a plane substantially parallel to a surface of the die.4. The integrated circuit package of claim 3 , wherein further comprising a metal embedded within an opening in the graphite sheet claim 3 , the opening located ...

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Номер записи: 20
22-03-2022 дата публикации

Micro-electronic package with substrate protrusion to facilitate dispense of underfill between a narrow die-to-die gap

Номер: US0011282717B2
Автор: Ziyin Lin, Vipul Mehta, Edvin Cetegen, Yuying Wei, Sushrutha Gujjula, Nisha Ananthakrishnan, Shan Zhong
Принадлежит: Intel Corporation

A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die. The substrate protrusion can enable void-free underfill.

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Номер записи: 21
07-05-2020 дата публикации

CONFORMABLE HEAT SINK INTERFACE WITH A HIGH THERMAL CONDUCTIVITY

Номер: US20200146183A1
Автор: Kelly Lofgreen, Joseph Petrini, Todd Coons, Christopher Wade Ackerman, Edvin Cetegen, Yang Jiao, Michael Rutigliano, Kuang Liu, LOFGREEN KELLY, PETRINI JOSEPH, COONS TODD, ACKERMAN CHRISTOPHER WADE, CETEGEN EDVIN, JIAO YANG, RUTIGLIANO MICHAEL, LIU KUANG, Lofgreen, Kelly, Petrini, Joseph, Coons, Todd, Ackerman, Christopher Wade, Cetegen, Edvin, Jiao, Yang, Rutigliano, Michael, Liu, Kuang
Принадлежит: Intel Corporation

A conformable heat sink interface for an integrated circuit package comprises a mounting plate having a first surface and a deformable membrane having a portion bonded to a second surface of the plate. A cavity is between the second surface of the plate and the deformable membrane. A flowable heat transfer medium is within the cavity. The flowable heat transfer medium has a thermal conductivity of not less than 30 W/m K. The deformable membrane is to conform to a three-dimensional shape of an IC package and the mounting plate has a second surface that is to be adjacent to a heat sink base.

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Номер записи: 22
24-07-2014 дата публикации

THERMAL MANAGEMENT SOLUTION FOR CIRCUIT PRODUCTS

Номер: US20140204534A1
Автор: Arnab Choudhury, Je-Young Chang, David W. Song, Edvin Cetegen, Ashish Gupta, CHOUDHURY ARNAB, CHANG JE-YOUNG, SONG DAVID W, CETEGEN EDVIN, GUPTA ASHISH, SONG DAVID W.
Принадлежит:

An apparatus including a cold plate body; a channel module disposed within the cold plate body including a channel body and a plurality of channels projecting through the channel body; and a manifold disposed on the channel module, the manifold including an inlet and an outlet and a first plurality of apertures in fluid communication with the inlet and a second plurality of apertures are in fluid communication with the outlet. A method including introducing a fluid to an integrated cold plate disposed on an integrated circuit device, the integrated cold plate comprising a cold plate body extending about the device, the fluid being introduced into a manifold in fluid communication with a channel module disposed between the manifold and a base plate, the channel module, and including channels to direct the fluid toward the base plate, and collecting the fluid returned to the manifold. 1. An apparatus comprising:a cold plate body comprising a cap portion and sidewall portion extending from the cap portion;a channel module disposed within the cold plate body comprising a channel body and a plurality of channels projecting through the channel body; anda manifold disposed on the channel module, the manifold comprising an inlet and an outlet and a plurality of apertures, wherein a first of the plurality of apertures are in fluid communication with the inlet and a second of the plurality of apertures are in fluid communication with the outlet.2. The apparatus of claim 1 , wherein the cold plate body has an opening in the cap portion and the manifold is disposed in the opening.3. The apparatus of claim 1 , further comprising a base plate coupled to the channel module such that the channel module is disposed between the manifold and the base plate and wherein the plurality of channels in the channel module project through the body in a direction toward the base plate.4. The apparatus of claim 1 , wherein the channel module and the base plate are a unitary body of a thermally ...

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Номер записи: 23
11-06-2024 дата публикации

Protruding SN substrate features for epoxy flow control

Номер: US0012009271B2
Автор: Edvin Cetegen, Jacob Vehonsky, Nicholas S. Haehn, Thomas Heaton, Steve S. Cho, Rahul Jain, Tarek Ibrahim, Antariksh Rao Pratap Singh, Nicholas Neal, Sergio Chan Arguedas, Vipul Mehta
Принадлежит: Intel Corporation

Embodiments disclosed herein include electronic packages with underfill flow control features. In an embodiment, an electronic package comprises a package substrate and a plurality of interconnects on the package substrate. In an embodiment, a die is coupled to the package substrate by the plurality of interconnects and a flow control feature is adjacent on the package substrate. In an embodiment, the flow control feature is electrically isolated from circuitry of the electronic package. In an embodiment, the electronic package further comprises an underfill surrounding the plurality of interconnects and in contact with the flow control feature.

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Номер записи: 24
09-05-2023 дата публикации

Multi-package assemblies having foam structures for warpage control

Номер: US0011646274B2
Автор: Mufei Yu, Gang Duan, Edvin Cetegen, Baris Bicen, Rahul Manepalli
Принадлежит: Intel Corporation

An integrated circuit package may be formed comprising a substrate that includes a mold material layer and a signal routing layer, wherein the mold material layer comprises at least one bridge and at least one foam structure embedded in a mold material. In one embodiment, the substrate may include the mold material of the mold material layer filling at least a portion of cells within the foam structure. In a further embodiment, at least two integrated circuit devices may be attached to the substrate, such that the bridge provides device-to-device interconnection between the at least two integrated circuit devices. In a further embodiment, the integrated circuit package may be electrically attached to an electronic board.

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Номер записи: 25
10-01-2023 дата публикации

Liquid metal TIM with STIM-like performance with no BSM and BGA compatible

Номер: US0011551994B2
Автор: Kelly Lofgreen, Chia-Pin Chiu, Joseph Petrini, Edvin Cetegen, Betsegaw Gebrehiwot, Feras Eid
Принадлежит: Intel Corporation

Embodiments include an electronic system and methods of forming an electronic system. In an embodiment, the electronic system may include a package substrate and a die coupled to the package substrate. In an embodiment, the electronic system may also include an integrated heat spreader (IHS) that is coupled to the package substrate. In an embodiment the electronic system may further comprise a thermal interface pad between the IHS and the die. In an embodiment the die is thermally coupled to the IHS by a liquid metal thermal interface material (TIM) that contacts the thermal interface pad.

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Номер записи: 26
04-06-2024 дата публикации

Barrier structures for underfill containment

Номер: US0012002727B2
Автор: Ziyin Lin, Vipul Mehta, Wei Li, Edvin Cetegen, Xavier Brun, Yang Guo, Soud Choudhury, Shan Zhong, Christopher Rumer, Nai-Yuan Liu, Ifeanyi Okafor, Hsin-Wei Wang
Принадлежит: Intel Corporation, INTEL CORPORATION

An integrated circuit assembly may be formed comprising an electronic substrate, a first and second integrated circuit device each having a first surface, a second surface, at least one side extending between the first and second surface, and an edge defined at an intersection of the second surface and the at least one side of each respective integrated circuit device, wherein the first surface of each integrated circuit device is electrically attached to the electronic substrate, an underfill material between the first surface of each integrated circuit device and the electronic substrate, and between the sides of the first and second integrated circuit devices, and at least one barrier structure adjacent at least one of the edge of first integrated circuit device and the edge of the second integrated circuit device, wherein the underfill material abuts the at least one barrier structure.

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Номер записи: 27
19-03-2024 дата публикации

Underfill flow management in electronic assemblies

Номер: US0011935861B2
Автор: Frederick W. Atadana, Taylor William Gaines, Edvin Cetegen, Wei Li, Hsin-Yu Li, Tony Dambrauskas
Принадлежит: Intel Coropration, Intel Corporation

Disclosed herein are structures and techniques for underfill flow management in electronic assemblies. For example, in some embodiments, an electronic assembly may include a first component, a second component, an underfill on the first component and at least partially between the first component and the second component, and a material at a surface of the first component, wherein the material is outside a footprint of the second component, and the underfill contacts the material with a contact angle greater than 50 degrees.

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Номер записи: 28
12-09-2019 дата публикации

INTEGRATED CIRCUIT PACKAGES WITH PLATES

Номер: US20190279960A1
Автор: Omkar G. Karhade, Edvin Cetegen, Sandeep B. Sane, KARHADE OMKAR G, CETEGEN EDVIN, SANE SANDEEP B, Karhade, Omkar G., Cetegen, Edvin, Sane, Sandeep B.
Принадлежит: Intel Corporation

Disclosed herein are integrated circuit (IC) packages with plates, as well as related devices and methods. For example, in some embodiments, an IC package may include: a package substrate; a plurality of electrical components secured to a face of the package substrate; and a plate secured to the plurality of electrical components with an adhesive such that the plurality of electrical components are between the plate and the package substrate. 1. An integrated circuit (IC) package , comprising:a package substrate;a plurality of electrical components secured to a face of the package substrate; anda plate secured to the plurality of electrical components with an adhesive such that the plurality of electrical components are between the plate and the package substrate.2. The IC package of claim 1 , wherein a thickness of the plate is less than 100 microns.3. (canceled)4. The IC package of claim 1 , wherein the adhesive does not contact the package substrate.5. The IC package of claim 1 , wherein the face is a first face claim 1 , the package substrate has a second face opposite to the first face claim 1 , and the IC package further includes:second level interconnects at the second face of the package substrate.6. The IC package of claim 5 , further comprising:at least one electrical component secured to the second face of the package substrate with first level interconnects.7. The IC package of claim 6 , wherein the at least one electrical component secured to the second face of the package substrate includes a processing die.8. The IC package of claim 6 , wherein an underfill material is between the at least one electrical component and the second face of the package substrate.9. The IC package of claim 8 , wherein no underfill material is between the plurality of electrical components and the first face of the package substrate.10. The IC package of claim 1 , wherein the plate includes at least one recessed portion in a face facing the plurality of electrical ...

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Номер записи: 29
25-04-2024 дата публикации

MICROELECTRONIC STRUCTURES INCLUDING BRIDGES

Номер: US20240136292A1
Автор: Omkar G. Karhade, Edvin Cetegen, Anurag Tripathi, Nitin A. Deshpande
Принадлежит: Intel Corp

Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

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Номер записи: 30
25-10-2016 дата публикации

Thermal management solution for circuit products

Номер: US0009477275B2
Автор: Arnab Choudhury, Je-Young Chang, David W. Song, Edvin Cetegen, Ashish Gupta, CHOUDHURY ARNAB, CHANG JE-YOUNG, SONG DAVID W, CETEGEN EDVIN, GUPTA ASHISH, Choudhury Arnab, Chang Je-Young, Song David W., Cetegen Edvin, Gupta Ashish
Принадлежит: Intel Corporation, CHOUDHURY ARNAB, CHANG JE-YOUNG, SONG DAVID W, CETEGEN EDVIN, GUPTA ASHISH, INTEL CORP, Choudhury Arnab, Chang Je-Young, Song David W., Cetegen Edvin, Gupta Ashish

An apparatus including a cold plate body; a channel module disposed within the cold plate body including a channel body and a plurality of channels projecting through the channel body; and a manifold disposed on the channel module, the manifold including an inlet and an outlet and a first plurality of apertures in fluid communication with the inlet and a second plurality of apertures are in fluid communication with the outlet. A method including introducing a fluid to an integrated cold plate disposed on an integrated circuit device, the integrated cold plate comprising a cold plate body extending about the device, the fluid being introduced into a manifold in fluid communication with a channel module disposed between the manifold and a base plate, the channel module, and including channels to direct the fluid toward the base plate, and collecting the fluid returned to the manifold.

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Номер записи: 31
30-01-2014 дата публикации

CONTROLLING THERMAL INTERFACE MATERIAL BLEED OUT

Номер: US20140027899A1
Автор: Gopi Krishnan, Mingjie Xu, Edvin Cetegen, Sung-Won Moon, KRISHNAN GOPI, XU MINGJIE, CETEGEN EDVIN, MOON SUNG-WON
Принадлежит: Intel Corp

An extended preform of a thermal interface material (TIM) is formed between a heat spreader and a die on a substrate. The preform has an extension beyond a footprint of the die. The preform is cured. A bleed out of the TIM is controlled by the extension upon curing of the preform.

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Номер записи: 32
13-02-2024 дата публикации

No mold shelf package design and process flow for advanced package architectures

Номер: US0011901333B2
Автор: Wei Li, Edvin Cetegen, Nicholas S. Haehn, Ram S. Viswanath, Nicholas Neal, Mitul Modi
Принадлежит: Intel Corporation

Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.

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Номер записи: 33
17-10-2023 дата публикации

Multichip semiconductor package including a bridge die disposed in a cavity having non-planar interconnects

Номер: US0011791274B2
Автор: Manish Dubey, Omkar G. Karhade, Nitin A. Deshpande, Jinhe Liu, Sairam Agraharam, Mohit Bhatia, Edvin Cetegen
Принадлежит: Intel Corporation

Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

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Номер записи: 34
26-12-2023 дата публикации

Underfill material flow control for reduced die-to-die spacing in semiconductor packages

Номер: US0011854945B2
Автор: Omkar G. Karhade, Nitin A. Deshpande, Rajendra C. Dias, Edvin Cetegen, Lars D. Skoglund
Принадлежит: Tahoe Research, Ltd.

Underfill material flow control for reduced die-to-die spacing in semiconductor packages and the resulting semiconductor packages are described. In an example, a semiconductor apparatus includes first and second semiconductor dies, each having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a common semiconductor package substrate by a plurality of conductive contacts, the first and second semiconductor dies separated by a spacing. A barrier structure is disposed between the first semiconductor die and the common semiconductor package substrate and at least partially underneath the first semiconductor die. An underfill material layer is in contact with the second semiconductor die and with the barrier structure, but not in contact with the first semiconductor die.

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Номер записи: 35
22-08-2017 дата публикации

Methods to form high density through-mold interconnections

Номер: US0009741692B2
Автор: Omkar G. Karhade, Nitin A. Deshpande, Edvin Cetegen, Eric J. Li, Debendra Mallik, Bassam M. Ziadeh, KARHADE OMKAR G, DESHPANDE NITIN A, CETEGEN EDVIN, LI ERIC J, MALLIK DEBENDRA, ZIADEH BASSAM M, Karhade Omkar G., Deshpande Nitin A., Cetegen Edvin, Li Eric J., Mallik Debendra, Ziadeh Bassam M.
Принадлежит: Intel Corporation, KARHADE OMKAR G, DESHPANDE NITIN A, CETEGEN EDVIN, LI ERIC J, MALLIK DEBENDRA, ZIADEH BASSAM M, INTEL CORP, Karhade Omkar G., Deshpande Nitin A., Cetegen Edvin, Li Eric J., Mallik Debendra, Ziadeh Bassam M.

Methods of fabricating a microelectronic device comprising forming a microelectronic substrate having a plurality microelectronic device attachment bond pads and at least one interconnection bond pad formed in and/or on an active surface thereof, attaching a microelectronic device to the plurality of microelectronic device attachment bond pads, forming a mold chase having a mold body and at least one projection extending from the mold body, wherein the at least one projection includes at least one sidewall and a contact surface, contacting the mold chase projection contact surface to a respective microelectronic substrate interconnection bond pad, disposing a mold material between the microelectronic substrate and the mold chase, and removing the mold chase to form at least one interconnection via extending from a top surface of the mold material to a respective microelectronic substrate interconnection bond pad.

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Номер записи: 36
31-03-2022 дата публикации

DUMMY DIE STRUCTURES OF A PACKAGED INTEGRATED CIRCUIT DEVICE

Номер: US20220102242A1
Автор: Mitul Modi, Joseph Van Nausdle, Omkar Karhade, Edvin Cetegen, Nicholas Haehn, Vaibhav Agrawal, Digvijay Raorane, Dingying Xu, Ziyin Lin, Yiqun Bai
Принадлежит: Intel Corporation

Techniques and mechanisms for facilitating heat conductivity in a packaged device with a dummy die. In an embodiment, a packaged device comprises a substrate and one or more IC die coupled to a surface thereof. A dummy die, adjacent to an IC die and coupled to a region of the substrate, comprises a polymer resin and a filler. A package mold structure of the packaged device adjoins respective sides of the IC die and the dummy die, and adjoins the surface of the substrate. In another embodiment, a first CTE of the dummy die is less than a second CTE of the package mold structure, and a first thermal conductivity of the dummy die is greater than a second thermal conductivity of the package mold structure.

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Номер записи: 37
23-03-2023 дата публикации

DEFORMABLE SEMICONDUCTOR DEVICE CONNECTION

Номер: US20230086180A1
Автор: Onur Ozkan, Edvin Cetegen, Steve Cho, Nicholas S. Haehn, Jacob Vehonsky, Gang Duan
Принадлежит:

A semiconductor device may include a first plate-like element having a first substantially planar connection surface with a first connection pad and a second plate-like element having a second substantially planar connection surface with a second connection pad corresponding to the first connection pad. The device may also include a connection electrically and physically coupling the first and second plate-like elements and arranged between the first and second connection pads. The connection may include a deformed elongate element arranged on the first connection pad and extending toward the second connection pad and solder in contact with the second connection pad and the elongate element.

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Номер записи: 38
24-12-2020 дата публикации

MULTI-PACKAGE ASSEMBLIES HAVING FOAM STRUCTURES FOR WARPAGE CONTROL

Номер: US20200402920A1
Автор: Mufei Yu, Gang Duan, Edvin Cetegen, Baris Bicen, Rahul Manepalli, YU MUFEI, DUAN GANG, CETEGEN EDVIN, BICEN BARIS, MANEPALLI RAHUL, Yu, Mufei, Duan, Gang, Cetegen, Edvin, Bicen, Baris, Manepalli, Rahul
Принадлежит: Intel Corporation

An integrated circuit package may be formed comprising a substrate that includes a mold material layer and a signal routing layer, wherein the mold material layer comprises at least one bridge and at least one foam structure embedded in a mold material. In one embodiment, the substrate may include the mold material of the mold material layer filling at least a portion of cells within the foam structure. In a further embodiment, at least two integrated circuit devices may be attached to the substrate, such that the bridge provides device-to-device interconnection between the at least two integrated circuit devices. In a further embodiment, the integrated circuit package may be electrically attached to an electronic board.

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Номер записи: 39
26-03-2024 дата публикации

Substrate with thermal insulation

Номер: US0011942393B2
Автор: Wei Li, Edvin Cetegen, Nicholas S. Haehn, Mitul Modi, Nicholas Neal
Принадлежит: Intel Corporation

Embodiments herein relate to systems, apparatuses, or processes directed to a substrate that includes a first region to be coupled with a die, and a second region separate and distinct from the first region that has a lower thermal conductivity than the first region, where the second region is to thermally insulate the first region when the die is coupled to the first region. The thermal insulation of the second region may be used during a TCB process to increase the quality of each of the interconnects of the die by promoting a higher temperature at the connection points to facilitate full melting of solder.

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Номер записи: 40
16-12-2021 дата публикации

MICROELECTRONIC STRUCTURES INCLUDING BRIDGES

Номер: US20210391295A1
Автор: Omkar G. Karhade, Nitin A. Deshpande, Mohit Bhatia, Sairam Agraharam, Edvin Cetegen, Anurag Tripathi, Malavarayan Sankarasubramanian, Jan Krajniak, Manish Dubey, Jinhe Liu, Wei Li, Jingyi Huang
Принадлежит: Intel Corporation

Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

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Номер записи: 41
03-01-2023 дата публикации

Thermal management solutions for integrated circuit packages

Номер: US0011545407B2
Автор: Kumar Abhishek Singh, Omkar Karhade, Nitin Deshpande, Mitul Modi, Edvin Cetegen, Aastha Uppal, Debendra Mallik, Sanka Ganesan, Yiqun Bai, Jan Krajniak, Manish Dubey, Ravindranath Mahajan, Ram Viswanath, James C. Matayabas, Jr.
Принадлежит: Intel Corporation

An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.

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Номер записи: 42
27-08-2020 дата публикации

CRYSTALLINE CARBON HEAT SPREADING MATERIALS FOR IC DIE HOT SPOT REDUCTION

Номер: US20200273768A1
Автор: Omkar Karhade, Nitin Deshpande, Mitul Modi, Edvin Cetegen, Aastha Uppal, Debendra Mallik, Sanka Ganesan, Yiqun Bai, Jan Krajniak, Kumar Singh, KARHADE OMKAR, DESHPANDE NITIN, MODI MITUL, CETEGEN EDVIN, UPPAL AASTHA, MALLIK DEBENDRA, GANESAN SANKA, BAI YIQUN, KRAJNIAK JAN, SINGH KUMAR, Karhade, Omkar, Deshpande, Nitin, Modi, Mitul, Cetegen, Edvin, Uppal, Aastha, Mallik, Debendra, Ganesan, Sanka, Bai, Yiqun, Krajniak, Jan, Singh, Kumar
Принадлежит: Intel Corporation

IC packages including a heat spreading material comprising crystalline carbon. The heat spreading material may be applied directly to an IC die surface, for example at a die prep stage, prior to an application or build-up of packaging material, so that the high thermal conductivity may best mitigate any hot spots that develop at the IC die surface during operation. The heat spreading material may be applied to surface of the IC die. 1. An integrated circuit package , comprising:a die comprising an integrated circuit;a first dielectric material adjacent to a surface of the die; anda second dielectric material between the surface of the die and the first dielectric material, the second dielectric material comprising crystalline carbon.2. The integrated circuit package of claim 1 , wherein:the surface is an edge sidewall of the die; andthe second dielectric material comprises graphene or graphite.3. The integrated circuit package of claim 2 , wherein the second dielectric material has anisotropic thermal conductivity with a highest thermal conductivity in a plane non-orthogonal to the surface of the die.4. The integrated circuit package of claim 1 , wherein:the first dielectric material has a thermal conductivity less than 4 W/mK; andthe second dielectric material has a thermal conductivity of at least 400 W/mK.5. The integrated circuit package of claim 1 , wherein the second dielectric material comprises a matrix material claim 1 , and the crystalline carbon is in the matrix material.6. The integrated circuit package of claim 5 , wherein the first dielectric material and the second dielectric material both comprise at least one of an epoxy or silicone.7. The integrated circuit package of claim 1 , wherein the second dielectric material is in contact with the surface of the die claim 1 , and the first dielectric material is in contact with the second dielectric material.8. The integrated circuit package of claim 1 , wherein:{'sup': '2', 'a first surface of the die ...

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Номер записи: 43
31-03-2022 дата публикации

DUMMY DIE IN A RECESSED MOLD STRUCTURE OF A PACKAGED INTEGRATED CIRCUIT DEVICE

Номер: US20220102231A1
Автор: Mitul Modi, Joseph Van Nausdle, Omkar Karhade, Edvin Cetegen, Nicholas Haehn, Vaibhav Agrawal, Digvijay Raorane
Принадлежит: Intel Corporation

Techniques and mechanisms for facilitating heat conductivity in a packaged device with a dummy die. In an embodiment, a packaged device comprises a substrate and one or more IC die coupled thereto. A dummy die structure extends to a bottom of a recess structure formed by a first package mold structure on the substrate. The dummy die structure comprises a polymer resin and a filler, or comprises a metal which has a low coefficient of thermal expansion (CTE). A second package mold structure, which extends to the recess structure, is adjacent to the first package mold structure and to an IC die. In another embodiment, a first CTE of the dummy die is less than a second CTE of one of the package mold structures, and a first thermal conductivity of the dummy die is greater than a second thermal conductivity of the one of the package mold structures.

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Номер записи: 44
02-01-2020 дата публикации

MICRO-ELECTRONIC PACKAGE WITH BARRIER STRUCTURE

Номер: US20200006169A1
Автор: Atadana Frederick, CETEGEN Edvin, GAINES Taylor, Guo Yang, LI Hsin-Yu, MEHTA Vipul, Warren William, Wei Yuying, ZHANG Ren
Принадлежит:

A structure including a barrier is described. In embodiments, a micro-electronic component may have a first face and a second face, wherein the second face includes interconnect structures and is opposite the first face. A fill material, such as a capillary underfill material (CUF), may fill a gap between the micro-electronic component and the substrate and substantially surround the interconnect structures. In embodiments, a barrier structure may be located on the surface of the substrate and along a perimeter or outside perimeter of the micro-electronic component, wherein a height of the barrier structure exceeds a height of the fill material in at least a portion of an open region of the substrate to confine the fill material to an area bordered by the barrier structure. 1. An apparatus , comprising:a micro-electronic component having a first face and a second face, wherein the second face includes interconnect structures and is opposite the first face;a fill material that fills a gap between the micro-electronic component and a substrate and substantially surrounds the interconnect structures; anda barrier structure located on a surface of the substrate and along a perimeter of the micro-electronic component, wherein a height of the barrier structure exceeds a height of the fill material in at least a portion of an open region of the substrate to confine the fill material to an area bordered by the barrier structure.2. The apparatus of claim 1 , wherein the barrier structure is formed from a different material than from that of the substrate and the barrier structure is located along an outside perimeter of the micro-electronic component.3. The apparatus of claim 1 , wherein the barrier structure comprises an epoxy material including one or more of amines claim 1 , anhydrides claim 1 , urethanes claim 1 , cyanos claim 1 , cationic epoxies claim 1 , and/or an acrylate material.4. The apparatus of claim 1 , wherein the fill material comprises a capillary underfill ...

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Номер записи: 45
21-01-2021 дата публикации

PROTRUDING SN SUBSTRATE FEATURES FOR EPOXY FLOW CONTROL

Номер: US20210020531A1
Автор: CETEGEN Edvin, CHAN ARGUEDAS Sergio, CHO Steve S., Haehn Nicholas S., HEATON Thomas, IBRAHIM Tarek, Jain Rahul, MEHTA Vipul, Neal Nicholas, SINGH Antariksh Rao Pratap, VEHONSKY Jacob
Принадлежит:

Embodiments disclosed herein include electronic packages with underfill flow control features. In an embodiment, an electronic package comprises a package substrate and a plurality of interconnects on the package substrate. In an embodiment, a die is coupled to the package substrate by the plurality of interconnects and a flow control feature is adjacent on the package substrate. In an embodiment, the flow control feature is electrically isolated from circuitry of the electronic package. In an embodiment, the electronic package further comprises an underfill surrounding the plurality of interconnects and in contact with the flow control feature. 1. An electronic package , comprising:a package substrate;a plurality of interconnects on the package substrate;a die coupled to the package substrate by the plurality of interconnects;a flow control feature adjacent on the package substrate, wherein the flow control feature is electrically isolated from circuitry of the electronic package; andan underfill surrounding the plurality of interconnects and in contact with the flow control feature.2. The electronic package of claim 1 , wherein the flow control feature comprises:a plurality of substantially parallel lines.3. The electronic package of claim 2 , wherein the plurality of substantially parallel lines run in a direction substantially parallel to a direction of flow of the underfill.4. The electronic package of claim 2 , wherein the plurality of substantially parallel lines run in a direction substantially orthogonal to a direction of flow of the underfill.5. The electronic package of claim 1 , wherein the flow control feature comprises first lines and second lines claim 1 , wherein the first lines are substantially orthogonal to the second lines.6. The electronic package of claim 1 , wherein a first flow control feature is adjacent to a first edge of the die and a second flow control feature is adjacent to a second edge of the die claim 1 , wherein the first edge is ...

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Номер записи: 46
21-01-2021 дата публикации

CORNER GUARD FOR IMPROVED ELECTROPLATED FIRST LEVEL INTERCONNECT BUMP HEIGHT RANGE

Номер: US20210020532A1
Автор: CETEGEN Edvin, CHAN ARGUEDAS Sergio, CHO Steve S., Haehn Nicholas S., HEATON Thomas, IBRAHIM Tarek, Jain Rahul, Neal Nicholas, SINGH Antariksh Rao Pratap, VEHONSKY Jacob
Принадлежит:

Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment an electronic package comprises a package substrate, and a first level interconnect (FLI) bump region on the package substrate. In an embodiment, the FLI bump region comprises a plurality of pads, and a plurality of bumps, where each bump is over a different one of the plurality of pads. In an embodiment, the electronic package further comprises a guard feature adjacent to the FLI bump region. In an embodiment, the guard feature comprises, a guard pad, and a guard bump over the guard pad, wherein the guard feature is electrically isolated from circuitry of the electronic package. 1. An electronic package , comprising:a package substrate; a plurality of pads; and', 'a plurality of bumps, wherein each bump is over a different one of the plurality of pads; and, 'a first level interconnect (FLI) bump region on the package substrate, wherein the FLI bump region comprises a guard pad; and', 'a guard bump over the guard pad, wherein the guard feature is electrically isolated from circuitry of the electronic package., 'a guard feature adjacent to the FLI bump region, wherein the guard feature comprises2. The electronic package of claim 1 , wherein the guard feature is proximate to a corner of the FLI bump region.3. The electronic package of claim 2 , wherein the guard feature is substantially L-shaped claim 2 , and wherein the guard feature wraps around the corner of the FLI bump region.4. The electronic package of claim 3 , wherein a first arm of the guard feature and a second arm of the guard feature have lengths that are approximately 15 mm or less.5. The electronic package of claim 1 , further comprising:a plurality of guard features, wherein the plurality of guard features are positioned around a perimeter of the FLI bump region.6. The electronic package of claim 1 , wherein the plurality of guard features are positioned proximate to two or more corners of ...

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Номер записи: 47
04-02-2021 дата публикации

SOLDERED METALLIC RESERVOIRS FOR ENHANCED TRANSIENT AND STEADY-STATE THERMAL PERFORMANCE

Номер: US20210035921A1
Автор: CETEGEN Edvin, CHAN ARGUEDAS Sergio, CHO Steve S., Haehn Nicholas S., HEATON Thomas, IBRAHIM Tarek A., Jain Rahul, Neal Nicholas, SINGH Antariksh Rao Pratap, VEHONSKY Jacob
Принадлежит:

Embodiments disclosed herein include electronic packages with thermal solutions. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and an integrated heat spreader (IHS) that is thermally coupled to a surface of the first die. In an embodiment, the IHS comprises a main body having an outer perimeter, and one or more legs attached to the outer perimeter of the main body, wherein the one or more legs are supported by the package substrate. In an embodiment, the electronic package further comprises a thermal block between the package substrate and the main body of the IHS, wherein the thermal block is within the outer perimeter of the main body. 1. An electronic package , comprising:a package substrate;a first die electrically coupled to the package substrate; a main body having an outer perimeter; and', 'one or more legs attached to the outer perimeter of the main body, wherein the one or more legs are supported by the package substrate; and, 'an integrated heat spreader (IHS) that is thermally coupled to a surface of the first die, wherein the IHS comprisesa thermal block between the package substrate and the main body of the IHS, wherein the thermal block is within the outer perimeter of the main body.2. The electronic package of claim 1 , wherein the thermal block is a part of the IHS.3. The electronic package of claim 2 , wherein a bottom of the thermal block is attached to the package substrate by a solder.4. The electronic package of claim 1 , wherein the thermal block is a pillar that extends up from the package substrate.5. The electronic package of claim 4 , wherein a top surface of the thermal block is separated from the IHS by a thermal interface material (TIM).6. The electronic package of claim 4 , wherein a bottom surface of the thermal block is attached to a metal plane that extends across a surface of the package substrate.7. The electronic package of claim 1 , wherein the ...

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Номер записи: 48
07-02-2019 дата публикации

DUAL-SIDED PACKAGE ASSEMBLY PROCESSING

Номер: US20190043776A1
Автор: Aleksov Aleksandar, CETEGEN Edvin, Malatkar Pramod, SENEVIRATNE Dilan
Принадлежит: Intel Corporation

Techniques and mechanisms for providing packaged circuitry. In an embodiment, first circuit structures are coupled to a release layer on a first side of a substrate, and second circuit structures are coupled to another release layer on a second side of the substrate. Respective portions of mold compound are variously injection molded or otherwise deposited around the first circuit structures and around the second circuit structures. The mold compound portions are cured while the first circuit structures and the second circuit structures are on opposite respective sides of the substrate. In another embodiment, the first circuit structures and the second circuit structures are separated from each other and from the substrate, after curing of the mold compound portions, to form distinct packaged devices. 125.-. (canceled)26. method comprising:coupling first circuit structures to a first release layer;coupling second circuit structures to a second release layer; disposing a first mold compound portion around the first circuit structures; and', 'disposing a second mold compound portion around the second circuit structures., 'while the first circuit structures are coupled to the first release layer, while the second circuit structures are coupled to the second release layer, and while the first release layer and the second release layer are on opposite respective sides of a substrate including one or more core layers27. The method of claim 26 , further comprising:curing the first mold compound portion to form a first package structure; andcuring the second mold compound portion to form a second package structure.28. The method of claim 27 , further comprising:after curing the first mold compound portion and curing the second mold compound portion, forming a first packaged device by separating the first package structure and the first circuit components from some or all of the substrate.29. The method of claim 28 , further comprising forming a second packaged device by ...

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Номер записи: 49
06-02-2020 дата публикации

THERMALLY-OPTIMIZED TUNABLE STACK IN CAVITY PACKAGE-ON-PACKAGE

Номер: US20200043894A1
Автор: CETEGEN Edvin, ELHALAWATY Shereen, HARIRCHIAN Tannaz, Jayaraman Saikumar, MCCANN Aaron, UPPAL Aastha, VAKANAS George
Принадлежит:

Embodiments disclosed herein include an electronics package and methods of forming such electronics packages. In an embodiment, the electronics package comprises a package substrate, and a first die coupled to the package substrate. In an embodiment, a cavity is formed through the package substrate. In an embodiment, the cavity is within a footprint of the first die. In an embodiment, the electronics package further comprises a thermal stack in the cavity. In an embodiment, the thermal stack contacts the first die. 1. An electronics package , comprising:a package substrate;a first die coupled to the package substrate;a cavity through the package substrate, wherein the cavity is within a footprint of the first die; anda thermal stack in the cavity, wherein the thermal stack contacts the first die.2. The electronics package of claim 1 , wherein the thermal stack comprises a thermal interface material (TIM).3. The electronics package of claim 1 , wherein the thermal stack comprises a substrate.4. The electronics package of claim 3 , wherein the substrate comprises copper.5. The electronics package of claim 3 , wherein the substrate comprises silicon.6. The electronics package of claim 3 , wherein the thermal stack further comprises a TIM between the substrate and the first die.7. The electronics package of claim 1 , wherein a width of the cavity is less than a width of the first die.8. The electronics package of claim 1 , further comprising a mold layer over the first die and the package substrate.9. The electronics package of claim 8 , wherein the thermal stack contacts a portion of the mold layer and the first die.10. The electronics package of claim 1 , further comprising a second die over the first die.11. The electronics package of claim 10 , wherein the first die and the second die are electrically coupled to the package substrate with wire bonds.12. The electronics package of claim 10 , wherein the first die and the second die are memory dies.13. The electronics ...

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Номер записи: 50
04-03-2021 дата публикации

SEMICONDUCTOR PACKAGE WITH ATTACHMENT AND/OR STOP STRUCTURES

Номер: US20210066162A1
Автор: CETEGEN Edvin, CHAN ARGUEDAS Sergio A., CHO Steve S., Haehn Nicholas S., HEATON Thomas, IBRAHIM Tarek A., Jain Rahul, MEHTA Vipul, Neal Nicholas, SINGH Antariksh Rao Pratap, VEHONSKY Jacob
Принадлежит:

A device is disclosed. The device includes a substrate, a die on the substrate, a thermal interface material (TIM) on the die, and solder bumps on a periphery of a top surface of the substrate. An integrated heat spreader (IHS) is formed on the solder bumps. The IHS covers the TIM. 1. A device , comprising:a substrate;a die on the substrate;a thermal interface material (TIM) on the die;solder bumps on a periphery of a top surface of the substrate, the solder bumps extending upward from the substrate; andan integrated heat spreader (IHS) on the solder bumps, the IHS covering the TIM.2. The device of claim 1 , wherein the solder bumps are aligned with the periphery of the IHS.3. The device of claim 1 , wherein the solder bumps have a thickness in the range of 10 to 200 um.4. The device of claim 1 , wherein the solder bumps are a part of a pattern of attachment material that includes solder bump portions and adhesive portions.5. The device of claim 1 , wherein the solder bumps are a part of a pattern of attachment material that includes solder bump portions at corners of the periphery of the top surface of the substrate and adhesive portions in other places on the periphery of the top surface of the substrate.6. The device of claim 1 , wherein the solder bumps are a part of a pattern of attachment material that includes adhesive portions at corners of the periphery of the top surface of the substrate.7. A device claim 1 , comprising:a substrate;solder bumps on a periphery of a top surface of the substrate, the solder bumps extending upward from the substrate and defining a space;a sealant on the top surface of the substrate, the sealant in the space defined by the solder bumps; andan integrated heat spreader (IHS) on the solder bumps and the sealant.8. The device of claim 7 , wherein the solder bumps are aligned with the periphery of the IHS.9. The device of claim 7 , wherein the solder bumps have a thickness in the range of 10 to 200 um.10. The device of claim 7 , ...

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Номер записи: 51
29-03-2018 дата публикации

THERMAL INTERFACES FOR INTEGRATED CIRCUIT PACKAGES

Номер: US20180090411A1
Автор: CETEGEN Edvin, Dhane Kedar, JHA Chandra M., Karhade Omkar G.
Принадлежит:

A thermal interface may include a wired network made of a first TIM, and a second TIM surrounding the wired network. A heat spreader lid may include a wired network attached to an inner surface of the heat spreader lid. An IC package may include a heat spreader lid placed over a first electronic component and a second electronic component. A first thermal interface may be formed between the first electronic component and the inner surface of the heat spreader lid, and a second thermal interface may be formed between the second electronic component and the inner surface of the heat spreader lid. The first thermal interface may include a wired network of a first TIM surrounded by a second TIM, while the second thermal interface may include the second TIM, without a wired network of the first TIM. Other embodiments may be described and/or claimed. 1. An integrated circuit (IC) package , comprising:a substrate;an electronic component having a first surface and a second surface opposite to the first surface, wherein the first surface is coupled to a surface of the substrate by a connector; and a wired network of a first thermal interface material (TIM); and', 'a second TIM, wherein the second TIM surrounds the wired network, and the second TIM is placed at an outer edge of the thermal interface., 'a heat spreader lid over the electronic component and the substrate, wherein the heat spreader lid is coupled to the electronic component through a thermal interface between an inner surface of the heat spreader lid and the second surface, and the thermal interface includes2. The IC package of claim 1 , wherein the wired network is deformable.3. The IC package of claim 1 , wherein the first TIM includes a metal claim 1 , a solder material claim 1 , copper claim 1 , aluminum claim 1 , tin claim 1 , nickel claim 1 , gold claim 1 , silver claim 1 , iron claim 1 , steel claim 1 , or a combination of metal and alloy.4. The IC package of claim 1 , wherein the second TIM includes an ...

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Номер записи: 52
08-04-2021 дата публикации

NO MOLD SHELF PACKAGE DESIGN AND PROCESS FLOW FOR ADVANCED PACKAGE ARCHITECTURES

Номер: US20210104490A1
Автор: CETEGEN Edvin, Haehn Nicholas S., Li Wei, Modi Mitul, Neal Nicholas, Viswanath Ram S.
Принадлежит:

Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer. 1. A semiconductor package , comprising:a plurality of dies on a substrate;an encapsulation layer over the substrate, wherein the encapsulation layer surrounds the plurality of dies; anda plurality of dummy silicon regions on the substrate, wherein the plurality of dummy silicon regions surround the plurality of dies and the encapsulation layer, wherein the plurality of dummy silicon regions are positioned on two or more edges of the substrate, and wherein the plurality of dummy silicon regions have a top surface that is substantially coplanar to a top surface of the plurality of dies.2. The semiconductor package of claim 1 , wherein the plurality of dummy silicon regions have a thickness that is substantially equal to a thickness of the plurality of dies.3. The semiconductor package of claim 1 , wherein the plurality of dummy silicon regions include one or more materials.4. The semiconductor package of claim 3 , wherein the one or more materials include silicon claim 3 , metals claim ...

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Номер записи: 53
26-03-2020 дата публикации

Liquid metal tim with stim-like performance with no bsm and bga compatible

Номер: US20200098661A1
Автор: Betsegaw GEBREHIWOT, Chia-Pin Chiu, Edvin Cetegen, Feras Eid, Joseph Petrini, Kelly Lofgreen
Принадлежит: Intel Corp

Embodiments include an electronic system and methods of forming an electronic system. In an embodiment, the electronic system may include a package substrate and a die coupled to the package substrate. In an embodiment, the electronic system may also include an integrated heat spreader (IHS) that is coupled to the package substrate. In an embodiment the electronic system may further comprise a thermal interface pad between the IHS and the die. In an embodiment the die is thermally coupled to the IHS by a liquid metal thermal interface material (TIM) that contacts the thermal interface pad.

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Номер записи: 54
16-05-2019 дата публикации

Underfill material flow control for reduced die-to-die spacing in semiconductor packages

Номер: US20190148268A1
Автор: Edvin Cetegen, Lars D. Skoglund, Nitin A. Deshpande, Omkar G. Karhade, Rajendra C. DIAS
Принадлежит: Intel Corp

Underfill material flow control for reduced die-to-die spacing in semiconductor packages and the resulting semiconductor packages are described. In an example, a semiconductor apparatus includes first and second semiconductor dies, each having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a common semiconductor package substrate by a plurality of conductive contacts, the first and second semiconductor dies separated by a spacing. A barrier structure is disposed between the first semiconductor die and the common semiconductor package substrate and at least partially underneath the first semiconductor die. An underfill material layer is in contact with the second semiconductor die and with the barrier structure, but not in contact with the first semiconductor die.

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Номер записи: 55
24-06-2021 дата публикации

FULL PACKAGE VAPOR CHAMBER WITH IHS

Номер: US20210195798A1
Автор: ARRINGTON Kyle, CETEGEN Edvin, CHAN ARGUEDAS Sergio A., Chang Je-Young, Hackenberg Ken P., Haehn Nicholas S., Mahajan Ravindranath V., MCCANN Aaron, Neal Nicholas, Sankman Robert L.
Принадлежит:

Embodiments include semiconductor packages. A semiconductor package includes dies on a package substrate, an integrated heat spreader (IHS) with a lid and sidewalls over the dies and package substrate, and a heatsink and a thermal interface material respectively on the IHS. The semiconductor package includes a vapor chamber defined by a surface of the package substrate and surfaces of the lid and sidewalls, and a wick layer in the vapor chamber. The wick layer is on the dies, package substrate, and IHS, where the vapor chamber has a vapor space defined by surfaces of the wick layer and lid of the IHS. The sidewalls are coupled to the package substrate with a sealant that hermetically seals the vapor chamber with the surfaces of the package substrate and the sidewalls and lid. The wick layer has a uniform or non-uniform thickness, and has porous materials including metals, powders, or graphite. 1. A semiconductor package , comprising:a die on a package substrate;an integrated heat spreader (IHS) over the die and the package substrate, wherein the IHS has a lid and a plurality of sidewalls;a sealant that couples the plurality of sidewalls of the IHS to the package substrate; anda layer below the lid of the IHS, wherein the layer is over the die and a top surface of the package substrate, and wherein the layer is on a bottom surface of the lid of the IHS and an interior surface of the plurality of sidewalls of the IHS.2. The semiconductor package of claim 1 , wherein a vapor chamber is defined by the top surface of the package substrate claim 1 , the bottom surface of the lid of the IHS claim 1 , and the interior surface of the plurality of sidewalls of the IHS claim 1 , wherein the vapor chamber is hermetically sealed with the sealant between the top surface of the package substrate and the plurality of sidewalls of the IHS claim 1 , and wherein the vapor chamber has a vapor space defined by a surface of the layer and the bottom surface of the lid of the IHS.3. The ...

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Номер записи: 56
25-06-2020 дата публикации

Dual strip backside metallization for improved alt-fli plating, koz minimization, test enhancement and warpage control

Номер: US20200203240A1
Автор: Edvin Cetegen, Nicholas S. HAEHN, Shankar Devasenathipathy
Принадлежит: Intel Corp

An integrated circuit assembly including a substrate having a surface including at least one area including contact points operable for connection with an integrated circuit die; and at least one ring surrounding the at least one area, the at least one ring including an electrically conductive material. A method of forming an integrated circuit assembly including forming a plurality of electrically conductive rings around a periphery of a die area of a substrate selected for attachment of at least one integrated circuit die, wherein the plurality of rings are formed one inside the other; and forming a plurality of contact points in the die area.

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Номер записи: 57
05-08-2021 дата публикации

SUBSTRATE WITH THERMAL INSULATION

Номер: US20210242107A1
Автор: CETEGEN Edvin, Haehn Nicholas S., Li Wei, Modi Mitul, Neal Nicholas
Принадлежит:

Embodiments herein relate to systems, apparatuses, or processes directed to a substrate that includes a first region to be coupled with a die, and a second region separate and distinct from the first region that has a lower thermal conductivity than the first region, where the second region is to thermally insulate the first region when the die is coupled to the first region. The thermal insulation of the second region may be used during a TCB process to increase the quality of each of the interconnects of the die by promoting a higher temperature at the connection points to facilitate full melting of solder. 1. An apparatus comprising:a substrate;a first region of the substrate to be coupled with a die;a second region of the substrate adjacent to the first region of the substrate, wherein the first region and the second region are separate and distinct regions and the second region has a lower thermal conductivity than the first region; andwherein the second region is to thermally insulate a portion of the first region when the die is coupled to the first region.2. The apparatus of claim 1 , wherein the first region includes one or more thermally conductive layers in the substrate.3. The apparatus of claim 2 , wherein the second region includes fewer thermally conductive layers then the first region.4. The apparatus of claim 2 , wherein the conductive layers are metallic layers.5. The apparatus of claim 4 , wherein the metallic layers include copper.6. The apparatus of claim 1 , wherein the second region is a volume removed from the substrate.7. The apparatus of claim 1 , wherein the second region is a dielectric.8. The apparatus of claim 1 , further comprising a third region of the substrate adjacent to the first region of the substrate claim 1 , wherein the first region claim 1 , the second region claim 1 , and the third region are different regions and the third region has a lower thermal conductivity than the first region.9. A package claim 1 , comprising:a ...

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Номер записи: 58
30-09-2021 дата публикации

OPEN CAVITY BRIDGE CO-PLANAR PLACEMENT ARCHITECTURES AND PROCESSES

Номер: US20210305132A1
Автор: Agraharam Sairam, CETEGEN Edvin, Deshpande Nitin, Dubey Manish, Karhade Omkar, Modi Mitul, Raorane Digvijay
Принадлежит:

Embodiments disclosed herein include multi-die packages with open cavity bridges. In an example, an electronic apparatus includes a package substrate having alternating metallization layers and dielectric layers. The package substrate includes a first plurality of substrate pads and a second plurality of substrate pads. The package substrate also includes an open cavity between the first plurality of substrate pads and the second plurality of substrate pads, the open cavity having a bottom and sides. The electronic apparatus also includes a bridge die in the open cavity, the bridge die including a first plurality of bridge pads, a second plurality of bridge pads, and conductive traces. An adhesive layer couples the bridge die to the bottom of the open cavity. A gap is laterally between the bridge die and the sides of the open cavity, the gap surrounding the bridge die.

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Номер записи: 59
03-10-2019 дата публикации

Micro-electronic package with substrate protrusion to facilitate dispense of underfill between a narrow die-to-die gap

Номер: US20190304808A1
Автор: Edvin Cetegen, Nisha ANANTHAKRISHNAN, Shan Zhong, Sushrutha GUJJULA, Vipul MEHTA, Yuying Wei, Ziyin LIN
Принадлежит: Intel Corp

A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die.

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Номер записи: 60
21-06-2018 дата публикации

Integrated circuit packages with plates

Номер: WO2018111249A1
Автор: Edvin Cetegen, Omkar G. Karhade, Sandeep B. Sane
Принадлежит: Intel Corporation

Disclosed herein are integrated circuit (IC) packages with plates, as well as related devices and methods. For example, in some embodiments, an IC package may include: a package substrate; a plurality of electrical components secured to a face of the package substrate; and a plate secured to the plurality of electrical components with an adhesive such that the plurality of electrical components are between the plate and the package substrate.

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Номер записи: 61
03-10-2023 дата публикации

Corner guard for improved electroplated first level interconnect bump height range

Номер: US11776864B2
Автор: Antariksh Rao Pratap SINGH, Edvin Cetegen, Jacob VEHONSKY, Nicholas Neal, Nicholas S. HAEHN, Rahul Jain, Sergio CHAN ARGUEDAS, Steve S. Cho, Tarek Ibrahim, Thomas Heaton
Принадлежит: Intel Corp

Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment an electronic package comprises a package substrate, and a first level interconnect (FLI) bump region on the package substrate. In an embodiment, the FLI bump region comprises a plurality of pads, and a plurality of bumps, where each bump is over a different one of the plurality of pads. In an embodiment, the electronic package further comprises a guard feature adjacent to the FLI bump region. In an embodiment, the guard feature comprises, a guard pad, and a guard bump over the guard pad, wherein the guard feature is electrically isolated from circuitry of the electronic package.

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Номер записи: 62
26-10-2023 дата публикации

Soldered metallic reservoirs for enhanced transient and steady-state thermal performance

Номер: US20230343723A1
Автор: Antariksh Rao Pratap SINGH, Edvin Cetegen, Jacob VEHONSKY, Nicholas Neal, Nicholas S. HAEHN, Rahul Jain, Sergio CHAN ARGUEDAS, Steve S. Cho, Tarek A. Ibrahim, Thomas Heaton
Принадлежит: Intel Corp

Embodiments disclosed herein include electronic packages with thermal solutions. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and an integrated heat spreader (IHS) that is thermally coupled to a surface of the first die. In an embodiment, the IHS comprises a main body having an outer perimeter, and one or more legs attached to the outer perimeter of the main body, wherein the one or more legs are supported by the package substrate. In an embodiment, the electronic package further comprises a thermal block between the package substrate and the main body of the IHS, wherein the thermal block is within the outer perimeter of the main body.

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Номер записи: 63
03-10-2023 дата публикации

Micro-electronic package with substrate protrusion to facilitate dispense of underfill between a narrow die-to-die gap

Номер: US11776821B2
Автор: Edvin Cetegen, Nisha ANANTHAKRISHNAN, Shan Zhong, Sushrutha GUJJULA, Vipul MEHTA, Yuying Wei, Ziyin LIN
Принадлежит: Intel Corp

A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die. An encapsulant is over the protrusion of the substrate, the encapsulant extending beneath the first die, and the encapsulant extending beneath the second die.

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Номер записи: 64
25-04-2024 дата публикации

No mold shelf package design and process flow for advanced package architectures

Номер: US20240136326A1
Автор: Edvin Cetegen, Mitul Modi, Nicholas Neal, Nicholas S. HAEHN, Ram S. Viswanath, Wei Li
Принадлежит: Intel Corp

Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.

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Номер записи: 65
23-06-2022 дата публикации

Mikroelektronische strukturen einschliesslich brücken

Номер: DE102021133812A1
Автор: Anurag TRIPATHI, Edvin Cetegen, Nitin A. Deshpande, Omkar G. Karhade
Принадлежит: Intel Corp

Hier werden mikroelektronische Strukturen einschließlich Brücken sowie zugehörige Baugruppen und Verfahren offenbart. Bei manchen Ausführungsformen kann eine mikroelektronische Struktur ein Substrat und eine Brücke beinhalten.

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Номер записи: 66
16-12-2021 дата публикации

Mikroelektronische Strukturen mit Brücken

Номер: DE102020132237A1
Автор: Anurag TRIPATHI, Edvin Cetegen, Jan Krajniak, Jingyi Huang, Jinhe Liu, Malavarayan Sankarasubramanian, Manish Dubey, Mohit Bhatia, Nitin A. Deshpande, Omkar G. Karhade, Sairam Agraharam, Wei Li
Принадлежит: Intel Corp

Hier werden mikroelektronische Strukturen mit Brücken sowie zugehörige Anordnungen und Verfahren offenbart. In einigen Ausführungsformen kann eine mikroelektronische Struktur ein Substrat und eine Brücke umfassen.

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Номер записи: 67
27-12-2021 дата публикации

ブリッジを含むマイクロエレクトロニクス構造体

Номер: JP2021197540A
Автор: A Deshpande Nitin, Agraharam Sairam, Bhatia Mohit, CETEGEN Edvin, Dubey Manish, G Karhade Omkar, Jingyi Huang, Jinhe Liu, KRAJNIAK Jan, Sankarasubramanian Malavarayan, Tripathi Anurag, Wei Li, アグラハラム サイラム, エー． デシュパンデ ニティン, クラジニャク ジャン, サンカラスブラマニアン マラバラヤン, ジー． カーハデ オムカー, セテジェン エドヴィン, デュベイ マニシュ, トライパシ アヌラグ, バティア モヒト, ホァン ジンイ, リ ウェイ, リウ ジンヘ
Принадлежит: Intel Corp

【課題】パッケージ基板とダイとの間の達成可能な相互接続密度、信号伝達速度および小型化が可能なマイクロエレクトロニクス構造体を提供する。【解決手段】マイクロエレクトロニクス構造体において、基板１０２と、基板の上面におけるキャビティ１２０と、キャビティ内のブリッジコンポーネント１１０と、を備える。ブリッジコンポーネント１１０は、第１の面および対向する第２の面を含む。ブリッジコンポーネント１１０の第２の面は、ブリッジコンポーネント１１０の第１の面と基板１０２との間にある。ブリッジコンポーネント１１０は、第１の面に第１の相互接続材料を含み、第２の面に第２の相互接続材料を含む。第１の相互接続材料は、第２の相互接続材料とは異なる材料組成を有する。【選択図】図１

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Номер записи: 68
26-05-2022 дата публикации

Micro-electronic package with substrate protrusion to facilitate dispense of underfill between a narrow die-to-die gap

Номер: US20220165585A1
Автор: Edvin Cetegen, Nisha ANANTHAKRISHNAN, Shan Zhong, Sushrutha GUJJULA, Vipul MEHTA, Yuying Wei, Ziyin LIN
Принадлежит: Intel Corp

A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die.

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Номер записи: 69
19-07-2023 дата публикации

Semiconductor device with tall and slender interconnecting bumps and corresponding manufacturing method

Номер: EP4163965A3
Автор: Edvin Cetegen, Gang Duan, Jacob VEHONSKY, Nicholas Haehn, Onur OZCAN, Steve Cho
Принадлежит: Intel Corp

A semiconductor device (100) includes a first plate-like element (104) having a first substantially planar connection surface (112) with a first connection pad (114) and a second plate-like element (102) having a second substantially planar connection surface (110) with a second connection pad (114) corresponding to the first connection pad (114); and a connection (106+108) electrically and physically coupling the first and second plate-like elements (104, 102) and arranged between the first and second connection pads (114). The connection (106+108) includes an elongate element (108) arranged on the first connection pad (114) and extending toward the second connection pad (114) and solder (106) in contact with the second connection pad (114) and the elongate element (108). The first or second plate-like element (104, 102) may comprise a die, in particular, a bridge die. An electronic system (800) may comprise the semiconductor device (100) and an electrical component electrically coupled to the first plate-like element, wherein the electrical component may comprise an antenna (878), a touch screen and/or a personal computer. A method of assembling a semiconductor device (100) comprises: heating first and second plate-like elements (104, 102) to a solder reflow temperature; and pressing the first plate-like element (104) against the second plate-like element (102) with pressing an elongate element (109) extending from a first connection pad (114) on the first plate-like element (104) toward a second connection pad (114) on the second plate-like element (102). The resulting connection formation (e.g., between a solder bump (107) on the second connection pad (114) and a corresponding elongate element (109)) may depend on the location of the connection and the deformations, warping, or other factors that affect the space between the first and second plate-like elements (104, 102) at various locations. A preassembled height (122) of the elongate element (109) may ...

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Номер записи: 70
06-06-2024 дата публикации

Symmetric dummy bridge design for fli alignment improvement

Номер: US20240186251A1
Автор: Alexander Aguinaga, Edvin Cetegen, Gang Duan, Lawrence ROSS, Mine KAYA, Minglu LIU, Yang Wu, Yuting Wang
Принадлежит: Intel Corp

Embodiments disclosed herein include package architectures. In an embodiment, the package architecture comprises a package substrate, a first bridge in the package substrate, where the first bridge includes conductive routing, and a second bridge in the package substrate. In an embodiment, the package architecture further comprises a third bridge in the package substrate, where the second bridge and the third bridge are positioned symmetrically about the first bridge.

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Номер записи: 71
23-12-2020 дата публикации

Multi-package assemblies having foam structures for warpage control

Номер: EP3754700A1
Автор: Baris Bicen, Edvin Cetegen, Gang Duan, Mufei Yu, Rahul Manepalli
Принадлежит: Intel Corp

An integrated circuit package may be formed comprising a substrate that includes a mold material layer and a signal routing layer, wherein the mold material layer comprises at least one bridge and at least one foam structure embedded in a mold material. In one embodiment, the substrate may include the mold material of the mold material layer filling at least a portion of cells within the foam structure. In a further embodiment, at least two integrated circuit devices may be attached to the substrate, such that the bridge provides device-to-device interconnection between the at least two integrated circuit devices. In a further embodiment, the integrated circuit package may be electrically attached to an electronic board.

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Номер записи: 72
12-04-2023 дата публикации

Semiconductor device with tall and slender interconnecting bumps and corresponding manufacturing method

Номер: EP4163965A2
Автор: Edvin Cetegen, Gang Duan, Jacob VEHONSKY, Nicholas Haehn, Onur OZCAN, Steve Cho
Принадлежит: Intel Corp

A semiconductor device (100) includes a first plate-like element (104) having a first substantially planar connection surface (112) with a first connection pad (114) and a second plate-like element (102) having a second substantially planar connection surface (110) with a second connection pad (114) corresponding to the first connection pad (114); and a connection (106+108) electrically and physically coupling the first and second plate-like elements (104, 102) and arranged between the first and second connection pads (114). The connection (106+108) includes an elongate element (108) arranged on the first connection pad (114) and extending toward the second connection pad (114) and solder (106) in contact with the second connection pad (114) and the elongate element (108). The first or second plate-like element (104, 102) may comprise a die, in particular, a bridge die. An electronic system (800) may comprise the semiconductor device (100) and an electrical component electrically coupled to the first plate-like element, wherein the electrical component may comprise an antenna (878), a touch screen and/or a personal computer. A method of assembling a semiconductor device (100) comprises: heating first and second plate-like elements (104, 102) to a solder reflow temperature; and pressing the first plate-like element (104) against the second plate-like element (102) with pressing an elongate element (109) extending from a first connection pad (114) on the first plate-like element (104) toward a second connection pad (114) on the second plate-like element (102). The resulting connection formation (e.g., between a solder bump (107) on the second connection pad (114) and a corresponding elongate element (109)) may depend on the location of the connection and the deformations, warping, or other factors that affect the space between the first and second plate-like elements (104, 102) at various locations. A preassembled height (122) of the elongate element (109) may ...

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Номер записи: 73
06-06-2024 дата публикации

Thermocompression bonding tool for panel-level thermo-compression bonding

Номер: US20240186280A1
Автор: Andrey GUNAWAN, Anurag TRIPATHI, Edvin Cetegen, Gang Duan, Kartik Srinivasan, Mihir Oka, Mine KAYA, Minglu LIU, Yuting Wang
Принадлежит: Intel Corp

The present disclosure is directed to an apparatus having a bond head configured to heat and compress a semiconductor package assembly, and a bonding stage configured to hold the semiconductor package assembly, wherein the bonding stage comprises a ceramic material including silicon and either magnesium or indium.

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Номер записи: 74
23-03-2023 дата публикации

Semiconductor Chip Package Having Internal I/O Structures With Modulated Thickness To Compensate For Die/Substrate Warpage

Номер: US20230086649A1
Автор: Edvin Cetegen, Jacob VEHONSKY, Nicholas S. HAEHN, Onur Ozkan, Steve Cho
Принадлежит: Intel Corp

An apparatus is described. The apparatus includes I/O structures having pads and solder balls to couple with a semiconductor chip, wherein, a first subset of pads and/or solder balls of the pads and solder balls that approach the semiconductor chip during coupling of the semiconductor chip to the I/O structures are thinner than a second subset of pads and/or solder balls of the pads and solder balls that move away from the semiconductor chip during the coupling of the semiconductor chip to the I/O structures.

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Номер записи: 75
01-08-2024 дата публикации

Protruding sn substrate features for epoxy flow control

Номер: US20240258183A1
Автор: Antariksh Rao Pratap SINGH, Edvin Cetegen, Jacob VEHONSKY, Nicholas Neal, Nicholas S. HAEHN, Rahul Jain, Sergio CHAN ARGUEDAS, Steve S. Cho, Tarek Ibrahim, Thomas Heaton, Vipul MEHTA
Принадлежит: Intel Corp

Embodiments disclosed herein include electronic packages with underfill flow control features. In an embodiment, an electronic package comprises a package substrate and a plurality of interconnects on the package substrate. In an embodiment, a die is coupled to the package substrate by the plurality of interconnects and a flow control feature is adjacent on the package substrate. In an embodiment, the flow control feature is electrically isolated from circuitry of the electronic package. In an embodiment, the electronic package further comprises an underfill surrounding the plurality of interconnects and in contact with the flow control feature.

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Номер записи: 76
27-06-2024 дата публикации

Enhanced nozzle for disaggregated die handling during thermal compression bonding

Номер: US20240213074A1
Автор: Albert KAMGA, Edvin Cetegen, James Mellody, Mark SALTAS, Mine KAYA, Rajesh Kumar Neerukatti, Tony Dambrauskas
Принадлежит: Intel Corp

This disclosure describes nozzle designs for holding disaggregated die flat in a bonding process. The nozzle designs may have trenches extending radially outward from the center of the nozzle to the corners, such as in a snowflake pattern. The trenches may be positioned to be axially unaligned with any mold dishes of the disaggregated die when lifting the disaggregated die. The trenches may have a depth of at least 200 micrometers to allow for sufficient air flow to prevent warpage of the disaggregated die.

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Номер записи: 77
10-09-2024 дата публикации

No mold shelf package design and process flow for advanced package architectures

Номер: US12087731B2
Автор: Edvin Cetegen, Mitul Modi, Nicholas Neal, Nicholas S. HAEHN, Ram S. Viswanath, Wei Li
Принадлежит: Intel Corp

Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.

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Номер записи: 78
20-08-2024 дата публикации

Dummy die structures of a packaged integrated circuit device

Номер: US12068222B2
Автор: Digvijay Raorane, Dingying Xu, Edvin Cetegen, Joseph VAN NAUSDLE, Mitul Modi, Nicholas Haehn, Omkar Karhade, Vaibhav Agrawal, Yiqun Bai, Ziyin LIN
Принадлежит: Intel Corp

Techniques and mechanisms for facilitating heat conductivity in a packaged device with a dummy die. In an embodiment, a packaged device comprises a substrate and one or more IC die coupled to a surface thereof. A dummy die, adjacent to an IC die and coupled to a region of the substrate, comprises a polymer resin and a filler. A package mold structure of the packaged device adjoins respective sides of the IC die and the dummy die, and adjoins the surface of the substrate. In another embodiment, a first CTE of the dummy die is less than a second CTE of the package mold structure, and a first thermal conductivity of the dummy die is greater than a second thermal conductivity of the package mold structure.

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Номер записи: 79