Semiconductor structure

The present disclosure relates to a semiconductor structure, which includes a semiconductor substrate, an insulating layer and a plurality of traces. The insulating layer is disposed on the semiconductor substrate. The plurality of traces are disposed between the insulating layer and the semiconductor substrate. At least one of the plurality of traces includes a plurality of apertures, wherein a total area of the plurality of apertures ranges from 10% to 70% of a surface area of the at least one trace.

MEMS Device

A MEMS device is disclosed. In an embodiment a MEMS device includes a substrate having an active region and at least one integrated electrical and mechanical connection element configured to electrically and mechanically mount the MEMS device to a carrier, wherein the connection element comprises a stress-reducing structure.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF, WIRING BOARD AND MANUFACTURING METHOD THEREOF, SEMICONDUCTOR PACKAGE, AND ELECTRONIC APPARATUS

A terminal pad is formed on an active surface of an LSI chip, and a composite barrier metal layer is provided over this terminal pad. In the composite barrier metal layer, a plurality of low-elasticity particles composed of a silicone resin is dispersed throughout a metal base phase composed of NiP. The composite barrier metal layer has a thickness of, e.g., 3 m, and the low-elasticity particles have a diameter of, e.g., 1 m. A semiconductor device is mounted on a wiring board by bonding a solder bump to the composite barrier metal layer. The low-elasticity particles are thereby allowed to deform according to the applied stress when the semiconductor device is bonded to the wiring board via the solder bump, whereby the stress can be absorbed.

Cu core ball, solder joint, foam solder, and solder paste

The present invention suppresses occurrences of soft errors while assuring alignment properties when mounting a Cu core ball on an electrode. A Cu core ball (11) is provided with a Cu ball (1) and a metal layer (2) that coats the surface of this Cu ball (1). The metal layer (2) is formed from one or more elements selected from Ni, Co, and Fe. The Cu ball (1) is such that the purity is 99.9 - 99.995%, the U content is 5 ppb or less, the Th content is 5 ppb or less, the total amount for the content of at least one of Pb and Bi is 1 ppm or greater, the sphericity is 0.95 or greater, and the alpha dose is 0.0200 cph/cm2 or less.

OSP treated Cu ball, solder joint, foam solder, and solder paste

The present invention assures alignment properties when mounting a Cu ball on an electrode while suppressing occurrences of soft errors. An OSP treated Cu ball (11) is provided with a Cu ball (1) and an organic coating (2), containing an imidazole compound, that covers the surface of this Cu ball (1). The Cu ball (1) is such that the purity is 99.9 - 99.995%, the U content is 5 ppb or less, the Th content is 5 ppb or less, the Pb or Bi content or the total amount for the content for both Pb and Bi together is 1 ppm or greater, the sphericity is 0.95 or greater, and the alpha dose is 0.0200 cph/cm2 or less.

Method of bonding solder pads of flip-chip package

Disclosed herein is a method of bonding solder pads of a flip-chip package. This invention relates to a method of bonding solder pads having different sizes to each other, when a bonding operation is executed between a chip and a PCB, between chips, or between PCBs. On a side having a larger solder pad, a general solder ball is used. Conversely, on a side having a smaller solder pad, a solder ball having a core is used. The core serves to maintain a predetermined interval between the chip and the PCB or between the chips, after the bonding operation has been completed. The solder bonded parts are aligned with each other so as to perform a final bonding operation. In a conventional flip-chip package, solder pads provided on a bonded part must have the same or similar size. According to this invention, even if the size difference between the solder pads is large, bonding is possible, thus ensuring electrical and mechanical reliability.

Magnetic contacts

Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.

Polyamide-imide resin and production method of polyamide-imide resin

MEMS-Vorrichtung

Eine MEMS-Vorrichtung (100) wird beschrieben, wobei die MEMS-Vorrichtung ein Substrat (1) mit einem aktiven Gebiet (2) und mindestens ein integriertes elektrisches und mechanisches Verbindungselement (3) zum elektrischen und mechanischen Befestigen der MEMS-Vorrichtung an einem Träger umfasst, wobei das Verbindungselement eine spannungsreduzierende Struktur (30) umfasst.

Semiconductor structure

Semiconductor Device and Manufacturing Method Thereof, Semiconductor Package, and Electronic Apparatus

A terminal pad is formed on an active surface of an LSI chip, and a composite barrier metal layer is provided over this terminal pad. In the composite barrier metal layer, a plurality of low-elasticity particles composed of a silicone resin is dispersed throughout a metal base phase composed of NiP. The composite barrier metal layer has a thickness of, e.g., 3 mum, and the low-elasticity particles have a diameter of, e.g., 1 mum. A semiconductor device is mounted on a wiring board by bonding a solder bump to the composite barrier metal layer. The low-elasticity particles are thereby allowed to deform according to the applied stress when the semiconductor device is bonded to the wiring board via the solder bump, whereby the stress can be absorbed.

SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR, WIRING BOARD AND PRODUCTION METHOD THEREFOR, SEMICONDUCTOR PACKAGE AND ELECTRONIC APPARATUS

A terminal pad is formed on the active surface of an LSI chip, and composite barrier metal layer is provided on this terminal pad. A plurality of low-elasticity-modulus particles consisting of silicone resin are dispersed into a metal parent phase consisting of NiP in the composite barrier metal layer. The film thickness of the composite barrier layer is, for example, 3 μm, and the diameter of the low-elasticity-modulus particles is, for example, 1μm. With the composite barrier metal layer connected with a solder bump, a semiconductor device is mounted on a wiring board. Accordingly, since low-elasticity-modulus particles are deformed according to an applied stress when the semiconductor device is connected with the wiring board via the solder bump, the stress can be absorbed.

Semiconductor device and production method therefor, wiring board and production method therefor, semiconductor package and electronic apparatus

Semiconductor element and forming method

Methods for forming pillar bumps on semiconductor wafers

The subject matter contained herein discloses methods for forming a vertical metallic pillar overlying an under bump metal pad further overlying a semiconductor substrate, and applying a discrete solder cap on a top surface of the pillar, wherein the metallic pillar is defined by at least one photoresist layer. The method includes heating a multi-element metallic paste containing a variable amount of metallic powder, a melting point depressant and a flux such that the metal powder sinters to form the metallic pillar and simultaneously adheres the metallic pillar to the underbump metal pad.

Doping minor elements into metal bumps

SEMICONDUCTOR PACKAGE HAVING MAGNETIC INTERCONNECTS AND RELATED METHODS

Implementations of semiconductor packages may include a first die including a plurality of contact pads, a second die including a plurality of contact pads, a plurality of solder interconnects bonding the plurality of contact pads of the first die to the plurality of contact pads of the second die, and a plurality of magnetic particles each coated in an oxide included in each of the plurality of solder interconnects.

MEMS device stress-reducing structure

A MEMS device is disclosed. In an embodiment a MEMS device includes a substrate having an active region and at least one integrated electrical and mechanical connection element configured to electrically and mechanically mount the MEMS device to a carrier, wherein the connection element comprises a stress-reducing structure.

DOPING MINOR ELEMENTS INTO METAL BUMPS, CAPABLE OF ACCURATELY CONTROLLING THE THICKNESS OF SOME ELEMENT INCLUDING LAYER

PURPOSE: Doping minor elements into metal bumps are provided to improve manufacturing costs and the property of a metal pump by adding some elements of a plurality of types. CONSTITUTION: In doping minor elements into metal bumps, a wafer including a substrate(10) is provided. A semiconductor device(14) is formed in the surface of the substrate. An interconnect structure(12) is electrically combined with the semiconductor device. The interconnect structure comprises an inter-layer dielectric and an inter-metal dielectric. A metal pad(28) is formed on the interconnect structure. COPYRIGHT KIPO 2012 ...

Method of bonding solder pads of flip-chip package

Disclosed herein is a method of bonding solder pads of a flip-chip package. This invention relates to a method of bonding solder pads having different sizes to each other, when a bonding operation is executed between a chip and a PCB, between chips, or between PCBs. On a side having a larger solder pad, a general solder ball is used. Conversely, on a side having a smaller solder pad, a solder ball having a core is used. The core serves to maintain a predetermined interval between the chip and the PCB or between the chips, after the bonding operation has been completed. The solder bonded parts are aligned with each other so as to perform a final bonding operation. In a conventional flip-chip package, solder pads provided on a bonded part must have the same or similar size. According to this invention, even if the size difference between the solder pads is large, bonding is possible, thus ensuring electrical and mechanical reliability.

Method for producing metal ball, joining material, and metal ball

Produced is a metal ball which suppresses an emitted α dose. Contained are the steps of melting a pure metal by heating the pure metal at a temperature which is higher than a boiling point of an impurity to be removed, higher than a melting point of the pure metal, and lower than a boiling point of the pure metal, the pure metal containing a U content of 5 ppb or less, a Th content of 5 ppb or less, purity of 99.9% or more and 99.995% or less, and a Pb or Bi content or a total content of Pb and Bi of 1 ppm or more, and the pure metal having the boiling point higher than the boiling point at atmospheric pressure of the impurity to be removed; and sphering the molten pure metal in a ball.

Doping Minor Elements into Metal Bumps

A method of forming a device includes providing a substrate, and forming a solder bump over the substrate. A minor element is introduced to a region adjacent a top surface of the solder bump. A re-flow process is then performed to the solder bump to drive the minor element into the solder bump.

METHOD FOR MELTING A SOLDER MATERIAL IN ALTERNATING MAGNETIC FIELDS

Die Erfindung betrifft ein Verfahren zum Aufschmelzen eines Lotmaterials zum Fügen und/oder Lösen einer Lötverbindung, wobei im Lotmaterial eingebrachte Nanopartikel magnetische Energie aus einem magnetischen Wechselfeld dissipieren, im Wesentlichen durch Relaxationsprozesse nach Brown und Neel, was zur Erwärmung und schließlich zum Aufschmelzen des Lotmaterials führt. Des Weiteren betrifft die Erfindung eine Baugruppe, welche wenigstens eine Lötverbindung aufweist, die durch das erfindungsgemäße Verfahren gebildet oder gelöst wird.

DOPING MINOR ELEMENTS INTO METAL BUMPS

Semiconductor device and production method therefor, wiring board and production method therefor, semiconductor package and electronic apparatus

A terminal pad is formed on the active surface of an LSI chip, and composite barrier metal layer is provided on this terminal pad. A plurality of low-elasticity-modulus particles consisting of silicone resin are dispersed into a metal parent phase consisting of NiP in the composite barrier metal layer. The film thickness of the composite barrier layer is, for example, 3 [mu]m, and the diameter of the low-elasticity-modulus particles is, for example, 1[mu]m. With the composite barrier metal layer connected with a solder bump, a semiconductor device is mounted on a wiring board. Accordingly, since low-elasticity-modulus particles are deformed according to an applied stress when the semiconductor device is connected with the wiring board via the solder bump, the stress can be absorbed.

MAGNETIC CONTACTS

Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.

Semiconductor structure

Semiconductor package having magnetic interconnects and related methods

Implementations of semiconductor packages may include a first die including a plurality of contact pads, a second die including a plurality of contact pads, a plurality of solder interconnects bonding the plurality of contact pads of the first die to the plurality of contact pads of the second die, and a plurality of magnetic particles each coated in an oxide included in each of the plurality of solder interconnects.

Magnetic contacts

Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.

Tools and methods for forming conductive bumps on microelectronic elements

A method of making a microelectronic assembly includes providing a microelectronic element having a front face and contact pads accessible at the front face, providing a dispensing tool containing a molten metal and having a discharge port for dispensing the molten metal, and aligning the discharge port of the dispensing tool with one of the contact pads of the microelectronic element. A mass of the molten metal is dispensed through the discharge port and onto the one of the contact pads of the microelectronic element; and ultrasonic waves are applied to the mass of molten metal during the dispensing step for facilitating wetting of the mass of molten metal with the one of the contact pads of the microelectronic element.

Semiconductor Device and Manufacturing Method Thereof, Semiconductor Package, and Electronic Apparatus

A terminal pad is formed on an active surface of an LSI chip, and a composite barrier metal layer is provided over this terminal pad. In the composite barrier metal layer, a plurality of low-elasticity particles composed of a silicone resin is dispersed throughout a metal base phase composed of NiP. The composite barrier metal layer has a thickness of, e.g., 3 μm, and the low-elasticity particles have a diameter of, e.g., 1 μm. A semiconductor device is mounted on a wiring board by bonding a solder bump to the composite barrier metal layer. The low-elasticity particles are thereby allowed to deform according to the applied stress when the semiconductor device is bonded to the wiring board via the solder bump, whereby the stress can be absorbed.

METHODS FOR FORMING PILLAR BUMPS ON SEMICONDUCTOR WAFERS

The subject matter contained herein discloses methods for forming a vertical metallic pillar overlying an under bump metal pad further overlying a semiconductor substrate, and applying a discrete solder cap on a top surface of the pillar, wherein the metallic pillar is defined by at least one photoresist layer. The method includes heating a multi-element metallic paste containing a variable amount of metallic powder, a melting point depressant and a flux such that the metal powder sinters to form the metallic pillar and simultaneously adheres the metallic pillar to the underbump metal pad.

Doping minor elements into metal bumps

A method of forming a device includes providing a substrate, and forming a solder bump over the substrate. A minor element is introduced to a region adjacent a top surface of the solder bump. A re-flow process is then performed to the solder bump to drive the minor element into the solder bump.

Doping Minor Elements into Metal Bumps

A method of forming a device includes providing a substrate, and forming a solder bump over the substrate. A minor element is introduced to a region adjacent a top surface of the solder bump. A re-flow process is then performed to the solder bump to drive the minor element into the solder bump.

Methods for forming pillar bumps on semiconductor wafers

The subject matter contained herein discloses methods for forming a vertical metallic pillar overlying an under bump metal pad further overlying a semiconductor substrate, and applying a discrete solder cap on a top surface of the pillar, wherein the metallic pillar is defined by at least one photoresist layer. The method includes heating a multi-element metallic paste containing a variable amount of metallic powder, a melting point depressant and a flux such that the metal powder sinters to form the metallic pillar and simultaneously adheres the metallic pillar to the under bump metal pad.

Magnetic contacts

Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.

Doping minor elements into metal bumps

A method of forming a device includes providing a substrate, and forming a solder bump over the substrate. A minor element is introduced to a region adjacent a top surface of the solder bump. A re-flow process is then performed to the solder bump to drive the minor element into the solder bump.

Methods for forming pillar bumps on semiconductor wafers

金属球の製造方法、接合材料及び金属球

Polyamide-imide resin and production method of polyamide-imide resin

The present invention produces a metal ball which suppresses a radiated [alpha] dose. This method involves a step for melting a pure metal by heating the following at a temperature which is higher than the boiling point of an impurity to be removed, higher than the melting point of the pure metal, and lower than the boiling point of the pure metal: a pure metal which has a higher boiling point than the boiling point, according to atmospheric pressure, of the impurity to be removed among impurities contained in the pure metal, has a U content of 5ppb or less, has a Th content of 5ppb or less, has a purity of 99.9-99.995%, inclusive, and has a Pb content, Bi content, or a total of the combined Pb and Bi content which is 1ppm or more. The method also includes a step for forming balls from the melted pure metal by making the same into a spherical shape.

Method for Producing Metal Ball, Joining Material, and Metal Ball

Produced is a metal ball which suppresses an emitted α dose. Contained are the steps of melting a pure metal by heating the pure metal at a temperature which is higher than a boiling point of an impurity to be removed, higher than a melting point of the pure metal, and lower than a boiling point of the pure metal, the pure metal containing a U content of 5 ppb or less, a Th content of 5 ppb or less, purity of 99.9% or more and 99.995% or less, and a Pb or Bi content or a total content of Pb and Bi of 1 ppm or more, and the pure metal having the boiling point higher than the boiling point at atmospheric pressure of the impurity to be removed; and sphering the molten pure metal in a ball.

MAGNETIC CONTACTS

Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.

SEMICONDUCTOR STRUCTURE

The present disclosure relates to a semiconductor structure, which includes a semiconductor substrate, an insulating layer and a plurality of wirings. The insulating layer is disposed on the semiconductor substrate. The plurality of wirings are disposed between the semiconductor substrate and the insulating layer. At least one wiring of the wirings includes a plurality of holes, and a total area of the holes is from 10% to 70% of a surface area of the at least one wiring.

Semiconductor element and forming method

Chip package with plank stack of semiconductor dies

In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are separated by a mechanical spacer (such as a filler material or an adhesive). Moreover, the chip package includes a substrate at a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the substrate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as: solder, stud bumps, plated traces, wire bonds, spring connectors, a conductive adhesive and/or an anisotropic conducting film. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the substrate.

Integrated circuit packaging system with external wire connection and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a package carrier; mounting an integrated circuit to the package carrier; forming an external wire on the package carrier and adjacent to the integrated circuit; forming an encapsulation on the package carrier over the external wire; and forming a hole in the encapsulation with the external wire and a portion of the package carrier exposed from the encapsulation.

Miniaturized Electrical Component Comprising an MEMS and an ASIC and Production Method

The invention relates to a miniaturized electrical component comprising an MEMS chip and an ASIC chip. The MEMS chip and the ASIC chip are disposed on top of each other; an internal mounting of MEMS chip and ASIC chip is connected to external electrical terminals of the electrical component by means of vias through the MEMS chip or the ASIC chip.

Sapphire substrate configured to form light emitting diode chip providing light in multi-directions, light emitting diode chip, and illumination device

A sapphire substrate configured to form a light emitting diode (LED) chip providing light in multi-directions, a LED chip and an illumination device are provided in the present invention. The sapphire substrate includes a growth surface and a second main surface opposite to each other. A thickness of the sapphire substrate is thicker than or equal to 200 micrometers. The LED chip includes the sapphire substrate and at least one LED structure. The LED structure is disposed on the growth surface and forms a first main surface where light emitted from with a part of the growth surface without the LED structures. At least a part of light beams emitted from the LED structure pass through the sapphire substrate and emerge from the second main surface. The illumination device includes at least one LED chip and a supporting base. The LED chip is disposed on the supporting base.

Semiconductor Device Apparatus and Assembly with Opposite Die Orientations

An electronic apparatus includes a base substrate, the base substrate including an interconnect. The electronic apparatus further includes a first die including a first semiconductor device, the first semiconductor device being coupled to the interconnect, and further includes a second die including a second semiconductor device, the second semiconductor device being coupled to the interconnect. The first and second die are attached to the base substrate in opposite orientations.

Lead-free solder alloy, solder joining material, electronic circuit mounting substrate, and electronic control device

A lead-free solder alloy includes 2.0% by mass or more and 4.0% by mass or less of Ag, 0.3% by mass or more and 0.7% by mass or less of Cu, 1.2% by mass or more and 2.0% by mass or less of Bi, 0.5% by mass or more and 2.1% by mass or less of In, 3.0% by mass or more and 4.0% by mass or less of Sb, 0.001% by mass or more and 0.05% by mass or less of Ni, 0.001% by mass or more and 0.01% by mass or less of Co, and the balance being Sn.

Planar integrated circuit package interconnects

Generally discussed herein are systems, methods, and apparatuses that include conductive pillars that are about co-planar. According to an example, a technique can include growing conductive pillars on respective exposed landing pads of a substrate, situating molding material around and on the grown conductive pillars, removing, simultaneously, a portion of the grown conductive pillars and the molding material to make the grown conductive pillars and the molding material about planar, and electrically coupling a die to the conductive pillars.

Thermal transfer structures for semiconductor die assemblies

Several embodiments of the present technology are described with reference to a semiconductor die assembly and processes for manufacturing the assembly. In some embodiments of the present technology, a semiconductor die assembly includes a stack of semiconductor dies attached to a thermal transfer structure (also known as a “heat spreader,” “lid,” or “thermal lid”). The thermal transfer structure conducts heat away from the stack of semiconductor dies. Additionally, the assembly can include molded walls fabricated with molding material to support the thermal transfer structure.

Wafer-level packaging for enhanced performance

The present disclosure relates to a mold module that includes a device layer, a number of first bump structures, a first mold compound, a stop layer, and a second mold compound. The device layer includes a number of input/output (I/O) contacts at a top surface of the device layer. Each first bump structure is formed over the device layer and electronically coupled to a corresponding I/O contact. The first mold compound resides over the device layer, and a portion of each first bump structure is exposed through the first mold compound. The stop layer is formed underneath the device layer. The second mold compound resides underneath the stop layer, such that the stop layer separates the device layer from the second mold compound.

SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor package device includes a carrier, a first electronic component, and a conductive element on the carrier. The first electronic component is over the carrier. The conductive element is on the carrier and electrically connects the first electronic component to the carrier. The conductive element includes at least one conductive particle and a solder material covering the conductive particle, and the conductive particle includes a metal core, a barrier layer covering the metal core, and a metal layer covering the barrier layer. 1. A conductive particle , comprising:a metal core;a barrier layer surrounding the metal core;a first conductive layer surrounding the barrier layer; anda second conductive layer surrounding the first conductive layer,wherein a ratio of a sum of volumes of the metal core, the barrier layer and the first conductive layer to a volume of the second conductive layer is from about 0.1 to about 200.21. The conductive particle of claim 1 , wherein a ratio of a thickness (t) of the second conductive layer to a distance (r) between a center of the metal core and an outer surface of the first conductive layer is from about 0.04 to about 110.31. The conductive particle of claim 2 , wherein about 0.05 micrometers (μm) Подробнее

Tall and fine pitch interconnects

Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.

CONDUCTIVE CONNECTIONS, STRUCTURES WITH SUCH CONNECTIONS, AND METHODS OF MANUFACTURE

A solder connection may be surrounded by a solder locking layer () and may be recessed in a hole () in that layer. The recess may be obtained by evaporating a vaporizable portion () of the solder connection. Other features are also provided. 1. A manufacturing method comprising: one or more first components each of which comprises solder and a material sublimatable or vaporizable when the solder is melted; and', 'a first layer comprising a top surface and one or more holes in the top surface, each hole containing at least a segment of a corresponding first component;, 'obtaining a first structure comprisingheating each first component to sublimate or vaporize at least part of each sublimatable or vaporizable material and provide an electrically conductive connection at a location of each first component;wherein in the heating operation at least part of each first component recedes down from the top surface to provide or increase a recess in each hole at the top surface.2. The method of wherein each hole is a through-hole.3. The method of wherein each hole's sidewall is a dielectric sidewall.4. The method of wherein the first layer is dielectric.5. The method of wherein the first layer is formed by molding.6. The method of further comprising:obtaining a second structure with one or more protruding conductive posts; andinserting each conductive post into a corresponding recess provided or increased in the heating operation, and forming a solder bond in each recess between the corresponding conductive post and the corresponding electrically conductive connection.7. The method of wherein before the heating operation claim 1 , at least a segment of each first component either:comprises of a solder core coated with the sublimatable or vaporizable material; orconsists of the sublimatable or vaporizable material.8. The method of wherein in obtaining the first structure claim 7 , the one or more first components are formed before the first layer.9. The method of wherein in ...

Wiring substrate and semiconductor package

A wiring substrate includes an insulating layer and a wiring layer buried in the insulating layer at a first surface of the insulating layer. The wiring layer includes a first portion and a second portion. The first portion is narrower and thinner than the second portion. The first portion includes a first surface exposed at the first surface of the insulating layer. The second portion includes a first surface exposed at the first surface of the insulating layer and a second surface partly exposed in an opening formed in the insulating layer. The opening is open at a second surface of the insulating layer opposite to the first surface thereof.

INTERCONNECT STRUCTURE WITH REDUNDANT ELECTRICAL CONNECTORS AND ASSOCIATED SYSTEMS AND METHODS

Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first semiconductor die and a second conductive film coupled to the second semiconductor die. The interconnect structure further includes a plurality of redundant electrical connectors extending between the first and second conductive films and electrically coupled to one another via the first conductive film. 1. A semiconductor device , comprising:a semiconductor substrate;a dielectric material over the substrate;a conductive trace extending at least partially through the dielectric material; and a conductive member coupled to the conductive trace, and', 'a conductive bond material bonded to the conductive member,, 'a plurality of redundant electrical connectors extending from the conductive trace and through at least a portion of the dielectric material, wherein each of the redundant electrical connectors includes—'}wherein all of the redundant electrical connectors are coupled to the conductive trace.2. The semiconductor device of wherein the dielectric includes a plurality of openings exposing portions of the conductive trace claim 1 , wherein the redundant electrical connectors are formed in the openings.3. The semiconductor device of wherein the conductive member comprises copper and the bond material comprises a solder material.4. The semiconductor device of wherein the conductive member includes an end portion claim 1 , and wherein the conductive bond material and conductive member form a conductive joint at the end portion.5. The semiconductor device of claim 1 , further comprising a through-substrate via (TSV) extending at least partially through the substrate claim 1 , ...

Method for Manufacturing Metal Powder

A method for manufacturing metal powder comprising: providing a basic metal salt solution; contacting the basic metal salt solution with a reducing agent to precipitate metal powder therefrom; and recovering precipitated metal powder from the solvent.

Method for Producing an Optoelectronic Component, and Optoelectronic Component

A method for producing an optoelectronic component and an optoelectronic component are disclosed. In an embodiment a method includes providing a semiconductor chip having an active region for radiation emission, applying a seed layer on the semiconductor chip, wherein the seed layer includes a first metal and a second metal being different from the first metal, and wherein the second metal is less noble than the first metal, applying a structured photoresist layer directly to the seed layer and applying a solder layer at least to regions of the seed layer which are not covered by the photoresist layer, wherein a ratio of the first metal to the second metal in the seed layer is between 95:5 to 99:1.

Integrated circuit chip and display device including the same

An exemplary embodiment provides a driving circuit chip including: a substrate; a terminal electrode disposed on the substrate; and an electrode pad disposed on the terminal electrode, wherein the electrode pad includes: a bump structure protruded from the substrate to include a short side and a long side; and a bump electrode disposed on the bump structure and connected with the terminal electrode around a short edge portion of the bump structure, wherein the bump electrode is disposed to not cover at least a part of a long edge portion of the bump structure.

Backplane, Preparation Method Thereof, Backlight Module and Display Device

A preparation method of a backplane includes: forming an insulating structure layer having a groove on a base substrate by a mask exposure process, the groove being used for accommodating a metal trace; and repeating a metal sub-layer forming step including an ashing process and a wet etching process multiple times to form the metal trace positioned in the groove.

SEMICONDUCTOR DEVICE WITH A SEMICONDUCTOR DIE EMBEDDED BETWEEN AN EXTENDED SUBSTRATE AND A BOTTOM SUBSTRATE

A method of manufacturing a semiconductor device having a semiconductor die within an extended substrate and a bottom substrate may include bonding a bottom surface of a semiconductor die to a top surface of a bottom substrate, forming an adhering member to a top surface of the semiconductor die, bonding an extended substrate to the semiconductor die and to the top surface of the bottom substrate utilizing the adhering member and a conductive bump on a bottom surface of the extended substrate and a conductive bump on the bottom substrate. The semiconductor die and the conductive bumps may be encapsulated utilizing a mold member. The conductive bump on the bottom surface of the extended substrate may be electrically connected to a terminal on the top surface of the extended substrate. The adhering member may include a laminate film, a non-conductive film adhesive, or a thermal hardening liquid adhesive. 120-. (canceled)21. An electronic device comprising:a conductive signal distribution layer (SDL) having an upper SDL side and a lower SDL side;a semiconductor die having an upper die side, and a lower die side facing the upper SDL side;a metal contact structure having an upper contact end coupled to the lower die side, and a lower contact end coupled to the upper SDL side;an encapsulating material having an upper encapsulating material side, and a lower encapsulating material side that faces the upper SDL side, wherein the encapsulating material laterally surrounds the semiconductor die and the metal contact structure; anda dielectric layer between lower die side and the upper SDL side and between the lower encapsulating material side and the upper SDL side.22. The electronic device of claim 21 , wherein the lower contact end is coplanar with the lower encapsulating material side.23. The electronic device of claim 21 , wherein the dielectric layer comprises an adhesive layer.24. The electronic device of claim 21 , wherein the dielectric layer comprises a material ...

Semiconductor integrated circuit device

A semiconductor integrated circuit chip, in which multi-core processors are integrated, is usually mounted over an organic wiring board by FC bonding to form a BGA package by being integrated with the substrate. In such a structure, power consumption is increased, and hence the power supplied only from a peripheral portion of the chip is insufficient, so that a power supply pad is also provided in the chip central portion. However, because of an increase in the wiring associated with the integration of a plurality of CPU cores, etc., there occurs a portion between the peripheral portion and the central portion of the chip, where a power supply pad cannot be arranged. According to the outline of the present application, in a semiconductor integrated circuit device such as a BGA, etc., in which a semiconductor chip is mounted over an interposer, such as a multilayer organic wiring board, in a face-up manner, a first group of metal through electrodes, which are provided in the semiconductor chip to supply a power supply potential to a core circuit, etc., and a first metal land over the interposer are interconnected by a first conductive adhesive member film.

Warpage Control for Flexible Substrates

A flexible substrate may be provided having a first side and a second side. A device may be electrically coupled to the first side of the flexible substrate through one or more electrical connections. A warpage control device may be attached to the second side flexible substrate. The warpage control device may include an adhesive layer and a rigid layer. The warpage control device may be formed in an area of the second side of the flexible substrate that may be opposite the one or more electrical connections on the first side of the flexible substrate.

Hybrid bonding structures, semiconductor devices having the same, and methods of manufacturing the semiconductor devices

Provided are a hybrid bonding structure, a solder paste composition, a semiconductor device, and a method of manufacturing the semiconductor device. The hybrid bonding structure includes a solder ball and a solder paste bonded to the solder ball. The solder paste includes a transient liquid phase. The transient liquid phase includes a core and a shell on a surface of the core. A melting point of the shell may be lower than a melting point of the core. The core and the shell are configured to form an intermetallic compound in response to the transient liquid phase at least partially being at a temperature that is within a temperature range of about 20° C. to about 190° C.

Package on package structure and method of manufacturing the same

A package on package structure includes a first substrate having a first region and a second region, a bump formed on the first region of the first substrate, a first semiconductor die bonded to the second region of the first substrate, and a semiconductor die package bonded to the first substrate. The bump includes a metallic structure and a plurality of minor elements dispersed in the metallic structure. The semiconductor die package includes a connector bonded to the bump, and the first semiconductor die is between the semiconductor die package and the first substrate.

Dual side cooling power module and manufacturing method of the same

A dual side cooling power module includes: a lower substrate including a recessed portion on at least one surface thereof, a semiconductor chip formed in the recessed portion, lead frames formed at both ends of the lower substrate, and an upper substrate formed on the semiconductor chip, a portion of the lead frames, and the lower substrate.

LOW TEMPERATURE SOLDER IN A PHOTONIC DEVICE

Photonic devices include a photonic assembly and a substrate coupled to the photonic assembly. The photonic assembly includes a photonic die and an optical device coupled to the photonic die with an adhesive to form an optical connection between the optical device and the photonic die. The photonic assembly is coupled to the photonic assembly by reflowing a plurality of solder connections at temperature that is less than a cure temperature of the adhesive. 1. A method for forming a photonic device , the method comprising:forming a photonic assembly by attaching an optical device to a photonic die with an optically clear adhesive to form an optical connection between the optical device and the photonic die; andattaching the photonic assembly to a substrate by reflowing one or more solder connections formed between the photonic assembly and the substrate, wherein a reflow temperature of the one or more solder connections is less than a cure temperature of the adhesive.2. The method of claim 1 , wherein attaching the optical device to the photonic die comprises aligning an optical fiber array to the photonic die.3. The method of further comprising attaching a laser to the photonic die.4. The method of further comprising at least one of electrically testing and optically testing the photonic assembly before attaching the photonic assembly to the substrate.5. The method of further comprising heating the photonic assembly and the substrate at a temperature less than the reflow temperature to convert solder of the one or more solder connections to an intermetallic compound; wherein reflowing the one or more solder connections includes reflowing the one or more solder connections at the reflow temperature.6. The method of claim 1 , wherein the cure temperature of the adhesive is less than about 160 degrees Celsius.7. The method of further comprising disposing solder bumps on the photonic die to form the one or more solder connections claim 1 , wherein the solder bumps ...

METHOD OF FABRICATING SEMICONDUCTOR PACKAGE

Provided is a method of fabricating a semiconductor package. The method of fabricating the semiconductor package include preparing a lower element including a lower substrate, a lower electrode, an UBM layer, and a reducing agent layer, providing an upper element including an upper substrate, an upper electrode, and a solder bump layer, providing a pressing member on the upper substrate to press the upper substrate to the lower substrate, and providing a laser beam passing through the pressing member to bond the upper element to the lower element. 1. A method of fabricating a semiconductor package , the method comprising:preparing a lower element including a lower substrate, a lower electrode on the lower substrate, an under bump metallurgy (UBM) layer on the lower electrode, and a reducing agent layer on the UBM layer;providing an upper element including an upper substrate, an upper electrode on the upper substrate, and a solder bump layer on the upper electrode;providing a pressing member on the upper substrate to press the upper substrate to the lower substrate; andproviding a laser beam passing through the pressing member to the upper substrate to form the UBM layer, the reducing agent layer, and the solder bump layer as an intermetallic compound layer by using a conductive heat of the upper substrate and the upper electrode.2. The method of claim 1 , wherein the lower element further comprises:a curing agent layer between the UBM layer and the reducing agent layer; anda base material layer between the curing agent layer and the reducing agent layer.3. The method of claim 2 , wherein the curing agent layer and the base material layer are formed as a protective layer around the intermetallic compound layer.4. The method of claim 3 , further comprising dipping the lower element and the upper element in DI (deionized) water through which the laser beam is transmitted claim 3 ,wherein the DI water allows the protective layer to be formed around the lower electrode ...

ADHESIVE COMPOSITION, ELECTRONIC-COMPONENT-MOUNTED SUBSTRATE AND

There are provided are an adhesive composition that keeps storage stability and further gives a cured product wherein metallic bonds are formed in the state that the cured product wets its components and is satisfactorily spread between the components (or parts), thereby turning excellent in adhesive property, electroconductivity, and reliability for mounting such as TCT resistance or high-temperature standing resistance; an electronic-component-mounted substrate using the same; and a semiconductor device. The adhesive composition comprises electroconductive particles (A) and a binder component (B), wherein the electroconductive particles (A) include a metal (a1) having a melting point equal to or higher than the reflow temperature and containing no lead, and a metal (a2) having a melting point lower than the reflow temperature and containing no lead, and the binder component (B) includes a thermosetting resin composition (b1) and an aliphatic dihydroxycarboxylic acid (b2). 2. The electronic component structure according to claim 1 , wherein R1 in the general formula (1) is an alkyl group having 1 to 5 carbon atom.3. The electronic component structure according to claim 1 , wherein the aliphatic dihydroxycarboxylic acid (b2) includes 2 claim 1 ,2-bishydroxymethylpropionic acid claim 1 , 2 claim 1 ,2-bishydroxymethylbutanoic acid claim 1 , and 2 claim 1 ,2-bishydroxymethylpentanoic acid.4. The electronic component structure according to claim 1 , wherein the reflow temperature is the temperature for mounting with SnAgCu cream solder.5. The electronic component structure according to claim 1 , wherein the reflow temperature is 260° C.6. The electronic component structure according to claim 1 , wherein the content of the aliphatic dihydroxycarboxylic acid (b2) is 0.1 part or more by weight and 20 parts or less by weight for 100 parts by weight of the metal (a2) having the melting point lower than the reflow temperature and containing no lead.7. The electronic component ...

Semiconductor device and method for manufacturing the same

A semiconductor device includes a dielectric interposer, a first interconnection layer, an electronic component, a plurality of electrical conductors and a plurality of conductive structures. The dielectric interposer has a first surface and a second surface opposite to the first surface. The first interconnection layer is over the first surface of the dielectric interposer. The electronic component is over and electrically connected to the first interconnection layer. The electrical conductors are over the second surface of the dielectric interposer. The conductive structures are through the dielectric interposer, wherein the conductive structures are electrically connected to the first interconnection layer and the electrical conductors.

Process for Manufacturing a Chip-Card Module with Soldered Electronic Component

Process for manufacturing a chip-card module. It includes one or more operations in which a meltable solder is deposited on connection pads formed in a layer of electrically conductive material located on the back side of a dielectric substrate, and at least one electronic component is connected to these connection pads by reflowing the solder. Chip-card module obtained using this process. Chip card including such a module.

Junction and electrical connection

A junction at which at least two conductors are connected together includes a compound region containing Cu, Sn and at least one element selected from the group consisting of Si, B, Ti, Al, Ag, Bi, In, Sb, Ga and Zn. The compound region forms a nanocomposite metal diffusion region with the conductor.

Tall and Fine Pitch Interconnects

Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers. 1. A method , comprising:applying a conductive layer to a temporary carrier;patterning the conductive layer to form a patterned conductive structure;applying a nonwettable layer to the patterned conductive structure;patterning the nonwettable layer to form nonwettable barriers on the patterned conductive structure;depositing a reflowable conductive material on the patterned conductive structure, between the nonwettable barriers, to form interconnect structures;mounting a first microelectronic element to the interconnect structures;removing the temporary carrier;mounting a second microelectronic element with interconnect structures onto the patterned conductive structure, on a side previously occupied by the temporary carrier; andcoupling the IC die to the patterned conductive structure via heated reflow.2. The method of claim 1 , further comprising patterning the nonwettable layer by removing the nonwettable layer from the patterned conductive structure claim 1 , except at one or more edges of the patterned conductive structure.3. The method of claim 1 , further comprising forming nonwettable barriers having closed geometric shapes with open interiors on the patterned conductive structure.4. The method of claim 1 , further comprising forming nonwettable barriers having partly-closed predefined shapes with open interiors on the patterned conductive structure.5. The method of claim 1 , wherein the nonwettable layer comprises a polymer or poly imide material.6. ...

Semiconductor packages

A semiconductor package includes a first substrate, a first flow channel and a second flow channel. The first flow channel is on the first substrate. The second flow channel is on the first substrate and in fluid communication with the first flow channel. The second flow channel is spaced from an inlet and an outlet of the first flow channel. The first flow channel and the second flow channel constitute a bonding region of the first substrate.

FLEXIBLE LIGHTING DEVICE INCLUDING A NANO-PARTICLE HEAT SPREADING LAYER

A lighting device is provided, including: a substrate having a first surface and a second surface opposite the first surface; one or more light-emitting structures formed on the first surface of the substrate; and a heat spreading and dissipating layer formed on the second surface of the substrate, wherein the heat spreading and dissipating layer comprises a polymer layer mixed with nano graphite particles. 110-. (canceled)11. A method of forming a lighting device , comprising:providing a substrate having a first surface and a second surface opposite the first surface;forming one or more light-emitting structures on the first surface of the substrate; andapplying a heat spreading and dissipating layer on the second surface of the substrate,wherein the heat spreading and dissipating layer comprises a polymer layer mixed with nano graphite particles.12. The method of claim 11 ,wherein the heat spreading and heat dissipating film is between 0.01 mm and 0.5 mm thick.13. The lighting device of claim 11 ,wherein the nano graphite particles are between 0.01 μm and 20 μm in diameter.14. The lighting device of claim 11 ,wherein the polymer layer comprises at least one of polyethylene, polyurethane, or poly(methyl methacrylate) (PMMA).15. The lighting device of claim 11 ,wherein the operation of applying the heat spreading and dissipating layer on the second surface of the substrate involves spraying or painting the heat spreading and dissipating layer on the second surface of the substrate.16. A method of forming a lighting device claim 11 , comprising:providing a substrate having a first surface and a second surface opposite the first surface;forming one or more light-emitting structures on the first surface of the substrate;forming a heat dissipating structure on the second surface of the substrate; andapplying a heat spreading and heat dissipating film on the heat dissipating structure,wherein the heat spreading and dissipating film comprises a polymer layer mixed with ...

Advanced Solder Alloys For Electronic Interconnects

Improved electrical and thermal properties of solder alloys are achieved by the use of micro-additives in solder alloys to engineer the electrical and thermal properties of the solder alloys and the properties of the reaction layers between the solder and the metal surfaces. The electrical and thermal conductivity of alloys and that of the reaction layers between the solder and the -metal surfaces can be controlled over a wide range of temperatures. The solder alloys produce stable microstructures wherein such stable microstructures of these alloys do not exhibit significant changes when exposed to changes in temperature, compared to traditional interconnect materials. 1. A lead-free , antimony-free solder alloy comprising:(a) 10 wt. % or less of silver(b) 10 wt. % or less of bismuth(c) 3 wt. % or less of copper up to 1 wt. % of nickel', 'up to 1 wt. % of titanium', 'up to 1 wt. % of cobalt', 'up to 3.5 wt. % of indium', 'up to 1 wt. % of zinc', 'up to 1 wt. % of cerium, '(d) at least one of the following elements'} 0 to 1 wt. % of manganese', '0 to 1 wt. % of chromium', '0 to 1 wt. % of germanium', '0 to 1 wt. % of iron', '0 to 1 wt. % of aluminum', '0 to 1 wt. % of phosphorus', '0 to 1 wt. % of gold', '0 to 1 wt. % of gallium', '0 to 1 wt. % of tellurium', '0 to 1 wt. % of selenium', '0 to 1 wt. % of calcium', '0 to 1 wt. % of vanadium', '0 to 1 wt. % of molybdenum', '0 to 1 wt. % of platinum', '0 to 1 wt. % of magnesium', '0 to 1 wt. % of rare earths, '(e) optionally one or more of the following elements'}(f) the balance tin, together with any unavoidable impurities.2. A lead-free , solder alloy comprising:(a) 10 wt. % or less of silver(b) 10 wt. % or less of bismuth(c) 3 wt. % or less of copper(d) 4 wt % or less of antimony up to 1 wt % of Ni', 'up to 1 wt. % of titanium', 'up to 1 wt. % of cobalt', 'up to 3.5 wt. % of indium', 'up to 1 wt. % of zinc', 'up to 1 wt. % of cerium, '(e) at least one of the following elements'} 0 to 1 wt. % of manganese', '0 to 1 wt. ...

METHOD FOR FABRICATING AN ELECTRONIC DEVICE AND A STACKED ELECTRONIC DEVICE

A method for fabricating an electronic device includes fixing a rear face of an integrated-circuit chip to a front face of a support wafer. An infused adhesive is applied in the form of drops or segments that are separated from each other. A protective wafer is applied to the infused adhesive, and the infused adhesive is cured. The infused adhesive includes a curable adhesive and solid spacer elements infused in the curable adhesive. A closed intermediate peripheral ring is deposited on the integrated-circuit chip outside the cured infused adhesive, and an encapsulation block is formed such that it surrounds the chip, the protective wafer and the closed intermediate peripheral ring. 1. A method , comprising:fixing a rear face of an integrated-circuit chip to a front face of a support wafer;depositing on a front face of the integrated-circuit chip an infused adhesive in a form of drops or segments at a distance from one another outside a central region of the front face of the integrated-circuit chip, the infused adhesive comprising a curable adhesive and solid spacer elements infused in the curable adhesive;placing a protective wafer on the infused adhesive so that a free space remains between the front face of the integrated-circuit chip and a rear face of the protective wafer;curing the curable adhesive to fix the protective wafer to the integrated-circuit chip;producing an intermediate peripheral ring between the integrated-circuit chip and the protective wafer after curing the curable adhesive; andproducing an encapsulation ring around the integrated-circuit chip, the protective wafer, and the intermediate peripheral ring on a peripheral zone of the front face of the support wafer.2. The method of claim 1 , wherein producing the intermediate peripheral ring comprises curing a resin using ultraviolet radiation without releasing gas.3. The method of claim 1 , wherein producing the encapsulating ring comprises supplying a coating material and curing the coating ...

Carbon nanotube structure, heat dissipation sheet, and method of manufacturing carbon nanotube structure

A carbon nanotube structure includes a plurality of carbon nanotubes, and a graphite film that binds one ends of the plurality of carbon nanotubes. And a heat dissipation sheet includes a plurality of carbon nanotube structures arranged in a sheet form, wherein each of the carbon nanotube structures includes a plurality of carbon nanotubes, and a graphite film that binds one ends of the plurality of carbon nanotubes.

FULLY MOLDED MINIATURIZED SEMICONDUCTOR MODULE

A semiconductor module can comprise a fully molded base portion comprising a planar surface that further comprises a semiconductor die comprising contact pads, conductive pillars coupled to the contact pads and extending to the planar surface, and an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion. A build-up interconnect structure comprising a routing layer can be disposed over the fully molded base portion. A photo-imageable solder mask material can be disposed over the routing layer and comprise openings to form surface mount device (SMD) land pads electrically coupled to the semiconductor die and the conductive pillars. A SMD component can be electrically coupled to the SMD land pads with surface mount technology (SMT). 1. A semiconductor module , comprising: a semiconductor die comprising contact pads,', 'conductive pillars coupled to the contact pads and extending to the planar surface, and', 'an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion;, 'a fully molded base portion comprising a planar surface that further comprisesa build-up interconnect structure comprising a routing layer disposed over the fully molded base portion;a photo-imageable solder mask material disposed over the routing layer and comprising openings to form surface mount device (SMD) land pads electrically coupled to the semiconductor die and the conductive pillars; anda SMD component electrically coupled to the SMD land pads with surface mount technology (SMT).2. The semiconductor module of claim 1 , wherein the photo-imageable solder mask comprises at least one of epoxy solder resist claim 1 , ...

IC CHIP PACKAGE WITH DUMMY SOLDER STRUCTURE UNDER CORNER, AND RELATED METHOD

An IC chip package includes a substrate having a plurality of interconnect metal pads, and a chip having a plurality of interconnect metal pads arranged thereon. An interconnect solder structure electrically connects each of the plurality of interconnect metal pads. The chip is devoid of the interconnect solder structures and interconnect metal pads at one or more corners of the chip. Rather, a dummy solder structure connects the IC chip to the substrate at each of the one or more corners of the IC chip, and the dummy solder structure is directly under at least one side of the IC chip at the one or more corners of the IC chip. The dummy solder structure has a larger volume than a volume of each of the plurality of interconnect solder structures. The dummy solder structure eliminates a chip-underfill interface at corner(s) of the chip where delamination would occur. 1. An integrated circuit (IC) chip package , comprising:a substrate having a first plurality of interconnect metal pads thereon;an integrated circuit (IC) chip having a second plurality of interconnect metal pads arranged thereon;an interconnect solder structure electrically connecting each of the first and second plurality of interconnect metal pads, the IC chip being devoid of the interconnect solder structures at one or more corners of the IC chip; anda dummy solder structure connecting the IC chip to the substrate at each of the one or more corners of the IC chip, andwherein the dummy solder structure is directly under at least one side of the IC chip at the one or more corners of the IC chip, andwherein the dummy solder structure has a larger volume than a volume of each of the interconnect solder structures.2. The IC chip package of claim 1 , wherein at least one dummy solder structure extends laterally outward beyond the at least one side of the IC chip.3. The IC chip package of claim 1 , wherein the dummy solder structure includes a first solder material that is softer than a different claim 1 , ...

Methods of processing semiconductor devices

Methods of processing a semiconductor device include providing a patterned mask over a major surface of a substrate and comprising at least one opening exposing a conductive structure, and depositing particles of material by direct material deposition adjacent and in contact with an edge wall of the mask adjacent the at least one opening to form a supplemental mask over the major surface of the substrate. Other methods of processing semiconductor devices include depositing particles of material by direct material deposition adjacent a conductive structure at an intersection of the conductive structure and a surface of a substrate.

Anchoring structure of fine pitch bva

A microelectronic package can include a substrate having a first surface and a second surface opposite therefrom, the substrate having a first conductive element at the first surface, and a plurality of wire bonds, each of the wire bonds having a base electrically connected to a corresponding one of the first conductive elements and having a tip remote from the base, each wire bond having edge surfaces extending from the tip toward the base. The microelectronic package can also include an encapsulation having a major surface facing away from the first surface of the substrate, the encapsulation having a recess extending from the major surface in a direction toward the first surface of the substrate, the tip of a first one of the wire bonds being disposed within the recess, and an electrically conductive layer overlying an inner surface of the encapsulation exposed within the recess, the electrically conductive layer overlying and electrically connected with the tip of the first one of the wire bonds.

Pad design for thermal fatigue resistance and interconnect joint reliability

Embodiments described herein provide techniques for forming an interconnect structure that includes micro features formed therein. Such embodiments can assist with improving interconnect joint reliability when compared to conventional pads that have a flat surface. An interconnect structure may comprise: a metal pad over a substrate (e.g., a semiconductor package, a PCB, an interposer, etc.). Micro features may be formed in an edge of the metal pad or away from the edge of the metal pad. The micro features can assist with: (i) increasing the contact area between solder used to form an interconnect joint and the metal pad; and (ii) improving adherence of solder used to form an interconnect joint to the metal pad. These benefits can improve interconnect joint reliability by, among others, improving the interconnect joint's ability to absorb stress from substrates having differing coefficients of thermal expansion.

Semiconductor device

A semiconductor device includes a first electronic component, a second electronic component, a third electronic component, a plurality of first interconnection structures, and a plurality of second interconnection structures. The second electronic component is between the first electronic component and the third electronic component. The first interconnection structures are between and electrically connected to the first electronic component and the second electronic component. Each of the first interconnection structures has a length along a first direction substantially parallel to a surface of the first electronic component and a width along a second direction substantially parallel to the surface and substantially perpendicular to the first direction. The length is larger than the width. The second interconnection structures are between and electrically connected to the second electronic component and the third electronic component.

Electronics package having a multi-thickness conductor layer and method of manufacturing thereof

An electronics package includes an insulating substrate, a first electrical component coupled to a first surface of the insulating substrate, and a first conductor layer formed on the first surface of the insulating substrate. A second conductor layer is formed on a second surface of the insulating substrate, opposite the first surface, the second conductor layer extending through vias in the insulating substrate to contact at least one contact pad of the first electrical component and couple with the first conductor layer. The electronics package also includes a second electrical component having at least one contact pad coupled to the first conductor layer. The first conductor layer has a thickness greater than a thickness of the second conductor layer.

WAFER LEVEL INTEGRATION INCLUDING DESIGN/CO-DESIGN, STRUCTURE PROCESS, EQUIPMENT STRESS MANAGEMENT AND THERMAL MANAGEMENT

A method of manufacturing a multi-layer wafer is provided. The method comprises creating under bump metallization (UMB) pads on each of the two heterogeneous wafers; applying a conductive means above the UMB pads on at least one of the two heterogeneous wafers; and low temperature bonding the two heterogeneous wafers to adhere the UMB pads together via the conductive means. At least one stress compensating polymer layer may be applied to at least one of two heterogeneous wafers. The multi-layer wafer comprises two heterogeneous wafers, each of the heterogeneous wafer having UMB pads and at least one of the heterogeneous wafers having a stress compensating polymer layer and a conductive means applied above the UMB pads on at least one of the two heterogeneous wafers. The two heterogeneous wafers low temperature bonded together to adhere the UMB pads together via the conductive means. 1. A method of manufacturing a multi-layer wafer comprising:creating under bump metallization pads on each of the two heterogeneous wafers;applying a conductive means above the under bump metallization pads on at least one of the two heterogeneous wafers; andlow temperature bonding the two heterogeneous wafers to adhere the under bump metallization pads together via the conductive means to form a multi-layer wafer pair.2. The method of claim 1 , further comprising:applying at least one stress compensating polymer and/or adhesive layer to at least one of two heterogeneous wafers3. The method of claim 1 , wherein each of the two heterogeneous wafers are formed from at least one of: complementary metal-oxide semiconductor (CMOS) and GaN on Si claim 1 , CMOS and glass claim 1 , CMOS and sapphire claim 1 , CMOS and SiC on Si claim 1 , CMOS and diamond on Si claim 1 , or CMOS and sapphire on Si.4. The method of claim 1 , wherein the stress compensating polymer layer is formed on the at least one heterogeneous wafer by:applying a liquid polymer to the at least one of the two heterogeneous ...

Microelectronic package with stacked microelectronic units and method for manufacture thereof

A microelectronic package may include a first microelectronic unit including a semiconductor chip having first chip contacts, an encapsulant contacting an edge of the semiconductor chip, and first unit contacts exposed at a surface of the encapsulant and electrically connected with the first chip contacts. The package may include a second microelectronic unit including a semiconductor chip having second chip contacts at a surface thereof, and an encapsulant contacting an edge of the chip of the second unit and having a surface extending away from the edge. The surfaces of the chip and the encapsulant of the second unit define a face of the second unit. Package terminals at the face may be electrically connected with the first unit contacts through bond wires electrically connected with the first unit contacts, and the second chip contacts through metallized vias and traces formed in contact with the second chip contacts.

Method for fabricating an electronic device and a stacked electronic device

A method for fabricating an electronic device, and an electronic device in a stacked configuration, includes a rear face of an integrated-circuit chip that is fixed to a front face of a support wafer. A protective wafer is located facing and at a distance from the front face of the chip, and an infused adhesive is interposed between the chip and the protective wafer and located on a zone of the front face of the chip outside a central region of this front face. The infused adhesive includes a curable adhesive and solid spacer elements infused in the curable adhesive. An obstruction barrier is arranged between the chip and the protective wafer and is disposed outside the central region of the front face of the chip. An encapsulation ring surrounds the chip, the protective wafer and the obstruction barrier.

System and Method for an Improved Fine Pitch Joint

Presented herein are an interconnect and method for forming the same, the method comprising forming an interconnect on a mounting surface of a mounting pad disposed on a first surface of a first substrate, the interconnect comprising a conductive material, optionally solder or metal, the interconnect avoiding the sides of the mounting pad. A molding compound is applied to the first surface of the first substrate and molded around the interconnect to covering at least a lower portion of the interconnect and a second substrate may be mounted on the interconnect. The interconnect may comprise an interconnect material disposed between a first and second substrate and a molding compound disposed on a surface of the first substrate, and exposing a portion of the interconnect. A sidewall of the interconnect material contacts the mounting pad at an angle less than about 30 degrees from a plane perpendicular to the first substrate.

SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME

According to aspects provided herein, a semiconductor device may include a bump providing improved reliability and reduced size. In some aspects, a conductive pad may be formed on a substrate, and a conductive support layer, which may be a pillar, may be formed on the conductive pad. An intermetallic compound (IMC) layer may be formed on the conductive support layer, and a solder layer may be formed on the IMC layer. In some aspects, the conductive support layer may be of a smaller width than the IMC layer. In some aspects, the conductive support layer may have side surfaces which are wider at the solder side than at the conductive pad side. In some aspects, other layers may be formed, such as a seed layer between the conductive pad and the conductive support layer, or a barrier layer between the conductive support layer and the IMC layer. 1. A semiconductor device , comprising:a conductive pad on a substrate;a conductive support layer on the conductive pad and comprising a first width;an intermetallic compound (IMC) layer on the conductive support layer and comprising a second width greater than the first width; anda solder layer on the IMC layer.2. The semiconductor device of claim 1 , further comprising a barrier layer between the conductive support layer and the IMC layer.3. The semiconductor device of claim 2 , wherein the barrier layer comprises a third width substantially equal to the second width.4. The semiconductor device of claim 3 , wherein the the first width is smaller than the third width.5. The semiconductor device of claim 2 , wherein side surfaces of the IMC layer are vertically aligned with side surfaces of the barrier layer.6. The semiconductor device of claim 2 , wherein the conductive support layer comprises an upper portion and a lower portion claim 2 , and wherein a distance between sidewalls of the conductive support layer at the upper portion is greater than a distance between sidewalls of the conductive support layer at the lower portion.7 ...

Semiconductor device and manufacturing method thereof

A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a stackable semiconductor device with small size and fine pitch and a method of manufacturing thereof.

Semiconductor device

A semiconductor device includes an electric conductor, a semiconductor element, and a bonding layer. The electric conductor has a main surface and a rear surface opposite to the main surface in a thickness direction. The semiconductor element includes a main body and electrodes. The main body has a side facing the main surface of the conductor, and the electrodes each protrude toward the main surface from the side of the main body to be electrically connected to the main surface. The bonding layer is held in contact with the main surface and the electrodes. Each electrode includes a base portion in contact with the main body, and a columnar portion protruding toward the main surface from the base portion to be held in contact with the bonding layer, which is a sintered body of a metal powder.

Flexible packages including chips

A flexible package may be provided. The flexible package may include a flexible molding member including a top surface. The flexible package may include a first chip within the flexible molding member, and including a first top surface. The flexible package may include a second chip within the flexible molding member, and including a second top surface. The first top surface may face away from the top surface of the flexible molding member and the second top surface may face towards the top surface of the flexible molding member.

Packaged semiconductor device with a particle roughened surface

A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame. A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame and with a reflow wall that surrounds a portion of the solder joint that couples the semiconductor device to the lead frame. A packaged semiconductor device with a reflow wall that surrounds a portion of a solder joint that couples a semiconductor device to a lead frame.

Advanced Solder Alloys For Electronic Interconnects

Improved electrical and thermal properties of solder alloys are achieved by the use of micro-additives in solder alloys to engineer the electrical and thermal properties of the solder alloys and the properties of the reaction layers between the solder and the metal surfaces. The electrical and thermal conductivity of alloys and that of the reaction layers between the solder and the -metal surfaces can be controlled over a wide range of temperatures. The solder alloys produce stable microstructures wherein such stable microstructures of these alloys do not exhibit significant changes when exposed to changes in temperature, compared to traditional interconnect materials.

Structures to enable a full intermetallic interconnect

A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder bump including a nickel copper colloid surrounded by a nickel or copper shell and suspended in a tin-based solder; aligning the chip with the laminate; performing a first reflow process to join the chip to the laminate; depositing an underfill material around the first solder bump and the second solder bump; and performing a second reflow process at a temperature that is lower than the first reflow process to convert the first solder bump and the second solder bump to an all intermetallic interconnect; wherein depositing the underfill material is performed before or after performing the second reflow process.

Contact structures with porous networks for solder connections, and methods of fabricating same

A contact pad includes a solder-wettable porous network ( 310 ) which wicks the molten solder ( 130 ) and thus restricts the lateral spread of the solder, thus preventing solder bridging between adjacent contact pads.

INDIUM SOLDER METALLURGY TO CONTROL ELECTRO-MIGRATION

Embodiments are generally directed to indium solder metallurgy to control electro-migration. An embodiment of an electronic device includes a die; and a package substrate, wherein the die is bonded to the package substrate by an interconnection. The interconnection includes multiple interconnects, and wherein the interconnection includes a solder. The solder for the interconnection includes a combination of tin (Sn), copper (Cu), and indium (In). 1. An electronic device comprising:a die; anda package substrate, the die being bonded to the package substrate by an interconnection including a plurality of interconnects;wherein the interconnects include a solder, the solder including tin (Sn), copper (Cu), and indium (In).2. The electronic device of claim 1 , wherein the bonding of the interconnects includes a thermal compression bond (TCB).3. The electronic device of claim 2 , wherein the bonding of the interconnects further includes reflow of the solder.4. The electronic device of claim 1 , wherein the solder includes between 0.1% and 2.0% indium by weight.5. The electronic device of claim 4 , wherein the solder includes between 0.5% and 1.0% indium by weight.6. The electronic device of claim 1 , wherein the solder includes between 0.1% and 1.0% copper by weight.7. The electronic device of claim 1 , wherein the interconnection further includes a nickel (Ni) layer.8. The electronic device of claim 1 , wherein the die is a silicon die.9. A method for fabrication of an electronic device or system comprising:obtaining a die and a package substrate for the electronic device or system;forming interconnects for an interconnection between the die and the package substrate, where the interconnects include includes a solder, the solder including tin (Sn), copper (Cu), and indium (In); andbonding the die to the package substrate using the interconnects.10. The method of claim 9 , wherein bonding the die to the package substrate includes formation of a thermal compression bond ( ...

Semiconductor device

A semiconductor device according to the present invention includes: a substrate; a heat generating portion provided on the substrate; a cap substrate provided above the substrate so that a hollow portion is provided between the substrate and the cap substrate; and a reflection film provided above the heat generating portion and reflecting a medium wavelength infrared ray. The reflection film reflects the infrared ray radiated to the cap substrate side through the hollow portion due to the temperature increase of the heat generating portion, so that the temperature increase of the cap substrate side can be suppressed. Because of this function, even if mold resin is provided on the cap substrate, increase of the temperature of the mold resin can be suppressed.

ELECTRICALLY CONDUCTIVE PASTE FOR FORMING PILLARS

The known electrolytic plating method is disadvantageous in that it is difficult to form thin pillars without being influenced by undercuts. The electroless plating method is disadvantageous in that it is difficult to form pillars in the same shape without voids. As a solution to these, the electrically conductive paste according to the present invention for forming pillars is used to make pillars by filling. This helps prevent undercuts, and it is also intended to provide metal pillars in the same shape with good reproducibility. The inventors found that an electrically conductive paste that is very small fine metal particles and contains a particular percentage of fine metal particles is extraordinarily advantageous in forming pillars. 1. An electrically conductive paste for forming pillars , the paste comprising:fine metal particles: anda protective agent, whereina diameter of the fine metal particles is less than 1 μm, and a percentage of the fine metal particles in the electrically conductive paste is 40% or more and less than 95% concentration by mass.2. The electrically conductive paste according to for forming pillars claim 1 , the paste further comprising a solvent having a boiling point of 250° C. or less.3. The electrically conductive paste according to for forming pillars claim 1 , wherein the protective agent contains an organic compound including a C8 to C200 polyethylene oxide structure.4. The electrically conductive paste according to for forming pillars claim 3 , wherein a percentage of the organic compound including a C8 to C200 polyethylene oxide structure is 15% concentration by mass or less of the entire paste.5. The electrically conductive paste according to for forming pillars claim 1 , wherein the fine metal particle are particles of silver claim 1 , copper claim 1 , or a composite thereof.6. A pillar made using the electrically conductive paste according to for forming pillars. The present invention relates to an electrically conductive ...

Led package and manufacturing method

An LED package ( 40 ) and manufacturing method in which the package has LED substrate ( 50 ) and a circuit substrate ( 54 ) bonded together, with the LED over the integrated circuit, and with electrical connection between the LED and corresponding integrated circuit. The package has package terminals ( 56 a, 56 b ) on one face only with through vias ( 58 a, 58 b ) providing connection between the LED substrate and the circuit substrate.

LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME

Provided are a light emitting device and a method of fabricating the same. The light emitting device includes: a light emitting structure including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer and including a first surface and a second surface; first and second contact electrodes each ohmic-contacting the first and second conductivity type semiconductor layers; and first and second electrodes disposed on the first surface of the light emitting structure, in which the first and second electrodes each include sintered metal particles and the first and second electrodes each include inclined sides of which the tangential gradients with respect to sides of vertical cross sections thereof are changing. 1. A light emitting device comprising:a semiconductor stack located between a first surface and a second surface that are on opposite sides of the semiconductor stack and including a first semiconductor layer, a second semiconductor layer, and an active layer interposed between the first semiconductor layer and the second semiconductor layer;an electrical contact structure formed on the first surface of the semiconductor stack and having an inclined side surface with an inclination angle changing along a direction away from the first surface of the semiconductor stack; anda wavelength conversion structure formed on the second surface of the semiconductor stack and structured to change a wavelength of light emitted from the semiconductor stack.2. The light emitting device of claim 1 , wherein the inclination angle of the inclined side surface changes with respect to an axis perpendicular to a surface of the electrical contact structure.3. The light emitting device of claim 1 , wherein the inclined side surface includes a first region in which the inclination angle increases and a second region in which the inclination angle decreases.4. The light emitting device of claim 1 , wherein the electrical contact ...

Electrode connection structure and electrode connection method

An electrode connection structure includes: a first electrode of an electrical circuit; and a second electrode of the electrical circuit that is electrically connected to the first electrode. The first and second electrodes are oppositely disposed in direct or indirect contact with each other. A plated lamination is substantially uniformly formed by plating process from a surface of a contact region and opposed surfaces of the first and second electrodes. A void near the surface of the contact region is filled by formation of the plated lamination. Portions of the plated lamination formed from the opposed surfaces of the first and second electrodes in a region other than the contact region are not joined together.

PACKAGED DIE AND RDL WITH BONDING STRUCTURES THEREBETWEEN

Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a redistribution layer coupled to the one or more dies at a first side of the first package with a first set of bonding joints. The redistribution layer including more than one metal layer disposed in more than one passivation layer, the first set of bonding joints being directly coupled to at least one of the one or more metal layers, and a first set of connectors coupled to a second side of the redistribution layer, the second side being opposite the first side. 1. A semiconductor package comprising:a die comprising a contact pad;a redistribution structure comprising a redistribution line and a passivation layer, a first portion of the redistribution line extending through the passivation layer; anda first bonding joint coupled to the first portion of the redistribution line and the contact pad, the first bonding joint being in physical contact with a first surface of the passivation layer, an entirety of the first bonding joint being interposed between the first surface of the passivation layer and the contact pad.2. The semiconductor package of claim 1 , further comprising a molding compound encapsulating the die claim 1 , wherein the redistribution structure extends across an interface between the die and the molding compound.3. The semiconductor package of claim 2 , further comprising a through via extending through the molding compound claim 2 , wherein a surface of the through via is level with a surface of the molding compound.4. The semiconductor package of claim 3 , further comprising a second bonding joint coupled to a second portion of the redistribution line and the through via claim 3 , the second portion of the redistribution line extending through the passivation layer claim 3 , the second bonding joint being in physical contact with a second surface ...

Solder paste, joining method using the same and joined structure

A solder paste including a metal component consisting of a first metal powder and a second metal powder having a melting point higher than that of the first metal, and a flux component. The first metal is Sn or an alloy containing Sn, the second metal is one of (1) a Cu—Mn alloy in which a ratio of Mn to the second metal is 5 to 30% by weight and (2) a Cu—Ni alloy in which a ratio of Ni to the second metal is 5 to 20% by weight, and a ratio of the second metal to the metal component is 36.9% by volume or greater.

LIGHT-EMITTING DEVICE, MANUFACTURING METHOD THEREOF AND DISPLAY MODULE USING THE SAME

A light-emitting device includes a light-emitting element, a supporting structure, a first wavelength conversion structure, and a light-absorbing layer. The light-emitting element includes a plurality of active stacks separated from each other, a first-type semiconductor layer continuously arranged on the plurality of active stacks, and a plurality of second-type semiconductor layers under the plurality of active stacks. The supporting structure is disposed on the light-emitting element and includes a first opening. The first wavelength conversion structure disposed in the first opening. The light-absorbing layer disposed on the top surface of the supporting structure. 1. A light-emitting device , comprising: a plurality of active stacks separated from each other;', 'a first-type semiconductor layer continuously arranged on the plurality of active stacks;', 'a plurality of second-type semiconductor layers under the plurality of active stacks;, 'a light-emitting element comprisinga supporting structure disposed on the light-emitting element and comprising a first opening and a top surface;a first wavelength conversion structure disposed in the first opening; anda light-absorbing layer disposed on the top surface.2. The light-emitting device according to claim 1 , wherein the supporting structure comprises a side surface which is not covered by the light-absorbing layer.3. The light-emitting device according to claim 2 , wherein the first wavelength conversion structure is directly contacted with the side surface.4. The light-emitting device according to claim 1 , wherein the supporting structure comprises metal.5. The light-emitting device according to claim 1 , wherein light-absorbing layer comprises a mixture of resin and light-absorbing substance.6. The light-emitting device according to claim 1 , further comprising a light-transmitting layer arranged in the first opening and covering the first wavelength conversion structure.7. The light-emitting device according ...

Microelectronic assemblies

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

DUAL SIDED FAN-OUT PACKAGE HAVING LOW WARPAGE ACROSS ALL TEMPERATURES

Semiconductor devices including a dual-sided redistribution structure and having low-warpage across all temperatures and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die electrically coupled to a first side of a redistribution structure and a second semiconductor die electrically coupled to a second side of the redistribution structure opposite the first side. The semiconductor device also includes a first molded material on the first side, a second molded material on the second side, and conductive columns electrically coupled to the first side and extending through the first molded material. The first and second molded materials can have the same volume and/or coefficients of thermal expansion to inhibit warpage of the semiconductor device. 1. A method of manufacturing a semiconductor device , the method comprising:forming a redistribution structure having a first surface and a second surface opposite the first surface;mounting a first semiconductor die to the first surface of the redistribution structure and electrically coupling the first semiconductor die to the redistribution structure;mounting a second semiconductor die to the second surface of the redistribution structure and electrically coupling the second semiconductor die to the redistribution structure; anddisposing a molded material on the first surface and the second surface of the redistribution structure and at least partially around the first semiconductor die and the second semiconductor die.2. The method of wherein forming the redistribution structure includes forming the redistribution structure without a pre-formed substrate.3. The method of wherein a ratio of the volume of the first semiconductor die to the volume of the molded material on the first surface is substantially equal to a ratio of the volume of the second semiconductor die to the volume of the molded material on the second surface.4. The method of ...

Trace Design for Bump-on-Trace (BOT) Assembly

A bump-on-trace (BOT) interconnection in a package and methods of making the BOT interconnection are provided. An embodiment BOT interconnection comprises a landing trace including a distal end, a conductive pillar extending at least to the distal end of the landing trace; and a solder feature electrically coupling the landing trace and the conductive pillar. In an embodiment, the conductive pillar overhangs the end surface of the landing trace. In another embodiment, the landing trace includes one or more recesses for trapping the solder feature after reflow. Therefore, a wetting area available to the solder feature is increased while permitting the bump pitch of the package to remain small. 1. A structure comprising:a substrate; anda landing trace on the substrate, the landing trace having a first side and a second side opposite to the first side, the landing trace having a plurality of indents extending into the first side in a plan view, the second side being free of indents in the plan view.2. The structure of claim 1 , further comprising a solder feature over the landing trace claim 1 , the solder feature extending into the plurality of indents.3. The structure of claim 2 , wherein solder feature is in physical contact with the plurality of indents.4. The structure of claim 2 , further comprising a conductive pillar over the solder feature claim 2 , the conductive pillar overlapping with the plurality of indents in the plan view.5. The structure of claim 4 , wherein a width of the solder feature is greater than a width of the conductive pillar.6. The structure of claim 4 , wherein a width of the landing trace is less than a width of the conductive pillar.7. The structure of claim 1 , wherein the plurality of indents have a comb pattern in the plan view.8. A structure comprising:a substrate; anda landing trace on the substrate, the landing trace having a first sidewall and a second sidewall opposite to the first sidewall, the first sidewall having a plurality ...

Electronic component built-in substrate and method for manufacturing the same

An electronic component built-in substrate includes an insulating substrate having a through hole and an inner wall surrounding the through hole, an electronic component accommodated in the through hole of the substrate, a sealing member filling the through hole such that the sealing member is covering the electronic component in the through hole of the substrate and exposing a terminal of the electronic component on a first side of the substrate, and a shield layer structure including a first metal film and a second metal film formed such that the first metal film is formed on the inner wall of the substrate and surrounding the through hole of the substrate and that the second metal film is formed on a second side of the substrate on the opposite side with respect to the first side and covering an opening of the through hole on the second side of the substrate.

FABRICATION METHOD OF SEMICONDUCTOR PACKAGE WITH STACKED SEMICONDUCTOR CHIPS

A semiconductor package includes a build-up structure; a semiconductor disposed on the build-up structure in a flip-chip manner and having a plurality of bumps penetrating therethrough; an electronic element disposed on the semiconductor chip; and an encapsulant formed on the build-up structure and encapsulating the semiconductor chip and the electronic element, thereby improving the product yield and the overall heat dissipating efficiency. 126-. (canceled)27. A fabrication method of a semiconductor package , comprising the steps of:providing a carrier having opposite first and second surfaces, wherein a build-up structure is formed on the first surface of the carrier and has a plurality of conductive pads exposed from the a top surface thereof;disposing a first semiconductor chip on the build-up structure in a flip-chip manner, wherein the first semiconductor chip has a first active surface and a first non-active surface opposite to the first active surface, and the first active surface has a plurality of first electrode pads electrically connected to the conductive pads, respectively;thinning the first semiconductor chip from the first non-active surface thereof;forming a plurality of first through holes in the first semiconductor chip via the first non-active surface thereof;forming in the first through holes a plurality of first bumps electrically connected to the first electrode pads;disposing an electronic element on the first semiconductor chip for electrically connecting the electronic element to the first bumps; andforming on the build-up structure an encapsulant that encapsulates the first semiconductor chip and the electronic element.28. The fabrication method of claim 27 , wherein the first electrode pads are exposed through the first through holes claim 27 , respectively.29. The fabrication method of claim 27 , wherein a circuit layer that is electrically connected to the first electrode pads is exposed through the first through holes.30. The ...

CIRCUIT STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Provided is a circuit structure including a substrate, a pad, a dielectric layer, a conductive layer, an adhesion layer, and a conductive bump. The pad is disposed on the substrate. The dielectric layer is disposed on the substrate and exposes a portion of the pad. The conductive layer contacts the pad and extends from the pad to cover a top surface of the dielectric layer. The adhesion layer is disposed between the dielectric layer and the conductive layer. The conductive bump extends in an upward manner from a top surface of the conductive layer. The conductive bump and the conductive layer are integrally formed. A method of manufacturing the circuit structure is also provided. 1. A circuit structure , comprising:a pad, disposed on a substrate;a dielectric layer, disposed on the substrate and exposing a portion of the pad;a conductive layer, contacting the pad and extending from the pad to cover a top surface of the dielectric layer;an adhesion layer, disposed between the dielectric layer and the conductive layer; anda conductive bump, extending in an upward manner from a top surface of the conductive layer, wherein the conductive bump and the conductive layer are integrally formed.2. The circuit structure as recited in claim 1 , wherein the conductive layer and the conductive bump are constituted by a plurality of conductive particles in contact with each other.3. The circuit structure as recited in claim 2 , wherein the conductive layer and the conductive bump share at least one of the plurality of conductive particles.4. The circuit structure as recited in claim 2 , wherein the plurality of conductive particles comprise a plurality of metal nanoparticles claim 2 , and the plurality of metal nanoparticles comprise silver nanoparticles claim 2 , copper-silver nanoparticles claim 2 , copper nanoparticles claim 2 , or a combination thereof.5. The circuit structure as recited in claim 1 , wherein an interface is free between the conductive layer and the conductive ...

Method for Producing an Optoelectronic Component, and Optoelectronic Component

A method for producing an optoelectronic component and an optoelectronic component are disclosed. In an embodiment a method includes providing a semiconductor chip having an active region for radiation emission, applying a seed layer on the semiconductor chip, wherein the seed layer includes a first metal and a second metal being different from the first metal, and wherein the second metal is less noble than the first metal, applying a structured photoresist layer directly to the seed layer, applying a solder layer at least to regions of the seed layer which are not covered by the photoresist layer and wherein a proportion of the second metal in the seed layer is between 0.5 wt % and 10 wt %. 1. A method for producing an optoelectronic component , the method comprising:providing a semiconductor chip having an active region for radiation emission;applying a seed layer on the semiconductor chip, wherein the seed layer comprises a first metal and a second metal being different from the first metal, and wherein the second metal is less noble than the first metal;applying a structured photoresist layer directly to the seed layer;applying a solder layer at least to regions of the seed layer which are not covered by the photoresist layer, andwherein a proportion of the second metal in the seed layer is between 0.5 wt % and 10 wt %.2. The method according to claim 1 , further comprising tempering the seed layer.3. The method according to claim 1 , further comprising removing the photoresist layer with a lift-off method.4. The method according to claim 1 , further comprising removing the regions of the seed layer not covered by the photoresist layer by wet chemical etching.5. The method according to claim 1 , wherein a region between the photoresist layer and the seed layer is free of a nitride layer for adhesion promotion.6. The method according to claim 1 , wherein the seed layer is free of titanium.7. The method according to claim 1 , wherein the first metal is gold claim ...

Die interconnect

One example embodiment discloses a chip having a chip area, wherein the chip area includes: an overhang area; a rigid coupling area, having a set of rigid coupling points, located on one side of the overhang area; and a flexible coupling area, having a set of flexible coupling points, located on a side of the overhang area opposite to the a rigid coupling area. Another example embodiment discloses a method for fabricating a die interconnect, comprising: fabricating a rigid coupler area, having a set of rigid coupler points, within a chip having a chip area; defining an overhang area within the chip area and abutted to the rigid coupler area; and fabricating a flexible coupler area, having a set of flexible coupler points, within the chip area abutted to a side of the overhang area opposite to the rigid coupler area.

Micro device transferring method, and micro device substrate manufactured by micro device transferring method

A method for transferring a micro device, includes: a compression step in which a carrier film having a micro-device attached to an adhesive layer thereof is brought into contact with a substrate comprising a solder deposited on metal electrodes formed on the substrate and is compressed on the substrate; a first adhesive strength generation step in which the solder disposed between the micro-device and the metal electrodes is compressed in the compression step to generate first adhesive strength between the micro-device and the solder; a second adhesive generation step in which the micro-device is bonded to the adhesive layer through press-fitting in the compression step to generate second adhesive strength between the micro-device and the adhesive layer; and a release step in which the carrier film is separated from the substrate, with the micro-device adhered to the solder.

EXPANDED HEAD PILLAR FOR BUMP BONDS

A microelectronic device has a bump bond structure including an electrically conductive pillar with an expanded head, and solder on the expanded head. The electrically conductive pillar includes a column extending from an I/O pad to the expanded head. The expanded head extends laterally past the column on at least one side of the electrically conductive pillar. In one aspect, the expanded head may have a rounded side profile with a radius approximately equal to a thickness of the expanded head, and a flat top surface. In another aspect, the expanded head may extend past the column by different lateral distances in different lateral directions. In a further aspect, the expanded head may have two connection areas for making electrical connections to two separate nodes. Methods for forming the microelectronic device are disclosed. 1. A device comprising:an I/O pad of a substrate;a column on the I/O pad; anda head on the column and extending on all lateral sides of the column, a portion of a surface of the head, aligned with the column in a cross-sectional view of the device, is substantially parallel to a surface of the substrate.2. The device of claim 1 , wherein a plane along the portion of a surface of the head is parallel to a plane along a surface of the head adjacent to the column.3. The device of claim 1 , wherein the head has a rounded side profile with a radius that is approximately equal to the thickness of the head.4. The device of further comprising solder on the head.5. The device of further comprising a barrier layer between the surface of the head and the solder.6. The device of claim 5 , wherein the barrier layer impacts formation of intermetallic compounds between a material of the head and solder.7. The device of claim 1 , wherein the head extends past the column on all lateral sides of the column by a lateral distance that is approximately equal to a vertical thickness of the head.8. The device of further comprising a seed layer between the column ...

SEMICONDUCTOR DEVICE STRUCTURE WITH BONDING PAD AND METHOD FOR FORMING THE SAME

A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a first insulating layer formed over a conductive feature and a capacitor structure embedded in the first insulating layer. The semiconductor device also includes a bonding pad formed over the first insulating layer and corresponding to the capacitor structure. The bonding pad has a top surface and a multi-step edge to form at least three corners. In addition, the semiconductor device structure includes a second insulating layer conformally covering the at least three corners formed by the top surface and the multi-step edge of the bonding pad. 1. A semiconductor device structure , comprising:a first insulating layer formed over a conductive feature;a capacitor structure embedded in the first insulating layer;a bonding pad formed over the first insulating layer and corresponding to the capacitor structure, wherein the bonding pad has a top surface and a multi-step edge to form at least three corners; anda second insulating layer conformally covering the at least three corners formed by the top surface and the multi-step edge of the bonding pad.2. The semiconductor device structure as claimed in claim 1 , further comprising:a third insulating layer formed over the second insulating layer; andan under bump metallization layer formed over the third insulating layer and passing through the third insulating layer and the second insulating layer to contact the top surface of the bonding pad.3. The semiconductor device structure as claimed in claim 1 , wherein the multi-step edge of the bonding pad defines a first step and a second step over the first step claim 1 , and wherein the first step and the second step each have a substantially vertical sidewall.4. The semiconductor device structure as claimed in claim 1 , wherein the multi-step edge of the bonding pad defines a first step and a second step over the first step claim 1 , and wherein the first ...

LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME

Provided are a light emitting device and a method of fabricating the same. The light emitting device includes: a light emitting structure including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer and including a first surface and a second surface; first and second contact electrodes each ohmic-contacting the first and second conductivity type semiconductor layers; and first and second electrodes disposed on the first surface of the light emitting structure, in which the first and second electrodes each include sintered metal particles and the first and second electrodes each include inclined sides of which the tangential gradients with respect to sides of vertical cross sections thereof are changing. 1. A light emitting device , comprising:a light emitting structure including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer disposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, the light emitting structure disposed between a first surface and a second surface opposite to the first surface;first and second contact electrodes disposed on the first surface of the light emitting structure to be in ohmic-contact with the first and second conductivity type semiconductor layers, respectively;a first electrode disposed on the first surface of the light emitting structure and electrically connected to the first contact electrode;a second electrode disposed on the first surface of the light emitting structure and electrically connected to the second contact electrode; andan insulating part covering sides of the first and second electrodes and the first surface of the light emitting structure,wherein the first and second electrodes, each including metal particles, andthe first and second electrodes, each including an inclined side having tangential gradients with respect to a ...

Methods for Making Multi-Die Package With Bridge Layer

A device is provided. The device includes a bridge layer over a first substrate. A first connector electrically connecting the bridge layer to the first substrate. A first die is coupled to the bridge layer and the first substrate, and a second die is coupled to the bridge layer. 1. A device , comprising:a first substrate comprising a plurality of first contacts extending along a first surface of the first substrate;a bridge overlying the first substrate, the bridge comprising a plurality of second contacts extending along a second surface of the bridge, second contacts of the plurality of second contacts being positioned along one or more edges of the second surface of the bridge, and the second surface of the bridge facing away from the first surface of the first substrate;a plurality of electrical connectors, wherein the plurality of electrical connectors electrically connect the plurality of second contacts to the plurality of first contacts, and each of the plurality of electrical connectors extends along a sidewall of the bridge;a first die overlying the bridge, wherein a perimeter of the first die is within a perimeter of the bridge in a plan view; anda second die overlying the bridge, wherein the second die partially overlaps the bridge and extends beyond the bridge in the plan view.2. The device according to claim 1 , wherein the first die comprises a plurality of blocks claim 1 , and each of the plurality of blocks comprises a respective plurality of third contacts.3. The device according to claim 2 , wherein the second die is connected to the respective plurality of third contacts of each of the plurality of blocks of the first die by a plurality of redistribution layers of the bridge.4. The device according to claim 1 , wherein each of the plurality of electrical connectors is a conductive bump that contacts the sidewall of the bridge.5. The device according to claim 4 , wherein a height of the plurality of electrical connectors over the first substrate ...

Method for bonding bare chip dies

A method is provided for assembly of a micro-electronic component comprising the steps of: providing a conductive die bonding material comprising of a conductive thermosettable resin material or flux based solder and a dynamic release layer adjacent to the conductive thermoplastic material die bonding material layer; and impinging a laser beam on the dynamic release layer adjacent to the die bonding material layer; in such a way that the dynamic release layer is activated to direct conductive die bonding material matter towards the pad structure to be treated to cover a selected part of the pad structure with a transferred conductive die bonding material; and wherein the laser beam is restricted in timing and energy, in such a way that the die bonding material matter remains thermosetting. Accordingly adhesive matter can be transferred while preventing that the adhesive is rendered ineffective by thermal overexposure in the transferring process.

SEMICONDUCTOR ELEMENT MOUNTING STRUCTURE, AND COMBINATION OF SEMICONDUCTOR ELEMENT AND SUBSTRATE

Provided is a semiconductor element mounting structure, including: a semiconductor element including an element electrode, and a substrate including a substrate electrode that is provided on a surface facing the semiconductor element at a position facing the element electrode, the semiconductor element and the substrate being connected via the element electrode and the substrate electrode, in which: one of the element electrode or the substrate electrode is a first protruding electrode including a solder layer at a tip portion thereof, the other of the element electrode or the substrate electrode is a first electrode pad including one or more metal protrusions on a surface thereof, the one or more metal protrusions of the first electrode pad extend into the solder layer of the first protruding electrode, and a bottom area of each of the one or more metal protrusions of the first electrode pad is 70% or less with respect to an area of the first electrode pad, or 75% or less with respect to a maximum cross-sectional area of the solder layer of the first protruding electrode. 1. A semiconductor element mounting structure , comprising:a semiconductor element comprising an element electrode, and a substrate comprising a substrate electrode that is provided on a surface facing the semiconductor element at a position facing the element electrode, the semiconductor element and the substrate being connected via the element electrode and the substrate electrode, wherein:one of the element electrode or the substrate electrode is a first protruding electrode comprising a solder layer at a tip portion thereof,the other of the element electrode or the substrate electrode is a first electrode pad comprising one or more metal protrusions on a surface thereof,the one or more metal protrusions of the first electrode pad extend into the solder layer of the first protruding electrode, anda bottom area of each of the one or more metal protrusions of the first electrode pad is 75% or ...

Illumination device

An illumination device includes a supporting base, and a light-emitting element inserted in the supporting base. The light-emitting element includes a substrate having a supporting surface and a side surface, a light-emitting chip disposed on the supporting surface, and a first wavelength conversion layer covering the light-emitting chip and only a portion of the supporting surface without covering the side surface.

Illumination device

An illumination device includes a supporting base, and a light-emitting element inserted in the supporting base. The light-emitting element includes a substrate having a supporting surface and a side surface, a light-emitting chip disposed on the supporting surface, and a first wavelength conversion layer covering the light-emitting chip and only a portion of the supporting surface without covering the side surface.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide a method for manufacturing a semiconductor device, and a semiconductor device produced thereby, that comprises an interposer without through silicon vias. 120-. (canceled)21. A method of manufacturing a semiconductor package , the method comprising: a carrier; and', 'an S1 dielectric layer directly on the carrier,', 'wherein the first structure comprises a first S1 side facing away from the carrier, a second S1 side opposite the first S1 side and at least one lateral S1 side that extends between the first S1 side and the second S1 side;, 'providing a first structure (S1) comprising an SDS dielectric layer; and', 'an SDS conductive layer that laterally routes electrical signals;, 'forming a signal distribution structure (SDS) on a first side of the first structure, the signal distribution structure comprisingafter said forming a signal distribution interposer structure, removing the carrier; andattaching a semiconductor die to a side of the signal distribution structure from which the carrier was removed.22. The method of claim 21 , wherein said attaching the semiconductor die to the side of the signal distribution structure comprises claim 21 , after said removing the carrier claim 21 , attaching the semiconductor die directly to the side of the signal distribution structure.23. The method of claim 21 , wherein said forming the signal distribution structure comprises sequentially forming the SDS conductive layer and the SDS dielectric layer after said providing the first structure.24. The method of claim 21 , wherein the first S1 dielectric layer of the provided first structure has no apertures.251. The method of claim claim 21 , wherein the signal distribution structure is TSV-less.261. The method of claim claim 21 , wherein the carrier comprises glass.27. A method of manufacturing a ...

Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths

Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

Package structure and manufacturing method thereof

A package structure and a manufacturing method thereof are disclosed. The package structure includes: a substrate; at least one light emitting diode disposed on the substrate by eutectic bonding; and at least one Zener diode disposed on the substrate by at least one silver glue. The method of manufacturing the package structure includes: providing a substrate; performing a eutectic bonding process to dispose at least one light emitting diode on the substrate; and performing a silver glue bonding process at room temperature to dispose at least one Zener diode on the substrate.

Wafer Level Dicing Method and Semiconductor Device

A semiconductor device includes a plurality of connectors and at least one insulating layer disposed over a semiconductor substrate. A molding layer extends around the plurality of connectors. A sidewall of the molding layer that is closest to a scribe line is offset from the scribe line.

Semiconductor package

A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection hump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.

Semiconductor structure and manufacturing method thereof

The present disclosure provides a semiconductor structure, including a substrate, a conductive pad, a passivation layer, a recess, a bump pad, and a conductive bump. The conductive pad is disposed over the substrate. The passivation layer is disposed over the substrate and partially covers the conductive pad. The recess extends through the passivation layer and extends at least partially into the conductive pad. The bump pad is disposed over the passivation layer and within the recess; and the conductive bump is disposed over the bump pad. A method of manufacturing the semiconductor structure is also provided.

Dual sided fan-out package having low warpage across all temperatures

Semiconductor devices including a dual-sided redistribution structure and having low-warpage across all temperatures and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die electrically coupled to a first side of a redistribution structure and a second semiconductor die electrically coupled to a second side of the redistribution structure opposite the first side. The semiconductor device also includes a first molded material on the first side, a second molded material on the second side, and conductive columns electrically coupled to the first side and extending through the first molded material. The first and second molded materials can have the same volume and/or coefficients of thermal expansion to inhibit warpage of the semiconductor device.

DEVICES AND METHODS RELATED TO RADIO-FREQUENCY FILTERS ON SILICON-ON-INSULATOR SUBSTRATE

Devices and methods related to radio-frequency (RF) filters on silicon-on-insulator (SOI) substrate. In some embodiments, an RF device can include a silicon die such as an SOI die including a first side and a second side. The silicon die can further include a plurality of vias, with each via configured to provide an electrical connection between the first side and the second side of the silicon die. The RF device can further include at least one RF flip chip mounted on the first side of the silicon die. The silicon die can include, for example, an RF circuit such as a switch circuit, and the RF flip chip can include, for example, a filter such as a surface acoustic wave (SAW) filter. 1a silicon die including a radio-frequency circuit, a first side and a second side, and a plurality of vias, each via configured to provide an electrical connection between the first side and the second side of the silicon die; andat least one radio-frequency flip chip mounted on the first side of the silicon die, the radio-frequency flip chip in communication with the radio-frequency circuit.. A radio-frequency device comprising: This application is a continuation of U.S. patent application Ser. No. 15/192,812, filed Jun. 24, 2016, entitled “DEVICES AND METHODS RELATED TO RADIO-FREQUENCY FILTERS ON SILICON-ON-INSULATOR SUBSTRATE,” which claims priority to U.S. Provisional Application No. 62/187,174, filed Jun. 30, 2015, entitled “DEVICES AND METHODS RELATED TO RADIO-FREQUENCY FILTERS ON SILICON-ON-INSULATOR SUBSTRATE,” the disclosure of each of which is hereby expressly incorporated by reference herein in its entirety.The present disclosure relates to, among others, radio-frequency (RF) filters on silicon-on-insulator (SOI) substrate.In some radio-frequency (RF) applications, a signal received or transmitted through an antenna can be routed to different amplification paths through band selection switches and respective filters. In such applications, it is desirable to minimize or ...

FULLY MOLDED PERIPHERAL PACKAGE ON PACKAGE DEVICE

A method of making a semiconductor device may include providing a carrier comprising a semiconductor die mounting site. A build-up interconnect structure may be formed over the carrier. A first portion of a conductive interconnect may be formed over the build-up interconnect structure in a periphery of the semiconductor die mounting site. An etch stop layer and a second portion of the conductive interconnect may be formed over the first portion of the conductive interconnect. A semiconductor die may be mounted to the build-up interconnect at the semiconductor die mounting site. The conductive interconnect and the semiconductor die may be encapsulated with a mold compound. A first end of the conductive interconnect on the second portion of the conductive interconnect may be exposed. The carrier may be removed to expose the build-up interconnect structure. The first portion of the conductive interconnect may be etched to expose the etch stop layer. 1. A method of making a semiconductor device , comprising:providing a carrier comprising a semiconductor die mounting site;forming a build-up interconnect structure over the carrier;forming a first portion of a conductive interconnect over the build-up interconnect structure in a periphery of the semiconductor die mounting site;forming an etch stop layer over the first portion of the conductive interconnect;forming a second portion of the conductive interconnect over the etch stop layer and over the first portion of the conductive interconnect;mounting a facedown semiconductor die to the build-up interconnect at the semiconductor die mounting site;encapsulating the conductive interconnect and semiconductor die with a mold compound;exposing a first end of the conductive interconnect on the second portion of the conductive interconnect;removing the carrier to expose the build-up interconnect structure; andetching the first portion of the conductive interconnect to expose the etch stop layer.2. The method of claim 1 , wherein ...

Display device

A display device includes: a display panel; a driver integrated circuit (IC) including a first surface electrically connected to the display panel and a second surface opposing the first surface and electrically connected to the first surface; and a connecting structure including a first side portion electrically connected to the second surface of the driver IC, and a second side portion electrically connected to an external device.

Conductive particle, and connection material, connection structure, and connecting method of circuit member

There is provided a conductive particle including a core particle containing a resin material, and a surface layer that covers a surface of the core particle and contains a solder material, in which a melting point of the solder material is equal to or lower than a softening point of the resin material.

Reversed build-up substrate for 2.5d

A method of making an assembly can include forming a circuit structure defining front and rear surfaces, and forming a substrate onto the rear surface. The forming of the circuit structure can include forming a first dielectric layer coupled to the carrier. The first dielectric layer can include front contacts configured for joining with contacts of one or more microelectronic elements, and first traces. The forming of the circuit structure can include forming rear conductive elements at the rear surface coupled with the front contacts through the first traces. The forming of the substrate can include forming a dielectric element directly on the rear surface. The dielectric element can have first conductive elements facing the rear conductive elements and joined thereto. The dielectric element can include second traces coupled with the first conductive elements. The forming of the substrate can include forming terminals at a surface of the substrate.

Semiconductor device and method for manufacturing the same

A semiconductor device includes a first electronic component, a second electronic component and a plurality of interconnection structures. The first electronic component has a first surface. The second electronic component is over the first electronic component, and the second electronic component has a second surface facing the first surface of the first electronic component. The interconnection structures are between and electrically connected to the first electronic component and the second electronic component, wherein each of the interconnection structures has a length along a first direction substantially parallel to the first surface and the second surface, a width along a second direction substantially parallel to the first surface and the second surface and substantially perpendicular to the first direction, and the length is larger than the width of at least one of the interconnection structures.

Assembly comprising hybrid interconnecting means including intermediate interconnecting elements and sintered metal joints, and manufacturing process

An assembly includes at least one first element comprising at least one first electrical bonding pad; at least one second element comprising at least one second electrical bonding pad; electrical and mechanical interconnect means, wherein the electrical and mechanical interconnect means comprise at least: at least one first intermediate metal interconnect element, on the surface of at least the first electrical bonding pad; at least one sintered joint of metal microparticles or nanoparticles stacked with the first intermediate metal interconnect element; the melting point of the first intermediate metal interconnect element being greater than the sintering temperature of the metal microparticles or nanoparticles. A method for fabricating an assembly is also provided.

Semiconductor Packages and Methods of Forming the Same

Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a redistribution layer coupled to the one or more dies at a first side of the first package with a first set of bonding joints. The redistribution layer including more than one metal layer disposed in more than one passivation layer, the first set of bonding joints being directly coupled to at least one of the one or more metal layers, and a first set of connectors coupled to a second side of the redistribution layer, the second side being opposite the first side. 1. A semiconductor package comprising:a die having a contact pad on a first surface;molding compound along sidewalls of the die;a first bonding structure on the contact pad, the first bonding structure extending away from the first surface;a redistribution structure, the redistribution structure comprising a first conductive line and a passivation layer covering a first portion of the first conductive line; anda second bonding structure coupled to a second portion of the first conductive line and the first bonding structure, wherein the passivation layer is interposed between the first conductive line and the die, a sidewall of the passivation layer being spaced apart from the second bonding structure.2. The semiconductor package of claim 1 , further comprising another second bonding structure claim 1 , wherein the passivation layer is interposed between the second bonding structure and the another second bonding structure.3. The semiconductor package of claim 1 , wherein the second bonding structure extends further from the first conductive line than the passivation layer.4. The semiconductor package of claim 1 , further comprising a solder material bonding the first bonding structure to the second bonding structure.5. The semiconductor package of claim 1 , wherein contact pad comprises a through via ...

Semiconductor structure and manufacturing method thereof

A semiconductor structure and manufacturing method thereof are provided. The semiconductor structure includes a metallization structure with a dielectric surface. A first protecting structure is on the dielectric surface. A conductive pad is on the dielectric surface and is leveled with the first protecting structure. A polymer layer is over the first protecting structure and the conductive pad. A conductive bump is electrically coupled to the conductive pad through an opening of the polymer layer. A method for manufacturing a semiconductor structure is also provided.

Quantum dot led package and quantum dot led module including the same

A quantum dot LED package is disclosed. The quantum dot LED package includes: a heat dissipating reflector having a through cavity; a quantum dot plate accommodated in the upper portion of the through cavity; an LED chip accommodated in the lower portion of the through cavity and whose top surface is coupled to the lower surface of the quantum dot plate; electrode pads disposed on the lower surface of the LED chip and protruding more downward than the lower surface of the heat dissipating reflector; and a resin part formed in the through cavity to fix between the LED chip and the reflector and between the quantum dot plate and the reflector.

Method of manufacturing semiconductor package structure

A semiconductor package structure includes a redistribution (RDL) layer, a first chip, at least one second chip, an encapsulant and a third chip. The redistribution layer has a first surface and a second surface opposite to each other. The first chip is over the first surface of the redistribution layer and electrically connected to the redistribution layer. The second chip is over the first surface of the redistribution layer. The second chip includes a plurality of through via structures. The encapsulant is over the first surface of the distribution layer, wherein the encapsulant surrounds the first chip and the second chip. The third chip is over the encapsulant and electrically connected to the first chip through the through via structures of the second chip and the redistribution layer.

Electrode connection method and electrode connection structure

Provided is an electrode connection method and the like which make it possible to connect tightly without leaving a gap, by connecting by plating while electrodes in an electrical circuit contact one another in a dot or linear pattern. Contact is made directly or indirectly in at least part of the interval between a plurality of electrically connected electrodes in an electrical circuit, and the interval between electrodes is plated and connected while a plating fluid flows around the periphery of the contact section. In addition, the contact section maintains a linear or dot pattern. Furthermore, nickel or a nickel alloy or copper or a copper alloy is used as the material for performing the plating, while the material for the surface of the electrodes to be connected is nickel or a nickel alloy, copper or a copper alloy, gold or a gold alloy, silver or a silver alloy, or palladium or a palladium alloy.