Semiconductor chip assembly and method for making same

A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. The vias, compliant layer and substrate contacts are adapted to appreciably relieve stress at the substrate contacts associated with differential thermal contact and expansion of the assembly.

Chip package with plank stack of semiconductor dies

In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are separated by a mechanical spacer (such as a filler material or an adhesive). Moreover, the chip package includes a substrate at a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the substrate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as: solder, stud bumps, plated traces, wire bonds, spring connectors, a conductive adhesive and/or an anisotropic conducting film. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the substrate.

Integrated circuit packaging system with external wire connection and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a package carrier; mounting an integrated circuit to the package carrier; forming an external wire on the package carrier and adjacent to the integrated circuit; forming an encapsulation on the package carrier over the external wire; and forming a hole in the encapsulation with the external wire and a portion of the package carrier exposed from the encapsulation.

Miniaturized Electrical Component Comprising an MEMS and an ASIC and Production Method

The invention relates to a miniaturized electrical component comprising an MEMS chip and an ASIC chip. The MEMS chip and the ASIC chip are disposed on top of each other; an internal mounting of MEMS chip and ASIC chip is connected to external electrical terminals of the electrical component by means of vias through the MEMS chip or the ASIC chip.

Sapphire substrate configured to form light emitting diode chip providing light in multi-directions, light emitting diode chip, and illumination device

A sapphire substrate configured to form a light emitting diode (LED) chip providing light in multi-directions, a LED chip and an illumination device are provided in the present invention. The sapphire substrate includes a growth surface and a second main surface opposite to each other. A thickness of the sapphire substrate is thicker than or equal to 200 micrometers. The LED chip includes the sapphire substrate and at least one LED structure. The LED structure is disposed on the growth surface and forms a first main surface where light emitted from with a part of the growth surface without the LED structures. At least a part of light beams emitted from the LED structure pass through the sapphire substrate and emerge from the second main surface. The illumination device includes at least one LED chip and a supporting base. The LED chip is disposed on the supporting base.

Lead-free solder alloy, solder joining material, electronic circuit mounting substrate, and electronic control device

A lead-free solder alloy includes 2.0% by mass or more and 4.0% by mass or less of Ag, 0.3% by mass or more and 0.7% by mass or less of Cu, 1.2% by mass or more and 2.0% by mass or less of Bi, 0.5% by mass or more and 2.1% by mass or less of In, 3.0% by mass or more and 4.0% by mass or less of Sb, 0.001% by mass or more and 0.05% by mass or less of Ni, 0.001% by mass or more and 0.01% by mass or less of Co, and the balance being Sn.

Planar integrated circuit package interconnects

Generally discussed herein are systems, methods, and apparatuses that include conductive pillars that are about co-planar. According to an example, a technique can include growing conductive pillars on respective exposed landing pads of a substrate, situating molding material around and on the grown conductive pillars, removing, simultaneously, a portion of the grown conductive pillars and the molding material to make the grown conductive pillars and the molding material about planar, and electrically coupling a die to the conductive pillars.

Wafer-level packaging for enhanced performance

The present disclosure relates to a mold module that includes a device layer, a number of first bump structures, a first mold compound, a stop layer, and a second mold compound. The device layer includes a number of input/output (I/O) contacts at a top surface of the device layer. Each first bump structure is formed over the device layer and electronically coupled to a corresponding I/O contact. The first mold compound resides over the device layer, and a portion of each first bump structure is exposed through the first mold compound. The stop layer is formed underneath the device layer. The second mold compound resides underneath the stop layer, such that the stop layer separates the device layer from the second mold compound.

Tall and fine pitch interconnects

Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.

CONDUCTIVE CONNECTIONS, STRUCTURES WITH SUCH CONNECTIONS, AND METHODS OF MANUFACTURE

A solder connection may be surrounded by a solder locking layer () and may be recessed in a hole () in that layer. The recess may be obtained by evaporating a vaporizable portion () of the solder connection. Other features are also provided. 1. A manufacturing method comprising: one or more first components each of which comprises solder and a material sublimatable or vaporizable when the solder is melted; and', 'a first layer comprising a top surface and one or more holes in the top surface, each hole containing at least a segment of a corresponding first component;, 'obtaining a first structure comprisingheating each first component to sublimate or vaporize at least part of each sublimatable or vaporizable material and provide an electrically conductive connection at a location of each first component;wherein in the heating operation at least part of each first component recedes down from the top surface to provide or increase a recess in each hole at the top surface.2. The method of wherein each hole is a through-hole.3. The method of wherein each hole's sidewall is a dielectric sidewall.4. The method of wherein the first layer is dielectric.5. The method of wherein the first layer is formed by molding.6. The method of further comprising:obtaining a second structure with one or more protruding conductive posts; andinserting each conductive post into a corresponding recess provided or increased in the heating operation, and forming a solder bond in each recess between the corresponding conductive post and the corresponding electrically conductive connection.7. The method of wherein before the heating operation claim 1 , at least a segment of each first component either:comprises of a solder core coated with the sublimatable or vaporizable material; orconsists of the sublimatable or vaporizable material.8. The method of wherein in obtaining the first structure claim 7 , the one or more first components are formed before the first layer.9. The method of wherein in ...

Wiring substrate and semiconductor package

A wiring substrate includes an insulating layer and a wiring layer buried in the insulating layer at a first surface of the insulating layer. The wiring layer includes a first portion and a second portion. The first portion is narrower and thinner than the second portion. The first portion includes a first surface exposed at the first surface of the insulating layer. The second portion includes a first surface exposed at the first surface of the insulating layer and a second surface partly exposed in an opening formed in the insulating layer. The opening is open at a second surface of the insulating layer opposite to the first surface thereof.

INTERCONNECT STRUCTURE WITH REDUNDANT ELECTRICAL CONNECTORS AND ASSOCIATED SYSTEMS AND METHODS

Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first semiconductor die and a second conductive film coupled to the second semiconductor die. The interconnect structure further includes a plurality of redundant electrical connectors extending between the first and second conductive films and electrically coupled to one another via the first conductive film. 1. A semiconductor device , comprising:a semiconductor substrate;a dielectric material over the substrate;a conductive trace extending at least partially through the dielectric material; and a conductive member coupled to the conductive trace, and', 'a conductive bond material bonded to the conductive member,, 'a plurality of redundant electrical connectors extending from the conductive trace and through at least a portion of the dielectric material, wherein each of the redundant electrical connectors includes—'}wherein all of the redundant electrical connectors are coupled to the conductive trace.2. The semiconductor device of wherein the dielectric includes a plurality of openings exposing portions of the conductive trace claim 1 , wherein the redundant electrical connectors are formed in the openings.3. The semiconductor device of wherein the conductive member comprises copper and the bond material comprises a solder material.4. The semiconductor device of wherein the conductive member includes an end portion claim 1 , and wherein the conductive bond material and conductive member form a conductive joint at the end portion.5. The semiconductor device of claim 1 , further comprising a through-substrate via (TSV) extending at least partially through the substrate claim 1 , ...

Method for Manufacturing Metal Powder

A method for manufacturing metal powder comprising: providing a basic metal salt solution; contacting the basic metal salt solution with a reducing agent to precipitate metal powder therefrom; and recovering precipitated metal powder from the solvent.

Integrated circuit chip and display device including the same

An exemplary embodiment provides a driving circuit chip including: a substrate; a terminal electrode disposed on the substrate; and an electrode pad disposed on the terminal electrode, wherein the electrode pad includes: a bump structure protruded from the substrate to include a short side and a long side; and a bump electrode disposed on the bump structure and connected with the terminal electrode around a short edge portion of the bump structure, wherein the bump electrode is disposed to not cover at least a part of a long edge portion of the bump structure.

Backplane, Preparation Method Thereof, Backlight Module and Display Device

A preparation method of a backplane includes: forming an insulating structure layer having a groove on a base substrate by a mask exposure process, the groove being used for accommodating a metal trace; and repeating a metal sub-layer forming step including an ashing process and a wet etching process multiple times to form the metal trace positioned in the groove.

SEMICONDUCTOR DEVICE WITH A SEMICONDUCTOR DIE EMBEDDED BETWEEN AN EXTENDED SUBSTRATE AND A BOTTOM SUBSTRATE

A method of manufacturing a semiconductor device having a semiconductor die within an extended substrate and a bottom substrate may include bonding a bottom surface of a semiconductor die to a top surface of a bottom substrate, forming an adhering member to a top surface of the semiconductor die, bonding an extended substrate to the semiconductor die and to the top surface of the bottom substrate utilizing the adhering member and a conductive bump on a bottom surface of the extended substrate and a conductive bump on the bottom substrate. The semiconductor die and the conductive bumps may be encapsulated utilizing a mold member. The conductive bump on the bottom surface of the extended substrate may be electrically connected to a terminal on the top surface of the extended substrate. The adhering member may include a laminate film, a non-conductive film adhesive, or a thermal hardening liquid adhesive. 120-. (canceled)21. An electronic device comprising:a conductive signal distribution layer (SDL) having an upper SDL side and a lower SDL side;a semiconductor die having an upper die side, and a lower die side facing the upper SDL side;a metal contact structure having an upper contact end coupled to the lower die side, and a lower contact end coupled to the upper SDL side;an encapsulating material having an upper encapsulating material side, and a lower encapsulating material side that faces the upper SDL side, wherein the encapsulating material laterally surrounds the semiconductor die and the metal contact structure; anda dielectric layer between lower die side and the upper SDL side and between the lower encapsulating material side and the upper SDL side.22. The electronic device of claim 21 , wherein the lower contact end is coplanar with the lower encapsulating material side.23. The electronic device of claim 21 , wherein the dielectric layer comprises an adhesive layer.24. The electronic device of claim 21 , wherein the dielectric layer comprises a material ...

Semiconductor integrated circuit device

A semiconductor integrated circuit chip, in which multi-core processors are integrated, is usually mounted over an organic wiring board by FC bonding to form a BGA package by being integrated with the substrate. In such a structure, power consumption is increased, and hence the power supplied only from a peripheral portion of the chip is insufficient, so that a power supply pad is also provided in the chip central portion. However, because of an increase in the wiring associated with the integration of a plurality of CPU cores, etc., there occurs a portion between the peripheral portion and the central portion of the chip, where a power supply pad cannot be arranged. According to the outline of the present application, in a semiconductor integrated circuit device such as a BGA, etc., in which a semiconductor chip is mounted over an interposer, such as a multilayer organic wiring board, in a face-up manner, a first group of metal through electrodes, which are provided in the semiconductor chip to supply a power supply potential to a core circuit, etc., and a first metal land over the interposer are interconnected by a first conductive adhesive member film.

Warpage Control for Flexible Substrates

A flexible substrate may be provided having a first side and a second side. A device may be electrically coupled to the first side of the flexible substrate through one or more electrical connections. A warpage control device may be attached to the second side flexible substrate. The warpage control device may include an adhesive layer and a rigid layer. The warpage control device may be formed in an area of the second side of the flexible substrate that may be opposite the one or more electrical connections on the first side of the flexible substrate.

METHOD OF FORMING A SOLDER BUMP STRUCTURE

A solder bump structure includes a pillar formed on an electrode pad. The pillar has a concave curve-shaped surface and a geometry defined at least in part by dimensions including a first height greater than a first width. The solder bump structure further includes solder formed on the concave curve-shaped surface of the pillar. The solder has a convex top surface and having dimensions including a second height greater than a second width due to the geometry of the pillar. 1. A solder bump structure comprising:a pillar formed on an electrode pad, the pillar having a concave curve-shaped surface and a geometry defined at least in part by dimensions including a first height greater than a first width; andsolder formed on the concave curve-shaped surface of the pillar, the solder having a convex top surface and having dimensions including a second height greater than a second width due to the geometry of the pillar.2. The solder bump structure according to claim 1 , wherein the solder is in contact with an entirety of the curve-shaped surface of the pillar.3. The solder bump structure according to claim 1 , wherein the pillar includes at least one material selected from the group consisting of: copper claim 1 , nickel claim 1 , silver and gold.4. The solder bump structure according to claim 1 , wherein a thickness of a central portion of the pillar is in a range of ⅕ to ⅔ of a length from a surface of the electrode pad to the convex top surface of the solder.5. The solder bump structure according to claim 4 , wherein the electrode pad includes aluminum.6. The solder bump structure according to claim 1 , wherein a thickness of a central portion of the pillar is in a range of 1 to 50 micrometers.7. The solder bump structure according to claim 1 , wherein the solder has a non-spherical shape.8. A solder bump structure comprising:a resist layer including an opening;a pillar formed on an electrode pad and in the opening of the resist layer, the pillar having a concave curve ...

Light-reflective anisotropic conductive adhesive agent, and light emitting device

A light-reflective anisotropic conductive adhesive is used for anisotropic conductive connection of a light-emitting element to a wiring board. The adhesive includes a thermosetting resin, conductive particles, and light-reflective acicular insulating particles. The conductive particles comprise a core particle coated with a metal particle or a metal material, and a light reflective layer formed on a surface of the core particle. The light reflective layer comprises inorganic particles selected from any one of titanium oxide particles, zinc oxide particles or aluminum oxide particles until the entire conductive particle appears a color in a range from white to gray.

Hybrid bonding structures, semiconductor devices having the same, and methods of manufacturing the semiconductor devices

Provided are a hybrid bonding structure, a solder paste composition, a semiconductor device, and a method of manufacturing the semiconductor device. The hybrid bonding structure includes a solder ball and a solder paste bonded to the solder ball. The solder paste includes a transient liquid phase. The transient liquid phase includes a core and a shell on a surface of the core. A melting point of the shell may be lower than a melting point of the core. The core and the shell are configured to form an intermetallic compound in response to the transient liquid phase at least partially being at a temperature that is within a temperature range of about 20° C. to about 190° C.

Package on package structure and method of manufacturing the same

A package on package structure includes a first substrate having a first region and a second region, a bump formed on the first region of the first substrate, a first semiconductor die bonded to the second region of the first substrate, and a semiconductor die package bonded to the first substrate. The bump includes a metallic structure and a plurality of minor elements dispersed in the metallic structure. The semiconductor die package includes a connector bonded to the bump, and the first semiconductor die is between the semiconductor die package and the first substrate.

Wafer level integration including design/co-design, structure process, equipment stress management and thermal management

A multi-layer wafer and method of manufacturing such wafer are provided. The method comprises applying at least one stress compensating polymer layer to at least one of two heterogeneous wafers and low temperature bonding the two heterogeneous wafers to bond the stress compensating polymer layer to the other of the two heterogeneous wafers to form a multi-layer wafer pair. The multi-layer wafer comprises two heterogeneous wafers, at least one of the heterogeneous wafers having a stress compensating polymer layer. The two heterogeneous wafers are low temperature bonded together to bond the stress compensating polymer layer to the other of the two heterogeneous wafers.

Dual side cooling power module and manufacturing method of the same

A dual side cooling power module includes: a lower substrate including a recessed portion on at least one surface thereof, a semiconductor chip formed in the recessed portion, lead frames formed at both ends of the lower substrate, and an upper substrate formed on the semiconductor chip, a portion of the lead frames, and the lower substrate.

ADHESIVE COMPOSITION, ELECTRONIC-COMPONENT-MOUNTED SUBSTRATE AND

There are provided are an adhesive composition that keeps storage stability and further gives a cured product wherein metallic bonds are formed in the state that the cured product wets its components and is satisfactorily spread between the components (or parts), thereby turning excellent in adhesive property, electroconductivity, and reliability for mounting such as TCT resistance or high-temperature standing resistance; an electronic-component-mounted substrate using the same; and a semiconductor device. The adhesive composition comprises electroconductive particles (A) and a binder component (B), wherein the electroconductive particles (A) include a metal (a1) having a melting point equal to or higher than the reflow temperature and containing no lead, and a metal (a2) having a melting point lower than the reflow temperature and containing no lead, and the binder component (B) includes a thermosetting resin composition (b1) and an aliphatic dihydroxycarboxylic acid (b2). 2. The electronic component structure according to claim 1 , wherein R1 in the general formula (1) is an alkyl group having 1 to 5 carbon atom.3. The electronic component structure according to claim 1 , wherein the aliphatic dihydroxycarboxylic acid (b2) includes 2 claim 1 ,2-bishydroxymethylpropionic acid claim 1 , 2 claim 1 ,2-bishydroxymethylbutanoic acid claim 1 , and 2 claim 1 ,2-bishydroxymethylpentanoic acid.4. The electronic component structure according to claim 1 , wherein the reflow temperature is the temperature for mounting with SnAgCu cream solder.5. The electronic component structure according to claim 1 , wherein the reflow temperature is 260° C.6. The electronic component structure according to claim 1 , wherein the content of the aliphatic dihydroxycarboxylic acid (b2) is 0.1 part or more by weight and 20 parts or less by weight for 100 parts by weight of the metal (a2) having the melting point lower than the reflow temperature and containing no lead.7. The electronic component ...

Semiconductor device and method for manufacturing the same

A semiconductor device includes a dielectric interposer, a first interconnection layer, an electronic component, a plurality of electrical conductors and a plurality of conductive structures. The dielectric interposer has a first surface and a second surface opposite to the first surface. The first interconnection layer is over the first surface of the dielectric interposer. The electronic component is over and electrically connected to the first interconnection layer. The electrical conductors are over the second surface of the dielectric interposer. The conductive structures are through the dielectric interposer, wherein the conductive structures are electrically connected to the first interconnection layer and the electrical conductors.

Junction and electrical connection

A junction at which at least two conductors are connected together includes a compound region containing Cu, Sn and at least one element selected from the group consisting of Si, B, Ti, Al, Ag, Bi, In, Sb, Ga and Zn. The compound region forms a nanocomposite metal diffusion region with the conductor.

Tall and Fine Pitch Interconnects

Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers. 1. A method , comprising:applying a conductive layer to a temporary carrier;patterning the conductive layer to form a patterned conductive structure;applying a nonwettable layer to the patterned conductive structure;patterning the nonwettable layer to form nonwettable barriers on the patterned conductive structure;depositing a reflowable conductive material on the patterned conductive structure, between the nonwettable barriers, to form interconnect structures;mounting a first microelectronic element to the interconnect structures;removing the temporary carrier;mounting a second microelectronic element with interconnect structures onto the patterned conductive structure, on a side previously occupied by the temporary carrier; andcoupling the IC die to the patterned conductive structure via heated reflow.2. The method of claim 1 , further comprising patterning the nonwettable layer by removing the nonwettable layer from the patterned conductive structure claim 1 , except at one or more edges of the patterned conductive structure.3. The method of claim 1 , further comprising forming nonwettable barriers having closed geometric shapes with open interiors on the patterned conductive structure.4. The method of claim 1 , further comprising forming nonwettable barriers having partly-closed predefined shapes with open interiors on the patterned conductive structure.5. The method of claim 1 , wherein the nonwettable layer comprises a polymer or poly imide material.6. ...

Semiconductor packages

A semiconductor package includes a first substrate, a first flow channel and a second flow channel. The first flow channel is on the first substrate. The second flow channel is on the first substrate and in fluid communication with the first flow channel. The second flow channel is spaced from an inlet and an outlet of the first flow channel. The first flow channel and the second flow channel constitute a bonding region of the first substrate.

FLEXIBLE LIGHTING DEVICE INCLUDING A NANO-PARTICLE HEAT SPREADING LAYER

A lighting device is provided, including: a substrate having a first surface and a second surface opposite the first surface; one or more light-emitting structures formed on the first surface of the substrate; and a heat spreading and dissipating layer formed on the second surface of the substrate, wherein the heat spreading and dissipating layer comprises a polymer layer mixed with nano graphite particles. 110-. (canceled)11. A method of forming a lighting device , comprising:providing a substrate having a first surface and a second surface opposite the first surface;forming one or more light-emitting structures on the first surface of the substrate; andapplying a heat spreading and dissipating layer on the second surface of the substrate,wherein the heat spreading and dissipating layer comprises a polymer layer mixed with nano graphite particles.12. The method of claim 11 ,wherein the heat spreading and heat dissipating film is between 0.01 mm and 0.5 mm thick.13. The lighting device of claim 11 ,wherein the nano graphite particles are between 0.01 μm and 20 μm in diameter.14. The lighting device of claim 11 ,wherein the polymer layer comprises at least one of polyethylene, polyurethane, or poly(methyl methacrylate) (PMMA).15. The lighting device of claim 11 ,wherein the operation of applying the heat spreading and dissipating layer on the second surface of the substrate involves spraying or painting the heat spreading and dissipating layer on the second surface of the substrate.16. A method of forming a lighting device claim 11 , comprising:providing a substrate having a first surface and a second surface opposite the first surface;forming one or more light-emitting structures on the first surface of the substrate;forming a heat dissipating structure on the second surface of the substrate; andapplying a heat spreading and heat dissipating film on the heat dissipating structure,wherein the heat spreading and dissipating film comprises a polymer layer mixed with ...

Advanced Solder Alloys For Electronic Interconnects

Improved electrical and thermal properties of solder alloys are achieved by the use of micro-additives in solder alloys to engineer the electrical and thermal properties of the solder alloys and the properties of the reaction layers between the solder and the metal surfaces. The electrical and thermal conductivity of alloys and that of the reaction layers between the solder and the -metal surfaces can be controlled over a wide range of temperatures. The solder alloys produce stable microstructures wherein such stable microstructures of these alloys do not exhibit significant changes when exposed to changes in temperature, compared to traditional interconnect materials. 1. A lead-free , antimony-free solder alloy comprising:(a) 10 wt. % or less of silver(b) 10 wt. % or less of bismuth(c) 3 wt. % or less of copper up to 1 wt. % of nickel', 'up to 1 wt. % of titanium', 'up to 1 wt. % of cobalt', 'up to 3.5 wt. % of indium', 'up to 1 wt. % of zinc', 'up to 1 wt. % of cerium, '(d) at least one of the following elements'} 0 to 1 wt. % of manganese', '0 to 1 wt. % of chromium', '0 to 1 wt. % of germanium', '0 to 1 wt. % of iron', '0 to 1 wt. % of aluminum', '0 to 1 wt. % of phosphorus', '0 to 1 wt. % of gold', '0 to 1 wt. % of gallium', '0 to 1 wt. % of tellurium', '0 to 1 wt. % of selenium', '0 to 1 wt. % of calcium', '0 to 1 wt. % of vanadium', '0 to 1 wt. % of molybdenum', '0 to 1 wt. % of platinum', '0 to 1 wt. % of magnesium', '0 to 1 wt. % of rare earths, '(e) optionally one or more of the following elements'}(f) the balance tin, together with any unavoidable impurities.2. A lead-free , solder alloy comprising:(a) 10 wt. % or less of silver(b) 10 wt. % or less of bismuth(c) 3 wt. % or less of copper(d) 4 wt % or less of antimony up to 1 wt % of Ni', 'up to 1 wt. % of titanium', 'up to 1 wt. % of cobalt', 'up to 3.5 wt. % of indium', 'up to 1 wt. % of zinc', 'up to 1 wt. % of cerium, '(e) at least one of the following elements'} 0 to 1 wt. % of manganese', '0 to 1 wt. ...

Carbon nanotube structure, heat dissipation sheet, and method of manufacturing carbon nanotube structure

A carbon nanotube structure includes a plurality of carbon nanotubes, and a graphite film that binds one ends of the plurality of carbon nanotubes. And a heat dissipation sheet includes a plurality of carbon nanotube structures arranged in a sheet form, wherein each of the carbon nanotube structures includes a plurality of carbon nanotubes, and a graphite film that binds one ends of the plurality of carbon nanotubes.

FULLY MOLDED MINIATURIZED SEMICONDUCTOR MODULE

A semiconductor module can comprise a fully molded base portion comprising a planar surface that further comprises a semiconductor die comprising contact pads, conductive pillars coupled to the contact pads and extending to the planar surface, and an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion. A build-up interconnect structure comprising a routing layer can be disposed over the fully molded base portion. A photo-imageable solder mask material can be disposed over the routing layer and comprise openings to form surface mount device (SMD) land pads electrically coupled to the semiconductor die and the conductive pillars. A SMD component can be electrically coupled to the SMD land pads with surface mount technology (SMT). 1. A semiconductor module , comprising: a semiconductor die comprising contact pads,', 'conductive pillars coupled to the contact pads and extending to the planar surface, and', 'an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion;, 'a fully molded base portion comprising a planar surface that further comprisesa build-up interconnect structure comprising a routing layer disposed over the fully molded base portion;a photo-imageable solder mask material disposed over the routing layer and comprising openings to form surface mount device (SMD) land pads electrically coupled to the semiconductor die and the conductive pillars; anda SMD component electrically coupled to the SMD land pads with surface mount technology (SMT).2. The semiconductor module of claim 1 , wherein the photo-imageable solder mask comprises at least one of epoxy solder resist claim 1 , ...

FORMING OF BUMP STRUCTURE

A technique for fabricating a bump structure is disclosed. A substrate that includes a set of pads formed on a surface thereof is prepared, in which the pads includes first conductive material. A metallic adhesion layer is coated on each pad. A bump base is formed on each pad by sintering conductive particles using a mold layer, in which the conductive particles includes second conductive material different from the first conductive material. 1. A method of fabricating a bump structure , the method comprising:preparing a substrate including a set of pads formed on a surface thereof, the pads comprising first conductive material;coating a metallic adhesion layer on each of the pads; andforming a bump on each of the pads by sintering conductive particles using a mold layer, the conductive particles comprising second conductive material different from the first conductive material.2. The method of claim 1 , wherein the mold layer has a set of openings each aligned with one of the pads and forming the bump on each of the pads comprises:disposing the mold layer on the substrate;filling conductive particles into the openings of the mold layer, the conductive particles filled in the openings of the mold layer being sintered to give a bump base on each of the pads; andfilling solder material into remaining space in each of the openings of the mold layer above the bump base to form a solder cap on each bump base.3. The method of claim 1 , wherein the first conductive material comprises Al and the second conductive material comprises Cu.4. The method of claim 2 , wherein the conductive particles are provided in a form of a paste and the bump base formed on each of the pads has a shape of a cup conforming to a contour of the opening of the mold layer and a bottom bonded to the pad by the metallic adhesion layer.5. The method of claim 2 , wherein the method further comprises:applying a resist layer over the surface of the substrate;patterning the resist layer to fabricate the ...

Methods of processing semiconductor devices

Methods of processing a semiconductor device include providing a patterned mask over a major surface of a substrate and comprising at least one opening exposing a conductive structure, and depositing particles of material by direct material deposition adjacent and in contact with an edge wall of the mask adjacent the at least one opening to form a supplemental mask over the major surface of the substrate. Other methods of processing semiconductor devices include depositing particles of material by direct material deposition adjacent a conductive structure at an intersection of the conductive structure and a surface of a substrate.

Semiconductor device and a method of manufacturing thereof

A semiconductor device comprises a semiconductor die, comprising a stacking structure, a first bonding pad with a first bonding surface positioned away from the stack structure, and a second bonding pad; a carrier comprising a connecting surface; a third bonding pad which comprises a second bonding surface and is arranged on the connecting surface, and a fourth bonding pad arranged on the connecting surface of the carrier; and a conductive connecting layer comprising a first conductive part, comprising a first outer contour, and formed between and directly contacting the first bonding pad and the third bonding pad; a second conductive part formed between the second bonding pad and the fourth bonding pad; and a blocking part covering the first conductive part to form a covering area, wherein the first bonding surface comprises a first position which is the closest to the carrier within the covering area and a second position which is the farthest from the carrier within the covering area in a cross section view, and a distance from the first position to the first out contour is greater than that from the second position to the first outer contour.

Anchoring structure of fine pitch bva

A microelectronic package can include a substrate having a first surface and a second surface opposite therefrom, the substrate having a first conductive element at the first surface, and a plurality of wire bonds, each of the wire bonds having a base electrically connected to a corresponding one of the first conductive elements and having a tip remote from the base, each wire bond having edge surfaces extending from the tip toward the base. The microelectronic package can also include an encapsulation having a major surface facing away from the first surface of the substrate, the encapsulation having a recess extending from the major surface in a direction toward the first surface of the substrate, the tip of a first one of the wire bonds being disposed within the recess, and an electrically conductive layer overlying an inner surface of the encapsulation exposed within the recess, the electrically conductive layer overlying and electrically connected with the tip of the first one of the wire bonds.

Pad design for thermal fatigue resistance and interconnect joint reliability

Embodiments described herein provide techniques for forming an interconnect structure that includes micro features formed therein. Such embodiments can assist with improving interconnect joint reliability when compared to conventional pads that have a flat surface. An interconnect structure may comprise: a metal pad over a substrate (e.g., a semiconductor package, a PCB, an interposer, etc.). Micro features may be formed in an edge of the metal pad or away from the edge of the metal pad. The micro features can assist with: (i) increasing the contact area between solder used to form an interconnect joint and the metal pad; and (ii) improving adherence of solder used to form an interconnect joint to the metal pad. These benefits can improve interconnect joint reliability by, among others, improving the interconnect joint's ability to absorb stress from substrates having differing coefficients of thermal expansion.

Semiconductor device

A semiconductor device includes a first electronic component, a second electronic component, a third electronic component, a plurality of first interconnection structures, and a plurality of second interconnection structures. The second electronic component is between the first electronic component and the third electronic component. The first interconnection structures are between and electrically connected to the first electronic component and the second electronic component. Each of the first interconnection structures has a length along a first direction substantially parallel to a surface of the first electronic component and a width along a second direction substantially parallel to the surface and substantially perpendicular to the first direction. The length is larger than the width. The second interconnection structures are between and electrically connected to the second electronic component and the third electronic component.

Electronics package having a multi-thickness conductor layer and method of manufacturing thereof

An electronics package includes an insulating substrate, a first electrical component coupled to a first surface of the insulating substrate, and a first conductor layer formed on the first surface of the insulating substrate. A second conductor layer is formed on a second surface of the insulating substrate, opposite the first surface, the second conductor layer extending through vias in the insulating substrate to contact at least one contact pad of the first electrical component and couple with the first conductor layer. The electronics package also includes a second electrical component having at least one contact pad coupled to the first conductor layer. The first conductor layer has a thickness greater than a thickness of the second conductor layer.

WAFER LEVEL INTEGRATION INCLUDING DESIGN/CO-DESIGN, STRUCTURE PROCESS, EQUIPMENT STRESS MANAGEMENT AND THERMAL MANAGEMENT

A method of manufacturing a multi-layer wafer is provided. The method comprises creating under bump metallization (UMB) pads on each of the two heterogeneous wafers; applying a conductive means above the UMB pads on at least one of the two heterogeneous wafers; and low temperature bonding the two heterogeneous wafers to adhere the UMB pads together via the conductive means. At least one stress compensating polymer layer may be applied to at least one of two heterogeneous wafers. The multi-layer wafer comprises two heterogeneous wafers, each of the heterogeneous wafer having UMB pads and at least one of the heterogeneous wafers having a stress compensating polymer layer and a conductive means applied above the UMB pads on at least one of the two heterogeneous wafers. The two heterogeneous wafers low temperature bonded together to adhere the UMB pads together via the conductive means. 1. A method of manufacturing a multi-layer wafer comprising:creating under bump metallization pads on each of the two heterogeneous wafers;applying a conductive means above the under bump metallization pads on at least one of the two heterogeneous wafers; andlow temperature bonding the two heterogeneous wafers to adhere the under bump metallization pads together via the conductive means to form a multi-layer wafer pair.2. The method of claim 1 , further comprising:applying at least one stress compensating polymer and/or adhesive layer to at least one of two heterogeneous wafers3. The method of claim 1 , wherein each of the two heterogeneous wafers are formed from at least one of: complementary metal-oxide semiconductor (CMOS) and GaN on Si claim 1 , CMOS and glass claim 1 , CMOS and sapphire claim 1 , CMOS and SiC on Si claim 1 , CMOS and diamond on Si claim 1 , or CMOS and sapphire on Si.4. The method of claim 1 , wherein the stress compensating polymer layer is formed on the at least one heterogeneous wafer by:applying a liquid polymer to the at least one of the two heterogeneous ...

Microelectronic package with stacked microelectronic units and method for manufacture thereof

A microelectronic package may include a first microelectronic unit including a semiconductor chip having first chip contacts, an encapsulant contacting an edge of the semiconductor chip, and first unit contacts exposed at a surface of the encapsulant and electrically connected with the first chip contacts. The package may include a second microelectronic unit including a semiconductor chip having second chip contacts at a surface thereof, and an encapsulant contacting an edge of the chip of the second unit and having a surface extending away from the edge. The surfaces of the chip and the encapsulant of the second unit define a face of the second unit. Package terminals at the face may be electrically connected with the first unit contacts through bond wires electrically connected with the first unit contacts, and the second chip contacts through metallized vias and traces formed in contact with the second chip contacts.

System and Method for an Improved Fine Pitch Joint

Presented herein are an interconnect and method for forming the same, the method comprising forming an interconnect on a mounting surface of a mounting pad disposed on a first surface of a first substrate, the interconnect comprising a conductive material, optionally solder or metal, the interconnect avoiding the sides of the mounting pad. A molding compound is applied to the first surface of the first substrate and molded around the interconnect to covering at least a lower portion of the interconnect and a second substrate may be mounted on the interconnect. The interconnect may comprise an interconnect material disposed between a first and second substrate and a molding compound disposed on a surface of the first substrate, and exposing a portion of the interconnect. A sidewall of the interconnect material contacts the mounting pad at an angle less than about 30 degrees from a plane perpendicular to the first substrate.

Semiconductor device

A semiconductor device includes an electric conductor, a semiconductor element, and a bonding layer. The electric conductor has a main surface and a rear surface opposite to the main surface in a thickness direction. The semiconductor element includes a main body and electrodes. The main body has a side facing the main surface of the conductor, and the electrodes each protrude toward the main surface from the side of the main body to be electrically connected to the main surface. The bonding layer is held in contact with the main surface and the electrodes. Each electrode includes a base portion in contact with the main body, and a columnar portion protruding toward the main surface from the base portion to be held in contact with the bonding layer, which is a sintered body of a metal powder.

Flexible packages including chips

A flexible package may be provided. The flexible package may include a flexible molding member including a top surface. The flexible package may include a first chip within the flexible molding member, and including a first top surface. The flexible package may include a second chip within the flexible molding member, and including a second top surface. The first top surface may face away from the top surface of the flexible molding member and the second top surface may face towards the top surface of the flexible molding member.

Packaged semiconductor device with a particle roughened surface

A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame. A packaged semiconductor device with a particle roughened surface on a portion of the lead frame that improves adhesion between the molding compound and the lead frame and with a reflow wall that surrounds a portion of the solder joint that couples the semiconductor device to the lead frame. A packaged semiconductor device with a reflow wall that surrounds a portion of a solder joint that couples a semiconductor device to a lead frame.

METHOD OF FORMING A SOLDER BUMP STRUCTURE

A method of the present invention includes preparing a substrate having a surface on which a electrode pad is formed, forming a resist layer on the substrate, the resist layer having an opening on the electrode pad, filling conductive paste in the opening of the resist layer; sintering the conductive paste in the opening to form a conductive layer which covers a side wall of the resist layer and a surface of the electrode pad in the opening, a space on the conductive layer leading to the upper end of the opening being formed, filling solder in the space on the conductive layer and removing the resist layer. 1. A method of forming a solder bump structure , comprising the steps of:filling conductive paste in an opening of a layer formed over an electrode pad;sintering the conductive paste in the opening to cause shrinkage of the conductive paste to form a conductive layer having a cone-shaped surface formed therein, the conductive layer covering a side wall of the opening and a surface of the electrode pad in the opening; andfilling solder in the cone-shaped surface on the conductive layer.2. The method according to claim 1 , wherein the step of filling conductive paste includes a step of screen-printing conductive paste containing metal nanoparticles in a solvent on the substrate.3. The method according to claim 1 , wherein the step of filling conductive paste includes a step of injecting conductive paste containing metal nanoparticles in a solvent into the opening.4. The method according to claim 1 , wherein the conductive paste includes at least one of copper claim 1 , nickel claim 1 , silver or gold.5. The method according to claim 1 , wherein a cross-section of the conductive layer has a conformal shape.6. The method according to claim 1 , wherein a thickness of a central portion of a cross-section of the conductive layer is in a range of ⅕ to ⅔ of a depth of the opening.7. The method according to claim 1 , further comprising a step of etching a surface of the ...

Advanced Solder Alloys For Electronic Interconnects

Improved electrical and thermal properties of solder alloys are achieved by the use of micro-additives in solder alloys to engineer the electrical and thermal properties of the solder alloys and the properties of the reaction layers between the solder and the metal surfaces. The electrical and thermal conductivity of alloys and that of the reaction layers between the solder and the -metal surfaces can be controlled over a wide range of temperatures. The solder alloys produce stable microstructures wherein such stable microstructures of these alloys do not exhibit significant changes when exposed to changes in temperature, compared to traditional interconnect materials.

Structures to enable a full intermetallic interconnect

A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder bump including a nickel copper colloid surrounded by a nickel or copper shell and suspended in a tin-based solder; aligning the chip with the laminate; performing a first reflow process to join the chip to the laminate; depositing an underfill material around the first solder bump and the second solder bump; and performing a second reflow process at a temperature that is lower than the first reflow process to convert the first solder bump and the second solder bump to an all intermetallic interconnect; wherein depositing the underfill material is performed before or after performing the second reflow process.

Contact structures with porous networks for solder connections, and methods of fabricating same

A contact pad includes a solder-wettable porous network ( 310 ) which wicks the molten solder ( 130 ) and thus restricts the lateral spread of the solder, thus preventing solder bridging between adjacent contact pads.

Semiconductor device

A semiconductor device according to the present invention includes: a substrate; a heat generating portion provided on the substrate; a cap substrate provided above the substrate so that a hollow portion is provided between the substrate and the cap substrate; and a reflection film provided above the heat generating portion and reflecting a medium wavelength infrared ray. The reflection film reflects the infrared ray radiated to the cap substrate side through the hollow portion due to the temperature increase of the heat generating portion, so that the temperature increase of the cap substrate side can be suppressed. Because of this function, even if mold resin is provided on the cap substrate, increase of the temperature of the mold resin can be suppressed.

ELECTRICALLY CONDUCTIVE PASTE FOR FORMING PILLARS

The known electrolytic plating method is disadvantageous in that it is difficult to form thin pillars without being influenced by undercuts. The electroless plating method is disadvantageous in that it is difficult to form pillars in the same shape without voids. As a solution to these, the electrically conductive paste according to the present invention for forming pillars is used to make pillars by filling. This helps prevent undercuts, and it is also intended to provide metal pillars in the same shape with good reproducibility. The inventors found that an electrically conductive paste that is very small fine metal particles and contains a particular percentage of fine metal particles is extraordinarily advantageous in forming pillars. 1. An electrically conductive paste for forming pillars , the paste comprising:fine metal particles: anda protective agent, whereina diameter of the fine metal particles is less than 1 μm, and a percentage of the fine metal particles in the electrically conductive paste is 40% or more and less than 95% concentration by mass.2. The electrically conductive paste according to for forming pillars claim 1 , the paste further comprising a solvent having a boiling point of 250° C. or less.3. The electrically conductive paste according to for forming pillars claim 1 , wherein the protective agent contains an organic compound including a C8 to C200 polyethylene oxide structure.4. The electrically conductive paste according to for forming pillars claim 3 , wherein a percentage of the organic compound including a C8 to C200 polyethylene oxide structure is 15% concentration by mass or less of the entire paste.5. The electrically conductive paste according to for forming pillars claim 1 , wherein the fine metal particle are particles of silver claim 1 , copper claim 1 , or a composite thereof.6. A pillar made using the electrically conductive paste according to for forming pillars. The present invention relates to an electrically conductive ...

Led package and manufacturing method

An LED package ( 40 ) and manufacturing method in which the package has LED substrate ( 50 ) and a circuit substrate ( 54 ) bonded together, with the LED over the integrated circuit, and with electrical connection between the LED and corresponding integrated circuit. The package has package terminals ( 56 a, 56 b ) on one face only with through vias ( 58 a, 58 b ) providing connection between the LED substrate and the circuit substrate.

Wafer level integration including design/co-design, structure process, equipment stress management and thermal management

A method of manufacturing a multi-layer wafer is provided. The method comprises applying at least one stress compensating polymer layer to at least one of two heterogeneous wafers and low temperature bonding the two heterogeneous wafers to bond the stress compensating polymer layer to the other of the two heterogeneous wafers to form a multi-layer wafer pair. The multi-layer wafer comprises two heterogeneous wafers, at least one of the heterogeneous wafers having a stress compensating polymer layer. The two heterogeneous wafers are low temperature bonded together to bond the stress compensating polymer layer to the other of the two heterogeneous wafers.

Electrode connection structure and electrode connection method

An electrode connection structure includes: a first electrode of an electrical circuit; and a second electrode of the electrical circuit that is electrically connected to the first electrode. The first and second electrodes are oppositely disposed in direct or indirect contact with each other. A plated lamination is substantially uniformly formed by plating process from a surface of a contact region and opposed surfaces of the first and second electrodes. A void near the surface of the contact region is filled by formation of the plated lamination. Portions of the plated lamination formed from the opposed surfaces of the first and second electrodes in a region other than the contact region are not joined together.

PACKAGED DIE AND RDL WITH BONDING STRUCTURES THEREBETWEEN

Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a redistribution layer coupled to the one or more dies at a first side of the first package with a first set of bonding joints. The redistribution layer including more than one metal layer disposed in more than one passivation layer, the first set of bonding joints being directly coupled to at least one of the one or more metal layers, and a first set of connectors coupled to a second side of the redistribution layer, the second side being opposite the first side. 1. A semiconductor package comprising:a die comprising a contact pad;a redistribution structure comprising a redistribution line and a passivation layer, a first portion of the redistribution line extending through the passivation layer; anda first bonding joint coupled to the first portion of the redistribution line and the contact pad, the first bonding joint being in physical contact with a first surface of the passivation layer, an entirety of the first bonding joint being interposed between the first surface of the passivation layer and the contact pad.2. The semiconductor package of claim 1 , further comprising a molding compound encapsulating the die claim 1 , wherein the redistribution structure extends across an interface between the die and the molding compound.3. The semiconductor package of claim 2 , further comprising a through via extending through the molding compound claim 2 , wherein a surface of the through via is level with a surface of the molding compound.4. The semiconductor package of claim 3 , further comprising a second bonding joint coupled to a second portion of the redistribution line and the through via claim 3 , the second portion of the redistribution line extending through the passivation layer claim 3 , the second bonding joint being in physical contact with a second surface ...

Solder paste, joining method using the same and joined structure

A solder paste including a metal component consisting of a first metal powder and a second metal powder having a melting point higher than that of the first metal, and a flux component. The first metal is Sn or an alloy containing Sn, the second metal is one of (1) a Cu—Mn alloy in which a ratio of Mn to the second metal is 5 to 30% by weight and (2) a Cu—Ni alloy in which a ratio of Ni to the second metal is 5 to 20% by weight, and a ratio of the second metal to the metal component is 36.9% by volume or greater.

Semiconductor device and method of fabricating the same

A semiconductor device includes a semiconductor substrate, a conductive pad disposed on the semiconductor substrate, and a pillar pattern disposed on the conductive pad. The semiconductor device further includes a solder seed pattern disposed on the pillar pattern, and a solder portion disposed on the pillar pattern and the solder seed pattern. A first width of the solder seed pattern is less than a second width of a top surface of the pillar pattern.

Microelectronic assemblies

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

DUAL SIDED FAN-OUT PACKAGE HAVING LOW WARPAGE ACROSS ALL TEMPERATURES

Semiconductor devices including a dual-sided redistribution structure and having low-warpage across all temperatures and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die electrically coupled to a first side of a redistribution structure and a second semiconductor die electrically coupled to a second side of the redistribution structure opposite the first side. The semiconductor device also includes a first molded material on the first side, a second molded material on the second side, and conductive columns electrically coupled to the first side and extending through the first molded material. The first and second molded materials can have the same volume and/or coefficients of thermal expansion to inhibit warpage of the semiconductor device. 1. A method of manufacturing a semiconductor device , the method comprising:forming a redistribution structure having a first surface and a second surface opposite the first surface;mounting a first semiconductor die to the first surface of the redistribution structure and electrically coupling the first semiconductor die to the redistribution structure;mounting a second semiconductor die to the second surface of the redistribution structure and electrically coupling the second semiconductor die to the redistribution structure; anddisposing a molded material on the first surface and the second surface of the redistribution structure and at least partially around the first semiconductor die and the second semiconductor die.2. The method of wherein forming the redistribution structure includes forming the redistribution structure without a pre-formed substrate.3. The method of wherein a ratio of the volume of the first semiconductor die to the volume of the molded material on the first surface is substantially equal to a ratio of the volume of the second semiconductor die to the volume of the molded material on the second surface.4. The method of ...

Trace Design for Bump-on-Trace (BOT) Assembly

A bump-on-trace (BOT) interconnection in a package and methods of making the BOT interconnection are provided. An embodiment BOT interconnection comprises a landing trace including a distal end, a conductive pillar extending at least to the distal end of the landing trace; and a solder feature electrically coupling the landing trace and the conductive pillar. In an embodiment, the conductive pillar overhangs the end surface of the landing trace. In another embodiment, the landing trace includes one or more recesses for trapping the solder feature after reflow. Therefore, a wetting area available to the solder feature is increased while permitting the bump pitch of the package to remain small. 1. A structure comprising:a substrate; anda landing trace on the substrate, the landing trace having a first side and a second side opposite to the first side, the landing trace having a plurality of indents extending into the first side in a plan view, the second side being free of indents in the plan view.2. The structure of claim 1 , further comprising a solder feature over the landing trace claim 1 , the solder feature extending into the plurality of indents.3. The structure of claim 2 , wherein solder feature is in physical contact with the plurality of indents.4. The structure of claim 2 , further comprising a conductive pillar over the solder feature claim 2 , the conductive pillar overlapping with the plurality of indents in the plan view.5. The structure of claim 4 , wherein a width of the solder feature is greater than a width of the conductive pillar.6. The structure of claim 4 , wherein a width of the landing trace is less than a width of the conductive pillar.7. The structure of claim 1 , wherein the plurality of indents have a comb pattern in the plan view.8. A structure comprising:a substrate; anda landing trace on the substrate, the landing trace having a first sidewall and a second sidewall opposite to the first sidewall, the first sidewall having a plurality ...

Electronic component built-in substrate and method for manufacturing the same

An electronic component built-in substrate includes an insulating substrate having a through hole and an inner wall surrounding the through hole, an electronic component accommodated in the through hole of the substrate, a sealing member filling the through hole such that the sealing member is covering the electronic component in the through hole of the substrate and exposing a terminal of the electronic component on a first side of the substrate, and a shield layer structure including a first metal film and a second metal film formed such that the first metal film is formed on the inner wall of the substrate and surrounding the through hole of the substrate and that the second metal film is formed on a second side of the substrate on the opposite side with respect to the first side and covering an opening of the through hole on the second side of the substrate.

FABRICATION METHOD OF SEMICONDUCTOR PACKAGE WITH STACKED SEMICONDUCTOR CHIPS

A semiconductor package includes a build-up structure; a semiconductor disposed on the build-up structure in a flip-chip manner and having a plurality of bumps penetrating therethrough; an electronic element disposed on the semiconductor chip; and an encapsulant formed on the build-up structure and encapsulating the semiconductor chip and the electronic element, thereby improving the product yield and the overall heat dissipating efficiency. 126-. (canceled)27. A fabrication method of a semiconductor package , comprising the steps of:providing a carrier having opposite first and second surfaces, wherein a build-up structure is formed on the first surface of the carrier and has a plurality of conductive pads exposed from the a top surface thereof;disposing a first semiconductor chip on the build-up structure in a flip-chip manner, wherein the first semiconductor chip has a first active surface and a first non-active surface opposite to the first active surface, and the first active surface has a plurality of first electrode pads electrically connected to the conductive pads, respectively;thinning the first semiconductor chip from the first non-active surface thereof;forming a plurality of first through holes in the first semiconductor chip via the first non-active surface thereof;forming in the first through holes a plurality of first bumps electrically connected to the first electrode pads;disposing an electronic element on the first semiconductor chip for electrically connecting the electronic element to the first bumps; andforming on the build-up structure an encapsulant that encapsulates the first semiconductor chip and the electronic element.28. The fabrication method of claim 27 , wherein the first electrode pads are exposed through the first through holes claim 27 , respectively.29. The fabrication method of claim 27 , wherein a circuit layer that is electrically connected to the first electrode pads is exposed through the first through holes.30. The ...

Die interconnect

One example embodiment discloses a chip having a chip area, wherein the chip area includes: an overhang area; a rigid coupling area, having a set of rigid coupling points, located on one side of the overhang area; and a flexible coupling area, having a set of flexible coupling points, located on a side of the overhang area opposite to the a rigid coupling area. Another example embodiment discloses a method for fabricating a die interconnect, comprising: fabricating a rigid coupler area, having a set of rigid coupler points, within a chip having a chip area; defining an overhang area within the chip area and abutted to the rigid coupler area; and fabricating a flexible coupler area, having a set of flexible coupler points, within the chip area abutted to a side of the overhang area opposite to the rigid coupler area.

Micro device transferring method, and micro device substrate manufactured by micro device transferring method

A method for transferring a micro device, includes: a compression step in which a carrier film having a micro-device attached to an adhesive layer thereof is brought into contact with a substrate comprising a solder deposited on metal electrodes formed on the substrate and is compressed on the substrate; a first adhesive strength generation step in which the solder disposed between the micro-device and the metal electrodes is compressed in the compression step to generate first adhesive strength between the micro-device and the solder; a second adhesive generation step in which the micro-device is bonded to the adhesive layer through press-fitting in the compression step to generate second adhesive strength between the micro-device and the adhesive layer; and a release step in which the carrier film is separated from the substrate, with the micro-device adhered to the solder.

Semiconductor device and a method of manufacturing thereof

A semiconductor device comprises a semiconductor die, comprising a stacking structure, a first bonding pad, and a second bonding pad on a top surface of the stacking structure, wherein a shortest distance between the first bonding pad and the second bonding pad is less than 150 μm; a carrier comprising a connecting surface; a third bonding pad and a fourth bonding pad on the connecting surface of the carrier; and a conductive connecting layer comprising a current conductive area between the first bonding pad and the third bonding pad and between the second bonding pad and the fourth bonding pad.

EXPANDED HEAD PILLAR FOR BUMP BONDS

A microelectronic device has a bump bond structure including an electrically conductive pillar with an expanded head, and solder on the expanded head. The electrically conductive pillar includes a column extending from an I/O pad to the expanded head. The expanded head extends laterally past the column on at least one side of the electrically conductive pillar. In one aspect, the expanded head may have a rounded side profile with a radius approximately equal to a thickness of the expanded head, and a flat top surface. In another aspect, the expanded head may extend past the column by different lateral distances in different lateral directions. In a further aspect, the expanded head may have two connection areas for making electrical connections to two separate nodes. Methods for forming the microelectronic device are disclosed. 1. A device comprising:an I/O pad of a substrate;a column on the I/O pad; anda head on the column and extending on all lateral sides of the column, a portion of a surface of the head, aligned with the column in a cross-sectional view of the device, is substantially parallel to a surface of the substrate.2. The device of claim 1 , wherein a plane along the portion of a surface of the head is parallel to a plane along a surface of the head adjacent to the column.3. The device of claim 1 , wherein the head has a rounded side profile with a radius that is approximately equal to the thickness of the head.4. The device of further comprising solder on the head.5. The device of further comprising a barrier layer between the surface of the head and the solder.6. The device of claim 5 , wherein the barrier layer impacts formation of intermetallic compounds between a material of the head and solder.7. The device of claim 1 , wherein the head extends past the column on all lateral sides of the column by a lateral distance that is approximately equal to a vertical thickness of the head.8. The device of further comprising a seed layer between the column ...

Methods for Making Multi-Die Package With Bridge Layer

A device is provided. The device includes a bridge layer over a first substrate. A first connector electrically connecting the bridge layer to the first substrate. A first die is coupled to the bridge layer and the first substrate, and a second die is coupled to the bridge layer. 1. A device , comprising:a first substrate comprising a plurality of first contacts extending along a first surface of the first substrate;a bridge overlying the first substrate, the bridge comprising a plurality of second contacts extending along a second surface of the bridge, second contacts of the plurality of second contacts being positioned along one or more edges of the second surface of the bridge, and the second surface of the bridge facing away from the first surface of the first substrate;a plurality of electrical connectors, wherein the plurality of electrical connectors electrically connect the plurality of second contacts to the plurality of first contacts, and each of the plurality of electrical connectors extends along a sidewall of the bridge;a first die overlying the bridge, wherein a perimeter of the first die is within a perimeter of the bridge in a plan view; anda second die overlying the bridge, wherein the second die partially overlaps the bridge and extends beyond the bridge in the plan view.2. The device according to claim 1 , wherein the first die comprises a plurality of blocks claim 1 , and each of the plurality of blocks comprises a respective plurality of third contacts.3. The device according to claim 2 , wherein the second die is connected to the respective plurality of third contacts of each of the plurality of blocks of the first die by a plurality of redistribution layers of the bridge.4. The device according to claim 1 , wherein each of the plurality of electrical connectors is a conductive bump that contacts the sidewall of the bridge.5. The device according to claim 4 , wherein a height of the plurality of electrical connectors over the first substrate ...

Die Stack Assembly Using An Edge Separation Structure For Connectivity Through A Die Of The Stack

A die stack assembly includes first and second power semiconductor device dice. The first die has a P type peripheral edge separation structure that extends from the top planar semiconductor surface of the first die all the way to the bottom planar semiconductor surface of the die, and that is doped at least in part with aluminum. The backside of the first die is mounted to the backside of the second die. A metal feature that is not covered with passivation, and that can serve as a bonding pad, is disposed on part of the peripheral edge separation structure. A metal member (for example, a bond wire or metal clip) contacts the metal feature such that an electrical connection is established from the metal member, through the metal feature, through the peripheral edge separation structure of the first die, and to an electrode of the second die. 1. An assembly comprising: wherein a peripheral edge separation structure extends from the first substantially planar semiconductor surface to the second substantially planar semiconductor surface along a side edge of the first power semiconductor device die,', 'wherein the peripheral edge separation structure comprises an amount of P type semiconductor material disposed in a trench, and a P type semiconductor region that is doped at least in part with aluminum, and', 'wherein a metal feature covers and makes electrical contact with the peripheral edge separation structure at the first substantially planar semiconductor surface of the first power semiconductor device die; and, 'a first power semiconductor device die having a first substantially planar semiconductor surface and a second substantially planar semiconductor surface,'}a second power semiconductor device die having a first substantially planar semiconductor surface and a second substantially planar semiconductor surface,wherein a peripheral edge separation diffusion region extends from the first substantially planar semiconductor surface to the second substantially ...

Metal particle, paste, formed article, and laminated article

Aiming at providing a metal particle, an electro-conductive paste, a formed article, and a laminated article that are able to form a highly reliable and high-quality electric interconnect, an electro-conductive bonding portion, or a three-dimensional structure that is less likely to produce the Kirkendall void, this invention discloses a metal particle which include an outer shell and a core part, the outer shell including an intermetallic compound and covering the core part.

Method for bonding bare chip dies

A method is provided for assembly of a micro-electronic component comprising the steps of: providing a conductive die bonding material comprising of a conductive thermosettable resin material or flux based solder and a dynamic release layer adjacent to the conductive thermoplastic material die bonding material layer; and impinging a laser beam on the dynamic release layer adjacent to the die bonding material layer; in such a way that the dynamic release layer is activated to direct conductive die bonding material matter towards the pad structure to be treated to cover a selected part of the pad structure with a transferred conductive die bonding material; and wherein the laser beam is restricted in timing and energy, in such a way that the die bonding material matter remains thermosetting. Accordingly adhesive matter can be transferred while preventing that the adhesive is rendered ineffective by thermal overexposure in the transferring process.

METAL PARTICLE AND ARTICLES FORMED THEREFROM

A formed article includes a metal particle which has a particle size in a range from 1 μm to 20 μm and consists of an outer shell and a core part. The core part contains Sn or a Sn alloy. The outer shell contains an intermetallic compound of Sn and Cu and covers 50% or more of a total surface area of the core part. 1. A formed article containing a metal particle , wherein:the metal particle consists of a core part and an outer shell, the core part containing a metal or an alloy, the outer shell comprising an intermetallic compound and covering the core part;50% or more of a total surface area of the core part is covered with the outer shell;a particle size of the metal particle being from 1 μm to 20 μm;the core part containing Sn or a Sn alloy; andthe outer shell containing an intermetallic compound of Sn and Cu.2. A laminated article having a laminated structure of a first layer and a second layer , the first layer containing a metal particle , and the second layer configuring a heat conductive layer or an electro-conductive layer , wherein:the metal particle consists of a core part and an outer shell, the core part containing a metal or an alloy, the outer shell comprising an intermetallic compound and covering the core part;wherein 50% or more of a total surface area of the core part is covered with the outer shell;a particle size of the metal particle being from 1 μm to 20 μm;the core part containing Sn or a Sn alloy; andthe outer shell containing an intermetallic compound of Sn and Cu. This application is a divisional application of co-pending U.S. patent application Ser. No. 15/334,898, filed Oct. 26, 2016, which is based on the Japanese Patent Application No. 2016-065287, filed on Mar. 29, 2016. The entire content of each of the related applications is incorporated herein by reference.This invention relates to a metal particle, a paste, a formed article, and a laminated article.First, the terms used in this specification will be defined as follows:(1) the ...

Illumination device

An illumination device includes a supporting base, and a light-emitting element inserted in the supporting base. The light-emitting element includes a substrate having a supporting surface and a side surface, a light-emitting chip disposed on the supporting surface, and a first wavelength conversion layer covering the light-emitting chip and only a portion of the supporting surface without covering the side surface.

Semiconductor chip assembly and method for making same

A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. The vias, compliant layer and substrate contacts are adapted to appreciably relieve stress at the substrate contacts associated with differential thermal contact and expansion of the assembly. 1. A microelectronic assembly comprising: ["a dielectric element having first and second opposed surfaces, a first dielectric layer having a first material structure adjacent the first surface, and a second dielectric layer having a second material structure different from the first material structure, the second dielectric layer disposed between the first dielectric layer and the second surface, the first dielectric layer having a Your modulus less than two gigapascal (GPa), wherein a Young's modulus of the second dielectric layer is at least 50% greater than the Young's modulus of the first dielectric layer;", 'a plurality of substrate contacts at the first surface;', 'a plurality of terminals at the second surface; and', 'a conductive structure extending through the first and second dielectric layers and electrically connecting the substrate contacts with the terminals;, 'a substrate including'}a microelectronic element having a face confronting the first surface and a plurality of element contacts thereon joined with the substrate contacts through conductive masses; anda rigid underfill between the face of the microelectronic element and the first surface,wherein the terminals are usable for bonding the microelectronic assembly to corresponding contacts of a component ...

Illumination device

An illumination device includes a supporting base, and a light-emitting element inserted in the supporting base. The light-emitting element includes a substrate having a supporting surface and a side surface, a light-emitting chip disposed on the supporting surface, and a first wavelength conversion layer covering the light-emitting chip and only a portion of the supporting surface without covering the side surface.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide a method for manufacturing a semiconductor device, and a semiconductor device produced thereby, that comprises an interposer without through silicon vias. 120-. (canceled)21. A method of manufacturing a semiconductor package , the method comprising: a carrier; and', 'an S1 dielectric layer directly on the carrier,', 'wherein the first structure comprises a first S1 side facing away from the carrier, a second S1 side opposite the first S1 side and at least one lateral S1 side that extends between the first S1 side and the second S1 side;, 'providing a first structure (S1) comprising an SDS dielectric layer; and', 'an SDS conductive layer that laterally routes electrical signals;, 'forming a signal distribution structure (SDS) on a first side of the first structure, the signal distribution structure comprisingafter said forming a signal distribution interposer structure, removing the carrier; andattaching a semiconductor die to a side of the signal distribution structure from which the carrier was removed.22. The method of claim 21 , wherein said attaching the semiconductor die to the side of the signal distribution structure comprises claim 21 , after said removing the carrier claim 21 , attaching the semiconductor die directly to the side of the signal distribution structure.23. The method of claim 21 , wherein said forming the signal distribution structure comprises sequentially forming the SDS conductive layer and the SDS dielectric layer after said providing the first structure.24. The method of claim 21 , wherein the first S1 dielectric layer of the provided first structure has no apertures.251. The method of claim claim 21 , wherein the signal distribution structure is TSV-less.261. The method of claim claim 21 , wherein the carrier comprises glass.27. A method of manufacturing a ...

Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths

Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

Light emitting diode display device

A light emitting diode display device includes a display board comprising a plurality of unit pixels, a drive circuit board including a plurality of drive circuit regions corresponding to the plurality of unit pixels, and a plurality of bumps interposed between the plurality of unit pixels and the plurality of drive circuit regions. The plurality of unit pixels comprises a first unit pixel including a first P electrode. The plurality of drive circuit regions comprises a first drive circuit region corresponding to the first unit pixel and a first pad connected to a first drive transistor, the plurality of bumps includes a first solder in contact with the first pad, and a first bump on the first solder and including a first filler in contact with the first P electrode, the first solder includes at least one of tin and silver, and the first filler includes copper or nickel.

METAL PARTICLE AND ELECTROCONDUCTIVE PASTE FORMED THEREFROM

An electro-conductive paste includes a metal particle and a vehicle in which the metal particle is dispersed. The metal particle has a particle size in a range from 1 μm to 20 μm and consists of an outer shell and a core part. The core part contains Sn or a Sn alloy. The outer shell contains an intermetallic compound of Sn and Cu and covers 50% or more of a total surface area of the core part. 1the metal particle consists of a core part and an outer shell, the core part containing a metal or an alloy, the outer shell containing an intermetallic compound and covering the core part;50% or more of a total surface area of the core part is covered with the outer shell;a particle size of the metal particle is from 1 μm to 20 μm;the core part containing Sn or a Sn alloy;the outer shell containing an intermetallic compound of Sn and Cu; andthe metal particle is dispersed in the vehicle.. An electro-conductive paste comprising a metal particle and a vehicle, wherein: This application is a divisional application of co-pending U.S. patent application Ser. No. 15/334,898, filed Oct. 26, 2016, which is based on the Japanese Patent Application No. 2016-065287, filed on Mar. 29, 2016. The entire content of each of the related applications is incorporated herein by reference.This invention relates to a metal particle, a paste, a formed article, and a laminated article.First, the terms used in this specification will be defined as follows:(1) the term “metal”, “metal particle” or “metal component” is used for indicating not only a simple metal element, but also an alloy composed of two or more metal elements, a composite structure, or, a combination of them;(2) “nanometer” denotes a range of dimension below 1 μm (1000 nm); and(3) “metal matrix” denotes a metal or alloy that serves as a base material for filling up the gaps around, and supporting, other ingredients.In devices such as those kept operated at high temperatures for a long duration of time, and operated under harsh ...

Wafer Level Dicing Method and Semiconductor Device

A semiconductor device includes a plurality of connectors and at least one insulating layer disposed over a semiconductor substrate. A molding layer extends around the plurality of connectors. A sidewall of the molding layer that is closest to a scribe line is offset from the scribe line.

Semiconductor structure and manufacturing method thereof

The present disclosure provides a semiconductor structure, including a substrate, a conductive pad, a passivation layer, a recess, a bump pad, and a conductive bump. The conductive pad is disposed over the substrate. The passivation layer is disposed over the substrate and partially covers the conductive pad. The recess extends through the passivation layer and extends at least partially into the conductive pad. The bump pad is disposed over the passivation layer and within the recess; and the conductive bump is disposed over the bump pad. A method of manufacturing the semiconductor structure is also provided.

Dual sided fan-out package having low warpage across all temperatures

Semiconductor devices including a dual-sided redistribution structure and having low-warpage across all temperatures and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die electrically coupled to a first side of a redistribution structure and a second semiconductor die electrically coupled to a second side of the redistribution structure opposite the first side. The semiconductor device also includes a first molded material on the first side, a second molded material on the second side, and conductive columns electrically coupled to the first side and extending through the first molded material. The first and second molded materials can have the same volume and/or coefficients of thermal expansion to inhibit warpage of the semiconductor device.

DEVICES AND METHODS RELATED TO RADIO-FREQUENCY FILTERS ON SILICON-ON-INSULATOR SUBSTRATE

Devices and methods related to radio-frequency (RF) filters on silicon-on-insulator (SOI) substrate. In some embodiments, an RF device can include a silicon die such as an SOI die including a first side and a second side. The silicon die can further include a plurality of vias, with each via configured to provide an electrical connection between the first side and the second side of the silicon die. The RF device can further include at least one RF flip chip mounted on the first side of the silicon die. The silicon die can include, for example, an RF circuit such as a switch circuit, and the RF flip chip can include, for example, a filter such as a surface acoustic wave (SAW) filter. 1a silicon die including a radio-frequency circuit, a first side and a second side, and a plurality of vias, each via configured to provide an electrical connection between the first side and the second side of the silicon die; andat least one radio-frequency flip chip mounted on the first side of the silicon die, the radio-frequency flip chip in communication with the radio-frequency circuit.. A radio-frequency device comprising: This application is a continuation of U.S. patent application Ser. No. 15/192,812, filed Jun. 24, 2016, entitled “DEVICES AND METHODS RELATED TO RADIO-FREQUENCY FILTERS ON SILICON-ON-INSULATOR SUBSTRATE,” which claims priority to U.S. Provisional Application No. 62/187,174, filed Jun. 30, 2015, entitled “DEVICES AND METHODS RELATED TO RADIO-FREQUENCY FILTERS ON SILICON-ON-INSULATOR SUBSTRATE,” the disclosure of each of which is hereby expressly incorporated by reference herein in its entirety.The present disclosure relates to, among others, radio-frequency (RF) filters on silicon-on-insulator (SOI) substrate.In some radio-frequency (RF) applications, a signal received or transmitted through an antenna can be routed to different amplification paths through band selection switches and respective filters. In such applications, it is desirable to minimize or ...

FULLY MOLDED PERIPHERAL PACKAGE ON PACKAGE DEVICE

A method of making a semiconductor device may include providing a carrier comprising a semiconductor die mounting site. A build-up interconnect structure may be formed over the carrier. A first portion of a conductive interconnect may be formed over the build-up interconnect structure in a periphery of the semiconductor die mounting site. An etch stop layer and a second portion of the conductive interconnect may be formed over the first portion of the conductive interconnect. A semiconductor die may be mounted to the build-up interconnect at the semiconductor die mounting site. The conductive interconnect and the semiconductor die may be encapsulated with a mold compound. A first end of the conductive interconnect on the second portion of the conductive interconnect may be exposed. The carrier may be removed to expose the build-up interconnect structure. The first portion of the conductive interconnect may be etched to expose the etch stop layer. 1. A method of making a semiconductor device , comprising:providing a carrier comprising a semiconductor die mounting site;forming a build-up interconnect structure over the carrier;forming a first portion of a conductive interconnect over the build-up interconnect structure in a periphery of the semiconductor die mounting site;forming an etch stop layer over the first portion of the conductive interconnect;forming a second portion of the conductive interconnect over the etch stop layer and over the first portion of the conductive interconnect;mounting a facedown semiconductor die to the build-up interconnect at the semiconductor die mounting site;encapsulating the conductive interconnect and semiconductor die with a mold compound;exposing a first end of the conductive interconnect on the second portion of the conductive interconnect;removing the carrier to expose the build-up interconnect structure; andetching the first portion of the conductive interconnect to expose the etch stop layer.2. The method of claim 1 , wherein ...

Display device

A display device includes: a display panel; a driver integrated circuit (IC) including a first surface electrically connected to the display panel and a second surface opposing the first surface and electrically connected to the first surface; and a connecting structure including a first side portion electrically connected to the second surface of the driver IC, and a second side portion electrically connected to an external device.

Conductive particle, and connection material, connection structure, and connecting method of circuit member

There is provided a conductive particle including a core particle containing a resin material, and a surface layer that covers a surface of the core particle and contains a solder material, in which a melting point of the solder material is equal to or lower than a softening point of the resin material.

Reversed build-up substrate for 2.5d

A method of making an assembly can include forming a circuit structure defining front and rear surfaces, and forming a substrate onto the rear surface. The forming of the circuit structure can include forming a first dielectric layer coupled to the carrier. The first dielectric layer can include front contacts configured for joining with contacts of one or more microelectronic elements, and first traces. The forming of the circuit structure can include forming rear conductive elements at the rear surface coupled with the front contacts through the first traces. The forming of the substrate can include forming a dielectric element directly on the rear surface. The dielectric element can have first conductive elements facing the rear conductive elements and joined thereto. The dielectric element can include second traces coupled with the first conductive elements. The forming of the substrate can include forming terminals at a surface of the substrate.

Semiconductor device and method for manufacturing the same

A semiconductor device includes a first electronic component, a second electronic component and a plurality of interconnection structures. The first electronic component has a first surface. The second electronic component is over the first electronic component, and the second electronic component has a second surface facing the first surface of the first electronic component. The interconnection structures are between and electrically connected to the first electronic component and the second electronic component, wherein each of the interconnection structures has a length along a first direction substantially parallel to the first surface and the second surface, a width along a second direction substantially parallel to the first surface and the second surface and substantially perpendicular to the first direction, and the length is larger than the width of at least one of the interconnection structures.

Assembly comprising hybrid interconnecting means including intermediate interconnecting elements and sintered metal joints, and manufacturing process

An assembly includes at least one first element comprising at least one first electrical bonding pad; at least one second element comprising at least one second electrical bonding pad; electrical and mechanical interconnect means, wherein the electrical and mechanical interconnect means comprise at least: at least one first intermediate metal interconnect element, on the surface of at least the first electrical bonding pad; at least one sintered joint of metal microparticles or nanoparticles stacked with the first intermediate metal interconnect element; the melting point of the first intermediate metal interconnect element being greater than the sintering temperature of the metal microparticles or nanoparticles. A method for fabricating an assembly is also provided.

Semiconductor Packages and Methods of Forming the Same

Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a redistribution layer coupled to the one or more dies at a first side of the first package with a first set of bonding joints. The redistribution layer including more than one metal layer disposed in more than one passivation layer, the first set of bonding joints being directly coupled to at least one of the one or more metal layers, and a first set of connectors coupled to a second side of the redistribution layer, the second side being opposite the first side. 1. A semiconductor package comprising:a die having a contact pad on a first surface;molding compound along sidewalls of the die;a first bonding structure on the contact pad, the first bonding structure extending away from the first surface;a redistribution structure, the redistribution structure comprising a first conductive line and a passivation layer covering a first portion of the first conductive line; anda second bonding structure coupled to a second portion of the first conductive line and the first bonding structure, wherein the passivation layer is interposed between the first conductive line and the die, a sidewall of the passivation layer being spaced apart from the second bonding structure.2. The semiconductor package of claim 1 , further comprising another second bonding structure claim 1 , wherein the passivation layer is interposed between the second bonding structure and the another second bonding structure.3. The semiconductor package of claim 1 , wherein the second bonding structure extends further from the first conductive line than the passivation layer.4. The semiconductor package of claim 1 , further comprising a solder material bonding the first bonding structure to the second bonding structure.5. The semiconductor package of claim 1 , wherein contact pad comprises a through via ...

Semiconductor structure and manufacturing method thereof

A semiconductor structure and manufacturing method thereof are provided. The semiconductor structure includes a metallization structure with a dielectric surface. A first protecting structure is on the dielectric surface. A conductive pad is on the dielectric surface and is leveled with the first protecting structure. A polymer layer is over the first protecting structure and the conductive pad. A conductive bump is electrically coupled to the conductive pad through an opening of the polymer layer. A method for manufacturing a semiconductor structure is also provided.

Quantum dot led package and quantum dot led module including the same

A quantum dot LED package is disclosed. The quantum dot LED package includes: a heat dissipating reflector having a through cavity; a quantum dot plate accommodated in the upper portion of the through cavity; an LED chip accommodated in the lower portion of the through cavity and whose top surface is coupled to the lower surface of the quantum dot plate; electrode pads disposed on the lower surface of the LED chip and protruding more downward than the lower surface of the heat dissipating reflector; and a resin part formed in the through cavity to fix between the LED chip and the reflector and between the quantum dot plate and the reflector.

Method of manufacturing semiconductor package structure

A semiconductor package structure includes a redistribution (RDL) layer, a first chip, at least one second chip, an encapsulant and a third chip. The redistribution layer has a first surface and a second surface opposite to each other. The first chip is over the first surface of the redistribution layer and electrically connected to the redistribution layer. The second chip is over the first surface of the redistribution layer. The second chip includes a plurality of through via structures. The encapsulant is over the first surface of the distribution layer, wherein the encapsulant surrounds the first chip and the second chip. The third chip is over the encapsulant and electrically connected to the first chip through the through via structures of the second chip and the redistribution layer.

Electrode connection method and electrode connection structure

Provided is an electrode connection method and the like which make it possible to connect tightly without leaving a gap, by connecting by plating while electrodes in an electrical circuit contact one another in a dot or linear pattern. Contact is made directly or indirectly in at least part of the interval between a plurality of electrically connected electrodes in an electrical circuit, and the interval between electrodes is plated and connected while a plating fluid flows around the periphery of the contact section. In addition, the contact section maintains a linear or dot pattern. Furthermore, nickel or a nickel alloy or copper or a copper alloy is used as the material for performing the plating, while the material for the surface of the electrodes to be connected is nickel or a nickel alloy, copper or a copper alloy, gold or a gold alloy, silver or a silver alloy, or palladium or a palladium alloy.

SEMICONDUCTOR DEVICE WITH A SEMICONDUCTOR DIE EMBEDDED BETWEEN AN EXTENDED SUBSTRATE AND A BOTTOM SUBSTRATE

A method of manufacturing a semiconductor device having a semiconductor die within an extended substrate and a bottom substrate may include bonding a bottom surface of a semiconductor die to a top surface of a bottom substrate, forming an adhering member to a top surface of the semiconductor die, bonding an extended substrate to the semiconductor die and to the top surface of the bottom substrate utilizing the adhering member and a conductive bump on a bottom surface of the extended substrate and a conductive bump on the bottom substrate. The semiconductor die and the conductive bumps may be encapsulated utilizing a mold member. The conductive bump on the bottom surface of the extended substrate may be electrically connected to a terminal on the top surface of the extended substrate. The adhering member may include a laminate film, a non-conductive film adhesive, or a thermal hardening liquid adhesive. 120-. (canceled)21. A semiconductor device comprising:a first substrate comprising a top surface and a bottom surface;a semiconductor die comprising a top surface and a bottom surface, wherein the bottom surface of the semiconductor die is bonded to the top surface of the first substrate;a second substrate comprising a top surface and a bottom surface;an adhering member between the bottom surface of the second substrate and the top surface of the semiconductor die;a solder-coated copper ball coupling the bottom surface of the second substrate to the top surface of the first substrate; anda mold member that encapsulates the semiconductor die and the solder-coated copper ball.22. The semiconductor device according to claim 21 , wherein the solder-coated copper ball is directly coupled to a first connecting pad on the first substrate and to a second connecting pad on the second substrate.23. The semiconductor device according to claim 21 , comprising a terminal on the top surface of the second substrate.24. The semiconductor device according to claim 23 , wherein the ...

Embedded package and method for forming the same

임베디드 패키지 및 그 형성방법이 개시되어 있다. 개시된 임베디드 패키지는, 반도체 칩 몸체 및 상기 반도체 칩 몸체의 일면 상에 장착되고 상기 반도체 칩 몸체의 측면으로 노출되는 범프를 각각 포함하며 상기 각각의 범프들이 상호 연결되도록 적층되는 제1,제2반도체 칩과, 상기 적층된 제1,제2반도체 칩을 감싸는 코어층, 상기 코어층 내부에 배치되며 상기 제1,제2반도체 칩의 범프들에 전기적으로 연결되는 제1회로 패턴, 상기 제1반도체 칩과 인접한 상기 코어층의 제1면에 배치되는 제2회로 패턴, 상기 코어층의 제1면과 대향하는 제2면에 배치되는 제3회로 패턴, 상기 코어층 내부에 형성되며 상기 제1회로 패턴과 제2회로 패턴을 전기적으로 연결하는 제1 비아 및 상기 제1회로 패턴과 제3회로 패턴을 전기적으로 연결하는 제2비아를 포함하는 기판을 포함하는 것을 특징으로 한다. An embedded package and a method of forming the same are disclosed. The disclosed embedded package includes first and second semiconductor chips each including a semiconductor chip body and bumps mounted on one surface of the semiconductor chip body and exposed to side surfaces of the semiconductor chip body, wherein the respective bumps are stacked to be interconnected. And a core layer surrounding the stacked first and second semiconductor chips, a first circuit pattern disposed in the core layer and electrically connected to bumps of the first and second semiconductor chips, and the first semiconductor chip. A second circuit pattern disposed on a first surface of the core layer adjacent to the third circuit pattern, a third circuit pattern disposed on a second surface of the core layer opposite to the first surface of the core layer, and formed inside the core layer; And a substrate including a first via electrically connecting the second circuit pattern to the second circuit pattern, and a second via electrically connecting the first circuit pattern to the third circuit pattern.

半导体封装及其制造方法

本发明公开了一种半导体封装，其中，半导体芯片和安装器件一起封装在半导体封装中。半导体封装包括半导体芯片、安装块和互连部件，在安装块上的第一安装器件安装在基板上，基板包括形成在其上的电路，互连部件被配置以将半导体芯片电连接至安装块。

接合装置

本发明包括：加热器(11)；以及接合工具(20)，具有对存储器芯片(60)进行吸附的下表面(24)及安装于加热器(11)的上表面(22)，下表面(24)的第1周缘区域(A)将存储器芯片(60)的周缘部(60a)按压至焊料球(41)，第1中央区域(B)将存储器芯片(60)的中央部(60b)按压至耐热温度低于焊料球(41)的DAF(44)，并且，从第1中央区域(B)传递至存储器芯片(60)的中央部(60b)的热量小于从第1周缘区域(A)传递至存储器芯片(60)的周缘部(60a)的热量。由此，可提供一种能够将接合构件的中央部加热为低于周缘部的温度的接合装置。

Electronic component mounting structure and manufacturing method thereof

Semiconductor device and method of forming fine pitch rdl over semiconductor die in fan-out package

本发明涉及在半导体管芯上形成细节距的RDL的半导体器件和方法。半导体器件具有包括多个导电迹线的第一导电层。第一导电层形成在衬底上。利用窄节距形成导电迹线。在第一导电层上放置第一半导体管芯和第二半导体管芯。在第一和第二半导体管芯上沉积第一密封剂。移除衬底。在第一密封剂上沉积第二密封剂。在第一导电层和第二密封剂上形成堆积互连结构。堆积互连结构包括第二导电层。在第一密封剂中放置第一无源器件。在第二密封剂中放置第二无源器件。在第二密封剂中放置垂直互连单元。第三导电层形成在第二密封剂上并且经由垂直互连单元电气连接到堆积互连结构。