BONDED SEMICONDUCTOR PACKAGE AND RELATED METHODS

Implementations of a semiconductor package may include: a first wafer having a first surface and a first set of blade interconnects, the first set of blade interconnects extending from the first surface. The package may include a second wafer having a first surface and a second set of blade interconnects, the second set of blade interconnects extending from the first surface and oriented substantially perpendicularly to a direction of orientation of the first set of blade interconnects. The first set of blade interconnects may be hybrid bonded to the second set of blade interconnects at a plurality of points of intersection between the first and second set of blade interconnects. The plurality of points of intersection may be located along a length of each blade interconnect of the first set of blade interconnects, and along the length of each blade interconnect of the second set of blade interconnects. 1. A method of forming a blade interconnect , comprising:forming an undercut pattern in a layer on a first surface of a first wafer, where the undercut pattern, when viewed from above the first surface, comprises one of two opposing triangles in the layer or an hourglass shape in the layer;electroplating a metal into the undercut pattern to form a blade interconnect; andforming a chamfer in the blade interconnect during electroplating using the one of two opposing triangles or the hourglass shape of the undercut pattern.2. The method of claim 1 , further comprising where the two opposing triangles comprise rounded vertices or the hourglass shape comprises rounded edges.3. The method of claim 1 , further comprising:depositing a metal seed layer between the first surface of the first wafer and the layer; andetching the metal seed layer after electroplating the metal into the undercut pattern.4. The method of claim 1 , further comprising depositing an underfill material around the blade interconnect.5. The method of claim 1 , further comprising depositing a solder layer ...

Substrate for pre-soldering material and fabrication method thereof

A substrate for a pre-soldering material and a fabrication method of the substrate are proposed. The substrate having at least one surface formed with a plurality of conductive pads is provided. An insulating layer is formed over the surface of the substrate in such a way that a top surface of each of the conductive pads is exposed. Next, a conductive film and a resist layer are formed in sequence on the insulating layer and the conductive pads, wherein a plurality of openings are formed in the resist layer to expose a part of the conductive film above the conductive pad. Then, a pre-soldering material is deposited over the conductive pad by stencil printing or electroplating process.

A method of coupling singulated chip to a substrate package, fluxless flip chip interconnection and a method of forming contact points on chip

칩과 기판을 결합하는 플립 칩 방법이 개시된다. 열압착 본더가 이용되어 칩과 기판을 정렬하고 기판의 땜납 범프가 칩의 금속 범프를 마주한 채 유지되도록 접촉력을 인가한다. 칩은, 땜납 범프의 재용융 온도에 도달하기까지 본더의 헤드에 있는 펄스 히터에 의하여 그 가공 측면(non-native side)으로부터 급속하게 가열된다. 땜납 범프에서 재용융 온도에 이르면 곧, 접촉력이 해제된다. 기판의 금속 돌출부가 적셔지고 결합이 이루어지도록 땜납이 수초 동안 재용융 온도이상으로 유지된다. 재용융 이전 및 재용융 동안 고온에서 금속 범프(일반적으로 구리와 같이 고전도성 및 고반응성을 갖는 금속으로 구성됨)가 산화되지 않도록 팔라듐 같은 귀금속으로 구성된 금속이 금속 범프의 표면에 인가된다. Disclosed is a flip chip method for joining a chip and a substrate. A thermocompression bonder is used to align the chip with the substrate and apply contact force such that the solder bumps of the substrate remain facing the metal bumps of the chip. The chip is rapidly heated from its non-native side by a pulse heater at the head of the bonder until the remelting temperature of the solder bumps is reached. As soon as the remelt temperature is reached in the solder bumps, the contact force is released. The solder is kept above the remelting temperature for a few seconds to wet the metal protrusions of the substrate and bond them. Metals composed of noble metals such as palladium are applied to the surface of the metal bumps such that metal bumps (usually composed of metals with high conductivity and high reactivity, such as copper) do not oxidize at high temperatures before and during remelting. 반도체 칩 패키징, 플립 칩 프로세스 Semiconductor Chip Packaging, Flip Chip Process

Semiconductor light emitting diode and semiconductor light emitting diode package using the same

본 발명은 제1 및 제2 전극이 배치된 제1 면과 상기 제1 면의 반대에 위치한 제2면을 갖는 발광다이오드 칩; 상기 제1 및 제2 전극의 본딩 영역들이 노출되도록 상기 발광다이오드 칩의 표면에 배치된 패시베이션층; 상기 본딩 영역들에 각각 배치되며 각각 분리된 복수의 영역을 갖는 복수의 솔더 패드; 상기 본딩 영역들에 각각 배치되며, 각각 상기 솔더 패드의 상기 분리된 복수의 영역을 덮는 복수의 솔더 범프;를 포함하여, 솔더 패드와 솔더 범프 사이의 계면이 손상되어 분리되는 것을 효과적으로 차단할 수 있다. The present invention includes a light emitting diode chip having a first surface on which first and second electrodes are disposed and a second surface opposite to the first surface; A passivation layer disposed on the surface of the LED chip to expose bonding regions of the first and second electrodes; A plurality of solder pads disposed on the bonding areas and each having a plurality of separated areas; Including a plurality of solder bumps disposed on the bonding regions, each covering the separated plurality of regions of the solder pad, it is possible to effectively block separation due to damage to the interface between the solder pad and the solder bump.

3d integrated circuit (3dic) structure and method of making same

하나의 실시예의 접합형 집적 회로(IC) 구조체는 제1 IC 구조체 및 이 제1 IC 구조체에 접합된 제2 IC 구조체를 포함한다. 제1 IC 구조체는 제1 본딩층 및 커넥터를 포함한다. 제2 IC 구조체는 제1 본딩층에 접합되어 접촉하는 제2 본딩층, 및 이 제2 본딩층 내의 접점 패드를 포함한다. 커넥터는 제1 본딩층과 제2 본딩층 간의 계면을 지나 연장하고, 접점 패드는 커넥터의 레터럴 표면 및 측벽과 접촉한다. A junction type integrated circuit (IC) structure of one embodiment includes a first IC structure and a second IC structure bonded to the first IC structure. The first IC structure includes a first bonding layer and a connector. The second IC structure includes a second bonding layer which is in contact with and bonded to the first bonding layer, and a contact pad in the second bonding layer. The connector extends beyond the interface between the first bonding layer and the second bonding layer and the contact pads contact the lateral surfaces and sidewalls of the connector.

Bump-on-lead flip chip interconnection

Microelectronic package containing silicon patches for high density interconnects, and methods of making same

Mikroelektronischer Baustein (100), umfassend: ein Substrat (110); einen ersten Chip (161) und einen zweiten Chip (162) über dem Substrat (110); einen Siliziumpatch (120), der in das Substrat (110) eingebettet ist; mehrere erste Zwischenverbindungsstrukturen (131) an dem Siliziumpatch (120) unter dem ersten Chip (161) und mehrere zweite Zwischenverbindungsstrukturen (132) an dem Siliziumpatch (120) unter dem zweiten Chip (162); und eine elektrische Leitung (150) in dem Siliziumpatch (120), die eine erste der mehreren ersten Zwischenverbindungsstrukturen (131) und eine erste der mehreren zweiten Zwischenverbindungsstrukturen (132) miteinander verbindet. A microelectronic device (100) comprising: a substrate (110); a first chip (161) and a second chip (162) over the substrate (110); a silicon patch (120) embedded in the substrate (110); a plurality of first interconnect structures (131) on the silicon patch (120) under the first chip (161) and a plurality of second interconnect structures (132) on the silicon patch (120) under the second chip (162); and an electrical lead (150) in the silicon patch (120) interconnecting a first of the plurality of first interconnect structures (131) and a first of the plurality of second interconnect structures (132).

Fluxless flip chip interconnection

A flip chip method of joining a chip and a substrate is described. A thermocompression bonder is utilized to align the chip and substrate and apply a contact force to hold solder bumps (305) on the substrate against metal bumps (320) on the chip. The chip is rapidly heated from its non-native side by a pulse heater (415) in the head (410) of the bonder until the re-flow temperature of the solder bumps (305) is reached. Proximate with reaching the re-flow temperature at the solder bumps (305), the contact force is released. The solder is held above its re-flow temperature for several seconds to facilitate wetting of the substrate's metal protrusions (320) and joining. Metal caps (330) comprised of a noble metal such as palladium is applied to the surface of the metal bumps (320) to prevent the metal bumps (320) (which generally comprise a highly-conductive and highly-reactive metal such as copper) from oxidizing in the elevated temperatures just prior to and during the re-flow operation.

Bump-on-lead flip chip interconnection

A flip chip interconnect is made by mating the interconnect bump directly onto a lead, rather than onto a capture pad. Also, a flip chip package includes a die having solder bumps attached to interconnect pads in an active surface, and a substrate having electrically conductive traces in a die attach surface, in which the bumps are mated directly onto the traces. In some embodiments the interconnection is formed without employing a solder mask. In some methods a curable adhesive is dispensed either onto the bumps on the die or onto the traces on the substrate; the adhesive is partly cured during the mating process, and the partly cured adhesive serves to confine the molten solder during a reflow process.

Semi-buried electrical connection insert rod device

Titre : Système doté d’un dispositif à tige d’insert de connexion électrique semi-enterrée L’invention concerne un système doté d’un dispositif microélectronique comprenant un substrat (100) exposé sur une face du dispositif, le substrat (100) comprenant au moins un élément (105) électriquement conducteur, et un organe de raccordement électrique (130) en continuité électrique avec l’élément (105) et comprenant au moins une tige (116) faisant saillie sur la face du dispositif, caractérisé en ce que l’organe de raccordement (130) comprend une portion d’ancrage (131) inorganique recouvrant l’élément (105) et en ce que la tige (116) comprend une portion enterrée (1161) dans la portion d'ancrage (131) suivie d’une portion saillante (1162) sur la face du dispositif. Figure pour l’abrégé : Fig.14

Method of manufacturing semiconductor device and semiconductor device

To improve coupling reliability in flip chip bonding of a semiconductor device. By using, in the fabrication of a semiconductor device, a wiring substrate in which a wiring that crosses an opening area of a solder resist film on the upper surface of the wiring substrate has, on one side of the wiring, a bump electrode and, on the other side, a plurality of wide-width portions having no bump electrode thereon, a solder on the wiring can be dispersed to each of the wide-width portions during reflow treatment in a solder precoating step. Such a configuration makes it possible to reduce a difference in height between the solder on each of terminals and the solder on each of the wide-width portions and to enhance the coupling reliability in flip chip bonding.

Supporting backplane, manufacturing method therefor, and backplane

A supporting substrate, comprising: a base substrate (10) and multiple connecting electrodes (11) provided on the base substrate (10). At least one of the connecting electrodes (11) is provided on the side facing away from the base substrate (10) with a clamping electrode (13b). The clamping electrode (13b) is electrically connected to the corresponding connecting electrode (11). The clamping electrode (13b) is configured as capable of clamping and fixing an electrode pin (21a) of a micro light-emitting component. Also provided are a manufacturing method for the supporting substrate and a backplane.

Semiconductor device package and method of manufacturing the same

A semiconductor device package includes a first substrate having a first surface, a first electrical contact disposed on the first surface of the first substrate, a second substrate having a second surface facing the first surface of the first substrate, and a second electrical contact disposed on the second surface of the second substrate. The first electrical contact has a base portion and a protrusion portion. The second electrical contact covers at least a portion of the protrusion portion of the first electrical contact. The second electrical contact has a first surface facing the first substrate and a second surface facing the second substrate. A slope of a first interface between the second electrical contact and the protrusion portion of the first electrical contact adjacent to the first surface of the second electrical contact is substantially the same as a slope of a second interface between the second electrical contact and the protrusion portion of the first electrical contact adjacent to the second surface of the second electrical contact. A method of manufacturing a semiconductor device package is also disclosed.

Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask

Fluxless flip chip interconnection

A flip chip method of joining a chip and a substrate is described. A thermo-compression bonder is utilized to align the chip and substrate and apply a contact force to hold solder bumps on the substrate against metal bumps on the chip. The chip is rapidly heated from its non-native side by a pulse heater in the head of the bonder until the re-flow temperature of the solder bumps is reached. Proximate with reaching the re-flow temperature at the solder bumps, the contact force is released. The solder is held above its re-flow temperature for several seconds to facilitate wetting of the substrate's metal protrusions and joining. Metal caps comprised of a noble metal such as palladium is applied to the surface of the metal bumps to prevent the metal bumps (which generally comprise a highly-conductive and highly-reactive metal such as copper) from oxidizing in the elevated temperatures just prior to and during the re-flow operation.

Semiconductor Device and Method of Self-Confinement of Conductive Bump Material During Reflow Without Solder Mask

A semiconductor device has a semiconductor die with an die bump pad and substrate with a trace line and integrated bump pad. Conductive bump material is deposited on the substrate bump pad or die bump pad. The semiconductor die over the substrate so that the bump material is disposed between the die bump pad and substrate bump pad. The bump material is reflowed without a solder mask around the die bump pad or substrate bump pad to form an interconnect. The bump material is self-confined within a footprint of the die bump pad or substrate bump pad. The bump material can be immersed in a flux solution prior to reflow to increase wettability. Alternatively, the interconnect includes a non-fusible base and fusible cap. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material within the bump pads during reflow.

Package structure and manufacturing method

提供了封裝結構及製作方法。封裝結構包括半導體基底及半導體基底上之第一導電構件。封裝結構還包括基底及基底上之第二導電構件。第二導電構件透過接合結構而與第一導電構件接合。封裝結構更包括圍繞接合結構之保護材料，且保護材料直接接觸第一導電構件之側表面。

Bump-on-lead flip chip interconnection

플립 칩 인터커넥트는 인터커넥트 범프를 캡처 패드 위로 접합되는 것보다, 리드에 직접 접합함으로써 제작된다. 또한, 플립 칩 패키지는 활성 표면에서 인터커넥트 패드에 부착되는 솔더 범프를 포함하는 다이와, 다이 부착 표면에 있는 전기 전도성 트레이스를 갖는 기판을 포함하며, 이때 상기 접프는 상기 트레이스로 직접 접합된다. 일부 실시예에서, 인터커넥션이 솔더 마스크를 이용하지 않고 형성된다. 일부 바업에서는 , 경화성 부착제가 다이 위에 존재하는 범프나 기판 위에 존재하는 트레이스 위로 배포되며, 상기 부착제는 접합 공정 동안 부분 경화되고, 상기 부분 경화된 부착제는 융용된 솔더를, 리플로우 공정 동안, 제한하는 기능을 수행한다. Flip chip interconnects are fabricated by bonding interconnect bumps directly to the leads, rather than bonding over the capture pads. The flip chip package also includes a die including solder bumps attached to interconnect pads at an active surface, and a substrate having electrically conductive traces on the die attach surface, wherein the fold is bonded directly to the traces. In some embodiments, interconnections are formed without using a solder mask. In some bapups, a curable adhesive is distributed over a bump present on a die or a trace present on a substrate, the adhesive being partially cured during the bonding process, the partially cured adhesive transferring molten solder during the reflow process, It performs a limiting function.

Device for mounting semiconductor element, lead frame, and substrate for mounting semiconductor element

A device for mounting a semiconductor element includes a metal plate serving as a base, a roughened silver plating layer with acicular projections, formed on at least either of: (a) top faces; and (b) faces that form concavities or through holes between the top faces and bottom faces; of the metal plate, and a reinforcing plating layer covering, as an outermost plating layer, an outer surface of the acicular projections in the roughened silver plating layer. The roughened silver plating layer has a crystal structure in which the crystal direction <101> occupies a largest proportion among the crystal directions <001>, <111>, and <101>. An outer surface of the reinforcing plating layer is shaped to have acicular projections with a surface area ratio of 1.30 or more and 6.00 or less to the corresponding smooth surface, as inheriting the shape of the acicular projections in the roughened silver plating layer.

Multi-strike process for bonding

A method includes performing a first strike process to strike a metal bump of a first package component against a metal pad of a second package component. A first one of the metal bump and the metal pad includes copper. A second one of the metal bump and the metal pad includes aluminum. The method further includes performing a second strike process to strike the metal bump against the metal pad. An annealing is performed to bond the metal bump on the metal pad.

Metallurgical clamshell methods for micro land grid array fabrication

A structure and method for manufacturing the same for manufacturing a contact structure for microelectronics manufacturing including the steps of forming first and second metal sheets to form a plurality of outwardly extending bump each defining a cavity. Symmetrically mating the first and second metal sheets in opposing relation to each other to form upper and lower bumps each defining an enclosure therebetween wherein the mated first and second sheets form a contact structure. Coating the contact structure with an insulating material, and fabricating helix shaped contacts from upper and lower bumps. The helix shaped contacts having first and second portions being in mirror image relationship to each other.

Bump-on-lead flip chip interconnection

A semiconductor device has a semiconductor die with a plurality of bumps formed over the die. A substrate has a plurality of conductive traces formed on the substrate. Each trace has an interconnect site for mating to the bumps. The interconnect sites have parallel edges along a length of the conductive traces under the bumps from a plan view for increasing escape routing density. The bumps have a noncollapsible portion for attaching to a contact pad on the die and fusible portion for attaching to the interconnect site. The fusible portion melts at a temperature which avoids damage to the substrate during reflow. The noncollapsible portion includes lead solder, and fusible portion includes eutectic solder. The interconnect sites have a width which is less than 1.2 times a width of the conductive trace. Alternatively, the interconnect sites have a width which is less than one-half a diameter of the bump.

Microelectronic substrate having embedded trace layers with integral attachment structures

A microelectronic substrate may be formed to have an embedded trace which includes an integral attachment structure that extends beyond a first surface of a dielectric layer of the microelectronic substrate for the attachment of a microelectronic device. In one embodiment, the embedded trace may be fabricated by forming a dummy layer, forming a recess in the dummy layer, conformally depositing surface finish in the recess, forming an embedded trace layer on the dummy layer and abutting the surface finish, and removing the dummy layer.

3D integrated circuit (3DIC) structure

An embodiment bonded integrated circuit (IC) structure includes a first IC structure and a second IC structure bonded to the first IC structure. The first IC structure includes a first bonding layer and a connector. The second IC structure includes a second bonding layer bonded to and contacting the first bonding layer and a contact pad in the second bonding layer. The connector extends past an interface between the first bonding layer and the second bonding layer, and the contact pad contacts a lateral surface and a sidewall of the connector.

ELECTRONIC STRUCTURE INCLUDING INTERCONNECTION FILM

STRUCTURE ÉLECTRONIQUE COMPRENANT UN FILM D’INTERCONNEXION Un aspect de l’invention concerne une structure électronique (1) comprenant : un substrat (10) ;un composant électronique (20) ;un film d’interconnexion (30) disposé entre le substrat (10) et le composant électronique (20), reliant électriquement et mécaniquement le composant électronique au substrat ; le film d’interconnexion (30) comprenant une première face (30a), une deuxième face (30b) opposée à la première face, une zone électriquement conductrice (31) s’étendant de la première face (30a) à la deuxième face (30b) et un matériau polymère (32) électriquement isolant enrobant la zone électriquement conductrice (31), au moins l’une des première et deuxième faces (30a, 30b) du film d’interconnexion (30) étant structurée de manière à former un film d’adhésif sec, ladite au moins une des première et deuxième faces (30a, 30b) présentant une pluralité de motifs (33), une partie au moins des motifs (33) étant formés du matériau polymère (32) électriquement isolant. Figure à publier avec l’abrégé : Figure 1 ELECTRONIC STRUCTURE COMPRISING AN INTERCONNECT FILM One aspect of the invention relates to an electronic structure (1) comprising: a substrate (10); an electronic component (20); an interconnect film (30) disposed between the substrate (10) ) and the electronic component (20), electrically and mechanically connecting the electronic component to the substrate; the interconnect film (30) comprising a first face (30a), a second face (30b) opposite the first face, an electrically conductive zone (31) extending from the first face (30a) to the second face ( 30b) and an electrically insulating polymeric material (32) coating the electrically conductive zone (31), at least one of the first and second faces (30a, 30b) of the interconnect film (30) being structured so as to form a film of dry adhesive, said at least one of the first and second faces (30a, 30b) having a plurality of patterns (33), at least part of the ...

Semiconductor element mounting parts, lead frame and semiconductor element mounting substrate

【課題】コストや作業時間を低減して、生産性を向上させながら、銀めっき層を含むめっき層全体の厚さを薄く抑え、且つ、封止樹脂との密着性を格段に高くした状態を維持することの可能な半導体素子搭載用部品を提供すること。【解決手段】リードフレーム基材をなす金属板１０の上面、側面、下面のうち、少なくとも上面又は側面に、針状の突起群を有する粗化銀めっき層１１を備えるとともに、粗化銀めっき層における針状の突起群の表面を覆う、補強用めっき層１１αを最表層のめっき層として備え、粗化銀めっき層は、結晶方位＜００１＞、＜１１１＞、＜１０１＞の夫々の比率のうち結晶方位＜１０１＞の比率が最も高い結晶構造を有し、補強用めっき層の表面は、粗化銀めっき層の針状の突起群を受け継いで、平滑な面の表面積に対する表面積比が、１．３０以上６．００以下となる針状の突起群を有する形状に形成されている。【選択図】図１ PROBLEM TO BE SOLVED: To reduce the cost and working time, improve productivity, suppress the overall thickness of a plating layer including a silver plating layer, and improve the adhesion to a sealing resin significantly. To provide a semiconductor element mounting component that can be maintained. SOLUTION: A roughened silver plating layer 11 having a needle-shaped projection group is provided on at least an upper surface or a side surface of a metal plate 10 forming a lead frame base material, and the roughened silver plating layer is provided. The surface of the needle-like protrusion group in the above is provided with a reinforcing plating layer 11α as the outermost plating layer, and the roughened silver plating layer has crystal orientations of <001>, <111>, and <101> at respective ratios. Among them, it has a crystal structure with the highest ratio of crystal orientation <101>, and the surface of the reinforcing plating layer inherits the needle-shaped protrusions of the roughened silver plating layer, and the surface area ratio to the surface area of the smooth surface is It is formed in a shape having a group of needle-shaped protrusions of 1.30 or more and 6.00 or less. [Selection diagram] Figure 1

Driving back plate and display device

本发明涉及显示领域，公开一种驱动背板及显示装置，该驱动背板，包括：衬底基板；设置于衬底基板上一侧的第一导电层、设置在所述第一导电层背离所述衬底基板一侧的第二导电层、设置在所述第一导电层和所述第二导电层之间的第一绝缘层；其中，所述第二导电层包括多个焊盘，每一个所述焊盘通过至少两个第一过孔与第一导电层连接。提高第二导电层与绝缘层之间的附着力，使得第二导电层的焊盘与绝缘层之间不易脱落；另外，每一个焊盘与第一导电层之间通过多个第一过孔实现导通，这样，即使焊盘中的部分区域对应的第一过孔受损，焊盘仍然可以通过其他的第一过孔与第一导电层保持良好的导通，提高了第二导电层中的焊盘与第一导电层连接的良率。

Integrated mechanical aids for high accuracy alignable-electrical contacts

A method and apparatus for laterally urging two semiconductor chips, dies or wafers into an improved state of registration with each other, the method and apparatus employing microstructures comprising: a first microstructure disposed on a first major surface of a first one of said two semiconductor chips, dies or wafers, wherein the first microstructure includes a sidewall which is tapered thereby disposing it at an acute angle compared to a perpendicular of said first major surface, and a second microstructure disposed on a first surface of a second one of said two semiconductor chips, dies or wafers, wherein the shape of the second microstructure is complementary to, and mates with or contacts, in use, the first microstructure, the second microstructure including a surface which contacts said sidewall when the first and second microstructures are mated or being mated, the sidewall of the first microstructure and the surface of the second microstructure imparting a lateral force for urging the two semiconductor chips, dies or wafers into said improved state of registration.

Stackable via package and method

A stackable via package includes a substrate having an upper surface and a trace on the upper surface, the trace including a terminal. A solder ball is on the terminal. The solder ball has a solder ball diameter A and a solder ball height D. A via aperture is formed in a package body enclosing the solder ball to expose the solder ball. The via aperture includes a via bottom having a via bottom diameter B and a via bottom height C from the upper surface of the substrate, where A<B and 0=<C<1/2×D. The shape of the via aperture prevents solder deformation of the solder column formed from the solder ball as well as prevents solder bridging between adjacent solder columns.

Semiconductor device package including stress buffering layer

A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.

Semiconductor modules, electronic devices, and printed wiring boards

Flip chip wiring having a narrow wiring portion on a substrate

基板上のダイのフリップチップ配線は、配線の隆起を、キャプチャパッド上にではなく、リードまたはトレースの上の狭い配線パッドの上に嵌合することによってなされる。狭い配線パッドの幅は、取り付けられるダイ上の隆起のベース直径未満である。また、フリップチップパッケージは、活性表面において配線パッドに取り付けられた半田の隆起を有しているダイと、ダイ取り付け表面において導電性トレースの上に狭い配線パッドを有している基板とを含んでおり、上記基板における隆起は、トレース上の狭いパッドに嵌合される。

Semiconductor component having an opening for optical monitoring

The invention relates to a semiconductor component. The semiconductor component comprises electrical connections which are each designed for soldering to a circuit carrier. The semiconductor component has a semiconductor, in particular a semiconductor chip. The semiconductor component also has a connection surface, wherein a plurality of electrical connections are formed on the connection surface. The connections each have a contact surface designed for soldering, in particular reflow soldering. According to the invention, the semiconductor component has at least one opening, which extends between the contact surface and a surface of the semiconductor component opposite the connection surface. The opening is designed in such a way that a soldering joint in the region of the connection can be optically recorded from outside through the opening.

Flip chip interconnection having narrow interconnection sites on the substrate

Semiconductor device assembly with pre-reflowed solder

A semiconductor device assembly includes a package substrate having a top side including a plurality of bondable features, at least one integrated circuit (IC) die including a substrate having at least a semiconductor surface including circuitry configured for realizing at least one function including nodes coupled to bond pads with metal posts on the bond pads. The metal posts are attached by a solder joint to the bondable features. The solder joint has a void density of less than or equal to (≥) 5% of a cross-sectional area of the solder joint.

Microelectronic package containing silicon patches for high density interconnects, and methods of making same

Mikroelektronischer Baustein, umfassend: ein Substrat; ein Siliziumpatch, der in das Substrat eingebettet ist; eine erste Zwischenverbindungsstruktur an einem ersten Ort des Siliziumpatches und eine zweite Zwischenverbindungsstruktur an einem zweiten Ort des Siliziumpatches; und eine elektrische Leitung im Siliziumpatch, die die erste Zwischenverbindungsstruktur und die zweite Zwischenverbindungsstruktur miteinander verbindet. Microelectronic device comprising: a substrate; a silicon patch embedded in the substrate; a first interconnect structure at a first location of the silicon patch and a second interconnect structure at a second location of the silicon patch; and an electrical line in the silicon patch interconnecting the first interconnect structure and the second interconnect structure.

Stackable via package and method

A stackable via package includes a substrate having an upper surface and a trace on the upper surface, the trace including a terminal. A solder ball is on the terminal. The solder ball has a solder ball diameter A and a solder ball height D. A via aperture is formed in a package body enclosing the solder ball to expose the solder ball. The via aperture includes a via bottom having a via bottom diameter B and a via bottom height C from the upper surface of the substrate, where A<B and 0=<C<½×D. The shape of the via aperture prevents solder deformation of the solder column formed from the solder ball as well as prevents solder bridging between adjacent solder columns.

Electrical interconnect structure for a semiconductor device and an assembly using the same

An electrical interconnect structure for a semiconductor device is provided herein. The electrical interconnect structure includes a conductive pillar (114) electrically coupled to a conductive contact (112) positioned on a emiconductor die (110) and a trace receiver (140) on a distal end of the pillar (114). The trace receiver (140) has a body (145) electrically coupled to the distal end, and may include a first leg(147a) projecting from a first side of the body (145) away from the distal end and a second leg (147b) projecting from a second side of the body (145) away from the distal end, such that the body (145), the first leg (147a), and the second leg (147b) together form a cavity. During assembly of the semiconductor device, the cavity is configured to at least partially surround a portion of a trace (122) positioned in an insulated substrate (120). To form the electrical connection, a solder material (142) may be disposed between the trace receiver (140) and the trace (122).

Fluxless flip chip interconnection

Room temperature direct metal-metal bonding

A method for forming direct metal-metal bond between metallic surfaces is disclosed. The method comprises depositing a first nanostructured organic coating ( 118 ) on a first metallic surface ( 116 ) to form a first passivation layer thereon, the first nanostructured organic coating ( 118 ) comprising an organic phase with nanoparticles dispersed within the organic phase, contacting the first nanostructured organic coating ( 118 ) with a second metallic surface ( 126 ), and applying on the first and second metallic surfaces ( 116, 126 ) at least a bonding temperature of at least room temperature and/or a bonding pressure for a bonding period to bond the first and second metallic surfaces ( 116, 126 ) thereby forming the direct metal-metal bond therebetween. A second nanostructured organic coating ( 128 ) comprising an organic phase with nanoparticles dispersed within the organic phase may also be deposited on the second metallic surface ( 126 ).

Substrate for Pre-Soldering Material and Fabrication Method Thereof

A substrate for a pre-soldering material and a fabrication method of the substrate are proposed. The substrate having at least one surface formed with a plurality of conductive pads is provided. An insulating layer is formed over the surface of the substrate in such a way that a top surface of each of the conductive pads is exposed. Next, a conductive film and a resist layer are formed in sequence on the insulating layer and the conductive pads, wherein a plurality of openings are formed in the resist layer to expose a part of the conductive film above the conductive pad. Then, a pre-soldering material is deposited over the conductive pad by stencil printing or electroplating process.

Bonding structure for semiconductor package and method of manufacturing the same

A method of manufacturing a bonding structure includes (a) providing a substrate, wherein the substrate includes a top surface and at least one bonding pad disposed adjacent to the top surface of the substrate, at least one bonding pad having a sloped surface with a first slope; (b) providing a semiconductor element, wherein the semiconductor element includes at least one pillar, and at least one pillar has a sidewall with a second slope, wherein the absolute value of the first slope is smaller than the absolute value of the second slope; and (c) bonding at least one pillar to a portion of the sloped surface of corresponding ones of the at least one bonding pad.

A method of forming a metallic interconnect, method of making a semiconductor interconnect having a metallic interconnect, and a semiconductor interconnect semiconductor device array

Eine metallische Zwischenverbindung und eine Halbleiteranordnung, die sie enthält, wobei ein Verfahren zu ihrer Herstellen Folgendes enthalten kann: Bereitstellen einer ersten Struktur, die eine erste metallische Schicht enthält, die vorstehende erste Mikrostrukturen aufweist; Bereitstellen einer zweiten Struktur, die eine zweite metallische Schicht enthält, die vorstehende zweite Mikrostrukturen aufweist; Kontaktieren der ersten und zweiten Mikrostrukturen, um eine mechanische Verbindung zwischen den Strukturen zu bilden, wobei die mechanische Verbindung konfiguriert ist, die Durchdringung eines Fluids zu erlauben; Entfernen einer oder mehrerer nichtmetallischer Verbindungen auf der ersten metallischen Schicht und der zweiten metallischen Schicht mit einem Reduktionsmittel, das die mechanische Verbindung durchdringt und mit der einen oder den mehreren nichtmetallischen Verbindungen reagiert; und Erwärmen der ersten metallischen Schicht und der zweiten metallischen Schicht auf eine Temperatur, die eine Zwischendiffusion der ersten metallischen Schicht und der zweiten metallischen Schicht verursacht, um die metallische Zwischenverbindung zwischen den Strukturen zu bilden. A metallic interconnect and a semiconductor device containing the same, wherein a method of making the same may include: providing a first structure including a first metallic layer having protruding first microstructures; Providing a second structure including a second metallic layer having protruding second microstructures; Contacting the first and second microstructures to form a mechanical connection between the structures, wherein the mechanical connection is configured to allow the penetration of a fluid; Removing one or more non-metallic compounds on the first metallic layer and the second metallic layer with a reducing agent which penetrates the mechanical compound and reacts with the one or more non-metallic compounds; and heating the first metallic layer and the second metallic layer to a ...

Semiconductor integrated circuit

本发明公开了一种半导体集成电路，包括：半导体芯片，所述半导体芯片包括存储器单元阵列；多个第一穿通芯片通孔，所述多个第一穿通芯片通孔被配置为垂直地贯穿所述半导体芯片且作为信号和电源电压的接口而操作；以及半导体衬底。半导体衬底包括：外围电路区域，所述外围电路区域与所述多个第一穿通芯片通孔相耦接且被配置为控制所述半导体芯片；以及导电图案区域，所述导电图案区域被配置为在所述外围电路区域与外部控制器之间作为信号和电源电压的接口而操作。

Stackable via package and method

A stackable via package includes a substrate having an upper surface and a trace on the upper surface, the trace including a terminal. A solder ball is on the terminal. The solder ball has a solder ball diameter A and a solder ball height D. A via aperture is formed in a package body enclosing the solder ball to expose the solder ball. The via aperture includes a via bottom having a via bottom diameter B and a via bottom height C from the upper surface of the substrate, where A<B and 0=<C< ½ ×D. The shape of the via aperture prevents solder deformation of the solder column formed from the solder ball as well as prevents solder bridging between adjacent solder columns.

Dispositif à tige d'insert de connexion électrique semi-enterrée

L'invention concerne un système doté d'un dispositif microélectronique comprenant un substrat (100) exposé sur une face du dispositif, le substrat (100) comprenant au moins un élément (105) électriquement conducteur, et un organe de raccordement électrique (130) en continuité électrique avec l'élément (105) et comprenant au moins une tige (116) faisant saillie sur la face du dispositif, caractérisé en ce que l'organe de raccordement (130) comprend une portion d'ancrage (131) inorganique recouvrant l'élément (105) et en ce que la tige (116) comprend une portion enterrée (1161) dans la portion d'ancrage (131) suivie d'une portion saillante (1162) sur la face du dispositif.

半埋式电连接插杆装置

本发明涉及一种设置有微电子装置的系统，该微电子装置包括暴露于装置的表面上的基板(100)，该基板(100)包括至少一个导电元件(105)，以及与该元件(105)电连接并包括突出于装置的表面上的至少一个杆(116)的电连接构件(130)，其特征在于，连接构件(130)包括覆盖元件(105)的无机锚固部分(131)，并且杆(116)包括掩埋在锚固部分(131)中的部分(1161)以及突出于装置的表面上的部分(1162)。

Half-buried electrical connection insert rod device

A system provided with a microelectronic device includes a substrate exposed on a face of the device, the substrate having at least one electrically conductive element, and an electrical connection member in electrical continuity with the element and including at least one rod projecting over the face of the device, wherein the connection member includes an inorganic anchoring portion covering the element and in that the rod comprises a portion buried in the anchoring portion followed by a portion projecting over the face of the device.

반도체 장치 및 반도체 장치의 제조 방법

패드가 소형화한 경우에도 솔더 접속 강도를 향상시킨다. 반도체 장치는 패드와 확산층과 용해층을 구비한다. 그 반도체 장치가 구비하는 패드는, 표면에 오목부를 구비하고 솔더 접속을 행한다. 그 반도체 장치가 구비하는 확산층은, 그 오목부에 배치되어 그 솔더 접속할 때에 솔더 내로 확산하면서 그 패드의 표면에 잔류하는 금속에 의해 구성된다. 그 반도체 장치가 구비하는 용해층은, 그 확산층에 인접하여 배치되어 그 솔더 접속할 때에 그 솔더 내로 확산하여 용해하는 금속에 의해 구성된다.

Display panel

A display panel is provided. The display panel includes a driving backplane with a connecting electrode, an insulating layer arranged on the connecting electrode, and a light-emitting unit arranged on the driving backplane. The insulating layer includes an opening exposing part of a surface of the connecting electrode. The light-emitting unit is electrically connected with a bump electrode, and the bump electrode is electrically connected with the connecting electrode through the opening. The opening has a ridge and furrow profile, which can increase an area of a sidewall of the opening, such that a contact area between the bump electrode and the sidewall is increased to prevent peeling or cracking between the films.

Nanowires plated on nanoparticles

In some examples, a system comprises a set of nanoparticles and a set of nanowires extending from the set of nanoparticles.

Semiconductor package and manufacturing method of the same

A semiconductor package and a manufacturing method thereof are described. The semiconductor package includes a package having dies encapsulated by an encapsulant, a redistribution circuit structure, first and second modules and affixing blocks. The redistribution circuit structure is disposed on the package. The first and second modules are disposed on and respectively electrically connected to the redistribution circuit structure by first and second connectors disposed there-between. The first and second modules are adjacent to each other and disposed side by side on the redistribution circuit structure. The affixing blocks are disposed on the redistribution circuit structure and between the first and second modules and the redistribution circuit structure. The affixing blocks include first footing portions located below the first module, second footing portions located below the second module, and exposed portions exposed from the first and second modules. The affixing blocks join the first and second modules to the redistribution circuit structure.

반도체 소자 탑재용 기판

본 발명은, 금속판의 한쪽의 면에 은 도금이 최외측 표층의 도금으로서 실시된, 도금층만을 포함하는 기둥형 단자부를 구비한 반도체 소자 탑재용 기판에 있어서, 비용이나 작업 시간을 저감하여, 생산성을 향상시키면서, 은 도금층을 포함하는 단자 등이 되는 도금층 전체의 두께를 얇게 억제하고, 또한, 밀봉 수지와의 밀착성을 각별히 높게 하는 것이 가능한 반도체 소자 탑재용 기판을 제공하는 것을 과제로 한다. 금속판(10)의 한쪽의 면에, 도금층만을 포함하는 기둥형 단자부(12-1)를 구비한 반도체 소자 탑재용 기판(1)으로서, 기둥형 단자부는, 바늘형의 돌기군을 갖는 조화 은 도금층(11)을 최외측 표층의 도금층으로서 구비하고, 조화 은 도금층은, 결정 방위 <001>, <111>, <101>의 각각의 비율 중 결정 방위 <101>의 비율이 가장 높은 결정 구조를 갖는다.

半導體元件搭載用基板

課題：提供一種半導體元件搭載用基板，其為藉由在由銅系材料構成的金屬板的上表面設置凹部而形成的柱狀端子部的上表面實施銀鍍覆作為最表層的鍍覆的半導體元件搭載用基板，能夠實現進行倒裝晶片安裝的半導體封裝的薄型化並且一方面減少成本、作業時間而提高生產率，另一方面將包含銀鍍層的鍍層整體的厚度抑制為較薄而且使得與密封樹脂的密合性顯著提高。 解決手段：一種半導體元件搭載用基板，其具有藉由在由銅系材料構成的金屬板10上表面設置凹部而形成的柱狀端子部10-1，且在柱狀端子部上表面具備具有針狀的突起群的粗糙化銀鍍層11作為最表層的鍍層，粗糙化銀鍍層具有在晶體方位＜001＞、＜111＞、＜101＞之各者之比率中晶體方位＜101＞的比率最高的晶體結構。

반도체 소자 탑재용 부품, 리드 프레임 및 반도체 소자 탑재용 기판

본 발명은, 비용이나 작업 시간을 저감하여, 생산성을 향상시키면서, 은 도금층을 포함하는 도금층 전체의 두께를 얇게 억제하고, 또한, 밀봉 수지와의 밀착성을 각별히 높게 한 상태를 유지하는 것이 가능한 반도체 소자 탑재용 부품을 제공하는 것을 과제로 한다. 리드 프레임 기재를 이루는 금속판(10)의 상면, 측면, 하면 중 적어도 상면 또는 측면에, 바늘형의 돌기군을 갖는 조화 은 도금층(11)을 구비하며, 조화 은 도금층에 있어서의 바늘형의 돌기군의 표면을 덮는, 보강용 도금층(11α)을 최외측 표층의 도금층으로서 구비하고, 조화 은 도금층은, 결정 방위 <001>, <111>, <101>의 각각의 비율 중 결정 방위 <101>의 비율이 가장 높은 결정 구조를 가지고, 보강용 도금층의 표면은, 조화 은 도금층의 바늘형의 돌기군을 이어받아, 평활한 면의 표면적에 대한 표면적비가, 1.30 이상 6.00 이하가 되는 바늘형의 돌기군을 갖는 형상으로 형성되어 있다.

반도체 소자 탑재용 기판

본 발명은, 구리계 재료를 포함하는 금속판의 상면에 오목부를 마련함으로써 형성된, 기둥형 단자부의 상면에, 은 도금이 최외측 표층의 도금으로서 실시된 반도체 소자 탑재용 기판에 있어서, 플립 칩 실장한 반도체 패키지의 박형화와 함께, 비용이나 작업 시간을 저감하여, 생산성을 향상시키면서, 은 도금층을 포함하는 도금층 전체의 두께를 얇게 억제하고, 또한, 밀봉 수지와의 밀착성을 각별히 높게 하는 것이 가능한 반도체 소자 탑재용 기판을 제공하는 것을 과제로 한다. 구리계 재료를 포함하는 금속판(10)의 상면에 오목부를 마련함으로써 형성된, 기둥형 단자부(10-1)를 갖는 반도체 소자 탑재용 기판으로서, 기둥형 단자부의 상면에 바늘형의 돌기군을 갖는 조화 은 도금층(11)을 최외측 표층의 도금층으로서 구비하고, 조화 은 도금층은, 결정 방위 <001>, <111>, <101>의 각각의 비율 중 결정 방위 <101>의 비율이 가장 높은 결정 구조를 갖는다.

Semiconductor device package including stress buffering layer

A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.

Semiconductor package and method of fabricating the same

Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a redistribution substrate including dielectric and redistribution patterns, a first substrate pad on the redistribution substrate and penetrating the dielectric pattern to be coupled to the redistribution pattern, a second substrate pad the redistribution substrate and spaced apart from the first substrate pad, a semiconductor chip on the redistribution substrate, a first connection terminal connecting the first substrate pad to one of chip pads of the semiconductor chip, and a second connection terminal connecting the second substrate pad to another one of the chip pads of the semiconductor chip. A top surface of the second substrate pad is located at a higher level than that of a top surface of the first substrate pad. A width of the second substrate pad is less than that of the first substrate pad.

Interconnect using nanoporous metal locking structures

Embodiments relate to the design of a device capable of maintaining the alignment an interconnect by resisting lateral forces acting on surfaces of the interconnect. The device comprises a first body comprising a first surface with a nanoporous metal structure protruding from the first surface. The device further comprises a second body comprising a second surface with a locking structure to resist a lateral force between the first body and the second body during or after assembly of the first body and the second body.

半导体装置和半导体装置的制造方法

即使当焊盘小型化时，本发明也能提高焊接强度。该半导体装置设置有焊盘、扩散层和熔融层。设置在所述半导体装置中的所述焊盘在其所述表面中包括凹部，并经过焊接。设置在所述半导体装置中的所述扩散层由布置在所述凹部中并当进行焊接时扩散到所述焊料中并保留在所述焊盘的表面上的金属制成。设置在所述半导体装置中的所述熔融层由与所述扩散层相邻布置并当进行焊接时扩散到所述焊料中并熔融的金属制成。

반도체 장치 및 반도체 장치의 제조 방법

패드가 소형화한 경우에도 솔더 접속 강도를 향상시킨다. 반도체 장치는 패드와 확산층과 용해층을 구비한다. 그 반도체 장치가 구비하는 패드는, 표면에 오목부를 구비하고 솔더 접속을 행한다. 그 반도체 장치가 구비하는 확산층은, 그 오목부에 배치되어 그 솔더 접속할 때에 솔더 내로 확산하면서 그 패드의 표면에 잔류하는 금속에 의해 구성된다. 그 반도체 장치가 구비하는 용해층은, 그 확산층에 인접하여 배치되어 그 솔더 접속할 때에 그 솔더 내로 확산하여 용해하는 금속에 의해 구성된다.

半導體元件搭載用零件、引線框和半導體元件搭載用基板

課題：提供一種能一方面減少成本、作業時間而提高生產率，另一方面將包含銀鍍層的鍍層整體厚度抑制為較薄且維持顯著提高了與密封樹脂的密合性的狀態的半導體元件搭載用零件。 解決手段：在成為基材的金屬板10的上表面、側面、下表面中的至少上表面或側面，具備具有針狀突起群的粗糙化銀鍍層，並且具備覆蓋粗糙化銀鍍層中針狀突起群的表面的增強用鍍層作為最表層的鍍層，粗糙化銀鍍層具有在晶體方位＜001＞、＜111＞、＜101＞的各者的比率中晶體方位＜101＞的比率最高的晶體結構，增強用鍍層的表面沿襲粗糙化銀鍍層的針狀突起群而形成為具有相對於平滑面的表面積的表面積比成為1.30以上6.00以下的針狀突起群的形狀。

금속 전해도금막을 이용한 구리 대 구리 직접 접합 방법, 이를 이용한 웨이퍼 레벨 패키징 방법 및 이를 이용하여 제조된 반도체 소자

본 발명은 구리 대 구리(Cu-to-Cu)를 직접 접합하는 방법에 관한 것으로, 분리된 구리 재질의 접합 대상물을 접합하는 방법에 있어서, 접합 대상면 중에 적어도 한쪽면의 표면에 전해 도금에 의해서 금속층을 형성하는 전해 도금 단계; 상기 전해 도금 단계에서 형성된 금속층이 사이에 위치하도록 접합 대상물을 위치시키는 배치 단계; 접합 대상물의 양쪽에서 금속층을 향하여 가압하면서 전류를 인가하는 가압 접합 단계를 포함하며, 상기 가압 접합 단계는 금속층에서 발생된 줄 열에 의해서 접합 대상물의 접합 대상면이 가열되어 접합되는 것을 특징으로 한다. 본 발명은, 금속층이 형성된 접합 대상면을 중심으로 가열하기 때문에, 기판을 포함한 소자 전체에 열을 가하였던 종래 기술들에 비하여 반도체 소자에 대한 손상 없이 구리 대 구리 직접 접합을 수행할 수 있는 뛰어난 효과가 있다. 또한, 반도체 소자에 손상이 발생하지 않는 저온에서 열접합을 수행하기 위한 종래 기술들에 비하여, 공정비용이 저렴하고 접합 품질이 뛰어난 효과가 있다.

Porous fli bumps for reducing bump thickness variation sensitivity to enable bump pitch scaling

Embodiments disclosed herein include electronic packages with fin pitch first level interconnects. In an embodiment, the electronic package comprises a die and a package substrate attached to the die by a plurality of first level interconnects (FLIs). In an embodiment, individual ones of the plurality of FLIs comprise, a first pad on the package substrate, a solder on the first pad, a second pad on the die, and a bump on the second pad. In an embodiment, the bump comprises a porous nanostructure, and the solder at least partially fills the porous nanostructure.

Bonded semiconductor package and related methods

Implementations of a semiconductor package may include: a first wafer having a first surface and a first set of blade interconnects, the first set of blade interconnects extending from the first surface. The package may include a second wafer having a first surface and a second set of blade interconnects, the second set of blade interconnects extending from the first surface and oriented substantially perpendicularly to a direction of orientation of the first set of blade interconnects. The first set of blade interconnects may be hybrid bonded to the second set of blade interconnects at a plurality of points of intersection between the first and second set of blade interconnects. The plurality of points of intersection may be located along a length of each blade interconnect of the first set of blade interconnects, and along the length of each blade interconnect of the second set of blade interconnects.

Dielectric and metallic nanowire bond layers

In some examples, an electronic device comprises a first component having a surface, a second component having a surface, and a bond layer positioned between the surfaces of the first and second components to couple the first and second components to each other. The bond layer includes a set of metallic nanowires and a dielectric portion. The dielectric portion comprises a polymer matrix and dielectric nanoparticles.

用于半导体封装件的Cu表面上的多孔Cu

本发明公开了一种半导体封装件，其包括多个金属引线和通过互连附接到多个金属引线的半导体管芯。多个金属引线的表面、半导体管芯的金属化表面和/或互连的表面包括Cu，并且具有在340至400W/mK范围内的热导率以及在80％至110％IACS范围内的电导率。包括Cu并且具有在340至400W/mK范围内的热导率以及在80％至110％IACS范围内的电导率的一个或多个所述表面还包括具有在1μm至10μm范围内的直径的微孔。还描述了一种制造具有这种微孔的金属表面的方法。

Substrates having bumps with holes, semiconductor chips having bumps with holes, semiconductor packages formed using the same, and methods of fabricating the same

Substrates and semiconductor chips are provided. The substrate or the semiconductor chip includes a body and a substantially pillar-shaped bump disposed on a first surface of the body. The pillar-shaped bump has a hole penetrating a portion thereof. Related semiconductor packages are also provided. Further, related methods are provided.

Zielträger, halbleiteranordnung und verfahren zum transferieren eines halbleiterbauelements und haltestruktur

Die Erfindung betrifft einen Zielträger für ein Transferieren von Halbleiterbauelementen (3), bei dem die Halbleiterbauelemente (3) wenigstens ein Kontaktpad (31, 31') aufweisen. Der Zielträger (1) umfasst ein Zielsubstrat (10) mit wenigstens zwei Kontaktbereichen (11, 11') und eine schrumpfbare Auffangschicht (20), die um jeden der wenigstens zwei Kontaktbereiche (11, 11') angeordnet ist und die wenigstens zwei Kontaktbereiche (11, 11') überragt. Ein lateraler Abstand zwischen Material der schrumpfbaren Auffangschicht (20) um jeden der wenigstens zwei Kontaktbereiche (11, 11') ist kleiner als eine laterale Abmessung des wenigstens einen Kontaktpads (31, 31').