Chip package with plank stack of semiconductor dies

In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are separated by a mechanical spacer (such as a filler material or an adhesive). Moreover, the chip package includes a substrate at a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the substrate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as: solder, stud bumps, plated traces, wire bonds, spring connectors, a conductive adhesive and/or an anisotropic conducting film. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the substrate.

Wafer-level device packaging

The present invention relates to a semiconductor device packaged at the wafer level such that an entire packaged device is formed prior to separation of individual devices. The semiconductor device package includes a semiconductor chip having one or more bonding pads associated with the chip and a protective layer bonded over the semiconductor chip. An insulation layer is positioned on at least side edges and a lower surface of the semiconductor chip. Interconnection/bump metallization is positioned adjacent one or more side edges of the semiconductor chip and is electrically connected to at least one bonding pad. A compact image sensor package can be formed that is vertically integrated with a digital signal processor and memory chip along with lenses and a protective cover.

Transient Electronic Device With Ion-Exchanged Glass Treated Interposer

A transient electronic device utilizes a glass-based interposer that is treated using ion-exchange processing to increase its fragility, and includes a trigger device operably mounted on a surface thereof. An integrated circuit (IC) die is then bonded to the interposer, and the interposer is mounted to a package structure where it serves, under normal operating conditions, to operably connect the IC die to the package I/O pins/balls. During a transient event (e.g., when unauthorized tampering is detected), a trigger signal is transmitted to the trigger device, causing the trigger device to generate an initial fracture force that is applied onto the glass-based interposer substrate. The interposer is configured such that the initial fracture force propagates through the glass-based interposer substrate with sufficient energy to both entirely powderize the interposer, and to transfer to the IC die, whereby the IC die also powderizes (i.e., visually disappears). 1. A method for manufacturing a transient electronic device using comprising:subjecting at least one interposer to an ion-exchange treatment, said at least one interposer including a glass substrate having a first surface and an opposing second surface, and including a trigger device on the glass substrate, said trigger device being configured to generate and apply an initial fracture force on said glass substrate in response to a trigger signal;fixedly attaching an integrated circuit (IC) die to the treated glass substrate such that a plurality of IC contact points disposed in a first pattern on a surface of the semiconductor substrate are electrically connected to corresponding first interposer contact structures disposed on the first surface of the treated glass substrate; andsecuring the interposer to a package structure such that a plurality of first package contact structures disposed in a second pattern on a surface of the package structure are electrically connected to corresponding second interposer ...

SEMICONDUCTOR DEVICE

A semiconductor device includes an insulating substrate, a wiring, a semiconductor chip and a resin layer. The wiring is provided on the insulating substrate. The wiring board includes (i) an insulating material and (ii) a pad exposed relative to the insulating material and electrically connected to the wiring. A height of the insulating material in a vertical direction of the wiring board varies along the wiring board. The semiconductor chip includes a bump connected to the pad on a first surface of the semiconductor chip. The resin layer covers a periphery of the bump between the wiring board and the semiconductor chip. 2. The semiconductor device according to claim 1 ,wherein the height of the insulating material decreases from a central portion of the semiconductor chip to an outer peripheral portion of the semiconductor chip.4. The semiconductor device according to claim 3 ,wherein the bump is provided in the first region.5. The semiconductor device according to claim 4 ,wherein an electrical signal passes through the bump.6. The semiconductor device according to claim 2 , whereinthe wiring board further includes a projecting portion that projects from the insulating material toward the outer peripheral portion of the semiconductor chip, anda height of an upper surface of the wiring board in the vertical direction of the wiring board is equal to or greater than a height of the pad in the vertical direction of the wiring board.7. The semiconductor device according to claim 1 ,wherein a maximum value of a height of the insulating material facing the semiconductor chip is equal to or less than a height of the pad.8. The semiconductor device according to claim 1 ,wherein the height of the insulating material is higher in a central portion of the semiconductor chip facing the wiring board than an outer peripheral portion of the semiconductor chip facing the wiring board.9. The semiconductor device according to claim 8 ,wherein the insulating material has a height ...

Electronic apparatus and method for fabricating the same

An electronic apparatus includes a first electronic part with a first terminal, a second electronic part with a second terminal opposite the first terminal, and a joining portion which joins the first terminal and the second terminal. The joining portion contains a pole-like compound extending in a direction in which the first terminal and the second terminal are opposite to each other. The joining portion contains the pole-like compound, so the strength of the joining portion is improved. When the first terminal and the second terminal are joined, the temperature of one of the first electronic part and the second electronic part is made higher than that of the other. A joining material is cooled and solidified in this state. By doing so, the pole-like compound is formed.

Protrusion Bump Pads for Bond-on-Trace Processing

An embodiment apparatus includes a dielectric layer, a conductive trace in the dielectric layer, and a bump pad. The conductive trace includes a first portion having an exposed top surface, wherein the exposed top surface is recessed from a top surface of the dielectric layer. Furthermore, the bump pad is disposed over and is electrically connected to a second portion of the conductive trace. 1. An apparatus comprising:a dielectric layer;a conductive trace in the dielectric layer, wherein the conductive trace comprises a first portion having an exposed top surface, and wherein the exposed top surface is recessed from a top surface of the dielectric layer; anda bump pad over and electrically connected to a second portion of the conductive trace.2. The apparatus of claim 1 , wherein the bump pad and the conductive trace comprise different conductive materials.3. The apparatus of claim 2 , wherein the bump pad comprises nickel or tin claim 2 , and wherein the conductive trace comprises copper.4. The apparatus of claim 1 , wherein the conductive trace is connected to a contact pad in the dielectric layer claim 1 , and wherein the apparatus further comprises a conductive pillar extending from the contact pad through the dielectric layer.5. The apparatus of further comprising:an integrated circuit chip; anda conductive bump physically coupled between the integrated circuit chip and the bump pad.6. The apparatus of claim 5 , wherein there are no conductive bumps physically coupling the integrated circuit chip to the first portion of the conductive trace.7. The apparatus of claim 1 , wherein a top surface of the bump pad is substantially level with the top surface of the dielectric layer.8. A device comprising:a substrate;a dielectric layer over the substrate;a conductive trace in the dielectric layer and comprising a first material; anda bump pad over and electrically coupled to a first portion of the conductive trace, wherein the bump pad comprises a second material ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF

A semiconductor device includes a board having a solder resist layer with first and second openings on a first surface, and a first electrode on the first surface, a portion thereof exposed in the first opening and electrically connected to the board. A second electrode is located on the first surface having a portion exposed in the second opening and electrically connected to the board. A portion of the second electrode is covered by the solder resist layer. A first solder bump is on the first electrode and covers a side surface. A second solder bump is on the second electrode. A semiconductor chip has a first region and a second region facing the first surface. A third electrode is in the first region and electrically connected to the first solder bump. A fourth electrode is in the second region and electrically connected to the second solder bump. 1. A semiconductor device , comprising:a board having a first surface;a solder resist layer on the first surface, the solder resist layer comprising a first opening and a second opening;a first electrode on the first surface and having a side surface exposed in the first opening, the first electrode electrically connected to the board;a second electrode, having an outer perimeter, on the first surface, wherein the second electrode electrically connected to the board and at least a portion of the outer perimeter of the second electrode covered by the solder resist layer;a first solder hump on the first electrode, the first solder bump covering the side surface of the first electrode;a second solder bump on the second electrode; anda semiconductor chip comprising a second surface facing the first surface, the second surface comprising a first region and a second region, wherein a third electrode in the first region of the semiconductor chip is electrically connected to the first solder bump, and a fourth electrode in the second region of the semiconductor chip is electrically connected to the second solder bump, ...

CIRCUIT SUBSTRATE, SEMICONDUCTOR PACKAGE AND PROCESS FOR FABRICATING THE SAME

A circuit substrate has the following elements. A stacked circuit structure has a first surface and a second surface opposite thereto surface. A first patterned inner conductive layer is disposed on the first surface and has multiple pads. A first patterned outer conductive layer is disposed on the patterned inner conductive layer and has multiple conductive pillars, wherein each of the first conductive pillar is located on the corresponding first pad. The first dielectric layer covers the first surface, the first patterned inner conductive layer and the first patterned outer conductive layer, and has multiple first concaves, wherein the first concave exposes the top and side of the corresponding first conductive pillar. A semiconductor package structure applied the above circuit substrate and a process for fabricating the same are also provided here. 1. A circuit substrate , comprising:a stacked circuit structure having a first surface and a second surface opposite to the first surface;a first patterned inner conductive layer disposed on the first surface and having a plurality of first pads;a first patterned outer conductive layer disposed on the first patterned inner conductive layer and having a plurality of first conductive pillars, wherein each of the first conductive pillars is located on the corresponding first pad;a first dielectric layer covering the first surface, the first patterned inner conductive layer and the first patterned outer conductive layer and having a plurality of first concaves, wherein each of the first concaves exposes a top and a side of the corresponding first conductive pillar, and the top and the side of the first conductive pillar are exposed for directly soldering a chip;a second patterned inner conductive layer disposed on the second surface and having a plurality of second pads;a second patterned outer conductive layer disposed on the second patterned inner conductive layer and having a plurality of second conductive pillars, ...

TRANSIENT ELECTRONIC DEVICE WITH ION-EXCHANGED GLASS TREATED INTERPOSER

A transient electronic device utilizes a glass-based interposer that is treated using ion-exchange processing to increase its fragility, and includes a trigger device operably mounted on a surface thereof. An integrated circuit (IC) die is then bonded to the interposer, and the interposer is mounted to a package structure where it serves, under normal operating conditions, to operably connect the IC die to the package I/O pins/balls. During a transient event (e.g., when unauthorized tampering is detected), a trigger signal is transmitted to the trigger device, causing the trigger device to generate an initial fracture force that is applied onto the glass-based interposer substrate. The interposer is configured such that the initial fracture force propagates through the glass-based interposer substrate with sufficient energy to both entirely powderize the interposer, and to transfer to the IC die, whereby the IC die also powderizes (i.e., visually disappears). 114-. (canceled)15. A transient device comprising:an integrated circuit (IC) die including a semiconductor substrate having an electronic circuit formed thereon, and IC contact pads disposed in a first pattern on a surface of the semiconductor substrate, the IC contact pads being operably coupled to the electronic circuit;a package structure including a package substrate, a plurality of first package contact structures disposed in a second pattern on a first surface thereof, a plurality of second package contact structures disposed on a second surface thereof, and a plurality of package conductors extending through the package structure between the first and second surfaces such that each package conductor forms an electrical path between an associated first package contact structure and an associated second package contact structure;an interposer comprising a glass substrate including a plurality of first contact points disposed in the first pattern on a first surface thereof, a plurality of second contact ...

SEMICONDUCTOR PACKAGE STRUCTURE FOR IMPROVING DIE WARPAGE AND MANUFACTURING METHOD THEREOF

A semiconductor die package includes a semiconductor die, a film for improving die warpage bonded to a first face of the semiconductor die, a plurality of electrically conductive bumps formed on a second face of the semiconductor die, a substrate onto which the electrically conductive bumps of the second face of the semiconductor die are bonded to electrically connect the semiconductor die and the substrate, and a mold compound applied these components to form an exposed surface of the semiconductor die package that is coplanar with an exposed surface of the film. 1. A semiconductor die package comprising:a semiconductor die having a first face and a second face opposite the first face;a film for improving warpage of the semiconductor die, the film having a first surface and a second surface opposite the first surface, the first surface of the film bonded to and covering the first face of the semiconductor die;a plurality of electrically conductive bumps formed on the second face of the semiconductor die;a substrate onto which the semiconductor die is bonded using the plurality of electrically conductive bumps that electrically interconnect the semiconductor die and the substrate; anda mold compound surrounding edges of the film and edges of the semiconductor die, and covering the substrate.2. The semiconductor die package structure according to claim 1 , wherein the film for improving die warpage is a single-layer claim 1 , self-adhesive film.3. The semiconductor die package according to claim 1 , wherein the second face of the semiconductor die comprises one or more circuit elements electrically connected to the plurality of electrically conductive bumps.4. The semiconductor die package according to claim 1 , wherein the film for improving die warpage has a thickness in a range of 10 μm to 100 μm.5. The semiconductor die package according to claim 1 , wherein the plurality of electrically conductive bumps comprise a solder.6. The semiconductor die package ...

Semiconductor Die Package and Method of Manufacture

In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.

Semiconductor package including a rewiring layer with an embedded chip

A semiconductor package includes a substrate, a rewiring layer, a plurality of semiconductor chip stack structures, and a second semiconductor chip. The rewiring layer is disposed on an upper surface of the substrate. The rewiring layer includes a concave portion. The semiconductor chip stack structures include a plurality of first semiconductor chips. The first semiconductor chips are disposed on the rewiring layer. The first semiconductor chips are spaced apart from each other in a horizontal direction. The second semiconductor chip is disposed within the concave portion. The second semiconductor chip is configured to electrically connect each of the plurality of semiconductor chip stack structures to each other.

PRINTED CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

A printed circuit board (PCB) includes a substrate base including at least two chip attach regions spaced apart from one another, a plurality of upper pads disposed in the at least two chip attach regions of the substrate base, an accommodation cavity overlapping a part of each of the at least two chip attach regions and recessed in an upper surface of the substrate base, and at least one spacing groove recessed in the upper surface of the substrate base. The at least one spacing groove is connected to the accommodation cavity, and extends in a region between the at least two chip attach regions. 1. A printed circuit board (PCB) , comprising:a substrate base comprising at least two chip attach regions spaced apart from one another,a plurality of upper pads disposed in the at least two chip attach regions of the substrate base;an accommodation cavity overlapping a part of each of the at least two chip attach regions, wherein the accommodation cavity is recessed in an upper surface of the substrate base; andat least one spacing groove recessed in the upper surface of the substrate base, wherein the at least one spacing groove is connected to the accommodation cavity, and extends in a region between the at least two chip attach regions.2. The PCB of claim 1 , wherein the at least two chip attach regions are spaced apart from one another in a first direction claim 1 , and the at least one spacing groove extends in a second direction substantially perpendicular to the first direction.3. The PCB of claim 2 , wherein the at least one spacing groove comprises a first spacing groove and a second spacing groove that respectively extend from opposite sides of the accommodation cavity in the second direction.4. The PCB of claim 3 , wherein a length of the first spacing groove is about equal to a length of the second spacing groove.5. The PCB of claim 3 , wherein a length of the first spacing groove is different from a length of the second spacing groove.6. The PCB of claim 1 , ...

PRINTED REPASSIVATION FOR WAFER CHIP SCALE PACKAGING

Described examples provide integrated circuits and methods, including forming a conductive seed layer at least partially above a conductive feature of a wafer, forming a conductive structure on at least a portion of the conductive seed layer, performing a printing process that forms a polymer material on a side of the wafer proximate a side of the conductive structure, curing the deposited polymer material, and attaching a solder ball structure to a side of the conductive structure. 1. A method , comprising:forming a conductive seed layer at least partially above a conductive feature of a wafer;forming a conductive structure on at least a portion of the conductive seed layer;performing a printing process that forms a polymer material on a side of the wafer proximate a side of the conductive structure;curing the deposited polymer material; andattaching a solder ball structure to a side of the conductive structure.2. The method of claim 1 , wherein performing the printing process includes performing multiple printing passes to deposit multiple layers of the polymer material proximate the side of the conductive structure.3. The method of claim 2 , wherein curing the deposited polymer material includes:heating the wafer while performing the printing process to at least partially cure the polymer material.4. The method of claim 3 , wherein curing the deposited polymer material further includes:after performing the printing process, performing a final curing process that thermally cures the polymer material.5. The method of claim 2 , wherein curing the deposited polymer material includes:exposing the polymer material to ultraviolet light while performing the printing process to at least partially cure the polymer material.6. The method of claim 5 , wherein curing the deposited polymer material further includes:after performing the printing process, performing a final curing process that UV cures the polymer material.7. The method of claim 1 , further comprising:after ...

ELECTRONIC APPARATUS AND METHOD FOR FABRICATING THE SAME

An electronic apparatus includes a first electronic part with a first terminal, a second electronic part with a second terminal opposite the first terminal, and a joining portion which joins the first terminal and the second terminal. The joining portion contains a pole-like compound extending in a direction in which the first terminal and the second terminal are opposite to each other. The joining portion contains the pole-like compound, so the strength of the joining portion is improved. When the first terminal and the second terminal are joined, the temperature of one of the first electronic part and the second electronic part is made higher than that of the other. A joining material is cooled and solidified in this state. By doing so, the pole-like compound is formed. 1. An electronic apparatus comprising:a first electronic part with a first terminal;a second electronic part with a second terminal opposite the first terminal; anda joining portion that joins the first terminal and the second terminal,wherein the joining portion that includes an intermetallic compound containing a first metallic element and a second metallic element different from the first metallic element, and a portion containing at least the first metallic element and the second metallic element, the intermetallic compound extending in a direction in which the first terminal and the second terminal are opposite to each other, the portion being around the intermetallic compound.2. The electronic apparatus according to claim 1 , wherein the first metallic element is Sn.3. The electronic apparatus according to claim 1 , wherein the second metallic element is one of Au claim 1 , Ag claim 1 , Cu claim 1 , Ni claim 1 , and Pd.4. The electronic apparatus according to claim 3 , wherein the intermetallic compound is pole-shaped. This application is a continuation of application Ser. No. 15/142,690, filed Apr. 29, 2016, which is a continuation of Ser. No. 14/532,032, filed Nov. 4, 2014, which is based ...

RELIABILITY TESTING METHOD

Disclosed is a chip reliability testing method that includes mounting a test chip on a test board whereby each test circuit of the test chip is connected to a different pair of input and output terminals. The reliability test can include applying a test voltage to a first (input) bump and measuring an output voltage on a second (output) bump connected to the same test circuit. The first and second bumps are, in turn, electrically connected to each other through a series of conductive materials to define the test circuit. The conductive materials include first and second contact pads under the first and second bumps with the contact pads, in turn, being connected to a conductive substrate or redistribution layer. The conductive substrate or redistribution layer is, in turn, connected to first and second conductive vias that each provide a connection to one or more of a series of conductive layers that are arranged under the conductive substrate or redistribution layer and over a silicon device. A series of dielectric layers are provided between the conductive substrate or redistribution layer, the conductive layers, and the silicon device. 1. A chip reliability testing method , comprising:mounting a test chip, comprising a plurality of test circuits, on a test board, wherein mounting the test chip includes connecting each test circuit of the plurality of test circuits to a different pair of input and output terminals on the test board; andsubjecting the test chip to a reliability test, wherein subjecting the test chip to a reliability test includes applying a test voltage to a first bump of the test circuit; and a first contact pad connected to the first bump;', 'a second contact pad connected to the second bump,', 'a first conductive via connected, through a conductive substrate or redistribution layer, to the first contact pad,', 'a second conductive via connected, through the conductive substrate or redistribution layer, to the second contact pad, wherein the ...

NICKEL-TIN MICROBUMP STRUCTURES AND METHOD OF MAKING SAME

Techniques and mechanisms for providing effective connectivity with surface level microbumps on an integrated circuit package substrate. In an embodiment, different metals are variously electroplated to form a microbump which extends through a surface-level dielectric of a substrate to a seed layer including copper. The microbump includes nickel and tin, wherein the nickel aids in mitigating an absorption of seed layer copper. In another embodiment, the microbump has a mass fraction of tin, or a mass fraction of nickel, that is different in various regions along a height of the microbump. 1. An integrated circuit (IC) package substrate , comprising:a dielectric layer having via holes formed therein;a sub-surface-level metal layer including copper contacts each exposed to a respective one of the via holes, the copper contacts including a first copper contact;a first seed layer deposited on the first copper contact, the first seed layer including copper which adjoins the first copper contact; anda first microbump formed on the first seed layer, the first microbump including tin and nickel.2. The IC package substrate of claim 1 , wherein the nickel of the microbump is disposed directly on the copper seed layer.3. The IC package substrate of claim 1 , wherein a bottom 10% of a volume of the first microbump has a first tin mass fraction claim 1 , wherein a top 10% of a volume of the first microbump has a second tin mass fraction and wherein the second tin mass fraction differs from the first tin mass fraction by at least 5% of the first tin mass fraction.4. The IC package substrate of claim 3 , wherein the second tin mass fraction differs from the first tin mass fraction by at least 10% of the first tin mass fraction.5. The IC package substrate of claim 1 , wherein a total volume of tin of the first microbump is equal to at least 75% of a total volume of nickel of the first microbump.6. The IC package substrate of claim 1 , wherein a total tin mass fraction of the first ...

INTERCONNECTION STRUCTURE OF A SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE INTERCONNECTION STRUCTURE

An interconnection structure of a semiconductor chip may include an interconnection via, a lower pad, a conductive bump, and an upper pad. The interconnection via may be arranged in the semiconductor chip. The lower pad may be arranged on a lower end of the interconnection via exposed through a lower surface of the semiconductor chip. The conductive bump may be arranged on the lower pad. The upper pad may be arranged on an upper end of the interconnection via exposed through an upper surface of the semiconductor chip. The upper pad may have a width wider than a width of the interconnection via and narrower than a width of the lower pad. Thus, an electrical short between the conductive bumps may not be generated in the interconnection structure having a thin thickness. 1. An interconnection structure of a semiconductor chip , the interconnection structure comprising:an interconnection via arranged in the semiconductor chip;a lower pad arranged on a lower end of the interconnection via exposed through a lower surface of the semiconductor chip;a conductive bump arranged on the lower pad; andan upper pad including a body pad arranged on an upper end of the interconnection via exposed through an upper surface of the semiconductor chip, and an interconnection pad arranged on an upper surface of the body pad,wherein the body pad has a width substantially the same as a width of the lower pad, and the interconnection pad has a width wider than a width of the interconnection via and narrower than the width of the lower pad.2. The interconnection structure of claim 1 , wherein the interconnection pad is positioned on a central portion of the upper surface of the body pad.3. The interconnection structure of claim 1 , wherein the interconnection pad is arranged on an upper surface and a side surface of the body pad.4. The interconnection structure of claim 1 , wherein the width of the lower pad is about 15 μm to about 20 μm claim 1 , the width of the interconnection via is about ...

PACKAGED SEMICONDUCTOR DEVICES FOR HIGH VOLTAGE WITH DIE EDGE PROTECTION

In a described example a device includes: a first corner formed between a circuit side surface of a semiconductor die and a first sidewall formed with a first depth extending along a side of the semiconductor die from the circuit side surface; a ledge having a planar surface formed parallel to the circuit side surface of the semiconductor die formed at the first depth from the circuit side surface at the first corner, and being perpendicular to the first sidewall; a second corner formed by an intersection of the planar surface of the ledge and a scribe lane sidewall of the semiconductor die, forming a second sidewall perpendicular to the circuit side surface; and portions of the circuit side surface of the semiconductor die, the first corner, the first sidewall, and the planar surface of the ledge covered by a passivation layer. 1. A device , comprising:a first corner formed between a circuit side surface of a semiconductor die and a first sidewall formed with a first depth extending along a side of the semiconductor die from the circuit side surface;a ledge having a planar surface formed parallel to the circuit side surface of the semiconductor die formed at the first depth from the circuit side surface at the first corner, and being perpendicular to the first sidewall;a second corner formed by an intersection of the planar surface of the ledge and a scribe lane sidewall of the semiconductor die, forming a second sidewall perpendicular to the circuit side surface; andportions of the circuit side surface of the semiconductor die, the first corner, the first sidewall, and the planar surface of the ledge covered by a passivation layer.2. The device of claim 1 , wherein a thickness of the passivation layer is at least 10 μm.3. The device of claim 1 , wherein the passivation layer is a material that is one selected from a group consisting essentially of: silicon dioxide claim 1 , silicon nitride claim 1 , silicon oxynitride claim 1 , polyimide claim 1 , and combinations ...

ELECTRONIC PACKAGE COVER HAVING UNDERSIDE RIB

An electronic package lid which includes one or more underside ribs. The ribs have a major length and a minor width and are generally aligned to be parallel with a diagonal or normal bisector of the processing device. The underside rib generally stiffens the cover such that an upper surface of the cover is more apt to stay flat. As such, cover warpage and, therefore, the peeling of the TIM1 and delamination of underfill due to the physical or dimensional expansion of the processing device and/or a carrier may be reduced. As a result, the surface area dedicated for the seal material upon the carrier surface may be reduced, thereby increasing the available surface area upon the carrier for additional electronic components to be placed in close proximity to the processing device. 1. A electronic package comprising:a processing device electrically connected to a carrier, the processing device comprising a diagonal bisector that travels through a center of the processing device and at least one corner of the processing device;a seal band upon the carrier; anda cover having a perimeter bottom surface connected to the carrier via the seal band, the cover comprising an underside rib having a major length and minor width, wherein the underside rib is positioned upon the cover such that the major length is parallel with the diagonal bisector and an inner end surface of the underside rib contacts a corner of the processing device, wherein the perimeter bottom surface of the cover and an underside rib surface are coplanar, and wherein the inner end surface is orthogonal to the underside rib surface.2. The electronic package of claim 1 , wherein the underside rib surface and the perimeter bottom surface are integral and coplanar.3. The electronic package of claim 1 , wherein the processing device is electrically connected to the carrier.4. The electronic package of claim 1 , further comprising underfill material between the processing device and the carrier.5. The electronic ...

ELECTRONIC PACKAGE COVER HAVING UNDERSIDE RIB

An electronic package lid which includes one or more underside ribs. The ribs have a major length and a minor width and are generally aligned to be parallel with a diagonal or normal bisector of the processing device. The underside rib generally stiffens the cover such that an upper surface of the cover is more apt to stay flat. As such, cover warpage and, therefore, the peeling of the TIM1 and delamination of underfill due to the physical or dimensional expansion of the processing device and/or a carrier may be reduced. As a result, the surface area dedicated for the seal material upon the carrier surface may be reduced, thereby increasing the available surface area upon the carrier for additional electronic components to be placed in close proximity to the processing device. 1. A electronic package comprising:a processing device electrically connected to a carrier, the processing device comprising a normal bisector along a center of the processing device and midpoint of an edge of a sidewall of the processing device;a seal band upon the carrier; anda cover having a perimeter bottom surface connected to the carrier via the seal band, the cover comprising an underside rib having a major length and minor width, wherein the underside rib is positioned upon the cover such that the major length is parallel with the normal bisector and an inner end surface of the underside rib contacts the sidewall of the processing device, wherein the perimeter bottom surface of the cover and an underside rib surface are coplanar, and wherein the inner end surface is orthogonal to the underside rib surface.2. The electronic package of claim 1 , wherein the underside rib surface and the perimeter bottom surface are integral and coplanar.3. An electronic package fabrication method comprising:positioning a cover comprising an underside rib against a carrier such that a major length of the underside rib is parallel with a normal bisector of a processing device electrically connected to the ...

Transient Electronic Device With ION-Exchanged Glass Treated Interposer

A transient electronic device utilizes a glass-based interposer that is treated using ion-exchange processing to increase its fragility, and includes a trigger device operably mounted on a surface thereof. An integrated circuit (IC) die is then bonded to the interposer, and the interposer is mounted to a package structure where it serves, under normal operating conditions, to operably connect the IC die to the package I/O pins/balls. During a transient event (e.g., when unauthorized tampering is detected), a trigger signal is transmitted to the trigger device, causing the trigger device to generate an initial fracture force that is applied onto the glass-based interposer substrate. The interposer is configured such that the initial fracture force propagates through the glass-based interposer substrate with sufficient energy to both entirely powderize the interposer, and to transfer to the IC die, whereby the IC die also powderizes (i.e., visually disappears). 1. A transient electronic device comprising:an integrated circuit (IC) die including a semiconductor substrate having an electronic circuit formed thereon, and IC contact pads disposed in a first pattern on a surface of the semiconductor substrate, said IC contact pads being operably coupled to said electronic circuit;a package structure including a package substrate, a plurality of first package contact structures disposed in a second pattern on a first surface thereof, a plurality of second package contact structures disposed on a second surface thereof, and a plurality of package conductors extending through the package structure between the first and second surfaces such that each said package conductor forms an electrical path between an associated first package contact structure and an associated second package contact structure;an interposer comprising a glass substrate including a plurality of first contact points disposed in the first pattern on a first surface thereof, a plurality of second contact ...

SEMICONDUCTOR DEVICE PACKAGES AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device package includes a carrier, a patterned passivation layer and a first patterned conductive layer. The patterned passivation layer is disposed on the carrier. The first patterned conductive layer is disposed on the carrier and surrounded by the patterned passivation layer. The first patterned conductive layer has a first portion and a second portion electrically disconnected from the first portion. The first portion has a first surface adjacent to the carrier and exposed by the patterned passivation layer. The second portion has a first surface adjacent to the carrier exposed by the patterned passivation layer. The first surface of the first portion is in direct contact with an insulation medium. 1. A semiconductor device package , comprising:a carrier;a patterned passivation layer disposed on the carrier; anda first patterned conductive layer disposed on the carrier and surrounded by the patterned passivation layer, the first patterned conductive layer having a first portion and a second portion electrically disconnected from the first portion, the first portion having a first surface adjacent to the carrier and exposed by the patterned passivation layer, and the second portion having a first surface adjacent to the carrier exposed by the patterned passivation layer;wherein the first surface of the first portion is in direct contact with an insulation medium, wherein the insulation medium comprises an insulation layer, and wherein the insulation layer comprises a pattern of grid.2. The semiconductor device package of claim 1 , wherein the first surface of the second portion is in direct contact with the insulation medium.3. (canceled)4. The semiconductor device package of claim 1 , wherein the insulation layer is disposed between the carrier and the first portion of the first patterned conductive layer.5. The semiconductor device package of claim 1 , wherein the insulation layer is disposed between the carrier and the second portion of the ...

RELIABILITY TESTING METHOD AND APPARATUS

A chip reliability testing method includes mounting a first test chip on a test board, wherein the first test chip comprises a silicon device having a plurality of metallization layers configured to establish a plurality of test circuits, a conductive redistribution layer contacting at least one of the plurality of metallization layers, and contact pads on exposed portions of the conductive redistribution layer. The mounting includes bonding the contact pads of the first test chip to corresponding contact pads of the test board. The method further includes applying a test voltage to a first contact pad connected to a first test circuit of the plurality of test circuits and, while maintaining the test voltage, subjecting the first test circuit to a reliability test. The method further includes monitoring an output voltage at a second contact pad connected to the first test circuit during a test period during the reliability test. 1. A chip reliability testing method , comprising: 'bonding the contact pads of the first test chip to corresponding contact pads of the test board;', 'mounting a first test chip on a test board, wherein the first test chip comprises a silicon device having a plurality of metallization layers configured to establish a plurality of test circuits, a conductive redistribution layer contacting at least one of the plurality of metallization layers, and contact pads on exposed portions of the conductive redistribution layer, and the mounting includesapplying a test voltage to a first contact pad connected to a first test circuit of the plurality of test circuits and, while maintaining the test voltage, subjecting the first test circuit to a reliability test; andmonitoring an output voltage at a second contact pad connected to the first test circuit during a test period encompassing predetermined portions of the reliability test.2. The method of claim 1 , wherein subjecting the first test circuit to the reliability test comprises subjecting the ...

Thermocompression bonding of electronic components

A method for producing an electronic module includes providing a first substrate including at least one first electrical contacting surface, an electronic component including at least one second electrical contacting surface, and a first material layer made of a thermoplastic material including at least one recess extending through the material layer. The first substrate, the electronic component and the first material layer are arranged with the first material layer disposed between the first substrate and the electronic component, and the at least one first electrical contacting surface, the at least one second electrical contacting surface and the at least one recess aligned relative to one another. The first substrate, the electronic component and the material layer are thermocompression bonded. A joint formed between the at least one first electrical contacting surface and the at least one second electrical contacting surface is surrounded or enclosed by the first material layer.

WIRING SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

A wiring substrate includes an insulating layer, at least one via hole formed in the insulating layer, a first wiring layer formed on one surface of the insulating layer and having a droop portion at an end-side of the via hole, a second wiring layer formed on the other surface of the insulating layer, and a metal-plated layer formed in the via hole and configured to connect the second wiring layer and the droop portion of the first wiring layer. One surface of the insulating layer around the via hole is formed as a convex curved surface and the droop portion of the first wiring layer is arranged on the convex curved surface. 1. A wiring substrate comprising:an insulating layer;at least one via hole formed in the insulating layer;a first wiring layer formed on one surface of the insulating layer and having a droop portion at an end-side of the via hole;a second wiring layer formed on the other surface of the insulating layer; anda metal-plated layer formed in the via hole and configured to connect the second wiring layer and the droop portion of the first wiring layer,wherein one surface of the insulating layer around the via hole is formed as a convex curved surface and the droop portion of the first wiring layer is arranged on the convex curved surface.2. The wiring substrate according to claim 1 , wherein the droop portion of the first wiring layer is configured to cover a side surface of the via hole.3. The wiring substrate according to claim 2 , wherein a length of the droop portion of the first wiring layer is different in at least two positions of the via hole.4. The wiring substrate according to claim 2 , wherein a plurality of the via holes are formed in the insulating layer claim 2 , and lengths of the droop portions of the first wiring layer are different between the plurality of the via holes. The present application claims priority from Japanese Patent Application No. 2015-205242 filed on Oct. 19, 2015, the entire content of which is incorporated herein ...

SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor package device includes a substrate, a passive component, an active component and a package body. The passive component is disposed on the substrate. The active component is disposed on the substrate. The package body is disposed on the substrate. The package body includes a first portion covering the active component and the passive component, and a second portion covering the passive component. A top surface of the second portion of the package body is higher than a top surface of the first portion of the package body. 1. A semiconductor package device comprising:a substrate;a passive component disposed on the substrate;an active component disposed on the substrate; anda package body disposed on the substrate, the package body comprising a first portion covering the active component and the passive component, and a second portion covering the passive component, wherein a top surface of the second portion of the package body is higher than a top surface of the first portion of the package body.2. The semiconductor package device according to claim 1 , further comprising a conductive layer disposed on the package body.3. The semiconductor package device according to claim 1 , wherein the top surface of the first portion of the package body is aligned with a backside surface of the active component.4. The semiconductor package device according to claim 1 , wherein the top surface of the first portion of the package body is aligned with a backside surface of the passive component.5. The semiconductor package device according to claim 1 , wherein the second portion of the package body comprises a cured photosensitive material.6. The semiconductor package device according to claim 1 , wherein an area of the second portion of the package body is larger than an area of the passive component.7. The semiconductor package device according to claim 1 , wherein a distance from the top surface of the second portion of the package body to a backside surface of ...

Method for Forming Chip Packages and a Chip Package

The present application provides a method for forming chip packages and a chip package. The method comprises arranging a plurality of interconnect devices at intervals on a surface of a carrier and assembling a plurality of chipsets over the interconnect devices. Each chipset comprises at least two chips electrically connected through an interconnect device. A front surface of each chip facing the carrier is provided with a plurality of first bumps. The method further comprises forming a molded package layer whereby the plurality of chipsets and the plurality of interconnect devices are embedded in the molded package layer; removing the carrier and thinning the molded package layer to expose the first bumps; forming second bumps on the surface on one side of the molded package layer where the first bumps are exposed; and dicing the molded package layer to obtain a plurality of package units. Thus, a flexible and low-cost packaging scheme is provided for multi-chip interconnection. 1. A method of forming a package , comprising:arranging a plurality of interconnect devices at intervals on a surface of a carrier, each interconnect device having a first side facing away from the carrier;assembling a plurality of chipsets over the plurality of interconnect devices, wherein each chipset includes at least two chips that are jointed by a corresponding interconnect device on the first side of the corresponding interconnect device whereby the at least two chips are electrically interconnected through the corresponding interconnect device, and wherein a front surface of each chip in each chipset faces the carrier and is provided with a plurality of first bumps;forming a molded package layer around the plurality of chipsets, wherein the plurality of chipsets and the plurality of interconnect devices are embedded in the molded package layer;removing the carrier and thinning the molded package layer to expose some of the plurality of first bumps;forming a second bump on the ...

Chip Interconnecting Method, Interconnect Device and Method for Forming Chip Packages

The present disclosure provides a chip interconnecting method, an interconnect device and a method for forming a chip interconnection package. The method comprises arranging at least one chipset on a carrier, each chipset including at least a first chip and a second chip. A contact surface (or diameter) of each of the first bumps is smaller than that of any of the second bumps. The method further comprises attaching an interconnect device to the first chip and the second chip, the interconnect device including first pads for bonding to corresponding bumps on the first chip and second pads for bonding to corresponding bumps on the second chip. Attaching the interconnect device includes aligning the plurality of first pads with the corresponding bumps on the first chip whereby the plurality of second pads are self-aligned for bonding to the plurality of second bumps.

SEMICONDUCTOR DEVICE HAVING PACKAGE ON PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE

A semiconductor device having a package on package (PoP) structure, in which a fine pitch between package substrates is implemented, a total height of a package is reduced, and reliability is enhanced. The semiconductor package includes a first package substrate including a first body layer and a first passivation layer, a first semiconductor chip on the first package substrate, a second package substrate on the first package substrate, the second package substrate including a second body layer and a second passivation layer, a first connection member on the first package substrate outside the first semiconductor chip, and a gap filler filled between the first package substrate and the second package substrate, wherein the first package substrate includes a first trench, the second package substrate includes a second trench, and the first semiconductor chip is disposed between the first trench and the second trench. 1. A semiconductor device having a package on package (PoP) structure comprising:a first package substrate including a first body layer and a first passivation layer on a top surface of the first body layer;a first semiconductor chip mounted on the first package substrate;a second package substrate disposed on the first package substrate and the first semiconductor chip, the second package substrate including a second body layer and a second passivation layer on a bottom surface of the second body layer;a plurality of first connection members disposed on the first package substrate outside the first semiconductor chip to electrically connect the first package substrate to the second package substrate; anda gap filler filled between the first package substrate and the second package substrate and surrounding at least some of portions of the plurality of first connection members,wherein the first package substrate comprises a first trench formed by removing a center portion of the first passivation layer,wherein the second package substrate comprises a ...

FILM FOR SEMICONDUCTOR PACKAGE, SEMICONDUCTOR PACKAGE USING FILM AND DISPLAY DEVICE INCLUDING THE SAME

A semiconductor package may include a first output test pad and a second output test pad disposed on a first surface of an insulating film, and a semiconductor chip disposed between the first output test pad and the second output test pad on a second surface opposing to the first surface of the insulating film. 1. A semiconductor package comprising:a substrate;a semiconductor chip disposed on the substrate;a first via penetrating the substrate;a first pad disposed on a first surface of the substrate;a second pad disposed on a second surface of the substrate;a first lower lead disposed on the first surface of the substrate, and connected to the first pad and to the first via;an upper lead disposed on the second surface of the substrate, and connected to the second pad and to the first via; anda transmission lead disposed on the second surface of the substrate and connected to the first via,wherein the transmission lead extends in a first direction opposite to a second direction in which the upper lead extends.2. The semiconductor package of claim 1 , further comprising a resist layer disposed on the second surface of the substrate claim 1 , and covering the upper lead and the transmission lead.3. The semiconductor package of claim 1 , further comprising a resin layer disposed between the semiconductor chip and the substrate claim 1 , and covering the first pad.4. The semiconductor package of claim 1 , further comprising:a second via penetrating the substrate;a third pad disposed on the first surface of the substrate;a fourth pad disposed on the second surface of the substrate and connected to the second via;a second lower lead connected to the third pad and the second via.5. The semiconductor package of claim 1 , further comprising a bump contacting the first pad.6. The semiconductor package of claim 1 , wherein the first via claim 1 , the transmission lead and the upper lead form a T-shape.7. The semiconductor package of claim 1 , wherein the substrate is a flexible ...

INTEGRATED CIRCUITS (ICs) WITH MULTI-ROW COLUMNAR DIE INTERCONNECTS AND IC PACKAGES INCLUDING HIGH DENSITY DIE-TO-DIE (D2D) INTERCONNECTS

An integrated circuit (IC) package including ICs with multi-row columnar die interconnects has increased die-to-die (D2D) interconnect density in a conductive layer. Positioning the die interconnects in die interconnect column clusters, that each include a plurality of die interconnect rows and two columns, reduces the linear dimension occupied by the die interconnects and leaves room for more D2D interconnects. A die interconnect column cluster pitch is a distance between columns of adjacent die interconnect column clusters and this distance is greater than a die interconnect pitch between columns within the column clusters. Die interconnects may be disposed in the space between the multi-row column clusters and additional die interconnects can be disposed at the D2D interconnect pitch between the die interconnect column clusters. IC packages with ICs including the multi-row columnar die interconnects have a greater number of D2D interconnects for better IC integration. 1. An integrated circuit (IC) die comprising:a substrate; 'a plurality of first die interconnect rows each comprising a first die interconnect spaced apart from a second die interconnect at a row die interconnect pitch; and', 'a first die interconnect column cluster on the substrate, comprising 'a plurality of second die interconnect rows each comprising a first die interconnect spaced apart from a second die interconnect at the row die interconnect pitch;', 'a second die interconnect column cluster on the substrate, comprising 'the second die interconnect in each first die interconnect row of the plurality of first die interconnect rows is adjacent to the first die interconnect in a second die interconnect row of the plurality of second die interconnect rows and is spaced apart from the first die interconnect in the second die interconnect row of the plurality of second die interconnect rows at a column cluster pitch greater than the row die interconnect pitch.', 'wherein2. The IC die of claim 1 , ...

Protrusion Bump Pads for Bond-on-Trace Processing

An embodiment apparatus includes a dielectric layer, a conductive trace in the dielectric layer, and a bump pad. The conductive trace includes a first portion having an exposed top surface, wherein the exposed top surface is recessed from a top surface of the dielectric layer. Furthermore, the bump pad is disposed over and is electrically connected to a second portion of the conductive trace. 1. A device comprising:a substrate;an insulating layer on the substrate;a conductive line in the insulating layer; anda conductive pad in the insulating layer and directly over a first region of the conductive line, wherein the conductive pad has a different material composition than the conductive line, wherein a top surface of the conductive pad is not higher than a top surface of the insulating layer, wherein no portions of the insulating layer and no portions of the conductive pad extend directly over a second region of the conductive line.2. The device of claim 1 , wherein the conductive pad comprises nickel or tin claim 1 , and wherein the conductive line comprises copper.3. The device of claim 1 , wherein the conductive pad is connected to a contact pad through the conductive line claim 1 , wherein the conductive pad is disposed in the insulating layer claim 1 , and wherein the device further comprises a conductive pillar extending from the contact pad through the insulating layer.4. The device of claim 3 , wherein the contact pad and the conductive line have a same material composition.5. The device of claim 3 , wherein a top surface of the contact pad is lower than a top surface of the insulating layer.6. The device of further comprising:an integrated circuit chip; anda solder region physically coupling the integrated circuit chip to the conductive pad.7. The device of claim 1 , wherein a top surface of the conductive pad is substantially level with the top surface of the insulating layer.8. The device of claim 1 , wherein a top surface of the second region of the ...

LED MOUNTING METHOD AND DEVICE

A mounting method and a mounting device for an LED chip are provided. The mounting method includes: providing a circuit substrate; disposing a plurality of conductors on the conductive solder pads; disposing the plurality of LED chips on the circuit substrate; and directing a laser source generated by a laser source generation module to each LED chip, so that the laser source passes through the LED chip and is projected on at least two conductors. The conductor disposed between the LED chip and the circuit substrate is cured by irradiation of the laser source so that the LED chip is mounted on the circuit substrate. Thereby, the conductor can be cured by the irradiation of the laser source passing through the LED chip, so that the LED chip is mounted on the circuit substrate. 1. An LED mounting method , comprising:providing a circuit substrate including a plurality of conductive solder pads;disposing a plurality of LED chips on the circuit substrate, each of the LED chips being disposed on at least two conductors;directing a laser source generated by a laser source generation module to each of the LED chips such that the laser source passes through the LED chip and is projected on at least two of the conductors; andcuring the conductor disposed between the LED chip and the circuit substrate by the laser source such that the LED chip is mounted on the circuit substrate.2. The LED mounting method according to claim 1 , wherein each of the LED chips includes an n-type conductive layer claim 1 , a light-emitting layer through which the laser source passes claim 1 , and a p-type conductive layer that are disposed in a stacked arrangement; the n-type conductive layer is an n-type gallium nitride material layer or an n-type gallium arsenide material layer claim 1 , the light-emitting layer is a multi-quantum well structure layer claim 1 , and the p-type conductive layer is a p-type gallium nitride material layer or a p-type gallium arsenide material layer; wherein the ...

SEMICONDUCTOR CHIP, METHOD OF MANUFACTURING THE SEMICONDUCTOR CHIP, AND SEMICONDUCTOR PACKAGE AND DISPLAY APPARATUS INCLUDING THE SEMICONDUCTOR CHIP

A semiconductor chip having an improved structure without an investment in photolithography equipment, a method of manufacturing the semiconductor chip, and a semiconductor package and a display apparatus which include the semiconductor chip are described. The semiconductor chip includes a circuit region disposed in a central part of a rectangle that is elongated in a first direction. The circuit region includes a plurality of driving circuit cells disposed at predetermined intervals in the first direction. A plurality of electrode pads is disposed around the circuit region, and a process pattern is disposed at at least one of the four sides of the rectangle. 1. A semiconductor chip comprising:a circuit region disposed in a central part of a rectangle that is elongated in a first direction, the circuit region comprising a plurality of driving circuit cells disposed at predetermined intervals in the first direction;a plurality of electrode pads disposed around the circuit region; anda process pattern disposed at at least one of four sides of the rectangle.2. The semiconductor chip of claim 1 , wherein the rectangle comprises long sides having a greater length than short sides thereof claim 1 , and wherein an entirety of the process pattern is disposed at one of the short sides of the rectangle.3. (canceled)4. The semiconductor chip of claim 1 , wherein the rectangle comprises long sides having a greater length than short sides thereof claim 1 , and wherein a portion of the process pattern is disposed at at least one of the long sides of the rectangle.5. (canceled)6. The semiconductor chip of claim 1 , wherein the semiconductor chip is one of a plurality of chips separated from a wafer claim 1 ,wherein an entirety of the process pattern is disposed in the semiconductor chip, or a portion of the process pattern is disposed in a scribe lane of the wafer and another portion of the process pattern is disposed in the semiconductor chip, andwherein a width of the process ...

SEMICONDUCTOR ELEMENT MOUNTING BOARD

A semiconductor element mounting board includes: a circuit conductor disposed on the insulating board, a plurality of semiconductor element connection pads connected to the circuit conductor, a semiconductor element mounted on a surface of the insulating board, a first capacitor and a second capacitor disposed on a surface or an inside of the insulating board, and a first conductor path configured to connect the first capacitor between the semiconductor element connection pads, and a second conductor path configured to connect the second capacitor between the semiconductor element connection pads; and an inductance of the first conductor path is smaller than an inductance of the second conductor path, and capacitance of the first capacitor is smaller than capacitance of the second capacitor, and an internal inductance of the first capacitor is smaller than an internal inductance of the second capacitor. 1. A semiconductor element mounting board comprising:an insulating board including a laminated structure where a plurality of insulating layers are laminated;a circuit conductor disposed on a surface and an inside of the insulating board;a plurality of semiconductor element connection pads disposed on the surface of the insulating board and connected to a part of the circuit conductor;a semiconductor element mounted on the surface of the insulating board through the semiconductor element connection pads;a first capacitor and a second capacitor that suppresses current fluctuation to the semiconductor element and are disposed on the surface or the inside of the insulating board;a first conductor path, including a part of the circuit conductor, that electrically connects the first capacitor to predetermined semiconductor element connection pads; anda second conductor path, including a part of the circuit conductor, that electrically connects the second capacitor to the predetermined semiconductor element connection pads in parallel with the first capacitor,wherein an ...

Multi-chip package structure having high density chip interconnect bridge with embedded power distribution network

A multi-chip package structure includes a package substrate, an interconnect bridge device, first and second integrated circuit chips, and a connection structure. The first integrated circuit chip is flip-chip attached to at least the interconnect bridge device. The second integrated circuit chip is flip-chip attached to the interconnect bridge device and to the package substrate. The interconnect bridge device includes (i) wiring that is configured to provide chip-to-chip connections between the first and second integrated circuit chips and (ii) an embedded power distribution network that is configured to distribute at least one of a positive power supply voltage and a negative power supply voltage to at least one of the first and second integrated circuit chips attached to the interconnect bridge device. The connection structure (e.g., wire bond, injection molded solder, etc.) connects the embedded power distribution network to a power supply voltage contact of the package substrate.

SENSOR SYSTEMS AND METHODS FOR PROVIDING SENSOR SYSTEMS

A sensor assembly includes a die substrate and a metalized layer formed on the die substrate. The metalized layer is formed of a first metal material and includes a bonding pad to facilitate electrically coupling the sensor assembly to a sensor system. A re-metalized bump is formed on the bonding pad of a second metal material and is electrically coupled to the metalized layer. An adhesive is applied to the re-metalized bump and facilitates mechanically coupling the sensor assembly to the sensor system. 1. A sensor assembly comprising:a die substrate;a metalized layer formed on said die substrate, said metalized layer formed of a first metal material and comprising a bonding pad to facilitate electrically coupling said sensor assembly to a sensor system;a re-metalized bump formed on said bonding pad, said re-metalized bump formed of a second metal material and electrically coupled to said metalized layer; andan adhesive applied to said re-metalized bump, wherein said adhesive facilitates mechanically coupling said sensor assembly to the sensor system.2. The sensor assembly of claim 1 , wherein said adhesive comprises at least one of a non-conductive adhesive and an anisotropic conductive adhesive layer claim 1 , said adhesive formed of at least one of a film claim 1 , a liquid claim 1 , and a paste.3. The sensor assembly of claim 1 , wherein said adhesive comprises a conductive adhesive.4. The sensor assembly of further comprising a lid coupled to said die substrate claim 1 , said lid substantially covering said die substrate and exposing said bonding pad.5. The sensor assembly of claim 1 , wherein said metalized layer comprises an oxidized surface layer covering the first metal material claim 1 , and wherein said re-metalized bump extends from the first metal material through the oxidized surface layer.6. The sensor assembly of claim 1 , wherein the first metal material is aluminum claim 1 , and wherein the second metal material is at least one of aluminum claim 1 ...

ELECTRONIC CIRCUIT PACKAGE HAVING HIGH COMPOSITE SHIELDING EFFECT

Disclosed herein is an electronic circuit package includes: a substrate having a power supply pattern; an electronic component mounted on a surface of the substrate; a magnetic mold resin that covers the surface of the substrate so as to embed the electronic component therein, the magnetic mold resin comprising a composite magnetic material containing a thermosetting resin material and a magnetic filler; and a laminated film including at least a metal film and a magnetic film, the laminated film covering at least an top surface of the magnetic mold resin. The metal film is connected to the power supply pattern, and the magnetic film has a higher effective permeability than that of the magnetic mold resin. 1. An electronic circuit package comprising:a substrate having a side surface and a power supply pattern exposed to the side surface;an electronic component mounted on a surface of the substrate;a magnetic mold resin that covers the surface of the substrate so as to embed the electronic component therein, the magnetic mold resin comprising a composite magnetic material containing a thermosetting resin material and a magnetic filler; anda laminated film including at least a metal film and a magnetic film, the laminated film covering at least a top surface of the magnetic mold resin,wherein the metal film of the laminated film extends over the side surface of the substrate in such a manner as to cover and connect to the power supply pattern exposed to the side surface of the substrate, without an intervention of the magnetic film,wherein the magnetic film has a higher effective permeability than that of the magnetic mold resin.2. The electronic circuit package as claimed in claim 1 , wherein the laminated film further covers a side surface of the magnetic mold resin.3. The electronic circuit package as claimed in claim 1 , wherein the magnetic film is positioned between the magnetic mold resin and the metal film.4. The electronic circuit package as claimed in claim 1 ...

CIRCUIT SUBSTRATE AND PACKAGE STRUCTURE

The invention provides a circuit substrate and a package structure. The circuit substrate includes a molding compound having a chip-side surface and a solder ball-side surface opposite from the chip side surface. A first conductive bulk is formed embedded in the molding compound. The first conductive bulk has a first number of first chip-side bond pad surfaces and a second number of first solder ball-side surfaces exposed from the chip side surface and the ball-side surface, respectively. The width of the first conductive bulk is greater than the first width of the first chip-side bond pad surfaces and the second width of the first solder ball-side surfaces. 1. A circuit substrate for a chip bonding thereon , comprising:a molding compound having a chip-side surface and a solder ball-side surface opposite from the chip-side surface; anda first conductive bulk formed embedded in the molding compound, wherein the first conductive bulk has a first number of first chip-side bond pad surfaces exposed from the chip-side surface and a second number of first ball-side bond pad surfaces exposed from the solder ball-side bond pad surface, wherein a width of the first conductive bulk is greater than a first width of the first chip-side bond pad surfaces and a second width of the first ball-side bond pad surfaces in a cross-sectional view.2. The circuit substrate as claimed in claim 1 , wherein the first number is different from the second number claim 1 , the first number is a positive number and the second number is a positive number.3. The circuit substrate as claimed in claim 1 , wherein the first number is equal to the second number claim 1 , the first number is a positive number and the second number is a positive number.4. The circuit substrate as claimed in claim 1 , wherein the first conductive bulk comprises:a first segment; anda second segment connecting to the first segment through a first connecting portion, wherein the first ball-side bond pad surface is positioned ...

INTEGRATED CIRCUIT STRUCTURES WITH INTERPOSERS HAVING RECESSES

Disclosed herein are integrated circuit (IC) structures having interposers with recesses. For example, an IC structure may include: an interposer having a resist surface; a recess disposed in the resist surface, wherein a bottom of the recess is surface-finished; and a plurality of conductive contacts located at the resist surface. Other embodiments may be disclosed and/or claimed. 125-. (canceled)26. An integrated circuit (IC) structure , comprising:an interposer having a resist surface;a recess disposed in the resist surface, wherein a bottom of the recess is surface-finished; anda plurality of conductive contacts located at the resist surface.27. The IC structure of claim 26 , wherein the plurality of conductive contacts is a first plurality of conductive contacts claim 26 , and wherein the IC structure further comprises:an IC package having a first surface, a second surface opposite to the first surface, a second plurality of conductive contacts located at the second surface of the IC package, and a component coupled to the second surface of the IC package;wherein the second plurality of conductive contacts are electrically coupled to the first plurality of conductive contacts and the IC package is arranged so that the component extends into the recess.28. The IC structure of claim 27 , wherein the component is a capacitor having a capacitance greater than 0.5 microfarads.29. The IC structure of claim 27 , wherein the component has a height that is greater than 200 microns.30. The IC structure of claim 27 , wherein the IC package has a processing core located at the first surface of the IC package and the component is a decoupling capacitor for the processing core.31. The IC structure of claim 27 , wherein a distance between the second surface of the IC package and the resist surface is less than 250 microns.32. The IC structure of claim 27 , further comprising:a solder material in physical contact with one of the first plurality of conductive contacts and also ...

Display apparatus and method of manufacturing the same

A display apparatus includes a display panel including a lower base substrate and a connecting portion disposed on the lower base substrate, a flexible circuit board attached on a side surface of the display panel, and including a base film and a conductive pattern disposed on the base film, a conductive paste part disposed between the side surface of the display panel and the flexible circuit board, a first anisotropic conductive film (ACF) film disposed between the side surface of the display panel and the conductive paste part, and a second ACF film disposed between the conductive paste part and the flexible circuit board. The connecting portion is exposed at the side surface of the display panel, and the first ACF film directly makes contact with the connecting portion.

POST-GRIND DIE BACKSIDE POWER DELIVERY

Disclosed is a die. The die may include a material layer, a plurality of vias, and a plurality of metal channels. The material layer may have a top side and a backside. The top side may include a plurality of pad connections. The plurality of vias may extend through the material layer from the top side to the backside. The plurality of metal channels may be in contact with the backside. Each of the plurality of metal channels may be in electrical communication with at least one of the plurality of pad connections and at least one of the plurality of vias. 1. A die comprising:a material layer having a top side and a backside, the top side including a plurality of pad connections, the backside including a power connection;a plurality of vias extending through the material layer from the top side to the backside; anda plurality of metal channels in contact with the backside, each of the plurality of metal channels in electrical communication with at least one of the plurality of pad connections and at least one of the plurality of vias, at least one of the plurality of metal channels in electrical communication with the power connection, wherein a first metal channel of the plurality of metal channels is located adjacent a reference channel within the material layer.2. The die of claim 1 , wherein the material layer is comprised of a semiconductor material.3. The die of claim 1 , wherein the die is one of a plurality of dies located on a semiconductor wafer.4. The die of claim 1 , wherein the top side comprises integrated circuitry in electrical communication with the plurality of pad connections.5. (canceled)6. The die of claim 1 , wherein each of the plurality of metal channels are substantially wider than a width of each of a plurality of signal traces located on the top side of the material layer.7. The die of claim 1 , wherein each of the plurality of metal channels has a width at least one order of magnitude greater than a width of each of a plurality of signal ...

Dual-layer dielectric in memory device

Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.

Film for semiconductor package, semiconductor package using film and display device including the same

A semiconductor package may include a first output test pad and a second output test pad disposed on a first surface of an insulating film, and a semiconductor chip disposed between the first output test pad and the second output test pad on a second surface opposing to the first surface of the insulating film.

Dual solder methodologies for ultrahigh density first level interconnections

An apparatus, comprising an integrated circuit (IC) package having at least one solder bond pad, a die having at least one solder bond pad, wherein the die is bonded to the IC package by at least one solder joint between the at least one solder bond pad of the die, and the at least one solder bond pad of the IC package, and an underfill material between the IC package and the die, wherein the at least one solder joint is embedded in the underfill material, and wherein the at least one solder joint comprises a first metallurgy and a second metallurgy.

Package Having Substrate With Embedded Metal Trace Overlapped by Landing Pad

An embodiment package includes a conductive pillar mounted on an integrated circuit chip, the conductive pillar having a stepper shape, a metal trace partially embedded in a substrate, the metal trace having a bonding pad portion protruding from the substrate, and a solder feature electrically coupling the conductive pillar to the bonding pad portion of the metal trace. 1. A method of forming a semiconductor device , the method comprising:forming a conductive trace on a first substrate, the conductive trace having a bonding pad portion protruding from the first substrate and a recessed portion recessed from an outermost surface of the first substrate, the first substrate not extending over the recessed portion, sidewalls of the recessed portion having a different profile than sidewalls of the bonding pad portion; andbonding the bonding pad portion to a conductive pillar on a second substrate, the conductive pillar having a decreasing width as the conductive pillar extends away from the second substrate.2. The method of claim 1 , wherein the bonding pad portion has a width that decreases as the bonding pad portion extends away from the first substrate.3. The method of claim 1 , wherein the bonding pad portion has a width that increases as the bonding pad portion extends away from the first substrate.4. The method of claim 1 , wherein a height of the bonding pad portion above the outermost surface of the first substrate is greater than a height of the conductive pillar.5. The method of claim 1 , wherein the bonding pad portion utilizes a stepper shape when a formula b-a>0.36 hs−0.1 μm is satisfied claim 1 , where b is a bottom width of the bonding pad portion claim 1 , a is a top width of the bonding pad portion claim 1 , and hs is a height of the bonding pad portion.6. The method of claim 1 , wherein the bonding pad portion utilizes an inverted stepper shape when a formula a-b>0.36 hs−0.1 μm is satisfied claim 1 , where a is a top width of the bonding pad portion ...

3D Package With Through Substrate Vias

A package, comprising a substrate having electrical devices disposed at a first side of the substrate, vias extending from the first side of the substrate to a second side of the substrate opposite the first side and metallization layers disposed on the first side of the substrate. Contact pads are disposed over the first metallization layers and a protection layer is disposed over the contact pads. Post-passivation interconnects are disposed over the protection layer and extend to the contact pads through openings in the protection layer. Connectors are disposed on the PPIs and a molding compound extends over the PPIs and around the connectors.

DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME

A display apparatus includes a display panel including a lower base substrate and a connecting portion disposed on the lower base substrate, a flexible circuit board attached on a side surface of the display panel, and including a base film and a conductive pattern disposed on the base film, a conductive paste part disposed between the side surface of the display panel and the flexible circuit board, a first anisotropic conductive film (ACF) film disposed between the side surface of the display panel and the conductive paste part, and a second ACF film disposed between the conductive paste part and the flexible circuit board. The connecting portion is exposed at the side surface of the display panel, and the first ACF film directly makes contact with the connecting portion. 1. A display apparatus , comprising:a display panel comprising a lower base substrate and a connecting portion disposed on the lower base substrate;a flexible circuit board comprising a base film and a conductive pattern disposed on the base film, wherein the flexible circuit board is attached on a side surface of the display panel;a conductive paste part disposed between the side surface of the display panel and the flexible circuit board; andan anisotropic conductive film (ACF) film disposed between the conductive paste part and the flexible circuit board,wherein the conductive paste part makes contact with the connecting portion at the side surface of the display panel.2. The display apparatus of claim 1 , wherein the ACF film further comprises a plurality of conductive balls claim 1 , and each of the plurality of conductive balls comprises a polymer particle and metal coated on a surface of the polymer particle.3. The display apparatus of claim 2 , wherein the plurality of conductive balls are solder balls claim 2 , andthe solder balls are soldered to the connecting part by heat.4. A method of manufacturing a display apparatus claim 2 , the method comprising:providing a display panel ...

DUAL-LAYER DIELECTRIC IN MEMORY DEVICE

Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed. 1a memory array comprising a plurality of wordlines; andfill regions between respective pairs of adjacent wordlines of the plurality of wordlines, wherein one or more of the fill regions includes a first dielectric material and a second dielectric material disposed on the first dielectric material, wherein the first dielectric material comprises an organic spin-on dielectric material (CSOD), and wherein the second dielectric material comprises a second dielectric material that is different from the first dielectric material.. An apparatus comprising: This application is a continuation application of U.S. patent application Ser. No. 15/612,245, entitled “DUAL-LAYER DIELECTRIC IN MEMORY DEVICE”, filed Jun. 2, 2017, now U.S. Pat. No. 10,134,809, which is a divisional application of U.S. patent application Ser. No. 14/998,194, entitled “DUAL-LAYER DIELECTRIC IN MEMORY DEVICE”, filed Dec. 23, 2015, now U.S. Pat. No. 9,704,923, and claims priority to the Ser. Nos. 15/612,245 and 14/998,194 applications. The disclosures of Ser. Nos. 15/612,245 and 14/998,194 are hereby fully incorporated by reference.Embodiments of the present disclosure generally relate to the field of integrated circuits (IC), and more particularly, to fabrication techniques for ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a pad electrode formed over a semiconductor substrate, a conductor pillar formed on the pad electrode, a cap film formed on the conductor pillar and made of a nickel film, a terminal formed in a wiring board, a metal film formed on the terminal and made of a nickel film containing phosphorus, a solder layer interposed between the cap film and the metal film and containing tin as a main component, and an alloy layer interposed between the solder layer and the metal film and containing tin and copper. 1. A semiconductor device comprising:a pad electrode formed over a semiconductor substrate;a conductor pillar formed on the pad electrode;a cap film formed on the conductor pillar and made of a nickel film;a terminal formed in a wiring board;a first metal film formed on the terminal and made of a nickel film containing phosphorus;a solder layer interposed between the cap film and the first metal film and containing tin as a main component; anda first alloy layer interposed between the solder layer and the first metal film and containing tin and copper.2. The semiconductor device according to further comprising:a second metal film interposed between the cap film and the solder layer and made of a copper film.3. The semiconductor device according to further comprising:a second alloy layer interposed between the second metal film and the solder layer and containing tin and copper.4. The semiconductor device according to claim 2 ,wherein a width of the second metal film is smaller than a width of the cap film.5. The semiconductor device according to further comprising:a third metal film interposed between the first metal film and the first alloy layer and made of a copper film.6. The semiconductor device according to claim 1 ,wherein a film thickness of the conductor pillar is larger than a film thickness of the solder layer.7. A manufacturing method of a semiconductor device comprising the steps of:(a) preparing a semiconductor chip including ...

NICKEL-TIN MICROBUMP STRUCTURES AND METHOD OF MAKING SAME

Techniques and mechanisms for providing effective connectivity with surface level microbumps on an integrated circuit package substrate. In an embodiment, different metals are variously electroplated to form a microbump which extends through a surface-level dielectric of a substrate to a seed layer including copper. The microbump includes nickel and tin, wherein the nickel aids in mitigating an absorption of seed layer copper. In another embodiment, the microbump has a mass fraction of tin, or a mass fraction of nickel, that is different in various regions along a height of the microbump. 1. A method for forming microbumps on a substrate , the method comprising:patterning a dielectric layer, wherein a copper contact is exposed by an opening formed in the dielectric layer;performing a deposition of a seed layer on the copper contact, the seed layer comprising copper;electroplating nickel of a first microbump directly on the seed layer; andelectroplating tin of the first microbump directly on the nickel.2. The method of claim 1 , wherein performing the deposition of the seed layer includes performing an electroless plating of the seed layer directly on the copper contact.3. The method of claim 1 , wherein a bottom 10% of a volume of the first microbump has a first tin mass fraction claim 1 , wherein a top 10% of a volume of the first microbump has a second tin mass fraction and wherein the second tin mass fraction differs from the first tin mass fraction by at least 5% of the first tin mass fraction.4. The method of claim 3 , wherein the second tin mass fraction differs from the first tin mass fraction by at least 10% of the first tin mass fraction.5. The method of claim 1 , wherein a total volume of tin of the first microbump is equal to at least 75% of a total volume of nickel of the first microbump.6. The method of claim 1 , wherein a total tin mass fraction of the first microbump is in a range of 50% to 90%.7. The method of claim 1 , further comprising forming a ...

SEMICONDUCTOR DEVICE AND ELECTRONIC CIRCUIT DEVICE

A semiconductor device according to an embodiment includes a first semiconductor unit including a plurality of first semiconductor chips, an organic resin provided between the first semiconductor chips, a wiring layer provided above the first semiconductor chips to electrically connect the first semiconductor chips to each other, and a plurality of connecting terminals provided on an upper portion of the wiring layer and a second semiconductor unit fixed to a wiring layer side of the first semiconductor unit, the second semiconductor unit fixed to a region sandwiched between the connecting terminals, the second semiconductor unit having a second semiconductor chip, the second semiconductor unit electrically connected to the first semiconductor unit. 1. A semiconductor device comprising:a first semiconductor unit including a plurality of first semiconductor chips, an organic resin provided between the first semiconductor chips, a wiring layer provided above the first semiconductor chips to electrically connect the first semiconductor chips to each other, and a plurality of connecting terminals provided on an upper portion of the wiring layer; anda second semiconductor unit fixed to a wiring layer side of the first semiconductor unit, the second semiconductor unit fixed to a region sandwiched between the connecting terminals, the second semiconductor unit having a second semiconductor chip, the second semiconductor unit electrically connected to the first semiconductor unit.2. The device according to claim 1 , wherein the first semiconductor unit includes a plurality of passive elements.3. The device according to claim 1 , wherein an area of the second semiconductor chip is larger than an area of any of the plurality of first semiconductor chips.4. The device according to claim 1 , further comprising a third semiconductor unit fixed to an opposite side of the second semiconductor unit of the first semiconductor unit claim 1 , the third semiconductor unit having a ...

EMBEDDED MULTI-DIE INTERCONNECT BRIDGE

The present disclosure relates to devices and techniques for an interconnect bridge to communicatively couple two or more dies. In an example, the interconnect bridge can include a base element having a first material. A first layer, including a second material, can be attached to the base element. A second layer, including a third material, can be disposed on the first layer. A two-dimensional electron gas (2DEG) can be located between the first layer and the second layer. A first contact, adapted to electrically couple to the first die, can be disposed in a first side of the 2DEG. A second contact, adapted to electrically couple to the second die, can be disposed in a second side of the 2DEG. Accordingly, the first die can be electrically coupled to the second die through the 2DEG. 1. An interconnect bridge for communicatively coupling two or more dies of an electronic package , the interconnect bridge comprising:a base element including a first material, wherein the base element is attachable to a substrate configured to support a first die and a second die;a first layer attached to the base element, wherein the first layer includes a second material;a second layer disposed on the first layer, wherein the second layer includes a third material;a two-dimensional electron gas (2DEG) located between the first layer and the second layer;a first contact disposed in a first side of the 2DEG, the first contact adapted to electrically couple to the first die; anda second contact disposed in a second side of the 2DEG at a distance from the first contact, the second contact adapted to electrically couple to the second die, wherein the first contact is electrically coupled to the second contact through the 2DEG.2. The interconnect bridge of claim 1 , wherein the second material includes a first lattice parameter and the third material includes a second lattice parameter claim 1 , and the 2DEG is formed by a heterojunction between the first layer and the second layer based ...

Semiconductor device

A semiconductor device includes a semiconductor substrate having a principal surface which has a first side in a first direction and a second side in a second direction. A plurality of transistor arrays is formed in a region adjacent to the first side of the semiconductor substrate. A plurality of bumps include first and second bumps which are longer in the first direction. The distance between the first side and the first bump is shorter than the distance between the first side and the second bump. The plurality of transistor arrays include a first and a second transistor arrays. The first transistor array has a plurality of first unit transistors arranged along the first direction such that the first unit transistors overlap the first bump. The second transistor array has a plurality of second unit transistors arranged along the first direction such that the second unit transistors overlap the second bump.

OPOSSUM REDISTRIBUTION FRAME FOR CONFIGURABLE MEMORY DEVICES

The present disclosure relates to a semiconductor package that may include a package substrate with a first surface and an opposing second surface, a first device coupled to the first surface of the package substrate, a redistribution frame coupled to the second surface of the package substrate, a plurality of solder balls coupled to the second surface of the package substrate, a second device coupled to the redistribution frame, and a printed circuit board coupled to the plurality of solder balls on the second surface of substrate, wherein the redistribution frame coupled with the second device and the plurality of solder balls are positioned between the package substrate and the printed circuit board. 2. The semiconductor package of claim 1 , wherein the redistribution frame comprises a plurality of first frame vias for coupling to the second surface of the package substrate.3. The semiconductor package of claim 2 , wherein the redistribution frame further comprises a plurality of second frame vias for coupling to the second device.4. The semiconductor package of claim 3 , wherein the redistribution frame further comprises one or more redistribution layers extending over the plurality of first and second frame vias.5. The semiconductor package of claim 1 , wherein the redistribution frame further comprises an extended frame portion to form an extended redistribution frame.6. The semiconductor package of claim 5 , wherein the package substrate comprises a first footprint and the extended frame portion comprises a second footprint greater than the first footprint.7. The semiconductor package of claim 1 , wherein the package substrate comprises a plurality of first contact pads to connect to the plurality of first frame vias.8. The semiconductor package of claim 7 , wherein the package substrate further comprises a plurality of second contact pads claim 7 , wherein each second contact pad has a diameter or dimension larger than that of each first contact pad.9. The ...

DUAL-LAYER DIELECTRIC IN MEMORY DEVICE

Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF

A semiconductor device includes a board having a solder resist layer with first and second openings on a first surface, and a first electrode on the first surface, a portion thereof exposed in the first opening and electrically connected to the board. A second electrode is located on the first surface having a portion exposed in the second opening and electrically connected to the board. A portion of the second electrode is covered by the solder resist layer. A first solder bump is on the first electrode and covers a side surface. A second solder bump is on the second electrode. A semiconductor chip has a first region and a second region facing the first surface. A third electrode is in the first region and electrically connected to the first solder bump. A fourth electrode is in the second region and electrically connected to the second solder bump. 1. A semiconductor device , comprising:a board having a first surface;a solder resist layer on the first surface, the solder resist layer comprising a first opening and a second opening;a first electrode on the first surface and having a side surface exposed in the first opening, the first electrode electrically connected to the board;a second electrode, having an outer perimeter, on the first surface, wherein the second electrode electrically connected to the board and at least a portion of the outer perimeter of the second electrode covered by the solder resist layer;a first solder bump on the first electrode, the first solder bump covering the side surface of the first electrode;a second solder bump on the second electrode; anda semiconductor chip comprising a second surface facing the first surface, the second surface comprising a first region and a second region, wherein a third electrode in the first region of the semiconductor chip is electrically connected to the first solder bump, and a fourth electrode in the second region of the semiconductor chip is electrically connected to the second solder bump.2. The ...

SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device package includes a first substrate, a second substrate, an electrical contact and a support element. The first substrate has a first surface. The second substrate has a first surface facing the first surface of the first substrate. The electrical contact is disposed between the first substrate and the second substrate. The support element is disposed between the first substrate and the second substrate. The support element includes a thermosetting material. 1. A semiconductor device package , comprising:a first substrate having a first surface;a second substrate having a first surface facing the first surface of the first substrate;an electrical contact disposed between the first substrate and the second substrate; anda support element disposed between the first substrate and the second substrate, wherein the support element includes a thermosetting material.2. The semiconductor device package of claim 1 , wherein the support element includes a cured B-stage adhesive.3. The semiconductor device package of claim 1 , wherein a curing temperature of the support element is higher than a melting point of the electrical contact.4. The semiconductor device package of claim 1 , whereinthe first surface of the first substrate includes a conductive pad; andthe first surface of the second substrate includes a conductive pad; and the electrical contact is in contact with the conductive pads of the first substrate and the second substrate.5. The semiconductor device package of claim 1 , wherein the first surface of the first substrate includes a solder resist claim 1 , and the first surface of the second substrate includes a solder resist; wherein the support element is in contact with the solder resists of the first substrate and the second substrate.6. The semiconductor device package of claim 1 , further comprising:a first antenna pattern disposed on the first surface of the first substrate; anda second antenna pattern disposed on the first surface of ...

PLANAR TRANSISTORS WITH WRAP-AROUND GATES AND WRAP-AROUND SOURCE AND DRAIN CONTACTS

Disclosed herein are IC structures, packages, and devices that include planar III-N transistors with wrap-around gates and/or one or more wrap-around source/drain (S/D) contacts. An example IC structure includes a support structure (e.g., a substrate) and a planar III-N transistor. The transistor includes a channel stack of a III-N semiconductor material and a polarization material, provided over the support structure, a pair of S/D regions provided in the channel stack, and a gate stack of a gate dielectric material and a gate electrode material provided over a portion of the channel stack between the S/D regions, where the gate stack at least partially wraps around an upper portion of the channel stack. 1. An integrated circuit (IC) structure , comprising:a support structure; and a channel stack over the support structure, the channel stack including a III-N semiconductor material and a polarization material over the III-N semiconductor material,', 'first and second source/drain (S/D) regions in the channel stack, and', 'a gate stack over a portion of the channel stack between the first and the second S/D regions,, 'a III-N transistor, comprisingwherein the gate stack at least partially wraps around an upper portion of the channel stack.2. The IC structure according to claim 1 , wherein the gate stack wrapping around the upper portion of the channel stack includes the gate stack being over an upper face of the channel stack and extending to a depth between 2 and 100 nanometers along at least one sidewall of the channel stack.3. The IC structure according to claim 2 , wherein the gate stack includes a gate dielectric material wrapping around the upper portion of the channel stack claim 2 , and a gate electrode material wrapping around the gate dielectric material.4. The IC structure according to claim 3 , wherein a portion of the gate dielectric material is in contact with the III-N semiconductor material at the at least one sidewall of the channel stack.5. The IC ...

Display apparatus and method of manufacturing the same

A display apparatus includes a display panel including a lower base substrate and a connecting portion disposed on the lower base substrate, a flexible circuit board attached on a side surface of the display panel, and including a base film and a conductive pattern disposed on the base film, a conductive paste part disposed between the side surface of the display panel and the flexible circuit board, a first anisotropic conductive film (ACF) film disposed between the side surface of the display panel and the conductive paste part, and a second ACF film disposed between the conductive paste part and the flexible circuit board. The connecting portion is exposed at the side surface of the display panel, and the first ACF film directly makes contact with the connecting portion.

SEMICONDUCTOR PACKAGES

A package is disclosed. The package includes a carrier that comprises a first conductive layer on a first side and a second conductive layer on a second side opposite the first side. The first conductive layer comprises wire bonding pads. The package also includes a semiconductor die that is flip chip mounted on the first side of the carrier. 1. A package comprising:a carrier comprising a first conductive layer on a first side and a second conductive layer on a second side opposite the first side, wherein the first conductive layer comprises wire bonding pads;a semiconductor die flip chip mounted on the first side of the carrier.2. The package of claim 1 , wherein the carrier comprises vias from the first side to the second side.3. The package of claim 2 , wherein the vias receive electrical ground from the second conductive layer.4. The package of claim 1 , wherein the first conductive layer comprises traces electrically connecting the semiconductor die and the wire bonding pads.5. The package of claim 1 , wherein the semiconductor die is a high frequency radio frequency (RF) die and the first conductive layer carries RF signals.6. The package of claim 1 , wherein the semiconductor die is a silicon-on-insulator (SOI) die.7. The package of claim 1 , further comprising copper pillars between the semiconductor die and the carrier.8. The package of claim 1 , further comprising molding material disposed around the semiconductor die.9. The apparatus of claim 1 , wherein the carrier comprises a laminated substrate claim 1 , a ceramic substrate claim 1 , or a semiconductor substrate.10. An apparatus comprising:a printed circuit board (PCB) comprising a first conductive layer and a second conductive layer separated by dielectric, wherein the first conductive layer is on a first side of the PCB, and wherein the PCB includes a recess on the first side and extending through the first conductive layer and the dielectric to the second conductive layer;a carrier including a first ...

THROUGH-SUBSTRATE WAVEGUIDE

Embodiments may relate to a semiconductor package that includes a die and a package substrate. The package substrate may include one or more cavities that go through the package substrate from a first side of the package substrate that faces the die to a second side of the package substrate opposite the first side. The semiconductor package may further include a waveguide communicatively coupled with the die. The waveguide may extend through one of the one or more cavities such that the waveguide protrudes from the second side of the package substrate. Other embodiments may be described or claimed.

Electronic Assembly and Electronic System With Impedance Matched Interconnected Structures

Provided is an electronic assembly including (a) an interconnect carrier having an electrically insulating core and at least two electrically conducting layers formed at the electrically insulating core; (b) a first integrated circuit chip mounted at a first side of the interconnect carrier; (c) a second integrated circuit chip mounted at a second side of the interconnect carrier opposite to the first side; and (d) an interconnection structure electrically connecting the first integrated circuit chip with the second integrated circuit chip. The electric interconnection structure extends around the insulating core and includes at least one electric conductor path which is designed in such a manner that an impedance match between the first integrated circuit chip and the second integrated circuit chip is provided. Further, there is provided an electronic system comprising such an electronic assembly.

METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING GANG BONDING AND SEMICONDUCTOR DEVICE FABRICATED BY THE SAME

A semiconductor device including a first lead electrode and a second lead electrode; a semiconductor stack structure disposed on the member, the semiconductor stack structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active region interposed between the first and second conductive semiconductor layers; a first electrode electrically connected to the first conductive semiconductor layer; a second electrode electrically connected to the second conductive semiconductor layer; a plating layer configured to bond the semiconductor stack structure to the member; and a first wavelength converter that covers at least side surfaces of the semiconductor stack structure. 1a member comprising a first lead electrode and a second lead electrode;a semiconductor stack structure disposed on the member, the semiconductor stack structure comprising a first conductive semiconductor layer, a second conductive semiconductor layer, and an active region interposed between the first and second conductive semiconductor layers;a first electrode electrically connected to the first conductive semiconductor layer;a second electrode electrically connected to the second conductive semiconductor layer;a plating layer configured to bond the semiconductor stack structure to the member;spacer electrodes respectively disposed on the first and second lead electrodes; anda first wavelength converter that covers at least side surfaces of the semiconductor stack structure,wherein the first electrode comprises a first electrode pad and a first additional electrode disposed on the first electrode pad,wherein the second electrode comprises a second electrode pad and a second additional electrode disposed on the second electrode pad,wherein the plating layer comprises a first plating layer configured to bond the first additional electrode to the spacer electrode on the first lead electrode, and a second plating layer configured to bond the second ...

POST-GRIND DIE BACKSIDE POWER DELIVERY

Disclosed is a die. The die may include a material layer, a plurality of vias, and a plurality of metal channels. The material layer may have a top side and a backside. The top side may include a plurality of pad connections. The plurality of vias may extend through the material layer from the top side to the backside. The plurality of metal channels may be in contact with the backside. Each of the plurality of metal channels may be in electrical communication with at least one of the plurality of pad connections and at least one of the plurality of vias. 1. A microelectronics package comprising:a package substrate; and a material layer having a top side and a backside, the top side including a plurality of pad connections, the backside including a power connection;', 'a plurality of vias extending through the material layer from the top side to the backside; and', 'a plurality of metal channels in contact with the backside, each of the plurality of metal channels in electrical communication with at least one of the plurality of pad connections and at least one of the plurality of vias, at least one of the plurality of metal channels in electrical communication with the power connection,, 'a die connected to the package substrate, the die comprisingwherein a first metal channel of the plurality of metal channels is located adjacent a reference channel within the material layer.2. The microelectronics package of claim 1 , wherein the material layer comprises a semiconductor material.3. The microelectronics package of claim 1 , wherein the die is one of a plurality of dies located on a semiconductor wafer.4. The microelectronics package of claim 1 , wherein the top side comprises integrated circuitry in electrical communication with the plurality of pad connections.5. The microelectronics package of claim 1 , wherein at least one of the plurality of metal channels is a reference plane.6. The microelectronics package of claim 1 , wherein each of the plurality of metal ...

Protrusion Bump Pads for Bond-on-Trace Processing

An embodiment apparatus includes a dielectric layer, a conductive trace in the dielectric layer, and a bump pad. The conductive trace includes a first portion having an exposed top surface, wherein the exposed top surface is recessed from a top surface of the dielectric layer. Furthermore, the bump pad is disposed over and is electrically connected to a second portion of the conductive trace. 1. A device comprising:a substrate;an insulating layer on the substrate;a conductive line in the insulating layer; anda conductive pad in the insulating layer and directly over a first region of the conductive line, wherein the conductive pad has a different material composition than the conductive line, wherein a top surface of the conductive pad is not higher than a top surface of the insulating layer, wherein no portions of the insulating layer and no portions of the conductive pad extend directly over a second region of the conductive line.2. The device of claim 1 , wherein the conductive pad comprises nickel or tin claim 1 , and wherein the conductive line comprises copper.3. The device of claim 1 , wherein the conductive pad is connected to a contact pad through the conductive line claim 1 , wherein the conductive pad is disposed in the insulating layer claim 1 , and wherein the device further comprises a conductive pillar extending from the contact pad through the insulating layer.4. The device of claim 3 , wherein the contact pad and the conductive line have a same material composition.5. The device of claim 3 , wherein a top surface of the contact pad is lower than a top surface of the insulating layer.6. The device of further comprising:an integrated circuit chip; anda solder region physically coupling the integrated circuit chip to the conductive pad.7. The device of claim 1 , wherein a top surface of the conductive pad is substantially level with the top surface of the insulating layer.8. The device of claim 1 , wherein a top surface of the second region of the ...

HEAT DISSIPATION DEVICE HAVING A THERMALLY CONDUCTIVE STRUCTURE AND A THERMAL ISOLATION STRUCTURE IN THE THERMALLY CONDUCTIVE STRUCTURE

A heat dissipation device may be formed as a thermally conductive structure having at least one thermal isolation structure extending at least partially through the thermally conductive structure. The heat dissipation device may be thermally connected to a plurality of integrated circuit devices, such that the at least one thermal isolation structure is positioned between at least two integrated circuit devices. The heat dissipation device allows for heat transfer away from each of the plurality of integrated circuit devices, such as in a z-direction within the thermally conductive structure, while substantially preventing heat transfer in either the x-direction and/or the y-direction within the thermally isolation structure, such that thermal cross-talk between integrated circuit devices is reduced. 1. A heat dissipation device , comprising:a thermally conductive structure having a first surface; andat least one thermal isolation structure extending at least partially through the thermally conductive structure from the first surface thereof.2. The heat dissipation device of claim 1 , wherein the at least one thermal isolation structure comprises at least one trench extending at least partially through the thermally conductive structure.3. The heat dissipation device of claim 2 , further comprising a thermally non-conductive material in the at least one trench.4. The heat dissipation device of claim 3 , wherein the thermally non-conductive material is selected from the group consisting of epoxies claim 3 , ceramics claim 3 , and composites of polymers and ceramics.5. An integrated circuit structure claim 3 , comprising:a substrate;a first integrated circuit device having a first surface and an opposing second surface, wherein the first surface of the first integrated circuit device is electrically attached to the substrate;a second integrated circuit device having a first surface and an opposing second surface, wherein the first surface of the second integrated ...

METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING CONDUCTIVE ADHESIVE AND SEMICONDUCTOR DEVICE FABRICATED BY THE SAME

A semiconductor device including a first lead electrode and a second lead electrode on a lead frame; a semiconductor stack structure disposed on the lead frame, the semiconductor stack structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active region interposed between the first and second conductive semiconductor layers; a first electrode electrically connected to the first conductive semiconductor layer; a second electrode electrically connected to the second conductive semiconductor layer; a conductive adhesive configured to bond the semiconductor stack structure to the lead frame; and a first wavelength converter that covers at least side surfaces of the semiconductor stack structure. 1. A semiconductor device , comprising:a lead frame, the lead frame comprising a housing forming a recess dimensioned to accommodate a light emitting diode (LED) and a first lead electrode and a second lead electrode disposed in the recess;the LED comprising a semiconductor stack structure disposed on the lead frame, the semiconductor stack structure comprising a first conductive semiconductor layer, a second conductive semiconductor layer, and an active region interposed between the first and second conductive semiconductor layers;a first electrode electrically connected to the first conductive semiconductor layer;a second electrode electrically connected to the second conductive semiconductor layer;a conductive adhesive configured to bond the semiconductor stack structure to the lead frame; anda first wavelength converter that covers at least side surfaces of the semiconductor stack structure,wherein the conductive adhesive comprises a first conductive adhesive configured to bond the first electrode to the first lead electrode, and a second conductive adhesive configured to bond the second electrode to second lead electrode, andwherein the first wavelength converter extends to a space between the semiconductor stack ...

SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor package device includes: (1) a substrate having a top surface; (2) a passive component disposed on the substrate and having a top surface; (3) an active component disposed on the substrate and having a top surface; and (4) a package body disposed on the substrate, the package body including a first portion covering the active component and the passive component, and a second portion covering the passive component, wherein a top surface of the second portion of the package body is higher than a top surface of the first portion of the package body, and the first portion and the second portion of the package body include different materials. 1. A semiconductor package device comprising:a substrate having a top surface;a passive component disposed on the substrate and having a top surface;an active component disposed on the substrate and having a top surface; anda package body disposed on the substrate, the package body comprising a first portion covering the active component and the passive component, and a second portion covering the passive component, wherein a top surface of the second portion of the package body is higher than a top surface of the first portion of the package body,wherein the first portion and the second portion of the package body comprise different materials.2. The semiconductor package device according to claim 1 , wherein the top surface of the first portion of the package body is aligned with a backside surface of the active component.3. The semiconductor package device according to claim 1 , wherein the top surface of the first portion of the package body is aligned with a backside surface of the passive component.4. The semiconductor package device according to claim 1 , wherein the second portion of the package body comprises a cured photosensitive material.5. The semiconductor package device according to claim 1 , wherein an area of the second portion of the package body is larger than an area of the passive component.6. ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device including a semiconductor chip and a heat dissipation unit (heat sink) is configured as follows. The heat dissipation unit (heat sink) includes a resin tape, and a fin constituted of a graphite sheet and protruding from the resin tape. The fin, including graphene, is disposed on the semiconductor chip such that the graphene is disposed in a direction crossing a surface of the semiconductor chip. The heat dissipation unit is a rolled body in which the graphite sheet and the resin tape are layered and rolled. Thus, by use of the graphene as a constituent material of the fin, thermal conductivity is improved, whereby a heat dissipation characteristic is improved. Furthermore, since the fin is protruded from the resin tape, an exposed area of the fin is increased, and accordingly, the heat dissipation characteristic can be improved. 1. A semiconductor device comprising:a semiconductor chip; anda heat dissipation unit on the semiconductor chip,wherein the heat dissipation unit has a resin and a fin protruding from the resin,the fin has graphene, andthe fin is disposed on the semiconductor chip such that the graphene is disposed in a direction crossing a surface of the semiconductor chip.2. The semiconductor device according to claim 1 ,wherein the heat dissipation unit is a rolled body in which a graphite sheet and a resin tape are layered and rolled.3. A semiconductor device comprising:a semiconductor chip;a sealing resin on the semiconductor chip; anda heat dissipation unit embedded in the sealing resin,wherein the heat dissipation unit has a resin and a fin protruding from the resin,the fin has graphene, andthe fin is disposed on the semiconductor chip such that the graphene is disposed in a direction crossing a surface of the semiconductor chip.4. The semiconductor device according to claim 3 ,wherein the heat dissipation unit is a rolled body in which the graphite sheet and the resin tape are layered and rolled.5. A method of manufacturing a ...

Solder balls and semiconductor device employing the same

A solder ball and a semiconductor device using the same are provided. In a Sn-based solder ball in which a first plating layer and a second plating layer are sequentially formed on a core ball, the second plating layer includes a Sn—Ag—Cu alloy, and Ag 3 Sn intermetallic compound (IMC) nanoparticles or Ag—Sn compound nanoparticles exist in the second plating layer. The solder balls have high sphericity and stand-off characteristics and connection reliability so that a semiconductor device having a high degree of integration may be implemented.

Display Device and Method of Manufacturing the Same

Disclosed is a display device and a method of manufacturing the same, wherein an end portion of a pad provided on a first substrate is spaced apart and separated from an upper surface of the first substrate, and a connection electrode electrically connected with the pad is in contact with a lateral surface of the pad and a lower surface of the pad. 1. A display device comprising:first and second substrates confronting each other;a pad on the first substrate; anda connection electrode electrically connected with the pad,wherein an end portion of the pad is spaced apart and separated from an upper surface of the first substrate, and the connection electrode is in contact with a lateral surface of the pad and a lower surface of the pad.2. The display device according to claim 1 , wherein an end portion of the first substrate substantially corresponds to an end portion of the second substrate at a contact portion between the pad and the connection electrode.3. The display device according to claim 1 , further comprising a flexible circuit film that is electrically connected with the connection electrode and is attached to a lateral surface of the first substrate and a lateral surface of the second substrate claim 1 , wherein the connection electrode is in contact with the lateral surface of the first substrate and the lateral surface of the second substrate claim 1 , and.4. The display device according to claim 1 , further comprising a light-shielding layer on the second substrate claim 1 , and an overcoat layer on the light-shielding layer claim 1 , wherein the overcoat layer is disposed between the light-shielding layer and the connection electrode so as to insulate the light-shielding layer from the connection electrode.5. The display device according to claim 1 , wherein the end portion of the pad is provided in a bent structure claim 1 , and further comprising a stopper on the second substrate for controlling a bending degree of the end portion of the pad.6. The ...

PACKAGED SEMICONDUCTOR DEVICES FOR HIGH VOLTAGE WITH DIE EDGE PROTECTION

In a described example a device includes: a first corner formed between a circuit side surface of a semiconductor die and a first sidewall formed with a first depth extending along a side of the semiconductor die from the circuit side surface; a ledge having a planar surface formed parallel to the circuit side surface of the semiconductor die formed at the first depth from the circuit side surface at the first corner, and being perpendicular to the first sidewall; a second corner formed by an intersection of the planar surface of the ledge and a scribe lane sidewall of the semiconductor die, forming a second sidewall perpendicular to the circuit side surface; and portions of the circuit side surface of the semiconductor die, the first corner, the first sidewall, and the planar surface of the ledge covered by a passivation layer. 1. A device , comprising:a first corner formed between a circuit side surface of a semiconductor die and a first sidewall formed with a first depth extending along a side of the semiconductor die from the circuit side surface;a ledge having a planar surface formed parallel to the circuit side surface of the semiconductor die formed at the first depth from the circuit side surface at the first corner, and being perpendicular to the first sidewall;a second corner formed by an intersection of the planar surface of the ledge and a scribe lane sidewall of the semiconductor die, forming a second sidewall perpendicular to the circuit side surface; andportions of the circuit side surface of the semiconductor die, the first corner, the first sidewall, and the planar surface of the ledge covered by a passivation layer.2. The device of claim 1 , wherein a thickness of the passivation layer is at least 10 μm.3. The device of claim 1 , wherein the passivation layer is a material that is one selected from a group consisting essentially of: silicon dioxide claim 1 , silicon nitride claim 1 , silicon oxynitride claim 1 , polyimide claim 1 , and combinations ...

SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor package device includes a substrate, an electronic component, and a thermal conductive layer. The electronic component is disposed on the substrate and includes a first surface facing away from the substrate. The thermal conductive layer is disposed above the first surface of the electronic component. The thermal conductive layer includes a plurality of portions spaced apart from each other. 1. A semiconductor package device , comprising:a substrate;an electronic component disposed on the substrate, the electronic component comprising a first surface facing away from the substrate; anda thermal conductive layer disposed above the first surface of the electronic component,wherein the thermal conductive layer comprises a plurality of portions spaced apart from each other.2. The semiconductor package device of claim 1 , wherein the thermal conductive layer contacts the first surface of the electronic component.3. The semiconductor package device of claim 2 , wherein the first surface of the electronic component is a passive surface.4. The semiconductor package device of claim 1 , wherein the thermal conductive layer comprises an epoxy and a thermal conductive filler.5. The semiconductor package device of claim 1 , wherein the portions of the thermal conductive layer are insulated from each other.6. The semiconductor package device of claim 1 , further comprising an encapsulant covering the substrate and the electronic component.7. The semiconductor package device of claim 6 , wherein the thermal conductive layer is disposed on the encapsulant and spaced apart from the first surface of the electronic component.8. The semiconductor package device of claim 6 , wherein the thermal conductive layer is encapsulated by the encapsulant claim 6 , and a surface of at least one of the portions of the thermal conductive layer is exposed from the encapsulant.9. An electrical device claim 6 , comprising:a main board; a substrate comprising a first surface and a ...

Semiconductor chip, method of fabricating the semiconductor chip, and semiconductor package and display apparatus comprising the semiconductor chip

본 발명의 기술적 사상은 별도의 포토리소그라피 장비에 대한 투자없이 최적화된 구조의 반도체 칩과 그 제조방법, 및 그 반도체 칩을 포함한 반도체 패키지와 디스플레이 장치를 제공한다. 그 반도체 칩은 제1 방향으로 길쭉한 직사각형의 중심 부분에 배치되고, 상기 제1 방향을 따라 기 설정된 간격을 가지고 배치된 다수의 구동회로 셀들을 구비한 회로 영역; 상기 회로 영역의 외곽으로 배치된 다수의 전극 패드들; 및 상기 직사각형의 네 변 중 적어도 한 변에 배치된 공정용 패턴;을 포함한다. The technical idea of the present invention is to provide a semiconductor chip having an optimized structure, a method for manufacturing the same, and a semiconductor package and a display device including the semiconductor chip without investment in separate photolithography equipment. The semiconductor chip includes: a circuit region having a plurality of driving circuit cells disposed at a center portion of a rectangle elongated in a first direction and having a predetermined interval along the first direction; a plurality of electrode pads disposed outside the circuit area; and a process pattern disposed on at least one of the four sides of the rectangle.

Method of fabricating semiconductor device using gang bonding and semiconductor device fabricated by the same

집단 본딩을 이용한 반도체 디바이스 제조 방법 및 반도체 디바이스가 개시된다. 본 발명의 일 태양에 따른 반도체 디바이스 제조 방법은, 정렬된 복수의 반도체 적층 구조체를 갖는 지지기판을 준비하는 것을 포함한다. 각 반도체 적층 구조체는 제1 도전형 반도체층, 제2 도전형 반도체층, 및 제1 도전형 반도체층과 제2 도전형 반도체층 사이에 개재된 활성 영역을 포함한다. 한편, 복수의 반도체 적층 구조체에 대응하도록 정렬된 제1 리드 전극들 및 제2 리드 전극들을 갖는 멤버가 준비된다. 그 후, 지지기판 상에서 상기 복수의 반도체 적층 구조체를 유지하면서, 복수의 반도체 적층 구조체가 멤버에 본딩된다. 복수의 반도체 적층 구조체가 본딩된 후, 멤버가 분할된다. 이에 따라, 칩 본딩 공정을 단순화할 수 있으며 작업시간을 크게 줄일 수 있다. Disclosed are a semiconductor device manufacturing method and a semiconductor device using collective bonding. A semiconductor device manufacturing method according to one aspect of the present invention includes preparing a support substrate having a plurality of aligned semiconductor laminate structures. Each semiconductor stacked structure includes a first conductive semiconductor layer, a second conductive semiconductor layer, and an active region interposed between the first conductive semiconductor layer and the second conductive semiconductor layer. Meanwhile, a member having first lead electrodes and second lead electrodes aligned to correspond to the plurality of semiconductor stacked structures is prepared. Thereafter, the plurality of semiconductor laminates are bonded to the members while maintaining the plurality of semiconductor laminates on the support substrate. After the plurality of semiconductor laminates are bonded, the members are divided. Accordingly, the chip bonding process can be simplified and the working time can be greatly reduced.

Integrated circuit structure including an interposer having a recess

본 명세서에는 리세스를 갖는 인터포저를 포함하는 집적 회로(IC) 구조물이 개시되어있다. 예를 들어, IC 구조물은 레지스트 표면, 레지스트 표면에 배치되는 리세스 - 리세스의 저부가 표면 처리됨 -, 및 레지스트 표면에 위치하는 복수의 전도성 콘택트를 갖는 인터포저를 포함한다. 다른 실시예가 개시 및/또는 청구될 수 있다. Disclosed herein is an integrated circuit (IC) structure that includes an interposer having a recess. For example, an IC structure includes an interposer having a resist surface, a recess disposed in the resist surface, the bottom of the recess having a surface treatment, and a plurality of conductive contacts disposed in the resist surface. Other embodiments may be disclosed and/or claimed.

Semiconductor device and manufacturing method thereof

A semiconductor device comprising a semiconductor chip substrate, an integrated circuit formed on a surface of the semiconductor chip substrate, and metal electrodes extending from the integrated circuit to at least one of the side surfaces of the semiconductor chip substrate. Occupation area on a wiring circuit board can be reduced. Damaged chips can be exchanged easily. When it is set vertically, heat radiation efficiency can be improved.

Film for package substrate, semiconductor package using the same and display device inclduing the semiconductor package

본 발명의 실시예에 따른 반도체 패키지는 칩 영역, 상기 칩 영역의 일측에 배치되는 제 1 테스트 영역 및 상기 칩 영역의 타측에 배치되는 제 2 테스트 영역을 포함하는 절연 필름, 상기 제 1 테스트 영역 내에서, 상기 절연 필름의 일면 상에 배치되는 제 1 출력 테스트 패드, 및 상기 제 2 테스트 영역 내에서, 상기 절연 필름의 상기 일면 상에 배치되는 제 2 출력 테스트 패드를 포함할 수 있다. A semiconductor package according to an embodiment of the present invention includes an insulating film including a chip region, a first test region disposed on one side of the chip region, and a second test region disposed on the other side of the chip region, A first output test pad disposed on one side of the insulating film and a second output test pad disposed on the one side of the insulating film in the second test area.

Display device and method of manufacturing the same

Disclosed is a display device and a method of manufacturing the same, wherein an end portion of a pad provided on a first substrate is spaced apart and separated from an upper surface of the first substrate, and a connection electrode electrically connected with the pad is in contact with a lateral surface of the pad and a lower surface of the pad.

Multi-chip package structure having high density chip interconnect bridge with embedded power distribution network

A multi-chip package structure includes a package substrate, an interconnect bridge device, first and second integrated circuit chips, and a connection structure. The first integrated circuit chip is flip-chip attached to at least the interconnect bridge device. The second integrated circuit chip is flip-chip attached to the interconnect bridge device and to the package substrate. The interconnect bridge device includes (i) wiring that is configured to provide chip-to-chip connections between the first and second integrated circuit chips and (ii) an embedded power distribution network that is configured to distribute at least one of a positive power supply voltage and a negative power supply voltage to at least one of the first and second integrated circuit chips attached to the interconnect bridge device. The connection structure (e.g., wire bond, injection molded solder, etc.) connects the embedded power distribution network to a power supply voltage contact of the package substrate.

Semiconductor device having first and second terminals

A semiconductor device includes a first substrate and a second substrate that is stacked on a first surface of the first substrate in a stacking direction and includes a second surface facing the first surface. A plurality of first terminals is provided on the first surface of the first substrate. A plurality of second terminals is provided on the second surface of the second substrate. A plurality of metallic portions is respectively provided between the plurality of first terminals and the plurality of second terminals. In a cross-section substantially perpendicular to the stacking direction, at least one of (i) each of the plurality of first terminals or (ii) each of the plurality of second terminals (a) includes a recessed portion in a first direction toward an adjacent first terminal or second terminal or (b) includes a projecting portion in a second direction intersecting with the first direction.

Dual-layer dielectric in memory device

Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.

Semiconductor Package Including a Wire Having a Zigzag Shape

상기 과제를 해결하기 위한 본 개시의 일 실시예에 따른 반도체 패키지는 패키지 기판 상에 실장된 칩 스택, 상기 패키지 기판 상에 배치된 제1 와이어, 및 상기 칩 스택 및 상기 제1 와이어를 감싸는 몰딩층을 포함할 수 있다. 상기 제1 와이어는 상기 패키지 기판의 상면으로부터 위 쪽으로 지그재그 모양을 가질 수 있다.

DOUBLE LAYER DIELECTRIC NON-VOLATILE MEMORY DEVICE AND SYSTEM

DIELÉTRICO DE DUPLA CAMADA EM DISPOSITIVO DE MEMÓRIA. As modalidades da presente divulgação descrevem técnicas e configurações para um dispositivo de memória compreendendo um arranjo de memória possuindo uma pluralidade de linhas de palavra dispostas numa região de memória de uma matriz. As regiões de enchimento podem ser dispostas entre pares respectivos de linhas de palavra adjacentes da pluralidade de linhas de palavra. As regiões de enchimento podem incluir uma primeira camada dielétrica e uma segunda camada dielétrica disposta sobre a primeira camada dielétrica. A primeira camada dielétrica pode compreender material dielétrico spin-on orgânico (por exemplo, à base de carbono) (CSOD). A segunda camada dielétrica pode compreender um material dielétrico diferente do da primeira camada dielétrica, tal como, por exemplo, material dielétrico inorgânico. Outras modalidades podem ser descritas e/ou reivindicadas. DOUBLE LAYER DIELECTRIC IN MEMORY DEVICE. Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of word lines arranged in a memory region of an array. The padding regions may be arranged between respective pairs of adjacent word lines of the plurality of word lines. The filling regions may include a first dielectric layer and a second dielectric layer disposed over the first dielectric layer. The first dielectric layer may comprise organic (e.g. carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a dielectric material different from that of the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.

3D package with through substrate vias

A package, comprising a substrate having electrical devices disposed at a first side of the substrate, vias extending from the first side of the substrate to a second side of the substrate opposite the first side and metallization layers disposed on the first side of the substrate. Contact pads are disposed over the first metallization layers and a protection layer is disposed over the contact pads. Post-passivation interconnects are disposed over the protection layer and extend to the contact pads through openings in the protection layer. Connectors are disposed on the PPIs and a molding compound extends over the PPIs and around the connectors.

Test structures for through silicon vias (TSVs) of three dimensional integrated circuit (3DIC)

A plurality of through silicon vias (TSVs) on a substrate or in a 3 dimensional integrated circuit (3DIC) are chained together. TSVs are chained together to increase the electrical signal. A plurality of test pads are used to enable the testing of the TVSs. One of the test pads is grounded. The remaining test pads are either electrically connected to TSVs in the chain or grounded.

Method for embedding magnetic structures in substrates

Ausführungsbeispiele umfassen Bilden einer ersten Verbindungsstruktur auf einem dielektrischen Material eines Substrats, selektives Bilden eines magnetischen Materials auf einer Oberfläche der ersten Verbindungsstruktur, Bilden einer Öffnung in dem magnetischen Material und Bilden einer zweiten Verbindungsstruktur in der Öffnung. Aufbauschichten werden dann auf dem magnetischen Material gebildet.

Semiconductor package and method of fabricating the same and semiconductor module and method of fabricating the same

Provided are a semiconductor package having connection terminals whose side surfaces are exposed and a semiconductor module including such a semiconductor package. Also provided are methods of fabricating the semiconductor package and semiconductor module. According to an embodiment of the present invention, a semiconductor package includes a semiconductor chip including a semiconductor wafer having first and second opposite surfaces and a plurality of conductive pads arranged in a row on the first surface along the edges of the semiconductor wafer such that a side surface of each conductive pad is exposed. An insulating layer is formed on the first surface of the semiconductor wafer and includes openings for exposing parts of the conductive pads. A plurality of connection terminals are respectively arranged on the conductive pads exposed through the openings and a reinforcing member is arranged on the insulating layer to cover a portion of each connection terminal.

Film-type semiconductor package and its manufacture method

本发明公开了膜型半导体封装以及制造膜型半导体封装的方法。该膜型半导体封装包括布置在膜基板上的金属引线部分、包括焊垫的半导体芯片以及将金属引线部分连接到半导体芯片的焊垫的凸块。凸块包括：金属柱，布置在焊垫上并且包括第一金属；以及焊接部分，布置在金属柱的整个表面上，接合到金属引线部分并且包括第一金属和不同于第一金属的第二金属。

Wafer level package

A wafer level package structure. The method of forming the wafer level package structure includes covering a silicon chip having a plurality of integrated circuit devices thereon with an insulation layer. Next, a plurality of bonding pads is formed on the periphery of the silicon chip above the insulation layer. The bonding pads are formed such that each bonding pad is electrically connected to the terminal of an integrated circuit device. Thereafter, a passivation layer is deposited over the insulation layer and the bonding pads, and then openings that expose a portion of the bonding pad are formed. Subsequently, a metallic layer is formed on the sidewalls and the exposed bonding pad area. The metallic layer also extends over the passivation layer in the neighborhood of the opening and towards the edge of the wafer chip. Next, a layer of packaging material is deposited over the passivation layer. Finally, a metallic bump is formed over the exposed metallic layer lying above each opening.

Electronic circuit package

Semiconductor device

【課題】 高調波の制御性が向上する電力増幅回路を搭載した半導体装置を提供すること。 【解決手段】 半導体装置は、互いに交差する第１方向及び第２方向により規定される平面に平行な主面を有するチップと、入力信号を増幅して複数の出力端子から増幅信号を出力する電力増幅器と、増幅信号の高調波を減衰させる第１及び第２フィルタ回路と、を備え、第１フィルタ回路は、複数の出力端子と接地との間に接続された第１キャパシタを含み、第２フィルタ回路は、複数の出力端子と接地との間に接続された第２キャパシタを含み、チップの主面上において、複数の出力端子は、第１方向に沿って並んで配置され、第１及び第２キャパシタは、それぞれ、複数の出力端子の第１方向側及び第１方向の反対側に配置される。 【選択図】図２

Protrusion bump pads for bond-on-trace processing

An embodiment apparatus includes a dielectric layer, a conductive trace in the dielectric layer, and a bump pad. The conductive trace includes a first portion having an exposed top surface, wherein the exposed top surface is recessed from a top surface of the dielectric layer. Furthermore, the bump pad is disposed over and is electrically connected to a second portion of the conductive trace.

Display device and method of manufacturing the same

提供一种显示设备及其制造方法。所述显示设备包括：显示面板，包括下基体基底和设置在下基体基底上的连接部；柔性电路板，附着在显示面板的侧表面上，并包括基体膜和设置在基体膜上的导电图案；导电部，设置在显示面板的侧表面与柔性电路板之间，导电部通过使用导电膏形成；第一ACF膜(各向异性导电膜)，设置在显示面板的侧表面与导电部之间；以及第二ACF膜，设置在导电部与柔性电路板之间。第一ACF膜在显示面板的侧表面处与连接部接触。

Semiconductor device

本发明的课题在于提供一种搭载了高次谐波的控制性提高的功率放大电路的半导体装置。为此，半导体装置具备：芯片，具有与由相互交叉的第一方向以及第二方向规定的平面平行的主面；功率放大器，将输入信号放大并从多个输出端子输出放大信号；和第一滤波器电路及第二滤波器电路，使放大信号的高次谐波衰减，第一滤波器电路包含连接在多个输出端子与接地之间的第一电容器，第二滤波器电路包含连接在多个输出端子与接地之间的第二电容器，在芯片的主面上，多个输出端子沿着第一方向排列配置，第一电容器以及第二电容器分别配置在多个输出端子的第一方向侧以及第一方向的相反侧。

Metal pillar in a film-type seconductor package

A film-type semiconductor package includes a metal lead portion arranged on a film substrate, a semiconductor chip including a pad, and a bump connecting the metal lead portion to the pad of the semiconductor chip. The bump includes a metal pillar arranged on the pad and including a first metal and a soldering portion arranged on an entire surface of the metal pillar, bonded to the metal lead portion, and including the first metal and a second metal that is different from the first metal.

Test structures for through silicon vias (TSVs) of three dimensional integrated circuit (3DIC)

将基板上的或者3维集成电路(3DIC)中的多个穿透硅通孔(TSV)链接在一起。将TSV链接在一起，从而增大了电信号。多个测试焊盘能够用于测试TSV。一个测试焊盘接地。剩下的测试焊盘电连接到链中的TSV，或者接地。

Manufacturing method of semiconductor structure having dielectric layer edge covering circuit carrier

A manufacturing method of a semiconductor structure includes at least the following steps. An encapsulated semiconductor die is disposed on a first surface of a circuit carrier to be in electrical contact with the circuit carrier. A second surface of the circuit carrier and an edge of the circuit carrier is protected with a patterned dielectric layer, where the second surface of the circuit carrier is opposite to the first surface, and the edge of the circuit carrier is connected to the second surface. A conductive terminal is formed to penetrate through the patterned dielectric layer to be in electrical contact with the circuit carrier.